1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #include "qlcnic_sriov.h" 9 #include "qlcnic.h" 10 #include "qlcnic_hw.h" 11 12 /* Reset template definitions */ 13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000 14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000 15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101 16 17 #define QLC_83XX_OPCODE_NOP 0x0000 18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001 19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002 20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004 21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008 22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010 23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020 24 #define QLC_83XX_OPCODE_SEQ_END 0x0040 25 #define QLC_83XX_OPCODE_TMPL_END 0x0080 26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100 27 28 /* EPORT control registers */ 29 #define QLC_83XX_RESET_CONTROL 0x28084E50 30 #define QLC_83XX_RESET_REG 0x28084E60 31 #define QLC_83XX_RESET_PORT0 0x28084E70 32 #define QLC_83XX_RESET_PORT1 0x28084E80 33 #define QLC_83XX_RESET_PORT2 0x28084E90 34 #define QLC_83XX_RESET_PORT3 0x28084EA0 35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0 36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0 37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0 38 39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter); 40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev); 41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter); 42 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev); 43 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *); 44 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *); 45 46 /* Template header */ 47 struct qlc_83xx_reset_hdr { 48 #if defined(__LITTLE_ENDIAN) 49 u16 version; 50 u16 signature; 51 u16 size; 52 u16 entries; 53 u16 hdr_size; 54 u16 checksum; 55 u16 init_offset; 56 u16 start_offset; 57 #elif defined(__BIG_ENDIAN) 58 u16 signature; 59 u16 version; 60 u16 entries; 61 u16 size; 62 u16 checksum; 63 u16 hdr_size; 64 u16 start_offset; 65 u16 init_offset; 66 #endif 67 } __packed; 68 69 /* Command entry header. */ 70 struct qlc_83xx_entry_hdr { 71 #if defined(__LITTLE_ENDIAN) 72 u16 cmd; 73 u16 size; 74 u16 count; 75 u16 delay; 76 #elif defined(__BIG_ENDIAN) 77 u16 size; 78 u16 cmd; 79 u16 delay; 80 u16 count; 81 #endif 82 } __packed; 83 84 /* Generic poll command */ 85 struct qlc_83xx_poll { 86 u32 mask; 87 u32 status; 88 } __packed; 89 90 /* Read modify write command */ 91 struct qlc_83xx_rmw { 92 u32 mask; 93 u32 xor_value; 94 u32 or_value; 95 #if defined(__LITTLE_ENDIAN) 96 u8 shl; 97 u8 shr; 98 u8 index_a; 99 u8 rsvd; 100 #elif defined(__BIG_ENDIAN) 101 u8 rsvd; 102 u8 index_a; 103 u8 shr; 104 u8 shl; 105 #endif 106 } __packed; 107 108 /* Generic command with 2 DWORD */ 109 struct qlc_83xx_entry { 110 u32 arg1; 111 u32 arg2; 112 } __packed; 113 114 /* Generic command with 4 DWORD */ 115 struct qlc_83xx_quad_entry { 116 u32 dr_addr; 117 u32 dr_value; 118 u32 ar_addr; 119 u32 ar_value; 120 } __packed; 121 static const char *const qlc_83xx_idc_states[] = { 122 "Unknown", 123 "Cold", 124 "Init", 125 "Ready", 126 "Need Reset", 127 "Need Quiesce", 128 "Failed", 129 "Quiesce" 130 }; 131 132 static int 133 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter) 134 { 135 u32 val; 136 137 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 138 if ((val & 0xFFFF)) 139 return 1; 140 else 141 return 0; 142 } 143 144 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter) 145 { 146 u32 cur, prev; 147 cur = adapter->ahw->idc.curr_state; 148 prev = adapter->ahw->idc.prev_state; 149 150 dev_info(&adapter->pdev->dev, 151 "current state = %s, prev state = %s\n", 152 adapter->ahw->idc.name[cur], 153 adapter->ahw->idc.name[prev]); 154 } 155 156 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter, 157 u8 mode, int lock) 158 { 159 u32 val; 160 int seconds; 161 162 if (lock) { 163 if (qlcnic_83xx_lock_driver(adapter)) 164 return -EBUSY; 165 } 166 167 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 168 val |= (adapter->portnum & 0xf); 169 val |= mode << 7; 170 if (mode) 171 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 172 else 173 seconds = jiffies / HZ; 174 175 val |= seconds << 8; 176 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val); 177 adapter->ahw->idc.sec_counter = jiffies / HZ; 178 179 if (lock) 180 qlcnic_83xx_unlock_driver(adapter); 181 182 return 0; 183 } 184 185 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter) 186 { 187 u32 val; 188 189 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION); 190 val = val & ~(0x3 << (adapter->portnum * 2)); 191 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2)); 192 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val); 193 } 194 195 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter, 196 int lock) 197 { 198 u32 val; 199 200 if (lock) { 201 if (qlcnic_83xx_lock_driver(adapter)) 202 return -EBUSY; 203 } 204 205 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 206 val = val & ~0xFF; 207 val = val | QLC_83XX_IDC_MAJOR_VERSION; 208 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val); 209 210 if (lock) 211 qlcnic_83xx_unlock_driver(adapter); 212 213 return 0; 214 } 215 216 static int 217 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter, 218 int status, int lock) 219 { 220 u32 val; 221 222 if (lock) { 223 if (qlcnic_83xx_lock_driver(adapter)) 224 return -EBUSY; 225 } 226 227 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 228 229 if (status) 230 val = val | (1 << adapter->portnum); 231 else 232 val = val & ~(1 << adapter->portnum); 233 234 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 235 qlcnic_83xx_idc_update_minor_version(adapter); 236 237 if (lock) 238 qlcnic_83xx_unlock_driver(adapter); 239 240 return 0; 241 } 242 243 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter) 244 { 245 u32 val; 246 u8 version; 247 248 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 249 version = val & 0xFF; 250 251 if (version != QLC_83XX_IDC_MAJOR_VERSION) { 252 dev_info(&adapter->pdev->dev, 253 "%s:mismatch. version 0x%x, expected version 0x%x\n", 254 __func__, version, QLC_83XX_IDC_MAJOR_VERSION); 255 return -EIO; 256 } 257 258 return 0; 259 } 260 261 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter, 262 int lock) 263 { 264 u32 val; 265 266 if (lock) { 267 if (qlcnic_83xx_lock_driver(adapter)) 268 return -EBUSY; 269 } 270 271 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0); 272 /* Clear gracefull reset bit */ 273 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 274 val &= ~QLC_83XX_IDC_GRACEFULL_RESET; 275 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 276 277 if (lock) 278 qlcnic_83xx_unlock_driver(adapter); 279 280 return 0; 281 } 282 283 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter, 284 int flag, int lock) 285 { 286 u32 val; 287 288 if (lock) { 289 if (qlcnic_83xx_lock_driver(adapter)) 290 return -EBUSY; 291 } 292 293 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 294 if (flag) 295 val = val | (1 << adapter->portnum); 296 else 297 val = val & ~(1 << adapter->portnum); 298 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val); 299 300 if (lock) 301 qlcnic_83xx_unlock_driver(adapter); 302 303 return 0; 304 } 305 306 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter, 307 int time_limit) 308 { 309 u64 seconds; 310 311 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 312 if (seconds <= time_limit) 313 return 0; 314 else 315 return -EBUSY; 316 } 317 318 /** 319 * qlcnic_83xx_idc_check_reset_ack_reg 320 * 321 * @adapter: adapter structure 322 * 323 * Check ACK wait limit and clear the functions which failed to ACK 324 * 325 * Return 0 if all functions have acknowledged the reset request. 326 **/ 327 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter) 328 { 329 int timeout; 330 u32 ack, presence, val; 331 332 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 333 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 334 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 335 dev_info(&adapter->pdev->dev, 336 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence); 337 if (!((ack & presence) == presence)) { 338 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) { 339 /* Clear functions which failed to ACK */ 340 dev_info(&adapter->pdev->dev, 341 "%s: ACK wait exceeds time limit\n", __func__); 342 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 343 val = val & ~(ack ^ presence); 344 if (qlcnic_83xx_lock_driver(adapter)) 345 return -EBUSY; 346 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 347 dev_info(&adapter->pdev->dev, 348 "%s: updated drv presence reg = 0x%x\n", 349 __func__, val); 350 qlcnic_83xx_unlock_driver(adapter); 351 return 0; 352 353 } else { 354 return 1; 355 } 356 } else { 357 dev_info(&adapter->pdev->dev, 358 "%s: Reset ACK received from all functions\n", 359 __func__); 360 return 0; 361 } 362 } 363 364 /** 365 * qlcnic_83xx_idc_tx_soft_reset 366 * 367 * @adapter: adapter structure 368 * 369 * Handle context deletion and recreation request from transmit routine 370 * 371 * Returns -EBUSY or Success (0) 372 * 373 **/ 374 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter) 375 { 376 struct net_device *netdev = adapter->netdev; 377 378 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 379 return -EBUSY; 380 381 netif_device_detach(netdev); 382 qlcnic_down(adapter, netdev); 383 qlcnic_up(adapter, netdev); 384 netif_device_attach(netdev); 385 clear_bit(__QLCNIC_RESETTING, &adapter->state); 386 netdev_info(adapter->netdev, "%s: soft reset complete.\n", __func__); 387 388 return 0; 389 } 390 391 /** 392 * qlcnic_83xx_idc_detach_driver 393 * 394 * @adapter: adapter structure 395 * Detach net interface, stop TX and cleanup resources before the HW reset. 396 * Returns: None 397 * 398 **/ 399 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter) 400 { 401 int i; 402 struct net_device *netdev = adapter->netdev; 403 404 netif_device_detach(netdev); 405 qlcnic_83xx_detach_mailbox_work(adapter); 406 407 /* Disable mailbox interrupt */ 408 qlcnic_83xx_disable_mbx_intr(adapter); 409 qlcnic_down(adapter, netdev); 410 for (i = 0; i < adapter->ahw->num_msix; i++) { 411 adapter->ahw->intr_tbl[i].id = i; 412 adapter->ahw->intr_tbl[i].enabled = 0; 413 adapter->ahw->intr_tbl[i].src = 0; 414 } 415 416 if (qlcnic_sriov_pf_check(adapter)) 417 qlcnic_sriov_pf_reset(adapter); 418 } 419 420 /** 421 * qlcnic_83xx_idc_attach_driver 422 * 423 * @adapter: adapter structure 424 * 425 * Re-attach and re-enable net interface 426 * Returns: None 427 * 428 **/ 429 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter) 430 { 431 struct net_device *netdev = adapter->netdev; 432 433 if (netif_running(netdev)) { 434 if (qlcnic_up(adapter, netdev)) 435 goto done; 436 qlcnic_restore_indev_addr(netdev, NETDEV_UP); 437 } 438 done: 439 netif_device_attach(netdev); 440 } 441 442 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter, 443 int lock) 444 { 445 if (lock) { 446 if (qlcnic_83xx_lock_driver(adapter)) 447 return -EBUSY; 448 } 449 450 qlcnic_83xx_idc_clear_registers(adapter, 0); 451 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED); 452 if (lock) 453 qlcnic_83xx_unlock_driver(adapter); 454 455 qlcnic_83xx_idc_log_state_history(adapter); 456 dev_info(&adapter->pdev->dev, "Device will enter failed state\n"); 457 458 return 0; 459 } 460 461 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter, 462 int lock) 463 { 464 if (lock) { 465 if (qlcnic_83xx_lock_driver(adapter)) 466 return -EBUSY; 467 } 468 469 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT); 470 471 if (lock) 472 qlcnic_83xx_unlock_driver(adapter); 473 474 return 0; 475 } 476 477 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter, 478 int lock) 479 { 480 if (lock) { 481 if (qlcnic_83xx_lock_driver(adapter)) 482 return -EBUSY; 483 } 484 485 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 486 QLC_83XX_IDC_DEV_NEED_QUISCENT); 487 488 if (lock) 489 qlcnic_83xx_unlock_driver(adapter); 490 491 return 0; 492 } 493 494 static int 495 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock) 496 { 497 if (lock) { 498 if (qlcnic_83xx_lock_driver(adapter)) 499 return -EBUSY; 500 } 501 502 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 503 QLC_83XX_IDC_DEV_NEED_RESET); 504 505 if (lock) 506 qlcnic_83xx_unlock_driver(adapter); 507 508 return 0; 509 } 510 511 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter, 512 int lock) 513 { 514 if (lock) { 515 if (qlcnic_83xx_lock_driver(adapter)) 516 return -EBUSY; 517 } 518 519 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY); 520 if (lock) 521 qlcnic_83xx_unlock_driver(adapter); 522 523 return 0; 524 } 525 526 /** 527 * qlcnic_83xx_idc_find_reset_owner_id 528 * 529 * @adapter: adapter structure 530 * 531 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE. 532 * Within the same class, function with lowest PCI ID assumes ownership 533 * 534 * Returns: reset owner id or failure indication (-EIO) 535 * 536 **/ 537 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter) 538 { 539 u32 reg, reg1, reg2, i, j, owner, class; 540 541 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1); 542 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2); 543 owner = QLCNIC_TYPE_NIC; 544 i = 0; 545 j = 0; 546 reg = reg1; 547 548 do { 549 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3); 550 if (class == owner) 551 break; 552 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) { 553 reg = reg2; 554 j = 0; 555 } else { 556 j++; 557 } 558 559 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) { 560 if (owner == QLCNIC_TYPE_NIC) 561 owner = QLCNIC_TYPE_ISCSI; 562 else if (owner == QLCNIC_TYPE_ISCSI) 563 owner = QLCNIC_TYPE_FCOE; 564 else if (owner == QLCNIC_TYPE_FCOE) 565 return -EIO; 566 reg = reg1; 567 j = 0; 568 i = 0; 569 } 570 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS); 571 572 return i; 573 } 574 575 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock) 576 { 577 int ret = 0; 578 579 ret = qlcnic_83xx_restart_hw(adapter); 580 581 if (ret) { 582 qlcnic_83xx_idc_enter_failed_state(adapter, lock); 583 } else { 584 qlcnic_83xx_idc_clear_registers(adapter, lock); 585 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock); 586 } 587 588 return ret; 589 } 590 591 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter) 592 { 593 u32 status; 594 595 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1); 596 597 if (status & QLCNIC_RCODE_FATAL_ERROR) { 598 dev_err(&adapter->pdev->dev, 599 "peg halt status1=0x%x\n", status); 600 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) { 601 dev_err(&adapter->pdev->dev, 602 "On board active cooling fan failed. " 603 "Device has been halted.\n"); 604 dev_err(&adapter->pdev->dev, 605 "Replace the adapter.\n"); 606 return -EIO; 607 } 608 } 609 610 return 0; 611 } 612 613 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter) 614 { 615 int err; 616 617 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox); 618 qlcnic_83xx_enable_mbx_interrupt(adapter); 619 620 qlcnic_83xx_initialize_nic(adapter, 1); 621 622 err = qlcnic_sriov_pf_reinit(adapter); 623 if (err) 624 return err; 625 626 qlcnic_83xx_enable_mbx_interrupt(adapter); 627 628 if (qlcnic_83xx_configure_opmode(adapter)) { 629 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 630 return -EIO; 631 } 632 633 if (adapter->nic_ops->init_driver(adapter)) { 634 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 635 return -EIO; 636 } 637 638 if (adapter->portnum == 0) 639 qlcnic_set_drv_version(adapter); 640 641 qlcnic_dcb_get_info(adapter->dcb); 642 qlcnic_83xx_idc_attach_driver(adapter); 643 644 return 0; 645 } 646 647 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter) 648 { 649 struct qlcnic_hardware_context *ahw = adapter->ahw; 650 651 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1); 652 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 653 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 654 655 ahw->idc.quiesce_req = 0; 656 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 657 ahw->idc.err_code = 0; 658 ahw->idc.collect_dump = 0; 659 ahw->reset_context = 0; 660 adapter->tx_timeo_cnt = 0; 661 ahw->idc.delay_reset = 0; 662 663 clear_bit(__QLCNIC_RESETTING, &adapter->state); 664 } 665 666 /** 667 * qlcnic_83xx_idc_ready_state_entry 668 * 669 * @adapter: adapter structure 670 * 671 * Perform ready state initialization, this routine will get invoked only 672 * once from READY state. 673 * 674 * Returns: Error code or Success(0) 675 * 676 **/ 677 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter) 678 { 679 struct qlcnic_hardware_context *ahw = adapter->ahw; 680 681 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) { 682 qlcnic_83xx_idc_update_idc_params(adapter); 683 /* Re-attach the device if required */ 684 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) || 685 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) { 686 if (qlcnic_83xx_idc_reattach_driver(adapter)) 687 return -EIO; 688 } 689 } 690 691 return 0; 692 } 693 694 /** 695 * qlcnic_83xx_idc_vnic_pf_entry 696 * 697 * @adapter: adapter structure 698 * 699 * Ensure vNIC mode privileged function starts only after vNIC mode is 700 * enabled by management function. 701 * If vNIC mode is ready, start initialization. 702 * 703 * Returns: -EIO or 0 704 * 705 **/ 706 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter) 707 { 708 u32 state; 709 struct qlcnic_hardware_context *ahw = adapter->ahw; 710 711 /* Privileged function waits till mgmt function enables VNIC mode */ 712 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE); 713 if (state != QLCNIC_DEV_NPAR_OPER) { 714 if (!ahw->idc.vnic_wait_limit--) { 715 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 716 return -EIO; 717 } 718 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n"); 719 return -EIO; 720 721 } else { 722 /* Perform one time initialization from ready state */ 723 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) { 724 qlcnic_83xx_idc_update_idc_params(adapter); 725 726 /* If the previous state is UNKNOWN, device will be 727 already attached properly by Init routine*/ 728 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) { 729 if (qlcnic_83xx_idc_reattach_driver(adapter)) 730 return -EIO; 731 } 732 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER; 733 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n"); 734 } 735 } 736 737 return 0; 738 } 739 740 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter) 741 { 742 adapter->ahw->idc.err_code = -EIO; 743 dev_err(&adapter->pdev->dev, 744 "%s: Device in unknown state\n", __func__); 745 clear_bit(__QLCNIC_RESETTING, &adapter->state); 746 return 0; 747 } 748 749 /** 750 * qlcnic_83xx_idc_cold_state 751 * 752 * @adapter: adapter structure 753 * 754 * If HW is up and running device will enter READY state. 755 * If firmware image from host needs to be loaded, device is 756 * forced to start with the file firmware image. 757 * 758 * Returns: Error code or Success(0) 759 * 760 **/ 761 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter) 762 { 763 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0); 764 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0); 765 766 if (qlcnic_load_fw_file) { 767 qlcnic_83xx_idc_restart_hw(adapter, 0); 768 } else { 769 if (qlcnic_83xx_check_hw_status(adapter)) { 770 qlcnic_83xx_idc_enter_failed_state(adapter, 0); 771 return -EIO; 772 } else { 773 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 774 } 775 } 776 return 0; 777 } 778 779 /** 780 * qlcnic_83xx_idc_init_state 781 * 782 * @adapter: adapter structure 783 * 784 * Reset owner will restart the device from this state. 785 * Device will enter failed state if it remains 786 * in this state for more than DEV_INIT time limit. 787 * 788 * Returns: Error code or Success(0) 789 * 790 **/ 791 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter) 792 { 793 int timeout, ret = 0; 794 u32 owner; 795 796 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 797 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) { 798 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 799 if (adapter->ahw->pci_func == owner) 800 ret = qlcnic_83xx_idc_restart_hw(adapter, 1); 801 } else { 802 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout); 803 } 804 805 return ret; 806 } 807 808 /** 809 * qlcnic_83xx_idc_ready_state 810 * 811 * @adapter: adapter structure 812 * 813 * Perform IDC protocol specicifed actions after monitoring device state and 814 * events. 815 * 816 * Returns: Error code or Success(0) 817 * 818 **/ 819 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter) 820 { 821 struct qlcnic_hardware_context *ahw = adapter->ahw; 822 struct qlcnic_mailbox *mbx = ahw->mailbox; 823 int ret = 0; 824 u32 val; 825 826 /* Perform NIC configuration based ready state entry actions */ 827 if (ahw->idc.state_entry(adapter)) 828 return -EIO; 829 830 if (qlcnic_check_temp(adapter)) { 831 if (ahw->temp == QLCNIC_TEMP_PANIC) { 832 qlcnic_83xx_idc_check_fan_failure(adapter); 833 dev_err(&adapter->pdev->dev, 834 "Error: device temperature %d above limits\n", 835 adapter->ahw->temp); 836 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 837 set_bit(__QLCNIC_RESETTING, &adapter->state); 838 qlcnic_83xx_idc_detach_driver(adapter); 839 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 840 return -EIO; 841 } 842 } 843 844 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 845 ret = qlcnic_83xx_check_heartbeat(adapter); 846 if (ret) { 847 adapter->flags |= QLCNIC_FW_HANG; 848 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 849 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 850 set_bit(__QLCNIC_RESETTING, &adapter->state); 851 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 852 } else { 853 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 854 __func__); 855 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 856 } 857 return -EIO; 858 } 859 860 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) { 861 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 862 863 /* Move to need reset state and prepare for reset */ 864 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 865 return ret; 866 } 867 868 /* Check for soft reset request */ 869 if (ahw->reset_context && 870 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 871 adapter->ahw->reset_context = 0; 872 qlcnic_83xx_idc_tx_soft_reset(adapter); 873 return ret; 874 } 875 876 /* Move to need quiesce state if requested */ 877 if (adapter->ahw->idc.quiesce_req) { 878 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1); 879 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 880 return ret; 881 } 882 883 return ret; 884 } 885 886 /** 887 * qlcnic_83xx_idc_need_reset_state 888 * 889 * @adapter: adapter structure 890 * 891 * Device will remain in this state until: 892 * Reset request ACK's are recieved from all the functions 893 * Wait time exceeds max time limit 894 * 895 * Returns: Error code or Success(0) 896 * 897 **/ 898 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter) 899 { 900 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 901 int ret = 0; 902 903 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) { 904 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 905 set_bit(__QLCNIC_RESETTING, &adapter->state); 906 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 907 if (adapter->ahw->nic_mode == QLCNIC_VNIC_MODE) 908 qlcnic_83xx_disable_vnic_mode(adapter, 1); 909 910 if (qlcnic_check_diag_status(adapter)) { 911 dev_info(&adapter->pdev->dev, 912 "%s: Wait for diag completion\n", __func__); 913 adapter->ahw->idc.delay_reset = 1; 914 return 0; 915 } else { 916 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 917 qlcnic_83xx_idc_detach_driver(adapter); 918 } 919 } 920 921 if (qlcnic_check_diag_status(adapter)) { 922 dev_info(&adapter->pdev->dev, 923 "%s: Wait for diag completion\n", __func__); 924 return -1; 925 } else { 926 if (adapter->ahw->idc.delay_reset) { 927 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 928 qlcnic_83xx_idc_detach_driver(adapter); 929 adapter->ahw->idc.delay_reset = 0; 930 } 931 932 /* Check for ACK from other functions */ 933 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter); 934 if (ret) { 935 dev_info(&adapter->pdev->dev, 936 "%s: Waiting for reset ACK\n", __func__); 937 return -1; 938 } 939 } 940 941 /* Transit to INIT state and restart the HW */ 942 qlcnic_83xx_idc_enter_init_state(adapter, 1); 943 944 return ret; 945 } 946 947 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter) 948 { 949 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__); 950 return 0; 951 } 952 953 static void qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter) 954 { 955 struct qlcnic_hardware_context *ahw = adapter->ahw; 956 u32 val, owner; 957 958 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 959 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 960 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 961 if (ahw->pci_func == owner) { 962 qlcnic_83xx_stop_hw(adapter); 963 qlcnic_dump_fw(adapter); 964 } 965 } 966 967 netdev_warn(adapter->netdev, "%s: Reboot will be required to recover the adapter!!\n", 968 __func__); 969 clear_bit(__QLCNIC_RESETTING, &adapter->state); 970 ahw->idc.err_code = -EIO; 971 972 return; 973 } 974 975 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter) 976 { 977 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__); 978 return 0; 979 } 980 981 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter, 982 u32 state) 983 { 984 u32 cur, prev, next; 985 986 cur = adapter->ahw->idc.curr_state; 987 prev = adapter->ahw->idc.prev_state; 988 next = state; 989 990 if ((next < QLC_83XX_IDC_DEV_COLD) || 991 (next > QLC_83XX_IDC_DEV_QUISCENT)) { 992 dev_err(&adapter->pdev->dev, 993 "%s: curr %d, prev %d, next state %d is invalid\n", 994 __func__, cur, prev, state); 995 return 1; 996 } 997 998 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) && 999 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) { 1000 if ((next != QLC_83XX_IDC_DEV_COLD) && 1001 (next != QLC_83XX_IDC_DEV_READY)) { 1002 dev_err(&adapter->pdev->dev, 1003 "%s: failed, cur %d prev %d next %d\n", 1004 __func__, cur, prev, next); 1005 return 1; 1006 } 1007 } 1008 1009 if (next == QLC_83XX_IDC_DEV_INIT) { 1010 if ((prev != QLC_83XX_IDC_DEV_INIT) && 1011 (prev != QLC_83XX_IDC_DEV_COLD) && 1012 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) { 1013 dev_err(&adapter->pdev->dev, 1014 "%s: failed, cur %d prev %d next %d\n", 1015 __func__, cur, prev, next); 1016 return 1; 1017 } 1018 } 1019 1020 return 0; 1021 } 1022 1023 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter) 1024 { 1025 if (adapter->fhash.fnum) 1026 qlcnic_prune_lb_filters(adapter); 1027 } 1028 1029 /** 1030 * qlcnic_83xx_idc_poll_dev_state 1031 * 1032 * @work: kernel work queue structure used to schedule the function 1033 * 1034 * Poll device state periodically and perform state specific 1035 * actions defined by Inter Driver Communication (IDC) protocol. 1036 * 1037 * Returns: None 1038 * 1039 **/ 1040 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work) 1041 { 1042 struct qlcnic_adapter *adapter; 1043 u32 state; 1044 1045 adapter = container_of(work, struct qlcnic_adapter, fw_work.work); 1046 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1047 1048 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1049 qlcnic_83xx_idc_log_state_history(adapter); 1050 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1051 } else { 1052 adapter->ahw->idc.curr_state = state; 1053 } 1054 1055 switch (adapter->ahw->idc.curr_state) { 1056 case QLC_83XX_IDC_DEV_READY: 1057 qlcnic_83xx_idc_ready_state(adapter); 1058 break; 1059 case QLC_83XX_IDC_DEV_NEED_RESET: 1060 qlcnic_83xx_idc_need_reset_state(adapter); 1061 break; 1062 case QLC_83XX_IDC_DEV_NEED_QUISCENT: 1063 qlcnic_83xx_idc_need_quiesce_state(adapter); 1064 break; 1065 case QLC_83XX_IDC_DEV_FAILED: 1066 qlcnic_83xx_idc_failed_state(adapter); 1067 return; 1068 case QLC_83XX_IDC_DEV_INIT: 1069 qlcnic_83xx_idc_init_state(adapter); 1070 break; 1071 case QLC_83XX_IDC_DEV_QUISCENT: 1072 qlcnic_83xx_idc_quiesce_state(adapter); 1073 break; 1074 default: 1075 qlcnic_83xx_idc_unknown_state(adapter); 1076 return; 1077 } 1078 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state; 1079 qlcnic_83xx_periodic_tasks(adapter); 1080 1081 /* Re-schedule the function */ 1082 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status)) 1083 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 1084 adapter->ahw->idc.delay); 1085 } 1086 1087 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter) 1088 { 1089 u32 idc_params, val; 1090 1091 if (qlcnic_83xx_lockless_flash_read32(adapter, 1092 QLC_83XX_IDC_FLASH_PARAM_ADDR, 1093 (u8 *)&idc_params, 1)) { 1094 dev_info(&adapter->pdev->dev, 1095 "%s:failed to get IDC params from flash\n", __func__); 1096 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 1097 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 1098 } else { 1099 adapter->dev_init_timeo = idc_params & 0xFFFF; 1100 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF); 1101 } 1102 1103 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1104 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN; 1105 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 1106 adapter->ahw->idc.err_code = 0; 1107 adapter->ahw->idc.collect_dump = 0; 1108 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states; 1109 1110 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1111 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1112 1113 /* Check if reset recovery is disabled */ 1114 if (!qlcnic_auto_fw_reset) { 1115 /* Propagate do not reset request to other functions */ 1116 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1117 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1118 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1119 } 1120 } 1121 1122 static int 1123 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter) 1124 { 1125 u32 state, val; 1126 1127 if (qlcnic_83xx_lock_driver(adapter)) 1128 return -EIO; 1129 1130 /* Clear driver lock register */ 1131 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0); 1132 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) { 1133 qlcnic_83xx_unlock_driver(adapter); 1134 return -EIO; 1135 } 1136 1137 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1138 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1139 qlcnic_83xx_unlock_driver(adapter); 1140 return -EIO; 1141 } 1142 1143 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) { 1144 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 1145 QLC_83XX_IDC_DEV_COLD); 1146 state = QLC_83XX_IDC_DEV_COLD; 1147 } 1148 1149 adapter->ahw->idc.curr_state = state; 1150 /* First to load function should cold boot the device */ 1151 if (state == QLC_83XX_IDC_DEV_COLD) 1152 qlcnic_83xx_idc_cold_state_handler(adapter); 1153 1154 /* Check if reset recovery is enabled */ 1155 if (qlcnic_auto_fw_reset) { 1156 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1157 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1158 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1159 } 1160 1161 qlcnic_83xx_unlock_driver(adapter); 1162 1163 return 0; 1164 } 1165 1166 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter) 1167 { 1168 int ret = -EIO; 1169 1170 qlcnic_83xx_setup_idc_parameters(adapter); 1171 1172 if (qlcnic_83xx_get_reset_instruction_template(adapter)) 1173 return ret; 1174 1175 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) { 1176 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter)) 1177 return -EIO; 1178 } else { 1179 if (qlcnic_83xx_idc_check_major_version(adapter)) 1180 return -EIO; 1181 } 1182 1183 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 1184 1185 return 0; 1186 } 1187 1188 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter) 1189 { 1190 int id; 1191 u32 val; 1192 1193 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 1194 usleep_range(10000, 11000); 1195 1196 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1197 id = id & 0xFF; 1198 1199 if (id == adapter->portnum) { 1200 dev_err(&adapter->pdev->dev, 1201 "%s: wait for lock recovery.. %d\n", __func__, id); 1202 msleep(20); 1203 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1204 id = id & 0xFF; 1205 } 1206 1207 /* Clear driver presence bit */ 1208 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 1209 val = val & ~(1 << adapter->portnum); 1210 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 1211 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1212 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1213 1214 cancel_delayed_work_sync(&adapter->fw_work); 1215 } 1216 1217 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key) 1218 { 1219 u32 val; 1220 1221 if (qlcnic_sriov_vf_check(adapter)) 1222 return; 1223 1224 if (qlcnic_83xx_lock_driver(adapter)) { 1225 dev_err(&adapter->pdev->dev, 1226 "%s:failed, please retry\n", __func__); 1227 return; 1228 } 1229 1230 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1231 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 1232 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 1233 __func__); 1234 qlcnic_83xx_idc_enter_failed_state(adapter, 0); 1235 qlcnic_83xx_unlock_driver(adapter); 1236 return; 1237 } 1238 1239 if (key == QLCNIC_FORCE_FW_RESET) { 1240 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1241 val = val | QLC_83XX_IDC_GRACEFULL_RESET; 1242 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1243 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) { 1244 adapter->ahw->idc.collect_dump = 1; 1245 } 1246 1247 qlcnic_83xx_unlock_driver(adapter); 1248 return; 1249 } 1250 1251 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter) 1252 { 1253 u8 *p_cache; 1254 u32 src, size; 1255 u64 dest; 1256 int ret = -EIO; 1257 1258 src = QLC_83XX_BOOTLOADER_FLASH_ADDR; 1259 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR); 1260 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE); 1261 1262 /* alignment check */ 1263 if (size & 0xF) 1264 size = (size + 16) & ~0xF; 1265 1266 p_cache = vzalloc(size); 1267 if (p_cache == NULL) 1268 return -ENOMEM; 1269 1270 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache, 1271 size / sizeof(u32)); 1272 if (ret) { 1273 vfree(p_cache); 1274 return ret; 1275 } 1276 /* 16 byte write to MS memory */ 1277 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache, 1278 size / 16); 1279 if (ret) { 1280 vfree(p_cache); 1281 return ret; 1282 } 1283 vfree(p_cache); 1284 1285 return ret; 1286 } 1287 1288 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter) 1289 { 1290 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info; 1291 const struct firmware *fw = fw_info->fw; 1292 u32 dest, *p_cache; 1293 int i, ret = -EIO; 1294 u8 data[16]; 1295 size_t size; 1296 u64 addr; 1297 1298 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR); 1299 size = (fw->size & ~0xF); 1300 p_cache = (u32 *)fw->data; 1301 addr = (u64)dest; 1302 1303 ret = qlcnic_83xx_ms_mem_write128(adapter, addr, 1304 (u32 *)p_cache, size / 16); 1305 if (ret) { 1306 dev_err(&adapter->pdev->dev, "MS memory write failed\n"); 1307 release_firmware(fw); 1308 fw_info->fw = NULL; 1309 return -EIO; 1310 } 1311 1312 /* alignment check */ 1313 if (fw->size & 0xF) { 1314 addr = dest + size; 1315 for (i = 0; i < (fw->size & 0xF); i++) 1316 data[i] = fw->data[size + i]; 1317 for (; i < 16; i++) 1318 data[i] = 0; 1319 ret = qlcnic_83xx_ms_mem_write128(adapter, addr, 1320 (u32 *)data, 1); 1321 if (ret) { 1322 dev_err(&adapter->pdev->dev, 1323 "MS memory write failed\n"); 1324 release_firmware(fw); 1325 fw_info->fw = NULL; 1326 return -EIO; 1327 } 1328 } 1329 release_firmware(fw); 1330 fw_info->fw = NULL; 1331 1332 return 0; 1333 } 1334 1335 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) 1336 { 1337 int i, j; 1338 u32 val = 0, val1 = 0, reg = 0; 1339 int err = 0; 1340 1341 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err); 1342 if (err == -EIO) 1343 return; 1344 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val); 1345 1346 for (j = 0; j < 2; j++) { 1347 if (j == 0) { 1348 dev_info(&adapter->pdev->dev, 1349 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:"); 1350 reg = QLC_83XX_PORT0_THRESHOLD; 1351 } else if (j == 1) { 1352 dev_info(&adapter->pdev->dev, 1353 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:"); 1354 reg = QLC_83XX_PORT1_THRESHOLD; 1355 } 1356 for (i = 0; i < 8; i++) { 1357 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1358 if (err == -EIO) 1359 return; 1360 dev_info(&adapter->pdev->dev, "0x%x ", val); 1361 } 1362 dev_info(&adapter->pdev->dev, "\n"); 1363 } 1364 1365 for (j = 0; j < 2; j++) { 1366 if (j == 0) { 1367 dev_info(&adapter->pdev->dev, 1368 "Port 0 RxB TC Max Cell Registers[4..1]:"); 1369 reg = QLC_83XX_PORT0_TC_MC_REG; 1370 } else if (j == 1) { 1371 dev_info(&adapter->pdev->dev, 1372 "Port 1 RxB TC Max Cell Registers[4..1]:"); 1373 reg = QLC_83XX_PORT1_TC_MC_REG; 1374 } 1375 for (i = 0; i < 4; i++) { 1376 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1377 if (err == -EIO) 1378 return; 1379 dev_info(&adapter->pdev->dev, "0x%x ", val); 1380 } 1381 dev_info(&adapter->pdev->dev, "\n"); 1382 } 1383 1384 for (j = 0; j < 2; j++) { 1385 if (j == 0) { 1386 dev_info(&adapter->pdev->dev, 1387 "Port 0 RxB Rx TC Stats[TC7..TC0]:"); 1388 reg = QLC_83XX_PORT0_TC_STATS; 1389 } else if (j == 1) { 1390 dev_info(&adapter->pdev->dev, 1391 "Port 1 RxB Rx TC Stats[TC7..TC0]:"); 1392 reg = QLC_83XX_PORT1_TC_STATS; 1393 } 1394 for (i = 7; i >= 0; i--) { 1395 val = QLCRD32(adapter, reg, &err); 1396 if (err == -EIO) 1397 return; 1398 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ 1399 QLCWR32(adapter, reg, (val | (i << 29))); 1400 val = QLCRD32(adapter, reg, &err); 1401 if (err == -EIO) 1402 return; 1403 dev_info(&adapter->pdev->dev, "0x%x ", val); 1404 } 1405 dev_info(&adapter->pdev->dev, "\n"); 1406 } 1407 1408 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err); 1409 if (err == -EIO) 1410 return; 1411 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err); 1412 if (err == -EIO) 1413 return; 1414 dev_info(&adapter->pdev->dev, 1415 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n", 1416 val, val1); 1417 } 1418 1419 1420 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter) 1421 { 1422 u32 reg = 0, i, j; 1423 1424 if (qlcnic_83xx_lock_driver(adapter)) { 1425 dev_err(&adapter->pdev->dev, 1426 "%s:failed to acquire driver lock\n", __func__); 1427 return; 1428 } 1429 1430 qlcnic_83xx_dump_pause_control_regs(adapter); 1431 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0); 1432 1433 for (j = 0; j < 2; j++) { 1434 if (j == 0) 1435 reg = QLC_83XX_PORT0_THRESHOLD; 1436 else if (j == 1) 1437 reg = QLC_83XX_PORT1_THRESHOLD; 1438 1439 for (i = 0; i < 8; i++) 1440 QLCWR32(adapter, reg + (i * 0x4), 0x0); 1441 } 1442 1443 for (j = 0; j < 2; j++) { 1444 if (j == 0) 1445 reg = QLC_83XX_PORT0_TC_MC_REG; 1446 else if (j == 1) 1447 reg = QLC_83XX_PORT1_TC_MC_REG; 1448 1449 for (i = 0; i < 4; i++) 1450 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF); 1451 } 1452 1453 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0); 1454 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0); 1455 dev_info(&adapter->pdev->dev, 1456 "Disabled pause frames successfully on all ports\n"); 1457 qlcnic_83xx_unlock_driver(adapter); 1458 } 1459 1460 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter) 1461 { 1462 QLCWR32(adapter, QLC_83XX_RESET_REG, 0); 1463 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0); 1464 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0); 1465 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0); 1466 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0); 1467 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0); 1468 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0); 1469 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0); 1470 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1); 1471 } 1472 1473 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev) 1474 { 1475 u32 heartbeat, peg_status; 1476 int retries, ret = -EIO, err = 0; 1477 1478 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT; 1479 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev, 1480 QLCNIC_PEG_ALIVE_COUNTER); 1481 1482 do { 1483 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS); 1484 heartbeat = QLC_SHARED_REG_RD32(p_dev, 1485 QLCNIC_PEG_ALIVE_COUNTER); 1486 if (heartbeat != p_dev->heartbeat) { 1487 ret = QLCNIC_RCODE_SUCCESS; 1488 break; 1489 } 1490 } while (--retries); 1491 1492 if (ret) { 1493 dev_err(&p_dev->pdev->dev, "firmware hang detected\n"); 1494 qlcnic_83xx_take_eport_out_of_reset(p_dev); 1495 qlcnic_83xx_disable_pause_frames(p_dev); 1496 peg_status = QLC_SHARED_REG_RD32(p_dev, 1497 QLCNIC_PEG_HALT_STATUS1); 1498 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n" 1499 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n" 1500 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n" 1501 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n" 1502 "PEG_NET_4_PC: 0x%x\n", peg_status, 1503 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2), 1504 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err), 1505 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err), 1506 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err), 1507 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err), 1508 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err)); 1509 1510 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67) 1511 dev_err(&p_dev->pdev->dev, 1512 "Device is being reset err code 0x00006700.\n"); 1513 } 1514 1515 return ret; 1516 } 1517 1518 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev) 1519 { 1520 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT; 1521 u32 val; 1522 1523 do { 1524 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE); 1525 if (val == QLC_83XX_CMDPEG_COMPLETE) 1526 return 0; 1527 msleep(QLCNIC_CMDPEG_CHECK_DELAY); 1528 } while (--retries); 1529 1530 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val); 1531 return -EIO; 1532 } 1533 1534 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev) 1535 { 1536 int err; 1537 1538 err = qlcnic_83xx_check_cmd_peg_status(p_dev); 1539 if (err) 1540 return err; 1541 1542 err = qlcnic_83xx_check_heartbeat(p_dev); 1543 if (err) 1544 return err; 1545 1546 return err; 1547 } 1548 1549 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr, 1550 int duration, u32 mask, u32 status) 1551 { 1552 int timeout_error, err = 0; 1553 u32 value; 1554 u8 retries; 1555 1556 value = QLCRD32(p_dev, addr, &err); 1557 if (err == -EIO) 1558 return err; 1559 retries = duration / 10; 1560 1561 do { 1562 if ((value & mask) != status) { 1563 timeout_error = 1; 1564 msleep(duration / 10); 1565 value = QLCRD32(p_dev, addr, &err); 1566 if (err == -EIO) 1567 return err; 1568 } else { 1569 timeout_error = 0; 1570 break; 1571 } 1572 } while (retries--); 1573 1574 if (timeout_error) { 1575 p_dev->ahw->reset.seq_error++; 1576 dev_err(&p_dev->pdev->dev, 1577 "%s: Timeout Err, entry_num = %d\n", 1578 __func__, p_dev->ahw->reset.seq_index); 1579 dev_err(&p_dev->pdev->dev, 1580 "0x%08x 0x%08x 0x%08x\n", 1581 value, mask, status); 1582 } 1583 1584 return timeout_error; 1585 } 1586 1587 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev) 1588 { 1589 u32 sum = 0; 1590 u16 *buff = (u16 *)p_dev->ahw->reset.buff; 1591 int count = p_dev->ahw->reset.hdr->size / sizeof(u16); 1592 1593 while (count-- > 0) 1594 sum += *buff++; 1595 1596 while (sum >> 16) 1597 sum = (sum & 0xFFFF) + (sum >> 16); 1598 1599 if (~sum) { 1600 return 0; 1601 } else { 1602 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1603 return -1; 1604 } 1605 } 1606 1607 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev) 1608 { 1609 struct qlcnic_hardware_context *ahw = p_dev->ahw; 1610 u32 addr, count, prev_ver, curr_ver; 1611 u8 *p_buff; 1612 1613 if (ahw->reset.buff != NULL) { 1614 prev_ver = p_dev->fw_version; 1615 curr_ver = qlcnic_83xx_get_fw_version(p_dev); 1616 if (curr_ver > prev_ver) 1617 kfree(ahw->reset.buff); 1618 else 1619 return 0; 1620 } 1621 1622 ahw->reset.seq_error = 0; 1623 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL); 1624 if (p_dev->ahw->reset.buff == NULL) 1625 return -ENOMEM; 1626 1627 p_buff = p_dev->ahw->reset.buff; 1628 addr = QLC_83XX_RESET_TEMPLATE_ADDR; 1629 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32); 1630 1631 /* Copy template header from flash */ 1632 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1633 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1634 return -EIO; 1635 } 1636 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff; 1637 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size; 1638 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1639 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32); 1640 1641 /* Copy rest of the template */ 1642 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1643 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1644 return -EIO; 1645 } 1646 1647 if (qlcnic_83xx_reset_template_checksum(p_dev)) 1648 return -EIO; 1649 /* Get Stop, Start and Init command offsets */ 1650 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset; 1651 ahw->reset.start_offset = ahw->reset.buff + 1652 ahw->reset.hdr->start_offset; 1653 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1654 return 0; 1655 } 1656 1657 /* Read Write HW register command */ 1658 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev, 1659 u32 raddr, u32 waddr) 1660 { 1661 int err = 0; 1662 u32 value; 1663 1664 value = QLCRD32(p_dev, raddr, &err); 1665 if (err == -EIO) 1666 return; 1667 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1668 } 1669 1670 /* Read Modify Write HW register command */ 1671 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev, 1672 u32 raddr, u32 waddr, 1673 struct qlc_83xx_rmw *p_rmw_hdr) 1674 { 1675 int err = 0; 1676 u32 value; 1677 1678 if (p_rmw_hdr->index_a) { 1679 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a]; 1680 } else { 1681 value = QLCRD32(p_dev, raddr, &err); 1682 if (err == -EIO) 1683 return; 1684 } 1685 1686 value &= p_rmw_hdr->mask; 1687 value <<= p_rmw_hdr->shl; 1688 value >>= p_rmw_hdr->shr; 1689 value |= p_rmw_hdr->or_value; 1690 value ^= p_rmw_hdr->xor_value; 1691 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1692 } 1693 1694 /* Write HW register command */ 1695 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev, 1696 struct qlc_83xx_entry_hdr *p_hdr) 1697 { 1698 int i; 1699 struct qlc_83xx_entry *entry; 1700 1701 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1702 sizeof(struct qlc_83xx_entry_hdr)); 1703 1704 for (i = 0; i < p_hdr->count; i++, entry++) { 1705 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1, 1706 entry->arg2); 1707 if (p_hdr->delay) 1708 udelay((u32)(p_hdr->delay)); 1709 } 1710 } 1711 1712 /* Read and Write instruction */ 1713 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev, 1714 struct qlc_83xx_entry_hdr *p_hdr) 1715 { 1716 int i; 1717 struct qlc_83xx_entry *entry; 1718 1719 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1720 sizeof(struct qlc_83xx_entry_hdr)); 1721 1722 for (i = 0; i < p_hdr->count; i++, entry++) { 1723 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1, 1724 entry->arg2); 1725 if (p_hdr->delay) 1726 udelay((u32)(p_hdr->delay)); 1727 } 1728 } 1729 1730 /* Poll HW register command */ 1731 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev, 1732 struct qlc_83xx_entry_hdr *p_hdr) 1733 { 1734 long delay; 1735 struct qlc_83xx_entry *entry; 1736 struct qlc_83xx_poll *poll; 1737 int i, err = 0; 1738 unsigned long arg1, arg2; 1739 1740 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1741 sizeof(struct qlc_83xx_entry_hdr)); 1742 1743 entry = (struct qlc_83xx_entry *)((char *)poll + 1744 sizeof(struct qlc_83xx_poll)); 1745 delay = (long)p_hdr->delay; 1746 1747 if (!delay) { 1748 for (i = 0; i < p_hdr->count; i++, entry++) 1749 qlcnic_83xx_poll_reg(p_dev, entry->arg1, 1750 delay, poll->mask, 1751 poll->status); 1752 } else { 1753 for (i = 0; i < p_hdr->count; i++, entry++) { 1754 arg1 = entry->arg1; 1755 arg2 = entry->arg2; 1756 if (delay) { 1757 if (qlcnic_83xx_poll_reg(p_dev, 1758 arg1, delay, 1759 poll->mask, 1760 poll->status)){ 1761 QLCRD32(p_dev, arg1, &err); 1762 if (err == -EIO) 1763 return; 1764 QLCRD32(p_dev, arg2, &err); 1765 if (err == -EIO) 1766 return; 1767 } 1768 } 1769 } 1770 } 1771 } 1772 1773 /* Poll and write HW register command */ 1774 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev, 1775 struct qlc_83xx_entry_hdr *p_hdr) 1776 { 1777 int i; 1778 long delay; 1779 struct qlc_83xx_quad_entry *entry; 1780 struct qlc_83xx_poll *poll; 1781 1782 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1783 sizeof(struct qlc_83xx_entry_hdr)); 1784 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1785 sizeof(struct qlc_83xx_poll)); 1786 delay = (long)p_hdr->delay; 1787 1788 for (i = 0; i < p_hdr->count; i++, entry++) { 1789 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr, 1790 entry->dr_value); 1791 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1792 entry->ar_value); 1793 if (delay) 1794 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1795 poll->mask, poll->status); 1796 } 1797 } 1798 1799 /* Read Modify Write register command */ 1800 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev, 1801 struct qlc_83xx_entry_hdr *p_hdr) 1802 { 1803 int i; 1804 struct qlc_83xx_entry *entry; 1805 struct qlc_83xx_rmw *rmw_hdr; 1806 1807 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr + 1808 sizeof(struct qlc_83xx_entry_hdr)); 1809 1810 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr + 1811 sizeof(struct qlc_83xx_rmw)); 1812 1813 for (i = 0; i < p_hdr->count; i++, entry++) { 1814 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1, 1815 entry->arg2, rmw_hdr); 1816 if (p_hdr->delay) 1817 udelay((u32)(p_hdr->delay)); 1818 } 1819 } 1820 1821 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr) 1822 { 1823 if (p_hdr->delay) 1824 mdelay((u32)((long)p_hdr->delay)); 1825 } 1826 1827 /* Read and poll register command */ 1828 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev, 1829 struct qlc_83xx_entry_hdr *p_hdr) 1830 { 1831 long delay; 1832 int index, i, j, err; 1833 struct qlc_83xx_quad_entry *entry; 1834 struct qlc_83xx_poll *poll; 1835 unsigned long addr; 1836 1837 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1838 sizeof(struct qlc_83xx_entry_hdr)); 1839 1840 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1841 sizeof(struct qlc_83xx_poll)); 1842 delay = (long)p_hdr->delay; 1843 1844 for (i = 0; i < p_hdr->count; i++, entry++) { 1845 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1846 entry->ar_value); 1847 if (delay) { 1848 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1849 poll->mask, poll->status)){ 1850 index = p_dev->ahw->reset.array_index; 1851 addr = entry->dr_addr; 1852 j = QLCRD32(p_dev, addr, &err); 1853 if (err == -EIO) 1854 return; 1855 1856 p_dev->ahw->reset.array[index++] = j; 1857 1858 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES) 1859 p_dev->ahw->reset.array_index = 1; 1860 } 1861 } 1862 } 1863 } 1864 1865 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev) 1866 { 1867 p_dev->ahw->reset.seq_end = 1; 1868 } 1869 1870 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev) 1871 { 1872 p_dev->ahw->reset.template_end = 1; 1873 if (p_dev->ahw->reset.seq_error == 0) 1874 dev_err(&p_dev->pdev->dev, 1875 "HW restart process completed successfully.\n"); 1876 else 1877 dev_err(&p_dev->pdev->dev, 1878 "HW restart completed with timeout errors.\n"); 1879 } 1880 1881 /** 1882 * qlcnic_83xx_exec_template_cmd 1883 * 1884 * @p_dev: adapter structure 1885 * @p_buff: Poiter to instruction template 1886 * 1887 * Template provides instructions to stop, restart and initalize firmware. 1888 * These instructions are abstracted as a series of read, write and 1889 * poll operations on hardware registers. Register information and operation 1890 * specifics are not exposed to the driver. Driver reads the template from 1891 * flash and executes the instructions located at pre-defined offsets. 1892 * 1893 * Returns: None 1894 * */ 1895 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev, 1896 char *p_buff) 1897 { 1898 int index, entries; 1899 struct qlc_83xx_entry_hdr *p_hdr; 1900 char *entry = p_buff; 1901 1902 p_dev->ahw->reset.seq_end = 0; 1903 p_dev->ahw->reset.template_end = 0; 1904 entries = p_dev->ahw->reset.hdr->entries; 1905 index = p_dev->ahw->reset.seq_index; 1906 1907 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) { 1908 p_hdr = (struct qlc_83xx_entry_hdr *)entry; 1909 1910 switch (p_hdr->cmd) { 1911 case QLC_83XX_OPCODE_NOP: 1912 break; 1913 case QLC_83XX_OPCODE_WRITE_LIST: 1914 qlcnic_83xx_write_list(p_dev, p_hdr); 1915 break; 1916 case QLC_83XX_OPCODE_READ_WRITE_LIST: 1917 qlcnic_83xx_read_write_list(p_dev, p_hdr); 1918 break; 1919 case QLC_83XX_OPCODE_POLL_LIST: 1920 qlcnic_83xx_poll_list(p_dev, p_hdr); 1921 break; 1922 case QLC_83XX_OPCODE_POLL_WRITE_LIST: 1923 qlcnic_83xx_poll_write_list(p_dev, p_hdr); 1924 break; 1925 case QLC_83XX_OPCODE_READ_MODIFY_WRITE: 1926 qlcnic_83xx_read_modify_write(p_dev, p_hdr); 1927 break; 1928 case QLC_83XX_OPCODE_SEQ_PAUSE: 1929 qlcnic_83xx_pause(p_hdr); 1930 break; 1931 case QLC_83XX_OPCODE_SEQ_END: 1932 qlcnic_83xx_seq_end(p_dev); 1933 break; 1934 case QLC_83XX_OPCODE_TMPL_END: 1935 qlcnic_83xx_template_end(p_dev); 1936 break; 1937 case QLC_83XX_OPCODE_POLL_READ_LIST: 1938 qlcnic_83xx_poll_read_list(p_dev, p_hdr); 1939 break; 1940 default: 1941 dev_err(&p_dev->pdev->dev, 1942 "%s: Unknown opcode 0x%04x in template %d\n", 1943 __func__, p_hdr->cmd, index); 1944 break; 1945 } 1946 entry += p_hdr->size; 1947 } 1948 p_dev->ahw->reset.seq_index = index; 1949 } 1950 1951 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev) 1952 { 1953 p_dev->ahw->reset.seq_index = 0; 1954 1955 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset); 1956 if (p_dev->ahw->reset.seq_end != 1) 1957 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1958 } 1959 1960 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev) 1961 { 1962 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset); 1963 if (p_dev->ahw->reset.template_end != 1) 1964 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1965 } 1966 1967 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev) 1968 { 1969 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset); 1970 if (p_dev->ahw->reset.seq_end != 1) 1971 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1972 } 1973 1974 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter) 1975 { 1976 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info; 1977 int err = -EIO; 1978 1979 if (request_firmware(&fw_info->fw, fw_info->fw_file_name, 1980 &(adapter->pdev->dev))) { 1981 dev_err(&adapter->pdev->dev, 1982 "No file FW image, loading flash FW image.\n"); 1983 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1984 QLC_83XX_BOOT_FROM_FLASH); 1985 } else { 1986 if (qlcnic_83xx_copy_fw_file(adapter)) 1987 return err; 1988 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1989 QLC_83XX_BOOT_FROM_FILE); 1990 } 1991 1992 return 0; 1993 } 1994 1995 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter) 1996 { 1997 u32 val; 1998 int err = -EIO; 1999 2000 qlcnic_83xx_stop_hw(adapter); 2001 2002 /* Collect FW register dump if required */ 2003 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 2004 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET)) 2005 qlcnic_dump_fw(adapter); 2006 2007 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 2008 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 2009 __func__); 2010 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 2011 return err; 2012 } 2013 2014 qlcnic_83xx_init_hw(adapter); 2015 2016 if (qlcnic_83xx_copy_bootloader(adapter)) 2017 return err; 2018 /* Boot either flash image or firmware image from host file system */ 2019 if (qlcnic_load_fw_file) { 2020 if (qlcnic_83xx_load_fw_image_from_host(adapter)) 2021 return err; 2022 } else { 2023 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 2024 QLC_83XX_BOOT_FROM_FLASH); 2025 } 2026 2027 qlcnic_83xx_start_hw(adapter); 2028 if (qlcnic_83xx_check_hw_status(adapter)) 2029 return -EIO; 2030 2031 return 0; 2032 } 2033 2034 static int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter) 2035 { 2036 int err; 2037 struct qlcnic_info nic_info; 2038 struct qlcnic_hardware_context *ahw = adapter->ahw; 2039 2040 memset(&nic_info, 0, sizeof(struct qlcnic_info)); 2041 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func); 2042 if (err) 2043 return -EIO; 2044 2045 ahw->physical_port = (u8) nic_info.phys_port; 2046 ahw->switch_mode = nic_info.switch_mode; 2047 ahw->max_tx_ques = nic_info.max_tx_ques; 2048 ahw->max_rx_ques = nic_info.max_rx_ques; 2049 ahw->capabilities = nic_info.capabilities; 2050 ahw->max_mac_filters = nic_info.max_mac_filters; 2051 ahw->max_mtu = nic_info.max_mtu; 2052 2053 adapter->max_tx_rings = ahw->max_tx_ques; 2054 adapter->max_sds_rings = ahw->max_rx_ques; 2055 /* eSwitch capability indicates vNIC mode. 2056 * vNIC and SRIOV are mutually exclusive operational modes. 2057 * If SR-IOV capability is detected, SR-IOV physical function 2058 * will get initialized in default mode. 2059 * SR-IOV virtual function initialization follows a 2060 * different code path and opmode. 2061 * SRIOV mode has precedence over vNIC mode. 2062 */ 2063 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) 2064 return QLC_83XX_DEFAULT_OPMODE; 2065 2066 if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY) 2067 return QLCNIC_VNIC_MODE; 2068 2069 return QLC_83XX_DEFAULT_OPMODE; 2070 } 2071 2072 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter) 2073 { 2074 struct qlcnic_hardware_context *ahw = adapter->ahw; 2075 int ret; 2076 2077 ret = qlcnic_83xx_get_nic_configuration(adapter); 2078 if (ret == -EIO) 2079 return -EIO; 2080 2081 if (ret == QLCNIC_VNIC_MODE) { 2082 ahw->nic_mode = QLCNIC_VNIC_MODE; 2083 2084 if (qlcnic_83xx_config_vnic_opmode(adapter)) 2085 return -EIO; 2086 2087 adapter->max_sds_rings = QLCNIC_MAX_VNIC_SDS_RINGS; 2088 adapter->max_tx_rings = QLCNIC_MAX_VNIC_TX_RINGS; 2089 } else if (ret == QLC_83XX_DEFAULT_OPMODE) { 2090 ahw->nic_mode = QLCNIC_DEFAULT_MODE; 2091 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver; 2092 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry; 2093 adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS; 2094 adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS; 2095 } else { 2096 return -EIO; 2097 } 2098 2099 return 0; 2100 } 2101 2102 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter) 2103 { 2104 struct qlcnic_hardware_context *ahw = adapter->ahw; 2105 2106 if (ahw->port_type == QLCNIC_XGBE) { 2107 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G; 2108 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G; 2109 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2110 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2111 2112 } else if (ahw->port_type == QLCNIC_GBE) { 2113 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G; 2114 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2115 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2116 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G; 2117 } 2118 adapter->num_txd = MAX_CMD_DESCRIPTORS; 2119 adapter->max_rds_rings = MAX_RDS_RINGS; 2120 } 2121 2122 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter) 2123 { 2124 int err = -EIO; 2125 2126 qlcnic_83xx_get_minidump_template(adapter); 2127 if (qlcnic_83xx_get_port_info(adapter)) 2128 return err; 2129 2130 qlcnic_83xx_config_buff_descriptors(adapter); 2131 adapter->ahw->msix_supported = !!qlcnic_use_msi_x; 2132 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED; 2133 2134 dev_info(&adapter->pdev->dev, "HAL Version: %d\n", 2135 adapter->ahw->fw_hal_version); 2136 2137 return 0; 2138 } 2139 2140 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1)) 2141 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter) 2142 { 2143 struct qlcnic_cmd_args cmd; 2144 u32 presence_mask, audit_mask; 2145 int status; 2146 2147 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 2148 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 2149 2150 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) { 2151 status = qlcnic_alloc_mbx_args(&cmd, adapter, 2152 QLCNIC_CMD_STOP_NIC_FUNC); 2153 if (status) 2154 return; 2155 2156 cmd.req.arg[1] = BIT_31; 2157 status = qlcnic_issue_cmd(adapter, &cmd); 2158 if (status) 2159 dev_err(&adapter->pdev->dev, 2160 "Failed to clean up the function resources\n"); 2161 qlcnic_free_mbx_args(&cmd); 2162 } 2163 } 2164 2165 static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter) 2166 { 2167 struct qlcnic_hardware_context *ahw = adapter->ahw; 2168 struct pci_dev *pdev = adapter->pdev; 2169 struct qlc_83xx_fw_info *fw_info; 2170 int err = 0; 2171 2172 ahw->fw_info = kzalloc(sizeof(*fw_info), GFP_KERNEL); 2173 if (!ahw->fw_info) { 2174 err = -ENOMEM; 2175 } else { 2176 fw_info = ahw->fw_info; 2177 switch (pdev->device) { 2178 case PCI_DEVICE_ID_QLOGIC_QLE834X: 2179 strncpy(fw_info->fw_file_name, QLC_83XX_FW_FILE_NAME, 2180 QLC_FW_FILE_NAME_LEN); 2181 break; 2182 case PCI_DEVICE_ID_QLOGIC_QLE844X: 2183 strncpy(fw_info->fw_file_name, QLC_84XX_FW_FILE_NAME, 2184 QLC_FW_FILE_NAME_LEN); 2185 break; 2186 default: 2187 dev_err(&pdev->dev, "%s: Invalid device id\n", 2188 __func__); 2189 err = -EINVAL; 2190 break; 2191 } 2192 } 2193 2194 return err; 2195 } 2196 2197 static void qlcnic_83xx_init_rings(struct qlcnic_adapter *adapter) 2198 { 2199 u8 rx_cnt = QLCNIC_DEF_SDS_RINGS; 2200 u8 tx_cnt = QLCNIC_DEF_TX_RINGS; 2201 2202 adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS; 2203 adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS; 2204 2205 if (!adapter->ahw->msix_supported) { 2206 rx_cnt = QLCNIC_SINGLE_RING; 2207 tx_cnt = QLCNIC_SINGLE_RING; 2208 } 2209 2210 /* compute and set drv sds rings */ 2211 qlcnic_set_tx_ring_count(adapter, tx_cnt); 2212 qlcnic_set_sds_ring_count(adapter, rx_cnt); 2213 } 2214 2215 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac) 2216 { 2217 struct qlcnic_hardware_context *ahw = adapter->ahw; 2218 int err = 0; 2219 2220 adapter->rx_mac_learn = false; 2221 ahw->msix_supported = !!qlcnic_use_msi_x; 2222 2223 qlcnic_83xx_init_rings(adapter); 2224 2225 err = qlcnic_83xx_init_mailbox_work(adapter); 2226 if (err) 2227 goto exit; 2228 2229 if (qlcnic_sriov_vf_check(adapter)) { 2230 err = qlcnic_sriov_vf_init(adapter, pci_using_dac); 2231 if (err) 2232 goto detach_mbx; 2233 else 2234 return err; 2235 } 2236 2237 if (qlcnic_83xx_read_flash_descriptor_table(adapter) || 2238 qlcnic_83xx_read_flash_mfg_id(adapter)) { 2239 dev_err(&adapter->pdev->dev, "Failed reading flash mfg id\n"); 2240 err = -ENOTRECOVERABLE; 2241 goto detach_mbx; 2242 } 2243 2244 err = qlcnic_83xx_check_hw_status(adapter); 2245 if (err) 2246 goto detach_mbx; 2247 2248 err = qlcnic_83xx_get_fw_info(adapter); 2249 if (err) 2250 goto detach_mbx; 2251 2252 err = qlcnic_83xx_idc_init(adapter); 2253 if (err) 2254 goto detach_mbx; 2255 2256 err = qlcnic_setup_intr(adapter); 2257 if (err) { 2258 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n"); 2259 goto disable_intr; 2260 } 2261 2262 err = qlcnic_83xx_setup_mbx_intr(adapter); 2263 if (err) 2264 goto disable_mbx_intr; 2265 2266 qlcnic_83xx_clear_function_resources(adapter); 2267 2268 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work); 2269 2270 qlcnic_83xx_initialize_nic(adapter, 1); 2271 2272 /* Configure default, SR-IOV or Virtual NIC mode of operation */ 2273 err = qlcnic_83xx_configure_opmode(adapter); 2274 if (err) 2275 goto disable_mbx_intr; 2276 2277 2278 /* Perform operating mode specific initialization */ 2279 err = adapter->nic_ops->init_driver(adapter); 2280 if (err) 2281 goto disable_mbx_intr; 2282 2283 /* Periodically monitor device status */ 2284 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work); 2285 return 0; 2286 2287 disable_mbx_intr: 2288 qlcnic_83xx_free_mbx_intr(adapter); 2289 2290 disable_intr: 2291 qlcnic_teardown_intr(adapter); 2292 2293 detach_mbx: 2294 qlcnic_83xx_detach_mailbox_work(adapter); 2295 qlcnic_83xx_free_mailbox(ahw->mailbox); 2296 ahw->mailbox = NULL; 2297 exit: 2298 return err; 2299 } 2300 2301 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *adapter) 2302 { 2303 struct qlcnic_hardware_context *ahw = adapter->ahw; 2304 struct qlc_83xx_idc *idc = &ahw->idc; 2305 2306 clear_bit(QLC_83XX_MBX_READY, &idc->status); 2307 cancel_delayed_work_sync(&adapter->fw_work); 2308 2309 if (ahw->nic_mode == QLCNIC_VNIC_MODE) 2310 qlcnic_83xx_disable_vnic_mode(adapter, 1); 2311 2312 qlcnic_83xx_idc_detach_driver(adapter); 2313 qlcnic_83xx_initialize_nic(adapter, 0); 2314 2315 cancel_delayed_work_sync(&adapter->idc_aen_work); 2316 } 2317 2318 int qlcnic_83xx_aer_reset(struct qlcnic_adapter *adapter) 2319 { 2320 struct qlcnic_hardware_context *ahw = adapter->ahw; 2321 struct qlc_83xx_idc *idc = &ahw->idc; 2322 int ret = 0; 2323 u32 owner; 2324 2325 /* Mark the previous IDC state as NEED_RESET so 2326 * that state_entry() will perform the reattachment 2327 * and bringup the device 2328 */ 2329 idc->prev_state = QLC_83XX_IDC_DEV_NEED_RESET; 2330 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 2331 if (ahw->pci_func == owner) { 2332 ret = qlcnic_83xx_restart_hw(adapter); 2333 if (ret < 0) 2334 return ret; 2335 qlcnic_83xx_idc_clear_registers(adapter, 0); 2336 } 2337 2338 ret = idc->state_entry(adapter); 2339 return ret; 2340 } 2341 2342 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *adapter) 2343 { 2344 struct qlcnic_hardware_context *ahw = adapter->ahw; 2345 struct qlc_83xx_idc *idc = &ahw->idc; 2346 u32 owner; 2347 2348 idc->prev_state = QLC_83XX_IDC_DEV_READY; 2349 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 2350 if (ahw->pci_func == owner) 2351 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 2352 2353 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 0); 2354 } 2355