1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #include "qlcnic.h" 9 #include "qlcnic_hw.h" 10 11 /* Reset template definitions */ 12 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000 13 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000 14 #define QLC_83XX_RESET_SEQ_VERSION 0x0101 15 16 #define QLC_83XX_OPCODE_NOP 0x0000 17 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001 18 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002 19 #define QLC_83XX_OPCODE_POLL_LIST 0x0004 20 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008 21 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010 22 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020 23 #define QLC_83XX_OPCODE_SEQ_END 0x0040 24 #define QLC_83XX_OPCODE_TMPL_END 0x0080 25 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100 26 27 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter); 28 static int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter); 29 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev); 30 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter); 31 32 /* Template header */ 33 struct qlc_83xx_reset_hdr { 34 u16 version; 35 u16 signature; 36 u16 size; 37 u16 entries; 38 u16 hdr_size; 39 u16 checksum; 40 u16 init_offset; 41 u16 start_offset; 42 } __packed; 43 44 /* Command entry header. */ 45 struct qlc_83xx_entry_hdr { 46 u16 cmd; 47 u16 size; 48 u16 count; 49 u16 delay; 50 } __packed; 51 52 /* Generic poll command */ 53 struct qlc_83xx_poll { 54 u32 mask; 55 u32 status; 56 } __packed; 57 58 /* Read modify write command */ 59 struct qlc_83xx_rmw { 60 u32 mask; 61 u32 xor_value; 62 u32 or_value; 63 u8 shl; 64 u8 shr; 65 u8 index_a; 66 u8 rsvd; 67 } __packed; 68 69 /* Generic command with 2 DWORD */ 70 struct qlc_83xx_entry { 71 u32 arg1; 72 u32 arg2; 73 } __packed; 74 75 /* Generic command with 4 DWORD */ 76 struct qlc_83xx_quad_entry { 77 u32 dr_addr; 78 u32 dr_value; 79 u32 ar_addr; 80 u32 ar_value; 81 } __packed; 82 static const char *const qlc_83xx_idc_states[] = { 83 "Unknown", 84 "Cold", 85 "Init", 86 "Ready", 87 "Need Reset", 88 "Need Quiesce", 89 "Failed", 90 "Quiesce" 91 }; 92 93 /* Device States */ 94 enum qlcnic_83xx_states { 95 QLC_83XX_IDC_DEV_UNKNOWN, 96 QLC_83XX_IDC_DEV_COLD, 97 QLC_83XX_IDC_DEV_INIT, 98 QLC_83XX_IDC_DEV_READY, 99 QLC_83XX_IDC_DEV_NEED_RESET, 100 QLC_83XX_IDC_DEV_NEED_QUISCENT, 101 QLC_83XX_IDC_DEV_FAILED, 102 QLC_83XX_IDC_DEV_QUISCENT 103 }; 104 105 static int 106 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter) 107 { 108 u32 val; 109 110 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 111 if ((val & 0xFFFF)) 112 return 1; 113 else 114 return 0; 115 } 116 117 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter) 118 { 119 u32 cur, prev; 120 cur = adapter->ahw->idc.curr_state; 121 prev = adapter->ahw->idc.prev_state; 122 123 dev_info(&adapter->pdev->dev, 124 "current state = %s, prev state = %s\n", 125 adapter->ahw->idc.name[cur], 126 adapter->ahw->idc.name[prev]); 127 } 128 129 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter, 130 u8 mode, int lock) 131 { 132 u32 val; 133 int seconds; 134 135 if (lock) { 136 if (qlcnic_83xx_lock_driver(adapter)) 137 return -EBUSY; 138 } 139 140 val = adapter->portnum & 0xf; 141 val |= mode << 7; 142 if (mode) 143 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 144 else 145 seconds = jiffies / HZ; 146 147 val |= seconds << 8; 148 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val); 149 adapter->ahw->idc.sec_counter = jiffies / HZ; 150 151 if (lock) 152 qlcnic_83xx_unlock_driver(adapter); 153 154 return 0; 155 } 156 157 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter) 158 { 159 u32 val; 160 161 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION); 162 val = val & ~(0x3 << (adapter->portnum * 2)); 163 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2)); 164 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val); 165 } 166 167 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter, 168 int lock) 169 { 170 u32 val; 171 172 if (lock) { 173 if (qlcnic_83xx_lock_driver(adapter)) 174 return -EBUSY; 175 } 176 177 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 178 val = val & ~0xFF; 179 val = val | QLC_83XX_IDC_MAJOR_VERSION; 180 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val); 181 182 if (lock) 183 qlcnic_83xx_unlock_driver(adapter); 184 185 return 0; 186 } 187 188 static int 189 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter, 190 int status, int lock) 191 { 192 u32 val; 193 194 if (lock) { 195 if (qlcnic_83xx_lock_driver(adapter)) 196 return -EBUSY; 197 } 198 199 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 200 201 if (status) 202 val = val | (1 << adapter->portnum); 203 else 204 val = val & ~(1 << adapter->portnum); 205 206 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 207 qlcnic_83xx_idc_update_minor_version(adapter); 208 209 if (lock) 210 qlcnic_83xx_unlock_driver(adapter); 211 212 return 0; 213 } 214 215 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter) 216 { 217 u32 val; 218 u8 version; 219 220 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 221 version = val & 0xFF; 222 223 if (version != QLC_83XX_IDC_MAJOR_VERSION) { 224 dev_info(&adapter->pdev->dev, 225 "%s:mismatch. version 0x%x, expected version 0x%x\n", 226 __func__, version, QLC_83XX_IDC_MAJOR_VERSION); 227 return -EIO; 228 } 229 230 return 0; 231 } 232 233 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter, 234 int lock) 235 { 236 u32 val; 237 238 if (lock) { 239 if (qlcnic_83xx_lock_driver(adapter)) 240 return -EBUSY; 241 } 242 243 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0); 244 /* Clear gracefull reset bit */ 245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 246 val &= ~QLC_83XX_IDC_GRACEFULL_RESET; 247 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 248 249 if (lock) 250 qlcnic_83xx_unlock_driver(adapter); 251 252 return 0; 253 } 254 255 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter, 256 int flag, int lock) 257 { 258 u32 val; 259 260 if (lock) { 261 if (qlcnic_83xx_lock_driver(adapter)) 262 return -EBUSY; 263 } 264 265 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 266 if (flag) 267 val = val | (1 << adapter->portnum); 268 else 269 val = val & ~(1 << adapter->portnum); 270 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val); 271 272 if (lock) 273 qlcnic_83xx_unlock_driver(adapter); 274 275 return 0; 276 } 277 278 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter, 279 int time_limit) 280 { 281 u64 seconds; 282 283 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 284 if (seconds <= time_limit) 285 return 0; 286 else 287 return -EBUSY; 288 } 289 290 /** 291 * qlcnic_83xx_idc_check_reset_ack_reg 292 * 293 * @adapter: adapter structure 294 * 295 * Check ACK wait limit and clear the functions which failed to ACK 296 * 297 * Return 0 if all functions have acknowledged the reset request. 298 **/ 299 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter) 300 { 301 int timeout; 302 u32 ack, presence, val; 303 304 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 305 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 306 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 307 dev_info(&adapter->pdev->dev, 308 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence); 309 if (!((ack & presence) == presence)) { 310 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) { 311 /* Clear functions which failed to ACK */ 312 dev_info(&adapter->pdev->dev, 313 "%s: ACK wait exceeds time limit\n", __func__); 314 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 315 val = val & ~(ack ^ presence); 316 if (qlcnic_83xx_lock_driver(adapter)) 317 return -EBUSY; 318 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 319 dev_info(&adapter->pdev->dev, 320 "%s: updated drv presence reg = 0x%x\n", 321 __func__, val); 322 qlcnic_83xx_unlock_driver(adapter); 323 return 0; 324 325 } else { 326 return 1; 327 } 328 } else { 329 dev_info(&adapter->pdev->dev, 330 "%s: Reset ACK received from all functions\n", 331 __func__); 332 return 0; 333 } 334 } 335 336 /** 337 * qlcnic_83xx_idc_tx_soft_reset 338 * 339 * @adapter: adapter structure 340 * 341 * Handle context deletion and recreation request from transmit routine 342 * 343 * Returns -EBUSY or Success (0) 344 * 345 **/ 346 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter) 347 { 348 struct net_device *netdev = adapter->netdev; 349 350 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 351 return -EBUSY; 352 353 netif_device_detach(netdev); 354 qlcnic_down(adapter, netdev); 355 qlcnic_up(adapter, netdev); 356 netif_device_attach(netdev); 357 clear_bit(__QLCNIC_RESETTING, &adapter->state); 358 dev_err(&adapter->pdev->dev, "%s:\n", __func__); 359 360 adapter->netdev->trans_start = jiffies; 361 362 return 0; 363 } 364 365 /** 366 * qlcnic_83xx_idc_detach_driver 367 * 368 * @adapter: adapter structure 369 * Detach net interface, stop TX and cleanup resources before the HW reset. 370 * Returns: None 371 * 372 **/ 373 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter) 374 { 375 int i; 376 struct net_device *netdev = adapter->netdev; 377 378 netif_device_detach(netdev); 379 /* Disable mailbox interrupt */ 380 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0); 381 qlcnic_down(adapter, netdev); 382 for (i = 0; i < adapter->ahw->num_msix; i++) { 383 adapter->ahw->intr_tbl[i].id = i; 384 adapter->ahw->intr_tbl[i].enabled = 0; 385 adapter->ahw->intr_tbl[i].src = 0; 386 } 387 } 388 389 /** 390 * qlcnic_83xx_idc_attach_driver 391 * 392 * @adapter: adapter structure 393 * 394 * Re-attach and re-enable net interface 395 * Returns: None 396 * 397 **/ 398 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter) 399 { 400 struct net_device *netdev = adapter->netdev; 401 402 if (netif_running(netdev)) { 403 if (qlcnic_up(adapter, netdev)) 404 goto done; 405 qlcnic_restore_indev_addr(netdev, NETDEV_UP); 406 } 407 done: 408 netif_device_attach(netdev); 409 if (netif_running(netdev)) { 410 netif_carrier_on(netdev); 411 netif_wake_queue(netdev); 412 } 413 } 414 415 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter, 416 int lock) 417 { 418 if (lock) { 419 if (qlcnic_83xx_lock_driver(adapter)) 420 return -EBUSY; 421 } 422 423 qlcnic_83xx_idc_clear_registers(adapter, 0); 424 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED); 425 if (lock) 426 qlcnic_83xx_unlock_driver(adapter); 427 428 qlcnic_83xx_idc_log_state_history(adapter); 429 dev_info(&adapter->pdev->dev, "Device will enter failed state\n"); 430 431 return 0; 432 } 433 434 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter, 435 int lock) 436 { 437 if (lock) { 438 if (qlcnic_83xx_lock_driver(adapter)) 439 return -EBUSY; 440 } 441 442 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT); 443 444 if (lock) 445 qlcnic_83xx_unlock_driver(adapter); 446 447 return 0; 448 } 449 450 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter, 451 int lock) 452 { 453 if (lock) { 454 if (qlcnic_83xx_lock_driver(adapter)) 455 return -EBUSY; 456 } 457 458 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 459 QLC_83XX_IDC_DEV_NEED_QUISCENT); 460 461 if (lock) 462 qlcnic_83xx_unlock_driver(adapter); 463 464 return 0; 465 } 466 467 static int 468 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock) 469 { 470 if (lock) { 471 if (qlcnic_83xx_lock_driver(adapter)) 472 return -EBUSY; 473 } 474 475 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 476 QLC_83XX_IDC_DEV_NEED_RESET); 477 478 if (lock) 479 qlcnic_83xx_unlock_driver(adapter); 480 481 return 0; 482 } 483 484 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter, 485 int lock) 486 { 487 if (lock) { 488 if (qlcnic_83xx_lock_driver(adapter)) 489 return -EBUSY; 490 } 491 492 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY); 493 if (lock) 494 qlcnic_83xx_unlock_driver(adapter); 495 496 return 0; 497 } 498 499 /** 500 * qlcnic_83xx_idc_find_reset_owner_id 501 * 502 * @adapter: adapter structure 503 * 504 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE. 505 * Within the same class, function with lowest PCI ID assumes ownership 506 * 507 * Returns: reset owner id or failure indication (-EIO) 508 * 509 **/ 510 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter) 511 { 512 u32 reg, reg1, reg2, i, j, owner, class; 513 514 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1); 515 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2); 516 owner = QLCNIC_TYPE_NIC; 517 i = 0; 518 j = 0; 519 reg = reg1; 520 521 do { 522 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3); 523 if (class == owner) 524 break; 525 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) { 526 reg = reg2; 527 j = 0; 528 } else { 529 j++; 530 } 531 532 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) { 533 if (owner == QLCNIC_TYPE_NIC) 534 owner = QLCNIC_TYPE_ISCSI; 535 else if (owner == QLCNIC_TYPE_ISCSI) 536 owner = QLCNIC_TYPE_FCOE; 537 else if (owner == QLCNIC_TYPE_FCOE) 538 return -EIO; 539 reg = reg1; 540 j = 0; 541 i = 0; 542 } 543 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS); 544 545 return i; 546 } 547 548 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock) 549 { 550 int ret = 0; 551 552 ret = qlcnic_83xx_restart_hw(adapter); 553 554 if (ret) { 555 qlcnic_83xx_idc_enter_failed_state(adapter, lock); 556 } else { 557 qlcnic_83xx_idc_clear_registers(adapter, lock); 558 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock); 559 } 560 561 return ret; 562 } 563 564 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter) 565 { 566 u32 status; 567 568 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1); 569 570 if (status & QLCNIC_RCODE_FATAL_ERROR) { 571 dev_err(&adapter->pdev->dev, 572 "peg halt status1=0x%x\n", status); 573 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) { 574 dev_err(&adapter->pdev->dev, 575 "On board active cooling fan failed. " 576 "Device has been halted.\n"); 577 dev_err(&adapter->pdev->dev, 578 "Replace the adapter.\n"); 579 return -EIO; 580 } 581 } 582 583 return 0; 584 } 585 586 static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter) 587 { 588 /* register for NIC IDC AEN Events */ 589 qlcnic_83xx_register_nic_idc_func(adapter, 1); 590 591 qlcnic_83xx_enable_mbx_intrpt(adapter); 592 593 if (qlcnic_83xx_configure_opmode(adapter)) { 594 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 595 return -EIO; 596 } 597 598 if (adapter->nic_ops->init_driver(adapter)) { 599 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 600 return -EIO; 601 } 602 603 qlcnic_83xx_idc_attach_driver(adapter); 604 605 return 0; 606 } 607 608 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter) 609 { 610 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1); 611 clear_bit(__QLCNIC_RESETTING, &adapter->state); 612 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); 613 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 614 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 615 adapter->ahw->idc.quiesce_req = 0; 616 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 617 adapter->ahw->idc.err_code = 0; 618 adapter->ahw->idc.collect_dump = 0; 619 } 620 621 /** 622 * qlcnic_83xx_idc_ready_state_entry 623 * 624 * @adapter: adapter structure 625 * 626 * Perform ready state initialization, this routine will get invoked only 627 * once from READY state. 628 * 629 * Returns: Error code or Success(0) 630 * 631 **/ 632 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter) 633 { 634 struct qlcnic_hardware_context *ahw = adapter->ahw; 635 636 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) { 637 qlcnic_83xx_idc_update_idc_params(adapter); 638 /* Re-attach the device if required */ 639 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) || 640 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) { 641 if (qlcnic_83xx_idc_reattach_driver(adapter)) 642 return -EIO; 643 } 644 } 645 646 return 0; 647 } 648 649 /** 650 * qlcnic_83xx_idc_vnic_pf_entry 651 * 652 * @adapter: adapter structure 653 * 654 * Ensure vNIC mode privileged function starts only after vNIC mode is 655 * enabled by management function. 656 * If vNIC mode is ready, start initialization. 657 * 658 * Returns: -EIO or 0 659 * 660 **/ 661 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter) 662 { 663 u32 state; 664 struct qlcnic_hardware_context *ahw = adapter->ahw; 665 666 /* Privileged function waits till mgmt function enables VNIC mode */ 667 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE); 668 if (state != QLCNIC_DEV_NPAR_OPER) { 669 if (!ahw->idc.vnic_wait_limit--) { 670 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 671 return -EIO; 672 } 673 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n"); 674 return -EIO; 675 676 } else { 677 /* Perform one time initialization from ready state */ 678 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) { 679 qlcnic_83xx_idc_update_idc_params(adapter); 680 681 /* If the previous state is UNKNOWN, device will be 682 already attached properly by Init routine*/ 683 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) { 684 if (qlcnic_83xx_idc_reattach_driver(adapter)) 685 return -EIO; 686 } 687 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER; 688 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n"); 689 } 690 } 691 692 return 0; 693 } 694 695 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter) 696 { 697 adapter->ahw->idc.err_code = -EIO; 698 dev_err(&adapter->pdev->dev, 699 "%s: Device in unknown state\n", __func__); 700 return 0; 701 } 702 703 /** 704 * qlcnic_83xx_idc_cold_state 705 * 706 * @adapter: adapter structure 707 * 708 * If HW is up and running device will enter READY state. 709 * If firmware image from host needs to be loaded, device is 710 * forced to start with the file firmware image. 711 * 712 * Returns: Error code or Success(0) 713 * 714 **/ 715 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter) 716 { 717 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0); 718 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0); 719 720 if (qlcnic_load_fw_file) { 721 qlcnic_83xx_idc_restart_hw(adapter, 0); 722 } else { 723 if (qlcnic_83xx_check_hw_status(adapter)) { 724 qlcnic_83xx_idc_enter_failed_state(adapter, 0); 725 return -EIO; 726 } else { 727 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 728 } 729 } 730 return 0; 731 } 732 733 /** 734 * qlcnic_83xx_idc_init_state 735 * 736 * @adapter: adapter structure 737 * 738 * Reset owner will restart the device from this state. 739 * Device will enter failed state if it remains 740 * in this state for more than DEV_INIT time limit. 741 * 742 * Returns: Error code or Success(0) 743 * 744 **/ 745 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter) 746 { 747 int timeout, ret = 0; 748 u32 owner; 749 750 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 751 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) { 752 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 753 if (adapter->ahw->pci_func == owner) 754 ret = qlcnic_83xx_idc_restart_hw(adapter, 1); 755 } else { 756 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout); 757 return ret; 758 } 759 760 return ret; 761 } 762 763 /** 764 * qlcnic_83xx_idc_ready_state 765 * 766 * @adapter: adapter structure 767 * 768 * Perform IDC protocol specicifed actions after monitoring device state and 769 * events. 770 * 771 * Returns: Error code or Success(0) 772 * 773 **/ 774 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter) 775 { 776 u32 val; 777 struct qlcnic_hardware_context *ahw = adapter->ahw; 778 int ret = 0; 779 780 /* Perform NIC configuration based ready state entry actions */ 781 if (ahw->idc.state_entry(adapter)) 782 return -EIO; 783 784 if (qlcnic_check_temp(adapter)) { 785 if (ahw->temp == QLCNIC_TEMP_PANIC) { 786 qlcnic_83xx_idc_check_fan_failure(adapter); 787 dev_err(&adapter->pdev->dev, 788 "Error: device temperature %d above limits\n", 789 adapter->ahw->temp); 790 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status); 791 set_bit(__QLCNIC_RESETTING, &adapter->state); 792 qlcnic_83xx_idc_detach_driver(adapter); 793 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 794 return -EIO; 795 } 796 } 797 798 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 799 ret = qlcnic_83xx_check_heartbeat(adapter); 800 if (ret) { 801 adapter->flags |= QLCNIC_FW_HANG; 802 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 803 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status); 804 set_bit(__QLCNIC_RESETTING, &adapter->state); 805 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 806 } 807 return -EIO; 808 } 809 810 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) { 811 /* Move to need reset state and prepare for reset */ 812 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 813 return ret; 814 } 815 816 /* Check for soft reset request */ 817 if (ahw->reset_context && 818 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 819 qlcnic_83xx_idc_tx_soft_reset(adapter); 820 return ret; 821 } 822 823 /* Move to need quiesce state if requested */ 824 if (adapter->ahw->idc.quiesce_req) { 825 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1); 826 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 827 return ret; 828 } 829 830 return ret; 831 } 832 833 /** 834 * qlcnic_83xx_idc_need_reset_state 835 * 836 * @adapter: adapter structure 837 * 838 * Device will remain in this state until: 839 * Reset request ACK's are recieved from all the functions 840 * Wait time exceeds max time limit 841 * 842 * Returns: Error code or Success(0) 843 * 844 **/ 845 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter) 846 { 847 int ret = 0; 848 849 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) { 850 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 851 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 852 set_bit(__QLCNIC_RESETTING, &adapter->state); 853 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); 854 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) 855 qlcnic_83xx_disable_vnic_mode(adapter, 1); 856 qlcnic_83xx_idc_detach_driver(adapter); 857 } 858 859 /* Check ACK from other functions */ 860 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter); 861 if (ret) { 862 dev_info(&adapter->pdev->dev, 863 "%s: Waiting for reset ACK\n", __func__); 864 return 0; 865 } 866 867 /* Transit to INIT state and restart the HW */ 868 qlcnic_83xx_idc_enter_init_state(adapter, 1); 869 870 return ret; 871 } 872 873 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter) 874 { 875 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__); 876 return 0; 877 } 878 879 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter) 880 { 881 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__); 882 adapter->ahw->idc.err_code = -EIO; 883 884 return 0; 885 } 886 887 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter) 888 { 889 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__); 890 return 0; 891 } 892 893 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter, 894 u32 state) 895 { 896 u32 cur, prev, next; 897 898 cur = adapter->ahw->idc.curr_state; 899 prev = adapter->ahw->idc.prev_state; 900 next = state; 901 902 if ((next < QLC_83XX_IDC_DEV_COLD) || 903 (next > QLC_83XX_IDC_DEV_QUISCENT)) { 904 dev_err(&adapter->pdev->dev, 905 "%s: curr %d, prev %d, next state %d is invalid\n", 906 __func__, cur, prev, state); 907 return 1; 908 } 909 910 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) && 911 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) { 912 if ((next != QLC_83XX_IDC_DEV_COLD) && 913 (next != QLC_83XX_IDC_DEV_READY)) { 914 dev_err(&adapter->pdev->dev, 915 "%s: failed, cur %d prev %d next %d\n", 916 __func__, cur, prev, next); 917 return 1; 918 } 919 } 920 921 if (next == QLC_83XX_IDC_DEV_INIT) { 922 if ((prev != QLC_83XX_IDC_DEV_INIT) && 923 (prev != QLC_83XX_IDC_DEV_COLD) && 924 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) { 925 dev_err(&adapter->pdev->dev, 926 "%s: failed, cur %d prev %d next %d\n", 927 __func__, cur, prev, next); 928 return 1; 929 } 930 } 931 932 return 0; 933 } 934 935 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter) 936 { 937 if (adapter->fhash.fnum) 938 qlcnic_prune_lb_filters(adapter); 939 } 940 941 /** 942 * qlcnic_83xx_idc_poll_dev_state 943 * 944 * @work: kernel work queue structure used to schedule the function 945 * 946 * Poll device state periodically and perform state specific 947 * actions defined by Inter Driver Communication (IDC) protocol. 948 * 949 * Returns: None 950 * 951 **/ 952 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work) 953 { 954 struct qlcnic_adapter *adapter; 955 u32 state; 956 957 adapter = container_of(work, struct qlcnic_adapter, fw_work.work); 958 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 959 960 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 961 qlcnic_83xx_idc_log_state_history(adapter); 962 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 963 } else { 964 adapter->ahw->idc.curr_state = state; 965 } 966 967 switch (adapter->ahw->idc.curr_state) { 968 case QLC_83XX_IDC_DEV_READY: 969 qlcnic_83xx_idc_ready_state(adapter); 970 break; 971 case QLC_83XX_IDC_DEV_NEED_RESET: 972 qlcnic_83xx_idc_need_reset_state(adapter); 973 break; 974 case QLC_83XX_IDC_DEV_NEED_QUISCENT: 975 qlcnic_83xx_idc_need_quiesce_state(adapter); 976 break; 977 case QLC_83XX_IDC_DEV_FAILED: 978 qlcnic_83xx_idc_failed_state(adapter); 979 return; 980 case QLC_83XX_IDC_DEV_INIT: 981 qlcnic_83xx_idc_init_state(adapter); 982 break; 983 case QLC_83XX_IDC_DEV_QUISCENT: 984 qlcnic_83xx_idc_quiesce_state(adapter); 985 break; 986 default: 987 qlcnic_83xx_idc_unknown_state(adapter); 988 return; 989 } 990 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state; 991 qlcnic_83xx_periodic_tasks(adapter); 992 993 /* Re-schedule the function */ 994 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status)) 995 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 996 adapter->ahw->idc.delay); 997 } 998 999 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter) 1000 { 1001 u32 idc_params, val; 1002 1003 if (qlcnic_83xx_lockless_flash_read32(adapter, 1004 QLC_83XX_IDC_FLASH_PARAM_ADDR, 1005 (u8 *)&idc_params, 1)) { 1006 dev_info(&adapter->pdev->dev, 1007 "%s:failed to get IDC params from flash\n", __func__); 1008 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 1009 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 1010 } else { 1011 adapter->dev_init_timeo = idc_params & 0xFFFF; 1012 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF); 1013 } 1014 1015 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1016 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN; 1017 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 1018 adapter->ahw->idc.err_code = 0; 1019 adapter->ahw->idc.collect_dump = 0; 1020 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states; 1021 1022 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1023 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); 1024 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1025 1026 /* Check if reset recovery is disabled */ 1027 if (!qlcnic_auto_fw_reset) { 1028 /* Propagate do not reset request to other functions */ 1029 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1030 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1031 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1032 } 1033 } 1034 1035 static int 1036 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter) 1037 { 1038 u32 state, val; 1039 1040 if (qlcnic_83xx_lock_driver(adapter)) 1041 return -EIO; 1042 1043 /* Clear driver lock register */ 1044 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0); 1045 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) { 1046 qlcnic_83xx_unlock_driver(adapter); 1047 return -EIO; 1048 } 1049 1050 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1051 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1052 qlcnic_83xx_unlock_driver(adapter); 1053 return -EIO; 1054 } 1055 1056 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) { 1057 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 1058 QLC_83XX_IDC_DEV_COLD); 1059 state = QLC_83XX_IDC_DEV_COLD; 1060 } 1061 1062 adapter->ahw->idc.curr_state = state; 1063 /* First to load function should cold boot the device */ 1064 if (state == QLC_83XX_IDC_DEV_COLD) 1065 qlcnic_83xx_idc_cold_state_handler(adapter); 1066 1067 /* Check if reset recovery is enabled */ 1068 if (qlcnic_auto_fw_reset) { 1069 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1070 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1071 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1072 } 1073 1074 qlcnic_83xx_unlock_driver(adapter); 1075 1076 return 0; 1077 } 1078 1079 static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter) 1080 { 1081 int ret = -EIO; 1082 1083 qlcnic_83xx_setup_idc_parameters(adapter); 1084 1085 if (qlcnic_83xx_get_reset_instruction_template(adapter)) 1086 return ret; 1087 1088 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) { 1089 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter)) 1090 return -EIO; 1091 } else { 1092 if (qlcnic_83xx_idc_check_major_version(adapter)) 1093 return -EIO; 1094 } 1095 1096 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 1097 1098 return 0; 1099 } 1100 1101 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter) 1102 { 1103 int id; 1104 u32 val; 1105 1106 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 1107 usleep_range(10000, 11000); 1108 1109 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1110 id = id & 0xFF; 1111 1112 if (id == adapter->portnum) { 1113 dev_err(&adapter->pdev->dev, 1114 "%s: wait for lock recovery.. %d\n", __func__, id); 1115 msleep(20); 1116 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1117 id = id & 0xFF; 1118 } 1119 1120 /* Clear driver presence bit */ 1121 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 1122 val = val & ~(1 << adapter->portnum); 1123 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 1124 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1125 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1126 1127 cancel_delayed_work_sync(&adapter->fw_work); 1128 } 1129 1130 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key) 1131 { 1132 u32 val; 1133 1134 if (qlcnic_83xx_lock_driver(adapter)) { 1135 dev_err(&adapter->pdev->dev, 1136 "%s:failed, please retry\n", __func__); 1137 return; 1138 } 1139 1140 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1141 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) || 1142 !qlcnic_auto_fw_reset) { 1143 dev_err(&adapter->pdev->dev, 1144 "%s:failed, device in non reset mode\n", __func__); 1145 qlcnic_83xx_unlock_driver(adapter); 1146 return; 1147 } 1148 1149 if (key == QLCNIC_FORCE_FW_RESET) { 1150 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1151 val = val | QLC_83XX_IDC_GRACEFULL_RESET; 1152 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1153 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) { 1154 adapter->ahw->idc.collect_dump = 1; 1155 } 1156 1157 qlcnic_83xx_unlock_driver(adapter); 1158 return; 1159 } 1160 1161 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter) 1162 { 1163 u8 *p_cache; 1164 u32 src, size; 1165 u64 dest; 1166 int ret = -EIO; 1167 1168 src = QLC_83XX_BOOTLOADER_FLASH_ADDR; 1169 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR); 1170 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE); 1171 1172 /* alignment check */ 1173 if (size & 0xF) 1174 size = (size + 16) & ~0xF; 1175 1176 p_cache = kzalloc(size, GFP_KERNEL); 1177 if (p_cache == NULL) 1178 return -ENOMEM; 1179 1180 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache, 1181 size / sizeof(u32)); 1182 if (ret) { 1183 kfree(p_cache); 1184 return ret; 1185 } 1186 /* 16 byte write to MS memory */ 1187 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache, 1188 size / 16); 1189 if (ret) { 1190 kfree(p_cache); 1191 return ret; 1192 } 1193 kfree(p_cache); 1194 1195 return ret; 1196 } 1197 1198 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter) 1199 { 1200 u32 dest, *p_cache; 1201 u64 addr; 1202 u8 data[16]; 1203 size_t size; 1204 int i, ret = -EIO; 1205 1206 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR); 1207 size = (adapter->ahw->fw_info.fw->size & ~0xF); 1208 p_cache = (u32 *)adapter->ahw->fw_info.fw->data; 1209 addr = (u64)dest; 1210 1211 ret = qlcnic_83xx_ms_mem_write128(adapter, addr, 1212 (u32 *)p_cache, size / 16); 1213 if (ret) { 1214 dev_err(&adapter->pdev->dev, "MS memory write failed\n"); 1215 release_firmware(adapter->ahw->fw_info.fw); 1216 adapter->ahw->fw_info.fw = NULL; 1217 return -EIO; 1218 } 1219 1220 /* alignment check */ 1221 if (adapter->ahw->fw_info.fw->size & 0xF) { 1222 addr = dest + size; 1223 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++) 1224 data[i] = adapter->ahw->fw_info.fw->data[size + i]; 1225 for (; i < 16; i++) 1226 data[i] = 0; 1227 ret = qlcnic_83xx_ms_mem_write128(adapter, addr, 1228 (u32 *)data, 1); 1229 if (ret) { 1230 dev_err(&adapter->pdev->dev, 1231 "MS memory write failed\n"); 1232 release_firmware(adapter->ahw->fw_info.fw); 1233 adapter->ahw->fw_info.fw = NULL; 1234 return -EIO; 1235 } 1236 } 1237 release_firmware(adapter->ahw->fw_info.fw); 1238 adapter->ahw->fw_info.fw = NULL; 1239 1240 return 0; 1241 } 1242 1243 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) 1244 { 1245 int i, j; 1246 u32 val = 0, val1 = 0, reg = 0; 1247 1248 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG); 1249 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val); 1250 1251 for (j = 0; j < 2; j++) { 1252 if (j == 0) { 1253 dev_info(&adapter->pdev->dev, 1254 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:"); 1255 reg = QLC_83XX_PORT0_THRESHOLD; 1256 } else if (j == 1) { 1257 dev_info(&adapter->pdev->dev, 1258 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:"); 1259 reg = QLC_83XX_PORT1_THRESHOLD; 1260 } 1261 for (i = 0; i < 8; i++) { 1262 val = QLCRD32(adapter, reg + (i * 0x4)); 1263 dev_info(&adapter->pdev->dev, "0x%x ", val); 1264 } 1265 dev_info(&adapter->pdev->dev, "\n"); 1266 } 1267 1268 for (j = 0; j < 2; j++) { 1269 if (j == 0) { 1270 dev_info(&adapter->pdev->dev, 1271 "Port 0 RxB TC Max Cell Registers[4..1]:"); 1272 reg = QLC_83XX_PORT0_TC_MC_REG; 1273 } else if (j == 1) { 1274 dev_info(&adapter->pdev->dev, 1275 "Port 1 RxB TC Max Cell Registers[4..1]:"); 1276 reg = QLC_83XX_PORT1_TC_MC_REG; 1277 } 1278 for (i = 0; i < 4; i++) { 1279 val = QLCRD32(adapter, reg + (i * 0x4)); 1280 dev_info(&adapter->pdev->dev, "0x%x ", val); 1281 } 1282 dev_info(&adapter->pdev->dev, "\n"); 1283 } 1284 1285 for (j = 0; j < 2; j++) { 1286 if (j == 0) { 1287 dev_info(&adapter->pdev->dev, 1288 "Port 0 RxB Rx TC Stats[TC7..TC0]:"); 1289 reg = QLC_83XX_PORT0_TC_STATS; 1290 } else if (j == 1) { 1291 dev_info(&adapter->pdev->dev, 1292 "Port 1 RxB Rx TC Stats[TC7..TC0]:"); 1293 reg = QLC_83XX_PORT1_TC_STATS; 1294 } 1295 for (i = 7; i >= 0; i--) { 1296 val = QLCRD32(adapter, reg); 1297 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ 1298 QLCWR32(adapter, reg, (val | (i << 29))); 1299 val = QLCRD32(adapter, reg); 1300 dev_info(&adapter->pdev->dev, "0x%x ", val); 1301 } 1302 dev_info(&adapter->pdev->dev, "\n"); 1303 } 1304 1305 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD); 1306 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD); 1307 dev_info(&adapter->pdev->dev, 1308 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n", 1309 val, val1); 1310 } 1311 1312 1313 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter) 1314 { 1315 u32 reg = 0, i, j; 1316 1317 if (qlcnic_83xx_lock_driver(adapter)) { 1318 dev_err(&adapter->pdev->dev, 1319 "%s:failed to acquire driver lock\n", __func__); 1320 return; 1321 } 1322 1323 qlcnic_83xx_dump_pause_control_regs(adapter); 1324 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0); 1325 1326 for (j = 0; j < 2; j++) { 1327 if (j == 0) 1328 reg = QLC_83XX_PORT0_THRESHOLD; 1329 else if (j == 1) 1330 reg = QLC_83XX_PORT1_THRESHOLD; 1331 1332 for (i = 0; i < 8; i++) 1333 QLCWR32(adapter, reg + (i * 0x4), 0x0); 1334 } 1335 1336 for (j = 0; j < 2; j++) { 1337 if (j == 0) 1338 reg = QLC_83XX_PORT0_TC_MC_REG; 1339 else if (j == 1) 1340 reg = QLC_83XX_PORT1_TC_MC_REG; 1341 1342 for (i = 0; i < 4; i++) 1343 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF); 1344 } 1345 1346 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0); 1347 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0); 1348 dev_info(&adapter->pdev->dev, 1349 "Disabled pause frames successfully on all ports\n"); 1350 qlcnic_83xx_unlock_driver(adapter); 1351 } 1352 1353 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev) 1354 { 1355 u32 heartbeat, peg_status; 1356 int retries, ret = -EIO; 1357 1358 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT; 1359 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev, 1360 QLCNIC_PEG_ALIVE_COUNTER); 1361 1362 do { 1363 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS); 1364 heartbeat = QLC_SHARED_REG_RD32(p_dev, 1365 QLCNIC_PEG_ALIVE_COUNTER); 1366 if (heartbeat != p_dev->heartbeat) { 1367 ret = QLCNIC_RCODE_SUCCESS; 1368 break; 1369 } 1370 } while (--retries); 1371 1372 if (ret) { 1373 dev_err(&p_dev->pdev->dev, "firmware hang detected\n"); 1374 qlcnic_83xx_disable_pause_frames(p_dev); 1375 peg_status = QLC_SHARED_REG_RD32(p_dev, 1376 QLCNIC_PEG_HALT_STATUS1); 1377 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n" 1378 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n" 1379 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n" 1380 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n" 1381 "PEG_NET_4_PC: 0x%x\n", peg_status, 1382 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2), 1383 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0), 1384 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1), 1385 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2), 1386 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3), 1387 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4)); 1388 1389 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67) 1390 dev_err(&p_dev->pdev->dev, 1391 "Device is being reset err code 0x00006700.\n"); 1392 } 1393 1394 return ret; 1395 } 1396 1397 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev) 1398 { 1399 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT; 1400 u32 val; 1401 1402 do { 1403 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE); 1404 if (val == QLC_83XX_CMDPEG_COMPLETE) 1405 return 0; 1406 msleep(QLCNIC_CMDPEG_CHECK_DELAY); 1407 } while (--retries); 1408 1409 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val); 1410 return -EIO; 1411 } 1412 1413 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev) 1414 { 1415 int err; 1416 1417 err = qlcnic_83xx_check_cmd_peg_status(p_dev); 1418 if (err) 1419 return err; 1420 1421 err = qlcnic_83xx_check_heartbeat(p_dev); 1422 if (err) 1423 return err; 1424 1425 return err; 1426 } 1427 1428 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr, 1429 int duration, u32 mask, u32 status) 1430 { 1431 u32 value; 1432 int timeout_error; 1433 u8 retries; 1434 1435 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr); 1436 retries = duration / 10; 1437 1438 do { 1439 if ((value & mask) != status) { 1440 timeout_error = 1; 1441 msleep(duration / 10); 1442 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr); 1443 } else { 1444 timeout_error = 0; 1445 break; 1446 } 1447 } while (retries--); 1448 1449 if (timeout_error) { 1450 p_dev->ahw->reset.seq_error++; 1451 dev_err(&p_dev->pdev->dev, 1452 "%s: Timeout Err, entry_num = %d\n", 1453 __func__, p_dev->ahw->reset.seq_index); 1454 dev_err(&p_dev->pdev->dev, 1455 "0x%08x 0x%08x 0x%08x\n", 1456 value, mask, status); 1457 } 1458 1459 return timeout_error; 1460 } 1461 1462 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev) 1463 { 1464 u32 sum = 0; 1465 u16 *buff = (u16 *)p_dev->ahw->reset.buff; 1466 int count = p_dev->ahw->reset.hdr->size / sizeof(u16); 1467 1468 while (count-- > 0) 1469 sum += *buff++; 1470 1471 while (sum >> 16) 1472 sum = (sum & 0xFFFF) + (sum >> 16); 1473 1474 if (~sum) { 1475 return 0; 1476 } else { 1477 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1478 return -1; 1479 } 1480 } 1481 1482 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev) 1483 { 1484 u8 *p_buff; 1485 u32 addr, count; 1486 struct qlcnic_hardware_context *ahw = p_dev->ahw; 1487 1488 ahw->reset.seq_error = 0; 1489 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL); 1490 if (p_dev->ahw->reset.buff == NULL) 1491 return -ENOMEM; 1492 1493 p_buff = p_dev->ahw->reset.buff; 1494 addr = QLC_83XX_RESET_TEMPLATE_ADDR; 1495 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32); 1496 1497 /* Copy template header from flash */ 1498 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1499 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1500 return -EIO; 1501 } 1502 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff; 1503 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size; 1504 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1505 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32); 1506 1507 /* Copy rest of the template */ 1508 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1509 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1510 return -EIO; 1511 } 1512 1513 if (qlcnic_83xx_reset_template_checksum(p_dev)) 1514 return -EIO; 1515 /* Get Stop, Start and Init command offsets */ 1516 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset; 1517 ahw->reset.start_offset = ahw->reset.buff + 1518 ahw->reset.hdr->start_offset; 1519 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1520 return 0; 1521 } 1522 1523 /* Read Write HW register command */ 1524 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev, 1525 u32 raddr, u32 waddr) 1526 { 1527 int value; 1528 1529 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr); 1530 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1531 } 1532 1533 /* Read Modify Write HW register command */ 1534 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev, 1535 u32 raddr, u32 waddr, 1536 struct qlc_83xx_rmw *p_rmw_hdr) 1537 { 1538 int value; 1539 1540 if (p_rmw_hdr->index_a) 1541 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a]; 1542 else 1543 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr); 1544 1545 value &= p_rmw_hdr->mask; 1546 value <<= p_rmw_hdr->shl; 1547 value >>= p_rmw_hdr->shr; 1548 value |= p_rmw_hdr->or_value; 1549 value ^= p_rmw_hdr->xor_value; 1550 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1551 } 1552 1553 /* Write HW register command */ 1554 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev, 1555 struct qlc_83xx_entry_hdr *p_hdr) 1556 { 1557 int i; 1558 struct qlc_83xx_entry *entry; 1559 1560 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1561 sizeof(struct qlc_83xx_entry_hdr)); 1562 1563 for (i = 0; i < p_hdr->count; i++, entry++) { 1564 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1, 1565 entry->arg2); 1566 if (p_hdr->delay) 1567 udelay((u32)(p_hdr->delay)); 1568 } 1569 } 1570 1571 /* Read and Write instruction */ 1572 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev, 1573 struct qlc_83xx_entry_hdr *p_hdr) 1574 { 1575 int i; 1576 struct qlc_83xx_entry *entry; 1577 1578 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1579 sizeof(struct qlc_83xx_entry_hdr)); 1580 1581 for (i = 0; i < p_hdr->count; i++, entry++) { 1582 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1, 1583 entry->arg2); 1584 if (p_hdr->delay) 1585 udelay((u32)(p_hdr->delay)); 1586 } 1587 } 1588 1589 /* Poll HW register command */ 1590 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev, 1591 struct qlc_83xx_entry_hdr *p_hdr) 1592 { 1593 long delay; 1594 struct qlc_83xx_entry *entry; 1595 struct qlc_83xx_poll *poll; 1596 int i; 1597 unsigned long arg1, arg2; 1598 1599 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1600 sizeof(struct qlc_83xx_entry_hdr)); 1601 1602 entry = (struct qlc_83xx_entry *)((char *)poll + 1603 sizeof(struct qlc_83xx_poll)); 1604 delay = (long)p_hdr->delay; 1605 1606 if (!delay) { 1607 for (i = 0; i < p_hdr->count; i++, entry++) 1608 qlcnic_83xx_poll_reg(p_dev, entry->arg1, 1609 delay, poll->mask, 1610 poll->status); 1611 } else { 1612 for (i = 0; i < p_hdr->count; i++, entry++) { 1613 arg1 = entry->arg1; 1614 arg2 = entry->arg2; 1615 if (delay) { 1616 if (qlcnic_83xx_poll_reg(p_dev, 1617 arg1, delay, 1618 poll->mask, 1619 poll->status)){ 1620 qlcnic_83xx_rd_reg_indirect(p_dev, 1621 arg1); 1622 qlcnic_83xx_rd_reg_indirect(p_dev, 1623 arg2); 1624 } 1625 } 1626 } 1627 } 1628 } 1629 1630 /* Poll and write HW register command */ 1631 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev, 1632 struct qlc_83xx_entry_hdr *p_hdr) 1633 { 1634 int i; 1635 long delay; 1636 struct qlc_83xx_quad_entry *entry; 1637 struct qlc_83xx_poll *poll; 1638 1639 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1640 sizeof(struct qlc_83xx_entry_hdr)); 1641 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1642 sizeof(struct qlc_83xx_poll)); 1643 delay = (long)p_hdr->delay; 1644 1645 for (i = 0; i < p_hdr->count; i++, entry++) { 1646 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr, 1647 entry->dr_value); 1648 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1649 entry->ar_value); 1650 if (delay) 1651 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1652 poll->mask, poll->status); 1653 } 1654 } 1655 1656 /* Read Modify Write register command */ 1657 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev, 1658 struct qlc_83xx_entry_hdr *p_hdr) 1659 { 1660 int i; 1661 struct qlc_83xx_entry *entry; 1662 struct qlc_83xx_rmw *rmw_hdr; 1663 1664 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr + 1665 sizeof(struct qlc_83xx_entry_hdr)); 1666 1667 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr + 1668 sizeof(struct qlc_83xx_rmw)); 1669 1670 for (i = 0; i < p_hdr->count; i++, entry++) { 1671 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1, 1672 entry->arg2, rmw_hdr); 1673 if (p_hdr->delay) 1674 udelay((u32)(p_hdr->delay)); 1675 } 1676 } 1677 1678 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr) 1679 { 1680 if (p_hdr->delay) 1681 mdelay((u32)((long)p_hdr->delay)); 1682 } 1683 1684 /* Read and poll register command */ 1685 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev, 1686 struct qlc_83xx_entry_hdr *p_hdr) 1687 { 1688 long delay; 1689 int index, i, j; 1690 struct qlc_83xx_quad_entry *entry; 1691 struct qlc_83xx_poll *poll; 1692 unsigned long addr; 1693 1694 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1695 sizeof(struct qlc_83xx_entry_hdr)); 1696 1697 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1698 sizeof(struct qlc_83xx_poll)); 1699 delay = (long)p_hdr->delay; 1700 1701 for (i = 0; i < p_hdr->count; i++, entry++) { 1702 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1703 entry->ar_value); 1704 if (delay) { 1705 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1706 poll->mask, poll->status)){ 1707 index = p_dev->ahw->reset.array_index; 1708 addr = entry->dr_addr; 1709 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr); 1710 p_dev->ahw->reset.array[index++] = j; 1711 1712 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES) 1713 p_dev->ahw->reset.array_index = 1; 1714 } 1715 } 1716 } 1717 } 1718 1719 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev) 1720 { 1721 p_dev->ahw->reset.seq_end = 1; 1722 } 1723 1724 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev) 1725 { 1726 p_dev->ahw->reset.template_end = 1; 1727 if (p_dev->ahw->reset.seq_error == 0) 1728 dev_err(&p_dev->pdev->dev, 1729 "HW restart process completed successfully.\n"); 1730 else 1731 dev_err(&p_dev->pdev->dev, 1732 "HW restart completed with timeout errors.\n"); 1733 } 1734 1735 /** 1736 * qlcnic_83xx_exec_template_cmd 1737 * 1738 * @p_dev: adapter structure 1739 * @p_buff: Poiter to instruction template 1740 * 1741 * Template provides instructions to stop, restart and initalize firmware. 1742 * These instructions are abstracted as a series of read, write and 1743 * poll operations on hardware registers. Register information and operation 1744 * specifics are not exposed to the driver. Driver reads the template from 1745 * flash and executes the instructions located at pre-defined offsets. 1746 * 1747 * Returns: None 1748 * */ 1749 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev, 1750 char *p_buff) 1751 { 1752 int index, entries; 1753 struct qlc_83xx_entry_hdr *p_hdr; 1754 char *entry = p_buff; 1755 1756 p_dev->ahw->reset.seq_end = 0; 1757 p_dev->ahw->reset.template_end = 0; 1758 entries = p_dev->ahw->reset.hdr->entries; 1759 index = p_dev->ahw->reset.seq_index; 1760 1761 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) { 1762 p_hdr = (struct qlc_83xx_entry_hdr *)entry; 1763 1764 switch (p_hdr->cmd) { 1765 case QLC_83XX_OPCODE_NOP: 1766 break; 1767 case QLC_83XX_OPCODE_WRITE_LIST: 1768 qlcnic_83xx_write_list(p_dev, p_hdr); 1769 break; 1770 case QLC_83XX_OPCODE_READ_WRITE_LIST: 1771 qlcnic_83xx_read_write_list(p_dev, p_hdr); 1772 break; 1773 case QLC_83XX_OPCODE_POLL_LIST: 1774 qlcnic_83xx_poll_list(p_dev, p_hdr); 1775 break; 1776 case QLC_83XX_OPCODE_POLL_WRITE_LIST: 1777 qlcnic_83xx_poll_write_list(p_dev, p_hdr); 1778 break; 1779 case QLC_83XX_OPCODE_READ_MODIFY_WRITE: 1780 qlcnic_83xx_read_modify_write(p_dev, p_hdr); 1781 break; 1782 case QLC_83XX_OPCODE_SEQ_PAUSE: 1783 qlcnic_83xx_pause(p_hdr); 1784 break; 1785 case QLC_83XX_OPCODE_SEQ_END: 1786 qlcnic_83xx_seq_end(p_dev); 1787 break; 1788 case QLC_83XX_OPCODE_TMPL_END: 1789 qlcnic_83xx_template_end(p_dev); 1790 break; 1791 case QLC_83XX_OPCODE_POLL_READ_LIST: 1792 qlcnic_83xx_poll_read_list(p_dev, p_hdr); 1793 break; 1794 default: 1795 dev_err(&p_dev->pdev->dev, 1796 "%s: Unknown opcode 0x%04x in template %d\n", 1797 __func__, p_hdr->cmd, index); 1798 break; 1799 } 1800 entry += p_hdr->size; 1801 } 1802 p_dev->ahw->reset.seq_index = index; 1803 } 1804 1805 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev) 1806 { 1807 p_dev->ahw->reset.seq_index = 0; 1808 1809 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset); 1810 if (p_dev->ahw->reset.seq_end != 1) 1811 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1812 } 1813 1814 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev) 1815 { 1816 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset); 1817 if (p_dev->ahw->reset.template_end != 1) 1818 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1819 } 1820 1821 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev) 1822 { 1823 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset); 1824 if (p_dev->ahw->reset.seq_end != 1) 1825 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1826 } 1827 1828 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter) 1829 { 1830 int err = -EIO; 1831 1832 if (request_firmware(&adapter->ahw->fw_info.fw, 1833 QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) { 1834 dev_err(&adapter->pdev->dev, 1835 "No file FW image, loading flash FW image.\n"); 1836 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1837 QLC_83XX_BOOT_FROM_FLASH); 1838 } else { 1839 if (qlcnic_83xx_copy_fw_file(adapter)) 1840 return err; 1841 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1842 QLC_83XX_BOOT_FROM_FILE); 1843 } 1844 1845 return 0; 1846 } 1847 1848 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter) 1849 { 1850 u32 val; 1851 int err = -EIO; 1852 1853 qlcnic_83xx_stop_hw(adapter); 1854 1855 /* Collect FW register dump if required */ 1856 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1857 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET)) 1858 qlcnic_dump_fw(adapter); 1859 qlcnic_83xx_init_hw(adapter); 1860 1861 if (qlcnic_83xx_copy_bootloader(adapter)) 1862 return err; 1863 /* Boot either flash image or firmware image from host file system */ 1864 if (qlcnic_load_fw_file) { 1865 if (qlcnic_83xx_load_fw_image_from_host(adapter)) 1866 return err; 1867 } else { 1868 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1869 QLC_83XX_BOOT_FROM_FLASH); 1870 } 1871 1872 qlcnic_83xx_start_hw(adapter); 1873 if (qlcnic_83xx_check_hw_status(adapter)) 1874 return -EIO; 1875 1876 return 0; 1877 } 1878 1879 /** 1880 * qlcnic_83xx_config_default_opmode 1881 * 1882 * @adapter: adapter structure 1883 * 1884 * Configure default driver operating mode 1885 * 1886 * Returns: Error code or Success(0) 1887 * */ 1888 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter) 1889 { 1890 u32 op_mode; 1891 struct qlcnic_hardware_context *ahw = adapter->ahw; 1892 1893 qlcnic_get_func_no(adapter); 1894 op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE); 1895 1896 if (op_mode == QLC_83XX_DEFAULT_OPMODE) { 1897 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver; 1898 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry; 1899 } else { 1900 return -EIO; 1901 } 1902 1903 return 0; 1904 } 1905 1906 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter) 1907 { 1908 int err; 1909 struct qlcnic_info nic_info; 1910 struct qlcnic_hardware_context *ahw = adapter->ahw; 1911 1912 memset(&nic_info, 0, sizeof(struct qlcnic_info)); 1913 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func); 1914 if (err) 1915 return -EIO; 1916 1917 ahw->physical_port = (u8) nic_info.phys_port; 1918 ahw->switch_mode = nic_info.switch_mode; 1919 ahw->max_tx_ques = nic_info.max_tx_ques; 1920 ahw->max_rx_ques = nic_info.max_rx_ques; 1921 ahw->capabilities = nic_info.capabilities; 1922 ahw->max_mac_filters = nic_info.max_mac_filters; 1923 ahw->max_mtu = nic_info.max_mtu; 1924 1925 if (ahw->capabilities & BIT_23) 1926 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE; 1927 else 1928 ahw->nic_mode = QLC_83XX_DEFAULT_MODE; 1929 1930 return ahw->nic_mode; 1931 } 1932 1933 static int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter) 1934 { 1935 int ret; 1936 1937 ret = qlcnic_83xx_get_nic_configuration(adapter); 1938 if (ret == -EIO) 1939 return -EIO; 1940 1941 if (ret == QLC_83XX_VIRTUAL_NIC_MODE) { 1942 if (qlcnic_83xx_config_vnic_opmode(adapter)) 1943 return -EIO; 1944 } else if (ret == QLC_83XX_DEFAULT_MODE) { 1945 if (qlcnic_83xx_config_default_opmode(adapter)) 1946 return -EIO; 1947 } 1948 1949 return 0; 1950 } 1951 1952 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter) 1953 { 1954 struct qlcnic_hardware_context *ahw = adapter->ahw; 1955 1956 if (ahw->port_type == QLCNIC_XGBE) { 1957 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G; 1958 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G; 1959 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 1960 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 1961 1962 } else if (ahw->port_type == QLCNIC_GBE) { 1963 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G; 1964 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 1965 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 1966 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G; 1967 } 1968 adapter->num_txd = MAX_CMD_DESCRIPTORS; 1969 adapter->max_rds_rings = MAX_RDS_RINGS; 1970 } 1971 1972 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter) 1973 { 1974 int err = -EIO; 1975 1976 qlcnic_83xx_get_minidump_template(adapter); 1977 if (qlcnic_83xx_get_port_info(adapter)) 1978 return err; 1979 1980 qlcnic_83xx_config_buff_descriptors(adapter); 1981 adapter->ahw->msix_supported = !!qlcnic_use_msi_x; 1982 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED; 1983 1984 dev_info(&adapter->pdev->dev, "HAL Version: %d\n", 1985 adapter->ahw->fw_hal_version); 1986 1987 return 0; 1988 } 1989 1990 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1)) 1991 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter) 1992 { 1993 struct qlcnic_cmd_args cmd; 1994 u32 presence_mask, audit_mask; 1995 int status; 1996 1997 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 1998 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 1999 2000 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) { 2001 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC); 2002 cmd.req.arg[1] = BIT_31; 2003 status = qlcnic_issue_cmd(adapter, &cmd); 2004 if (status) 2005 dev_err(&adapter->pdev->dev, 2006 "Failed to clean up the function resources\n"); 2007 qlcnic_free_mbx_args(&cmd); 2008 } 2009 } 2010 2011 int qlcnic_83xx_init(struct qlcnic_adapter *adapter) 2012 { 2013 struct qlcnic_hardware_context *ahw = adapter->ahw; 2014 2015 if (qlcnic_83xx_check_hw_status(adapter)) 2016 return -EIO; 2017 2018 /* Initilaize 83xx mailbox spinlock */ 2019 spin_lock_init(&ahw->mbx_lock); 2020 2021 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); 2022 qlcnic_83xx_clear_function_resources(adapter); 2023 2024 /* register for NIC IDC AEN Events */ 2025 qlcnic_83xx_register_nic_idc_func(adapter, 1); 2026 2027 if (!qlcnic_83xx_read_flash_descriptor_table(adapter)) 2028 qlcnic_83xx_read_flash_mfg_id(adapter); 2029 2030 if (qlcnic_83xx_idc_init(adapter)) 2031 return -EIO; 2032 2033 /* Configure default, SR-IOV or Virtual NIC mode of operation */ 2034 if (qlcnic_83xx_configure_opmode(adapter)) 2035 return -EIO; 2036 2037 /* Perform operating mode specific initialization */ 2038 if (adapter->nic_ops->init_driver(adapter)) 2039 return -EIO; 2040 2041 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work); 2042 2043 /* Periodically monitor device status */ 2044 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work); 2045 2046 return adapter->ahw->idc.err_code; 2047 } 2048