1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #include "qlcnic_sriov.h" 9 #include "qlcnic.h" 10 #include "qlcnic_hw.h" 11 12 /* Reset template definitions */ 13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000 14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000 15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101 16 17 #define QLC_83XX_OPCODE_NOP 0x0000 18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001 19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002 20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004 21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008 22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010 23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020 24 #define QLC_83XX_OPCODE_SEQ_END 0x0040 25 #define QLC_83XX_OPCODE_TMPL_END 0x0080 26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100 27 28 /* EPORT control registers */ 29 #define QLC_83XX_RESET_CONTROL 0x28084E50 30 #define QLC_83XX_RESET_REG 0x28084E60 31 #define QLC_83XX_RESET_PORT0 0x28084E70 32 #define QLC_83XX_RESET_PORT1 0x28084E80 33 #define QLC_83XX_RESET_PORT2 0x28084E90 34 #define QLC_83XX_RESET_PORT3 0x28084EA0 35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0 36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0 37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0 38 39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter); 40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev); 41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter); 42 43 /* Template header */ 44 struct qlc_83xx_reset_hdr { 45 #if defined(__LITTLE_ENDIAN) 46 u16 version; 47 u16 signature; 48 u16 size; 49 u16 entries; 50 u16 hdr_size; 51 u16 checksum; 52 u16 init_offset; 53 u16 start_offset; 54 #elif defined(__BIG_ENDIAN) 55 u16 signature; 56 u16 version; 57 u16 entries; 58 u16 size; 59 u16 checksum; 60 u16 hdr_size; 61 u16 start_offset; 62 u16 init_offset; 63 #endif 64 } __packed; 65 66 /* Command entry header. */ 67 struct qlc_83xx_entry_hdr { 68 #if defined(__LITTLE_ENDIAN) 69 u16 cmd; 70 u16 size; 71 u16 count; 72 u16 delay; 73 #elif defined(__BIG_ENDIAN) 74 u16 size; 75 u16 cmd; 76 u16 delay; 77 u16 count; 78 #endif 79 } __packed; 80 81 /* Generic poll command */ 82 struct qlc_83xx_poll { 83 u32 mask; 84 u32 status; 85 } __packed; 86 87 /* Read modify write command */ 88 struct qlc_83xx_rmw { 89 u32 mask; 90 u32 xor_value; 91 u32 or_value; 92 #if defined(__LITTLE_ENDIAN) 93 u8 shl; 94 u8 shr; 95 u8 index_a; 96 u8 rsvd; 97 #elif defined(__BIG_ENDIAN) 98 u8 rsvd; 99 u8 index_a; 100 u8 shr; 101 u8 shl; 102 #endif 103 } __packed; 104 105 /* Generic command with 2 DWORD */ 106 struct qlc_83xx_entry { 107 u32 arg1; 108 u32 arg2; 109 } __packed; 110 111 /* Generic command with 4 DWORD */ 112 struct qlc_83xx_quad_entry { 113 u32 dr_addr; 114 u32 dr_value; 115 u32 ar_addr; 116 u32 ar_value; 117 } __packed; 118 static const char *const qlc_83xx_idc_states[] = { 119 "Unknown", 120 "Cold", 121 "Init", 122 "Ready", 123 "Need Reset", 124 "Need Quiesce", 125 "Failed", 126 "Quiesce" 127 }; 128 129 static int 130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter) 131 { 132 u32 val; 133 134 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 135 if ((val & 0xFFFF)) 136 return 1; 137 else 138 return 0; 139 } 140 141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter) 142 { 143 u32 cur, prev; 144 cur = adapter->ahw->idc.curr_state; 145 prev = adapter->ahw->idc.prev_state; 146 147 dev_info(&adapter->pdev->dev, 148 "current state = %s, prev state = %s\n", 149 adapter->ahw->idc.name[cur], 150 adapter->ahw->idc.name[prev]); 151 } 152 153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter, 154 u8 mode, int lock) 155 { 156 u32 val; 157 int seconds; 158 159 if (lock) { 160 if (qlcnic_83xx_lock_driver(adapter)) 161 return -EBUSY; 162 } 163 164 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 165 val |= (adapter->portnum & 0xf); 166 val |= mode << 7; 167 if (mode) 168 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 169 else 170 seconds = jiffies / HZ; 171 172 val |= seconds << 8; 173 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val); 174 adapter->ahw->idc.sec_counter = jiffies / HZ; 175 176 if (lock) 177 qlcnic_83xx_unlock_driver(adapter); 178 179 return 0; 180 } 181 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter) 183 { 184 u32 val; 185 186 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION); 187 val = val & ~(0x3 << (adapter->portnum * 2)); 188 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2)); 189 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val); 190 } 191 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter, 193 int lock) 194 { 195 u32 val; 196 197 if (lock) { 198 if (qlcnic_83xx_lock_driver(adapter)) 199 return -EBUSY; 200 } 201 202 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 203 val = val & ~0xFF; 204 val = val | QLC_83XX_IDC_MAJOR_VERSION; 205 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val); 206 207 if (lock) 208 qlcnic_83xx_unlock_driver(adapter); 209 210 return 0; 211 } 212 213 static int 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter, 215 int status, int lock) 216 { 217 u32 val; 218 219 if (lock) { 220 if (qlcnic_83xx_lock_driver(adapter)) 221 return -EBUSY; 222 } 223 224 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 225 226 if (status) 227 val = val | (1 << adapter->portnum); 228 else 229 val = val & ~(1 << adapter->portnum); 230 231 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 232 qlcnic_83xx_idc_update_minor_version(adapter); 233 234 if (lock) 235 qlcnic_83xx_unlock_driver(adapter); 236 237 return 0; 238 } 239 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter) 241 { 242 u32 val; 243 u8 version; 244 245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 246 version = val & 0xFF; 247 248 if (version != QLC_83XX_IDC_MAJOR_VERSION) { 249 dev_info(&adapter->pdev->dev, 250 "%s:mismatch. version 0x%x, expected version 0x%x\n", 251 __func__, version, QLC_83XX_IDC_MAJOR_VERSION); 252 return -EIO; 253 } 254 255 return 0; 256 } 257 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter, 259 int lock) 260 { 261 u32 val; 262 263 if (lock) { 264 if (qlcnic_83xx_lock_driver(adapter)) 265 return -EBUSY; 266 } 267 268 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0); 269 /* Clear gracefull reset bit */ 270 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 271 val &= ~QLC_83XX_IDC_GRACEFULL_RESET; 272 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 273 274 if (lock) 275 qlcnic_83xx_unlock_driver(adapter); 276 277 return 0; 278 } 279 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter, 281 int flag, int lock) 282 { 283 u32 val; 284 285 if (lock) { 286 if (qlcnic_83xx_lock_driver(adapter)) 287 return -EBUSY; 288 } 289 290 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 291 if (flag) 292 val = val | (1 << adapter->portnum); 293 else 294 val = val & ~(1 << adapter->portnum); 295 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val); 296 297 if (lock) 298 qlcnic_83xx_unlock_driver(adapter); 299 300 return 0; 301 } 302 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter, 304 int time_limit) 305 { 306 u64 seconds; 307 308 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 309 if (seconds <= time_limit) 310 return 0; 311 else 312 return -EBUSY; 313 } 314 315 /** 316 * qlcnic_83xx_idc_check_reset_ack_reg 317 * 318 * @adapter: adapter structure 319 * 320 * Check ACK wait limit and clear the functions which failed to ACK 321 * 322 * Return 0 if all functions have acknowledged the reset request. 323 **/ 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter) 325 { 326 int timeout; 327 u32 ack, presence, val; 328 329 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 330 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 331 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 332 dev_info(&adapter->pdev->dev, 333 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence); 334 if (!((ack & presence) == presence)) { 335 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) { 336 /* Clear functions which failed to ACK */ 337 dev_info(&adapter->pdev->dev, 338 "%s: ACK wait exceeds time limit\n", __func__); 339 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 340 val = val & ~(ack ^ presence); 341 if (qlcnic_83xx_lock_driver(adapter)) 342 return -EBUSY; 343 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 344 dev_info(&adapter->pdev->dev, 345 "%s: updated drv presence reg = 0x%x\n", 346 __func__, val); 347 qlcnic_83xx_unlock_driver(adapter); 348 return 0; 349 350 } else { 351 return 1; 352 } 353 } else { 354 dev_info(&adapter->pdev->dev, 355 "%s: Reset ACK received from all functions\n", 356 __func__); 357 return 0; 358 } 359 } 360 361 /** 362 * qlcnic_83xx_idc_tx_soft_reset 363 * 364 * @adapter: adapter structure 365 * 366 * Handle context deletion and recreation request from transmit routine 367 * 368 * Returns -EBUSY or Success (0) 369 * 370 **/ 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter) 372 { 373 struct net_device *netdev = adapter->netdev; 374 375 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 376 return -EBUSY; 377 378 netif_device_detach(netdev); 379 qlcnic_down(adapter, netdev); 380 qlcnic_up(adapter, netdev); 381 netif_device_attach(netdev); 382 clear_bit(__QLCNIC_RESETTING, &adapter->state); 383 dev_err(&adapter->pdev->dev, "%s:\n", __func__); 384 385 return 0; 386 } 387 388 /** 389 * qlcnic_83xx_idc_detach_driver 390 * 391 * @adapter: adapter structure 392 * Detach net interface, stop TX and cleanup resources before the HW reset. 393 * Returns: None 394 * 395 **/ 396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter) 397 { 398 int i; 399 struct net_device *netdev = adapter->netdev; 400 401 netif_device_detach(netdev); 402 qlcnic_83xx_detach_mailbox_work(adapter); 403 404 /* Disable mailbox interrupt */ 405 qlcnic_83xx_disable_mbx_intr(adapter); 406 qlcnic_down(adapter, netdev); 407 for (i = 0; i < adapter->ahw->num_msix; i++) { 408 adapter->ahw->intr_tbl[i].id = i; 409 adapter->ahw->intr_tbl[i].enabled = 0; 410 adapter->ahw->intr_tbl[i].src = 0; 411 } 412 413 if (qlcnic_sriov_pf_check(adapter)) 414 qlcnic_sriov_pf_reset(adapter); 415 } 416 417 /** 418 * qlcnic_83xx_idc_attach_driver 419 * 420 * @adapter: adapter structure 421 * 422 * Re-attach and re-enable net interface 423 * Returns: None 424 * 425 **/ 426 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter) 427 { 428 struct net_device *netdev = adapter->netdev; 429 430 if (netif_running(netdev)) { 431 if (qlcnic_up(adapter, netdev)) 432 goto done; 433 qlcnic_restore_indev_addr(netdev, NETDEV_UP); 434 } 435 done: 436 netif_device_attach(netdev); 437 } 438 439 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter, 440 int lock) 441 { 442 if (lock) { 443 if (qlcnic_83xx_lock_driver(adapter)) 444 return -EBUSY; 445 } 446 447 qlcnic_83xx_idc_clear_registers(adapter, 0); 448 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED); 449 if (lock) 450 qlcnic_83xx_unlock_driver(adapter); 451 452 qlcnic_83xx_idc_log_state_history(adapter); 453 dev_info(&adapter->pdev->dev, "Device will enter failed state\n"); 454 455 return 0; 456 } 457 458 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter, 459 int lock) 460 { 461 if (lock) { 462 if (qlcnic_83xx_lock_driver(adapter)) 463 return -EBUSY; 464 } 465 466 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT); 467 468 if (lock) 469 qlcnic_83xx_unlock_driver(adapter); 470 471 return 0; 472 } 473 474 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter, 475 int lock) 476 { 477 if (lock) { 478 if (qlcnic_83xx_lock_driver(adapter)) 479 return -EBUSY; 480 } 481 482 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 483 QLC_83XX_IDC_DEV_NEED_QUISCENT); 484 485 if (lock) 486 qlcnic_83xx_unlock_driver(adapter); 487 488 return 0; 489 } 490 491 static int 492 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock) 493 { 494 if (lock) { 495 if (qlcnic_83xx_lock_driver(adapter)) 496 return -EBUSY; 497 } 498 499 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 500 QLC_83XX_IDC_DEV_NEED_RESET); 501 502 if (lock) 503 qlcnic_83xx_unlock_driver(adapter); 504 505 return 0; 506 } 507 508 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter, 509 int lock) 510 { 511 if (lock) { 512 if (qlcnic_83xx_lock_driver(adapter)) 513 return -EBUSY; 514 } 515 516 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY); 517 if (lock) 518 qlcnic_83xx_unlock_driver(adapter); 519 520 return 0; 521 } 522 523 /** 524 * qlcnic_83xx_idc_find_reset_owner_id 525 * 526 * @adapter: adapter structure 527 * 528 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE. 529 * Within the same class, function with lowest PCI ID assumes ownership 530 * 531 * Returns: reset owner id or failure indication (-EIO) 532 * 533 **/ 534 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter) 535 { 536 u32 reg, reg1, reg2, i, j, owner, class; 537 538 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1); 539 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2); 540 owner = QLCNIC_TYPE_NIC; 541 i = 0; 542 j = 0; 543 reg = reg1; 544 545 do { 546 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3); 547 if (class == owner) 548 break; 549 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) { 550 reg = reg2; 551 j = 0; 552 } else { 553 j++; 554 } 555 556 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) { 557 if (owner == QLCNIC_TYPE_NIC) 558 owner = QLCNIC_TYPE_ISCSI; 559 else if (owner == QLCNIC_TYPE_ISCSI) 560 owner = QLCNIC_TYPE_FCOE; 561 else if (owner == QLCNIC_TYPE_FCOE) 562 return -EIO; 563 reg = reg1; 564 j = 0; 565 i = 0; 566 } 567 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS); 568 569 return i; 570 } 571 572 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock) 573 { 574 int ret = 0; 575 576 ret = qlcnic_83xx_restart_hw(adapter); 577 578 if (ret) { 579 qlcnic_83xx_idc_enter_failed_state(adapter, lock); 580 } else { 581 qlcnic_83xx_idc_clear_registers(adapter, lock); 582 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock); 583 } 584 585 return ret; 586 } 587 588 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter) 589 { 590 u32 status; 591 592 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1); 593 594 if (status & QLCNIC_RCODE_FATAL_ERROR) { 595 dev_err(&adapter->pdev->dev, 596 "peg halt status1=0x%x\n", status); 597 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) { 598 dev_err(&adapter->pdev->dev, 599 "On board active cooling fan failed. " 600 "Device has been halted.\n"); 601 dev_err(&adapter->pdev->dev, 602 "Replace the adapter.\n"); 603 return -EIO; 604 } 605 } 606 607 return 0; 608 } 609 610 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter) 611 { 612 int err; 613 614 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox); 615 qlcnic_83xx_enable_mbx_interrupt(adapter); 616 617 /* register for NIC IDC AEN Events */ 618 qlcnic_83xx_register_nic_idc_func(adapter, 1); 619 620 err = qlcnic_sriov_pf_reinit(adapter); 621 if (err) 622 return err; 623 624 qlcnic_83xx_enable_mbx_interrupt(adapter); 625 626 if (qlcnic_83xx_configure_opmode(adapter)) { 627 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 628 return -EIO; 629 } 630 631 if (adapter->nic_ops->init_driver(adapter)) { 632 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 633 return -EIO; 634 } 635 636 if (adapter->portnum == 0) 637 qlcnic_set_drv_version(adapter); 638 639 qlcnic_dcb_get_info(adapter->dcb); 640 qlcnic_83xx_idc_attach_driver(adapter); 641 642 return 0; 643 } 644 645 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter) 646 { 647 struct qlcnic_hardware_context *ahw = adapter->ahw; 648 649 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1); 650 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 651 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 652 653 ahw->idc.quiesce_req = 0; 654 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 655 ahw->idc.err_code = 0; 656 ahw->idc.collect_dump = 0; 657 ahw->reset_context = 0; 658 adapter->tx_timeo_cnt = 0; 659 ahw->idc.delay_reset = 0; 660 661 clear_bit(__QLCNIC_RESETTING, &adapter->state); 662 } 663 664 /** 665 * qlcnic_83xx_idc_ready_state_entry 666 * 667 * @adapter: adapter structure 668 * 669 * Perform ready state initialization, this routine will get invoked only 670 * once from READY state. 671 * 672 * Returns: Error code or Success(0) 673 * 674 **/ 675 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter) 676 { 677 struct qlcnic_hardware_context *ahw = adapter->ahw; 678 679 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) { 680 qlcnic_83xx_idc_update_idc_params(adapter); 681 /* Re-attach the device if required */ 682 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) || 683 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) { 684 if (qlcnic_83xx_idc_reattach_driver(adapter)) 685 return -EIO; 686 } 687 } 688 689 return 0; 690 } 691 692 /** 693 * qlcnic_83xx_idc_vnic_pf_entry 694 * 695 * @adapter: adapter structure 696 * 697 * Ensure vNIC mode privileged function starts only after vNIC mode is 698 * enabled by management function. 699 * If vNIC mode is ready, start initialization. 700 * 701 * Returns: -EIO or 0 702 * 703 **/ 704 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter) 705 { 706 u32 state; 707 struct qlcnic_hardware_context *ahw = adapter->ahw; 708 709 /* Privileged function waits till mgmt function enables VNIC mode */ 710 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE); 711 if (state != QLCNIC_DEV_NPAR_OPER) { 712 if (!ahw->idc.vnic_wait_limit--) { 713 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 714 return -EIO; 715 } 716 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n"); 717 return -EIO; 718 719 } else { 720 /* Perform one time initialization from ready state */ 721 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) { 722 qlcnic_83xx_idc_update_idc_params(adapter); 723 724 /* If the previous state is UNKNOWN, device will be 725 already attached properly by Init routine*/ 726 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) { 727 if (qlcnic_83xx_idc_reattach_driver(adapter)) 728 return -EIO; 729 } 730 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER; 731 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n"); 732 } 733 } 734 735 return 0; 736 } 737 738 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter) 739 { 740 adapter->ahw->idc.err_code = -EIO; 741 dev_err(&adapter->pdev->dev, 742 "%s: Device in unknown state\n", __func__); 743 clear_bit(__QLCNIC_RESETTING, &adapter->state); 744 return 0; 745 } 746 747 /** 748 * qlcnic_83xx_idc_cold_state 749 * 750 * @adapter: adapter structure 751 * 752 * If HW is up and running device will enter READY state. 753 * If firmware image from host needs to be loaded, device is 754 * forced to start with the file firmware image. 755 * 756 * Returns: Error code or Success(0) 757 * 758 **/ 759 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter) 760 { 761 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0); 762 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0); 763 764 if (qlcnic_load_fw_file) { 765 qlcnic_83xx_idc_restart_hw(adapter, 0); 766 } else { 767 if (qlcnic_83xx_check_hw_status(adapter)) { 768 qlcnic_83xx_idc_enter_failed_state(adapter, 0); 769 return -EIO; 770 } else { 771 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 772 } 773 } 774 return 0; 775 } 776 777 /** 778 * qlcnic_83xx_idc_init_state 779 * 780 * @adapter: adapter structure 781 * 782 * Reset owner will restart the device from this state. 783 * Device will enter failed state if it remains 784 * in this state for more than DEV_INIT time limit. 785 * 786 * Returns: Error code or Success(0) 787 * 788 **/ 789 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter) 790 { 791 int timeout, ret = 0; 792 u32 owner; 793 794 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 795 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) { 796 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 797 if (adapter->ahw->pci_func == owner) 798 ret = qlcnic_83xx_idc_restart_hw(adapter, 1); 799 } else { 800 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout); 801 } 802 803 return ret; 804 } 805 806 /** 807 * qlcnic_83xx_idc_ready_state 808 * 809 * @adapter: adapter structure 810 * 811 * Perform IDC protocol specicifed actions after monitoring device state and 812 * events. 813 * 814 * Returns: Error code or Success(0) 815 * 816 **/ 817 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter) 818 { 819 struct qlcnic_hardware_context *ahw = adapter->ahw; 820 struct qlcnic_mailbox *mbx = ahw->mailbox; 821 int ret = 0; 822 u32 val; 823 824 /* Perform NIC configuration based ready state entry actions */ 825 if (ahw->idc.state_entry(adapter)) 826 return -EIO; 827 828 if (qlcnic_check_temp(adapter)) { 829 if (ahw->temp == QLCNIC_TEMP_PANIC) { 830 qlcnic_83xx_idc_check_fan_failure(adapter); 831 dev_err(&adapter->pdev->dev, 832 "Error: device temperature %d above limits\n", 833 adapter->ahw->temp); 834 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 835 set_bit(__QLCNIC_RESETTING, &adapter->state); 836 qlcnic_83xx_idc_detach_driver(adapter); 837 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 838 return -EIO; 839 } 840 } 841 842 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 843 ret = qlcnic_83xx_check_heartbeat(adapter); 844 if (ret) { 845 adapter->flags |= QLCNIC_FW_HANG; 846 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 847 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 848 set_bit(__QLCNIC_RESETTING, &adapter->state); 849 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 850 } else { 851 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 852 __func__); 853 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 854 } 855 return -EIO; 856 } 857 858 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) { 859 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 860 861 /* Move to need reset state and prepare for reset */ 862 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 863 return ret; 864 } 865 866 /* Check for soft reset request */ 867 if (ahw->reset_context && 868 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 869 adapter->ahw->reset_context = 0; 870 qlcnic_83xx_idc_tx_soft_reset(adapter); 871 return ret; 872 } 873 874 /* Move to need quiesce state if requested */ 875 if (adapter->ahw->idc.quiesce_req) { 876 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1); 877 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 878 return ret; 879 } 880 881 return ret; 882 } 883 884 /** 885 * qlcnic_83xx_idc_need_reset_state 886 * 887 * @adapter: adapter structure 888 * 889 * Device will remain in this state until: 890 * Reset request ACK's are recieved from all the functions 891 * Wait time exceeds max time limit 892 * 893 * Returns: Error code or Success(0) 894 * 895 **/ 896 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter) 897 { 898 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 899 int ret = 0; 900 901 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) { 902 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 903 set_bit(__QLCNIC_RESETTING, &adapter->state); 904 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 905 if (adapter->ahw->nic_mode == QLCNIC_VNIC_MODE) 906 qlcnic_83xx_disable_vnic_mode(adapter, 1); 907 908 if (qlcnic_check_diag_status(adapter)) { 909 dev_info(&adapter->pdev->dev, 910 "%s: Wait for diag completion\n", __func__); 911 adapter->ahw->idc.delay_reset = 1; 912 return 0; 913 } else { 914 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 915 qlcnic_83xx_idc_detach_driver(adapter); 916 } 917 } 918 919 if (qlcnic_check_diag_status(adapter)) { 920 dev_info(&adapter->pdev->dev, 921 "%s: Wait for diag completion\n", __func__); 922 return -1; 923 } else { 924 if (adapter->ahw->idc.delay_reset) { 925 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 926 qlcnic_83xx_idc_detach_driver(adapter); 927 adapter->ahw->idc.delay_reset = 0; 928 } 929 930 /* Check for ACK from other functions */ 931 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter); 932 if (ret) { 933 dev_info(&adapter->pdev->dev, 934 "%s: Waiting for reset ACK\n", __func__); 935 return -1; 936 } 937 } 938 939 /* Transit to INIT state and restart the HW */ 940 qlcnic_83xx_idc_enter_init_state(adapter, 1); 941 942 return ret; 943 } 944 945 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter) 946 { 947 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__); 948 return 0; 949 } 950 951 static void qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter) 952 { 953 struct qlcnic_hardware_context *ahw = adapter->ahw; 954 u32 val, owner; 955 956 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 957 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 958 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 959 if (ahw->pci_func == owner) { 960 qlcnic_83xx_stop_hw(adapter); 961 qlcnic_dump_fw(adapter); 962 } 963 } 964 965 netdev_warn(adapter->netdev, "%s: Reboot will be required to recover the adapter!!\n", 966 __func__); 967 clear_bit(__QLCNIC_RESETTING, &adapter->state); 968 ahw->idc.err_code = -EIO; 969 970 return; 971 } 972 973 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter) 974 { 975 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__); 976 return 0; 977 } 978 979 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter, 980 u32 state) 981 { 982 u32 cur, prev, next; 983 984 cur = adapter->ahw->idc.curr_state; 985 prev = adapter->ahw->idc.prev_state; 986 next = state; 987 988 if ((next < QLC_83XX_IDC_DEV_COLD) || 989 (next > QLC_83XX_IDC_DEV_QUISCENT)) { 990 dev_err(&adapter->pdev->dev, 991 "%s: curr %d, prev %d, next state %d is invalid\n", 992 __func__, cur, prev, state); 993 return 1; 994 } 995 996 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) && 997 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) { 998 if ((next != QLC_83XX_IDC_DEV_COLD) && 999 (next != QLC_83XX_IDC_DEV_READY)) { 1000 dev_err(&adapter->pdev->dev, 1001 "%s: failed, cur %d prev %d next %d\n", 1002 __func__, cur, prev, next); 1003 return 1; 1004 } 1005 } 1006 1007 if (next == QLC_83XX_IDC_DEV_INIT) { 1008 if ((prev != QLC_83XX_IDC_DEV_INIT) && 1009 (prev != QLC_83XX_IDC_DEV_COLD) && 1010 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) { 1011 dev_err(&adapter->pdev->dev, 1012 "%s: failed, cur %d prev %d next %d\n", 1013 __func__, cur, prev, next); 1014 return 1; 1015 } 1016 } 1017 1018 return 0; 1019 } 1020 1021 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter) 1022 { 1023 if (adapter->fhash.fnum) 1024 qlcnic_prune_lb_filters(adapter); 1025 } 1026 1027 /** 1028 * qlcnic_83xx_idc_poll_dev_state 1029 * 1030 * @work: kernel work queue structure used to schedule the function 1031 * 1032 * Poll device state periodically and perform state specific 1033 * actions defined by Inter Driver Communication (IDC) protocol. 1034 * 1035 * Returns: None 1036 * 1037 **/ 1038 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work) 1039 { 1040 struct qlcnic_adapter *adapter; 1041 u32 state; 1042 1043 adapter = container_of(work, struct qlcnic_adapter, fw_work.work); 1044 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1045 1046 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1047 qlcnic_83xx_idc_log_state_history(adapter); 1048 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1049 } else { 1050 adapter->ahw->idc.curr_state = state; 1051 } 1052 1053 switch (adapter->ahw->idc.curr_state) { 1054 case QLC_83XX_IDC_DEV_READY: 1055 qlcnic_83xx_idc_ready_state(adapter); 1056 break; 1057 case QLC_83XX_IDC_DEV_NEED_RESET: 1058 qlcnic_83xx_idc_need_reset_state(adapter); 1059 break; 1060 case QLC_83XX_IDC_DEV_NEED_QUISCENT: 1061 qlcnic_83xx_idc_need_quiesce_state(adapter); 1062 break; 1063 case QLC_83XX_IDC_DEV_FAILED: 1064 qlcnic_83xx_idc_failed_state(adapter); 1065 return; 1066 case QLC_83XX_IDC_DEV_INIT: 1067 qlcnic_83xx_idc_init_state(adapter); 1068 break; 1069 case QLC_83XX_IDC_DEV_QUISCENT: 1070 qlcnic_83xx_idc_quiesce_state(adapter); 1071 break; 1072 default: 1073 qlcnic_83xx_idc_unknown_state(adapter); 1074 return; 1075 } 1076 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state; 1077 qlcnic_83xx_periodic_tasks(adapter); 1078 1079 /* Re-schedule the function */ 1080 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status)) 1081 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 1082 adapter->ahw->idc.delay); 1083 } 1084 1085 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter) 1086 { 1087 u32 idc_params, val; 1088 1089 if (qlcnic_83xx_lockless_flash_read32(adapter, 1090 QLC_83XX_IDC_FLASH_PARAM_ADDR, 1091 (u8 *)&idc_params, 1)) { 1092 dev_info(&adapter->pdev->dev, 1093 "%s:failed to get IDC params from flash\n", __func__); 1094 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 1095 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 1096 } else { 1097 adapter->dev_init_timeo = idc_params & 0xFFFF; 1098 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF); 1099 } 1100 1101 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1102 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN; 1103 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 1104 adapter->ahw->idc.err_code = 0; 1105 adapter->ahw->idc.collect_dump = 0; 1106 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states; 1107 1108 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1109 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1110 1111 /* Check if reset recovery is disabled */ 1112 if (!qlcnic_auto_fw_reset) { 1113 /* Propagate do not reset request to other functions */ 1114 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1115 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1116 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1117 } 1118 } 1119 1120 static int 1121 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter) 1122 { 1123 u32 state, val; 1124 1125 if (qlcnic_83xx_lock_driver(adapter)) 1126 return -EIO; 1127 1128 /* Clear driver lock register */ 1129 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0); 1130 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) { 1131 qlcnic_83xx_unlock_driver(adapter); 1132 return -EIO; 1133 } 1134 1135 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1136 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1137 qlcnic_83xx_unlock_driver(adapter); 1138 return -EIO; 1139 } 1140 1141 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) { 1142 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 1143 QLC_83XX_IDC_DEV_COLD); 1144 state = QLC_83XX_IDC_DEV_COLD; 1145 } 1146 1147 adapter->ahw->idc.curr_state = state; 1148 /* First to load function should cold boot the device */ 1149 if (state == QLC_83XX_IDC_DEV_COLD) 1150 qlcnic_83xx_idc_cold_state_handler(adapter); 1151 1152 /* Check if reset recovery is enabled */ 1153 if (qlcnic_auto_fw_reset) { 1154 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1155 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1156 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1157 } 1158 1159 qlcnic_83xx_unlock_driver(adapter); 1160 1161 return 0; 1162 } 1163 1164 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter) 1165 { 1166 int ret = -EIO; 1167 1168 qlcnic_83xx_setup_idc_parameters(adapter); 1169 1170 if (qlcnic_83xx_get_reset_instruction_template(adapter)) 1171 return ret; 1172 1173 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) { 1174 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter)) 1175 return -EIO; 1176 } else { 1177 if (qlcnic_83xx_idc_check_major_version(adapter)) 1178 return -EIO; 1179 } 1180 1181 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 1182 1183 return 0; 1184 } 1185 1186 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter) 1187 { 1188 int id; 1189 u32 val; 1190 1191 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 1192 usleep_range(10000, 11000); 1193 1194 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1195 id = id & 0xFF; 1196 1197 if (id == adapter->portnum) { 1198 dev_err(&adapter->pdev->dev, 1199 "%s: wait for lock recovery.. %d\n", __func__, id); 1200 msleep(20); 1201 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1202 id = id & 0xFF; 1203 } 1204 1205 /* Clear driver presence bit */ 1206 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 1207 val = val & ~(1 << adapter->portnum); 1208 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 1209 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1210 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1211 1212 cancel_delayed_work_sync(&adapter->fw_work); 1213 } 1214 1215 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key) 1216 { 1217 u32 val; 1218 1219 if (qlcnic_sriov_vf_check(adapter)) 1220 return; 1221 1222 if (qlcnic_83xx_lock_driver(adapter)) { 1223 dev_err(&adapter->pdev->dev, 1224 "%s:failed, please retry\n", __func__); 1225 return; 1226 } 1227 1228 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1229 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 1230 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 1231 __func__); 1232 qlcnic_83xx_idc_enter_failed_state(adapter, 0); 1233 qlcnic_83xx_unlock_driver(adapter); 1234 return; 1235 } 1236 1237 if (key == QLCNIC_FORCE_FW_RESET) { 1238 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1239 val = val | QLC_83XX_IDC_GRACEFULL_RESET; 1240 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1241 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) { 1242 adapter->ahw->idc.collect_dump = 1; 1243 } 1244 1245 qlcnic_83xx_unlock_driver(adapter); 1246 return; 1247 } 1248 1249 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter) 1250 { 1251 u8 *p_cache; 1252 u32 src, size; 1253 u64 dest; 1254 int ret = -EIO; 1255 1256 src = QLC_83XX_BOOTLOADER_FLASH_ADDR; 1257 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR); 1258 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE); 1259 1260 /* alignment check */ 1261 if (size & 0xF) 1262 size = (size + 16) & ~0xF; 1263 1264 p_cache = vzalloc(size); 1265 if (p_cache == NULL) 1266 return -ENOMEM; 1267 1268 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache, 1269 size / sizeof(u32)); 1270 if (ret) { 1271 vfree(p_cache); 1272 return ret; 1273 } 1274 /* 16 byte write to MS memory */ 1275 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache, 1276 size / 16); 1277 if (ret) { 1278 vfree(p_cache); 1279 return ret; 1280 } 1281 vfree(p_cache); 1282 1283 return ret; 1284 } 1285 1286 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter) 1287 { 1288 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info; 1289 const struct firmware *fw = fw_info->fw; 1290 u32 dest, *p_cache; 1291 int i, ret = -EIO; 1292 u8 data[16]; 1293 size_t size; 1294 u64 addr; 1295 1296 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR); 1297 size = (fw->size & ~0xF); 1298 p_cache = (u32 *)fw->data; 1299 addr = (u64)dest; 1300 1301 ret = qlcnic_83xx_ms_mem_write128(adapter, addr, 1302 (u32 *)p_cache, size / 16); 1303 if (ret) { 1304 dev_err(&adapter->pdev->dev, "MS memory write failed\n"); 1305 release_firmware(fw); 1306 fw_info->fw = NULL; 1307 return -EIO; 1308 } 1309 1310 /* alignment check */ 1311 if (fw->size & 0xF) { 1312 addr = dest + size; 1313 for (i = 0; i < (fw->size & 0xF); i++) 1314 data[i] = fw->data[size + i]; 1315 for (; i < 16; i++) 1316 data[i] = 0; 1317 ret = qlcnic_83xx_ms_mem_write128(adapter, addr, 1318 (u32 *)data, 1); 1319 if (ret) { 1320 dev_err(&adapter->pdev->dev, 1321 "MS memory write failed\n"); 1322 release_firmware(fw); 1323 fw_info->fw = NULL; 1324 return -EIO; 1325 } 1326 } 1327 release_firmware(fw); 1328 fw_info->fw = NULL; 1329 1330 return 0; 1331 } 1332 1333 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) 1334 { 1335 int i, j; 1336 u32 val = 0, val1 = 0, reg = 0; 1337 int err = 0; 1338 1339 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err); 1340 if (err == -EIO) 1341 return; 1342 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val); 1343 1344 for (j = 0; j < 2; j++) { 1345 if (j == 0) { 1346 dev_info(&adapter->pdev->dev, 1347 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:"); 1348 reg = QLC_83XX_PORT0_THRESHOLD; 1349 } else if (j == 1) { 1350 dev_info(&adapter->pdev->dev, 1351 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:"); 1352 reg = QLC_83XX_PORT1_THRESHOLD; 1353 } 1354 for (i = 0; i < 8; i++) { 1355 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1356 if (err == -EIO) 1357 return; 1358 dev_info(&adapter->pdev->dev, "0x%x ", val); 1359 } 1360 dev_info(&adapter->pdev->dev, "\n"); 1361 } 1362 1363 for (j = 0; j < 2; j++) { 1364 if (j == 0) { 1365 dev_info(&adapter->pdev->dev, 1366 "Port 0 RxB TC Max Cell Registers[4..1]:"); 1367 reg = QLC_83XX_PORT0_TC_MC_REG; 1368 } else if (j == 1) { 1369 dev_info(&adapter->pdev->dev, 1370 "Port 1 RxB TC Max Cell Registers[4..1]:"); 1371 reg = QLC_83XX_PORT1_TC_MC_REG; 1372 } 1373 for (i = 0; i < 4; i++) { 1374 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1375 if (err == -EIO) 1376 return; 1377 dev_info(&adapter->pdev->dev, "0x%x ", val); 1378 } 1379 dev_info(&adapter->pdev->dev, "\n"); 1380 } 1381 1382 for (j = 0; j < 2; j++) { 1383 if (j == 0) { 1384 dev_info(&adapter->pdev->dev, 1385 "Port 0 RxB Rx TC Stats[TC7..TC0]:"); 1386 reg = QLC_83XX_PORT0_TC_STATS; 1387 } else if (j == 1) { 1388 dev_info(&adapter->pdev->dev, 1389 "Port 1 RxB Rx TC Stats[TC7..TC0]:"); 1390 reg = QLC_83XX_PORT1_TC_STATS; 1391 } 1392 for (i = 7; i >= 0; i--) { 1393 val = QLCRD32(adapter, reg, &err); 1394 if (err == -EIO) 1395 return; 1396 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ 1397 QLCWR32(adapter, reg, (val | (i << 29))); 1398 val = QLCRD32(adapter, reg, &err); 1399 if (err == -EIO) 1400 return; 1401 dev_info(&adapter->pdev->dev, "0x%x ", val); 1402 } 1403 dev_info(&adapter->pdev->dev, "\n"); 1404 } 1405 1406 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err); 1407 if (err == -EIO) 1408 return; 1409 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err); 1410 if (err == -EIO) 1411 return; 1412 dev_info(&adapter->pdev->dev, 1413 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n", 1414 val, val1); 1415 } 1416 1417 1418 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter) 1419 { 1420 u32 reg = 0, i, j; 1421 1422 if (qlcnic_83xx_lock_driver(adapter)) { 1423 dev_err(&adapter->pdev->dev, 1424 "%s:failed to acquire driver lock\n", __func__); 1425 return; 1426 } 1427 1428 qlcnic_83xx_dump_pause_control_regs(adapter); 1429 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0); 1430 1431 for (j = 0; j < 2; j++) { 1432 if (j == 0) 1433 reg = QLC_83XX_PORT0_THRESHOLD; 1434 else if (j == 1) 1435 reg = QLC_83XX_PORT1_THRESHOLD; 1436 1437 for (i = 0; i < 8; i++) 1438 QLCWR32(adapter, reg + (i * 0x4), 0x0); 1439 } 1440 1441 for (j = 0; j < 2; j++) { 1442 if (j == 0) 1443 reg = QLC_83XX_PORT0_TC_MC_REG; 1444 else if (j == 1) 1445 reg = QLC_83XX_PORT1_TC_MC_REG; 1446 1447 for (i = 0; i < 4; i++) 1448 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF); 1449 } 1450 1451 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0); 1452 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0); 1453 dev_info(&adapter->pdev->dev, 1454 "Disabled pause frames successfully on all ports\n"); 1455 qlcnic_83xx_unlock_driver(adapter); 1456 } 1457 1458 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter) 1459 { 1460 QLCWR32(adapter, QLC_83XX_RESET_REG, 0); 1461 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0); 1462 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0); 1463 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0); 1464 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0); 1465 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0); 1466 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0); 1467 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0); 1468 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1); 1469 } 1470 1471 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev) 1472 { 1473 u32 heartbeat, peg_status; 1474 int retries, ret = -EIO, err = 0; 1475 1476 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT; 1477 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev, 1478 QLCNIC_PEG_ALIVE_COUNTER); 1479 1480 do { 1481 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS); 1482 heartbeat = QLC_SHARED_REG_RD32(p_dev, 1483 QLCNIC_PEG_ALIVE_COUNTER); 1484 if (heartbeat != p_dev->heartbeat) { 1485 ret = QLCNIC_RCODE_SUCCESS; 1486 break; 1487 } 1488 } while (--retries); 1489 1490 if (ret) { 1491 dev_err(&p_dev->pdev->dev, "firmware hang detected\n"); 1492 qlcnic_83xx_take_eport_out_of_reset(p_dev); 1493 qlcnic_83xx_disable_pause_frames(p_dev); 1494 peg_status = QLC_SHARED_REG_RD32(p_dev, 1495 QLCNIC_PEG_HALT_STATUS1); 1496 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n" 1497 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n" 1498 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n" 1499 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n" 1500 "PEG_NET_4_PC: 0x%x\n", peg_status, 1501 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2), 1502 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err), 1503 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err), 1504 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err), 1505 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err), 1506 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err)); 1507 1508 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67) 1509 dev_err(&p_dev->pdev->dev, 1510 "Device is being reset err code 0x00006700.\n"); 1511 } 1512 1513 return ret; 1514 } 1515 1516 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev) 1517 { 1518 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT; 1519 u32 val; 1520 1521 do { 1522 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE); 1523 if (val == QLC_83XX_CMDPEG_COMPLETE) 1524 return 0; 1525 msleep(QLCNIC_CMDPEG_CHECK_DELAY); 1526 } while (--retries); 1527 1528 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val); 1529 return -EIO; 1530 } 1531 1532 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev) 1533 { 1534 int err; 1535 1536 err = qlcnic_83xx_check_cmd_peg_status(p_dev); 1537 if (err) 1538 return err; 1539 1540 err = qlcnic_83xx_check_heartbeat(p_dev); 1541 if (err) 1542 return err; 1543 1544 return err; 1545 } 1546 1547 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr, 1548 int duration, u32 mask, u32 status) 1549 { 1550 int timeout_error, err = 0; 1551 u32 value; 1552 u8 retries; 1553 1554 value = QLCRD32(p_dev, addr, &err); 1555 if (err == -EIO) 1556 return err; 1557 retries = duration / 10; 1558 1559 do { 1560 if ((value & mask) != status) { 1561 timeout_error = 1; 1562 msleep(duration / 10); 1563 value = QLCRD32(p_dev, addr, &err); 1564 if (err == -EIO) 1565 return err; 1566 } else { 1567 timeout_error = 0; 1568 break; 1569 } 1570 } while (retries--); 1571 1572 if (timeout_error) { 1573 p_dev->ahw->reset.seq_error++; 1574 dev_err(&p_dev->pdev->dev, 1575 "%s: Timeout Err, entry_num = %d\n", 1576 __func__, p_dev->ahw->reset.seq_index); 1577 dev_err(&p_dev->pdev->dev, 1578 "0x%08x 0x%08x 0x%08x\n", 1579 value, mask, status); 1580 } 1581 1582 return timeout_error; 1583 } 1584 1585 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev) 1586 { 1587 u32 sum = 0; 1588 u16 *buff = (u16 *)p_dev->ahw->reset.buff; 1589 int count = p_dev->ahw->reset.hdr->size / sizeof(u16); 1590 1591 while (count-- > 0) 1592 sum += *buff++; 1593 1594 while (sum >> 16) 1595 sum = (sum & 0xFFFF) + (sum >> 16); 1596 1597 if (~sum) { 1598 return 0; 1599 } else { 1600 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1601 return -1; 1602 } 1603 } 1604 1605 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev) 1606 { 1607 struct qlcnic_hardware_context *ahw = p_dev->ahw; 1608 u32 addr, count, prev_ver, curr_ver; 1609 u8 *p_buff; 1610 1611 if (ahw->reset.buff != NULL) { 1612 prev_ver = p_dev->fw_version; 1613 curr_ver = qlcnic_83xx_get_fw_version(p_dev); 1614 if (curr_ver > prev_ver) 1615 kfree(ahw->reset.buff); 1616 else 1617 return 0; 1618 } 1619 1620 ahw->reset.seq_error = 0; 1621 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL); 1622 if (p_dev->ahw->reset.buff == NULL) 1623 return -ENOMEM; 1624 1625 p_buff = p_dev->ahw->reset.buff; 1626 addr = QLC_83XX_RESET_TEMPLATE_ADDR; 1627 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32); 1628 1629 /* Copy template header from flash */ 1630 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1631 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1632 return -EIO; 1633 } 1634 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff; 1635 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size; 1636 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1637 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32); 1638 1639 /* Copy rest of the template */ 1640 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1641 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1642 return -EIO; 1643 } 1644 1645 if (qlcnic_83xx_reset_template_checksum(p_dev)) 1646 return -EIO; 1647 /* Get Stop, Start and Init command offsets */ 1648 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset; 1649 ahw->reset.start_offset = ahw->reset.buff + 1650 ahw->reset.hdr->start_offset; 1651 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1652 return 0; 1653 } 1654 1655 /* Read Write HW register command */ 1656 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev, 1657 u32 raddr, u32 waddr) 1658 { 1659 int err = 0; 1660 u32 value; 1661 1662 value = QLCRD32(p_dev, raddr, &err); 1663 if (err == -EIO) 1664 return; 1665 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1666 } 1667 1668 /* Read Modify Write HW register command */ 1669 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev, 1670 u32 raddr, u32 waddr, 1671 struct qlc_83xx_rmw *p_rmw_hdr) 1672 { 1673 int err = 0; 1674 u32 value; 1675 1676 if (p_rmw_hdr->index_a) { 1677 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a]; 1678 } else { 1679 value = QLCRD32(p_dev, raddr, &err); 1680 if (err == -EIO) 1681 return; 1682 } 1683 1684 value &= p_rmw_hdr->mask; 1685 value <<= p_rmw_hdr->shl; 1686 value >>= p_rmw_hdr->shr; 1687 value |= p_rmw_hdr->or_value; 1688 value ^= p_rmw_hdr->xor_value; 1689 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1690 } 1691 1692 /* Write HW register command */ 1693 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev, 1694 struct qlc_83xx_entry_hdr *p_hdr) 1695 { 1696 int i; 1697 struct qlc_83xx_entry *entry; 1698 1699 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1700 sizeof(struct qlc_83xx_entry_hdr)); 1701 1702 for (i = 0; i < p_hdr->count; i++, entry++) { 1703 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1, 1704 entry->arg2); 1705 if (p_hdr->delay) 1706 udelay((u32)(p_hdr->delay)); 1707 } 1708 } 1709 1710 /* Read and Write instruction */ 1711 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev, 1712 struct qlc_83xx_entry_hdr *p_hdr) 1713 { 1714 int i; 1715 struct qlc_83xx_entry *entry; 1716 1717 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1718 sizeof(struct qlc_83xx_entry_hdr)); 1719 1720 for (i = 0; i < p_hdr->count; i++, entry++) { 1721 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1, 1722 entry->arg2); 1723 if (p_hdr->delay) 1724 udelay((u32)(p_hdr->delay)); 1725 } 1726 } 1727 1728 /* Poll HW register command */ 1729 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev, 1730 struct qlc_83xx_entry_hdr *p_hdr) 1731 { 1732 long delay; 1733 struct qlc_83xx_entry *entry; 1734 struct qlc_83xx_poll *poll; 1735 int i, err = 0; 1736 unsigned long arg1, arg2; 1737 1738 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1739 sizeof(struct qlc_83xx_entry_hdr)); 1740 1741 entry = (struct qlc_83xx_entry *)((char *)poll + 1742 sizeof(struct qlc_83xx_poll)); 1743 delay = (long)p_hdr->delay; 1744 1745 if (!delay) { 1746 for (i = 0; i < p_hdr->count; i++, entry++) 1747 qlcnic_83xx_poll_reg(p_dev, entry->arg1, 1748 delay, poll->mask, 1749 poll->status); 1750 } else { 1751 for (i = 0; i < p_hdr->count; i++, entry++) { 1752 arg1 = entry->arg1; 1753 arg2 = entry->arg2; 1754 if (delay) { 1755 if (qlcnic_83xx_poll_reg(p_dev, 1756 arg1, delay, 1757 poll->mask, 1758 poll->status)){ 1759 QLCRD32(p_dev, arg1, &err); 1760 if (err == -EIO) 1761 return; 1762 QLCRD32(p_dev, arg2, &err); 1763 if (err == -EIO) 1764 return; 1765 } 1766 } 1767 } 1768 } 1769 } 1770 1771 /* Poll and write HW register command */ 1772 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev, 1773 struct qlc_83xx_entry_hdr *p_hdr) 1774 { 1775 int i; 1776 long delay; 1777 struct qlc_83xx_quad_entry *entry; 1778 struct qlc_83xx_poll *poll; 1779 1780 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1781 sizeof(struct qlc_83xx_entry_hdr)); 1782 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1783 sizeof(struct qlc_83xx_poll)); 1784 delay = (long)p_hdr->delay; 1785 1786 for (i = 0; i < p_hdr->count; i++, entry++) { 1787 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr, 1788 entry->dr_value); 1789 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1790 entry->ar_value); 1791 if (delay) 1792 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1793 poll->mask, poll->status); 1794 } 1795 } 1796 1797 /* Read Modify Write register command */ 1798 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev, 1799 struct qlc_83xx_entry_hdr *p_hdr) 1800 { 1801 int i; 1802 struct qlc_83xx_entry *entry; 1803 struct qlc_83xx_rmw *rmw_hdr; 1804 1805 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr + 1806 sizeof(struct qlc_83xx_entry_hdr)); 1807 1808 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr + 1809 sizeof(struct qlc_83xx_rmw)); 1810 1811 for (i = 0; i < p_hdr->count; i++, entry++) { 1812 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1, 1813 entry->arg2, rmw_hdr); 1814 if (p_hdr->delay) 1815 udelay((u32)(p_hdr->delay)); 1816 } 1817 } 1818 1819 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr) 1820 { 1821 if (p_hdr->delay) 1822 mdelay((u32)((long)p_hdr->delay)); 1823 } 1824 1825 /* Read and poll register command */ 1826 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev, 1827 struct qlc_83xx_entry_hdr *p_hdr) 1828 { 1829 long delay; 1830 int index, i, j, err; 1831 struct qlc_83xx_quad_entry *entry; 1832 struct qlc_83xx_poll *poll; 1833 unsigned long addr; 1834 1835 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1836 sizeof(struct qlc_83xx_entry_hdr)); 1837 1838 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1839 sizeof(struct qlc_83xx_poll)); 1840 delay = (long)p_hdr->delay; 1841 1842 for (i = 0; i < p_hdr->count; i++, entry++) { 1843 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1844 entry->ar_value); 1845 if (delay) { 1846 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1847 poll->mask, poll->status)){ 1848 index = p_dev->ahw->reset.array_index; 1849 addr = entry->dr_addr; 1850 j = QLCRD32(p_dev, addr, &err); 1851 if (err == -EIO) 1852 return; 1853 1854 p_dev->ahw->reset.array[index++] = j; 1855 1856 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES) 1857 p_dev->ahw->reset.array_index = 1; 1858 } 1859 } 1860 } 1861 } 1862 1863 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev) 1864 { 1865 p_dev->ahw->reset.seq_end = 1; 1866 } 1867 1868 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev) 1869 { 1870 p_dev->ahw->reset.template_end = 1; 1871 if (p_dev->ahw->reset.seq_error == 0) 1872 dev_err(&p_dev->pdev->dev, 1873 "HW restart process completed successfully.\n"); 1874 else 1875 dev_err(&p_dev->pdev->dev, 1876 "HW restart completed with timeout errors.\n"); 1877 } 1878 1879 /** 1880 * qlcnic_83xx_exec_template_cmd 1881 * 1882 * @p_dev: adapter structure 1883 * @p_buff: Poiter to instruction template 1884 * 1885 * Template provides instructions to stop, restart and initalize firmware. 1886 * These instructions are abstracted as a series of read, write and 1887 * poll operations on hardware registers. Register information and operation 1888 * specifics are not exposed to the driver. Driver reads the template from 1889 * flash and executes the instructions located at pre-defined offsets. 1890 * 1891 * Returns: None 1892 * */ 1893 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev, 1894 char *p_buff) 1895 { 1896 int index, entries; 1897 struct qlc_83xx_entry_hdr *p_hdr; 1898 char *entry = p_buff; 1899 1900 p_dev->ahw->reset.seq_end = 0; 1901 p_dev->ahw->reset.template_end = 0; 1902 entries = p_dev->ahw->reset.hdr->entries; 1903 index = p_dev->ahw->reset.seq_index; 1904 1905 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) { 1906 p_hdr = (struct qlc_83xx_entry_hdr *)entry; 1907 1908 switch (p_hdr->cmd) { 1909 case QLC_83XX_OPCODE_NOP: 1910 break; 1911 case QLC_83XX_OPCODE_WRITE_LIST: 1912 qlcnic_83xx_write_list(p_dev, p_hdr); 1913 break; 1914 case QLC_83XX_OPCODE_READ_WRITE_LIST: 1915 qlcnic_83xx_read_write_list(p_dev, p_hdr); 1916 break; 1917 case QLC_83XX_OPCODE_POLL_LIST: 1918 qlcnic_83xx_poll_list(p_dev, p_hdr); 1919 break; 1920 case QLC_83XX_OPCODE_POLL_WRITE_LIST: 1921 qlcnic_83xx_poll_write_list(p_dev, p_hdr); 1922 break; 1923 case QLC_83XX_OPCODE_READ_MODIFY_WRITE: 1924 qlcnic_83xx_read_modify_write(p_dev, p_hdr); 1925 break; 1926 case QLC_83XX_OPCODE_SEQ_PAUSE: 1927 qlcnic_83xx_pause(p_hdr); 1928 break; 1929 case QLC_83XX_OPCODE_SEQ_END: 1930 qlcnic_83xx_seq_end(p_dev); 1931 break; 1932 case QLC_83XX_OPCODE_TMPL_END: 1933 qlcnic_83xx_template_end(p_dev); 1934 break; 1935 case QLC_83XX_OPCODE_POLL_READ_LIST: 1936 qlcnic_83xx_poll_read_list(p_dev, p_hdr); 1937 break; 1938 default: 1939 dev_err(&p_dev->pdev->dev, 1940 "%s: Unknown opcode 0x%04x in template %d\n", 1941 __func__, p_hdr->cmd, index); 1942 break; 1943 } 1944 entry += p_hdr->size; 1945 } 1946 p_dev->ahw->reset.seq_index = index; 1947 } 1948 1949 void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev) 1950 { 1951 p_dev->ahw->reset.seq_index = 0; 1952 1953 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset); 1954 if (p_dev->ahw->reset.seq_end != 1) 1955 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1956 } 1957 1958 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev) 1959 { 1960 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset); 1961 if (p_dev->ahw->reset.template_end != 1) 1962 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1963 } 1964 1965 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev) 1966 { 1967 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset); 1968 if (p_dev->ahw->reset.seq_end != 1) 1969 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1970 } 1971 1972 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter) 1973 { 1974 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info; 1975 int err = -EIO; 1976 1977 if (request_firmware(&fw_info->fw, fw_info->fw_file_name, 1978 &(adapter->pdev->dev))) { 1979 dev_err(&adapter->pdev->dev, 1980 "No file FW image, loading flash FW image.\n"); 1981 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1982 QLC_83XX_BOOT_FROM_FLASH); 1983 } else { 1984 if (qlcnic_83xx_copy_fw_file(adapter)) 1985 return err; 1986 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1987 QLC_83XX_BOOT_FROM_FILE); 1988 } 1989 1990 return 0; 1991 } 1992 1993 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter) 1994 { 1995 u32 val; 1996 int err = -EIO; 1997 1998 qlcnic_83xx_stop_hw(adapter); 1999 2000 /* Collect FW register dump if required */ 2001 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 2002 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET)) 2003 qlcnic_dump_fw(adapter); 2004 2005 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 2006 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 2007 __func__); 2008 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 2009 return err; 2010 } 2011 2012 qlcnic_83xx_init_hw(adapter); 2013 2014 if (qlcnic_83xx_copy_bootloader(adapter)) 2015 return err; 2016 /* Boot either flash image or firmware image from host file system */ 2017 if (qlcnic_load_fw_file) { 2018 if (qlcnic_83xx_load_fw_image_from_host(adapter)) 2019 return err; 2020 } else { 2021 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 2022 QLC_83XX_BOOT_FROM_FLASH); 2023 } 2024 2025 qlcnic_83xx_start_hw(adapter); 2026 if (qlcnic_83xx_check_hw_status(adapter)) 2027 return -EIO; 2028 2029 return 0; 2030 } 2031 2032 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter) 2033 { 2034 int err; 2035 struct qlcnic_info nic_info; 2036 struct qlcnic_hardware_context *ahw = adapter->ahw; 2037 2038 memset(&nic_info, 0, sizeof(struct qlcnic_info)); 2039 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func); 2040 if (err) 2041 return -EIO; 2042 2043 ahw->physical_port = (u8) nic_info.phys_port; 2044 ahw->switch_mode = nic_info.switch_mode; 2045 ahw->max_tx_ques = nic_info.max_tx_ques; 2046 ahw->max_rx_ques = nic_info.max_rx_ques; 2047 ahw->capabilities = nic_info.capabilities; 2048 ahw->max_mac_filters = nic_info.max_mac_filters; 2049 ahw->max_mtu = nic_info.max_mtu; 2050 2051 adapter->max_tx_rings = ahw->max_tx_ques; 2052 adapter->max_sds_rings = ahw->max_rx_ques; 2053 /* eSwitch capability indicates vNIC mode. 2054 * vNIC and SRIOV are mutually exclusive operational modes. 2055 * If SR-IOV capability is detected, SR-IOV physical function 2056 * will get initialized in default mode. 2057 * SR-IOV virtual function initialization follows a 2058 * different code path and opmode. 2059 * SRIOV mode has precedence over vNIC mode. 2060 */ 2061 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) 2062 return QLC_83XX_DEFAULT_OPMODE; 2063 2064 if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY) 2065 return QLCNIC_VNIC_MODE; 2066 2067 return QLC_83XX_DEFAULT_OPMODE; 2068 } 2069 2070 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter) 2071 { 2072 struct qlcnic_hardware_context *ahw = adapter->ahw; 2073 int ret; 2074 2075 ret = qlcnic_83xx_get_nic_configuration(adapter); 2076 if (ret == -EIO) 2077 return -EIO; 2078 2079 if (ret == QLCNIC_VNIC_MODE) { 2080 ahw->nic_mode = QLCNIC_VNIC_MODE; 2081 2082 if (qlcnic_83xx_config_vnic_opmode(adapter)) 2083 return -EIO; 2084 2085 adapter->max_sds_rings = QLCNIC_MAX_VNIC_SDS_RINGS; 2086 adapter->max_tx_rings = QLCNIC_MAX_VNIC_TX_RINGS; 2087 } else if (ret == QLC_83XX_DEFAULT_OPMODE) { 2088 ahw->nic_mode = QLCNIC_DEFAULT_MODE; 2089 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver; 2090 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry; 2091 adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS; 2092 adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS; 2093 } else { 2094 return -EIO; 2095 } 2096 2097 return 0; 2098 } 2099 2100 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter) 2101 { 2102 struct qlcnic_hardware_context *ahw = adapter->ahw; 2103 2104 if (ahw->port_type == QLCNIC_XGBE) { 2105 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G; 2106 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G; 2107 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2108 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2109 2110 } else if (ahw->port_type == QLCNIC_GBE) { 2111 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G; 2112 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2113 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2114 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G; 2115 } 2116 adapter->num_txd = MAX_CMD_DESCRIPTORS; 2117 adapter->max_rds_rings = MAX_RDS_RINGS; 2118 } 2119 2120 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter) 2121 { 2122 int err = -EIO; 2123 2124 qlcnic_83xx_get_minidump_template(adapter); 2125 if (qlcnic_83xx_get_port_info(adapter)) 2126 return err; 2127 2128 qlcnic_83xx_config_buff_descriptors(adapter); 2129 adapter->ahw->msix_supported = !!qlcnic_use_msi_x; 2130 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED; 2131 2132 dev_info(&adapter->pdev->dev, "HAL Version: %d\n", 2133 adapter->ahw->fw_hal_version); 2134 2135 return 0; 2136 } 2137 2138 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1)) 2139 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter) 2140 { 2141 struct qlcnic_cmd_args cmd; 2142 u32 presence_mask, audit_mask; 2143 int status; 2144 2145 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 2146 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 2147 2148 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) { 2149 status = qlcnic_alloc_mbx_args(&cmd, adapter, 2150 QLCNIC_CMD_STOP_NIC_FUNC); 2151 if (status) 2152 return; 2153 2154 cmd.req.arg[1] = BIT_31; 2155 status = qlcnic_issue_cmd(adapter, &cmd); 2156 if (status) 2157 dev_err(&adapter->pdev->dev, 2158 "Failed to clean up the function resources\n"); 2159 qlcnic_free_mbx_args(&cmd); 2160 } 2161 } 2162 2163 static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter) 2164 { 2165 struct qlcnic_hardware_context *ahw = adapter->ahw; 2166 struct pci_dev *pdev = adapter->pdev; 2167 struct qlc_83xx_fw_info *fw_info; 2168 int err = 0; 2169 2170 ahw->fw_info = kzalloc(sizeof(*fw_info), GFP_KERNEL); 2171 if (!ahw->fw_info) { 2172 err = -ENOMEM; 2173 } else { 2174 fw_info = ahw->fw_info; 2175 switch (pdev->device) { 2176 case PCI_DEVICE_ID_QLOGIC_QLE834X: 2177 strncpy(fw_info->fw_file_name, QLC_83XX_FW_FILE_NAME, 2178 QLC_FW_FILE_NAME_LEN); 2179 break; 2180 case PCI_DEVICE_ID_QLOGIC_QLE844X: 2181 strncpy(fw_info->fw_file_name, QLC_84XX_FW_FILE_NAME, 2182 QLC_FW_FILE_NAME_LEN); 2183 break; 2184 default: 2185 dev_err(&pdev->dev, "%s: Invalid device id\n", 2186 __func__); 2187 err = -EINVAL; 2188 break; 2189 } 2190 } 2191 2192 return err; 2193 } 2194 2195 static void qlcnic_83xx_init_rings(struct qlcnic_adapter *adapter) 2196 { 2197 u8 rx_cnt = QLCNIC_DEF_SDS_RINGS; 2198 u8 tx_cnt = QLCNIC_DEF_TX_RINGS; 2199 2200 adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS; 2201 adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS; 2202 2203 if (!adapter->ahw->msix_supported) { 2204 rx_cnt = QLCNIC_SINGLE_RING; 2205 tx_cnt = QLCNIC_SINGLE_RING; 2206 } 2207 2208 /* compute and set drv sds rings */ 2209 qlcnic_set_tx_ring_count(adapter, tx_cnt); 2210 qlcnic_set_sds_ring_count(adapter, rx_cnt); 2211 } 2212 2213 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac) 2214 { 2215 struct qlcnic_hardware_context *ahw = adapter->ahw; 2216 struct qlcnic_dcb *dcb; 2217 int err = 0; 2218 2219 ahw->msix_supported = !!qlcnic_use_msi_x; 2220 2221 qlcnic_83xx_init_rings(adapter); 2222 2223 err = qlcnic_83xx_init_mailbox_work(adapter); 2224 if (err) 2225 goto exit; 2226 2227 if (qlcnic_sriov_vf_check(adapter)) { 2228 err = qlcnic_sriov_vf_init(adapter, pci_using_dac); 2229 if (err) 2230 goto detach_mbx; 2231 else 2232 return err; 2233 } 2234 2235 if (qlcnic_83xx_read_flash_descriptor_table(adapter) || 2236 qlcnic_83xx_read_flash_mfg_id(adapter)) { 2237 dev_err(&adapter->pdev->dev, "Failed reading flash mfg id\n"); 2238 err = -ENOTRECOVERABLE; 2239 goto detach_mbx; 2240 } 2241 2242 err = qlcnic_83xx_check_hw_status(adapter); 2243 if (err) 2244 goto detach_mbx; 2245 2246 err = qlcnic_83xx_get_fw_info(adapter); 2247 if (err) 2248 goto detach_mbx; 2249 2250 err = qlcnic_83xx_idc_init(adapter); 2251 if (err) 2252 goto detach_mbx; 2253 2254 err = qlcnic_setup_intr(adapter); 2255 if (err) { 2256 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n"); 2257 goto disable_intr; 2258 } 2259 2260 err = qlcnic_83xx_setup_mbx_intr(adapter); 2261 if (err) 2262 goto disable_mbx_intr; 2263 2264 qlcnic_83xx_clear_function_resources(adapter); 2265 2266 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work); 2267 2268 /* register for NIC IDC AEN Events */ 2269 qlcnic_83xx_register_nic_idc_func(adapter, 1); 2270 2271 /* Configure default, SR-IOV or Virtual NIC mode of operation */ 2272 err = qlcnic_83xx_configure_opmode(adapter); 2273 if (err) 2274 goto disable_mbx_intr; 2275 2276 2277 /* Perform operating mode specific initialization */ 2278 err = adapter->nic_ops->init_driver(adapter); 2279 if (err) 2280 goto disable_mbx_intr; 2281 2282 dcb = adapter->dcb; 2283 2284 if (dcb && qlcnic_dcb_attach(dcb)) 2285 qlcnic_clear_dcb_ops(dcb); 2286 2287 /* Periodically monitor device status */ 2288 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work); 2289 return 0; 2290 2291 disable_mbx_intr: 2292 qlcnic_83xx_free_mbx_intr(adapter); 2293 2294 disable_intr: 2295 qlcnic_teardown_intr(adapter); 2296 2297 detach_mbx: 2298 qlcnic_83xx_detach_mailbox_work(adapter); 2299 qlcnic_83xx_free_mailbox(ahw->mailbox); 2300 ahw->mailbox = NULL; 2301 exit: 2302 return err; 2303 } 2304 2305 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *adapter) 2306 { 2307 struct qlcnic_hardware_context *ahw = adapter->ahw; 2308 struct qlc_83xx_idc *idc = &ahw->idc; 2309 2310 clear_bit(QLC_83XX_MBX_READY, &idc->status); 2311 cancel_delayed_work_sync(&adapter->fw_work); 2312 2313 if (ahw->nic_mode == QLCNIC_VNIC_MODE) 2314 qlcnic_83xx_disable_vnic_mode(adapter, 1); 2315 2316 qlcnic_83xx_idc_detach_driver(adapter); 2317 qlcnic_83xx_register_nic_idc_func(adapter, 0); 2318 2319 cancel_delayed_work_sync(&adapter->idc_aen_work); 2320 } 2321 2322 int qlcnic_83xx_aer_reset(struct qlcnic_adapter *adapter) 2323 { 2324 struct qlcnic_hardware_context *ahw = adapter->ahw; 2325 struct qlc_83xx_idc *idc = &ahw->idc; 2326 int ret = 0; 2327 u32 owner; 2328 2329 /* Mark the previous IDC state as NEED_RESET so 2330 * that state_entry() will perform the reattachment 2331 * and bringup the device 2332 */ 2333 idc->prev_state = QLC_83XX_IDC_DEV_NEED_RESET; 2334 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 2335 if (ahw->pci_func == owner) { 2336 ret = qlcnic_83xx_restart_hw(adapter); 2337 if (ret < 0) 2338 return ret; 2339 qlcnic_83xx_idc_clear_registers(adapter, 0); 2340 } 2341 2342 ret = idc->state_entry(adapter); 2343 return ret; 2344 } 2345 2346 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *adapter) 2347 { 2348 struct qlcnic_hardware_context *ahw = adapter->ahw; 2349 struct qlc_83xx_idc *idc = &ahw->idc; 2350 u32 owner; 2351 2352 idc->prev_state = QLC_83XX_IDC_DEV_READY; 2353 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 2354 if (ahw->pci_func == owner) 2355 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 2356 2357 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 0); 2358 } 2359