1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #include "qlcnic_sriov.h" 9 #include "qlcnic.h" 10 #include "qlcnic_hw.h" 11 12 /* Reset template definitions */ 13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000 14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000 15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101 16 17 #define QLC_83XX_OPCODE_NOP 0x0000 18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001 19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002 20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004 21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008 22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010 23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020 24 #define QLC_83XX_OPCODE_SEQ_END 0x0040 25 #define QLC_83XX_OPCODE_TMPL_END 0x0080 26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100 27 28 /* EPORT control registers */ 29 #define QLC_83XX_RESET_CONTROL 0x28084E50 30 #define QLC_83XX_RESET_REG 0x28084E60 31 #define QLC_83XX_RESET_PORT0 0x28084E70 32 #define QLC_83XX_RESET_PORT1 0x28084E80 33 #define QLC_83XX_RESET_PORT2 0x28084E90 34 #define QLC_83XX_RESET_PORT3 0x28084EA0 35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0 36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0 37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0 38 39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter); 40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev); 41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter); 42 43 /* Template header */ 44 struct qlc_83xx_reset_hdr { 45 #if defined(__LITTLE_ENDIAN) 46 u16 version; 47 u16 signature; 48 u16 size; 49 u16 entries; 50 u16 hdr_size; 51 u16 checksum; 52 u16 init_offset; 53 u16 start_offset; 54 #elif defined(__BIG_ENDIAN) 55 u16 signature; 56 u16 version; 57 u16 entries; 58 u16 size; 59 u16 checksum; 60 u16 hdr_size; 61 u16 start_offset; 62 u16 init_offset; 63 #endif 64 } __packed; 65 66 /* Command entry header. */ 67 struct qlc_83xx_entry_hdr { 68 #if defined(__LITTLE_ENDIAN) 69 u16 cmd; 70 u16 size; 71 u16 count; 72 u16 delay; 73 #elif defined(__BIG_ENDIAN) 74 u16 size; 75 u16 cmd; 76 u16 delay; 77 u16 count; 78 #endif 79 } __packed; 80 81 /* Generic poll command */ 82 struct qlc_83xx_poll { 83 u32 mask; 84 u32 status; 85 } __packed; 86 87 /* Read modify write command */ 88 struct qlc_83xx_rmw { 89 u32 mask; 90 u32 xor_value; 91 u32 or_value; 92 #if defined(__LITTLE_ENDIAN) 93 u8 shl; 94 u8 shr; 95 u8 index_a; 96 u8 rsvd; 97 #elif defined(__BIG_ENDIAN) 98 u8 rsvd; 99 u8 index_a; 100 u8 shr; 101 u8 shl; 102 #endif 103 } __packed; 104 105 /* Generic command with 2 DWORD */ 106 struct qlc_83xx_entry { 107 u32 arg1; 108 u32 arg2; 109 } __packed; 110 111 /* Generic command with 4 DWORD */ 112 struct qlc_83xx_quad_entry { 113 u32 dr_addr; 114 u32 dr_value; 115 u32 ar_addr; 116 u32 ar_value; 117 } __packed; 118 static const char *const qlc_83xx_idc_states[] = { 119 "Unknown", 120 "Cold", 121 "Init", 122 "Ready", 123 "Need Reset", 124 "Need Quiesce", 125 "Failed", 126 "Quiesce" 127 }; 128 129 static int 130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter) 131 { 132 u32 val; 133 134 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 135 if ((val & 0xFFFF)) 136 return 1; 137 else 138 return 0; 139 } 140 141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter) 142 { 143 u32 cur, prev; 144 cur = adapter->ahw->idc.curr_state; 145 prev = adapter->ahw->idc.prev_state; 146 147 dev_info(&adapter->pdev->dev, 148 "current state = %s, prev state = %s\n", 149 adapter->ahw->idc.name[cur], 150 adapter->ahw->idc.name[prev]); 151 } 152 153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter, 154 u8 mode, int lock) 155 { 156 u32 val; 157 int seconds; 158 159 if (lock) { 160 if (qlcnic_83xx_lock_driver(adapter)) 161 return -EBUSY; 162 } 163 164 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 165 val |= (adapter->portnum & 0xf); 166 val |= mode << 7; 167 if (mode) 168 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 169 else 170 seconds = jiffies / HZ; 171 172 val |= seconds << 8; 173 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val); 174 adapter->ahw->idc.sec_counter = jiffies / HZ; 175 176 if (lock) 177 qlcnic_83xx_unlock_driver(adapter); 178 179 return 0; 180 } 181 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter) 183 { 184 u32 val; 185 186 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION); 187 val = val & ~(0x3 << (adapter->portnum * 2)); 188 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2)); 189 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val); 190 } 191 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter, 193 int lock) 194 { 195 u32 val; 196 197 if (lock) { 198 if (qlcnic_83xx_lock_driver(adapter)) 199 return -EBUSY; 200 } 201 202 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 203 val = val & ~0xFF; 204 val = val | QLC_83XX_IDC_MAJOR_VERSION; 205 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val); 206 207 if (lock) 208 qlcnic_83xx_unlock_driver(adapter); 209 210 return 0; 211 } 212 213 static int 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter, 215 int status, int lock) 216 { 217 u32 val; 218 219 if (lock) { 220 if (qlcnic_83xx_lock_driver(adapter)) 221 return -EBUSY; 222 } 223 224 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 225 226 if (status) 227 val = val | (1 << adapter->portnum); 228 else 229 val = val & ~(1 << adapter->portnum); 230 231 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 232 qlcnic_83xx_idc_update_minor_version(adapter); 233 234 if (lock) 235 qlcnic_83xx_unlock_driver(adapter); 236 237 return 0; 238 } 239 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter) 241 { 242 u32 val; 243 u8 version; 244 245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 246 version = val & 0xFF; 247 248 if (version != QLC_83XX_IDC_MAJOR_VERSION) { 249 dev_info(&adapter->pdev->dev, 250 "%s:mismatch. version 0x%x, expected version 0x%x\n", 251 __func__, version, QLC_83XX_IDC_MAJOR_VERSION); 252 return -EIO; 253 } 254 255 return 0; 256 } 257 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter, 259 int lock) 260 { 261 u32 val; 262 263 if (lock) { 264 if (qlcnic_83xx_lock_driver(adapter)) 265 return -EBUSY; 266 } 267 268 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0); 269 /* Clear gracefull reset bit */ 270 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 271 val &= ~QLC_83XX_IDC_GRACEFULL_RESET; 272 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 273 274 if (lock) 275 qlcnic_83xx_unlock_driver(adapter); 276 277 return 0; 278 } 279 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter, 281 int flag, int lock) 282 { 283 u32 val; 284 285 if (lock) { 286 if (qlcnic_83xx_lock_driver(adapter)) 287 return -EBUSY; 288 } 289 290 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 291 if (flag) 292 val = val | (1 << adapter->portnum); 293 else 294 val = val & ~(1 << adapter->portnum); 295 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val); 296 297 if (lock) 298 qlcnic_83xx_unlock_driver(adapter); 299 300 return 0; 301 } 302 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter, 304 int time_limit) 305 { 306 u64 seconds; 307 308 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 309 if (seconds <= time_limit) 310 return 0; 311 else 312 return -EBUSY; 313 } 314 315 /** 316 * qlcnic_83xx_idc_check_reset_ack_reg 317 * 318 * @adapter: adapter structure 319 * 320 * Check ACK wait limit and clear the functions which failed to ACK 321 * 322 * Return 0 if all functions have acknowledged the reset request. 323 **/ 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter) 325 { 326 int timeout; 327 u32 ack, presence, val; 328 329 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 330 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 331 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 332 dev_info(&adapter->pdev->dev, 333 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence); 334 if (!((ack & presence) == presence)) { 335 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) { 336 /* Clear functions which failed to ACK */ 337 dev_info(&adapter->pdev->dev, 338 "%s: ACK wait exceeds time limit\n", __func__); 339 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 340 val = val & ~(ack ^ presence); 341 if (qlcnic_83xx_lock_driver(adapter)) 342 return -EBUSY; 343 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 344 dev_info(&adapter->pdev->dev, 345 "%s: updated drv presence reg = 0x%x\n", 346 __func__, val); 347 qlcnic_83xx_unlock_driver(adapter); 348 return 0; 349 350 } else { 351 return 1; 352 } 353 } else { 354 dev_info(&adapter->pdev->dev, 355 "%s: Reset ACK received from all functions\n", 356 __func__); 357 return 0; 358 } 359 } 360 361 /** 362 * qlcnic_83xx_idc_tx_soft_reset 363 * 364 * @adapter: adapter structure 365 * 366 * Handle context deletion and recreation request from transmit routine 367 * 368 * Returns -EBUSY or Success (0) 369 * 370 **/ 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter) 372 { 373 struct net_device *netdev = adapter->netdev; 374 375 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 376 return -EBUSY; 377 378 netif_device_detach(netdev); 379 qlcnic_down(adapter, netdev); 380 qlcnic_up(adapter, netdev); 381 netif_device_attach(netdev); 382 clear_bit(__QLCNIC_RESETTING, &adapter->state); 383 dev_err(&adapter->pdev->dev, "%s:\n", __func__); 384 385 return 0; 386 } 387 388 /** 389 * qlcnic_83xx_idc_detach_driver 390 * 391 * @adapter: adapter structure 392 * Detach net interface, stop TX and cleanup resources before the HW reset. 393 * Returns: None 394 * 395 **/ 396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter) 397 { 398 int i; 399 struct net_device *netdev = adapter->netdev; 400 401 netif_device_detach(netdev); 402 403 /* Disable mailbox interrupt */ 404 qlcnic_83xx_disable_mbx_intr(adapter); 405 qlcnic_down(adapter, netdev); 406 for (i = 0; i < adapter->ahw->num_msix; i++) { 407 adapter->ahw->intr_tbl[i].id = i; 408 adapter->ahw->intr_tbl[i].enabled = 0; 409 adapter->ahw->intr_tbl[i].src = 0; 410 } 411 412 if (qlcnic_sriov_pf_check(adapter)) 413 qlcnic_sriov_pf_reset(adapter); 414 } 415 416 /** 417 * qlcnic_83xx_idc_attach_driver 418 * 419 * @adapter: adapter structure 420 * 421 * Re-attach and re-enable net interface 422 * Returns: None 423 * 424 **/ 425 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter) 426 { 427 struct net_device *netdev = adapter->netdev; 428 429 if (netif_running(netdev)) { 430 if (qlcnic_up(adapter, netdev)) 431 goto done; 432 qlcnic_restore_indev_addr(netdev, NETDEV_UP); 433 } 434 done: 435 netif_device_attach(netdev); 436 } 437 438 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter, 439 int lock) 440 { 441 if (lock) { 442 if (qlcnic_83xx_lock_driver(adapter)) 443 return -EBUSY; 444 } 445 446 qlcnic_83xx_idc_clear_registers(adapter, 0); 447 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED); 448 if (lock) 449 qlcnic_83xx_unlock_driver(adapter); 450 451 qlcnic_83xx_idc_log_state_history(adapter); 452 dev_info(&adapter->pdev->dev, "Device will enter failed state\n"); 453 454 return 0; 455 } 456 457 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter, 458 int lock) 459 { 460 if (lock) { 461 if (qlcnic_83xx_lock_driver(adapter)) 462 return -EBUSY; 463 } 464 465 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT); 466 467 if (lock) 468 qlcnic_83xx_unlock_driver(adapter); 469 470 return 0; 471 } 472 473 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter, 474 int lock) 475 { 476 if (lock) { 477 if (qlcnic_83xx_lock_driver(adapter)) 478 return -EBUSY; 479 } 480 481 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 482 QLC_83XX_IDC_DEV_NEED_QUISCENT); 483 484 if (lock) 485 qlcnic_83xx_unlock_driver(adapter); 486 487 return 0; 488 } 489 490 static int 491 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock) 492 { 493 if (lock) { 494 if (qlcnic_83xx_lock_driver(adapter)) 495 return -EBUSY; 496 } 497 498 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 499 QLC_83XX_IDC_DEV_NEED_RESET); 500 501 if (lock) 502 qlcnic_83xx_unlock_driver(adapter); 503 504 return 0; 505 } 506 507 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter, 508 int lock) 509 { 510 if (lock) { 511 if (qlcnic_83xx_lock_driver(adapter)) 512 return -EBUSY; 513 } 514 515 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY); 516 if (lock) 517 qlcnic_83xx_unlock_driver(adapter); 518 519 return 0; 520 } 521 522 /** 523 * qlcnic_83xx_idc_find_reset_owner_id 524 * 525 * @adapter: adapter structure 526 * 527 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE. 528 * Within the same class, function with lowest PCI ID assumes ownership 529 * 530 * Returns: reset owner id or failure indication (-EIO) 531 * 532 **/ 533 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter) 534 { 535 u32 reg, reg1, reg2, i, j, owner, class; 536 537 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1); 538 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2); 539 owner = QLCNIC_TYPE_NIC; 540 i = 0; 541 j = 0; 542 reg = reg1; 543 544 do { 545 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3); 546 if (class == owner) 547 break; 548 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) { 549 reg = reg2; 550 j = 0; 551 } else { 552 j++; 553 } 554 555 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) { 556 if (owner == QLCNIC_TYPE_NIC) 557 owner = QLCNIC_TYPE_ISCSI; 558 else if (owner == QLCNIC_TYPE_ISCSI) 559 owner = QLCNIC_TYPE_FCOE; 560 else if (owner == QLCNIC_TYPE_FCOE) 561 return -EIO; 562 reg = reg1; 563 j = 0; 564 i = 0; 565 } 566 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS); 567 568 return i; 569 } 570 571 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock) 572 { 573 int ret = 0; 574 575 ret = qlcnic_83xx_restart_hw(adapter); 576 577 if (ret) { 578 qlcnic_83xx_idc_enter_failed_state(adapter, lock); 579 } else { 580 qlcnic_83xx_idc_clear_registers(adapter, lock); 581 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock); 582 } 583 584 return ret; 585 } 586 587 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter) 588 { 589 u32 status; 590 591 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1); 592 593 if (status & QLCNIC_RCODE_FATAL_ERROR) { 594 dev_err(&adapter->pdev->dev, 595 "peg halt status1=0x%x\n", status); 596 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) { 597 dev_err(&adapter->pdev->dev, 598 "On board active cooling fan failed. " 599 "Device has been halted.\n"); 600 dev_err(&adapter->pdev->dev, 601 "Replace the adapter.\n"); 602 return -EIO; 603 } 604 } 605 606 return 0; 607 } 608 609 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter) 610 { 611 int err; 612 613 /* register for NIC IDC AEN Events */ 614 qlcnic_83xx_register_nic_idc_func(adapter, 1); 615 616 err = qlcnic_sriov_pf_reinit(adapter); 617 if (err) 618 return err; 619 620 qlcnic_83xx_enable_mbx_intrpt(adapter); 621 622 if (qlcnic_83xx_configure_opmode(adapter)) { 623 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 624 return -EIO; 625 } 626 627 if (adapter->nic_ops->init_driver(adapter)) { 628 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 629 return -EIO; 630 } 631 632 if (adapter->portnum == 0) 633 qlcnic_set_drv_version(adapter); 634 qlcnic_83xx_idc_attach_driver(adapter); 635 636 return 0; 637 } 638 639 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter) 640 { 641 struct qlcnic_hardware_context *ahw = adapter->ahw; 642 643 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1); 644 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); 645 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 646 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 647 648 ahw->idc.quiesce_req = 0; 649 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 650 ahw->idc.err_code = 0; 651 ahw->idc.collect_dump = 0; 652 ahw->reset_context = 0; 653 adapter->tx_timeo_cnt = 0; 654 ahw->idc.delay_reset = 0; 655 656 clear_bit(__QLCNIC_RESETTING, &adapter->state); 657 } 658 659 /** 660 * qlcnic_83xx_idc_ready_state_entry 661 * 662 * @adapter: adapter structure 663 * 664 * Perform ready state initialization, this routine will get invoked only 665 * once from READY state. 666 * 667 * Returns: Error code or Success(0) 668 * 669 **/ 670 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter) 671 { 672 struct qlcnic_hardware_context *ahw = adapter->ahw; 673 674 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) { 675 qlcnic_83xx_idc_update_idc_params(adapter); 676 /* Re-attach the device if required */ 677 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) || 678 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) { 679 if (qlcnic_83xx_idc_reattach_driver(adapter)) 680 return -EIO; 681 } 682 } 683 684 return 0; 685 } 686 687 /** 688 * qlcnic_83xx_idc_vnic_pf_entry 689 * 690 * @adapter: adapter structure 691 * 692 * Ensure vNIC mode privileged function starts only after vNIC mode is 693 * enabled by management function. 694 * If vNIC mode is ready, start initialization. 695 * 696 * Returns: -EIO or 0 697 * 698 **/ 699 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter) 700 { 701 u32 state; 702 struct qlcnic_hardware_context *ahw = adapter->ahw; 703 704 /* Privileged function waits till mgmt function enables VNIC mode */ 705 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE); 706 if (state != QLCNIC_DEV_NPAR_OPER) { 707 if (!ahw->idc.vnic_wait_limit--) { 708 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 709 return -EIO; 710 } 711 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n"); 712 return -EIO; 713 714 } else { 715 /* Perform one time initialization from ready state */ 716 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) { 717 qlcnic_83xx_idc_update_idc_params(adapter); 718 719 /* If the previous state is UNKNOWN, device will be 720 already attached properly by Init routine*/ 721 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) { 722 if (qlcnic_83xx_idc_reattach_driver(adapter)) 723 return -EIO; 724 } 725 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER; 726 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n"); 727 } 728 } 729 730 return 0; 731 } 732 733 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter) 734 { 735 adapter->ahw->idc.err_code = -EIO; 736 dev_err(&adapter->pdev->dev, 737 "%s: Device in unknown state\n", __func__); 738 return 0; 739 } 740 741 /** 742 * qlcnic_83xx_idc_cold_state 743 * 744 * @adapter: adapter structure 745 * 746 * If HW is up and running device will enter READY state. 747 * If firmware image from host needs to be loaded, device is 748 * forced to start with the file firmware image. 749 * 750 * Returns: Error code or Success(0) 751 * 752 **/ 753 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter) 754 { 755 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0); 756 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0); 757 758 if (qlcnic_load_fw_file) { 759 qlcnic_83xx_idc_restart_hw(adapter, 0); 760 } else { 761 if (qlcnic_83xx_check_hw_status(adapter)) { 762 qlcnic_83xx_idc_enter_failed_state(adapter, 0); 763 return -EIO; 764 } else { 765 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 766 } 767 } 768 return 0; 769 } 770 771 /** 772 * qlcnic_83xx_idc_init_state 773 * 774 * @adapter: adapter structure 775 * 776 * Reset owner will restart the device from this state. 777 * Device will enter failed state if it remains 778 * in this state for more than DEV_INIT time limit. 779 * 780 * Returns: Error code or Success(0) 781 * 782 **/ 783 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter) 784 { 785 int timeout, ret = 0; 786 u32 owner; 787 788 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 789 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) { 790 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 791 if (adapter->ahw->pci_func == owner) 792 ret = qlcnic_83xx_idc_restart_hw(adapter, 1); 793 } else { 794 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout); 795 return ret; 796 } 797 798 return ret; 799 } 800 801 /** 802 * qlcnic_83xx_idc_ready_state 803 * 804 * @adapter: adapter structure 805 * 806 * Perform IDC protocol specicifed actions after monitoring device state and 807 * events. 808 * 809 * Returns: Error code or Success(0) 810 * 811 **/ 812 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter) 813 { 814 u32 val; 815 struct qlcnic_hardware_context *ahw = adapter->ahw; 816 int ret = 0; 817 818 /* Perform NIC configuration based ready state entry actions */ 819 if (ahw->idc.state_entry(adapter)) 820 return -EIO; 821 822 if (qlcnic_check_temp(adapter)) { 823 if (ahw->temp == QLCNIC_TEMP_PANIC) { 824 qlcnic_83xx_idc_check_fan_failure(adapter); 825 dev_err(&adapter->pdev->dev, 826 "Error: device temperature %d above limits\n", 827 adapter->ahw->temp); 828 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status); 829 set_bit(__QLCNIC_RESETTING, &adapter->state); 830 qlcnic_83xx_idc_detach_driver(adapter); 831 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 832 return -EIO; 833 } 834 } 835 836 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 837 ret = qlcnic_83xx_check_heartbeat(adapter); 838 if (ret) { 839 adapter->flags |= QLCNIC_FW_HANG; 840 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 841 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status); 842 set_bit(__QLCNIC_RESETTING, &adapter->state); 843 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 844 } 845 return -EIO; 846 } 847 848 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) { 849 /* Move to need reset state and prepare for reset */ 850 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 851 return ret; 852 } 853 854 /* Check for soft reset request */ 855 if (ahw->reset_context && 856 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 857 adapter->ahw->reset_context = 0; 858 qlcnic_83xx_idc_tx_soft_reset(adapter); 859 return ret; 860 } 861 862 /* Move to need quiesce state if requested */ 863 if (adapter->ahw->idc.quiesce_req) { 864 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1); 865 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 866 return ret; 867 } 868 869 return ret; 870 } 871 872 /** 873 * qlcnic_83xx_idc_need_reset_state 874 * 875 * @adapter: adapter structure 876 * 877 * Device will remain in this state until: 878 * Reset request ACK's are recieved from all the functions 879 * Wait time exceeds max time limit 880 * 881 * Returns: Error code or Success(0) 882 * 883 **/ 884 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter) 885 { 886 int ret = 0; 887 888 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) { 889 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 890 set_bit(__QLCNIC_RESETTING, &adapter->state); 891 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); 892 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) 893 qlcnic_83xx_disable_vnic_mode(adapter, 1); 894 895 if (qlcnic_check_diag_status(adapter)) { 896 dev_info(&adapter->pdev->dev, 897 "%s: Wait for diag completion\n", __func__); 898 adapter->ahw->idc.delay_reset = 1; 899 return 0; 900 } else { 901 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 902 qlcnic_83xx_idc_detach_driver(adapter); 903 } 904 } 905 906 if (qlcnic_check_diag_status(adapter)) { 907 dev_info(&adapter->pdev->dev, 908 "%s: Wait for diag completion\n", __func__); 909 return -1; 910 } else { 911 if (adapter->ahw->idc.delay_reset) { 912 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 913 qlcnic_83xx_idc_detach_driver(adapter); 914 adapter->ahw->idc.delay_reset = 0; 915 } 916 917 /* Check for ACK from other functions */ 918 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter); 919 if (ret) { 920 dev_info(&adapter->pdev->dev, 921 "%s: Waiting for reset ACK\n", __func__); 922 return -1; 923 } 924 } 925 926 /* Transit to INIT state and restart the HW */ 927 qlcnic_83xx_idc_enter_init_state(adapter, 1); 928 929 return ret; 930 } 931 932 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter) 933 { 934 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__); 935 return 0; 936 } 937 938 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter) 939 { 940 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__); 941 clear_bit(__QLCNIC_RESETTING, &adapter->state); 942 adapter->ahw->idc.err_code = -EIO; 943 944 return 0; 945 } 946 947 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter) 948 { 949 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__); 950 return 0; 951 } 952 953 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter, 954 u32 state) 955 { 956 u32 cur, prev, next; 957 958 cur = adapter->ahw->idc.curr_state; 959 prev = adapter->ahw->idc.prev_state; 960 next = state; 961 962 if ((next < QLC_83XX_IDC_DEV_COLD) || 963 (next > QLC_83XX_IDC_DEV_QUISCENT)) { 964 dev_err(&adapter->pdev->dev, 965 "%s: curr %d, prev %d, next state %d is invalid\n", 966 __func__, cur, prev, state); 967 return 1; 968 } 969 970 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) && 971 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) { 972 if ((next != QLC_83XX_IDC_DEV_COLD) && 973 (next != QLC_83XX_IDC_DEV_READY)) { 974 dev_err(&adapter->pdev->dev, 975 "%s: failed, cur %d prev %d next %d\n", 976 __func__, cur, prev, next); 977 return 1; 978 } 979 } 980 981 if (next == QLC_83XX_IDC_DEV_INIT) { 982 if ((prev != QLC_83XX_IDC_DEV_INIT) && 983 (prev != QLC_83XX_IDC_DEV_COLD) && 984 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) { 985 dev_err(&adapter->pdev->dev, 986 "%s: failed, cur %d prev %d next %d\n", 987 __func__, cur, prev, next); 988 return 1; 989 } 990 } 991 992 return 0; 993 } 994 995 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter) 996 { 997 if (adapter->fhash.fnum) 998 qlcnic_prune_lb_filters(adapter); 999 } 1000 1001 /** 1002 * qlcnic_83xx_idc_poll_dev_state 1003 * 1004 * @work: kernel work queue structure used to schedule the function 1005 * 1006 * Poll device state periodically and perform state specific 1007 * actions defined by Inter Driver Communication (IDC) protocol. 1008 * 1009 * Returns: None 1010 * 1011 **/ 1012 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work) 1013 { 1014 struct qlcnic_adapter *adapter; 1015 u32 state; 1016 1017 adapter = container_of(work, struct qlcnic_adapter, fw_work.work); 1018 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1019 1020 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1021 qlcnic_83xx_idc_log_state_history(adapter); 1022 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1023 } else { 1024 adapter->ahw->idc.curr_state = state; 1025 } 1026 1027 switch (adapter->ahw->idc.curr_state) { 1028 case QLC_83XX_IDC_DEV_READY: 1029 qlcnic_83xx_idc_ready_state(adapter); 1030 break; 1031 case QLC_83XX_IDC_DEV_NEED_RESET: 1032 qlcnic_83xx_idc_need_reset_state(adapter); 1033 break; 1034 case QLC_83XX_IDC_DEV_NEED_QUISCENT: 1035 qlcnic_83xx_idc_need_quiesce_state(adapter); 1036 break; 1037 case QLC_83XX_IDC_DEV_FAILED: 1038 qlcnic_83xx_idc_failed_state(adapter); 1039 return; 1040 case QLC_83XX_IDC_DEV_INIT: 1041 qlcnic_83xx_idc_init_state(adapter); 1042 break; 1043 case QLC_83XX_IDC_DEV_QUISCENT: 1044 qlcnic_83xx_idc_quiesce_state(adapter); 1045 break; 1046 default: 1047 qlcnic_83xx_idc_unknown_state(adapter); 1048 return; 1049 } 1050 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state; 1051 qlcnic_83xx_periodic_tasks(adapter); 1052 1053 /* Re-schedule the function */ 1054 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status)) 1055 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 1056 adapter->ahw->idc.delay); 1057 } 1058 1059 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter) 1060 { 1061 u32 idc_params, val; 1062 1063 if (qlcnic_83xx_lockless_flash_read32(adapter, 1064 QLC_83XX_IDC_FLASH_PARAM_ADDR, 1065 (u8 *)&idc_params, 1)) { 1066 dev_info(&adapter->pdev->dev, 1067 "%s:failed to get IDC params from flash\n", __func__); 1068 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 1069 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 1070 } else { 1071 adapter->dev_init_timeo = idc_params & 0xFFFF; 1072 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF); 1073 } 1074 1075 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1076 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN; 1077 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 1078 adapter->ahw->idc.err_code = 0; 1079 adapter->ahw->idc.collect_dump = 0; 1080 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states; 1081 1082 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1083 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); 1084 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1085 1086 /* Check if reset recovery is disabled */ 1087 if (!qlcnic_auto_fw_reset) { 1088 /* Propagate do not reset request to other functions */ 1089 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1090 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1091 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1092 } 1093 } 1094 1095 static int 1096 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter) 1097 { 1098 u32 state, val; 1099 1100 if (qlcnic_83xx_lock_driver(adapter)) 1101 return -EIO; 1102 1103 /* Clear driver lock register */ 1104 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0); 1105 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) { 1106 qlcnic_83xx_unlock_driver(adapter); 1107 return -EIO; 1108 } 1109 1110 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1111 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1112 qlcnic_83xx_unlock_driver(adapter); 1113 return -EIO; 1114 } 1115 1116 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) { 1117 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 1118 QLC_83XX_IDC_DEV_COLD); 1119 state = QLC_83XX_IDC_DEV_COLD; 1120 } 1121 1122 adapter->ahw->idc.curr_state = state; 1123 /* First to load function should cold boot the device */ 1124 if (state == QLC_83XX_IDC_DEV_COLD) 1125 qlcnic_83xx_idc_cold_state_handler(adapter); 1126 1127 /* Check if reset recovery is enabled */ 1128 if (qlcnic_auto_fw_reset) { 1129 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1130 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1131 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1132 } 1133 1134 qlcnic_83xx_unlock_driver(adapter); 1135 1136 return 0; 1137 } 1138 1139 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter) 1140 { 1141 int ret = -EIO; 1142 1143 qlcnic_83xx_setup_idc_parameters(adapter); 1144 1145 if (qlcnic_83xx_get_reset_instruction_template(adapter)) 1146 return ret; 1147 1148 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) { 1149 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter)) 1150 return -EIO; 1151 } else { 1152 if (qlcnic_83xx_idc_check_major_version(adapter)) 1153 return -EIO; 1154 } 1155 1156 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 1157 1158 return 0; 1159 } 1160 1161 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter) 1162 { 1163 int id; 1164 u32 val; 1165 1166 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 1167 usleep_range(10000, 11000); 1168 1169 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1170 id = id & 0xFF; 1171 1172 if (id == adapter->portnum) { 1173 dev_err(&adapter->pdev->dev, 1174 "%s: wait for lock recovery.. %d\n", __func__, id); 1175 msleep(20); 1176 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1177 id = id & 0xFF; 1178 } 1179 1180 /* Clear driver presence bit */ 1181 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 1182 val = val & ~(1 << adapter->portnum); 1183 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 1184 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1185 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1186 1187 cancel_delayed_work_sync(&adapter->fw_work); 1188 } 1189 1190 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key) 1191 { 1192 u32 val; 1193 1194 if (qlcnic_83xx_lock_driver(adapter)) { 1195 dev_err(&adapter->pdev->dev, 1196 "%s:failed, please retry\n", __func__); 1197 return; 1198 } 1199 1200 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1201 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) || 1202 !qlcnic_auto_fw_reset) { 1203 dev_err(&adapter->pdev->dev, 1204 "%s:failed, device in non reset mode\n", __func__); 1205 qlcnic_83xx_unlock_driver(adapter); 1206 return; 1207 } 1208 1209 if (key == QLCNIC_FORCE_FW_RESET) { 1210 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1211 val = val | QLC_83XX_IDC_GRACEFULL_RESET; 1212 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1213 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) { 1214 adapter->ahw->idc.collect_dump = 1; 1215 } 1216 1217 qlcnic_83xx_unlock_driver(adapter); 1218 return; 1219 } 1220 1221 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter) 1222 { 1223 u8 *p_cache; 1224 u32 src, size; 1225 u64 dest; 1226 int ret = -EIO; 1227 1228 src = QLC_83XX_BOOTLOADER_FLASH_ADDR; 1229 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR); 1230 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE); 1231 1232 /* alignment check */ 1233 if (size & 0xF) 1234 size = (size + 16) & ~0xF; 1235 1236 p_cache = kzalloc(size, GFP_KERNEL); 1237 if (p_cache == NULL) 1238 return -ENOMEM; 1239 1240 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache, 1241 size / sizeof(u32)); 1242 if (ret) { 1243 kfree(p_cache); 1244 return ret; 1245 } 1246 /* 16 byte write to MS memory */ 1247 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache, 1248 size / 16); 1249 if (ret) { 1250 kfree(p_cache); 1251 return ret; 1252 } 1253 kfree(p_cache); 1254 1255 return ret; 1256 } 1257 1258 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter) 1259 { 1260 u32 dest, *p_cache; 1261 u64 addr; 1262 u8 data[16]; 1263 size_t size; 1264 int i, ret = -EIO; 1265 1266 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR); 1267 size = (adapter->ahw->fw_info.fw->size & ~0xF); 1268 p_cache = (u32 *)adapter->ahw->fw_info.fw->data; 1269 addr = (u64)dest; 1270 1271 ret = qlcnic_83xx_ms_mem_write128(adapter, addr, 1272 (u32 *)p_cache, size / 16); 1273 if (ret) { 1274 dev_err(&adapter->pdev->dev, "MS memory write failed\n"); 1275 release_firmware(adapter->ahw->fw_info.fw); 1276 adapter->ahw->fw_info.fw = NULL; 1277 return -EIO; 1278 } 1279 1280 /* alignment check */ 1281 if (adapter->ahw->fw_info.fw->size & 0xF) { 1282 addr = dest + size; 1283 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++) 1284 data[i] = adapter->ahw->fw_info.fw->data[size + i]; 1285 for (; i < 16; i++) 1286 data[i] = 0; 1287 ret = qlcnic_83xx_ms_mem_write128(adapter, addr, 1288 (u32 *)data, 1); 1289 if (ret) { 1290 dev_err(&adapter->pdev->dev, 1291 "MS memory write failed\n"); 1292 release_firmware(adapter->ahw->fw_info.fw); 1293 adapter->ahw->fw_info.fw = NULL; 1294 return -EIO; 1295 } 1296 } 1297 release_firmware(adapter->ahw->fw_info.fw); 1298 adapter->ahw->fw_info.fw = NULL; 1299 1300 return 0; 1301 } 1302 1303 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) 1304 { 1305 int i, j; 1306 u32 val = 0, val1 = 0, reg = 0; 1307 int err = 0; 1308 1309 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err); 1310 if (err == -EIO) 1311 return; 1312 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val); 1313 1314 for (j = 0; j < 2; j++) { 1315 if (j == 0) { 1316 dev_info(&adapter->pdev->dev, 1317 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:"); 1318 reg = QLC_83XX_PORT0_THRESHOLD; 1319 } else if (j == 1) { 1320 dev_info(&adapter->pdev->dev, 1321 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:"); 1322 reg = QLC_83XX_PORT1_THRESHOLD; 1323 } 1324 for (i = 0; i < 8; i++) { 1325 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1326 if (err == -EIO) 1327 return; 1328 dev_info(&adapter->pdev->dev, "0x%x ", val); 1329 } 1330 dev_info(&adapter->pdev->dev, "\n"); 1331 } 1332 1333 for (j = 0; j < 2; j++) { 1334 if (j == 0) { 1335 dev_info(&adapter->pdev->dev, 1336 "Port 0 RxB TC Max Cell Registers[4..1]:"); 1337 reg = QLC_83XX_PORT0_TC_MC_REG; 1338 } else if (j == 1) { 1339 dev_info(&adapter->pdev->dev, 1340 "Port 1 RxB TC Max Cell Registers[4..1]:"); 1341 reg = QLC_83XX_PORT1_TC_MC_REG; 1342 } 1343 for (i = 0; i < 4; i++) { 1344 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1345 if (err == -EIO) 1346 return; 1347 dev_info(&adapter->pdev->dev, "0x%x ", val); 1348 } 1349 dev_info(&adapter->pdev->dev, "\n"); 1350 } 1351 1352 for (j = 0; j < 2; j++) { 1353 if (j == 0) { 1354 dev_info(&adapter->pdev->dev, 1355 "Port 0 RxB Rx TC Stats[TC7..TC0]:"); 1356 reg = QLC_83XX_PORT0_TC_STATS; 1357 } else if (j == 1) { 1358 dev_info(&adapter->pdev->dev, 1359 "Port 1 RxB Rx TC Stats[TC7..TC0]:"); 1360 reg = QLC_83XX_PORT1_TC_STATS; 1361 } 1362 for (i = 7; i >= 0; i--) { 1363 val = QLCRD32(adapter, reg, &err); 1364 if (err == -EIO) 1365 return; 1366 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ 1367 QLCWR32(adapter, reg, (val | (i << 29))); 1368 val = QLCRD32(adapter, reg, &err); 1369 if (err == -EIO) 1370 return; 1371 dev_info(&adapter->pdev->dev, "0x%x ", val); 1372 } 1373 dev_info(&adapter->pdev->dev, "\n"); 1374 } 1375 1376 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err); 1377 if (err == -EIO) 1378 return; 1379 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err); 1380 if (err == -EIO) 1381 return; 1382 dev_info(&adapter->pdev->dev, 1383 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n", 1384 val, val1); 1385 } 1386 1387 1388 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter) 1389 { 1390 u32 reg = 0, i, j; 1391 1392 if (qlcnic_83xx_lock_driver(adapter)) { 1393 dev_err(&adapter->pdev->dev, 1394 "%s:failed to acquire driver lock\n", __func__); 1395 return; 1396 } 1397 1398 qlcnic_83xx_dump_pause_control_regs(adapter); 1399 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0); 1400 1401 for (j = 0; j < 2; j++) { 1402 if (j == 0) 1403 reg = QLC_83XX_PORT0_THRESHOLD; 1404 else if (j == 1) 1405 reg = QLC_83XX_PORT1_THRESHOLD; 1406 1407 for (i = 0; i < 8; i++) 1408 QLCWR32(adapter, reg + (i * 0x4), 0x0); 1409 } 1410 1411 for (j = 0; j < 2; j++) { 1412 if (j == 0) 1413 reg = QLC_83XX_PORT0_TC_MC_REG; 1414 else if (j == 1) 1415 reg = QLC_83XX_PORT1_TC_MC_REG; 1416 1417 for (i = 0; i < 4; i++) 1418 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF); 1419 } 1420 1421 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0); 1422 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0); 1423 dev_info(&adapter->pdev->dev, 1424 "Disabled pause frames successfully on all ports\n"); 1425 qlcnic_83xx_unlock_driver(adapter); 1426 } 1427 1428 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter) 1429 { 1430 QLCWR32(adapter, QLC_83XX_RESET_REG, 0); 1431 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0); 1432 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0); 1433 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0); 1434 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0); 1435 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0); 1436 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0); 1437 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0); 1438 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1); 1439 } 1440 1441 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev) 1442 { 1443 u32 heartbeat, peg_status; 1444 int retries, ret = -EIO, err = 0; 1445 1446 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT; 1447 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev, 1448 QLCNIC_PEG_ALIVE_COUNTER); 1449 1450 do { 1451 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS); 1452 heartbeat = QLC_SHARED_REG_RD32(p_dev, 1453 QLCNIC_PEG_ALIVE_COUNTER); 1454 if (heartbeat != p_dev->heartbeat) { 1455 ret = QLCNIC_RCODE_SUCCESS; 1456 break; 1457 } 1458 } while (--retries); 1459 1460 if (ret) { 1461 dev_err(&p_dev->pdev->dev, "firmware hang detected\n"); 1462 qlcnic_83xx_take_eport_out_of_reset(p_dev); 1463 qlcnic_83xx_disable_pause_frames(p_dev); 1464 peg_status = QLC_SHARED_REG_RD32(p_dev, 1465 QLCNIC_PEG_HALT_STATUS1); 1466 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n" 1467 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n" 1468 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n" 1469 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n" 1470 "PEG_NET_4_PC: 0x%x\n", peg_status, 1471 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2), 1472 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err), 1473 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err), 1474 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err), 1475 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err), 1476 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err)); 1477 1478 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67) 1479 dev_err(&p_dev->pdev->dev, 1480 "Device is being reset err code 0x00006700.\n"); 1481 } 1482 1483 return ret; 1484 } 1485 1486 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev) 1487 { 1488 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT; 1489 u32 val; 1490 1491 do { 1492 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE); 1493 if (val == QLC_83XX_CMDPEG_COMPLETE) 1494 return 0; 1495 msleep(QLCNIC_CMDPEG_CHECK_DELAY); 1496 } while (--retries); 1497 1498 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val); 1499 return -EIO; 1500 } 1501 1502 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev) 1503 { 1504 int err; 1505 1506 err = qlcnic_83xx_check_cmd_peg_status(p_dev); 1507 if (err) 1508 return err; 1509 1510 err = qlcnic_83xx_check_heartbeat(p_dev); 1511 if (err) 1512 return err; 1513 1514 return err; 1515 } 1516 1517 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr, 1518 int duration, u32 mask, u32 status) 1519 { 1520 int timeout_error, err = 0; 1521 u32 value; 1522 u8 retries; 1523 1524 value = QLCRD32(p_dev, addr, &err); 1525 if (err == -EIO) 1526 return err; 1527 retries = duration / 10; 1528 1529 do { 1530 if ((value & mask) != status) { 1531 timeout_error = 1; 1532 msleep(duration / 10); 1533 value = QLCRD32(p_dev, addr, &err); 1534 if (err == -EIO) 1535 return err; 1536 } else { 1537 timeout_error = 0; 1538 break; 1539 } 1540 } while (retries--); 1541 1542 if (timeout_error) { 1543 p_dev->ahw->reset.seq_error++; 1544 dev_err(&p_dev->pdev->dev, 1545 "%s: Timeout Err, entry_num = %d\n", 1546 __func__, p_dev->ahw->reset.seq_index); 1547 dev_err(&p_dev->pdev->dev, 1548 "0x%08x 0x%08x 0x%08x\n", 1549 value, mask, status); 1550 } 1551 1552 return timeout_error; 1553 } 1554 1555 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev) 1556 { 1557 u32 sum = 0; 1558 u16 *buff = (u16 *)p_dev->ahw->reset.buff; 1559 int count = p_dev->ahw->reset.hdr->size / sizeof(u16); 1560 1561 while (count-- > 0) 1562 sum += *buff++; 1563 1564 while (sum >> 16) 1565 sum = (sum & 0xFFFF) + (sum >> 16); 1566 1567 if (~sum) { 1568 return 0; 1569 } else { 1570 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1571 return -1; 1572 } 1573 } 1574 1575 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev) 1576 { 1577 struct qlcnic_hardware_context *ahw = p_dev->ahw; 1578 u32 addr, count, prev_ver, curr_ver; 1579 u8 *p_buff; 1580 1581 if (ahw->reset.buff != NULL) { 1582 prev_ver = p_dev->fw_version; 1583 curr_ver = qlcnic_83xx_get_fw_version(p_dev); 1584 if (curr_ver > prev_ver) 1585 kfree(ahw->reset.buff); 1586 else 1587 return 0; 1588 } 1589 1590 ahw->reset.seq_error = 0; 1591 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL); 1592 if (p_dev->ahw->reset.buff == NULL) 1593 return -ENOMEM; 1594 1595 p_buff = p_dev->ahw->reset.buff; 1596 addr = QLC_83XX_RESET_TEMPLATE_ADDR; 1597 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32); 1598 1599 /* Copy template header from flash */ 1600 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1601 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1602 return -EIO; 1603 } 1604 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff; 1605 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size; 1606 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1607 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32); 1608 1609 /* Copy rest of the template */ 1610 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1611 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1612 return -EIO; 1613 } 1614 1615 if (qlcnic_83xx_reset_template_checksum(p_dev)) 1616 return -EIO; 1617 /* Get Stop, Start and Init command offsets */ 1618 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset; 1619 ahw->reset.start_offset = ahw->reset.buff + 1620 ahw->reset.hdr->start_offset; 1621 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1622 return 0; 1623 } 1624 1625 /* Read Write HW register command */ 1626 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev, 1627 u32 raddr, u32 waddr) 1628 { 1629 int err = 0; 1630 u32 value; 1631 1632 value = QLCRD32(p_dev, raddr, &err); 1633 if (err == -EIO) 1634 return; 1635 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1636 } 1637 1638 /* Read Modify Write HW register command */ 1639 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev, 1640 u32 raddr, u32 waddr, 1641 struct qlc_83xx_rmw *p_rmw_hdr) 1642 { 1643 int err = 0; 1644 u32 value; 1645 1646 if (p_rmw_hdr->index_a) { 1647 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a]; 1648 } else { 1649 value = QLCRD32(p_dev, raddr, &err); 1650 if (err == -EIO) 1651 return; 1652 } 1653 1654 value &= p_rmw_hdr->mask; 1655 value <<= p_rmw_hdr->shl; 1656 value >>= p_rmw_hdr->shr; 1657 value |= p_rmw_hdr->or_value; 1658 value ^= p_rmw_hdr->xor_value; 1659 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1660 } 1661 1662 /* Write HW register command */ 1663 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev, 1664 struct qlc_83xx_entry_hdr *p_hdr) 1665 { 1666 int i; 1667 struct qlc_83xx_entry *entry; 1668 1669 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1670 sizeof(struct qlc_83xx_entry_hdr)); 1671 1672 for (i = 0; i < p_hdr->count; i++, entry++) { 1673 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1, 1674 entry->arg2); 1675 if (p_hdr->delay) 1676 udelay((u32)(p_hdr->delay)); 1677 } 1678 } 1679 1680 /* Read and Write instruction */ 1681 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev, 1682 struct qlc_83xx_entry_hdr *p_hdr) 1683 { 1684 int i; 1685 struct qlc_83xx_entry *entry; 1686 1687 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1688 sizeof(struct qlc_83xx_entry_hdr)); 1689 1690 for (i = 0; i < p_hdr->count; i++, entry++) { 1691 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1, 1692 entry->arg2); 1693 if (p_hdr->delay) 1694 udelay((u32)(p_hdr->delay)); 1695 } 1696 } 1697 1698 /* Poll HW register command */ 1699 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev, 1700 struct qlc_83xx_entry_hdr *p_hdr) 1701 { 1702 long delay; 1703 struct qlc_83xx_entry *entry; 1704 struct qlc_83xx_poll *poll; 1705 int i, err = 0; 1706 unsigned long arg1, arg2; 1707 1708 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1709 sizeof(struct qlc_83xx_entry_hdr)); 1710 1711 entry = (struct qlc_83xx_entry *)((char *)poll + 1712 sizeof(struct qlc_83xx_poll)); 1713 delay = (long)p_hdr->delay; 1714 1715 if (!delay) { 1716 for (i = 0; i < p_hdr->count; i++, entry++) 1717 qlcnic_83xx_poll_reg(p_dev, entry->arg1, 1718 delay, poll->mask, 1719 poll->status); 1720 } else { 1721 for (i = 0; i < p_hdr->count; i++, entry++) { 1722 arg1 = entry->arg1; 1723 arg2 = entry->arg2; 1724 if (delay) { 1725 if (qlcnic_83xx_poll_reg(p_dev, 1726 arg1, delay, 1727 poll->mask, 1728 poll->status)){ 1729 QLCRD32(p_dev, arg1, &err); 1730 if (err == -EIO) 1731 return; 1732 QLCRD32(p_dev, arg2, &err); 1733 if (err == -EIO) 1734 return; 1735 } 1736 } 1737 } 1738 } 1739 } 1740 1741 /* Poll and write HW register command */ 1742 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev, 1743 struct qlc_83xx_entry_hdr *p_hdr) 1744 { 1745 int i; 1746 long delay; 1747 struct qlc_83xx_quad_entry *entry; 1748 struct qlc_83xx_poll *poll; 1749 1750 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1751 sizeof(struct qlc_83xx_entry_hdr)); 1752 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1753 sizeof(struct qlc_83xx_poll)); 1754 delay = (long)p_hdr->delay; 1755 1756 for (i = 0; i < p_hdr->count; i++, entry++) { 1757 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr, 1758 entry->dr_value); 1759 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1760 entry->ar_value); 1761 if (delay) 1762 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1763 poll->mask, poll->status); 1764 } 1765 } 1766 1767 /* Read Modify Write register command */ 1768 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev, 1769 struct qlc_83xx_entry_hdr *p_hdr) 1770 { 1771 int i; 1772 struct qlc_83xx_entry *entry; 1773 struct qlc_83xx_rmw *rmw_hdr; 1774 1775 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr + 1776 sizeof(struct qlc_83xx_entry_hdr)); 1777 1778 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr + 1779 sizeof(struct qlc_83xx_rmw)); 1780 1781 for (i = 0; i < p_hdr->count; i++, entry++) { 1782 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1, 1783 entry->arg2, rmw_hdr); 1784 if (p_hdr->delay) 1785 udelay((u32)(p_hdr->delay)); 1786 } 1787 } 1788 1789 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr) 1790 { 1791 if (p_hdr->delay) 1792 mdelay((u32)((long)p_hdr->delay)); 1793 } 1794 1795 /* Read and poll register command */ 1796 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev, 1797 struct qlc_83xx_entry_hdr *p_hdr) 1798 { 1799 long delay; 1800 int index, i, j, err; 1801 struct qlc_83xx_quad_entry *entry; 1802 struct qlc_83xx_poll *poll; 1803 unsigned long addr; 1804 1805 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1806 sizeof(struct qlc_83xx_entry_hdr)); 1807 1808 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1809 sizeof(struct qlc_83xx_poll)); 1810 delay = (long)p_hdr->delay; 1811 1812 for (i = 0; i < p_hdr->count; i++, entry++) { 1813 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1814 entry->ar_value); 1815 if (delay) { 1816 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1817 poll->mask, poll->status)){ 1818 index = p_dev->ahw->reset.array_index; 1819 addr = entry->dr_addr; 1820 j = QLCRD32(p_dev, addr, &err); 1821 if (err == -EIO) 1822 return; 1823 1824 p_dev->ahw->reset.array[index++] = j; 1825 1826 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES) 1827 p_dev->ahw->reset.array_index = 1; 1828 } 1829 } 1830 } 1831 } 1832 1833 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev) 1834 { 1835 p_dev->ahw->reset.seq_end = 1; 1836 } 1837 1838 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev) 1839 { 1840 p_dev->ahw->reset.template_end = 1; 1841 if (p_dev->ahw->reset.seq_error == 0) 1842 dev_err(&p_dev->pdev->dev, 1843 "HW restart process completed successfully.\n"); 1844 else 1845 dev_err(&p_dev->pdev->dev, 1846 "HW restart completed with timeout errors.\n"); 1847 } 1848 1849 /** 1850 * qlcnic_83xx_exec_template_cmd 1851 * 1852 * @p_dev: adapter structure 1853 * @p_buff: Poiter to instruction template 1854 * 1855 * Template provides instructions to stop, restart and initalize firmware. 1856 * These instructions are abstracted as a series of read, write and 1857 * poll operations on hardware registers. Register information and operation 1858 * specifics are not exposed to the driver. Driver reads the template from 1859 * flash and executes the instructions located at pre-defined offsets. 1860 * 1861 * Returns: None 1862 * */ 1863 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev, 1864 char *p_buff) 1865 { 1866 int index, entries; 1867 struct qlc_83xx_entry_hdr *p_hdr; 1868 char *entry = p_buff; 1869 1870 p_dev->ahw->reset.seq_end = 0; 1871 p_dev->ahw->reset.template_end = 0; 1872 entries = p_dev->ahw->reset.hdr->entries; 1873 index = p_dev->ahw->reset.seq_index; 1874 1875 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) { 1876 p_hdr = (struct qlc_83xx_entry_hdr *)entry; 1877 1878 switch (p_hdr->cmd) { 1879 case QLC_83XX_OPCODE_NOP: 1880 break; 1881 case QLC_83XX_OPCODE_WRITE_LIST: 1882 qlcnic_83xx_write_list(p_dev, p_hdr); 1883 break; 1884 case QLC_83XX_OPCODE_READ_WRITE_LIST: 1885 qlcnic_83xx_read_write_list(p_dev, p_hdr); 1886 break; 1887 case QLC_83XX_OPCODE_POLL_LIST: 1888 qlcnic_83xx_poll_list(p_dev, p_hdr); 1889 break; 1890 case QLC_83XX_OPCODE_POLL_WRITE_LIST: 1891 qlcnic_83xx_poll_write_list(p_dev, p_hdr); 1892 break; 1893 case QLC_83XX_OPCODE_READ_MODIFY_WRITE: 1894 qlcnic_83xx_read_modify_write(p_dev, p_hdr); 1895 break; 1896 case QLC_83XX_OPCODE_SEQ_PAUSE: 1897 qlcnic_83xx_pause(p_hdr); 1898 break; 1899 case QLC_83XX_OPCODE_SEQ_END: 1900 qlcnic_83xx_seq_end(p_dev); 1901 break; 1902 case QLC_83XX_OPCODE_TMPL_END: 1903 qlcnic_83xx_template_end(p_dev); 1904 break; 1905 case QLC_83XX_OPCODE_POLL_READ_LIST: 1906 qlcnic_83xx_poll_read_list(p_dev, p_hdr); 1907 break; 1908 default: 1909 dev_err(&p_dev->pdev->dev, 1910 "%s: Unknown opcode 0x%04x in template %d\n", 1911 __func__, p_hdr->cmd, index); 1912 break; 1913 } 1914 entry += p_hdr->size; 1915 } 1916 p_dev->ahw->reset.seq_index = index; 1917 } 1918 1919 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev) 1920 { 1921 p_dev->ahw->reset.seq_index = 0; 1922 1923 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset); 1924 if (p_dev->ahw->reset.seq_end != 1) 1925 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1926 } 1927 1928 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev) 1929 { 1930 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset); 1931 if (p_dev->ahw->reset.template_end != 1) 1932 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1933 } 1934 1935 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev) 1936 { 1937 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset); 1938 if (p_dev->ahw->reset.seq_end != 1) 1939 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1940 } 1941 1942 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter) 1943 { 1944 int err = -EIO; 1945 1946 if (request_firmware(&adapter->ahw->fw_info.fw, 1947 QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) { 1948 dev_err(&adapter->pdev->dev, 1949 "No file FW image, loading flash FW image.\n"); 1950 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1951 QLC_83XX_BOOT_FROM_FLASH); 1952 } else { 1953 if (qlcnic_83xx_copy_fw_file(adapter)) 1954 return err; 1955 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1956 QLC_83XX_BOOT_FROM_FILE); 1957 } 1958 1959 return 0; 1960 } 1961 1962 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter) 1963 { 1964 u32 val; 1965 int err = -EIO; 1966 1967 qlcnic_83xx_stop_hw(adapter); 1968 1969 /* Collect FW register dump if required */ 1970 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1971 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET)) 1972 qlcnic_dump_fw(adapter); 1973 qlcnic_83xx_init_hw(adapter); 1974 1975 if (qlcnic_83xx_copy_bootloader(adapter)) 1976 return err; 1977 /* Boot either flash image or firmware image from host file system */ 1978 if (qlcnic_load_fw_file) { 1979 if (qlcnic_83xx_load_fw_image_from_host(adapter)) 1980 return err; 1981 } else { 1982 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1983 QLC_83XX_BOOT_FROM_FLASH); 1984 } 1985 1986 qlcnic_83xx_start_hw(adapter); 1987 if (qlcnic_83xx_check_hw_status(adapter)) 1988 return -EIO; 1989 1990 return 0; 1991 } 1992 1993 /** 1994 * qlcnic_83xx_config_default_opmode 1995 * 1996 * @adapter: adapter structure 1997 * 1998 * Configure default driver operating mode 1999 * 2000 * Returns: Error code or Success(0) 2001 * */ 2002 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter) 2003 { 2004 u32 op_mode; 2005 struct qlcnic_hardware_context *ahw = adapter->ahw; 2006 2007 qlcnic_get_func_no(adapter); 2008 op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE); 2009 2010 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) 2011 op_mode = QLC_83XX_DEFAULT_OPMODE; 2012 2013 if (op_mode == QLC_83XX_DEFAULT_OPMODE) { 2014 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver; 2015 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry; 2016 } else { 2017 return -EIO; 2018 } 2019 2020 return 0; 2021 } 2022 2023 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter) 2024 { 2025 int err; 2026 struct qlcnic_info nic_info; 2027 struct qlcnic_hardware_context *ahw = adapter->ahw; 2028 2029 memset(&nic_info, 0, sizeof(struct qlcnic_info)); 2030 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func); 2031 if (err) 2032 return -EIO; 2033 2034 ahw->physical_port = (u8) nic_info.phys_port; 2035 ahw->switch_mode = nic_info.switch_mode; 2036 ahw->max_tx_ques = nic_info.max_tx_ques; 2037 ahw->max_rx_ques = nic_info.max_rx_ques; 2038 ahw->capabilities = nic_info.capabilities; 2039 ahw->max_mac_filters = nic_info.max_mac_filters; 2040 ahw->max_mtu = nic_info.max_mtu; 2041 2042 /* VNIC mode is detected by BIT_23 in capabilities. This bit is also 2043 * set in case device is SRIOV capable. VNIC and SRIOV are mutually 2044 * exclusive. So in case of sriov capable device load driver in 2045 * default mode 2046 */ 2047 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) { 2048 ahw->nic_mode = QLC_83XX_DEFAULT_MODE; 2049 return ahw->nic_mode; 2050 } 2051 2052 if (ahw->capabilities & BIT_23) 2053 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE; 2054 else 2055 ahw->nic_mode = QLC_83XX_DEFAULT_MODE; 2056 2057 return ahw->nic_mode; 2058 } 2059 2060 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter) 2061 { 2062 int ret; 2063 2064 ret = qlcnic_83xx_get_nic_configuration(adapter); 2065 if (ret == -EIO) 2066 return -EIO; 2067 2068 if (ret == QLC_83XX_VIRTUAL_NIC_MODE) { 2069 if (qlcnic_83xx_config_vnic_opmode(adapter)) 2070 return -EIO; 2071 } else if (ret == QLC_83XX_DEFAULT_MODE) { 2072 if (qlcnic_83xx_config_default_opmode(adapter)) 2073 return -EIO; 2074 } 2075 2076 return 0; 2077 } 2078 2079 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter) 2080 { 2081 struct qlcnic_hardware_context *ahw = adapter->ahw; 2082 2083 if (ahw->port_type == QLCNIC_XGBE) { 2084 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G; 2085 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G; 2086 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2087 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2088 2089 } else if (ahw->port_type == QLCNIC_GBE) { 2090 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G; 2091 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2092 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2093 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G; 2094 } 2095 adapter->num_txd = MAX_CMD_DESCRIPTORS; 2096 adapter->max_rds_rings = MAX_RDS_RINGS; 2097 } 2098 2099 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter) 2100 { 2101 int err = -EIO; 2102 2103 qlcnic_83xx_get_minidump_template(adapter); 2104 if (qlcnic_83xx_get_port_info(adapter)) 2105 return err; 2106 2107 qlcnic_83xx_config_buff_descriptors(adapter); 2108 adapter->ahw->msix_supported = !!qlcnic_use_msi_x; 2109 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED; 2110 2111 dev_info(&adapter->pdev->dev, "HAL Version: %d\n", 2112 adapter->ahw->fw_hal_version); 2113 2114 return 0; 2115 } 2116 2117 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1)) 2118 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter) 2119 { 2120 struct qlcnic_cmd_args cmd; 2121 u32 presence_mask, audit_mask; 2122 int status; 2123 2124 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 2125 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 2126 2127 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) { 2128 status = qlcnic_alloc_mbx_args(&cmd, adapter, 2129 QLCNIC_CMD_STOP_NIC_FUNC); 2130 if (status) 2131 return; 2132 2133 cmd.req.arg[1] = BIT_31; 2134 status = qlcnic_issue_cmd(adapter, &cmd); 2135 if (status) 2136 dev_err(&adapter->pdev->dev, 2137 "Failed to clean up the function resources\n"); 2138 qlcnic_free_mbx_args(&cmd); 2139 } 2140 } 2141 2142 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac) 2143 { 2144 struct qlcnic_hardware_context *ahw = adapter->ahw; 2145 2146 if (qlcnic_sriov_vf_check(adapter)) 2147 return qlcnic_sriov_vf_init(adapter, pci_using_dac); 2148 2149 if (qlcnic_83xx_check_hw_status(adapter)) 2150 return -EIO; 2151 2152 /* Initilaize 83xx mailbox spinlock */ 2153 spin_lock_init(&ahw->mbx_lock); 2154 2155 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); 2156 qlcnic_83xx_clear_function_resources(adapter); 2157 2158 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work); 2159 2160 /* register for NIC IDC AEN Events */ 2161 qlcnic_83xx_register_nic_idc_func(adapter, 1); 2162 2163 if (!qlcnic_83xx_read_flash_descriptor_table(adapter)) 2164 qlcnic_83xx_read_flash_mfg_id(adapter); 2165 2166 if (qlcnic_83xx_idc_init(adapter)) 2167 return -EIO; 2168 2169 /* Configure default, SR-IOV or Virtual NIC mode of operation */ 2170 if (qlcnic_83xx_configure_opmode(adapter)) 2171 return -EIO; 2172 2173 /* Perform operating mode specific initialization */ 2174 if (adapter->nic_ops->init_driver(adapter)) 2175 return -EIO; 2176 2177 /* Periodically monitor device status */ 2178 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work); 2179 2180 return adapter->ahw->idc.err_code; 2181 } 2182