1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #include "qlcnic_sriov.h" 9 #include "qlcnic.h" 10 #include "qlcnic_hw.h" 11 12 /* Reset template definitions */ 13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000 14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000 15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101 16 17 #define QLC_83XX_OPCODE_NOP 0x0000 18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001 19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002 20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004 21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008 22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010 23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020 24 #define QLC_83XX_OPCODE_SEQ_END 0x0040 25 #define QLC_83XX_OPCODE_TMPL_END 0x0080 26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100 27 28 /* EPORT control registers */ 29 #define QLC_83XX_RESET_CONTROL 0x28084E50 30 #define QLC_83XX_RESET_REG 0x28084E60 31 #define QLC_83XX_RESET_PORT0 0x28084E70 32 #define QLC_83XX_RESET_PORT1 0x28084E80 33 #define QLC_83XX_RESET_PORT2 0x28084E90 34 #define QLC_83XX_RESET_PORT3 0x28084EA0 35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0 36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0 37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0 38 39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter); 40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev); 41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter); 42 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev); 43 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *); 44 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *); 45 46 /* Template header */ 47 struct qlc_83xx_reset_hdr { 48 #if defined(__LITTLE_ENDIAN) 49 u16 version; 50 u16 signature; 51 u16 size; 52 u16 entries; 53 u16 hdr_size; 54 u16 checksum; 55 u16 init_offset; 56 u16 start_offset; 57 #elif defined(__BIG_ENDIAN) 58 u16 signature; 59 u16 version; 60 u16 entries; 61 u16 size; 62 u16 checksum; 63 u16 hdr_size; 64 u16 start_offset; 65 u16 init_offset; 66 #endif 67 } __packed; 68 69 /* Command entry header. */ 70 struct qlc_83xx_entry_hdr { 71 #if defined(__LITTLE_ENDIAN) 72 u16 cmd; 73 u16 size; 74 u16 count; 75 u16 delay; 76 #elif defined(__BIG_ENDIAN) 77 u16 size; 78 u16 cmd; 79 u16 delay; 80 u16 count; 81 #endif 82 } __packed; 83 84 /* Generic poll command */ 85 struct qlc_83xx_poll { 86 u32 mask; 87 u32 status; 88 } __packed; 89 90 /* Read modify write command */ 91 struct qlc_83xx_rmw { 92 u32 mask; 93 u32 xor_value; 94 u32 or_value; 95 #if defined(__LITTLE_ENDIAN) 96 u8 shl; 97 u8 shr; 98 u8 index_a; 99 u8 rsvd; 100 #elif defined(__BIG_ENDIAN) 101 u8 rsvd; 102 u8 index_a; 103 u8 shr; 104 u8 shl; 105 #endif 106 } __packed; 107 108 /* Generic command with 2 DWORD */ 109 struct qlc_83xx_entry { 110 u32 arg1; 111 u32 arg2; 112 } __packed; 113 114 /* Generic command with 4 DWORD */ 115 struct qlc_83xx_quad_entry { 116 u32 dr_addr; 117 u32 dr_value; 118 u32 ar_addr; 119 u32 ar_value; 120 } __packed; 121 static const char *const qlc_83xx_idc_states[] = { 122 "Unknown", 123 "Cold", 124 "Init", 125 "Ready", 126 "Need Reset", 127 "Need Quiesce", 128 "Failed", 129 "Quiesce" 130 }; 131 132 static int 133 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter) 134 { 135 u32 val; 136 137 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 138 if ((val & 0xFFFF)) 139 return 1; 140 else 141 return 0; 142 } 143 144 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter) 145 { 146 u32 cur, prev; 147 cur = adapter->ahw->idc.curr_state; 148 prev = adapter->ahw->idc.prev_state; 149 150 dev_info(&adapter->pdev->dev, 151 "current state = %s, prev state = %s\n", 152 adapter->ahw->idc.name[cur], 153 adapter->ahw->idc.name[prev]); 154 } 155 156 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter, 157 u8 mode, int lock) 158 { 159 u32 val; 160 int seconds; 161 162 if (lock) { 163 if (qlcnic_83xx_lock_driver(adapter)) 164 return -EBUSY; 165 } 166 167 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 168 val |= (adapter->portnum & 0xf); 169 val |= mode << 7; 170 if (mode) 171 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 172 else 173 seconds = jiffies / HZ; 174 175 val |= seconds << 8; 176 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val); 177 adapter->ahw->idc.sec_counter = jiffies / HZ; 178 179 if (lock) 180 qlcnic_83xx_unlock_driver(adapter); 181 182 return 0; 183 } 184 185 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter) 186 { 187 u32 val; 188 189 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION); 190 val = val & ~(0x3 << (adapter->portnum * 2)); 191 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2)); 192 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val); 193 } 194 195 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter, 196 int lock) 197 { 198 u32 val; 199 200 if (lock) { 201 if (qlcnic_83xx_lock_driver(adapter)) 202 return -EBUSY; 203 } 204 205 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 206 val = val & ~0xFF; 207 val = val | QLC_83XX_IDC_MAJOR_VERSION; 208 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val); 209 210 if (lock) 211 qlcnic_83xx_unlock_driver(adapter); 212 213 return 0; 214 } 215 216 static int 217 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter, 218 int status, int lock) 219 { 220 u32 val; 221 222 if (lock) { 223 if (qlcnic_83xx_lock_driver(adapter)) 224 return -EBUSY; 225 } 226 227 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 228 229 if (status) 230 val = val | (1 << adapter->portnum); 231 else 232 val = val & ~(1 << adapter->portnum); 233 234 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 235 qlcnic_83xx_idc_update_minor_version(adapter); 236 237 if (lock) 238 qlcnic_83xx_unlock_driver(adapter); 239 240 return 0; 241 } 242 243 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter) 244 { 245 u32 val; 246 u8 version; 247 248 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 249 version = val & 0xFF; 250 251 if (version != QLC_83XX_IDC_MAJOR_VERSION) { 252 dev_info(&adapter->pdev->dev, 253 "%s:mismatch. version 0x%x, expected version 0x%x\n", 254 __func__, version, QLC_83XX_IDC_MAJOR_VERSION); 255 return -EIO; 256 } 257 258 return 0; 259 } 260 261 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter, 262 int lock) 263 { 264 u32 val; 265 266 if (lock) { 267 if (qlcnic_83xx_lock_driver(adapter)) 268 return -EBUSY; 269 } 270 271 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0); 272 /* Clear gracefull reset bit */ 273 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 274 val &= ~QLC_83XX_IDC_GRACEFULL_RESET; 275 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 276 277 if (lock) 278 qlcnic_83xx_unlock_driver(adapter); 279 280 return 0; 281 } 282 283 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter, 284 int flag, int lock) 285 { 286 u32 val; 287 288 if (lock) { 289 if (qlcnic_83xx_lock_driver(adapter)) 290 return -EBUSY; 291 } 292 293 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 294 if (flag) 295 val = val | (1 << adapter->portnum); 296 else 297 val = val & ~(1 << adapter->portnum); 298 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val); 299 300 if (lock) 301 qlcnic_83xx_unlock_driver(adapter); 302 303 return 0; 304 } 305 306 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter, 307 int time_limit) 308 { 309 u64 seconds; 310 311 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 312 if (seconds <= time_limit) 313 return 0; 314 else 315 return -EBUSY; 316 } 317 318 /** 319 * qlcnic_83xx_idc_check_reset_ack_reg 320 * 321 * @adapter: adapter structure 322 * 323 * Check ACK wait limit and clear the functions which failed to ACK 324 * 325 * Return 0 if all functions have acknowledged the reset request. 326 **/ 327 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter) 328 { 329 int timeout; 330 u32 ack, presence, val; 331 332 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 333 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 334 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 335 dev_info(&adapter->pdev->dev, 336 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence); 337 if (!((ack & presence) == presence)) { 338 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) { 339 /* Clear functions which failed to ACK */ 340 dev_info(&adapter->pdev->dev, 341 "%s: ACK wait exceeds time limit\n", __func__); 342 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 343 val = val & ~(ack ^ presence); 344 if (qlcnic_83xx_lock_driver(adapter)) 345 return -EBUSY; 346 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 347 dev_info(&adapter->pdev->dev, 348 "%s: updated drv presence reg = 0x%x\n", 349 __func__, val); 350 qlcnic_83xx_unlock_driver(adapter); 351 return 0; 352 353 } else { 354 return 1; 355 } 356 } else { 357 dev_info(&adapter->pdev->dev, 358 "%s: Reset ACK received from all functions\n", 359 __func__); 360 return 0; 361 } 362 } 363 364 /** 365 * qlcnic_83xx_idc_tx_soft_reset 366 * 367 * @adapter: adapter structure 368 * 369 * Handle context deletion and recreation request from transmit routine 370 * 371 * Returns -EBUSY or Success (0) 372 * 373 **/ 374 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter) 375 { 376 struct net_device *netdev = adapter->netdev; 377 378 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 379 return -EBUSY; 380 381 netif_device_detach(netdev); 382 qlcnic_down(adapter, netdev); 383 qlcnic_up(adapter, netdev); 384 netif_device_attach(netdev); 385 clear_bit(__QLCNIC_RESETTING, &adapter->state); 386 netdev_info(adapter->netdev, "%s: soft reset complete.\n", __func__); 387 388 return 0; 389 } 390 391 /** 392 * qlcnic_83xx_idc_detach_driver 393 * 394 * @adapter: adapter structure 395 * Detach net interface, stop TX and cleanup resources before the HW reset. 396 * Returns: None 397 * 398 **/ 399 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter) 400 { 401 int i; 402 struct net_device *netdev = adapter->netdev; 403 404 netif_device_detach(netdev); 405 qlcnic_83xx_detach_mailbox_work(adapter); 406 407 /* Disable mailbox interrupt */ 408 qlcnic_83xx_disable_mbx_intr(adapter); 409 qlcnic_down(adapter, netdev); 410 for (i = 0; i < adapter->ahw->num_msix; i++) { 411 adapter->ahw->intr_tbl[i].id = i; 412 adapter->ahw->intr_tbl[i].enabled = 0; 413 adapter->ahw->intr_tbl[i].src = 0; 414 } 415 416 if (qlcnic_sriov_pf_check(adapter)) 417 qlcnic_sriov_pf_reset(adapter); 418 } 419 420 /** 421 * qlcnic_83xx_idc_attach_driver 422 * 423 * @adapter: adapter structure 424 * 425 * Re-attach and re-enable net interface 426 * Returns: None 427 * 428 **/ 429 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter) 430 { 431 struct net_device *netdev = adapter->netdev; 432 433 if (netif_running(netdev)) { 434 if (qlcnic_up(adapter, netdev)) 435 goto done; 436 qlcnic_restore_indev_addr(netdev, NETDEV_UP); 437 } 438 done: 439 netif_device_attach(netdev); 440 } 441 442 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter, 443 int lock) 444 { 445 if (lock) { 446 if (qlcnic_83xx_lock_driver(adapter)) 447 return -EBUSY; 448 } 449 450 qlcnic_83xx_idc_clear_registers(adapter, 0); 451 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED); 452 if (lock) 453 qlcnic_83xx_unlock_driver(adapter); 454 455 qlcnic_83xx_idc_log_state_history(adapter); 456 dev_info(&adapter->pdev->dev, "Device will enter failed state\n"); 457 458 return 0; 459 } 460 461 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter, 462 int lock) 463 { 464 if (lock) { 465 if (qlcnic_83xx_lock_driver(adapter)) 466 return -EBUSY; 467 } 468 469 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT); 470 471 if (lock) 472 qlcnic_83xx_unlock_driver(adapter); 473 474 return 0; 475 } 476 477 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter, 478 int lock) 479 { 480 if (lock) { 481 if (qlcnic_83xx_lock_driver(adapter)) 482 return -EBUSY; 483 } 484 485 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 486 QLC_83XX_IDC_DEV_NEED_QUISCENT); 487 488 if (lock) 489 qlcnic_83xx_unlock_driver(adapter); 490 491 return 0; 492 } 493 494 static int 495 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock) 496 { 497 if (lock) { 498 if (qlcnic_83xx_lock_driver(adapter)) 499 return -EBUSY; 500 } 501 502 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 503 QLC_83XX_IDC_DEV_NEED_RESET); 504 505 if (lock) 506 qlcnic_83xx_unlock_driver(adapter); 507 508 return 0; 509 } 510 511 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter, 512 int lock) 513 { 514 if (lock) { 515 if (qlcnic_83xx_lock_driver(adapter)) 516 return -EBUSY; 517 } 518 519 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY); 520 if (lock) 521 qlcnic_83xx_unlock_driver(adapter); 522 523 return 0; 524 } 525 526 /** 527 * qlcnic_83xx_idc_find_reset_owner_id 528 * 529 * @adapter: adapter structure 530 * 531 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE. 532 * Within the same class, function with lowest PCI ID assumes ownership 533 * 534 * Returns: reset owner id or failure indication (-EIO) 535 * 536 **/ 537 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter) 538 { 539 u32 reg, reg1, reg2, i, j, owner, class; 540 541 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1); 542 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2); 543 owner = QLCNIC_TYPE_NIC; 544 i = 0; 545 j = 0; 546 reg = reg1; 547 548 do { 549 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3); 550 if (class == owner) 551 break; 552 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) { 553 reg = reg2; 554 j = 0; 555 } else { 556 j++; 557 } 558 559 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) { 560 if (owner == QLCNIC_TYPE_NIC) 561 owner = QLCNIC_TYPE_ISCSI; 562 else if (owner == QLCNIC_TYPE_ISCSI) 563 owner = QLCNIC_TYPE_FCOE; 564 else if (owner == QLCNIC_TYPE_FCOE) 565 return -EIO; 566 reg = reg1; 567 j = 0; 568 i = 0; 569 } 570 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS); 571 572 return i; 573 } 574 575 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock) 576 { 577 int ret = 0; 578 579 ret = qlcnic_83xx_restart_hw(adapter); 580 581 if (ret) { 582 qlcnic_83xx_idc_enter_failed_state(adapter, lock); 583 } else { 584 qlcnic_83xx_idc_clear_registers(adapter, lock); 585 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock); 586 } 587 588 return ret; 589 } 590 591 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter) 592 { 593 u32 status; 594 595 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1); 596 597 if (status & QLCNIC_RCODE_FATAL_ERROR) { 598 dev_err(&adapter->pdev->dev, 599 "peg halt status1=0x%x\n", status); 600 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) { 601 dev_err(&adapter->pdev->dev, 602 "On board active cooling fan failed. " 603 "Device has been halted.\n"); 604 dev_err(&adapter->pdev->dev, 605 "Replace the adapter.\n"); 606 return -EIO; 607 } 608 } 609 610 return 0; 611 } 612 613 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter) 614 { 615 int err; 616 617 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox); 618 qlcnic_83xx_enable_mbx_interrupt(adapter); 619 620 qlcnic_83xx_initialize_nic(adapter, 1); 621 622 err = qlcnic_sriov_pf_reinit(adapter); 623 if (err) 624 return err; 625 626 qlcnic_83xx_enable_mbx_interrupt(adapter); 627 628 if (qlcnic_83xx_configure_opmode(adapter)) { 629 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 630 return -EIO; 631 } 632 633 if (adapter->nic_ops->init_driver(adapter)) { 634 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 635 return -EIO; 636 } 637 638 if (adapter->portnum == 0) 639 qlcnic_set_drv_version(adapter); 640 641 qlcnic_dcb_get_info(adapter->dcb); 642 qlcnic_83xx_idc_attach_driver(adapter); 643 644 return 0; 645 } 646 647 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter) 648 { 649 struct qlcnic_hardware_context *ahw = adapter->ahw; 650 651 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1); 652 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 653 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 654 655 ahw->idc.quiesce_req = 0; 656 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 657 ahw->idc.err_code = 0; 658 ahw->idc.collect_dump = 0; 659 ahw->reset_context = 0; 660 adapter->tx_timeo_cnt = 0; 661 ahw->idc.delay_reset = 0; 662 663 clear_bit(__QLCNIC_RESETTING, &adapter->state); 664 } 665 666 /** 667 * qlcnic_83xx_idc_ready_state_entry 668 * 669 * @adapter: adapter structure 670 * 671 * Perform ready state initialization, this routine will get invoked only 672 * once from READY state. 673 * 674 * Returns: Error code or Success(0) 675 * 676 **/ 677 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter) 678 { 679 struct qlcnic_hardware_context *ahw = adapter->ahw; 680 681 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) { 682 qlcnic_83xx_idc_update_idc_params(adapter); 683 /* Re-attach the device if required */ 684 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) || 685 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) { 686 if (qlcnic_83xx_idc_reattach_driver(adapter)) 687 return -EIO; 688 } 689 } 690 691 return 0; 692 } 693 694 /** 695 * qlcnic_83xx_idc_vnic_pf_entry 696 * 697 * @adapter: adapter structure 698 * 699 * Ensure vNIC mode privileged function starts only after vNIC mode is 700 * enabled by management function. 701 * If vNIC mode is ready, start initialization. 702 * 703 * Returns: -EIO or 0 704 * 705 **/ 706 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter) 707 { 708 u32 state; 709 struct qlcnic_hardware_context *ahw = adapter->ahw; 710 711 /* Privileged function waits till mgmt function enables VNIC mode */ 712 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE); 713 if (state != QLCNIC_DEV_NPAR_OPER) { 714 if (!ahw->idc.vnic_wait_limit--) { 715 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 716 return -EIO; 717 } 718 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n"); 719 return -EIO; 720 721 } else { 722 /* Perform one time initialization from ready state */ 723 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) { 724 qlcnic_83xx_idc_update_idc_params(adapter); 725 726 /* If the previous state is UNKNOWN, device will be 727 already attached properly by Init routine*/ 728 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) { 729 if (qlcnic_83xx_idc_reattach_driver(adapter)) 730 return -EIO; 731 } 732 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER; 733 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n"); 734 } 735 } 736 737 return 0; 738 } 739 740 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter) 741 { 742 adapter->ahw->idc.err_code = -EIO; 743 dev_err(&adapter->pdev->dev, 744 "%s: Device in unknown state\n", __func__); 745 clear_bit(__QLCNIC_RESETTING, &adapter->state); 746 return 0; 747 } 748 749 /** 750 * qlcnic_83xx_idc_cold_state 751 * 752 * @adapter: adapter structure 753 * 754 * If HW is up and running device will enter READY state. 755 * If firmware image from host needs to be loaded, device is 756 * forced to start with the file firmware image. 757 * 758 * Returns: Error code or Success(0) 759 * 760 **/ 761 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter) 762 { 763 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0); 764 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0); 765 766 if (qlcnic_load_fw_file) { 767 qlcnic_83xx_idc_restart_hw(adapter, 0); 768 } else { 769 if (qlcnic_83xx_check_hw_status(adapter)) { 770 qlcnic_83xx_idc_enter_failed_state(adapter, 0); 771 return -EIO; 772 } else { 773 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 774 } 775 } 776 return 0; 777 } 778 779 /** 780 * qlcnic_83xx_idc_init_state 781 * 782 * @adapter: adapter structure 783 * 784 * Reset owner will restart the device from this state. 785 * Device will enter failed state if it remains 786 * in this state for more than DEV_INIT time limit. 787 * 788 * Returns: Error code or Success(0) 789 * 790 **/ 791 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter) 792 { 793 int timeout, ret = 0; 794 u32 owner; 795 796 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 797 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) { 798 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 799 if (adapter->ahw->pci_func == owner) 800 ret = qlcnic_83xx_idc_restart_hw(adapter, 1); 801 } else { 802 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout); 803 } 804 805 return ret; 806 } 807 808 /** 809 * qlcnic_83xx_idc_ready_state 810 * 811 * @adapter: adapter structure 812 * 813 * Perform IDC protocol specicifed actions after monitoring device state and 814 * events. 815 * 816 * Returns: Error code or Success(0) 817 * 818 **/ 819 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter) 820 { 821 struct qlcnic_hardware_context *ahw = adapter->ahw; 822 struct qlcnic_mailbox *mbx = ahw->mailbox; 823 int ret = 0; 824 u32 val; 825 826 /* Perform NIC configuration based ready state entry actions */ 827 if (ahw->idc.state_entry(adapter)) 828 return -EIO; 829 830 if (qlcnic_check_temp(adapter)) { 831 if (ahw->temp == QLCNIC_TEMP_PANIC) { 832 qlcnic_83xx_idc_check_fan_failure(adapter); 833 dev_err(&adapter->pdev->dev, 834 "Error: device temperature %d above limits\n", 835 adapter->ahw->temp); 836 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 837 set_bit(__QLCNIC_RESETTING, &adapter->state); 838 qlcnic_83xx_idc_detach_driver(adapter); 839 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 840 return -EIO; 841 } 842 } 843 844 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 845 ret = qlcnic_83xx_check_heartbeat(adapter); 846 if (ret) { 847 adapter->flags |= QLCNIC_FW_HANG; 848 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 849 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 850 set_bit(__QLCNIC_RESETTING, &adapter->state); 851 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 852 } else { 853 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 854 __func__); 855 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 856 } 857 return -EIO; 858 } 859 860 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) { 861 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 862 863 /* Move to need reset state and prepare for reset */ 864 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 865 return ret; 866 } 867 868 /* Check for soft reset request */ 869 if (ahw->reset_context && 870 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 871 adapter->ahw->reset_context = 0; 872 qlcnic_83xx_idc_tx_soft_reset(adapter); 873 return ret; 874 } 875 876 /* Move to need quiesce state if requested */ 877 if (adapter->ahw->idc.quiesce_req) { 878 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1); 879 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 880 return ret; 881 } 882 883 return ret; 884 } 885 886 /** 887 * qlcnic_83xx_idc_need_reset_state 888 * 889 * @adapter: adapter structure 890 * 891 * Device will remain in this state until: 892 * Reset request ACK's are recieved from all the functions 893 * Wait time exceeds max time limit 894 * 895 * Returns: Error code or Success(0) 896 * 897 **/ 898 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter) 899 { 900 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 901 int ret = 0; 902 903 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) { 904 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 905 set_bit(__QLCNIC_RESETTING, &adapter->state); 906 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 907 if (adapter->ahw->nic_mode == QLCNIC_VNIC_MODE) 908 qlcnic_83xx_disable_vnic_mode(adapter, 1); 909 910 if (qlcnic_check_diag_status(adapter)) { 911 dev_info(&adapter->pdev->dev, 912 "%s: Wait for diag completion\n", __func__); 913 adapter->ahw->idc.delay_reset = 1; 914 return 0; 915 } else { 916 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 917 qlcnic_83xx_idc_detach_driver(adapter); 918 } 919 } 920 921 if (qlcnic_check_diag_status(adapter)) { 922 dev_info(&adapter->pdev->dev, 923 "%s: Wait for diag completion\n", __func__); 924 return -1; 925 } else { 926 if (adapter->ahw->idc.delay_reset) { 927 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 928 qlcnic_83xx_idc_detach_driver(adapter); 929 adapter->ahw->idc.delay_reset = 0; 930 } 931 932 /* Check for ACK from other functions */ 933 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter); 934 if (ret) { 935 dev_info(&adapter->pdev->dev, 936 "%s: Waiting for reset ACK\n", __func__); 937 return -1; 938 } 939 } 940 941 /* Transit to INIT state and restart the HW */ 942 qlcnic_83xx_idc_enter_init_state(adapter, 1); 943 944 return ret; 945 } 946 947 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter) 948 { 949 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__); 950 return 0; 951 } 952 953 static void qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter) 954 { 955 struct qlcnic_hardware_context *ahw = adapter->ahw; 956 u32 val, owner; 957 958 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 959 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 960 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 961 if (ahw->pci_func == owner) { 962 qlcnic_83xx_stop_hw(adapter); 963 qlcnic_dump_fw(adapter); 964 } 965 } 966 967 netdev_warn(adapter->netdev, "%s: Reboot will be required to recover the adapter!!\n", 968 __func__); 969 clear_bit(__QLCNIC_RESETTING, &adapter->state); 970 ahw->idc.err_code = -EIO; 971 972 return; 973 } 974 975 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter) 976 { 977 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__); 978 return 0; 979 } 980 981 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter, 982 u32 state) 983 { 984 u32 cur, prev, next; 985 986 cur = adapter->ahw->idc.curr_state; 987 prev = adapter->ahw->idc.prev_state; 988 next = state; 989 990 if ((next < QLC_83XX_IDC_DEV_COLD) || 991 (next > QLC_83XX_IDC_DEV_QUISCENT)) { 992 dev_err(&adapter->pdev->dev, 993 "%s: curr %d, prev %d, next state %d is invalid\n", 994 __func__, cur, prev, state); 995 return 1; 996 } 997 998 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) && 999 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) { 1000 if ((next != QLC_83XX_IDC_DEV_COLD) && 1001 (next != QLC_83XX_IDC_DEV_READY)) { 1002 dev_err(&adapter->pdev->dev, 1003 "%s: failed, cur %d prev %d next %d\n", 1004 __func__, cur, prev, next); 1005 return 1; 1006 } 1007 } 1008 1009 if (next == QLC_83XX_IDC_DEV_INIT) { 1010 if ((prev != QLC_83XX_IDC_DEV_INIT) && 1011 (prev != QLC_83XX_IDC_DEV_COLD) && 1012 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) { 1013 dev_err(&adapter->pdev->dev, 1014 "%s: failed, cur %d prev %d next %d\n", 1015 __func__, cur, prev, next); 1016 return 1; 1017 } 1018 } 1019 1020 return 0; 1021 } 1022 1023 #ifdef CONFIG_QLCNIC_VXLAN 1024 #define QLC_83XX_ENCAP_TYPE_VXLAN BIT_1 1025 #define QLC_83XX_MATCH_ENCAP_ID BIT_2 1026 #define QLC_83XX_SET_VXLAN_UDP_DPORT BIT_3 1027 #define QLC_83XX_VXLAN_UDP_DPORT(PORT) ((PORT & 0xffff) << 16) 1028 1029 #define QLCNIC_ENABLE_INGRESS_ENCAP_PARSING 1 1030 #define QLCNIC_DISABLE_INGRESS_ENCAP_PARSING 0 1031 1032 static int qlcnic_set_vxlan_port(struct qlcnic_adapter *adapter) 1033 { 1034 u16 port = adapter->ahw->vxlan_port; 1035 struct qlcnic_cmd_args cmd; 1036 int ret = 0; 1037 1038 memset(&cmd, 0, sizeof(cmd)); 1039 1040 ret = qlcnic_alloc_mbx_args(&cmd, adapter, 1041 QLCNIC_CMD_INIT_NIC_FUNC); 1042 if (ret) 1043 return ret; 1044 1045 cmd.req.arg[1] = QLC_83XX_MULTI_TENANCY_INFO; 1046 cmd.req.arg[2] = QLC_83XX_ENCAP_TYPE_VXLAN | 1047 QLC_83XX_SET_VXLAN_UDP_DPORT | 1048 QLC_83XX_VXLAN_UDP_DPORT(port); 1049 1050 ret = qlcnic_issue_cmd(adapter, &cmd); 1051 if (ret) 1052 netdev_err(adapter->netdev, 1053 "Failed to set VXLAN port %d in adapter\n", 1054 port); 1055 1056 qlcnic_free_mbx_args(&cmd); 1057 1058 return ret; 1059 } 1060 1061 static int qlcnic_set_vxlan_parsing(struct qlcnic_adapter *adapter, 1062 bool state) 1063 { 1064 u16 vxlan_port = adapter->ahw->vxlan_port; 1065 struct qlcnic_cmd_args cmd; 1066 int ret = 0; 1067 1068 memset(&cmd, 0, sizeof(cmd)); 1069 1070 ret = qlcnic_alloc_mbx_args(&cmd, adapter, 1071 QLCNIC_CMD_SET_INGRESS_ENCAP); 1072 if (ret) 1073 return ret; 1074 1075 cmd.req.arg[1] = state ? QLCNIC_ENABLE_INGRESS_ENCAP_PARSING : 1076 QLCNIC_DISABLE_INGRESS_ENCAP_PARSING; 1077 1078 ret = qlcnic_issue_cmd(adapter, &cmd); 1079 if (ret) 1080 netdev_err(adapter->netdev, 1081 "Failed to %s VXLAN parsing for port %d\n", 1082 state ? "enable" : "disable", vxlan_port); 1083 else 1084 netdev_info(adapter->netdev, 1085 "%s VXLAN parsing for port %d\n", 1086 state ? "Enabled" : "Disabled", vxlan_port); 1087 1088 qlcnic_free_mbx_args(&cmd); 1089 1090 return ret; 1091 } 1092 #endif 1093 1094 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter) 1095 { 1096 if (adapter->fhash.fnum) 1097 qlcnic_prune_lb_filters(adapter); 1098 1099 #ifdef CONFIG_QLCNIC_VXLAN 1100 if (adapter->flags & QLCNIC_ADD_VXLAN_PORT) { 1101 if (qlcnic_set_vxlan_port(adapter)) 1102 return; 1103 1104 if (qlcnic_set_vxlan_parsing(adapter, true)) 1105 return; 1106 1107 adapter->flags &= ~QLCNIC_ADD_VXLAN_PORT; 1108 } else if (adapter->flags & QLCNIC_DEL_VXLAN_PORT) { 1109 if (qlcnic_set_vxlan_parsing(adapter, false)) 1110 return; 1111 1112 adapter->ahw->vxlan_port = 0; 1113 adapter->flags &= ~QLCNIC_DEL_VXLAN_PORT; 1114 } 1115 #endif 1116 } 1117 1118 /** 1119 * qlcnic_83xx_idc_poll_dev_state 1120 * 1121 * @work: kernel work queue structure used to schedule the function 1122 * 1123 * Poll device state periodically and perform state specific 1124 * actions defined by Inter Driver Communication (IDC) protocol. 1125 * 1126 * Returns: None 1127 * 1128 **/ 1129 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work) 1130 { 1131 struct qlcnic_adapter *adapter; 1132 u32 state; 1133 1134 adapter = container_of(work, struct qlcnic_adapter, fw_work.work); 1135 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1136 1137 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1138 qlcnic_83xx_idc_log_state_history(adapter); 1139 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1140 } else { 1141 adapter->ahw->idc.curr_state = state; 1142 } 1143 1144 switch (adapter->ahw->idc.curr_state) { 1145 case QLC_83XX_IDC_DEV_READY: 1146 qlcnic_83xx_idc_ready_state(adapter); 1147 break; 1148 case QLC_83XX_IDC_DEV_NEED_RESET: 1149 qlcnic_83xx_idc_need_reset_state(adapter); 1150 break; 1151 case QLC_83XX_IDC_DEV_NEED_QUISCENT: 1152 qlcnic_83xx_idc_need_quiesce_state(adapter); 1153 break; 1154 case QLC_83XX_IDC_DEV_FAILED: 1155 qlcnic_83xx_idc_failed_state(adapter); 1156 return; 1157 case QLC_83XX_IDC_DEV_INIT: 1158 qlcnic_83xx_idc_init_state(adapter); 1159 break; 1160 case QLC_83XX_IDC_DEV_QUISCENT: 1161 qlcnic_83xx_idc_quiesce_state(adapter); 1162 break; 1163 default: 1164 qlcnic_83xx_idc_unknown_state(adapter); 1165 return; 1166 } 1167 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state; 1168 qlcnic_83xx_periodic_tasks(adapter); 1169 1170 /* Re-schedule the function */ 1171 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status)) 1172 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 1173 adapter->ahw->idc.delay); 1174 } 1175 1176 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter) 1177 { 1178 u32 idc_params, val; 1179 1180 if (qlcnic_83xx_lockless_flash_read32(adapter, 1181 QLC_83XX_IDC_FLASH_PARAM_ADDR, 1182 (u8 *)&idc_params, 1)) { 1183 dev_info(&adapter->pdev->dev, 1184 "%s:failed to get IDC params from flash\n", __func__); 1185 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 1186 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 1187 } else { 1188 adapter->dev_init_timeo = idc_params & 0xFFFF; 1189 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF); 1190 } 1191 1192 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1193 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN; 1194 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 1195 adapter->ahw->idc.err_code = 0; 1196 adapter->ahw->idc.collect_dump = 0; 1197 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states; 1198 1199 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1200 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1201 1202 /* Check if reset recovery is disabled */ 1203 if (!qlcnic_auto_fw_reset) { 1204 /* Propagate do not reset request to other functions */ 1205 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1206 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1207 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1208 } 1209 } 1210 1211 static int 1212 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter) 1213 { 1214 u32 state, val; 1215 1216 if (qlcnic_83xx_lock_driver(adapter)) 1217 return -EIO; 1218 1219 /* Clear driver lock register */ 1220 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0); 1221 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) { 1222 qlcnic_83xx_unlock_driver(adapter); 1223 return -EIO; 1224 } 1225 1226 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1227 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1228 qlcnic_83xx_unlock_driver(adapter); 1229 return -EIO; 1230 } 1231 1232 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) { 1233 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 1234 QLC_83XX_IDC_DEV_COLD); 1235 state = QLC_83XX_IDC_DEV_COLD; 1236 } 1237 1238 adapter->ahw->idc.curr_state = state; 1239 /* First to load function should cold boot the device */ 1240 if (state == QLC_83XX_IDC_DEV_COLD) 1241 qlcnic_83xx_idc_cold_state_handler(adapter); 1242 1243 /* Check if reset recovery is enabled */ 1244 if (qlcnic_auto_fw_reset) { 1245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1246 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1247 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1248 } 1249 1250 qlcnic_83xx_unlock_driver(adapter); 1251 1252 return 0; 1253 } 1254 1255 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter) 1256 { 1257 int ret = -EIO; 1258 1259 qlcnic_83xx_setup_idc_parameters(adapter); 1260 1261 if (qlcnic_83xx_get_reset_instruction_template(adapter)) 1262 return ret; 1263 1264 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) { 1265 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter)) 1266 return -EIO; 1267 } else { 1268 if (qlcnic_83xx_idc_check_major_version(adapter)) 1269 return -EIO; 1270 } 1271 1272 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 1273 1274 return 0; 1275 } 1276 1277 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter) 1278 { 1279 int id; 1280 u32 val; 1281 1282 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 1283 usleep_range(10000, 11000); 1284 1285 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1286 id = id & 0xFF; 1287 1288 if (id == adapter->portnum) { 1289 dev_err(&adapter->pdev->dev, 1290 "%s: wait for lock recovery.. %d\n", __func__, id); 1291 msleep(20); 1292 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1293 id = id & 0xFF; 1294 } 1295 1296 /* Clear driver presence bit */ 1297 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 1298 val = val & ~(1 << adapter->portnum); 1299 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 1300 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1301 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1302 1303 cancel_delayed_work_sync(&adapter->fw_work); 1304 } 1305 1306 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key) 1307 { 1308 u32 val; 1309 1310 if (qlcnic_sriov_vf_check(adapter)) 1311 return; 1312 1313 if (qlcnic_83xx_lock_driver(adapter)) { 1314 dev_err(&adapter->pdev->dev, 1315 "%s:failed, please retry\n", __func__); 1316 return; 1317 } 1318 1319 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1320 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 1321 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 1322 __func__); 1323 qlcnic_83xx_idc_enter_failed_state(adapter, 0); 1324 qlcnic_83xx_unlock_driver(adapter); 1325 return; 1326 } 1327 1328 if (key == QLCNIC_FORCE_FW_RESET) { 1329 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1330 val = val | QLC_83XX_IDC_GRACEFULL_RESET; 1331 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1332 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) { 1333 adapter->ahw->idc.collect_dump = 1; 1334 } 1335 1336 qlcnic_83xx_unlock_driver(adapter); 1337 return; 1338 } 1339 1340 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter) 1341 { 1342 u8 *p_cache; 1343 u32 src, size; 1344 u64 dest; 1345 int ret = -EIO; 1346 1347 src = QLC_83XX_BOOTLOADER_FLASH_ADDR; 1348 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR); 1349 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE); 1350 1351 /* alignment check */ 1352 if (size & 0xF) 1353 size = (size + 16) & ~0xF; 1354 1355 p_cache = vzalloc(size); 1356 if (p_cache == NULL) 1357 return -ENOMEM; 1358 1359 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache, 1360 size / sizeof(u32)); 1361 if (ret) { 1362 vfree(p_cache); 1363 return ret; 1364 } 1365 /* 16 byte write to MS memory */ 1366 ret = qlcnic_ms_mem_write128(adapter, dest, (u32 *)p_cache, 1367 size / 16); 1368 if (ret) { 1369 vfree(p_cache); 1370 return ret; 1371 } 1372 vfree(p_cache); 1373 1374 return ret; 1375 } 1376 1377 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter) 1378 { 1379 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info; 1380 const struct firmware *fw = fw_info->fw; 1381 u32 dest, *p_cache; 1382 int i, ret = -EIO; 1383 u8 data[16]; 1384 size_t size; 1385 u64 addr; 1386 1387 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR); 1388 size = (fw->size & ~0xF); 1389 p_cache = (u32 *)fw->data; 1390 addr = (u64)dest; 1391 1392 ret = qlcnic_ms_mem_write128(adapter, addr, 1393 p_cache, size / 16); 1394 if (ret) { 1395 dev_err(&adapter->pdev->dev, "MS memory write failed\n"); 1396 release_firmware(fw); 1397 fw_info->fw = NULL; 1398 return -EIO; 1399 } 1400 1401 /* alignment check */ 1402 if (fw->size & 0xF) { 1403 addr = dest + size; 1404 for (i = 0; i < (fw->size & 0xF); i++) 1405 data[i] = fw->data[size + i]; 1406 for (; i < 16; i++) 1407 data[i] = 0; 1408 ret = qlcnic_ms_mem_write128(adapter, addr, 1409 (u32 *)data, 1); 1410 if (ret) { 1411 dev_err(&adapter->pdev->dev, 1412 "MS memory write failed\n"); 1413 release_firmware(fw); 1414 fw_info->fw = NULL; 1415 return -EIO; 1416 } 1417 } 1418 release_firmware(fw); 1419 fw_info->fw = NULL; 1420 1421 return 0; 1422 } 1423 1424 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) 1425 { 1426 int i, j; 1427 u32 val = 0, val1 = 0, reg = 0; 1428 int err = 0; 1429 1430 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err); 1431 if (err == -EIO) 1432 return; 1433 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val); 1434 1435 for (j = 0; j < 2; j++) { 1436 if (j == 0) { 1437 dev_info(&adapter->pdev->dev, 1438 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:"); 1439 reg = QLC_83XX_PORT0_THRESHOLD; 1440 } else if (j == 1) { 1441 dev_info(&adapter->pdev->dev, 1442 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:"); 1443 reg = QLC_83XX_PORT1_THRESHOLD; 1444 } 1445 for (i = 0; i < 8; i++) { 1446 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1447 if (err == -EIO) 1448 return; 1449 dev_info(&adapter->pdev->dev, "0x%x ", val); 1450 } 1451 dev_info(&adapter->pdev->dev, "\n"); 1452 } 1453 1454 for (j = 0; j < 2; j++) { 1455 if (j == 0) { 1456 dev_info(&adapter->pdev->dev, 1457 "Port 0 RxB TC Max Cell Registers[4..1]:"); 1458 reg = QLC_83XX_PORT0_TC_MC_REG; 1459 } else if (j == 1) { 1460 dev_info(&adapter->pdev->dev, 1461 "Port 1 RxB TC Max Cell Registers[4..1]:"); 1462 reg = QLC_83XX_PORT1_TC_MC_REG; 1463 } 1464 for (i = 0; i < 4; i++) { 1465 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1466 if (err == -EIO) 1467 return; 1468 dev_info(&adapter->pdev->dev, "0x%x ", val); 1469 } 1470 dev_info(&adapter->pdev->dev, "\n"); 1471 } 1472 1473 for (j = 0; j < 2; j++) { 1474 if (j == 0) { 1475 dev_info(&adapter->pdev->dev, 1476 "Port 0 RxB Rx TC Stats[TC7..TC0]:"); 1477 reg = QLC_83XX_PORT0_TC_STATS; 1478 } else if (j == 1) { 1479 dev_info(&adapter->pdev->dev, 1480 "Port 1 RxB Rx TC Stats[TC7..TC0]:"); 1481 reg = QLC_83XX_PORT1_TC_STATS; 1482 } 1483 for (i = 7; i >= 0; i--) { 1484 val = QLCRD32(adapter, reg, &err); 1485 if (err == -EIO) 1486 return; 1487 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ 1488 QLCWR32(adapter, reg, (val | (i << 29))); 1489 val = QLCRD32(adapter, reg, &err); 1490 if (err == -EIO) 1491 return; 1492 dev_info(&adapter->pdev->dev, "0x%x ", val); 1493 } 1494 dev_info(&adapter->pdev->dev, "\n"); 1495 } 1496 1497 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err); 1498 if (err == -EIO) 1499 return; 1500 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err); 1501 if (err == -EIO) 1502 return; 1503 dev_info(&adapter->pdev->dev, 1504 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n", 1505 val, val1); 1506 } 1507 1508 1509 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter) 1510 { 1511 u32 reg = 0, i, j; 1512 1513 if (qlcnic_83xx_lock_driver(adapter)) { 1514 dev_err(&adapter->pdev->dev, 1515 "%s:failed to acquire driver lock\n", __func__); 1516 return; 1517 } 1518 1519 qlcnic_83xx_dump_pause_control_regs(adapter); 1520 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0); 1521 1522 for (j = 0; j < 2; j++) { 1523 if (j == 0) 1524 reg = QLC_83XX_PORT0_THRESHOLD; 1525 else if (j == 1) 1526 reg = QLC_83XX_PORT1_THRESHOLD; 1527 1528 for (i = 0; i < 8; i++) 1529 QLCWR32(adapter, reg + (i * 0x4), 0x0); 1530 } 1531 1532 for (j = 0; j < 2; j++) { 1533 if (j == 0) 1534 reg = QLC_83XX_PORT0_TC_MC_REG; 1535 else if (j == 1) 1536 reg = QLC_83XX_PORT1_TC_MC_REG; 1537 1538 for (i = 0; i < 4; i++) 1539 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF); 1540 } 1541 1542 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0); 1543 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0); 1544 dev_info(&adapter->pdev->dev, 1545 "Disabled pause frames successfully on all ports\n"); 1546 qlcnic_83xx_unlock_driver(adapter); 1547 } 1548 1549 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter) 1550 { 1551 QLCWR32(adapter, QLC_83XX_RESET_REG, 0); 1552 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0); 1553 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0); 1554 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0); 1555 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0); 1556 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0); 1557 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0); 1558 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0); 1559 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1); 1560 } 1561 1562 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev) 1563 { 1564 u32 heartbeat, peg_status; 1565 int retries, ret = -EIO, err = 0; 1566 1567 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT; 1568 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev, 1569 QLCNIC_PEG_ALIVE_COUNTER); 1570 1571 do { 1572 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS); 1573 heartbeat = QLC_SHARED_REG_RD32(p_dev, 1574 QLCNIC_PEG_ALIVE_COUNTER); 1575 if (heartbeat != p_dev->heartbeat) { 1576 ret = QLCNIC_RCODE_SUCCESS; 1577 break; 1578 } 1579 } while (--retries); 1580 1581 if (ret) { 1582 dev_err(&p_dev->pdev->dev, "firmware hang detected\n"); 1583 qlcnic_83xx_take_eport_out_of_reset(p_dev); 1584 qlcnic_83xx_disable_pause_frames(p_dev); 1585 peg_status = QLC_SHARED_REG_RD32(p_dev, 1586 QLCNIC_PEG_HALT_STATUS1); 1587 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n" 1588 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n" 1589 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n" 1590 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n" 1591 "PEG_NET_4_PC: 0x%x\n", peg_status, 1592 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2), 1593 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err), 1594 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err), 1595 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err), 1596 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err), 1597 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err)); 1598 1599 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67) 1600 dev_err(&p_dev->pdev->dev, 1601 "Device is being reset err code 0x00006700.\n"); 1602 } 1603 1604 return ret; 1605 } 1606 1607 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev) 1608 { 1609 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT; 1610 u32 val; 1611 1612 do { 1613 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE); 1614 if (val == QLC_83XX_CMDPEG_COMPLETE) 1615 return 0; 1616 msleep(QLCNIC_CMDPEG_CHECK_DELAY); 1617 } while (--retries); 1618 1619 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val); 1620 return -EIO; 1621 } 1622 1623 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev) 1624 { 1625 int err; 1626 1627 err = qlcnic_83xx_check_cmd_peg_status(p_dev); 1628 if (err) 1629 return err; 1630 1631 err = qlcnic_83xx_check_heartbeat(p_dev); 1632 if (err) 1633 return err; 1634 1635 return err; 1636 } 1637 1638 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr, 1639 int duration, u32 mask, u32 status) 1640 { 1641 int timeout_error, err = 0; 1642 u32 value; 1643 u8 retries; 1644 1645 value = QLCRD32(p_dev, addr, &err); 1646 if (err == -EIO) 1647 return err; 1648 retries = duration / 10; 1649 1650 do { 1651 if ((value & mask) != status) { 1652 timeout_error = 1; 1653 msleep(duration / 10); 1654 value = QLCRD32(p_dev, addr, &err); 1655 if (err == -EIO) 1656 return err; 1657 } else { 1658 timeout_error = 0; 1659 break; 1660 } 1661 } while (retries--); 1662 1663 if (timeout_error) { 1664 p_dev->ahw->reset.seq_error++; 1665 dev_err(&p_dev->pdev->dev, 1666 "%s: Timeout Err, entry_num = %d\n", 1667 __func__, p_dev->ahw->reset.seq_index); 1668 dev_err(&p_dev->pdev->dev, 1669 "0x%08x 0x%08x 0x%08x\n", 1670 value, mask, status); 1671 } 1672 1673 return timeout_error; 1674 } 1675 1676 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev) 1677 { 1678 u32 sum = 0; 1679 u16 *buff = (u16 *)p_dev->ahw->reset.buff; 1680 int count = p_dev->ahw->reset.hdr->size / sizeof(u16); 1681 1682 while (count-- > 0) 1683 sum += *buff++; 1684 1685 while (sum >> 16) 1686 sum = (sum & 0xFFFF) + (sum >> 16); 1687 1688 if (~sum) { 1689 return 0; 1690 } else { 1691 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1692 return -1; 1693 } 1694 } 1695 1696 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev) 1697 { 1698 struct qlcnic_hardware_context *ahw = p_dev->ahw; 1699 u32 addr, count, prev_ver, curr_ver; 1700 u8 *p_buff; 1701 1702 if (ahw->reset.buff != NULL) { 1703 prev_ver = p_dev->fw_version; 1704 curr_ver = qlcnic_83xx_get_fw_version(p_dev); 1705 if (curr_ver > prev_ver) 1706 kfree(ahw->reset.buff); 1707 else 1708 return 0; 1709 } 1710 1711 ahw->reset.seq_error = 0; 1712 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL); 1713 if (p_dev->ahw->reset.buff == NULL) 1714 return -ENOMEM; 1715 1716 p_buff = p_dev->ahw->reset.buff; 1717 addr = QLC_83XX_RESET_TEMPLATE_ADDR; 1718 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32); 1719 1720 /* Copy template header from flash */ 1721 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1722 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1723 return -EIO; 1724 } 1725 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff; 1726 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size; 1727 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1728 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32); 1729 1730 /* Copy rest of the template */ 1731 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1732 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1733 return -EIO; 1734 } 1735 1736 if (qlcnic_83xx_reset_template_checksum(p_dev)) 1737 return -EIO; 1738 /* Get Stop, Start and Init command offsets */ 1739 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset; 1740 ahw->reset.start_offset = ahw->reset.buff + 1741 ahw->reset.hdr->start_offset; 1742 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1743 return 0; 1744 } 1745 1746 /* Read Write HW register command */ 1747 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev, 1748 u32 raddr, u32 waddr) 1749 { 1750 int err = 0; 1751 u32 value; 1752 1753 value = QLCRD32(p_dev, raddr, &err); 1754 if (err == -EIO) 1755 return; 1756 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1757 } 1758 1759 /* Read Modify Write HW register command */ 1760 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev, 1761 u32 raddr, u32 waddr, 1762 struct qlc_83xx_rmw *p_rmw_hdr) 1763 { 1764 int err = 0; 1765 u32 value; 1766 1767 if (p_rmw_hdr->index_a) { 1768 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a]; 1769 } else { 1770 value = QLCRD32(p_dev, raddr, &err); 1771 if (err == -EIO) 1772 return; 1773 } 1774 1775 value &= p_rmw_hdr->mask; 1776 value <<= p_rmw_hdr->shl; 1777 value >>= p_rmw_hdr->shr; 1778 value |= p_rmw_hdr->or_value; 1779 value ^= p_rmw_hdr->xor_value; 1780 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1781 } 1782 1783 /* Write HW register command */ 1784 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev, 1785 struct qlc_83xx_entry_hdr *p_hdr) 1786 { 1787 int i; 1788 struct qlc_83xx_entry *entry; 1789 1790 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1791 sizeof(struct qlc_83xx_entry_hdr)); 1792 1793 for (i = 0; i < p_hdr->count; i++, entry++) { 1794 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1, 1795 entry->arg2); 1796 if (p_hdr->delay) 1797 udelay((u32)(p_hdr->delay)); 1798 } 1799 } 1800 1801 /* Read and Write instruction */ 1802 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev, 1803 struct qlc_83xx_entry_hdr *p_hdr) 1804 { 1805 int i; 1806 struct qlc_83xx_entry *entry; 1807 1808 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1809 sizeof(struct qlc_83xx_entry_hdr)); 1810 1811 for (i = 0; i < p_hdr->count; i++, entry++) { 1812 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1, 1813 entry->arg2); 1814 if (p_hdr->delay) 1815 udelay((u32)(p_hdr->delay)); 1816 } 1817 } 1818 1819 /* Poll HW register command */ 1820 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev, 1821 struct qlc_83xx_entry_hdr *p_hdr) 1822 { 1823 long delay; 1824 struct qlc_83xx_entry *entry; 1825 struct qlc_83xx_poll *poll; 1826 int i, err = 0; 1827 unsigned long arg1, arg2; 1828 1829 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1830 sizeof(struct qlc_83xx_entry_hdr)); 1831 1832 entry = (struct qlc_83xx_entry *)((char *)poll + 1833 sizeof(struct qlc_83xx_poll)); 1834 delay = (long)p_hdr->delay; 1835 1836 if (!delay) { 1837 for (i = 0; i < p_hdr->count; i++, entry++) 1838 qlcnic_83xx_poll_reg(p_dev, entry->arg1, 1839 delay, poll->mask, 1840 poll->status); 1841 } else { 1842 for (i = 0; i < p_hdr->count; i++, entry++) { 1843 arg1 = entry->arg1; 1844 arg2 = entry->arg2; 1845 if (delay) { 1846 if (qlcnic_83xx_poll_reg(p_dev, 1847 arg1, delay, 1848 poll->mask, 1849 poll->status)){ 1850 QLCRD32(p_dev, arg1, &err); 1851 if (err == -EIO) 1852 return; 1853 QLCRD32(p_dev, arg2, &err); 1854 if (err == -EIO) 1855 return; 1856 } 1857 } 1858 } 1859 } 1860 } 1861 1862 /* Poll and write HW register command */ 1863 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev, 1864 struct qlc_83xx_entry_hdr *p_hdr) 1865 { 1866 int i; 1867 long delay; 1868 struct qlc_83xx_quad_entry *entry; 1869 struct qlc_83xx_poll *poll; 1870 1871 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1872 sizeof(struct qlc_83xx_entry_hdr)); 1873 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1874 sizeof(struct qlc_83xx_poll)); 1875 delay = (long)p_hdr->delay; 1876 1877 for (i = 0; i < p_hdr->count; i++, entry++) { 1878 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr, 1879 entry->dr_value); 1880 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1881 entry->ar_value); 1882 if (delay) 1883 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1884 poll->mask, poll->status); 1885 } 1886 } 1887 1888 /* Read Modify Write register command */ 1889 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev, 1890 struct qlc_83xx_entry_hdr *p_hdr) 1891 { 1892 int i; 1893 struct qlc_83xx_entry *entry; 1894 struct qlc_83xx_rmw *rmw_hdr; 1895 1896 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr + 1897 sizeof(struct qlc_83xx_entry_hdr)); 1898 1899 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr + 1900 sizeof(struct qlc_83xx_rmw)); 1901 1902 for (i = 0; i < p_hdr->count; i++, entry++) { 1903 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1, 1904 entry->arg2, rmw_hdr); 1905 if (p_hdr->delay) 1906 udelay((u32)(p_hdr->delay)); 1907 } 1908 } 1909 1910 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr) 1911 { 1912 if (p_hdr->delay) 1913 mdelay((u32)((long)p_hdr->delay)); 1914 } 1915 1916 /* Read and poll register command */ 1917 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev, 1918 struct qlc_83xx_entry_hdr *p_hdr) 1919 { 1920 long delay; 1921 int index, i, j, err; 1922 struct qlc_83xx_quad_entry *entry; 1923 struct qlc_83xx_poll *poll; 1924 unsigned long addr; 1925 1926 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1927 sizeof(struct qlc_83xx_entry_hdr)); 1928 1929 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1930 sizeof(struct qlc_83xx_poll)); 1931 delay = (long)p_hdr->delay; 1932 1933 for (i = 0; i < p_hdr->count; i++, entry++) { 1934 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1935 entry->ar_value); 1936 if (delay) { 1937 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1938 poll->mask, poll->status)){ 1939 index = p_dev->ahw->reset.array_index; 1940 addr = entry->dr_addr; 1941 j = QLCRD32(p_dev, addr, &err); 1942 if (err == -EIO) 1943 return; 1944 1945 p_dev->ahw->reset.array[index++] = j; 1946 1947 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES) 1948 p_dev->ahw->reset.array_index = 1; 1949 } 1950 } 1951 } 1952 } 1953 1954 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev) 1955 { 1956 p_dev->ahw->reset.seq_end = 1; 1957 } 1958 1959 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev) 1960 { 1961 p_dev->ahw->reset.template_end = 1; 1962 if (p_dev->ahw->reset.seq_error == 0) 1963 dev_err(&p_dev->pdev->dev, 1964 "HW restart process completed successfully.\n"); 1965 else 1966 dev_err(&p_dev->pdev->dev, 1967 "HW restart completed with timeout errors.\n"); 1968 } 1969 1970 /** 1971 * qlcnic_83xx_exec_template_cmd 1972 * 1973 * @p_dev: adapter structure 1974 * @p_buff: Poiter to instruction template 1975 * 1976 * Template provides instructions to stop, restart and initalize firmware. 1977 * These instructions are abstracted as a series of read, write and 1978 * poll operations on hardware registers. Register information and operation 1979 * specifics are not exposed to the driver. Driver reads the template from 1980 * flash and executes the instructions located at pre-defined offsets. 1981 * 1982 * Returns: None 1983 * */ 1984 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev, 1985 char *p_buff) 1986 { 1987 int index, entries; 1988 struct qlc_83xx_entry_hdr *p_hdr; 1989 char *entry = p_buff; 1990 1991 p_dev->ahw->reset.seq_end = 0; 1992 p_dev->ahw->reset.template_end = 0; 1993 entries = p_dev->ahw->reset.hdr->entries; 1994 index = p_dev->ahw->reset.seq_index; 1995 1996 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) { 1997 p_hdr = (struct qlc_83xx_entry_hdr *)entry; 1998 1999 switch (p_hdr->cmd) { 2000 case QLC_83XX_OPCODE_NOP: 2001 break; 2002 case QLC_83XX_OPCODE_WRITE_LIST: 2003 qlcnic_83xx_write_list(p_dev, p_hdr); 2004 break; 2005 case QLC_83XX_OPCODE_READ_WRITE_LIST: 2006 qlcnic_83xx_read_write_list(p_dev, p_hdr); 2007 break; 2008 case QLC_83XX_OPCODE_POLL_LIST: 2009 qlcnic_83xx_poll_list(p_dev, p_hdr); 2010 break; 2011 case QLC_83XX_OPCODE_POLL_WRITE_LIST: 2012 qlcnic_83xx_poll_write_list(p_dev, p_hdr); 2013 break; 2014 case QLC_83XX_OPCODE_READ_MODIFY_WRITE: 2015 qlcnic_83xx_read_modify_write(p_dev, p_hdr); 2016 break; 2017 case QLC_83XX_OPCODE_SEQ_PAUSE: 2018 qlcnic_83xx_pause(p_hdr); 2019 break; 2020 case QLC_83XX_OPCODE_SEQ_END: 2021 qlcnic_83xx_seq_end(p_dev); 2022 break; 2023 case QLC_83XX_OPCODE_TMPL_END: 2024 qlcnic_83xx_template_end(p_dev); 2025 break; 2026 case QLC_83XX_OPCODE_POLL_READ_LIST: 2027 qlcnic_83xx_poll_read_list(p_dev, p_hdr); 2028 break; 2029 default: 2030 dev_err(&p_dev->pdev->dev, 2031 "%s: Unknown opcode 0x%04x in template %d\n", 2032 __func__, p_hdr->cmd, index); 2033 break; 2034 } 2035 entry += p_hdr->size; 2036 } 2037 p_dev->ahw->reset.seq_index = index; 2038 } 2039 2040 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev) 2041 { 2042 p_dev->ahw->reset.seq_index = 0; 2043 2044 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset); 2045 if (p_dev->ahw->reset.seq_end != 1) 2046 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 2047 } 2048 2049 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev) 2050 { 2051 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset); 2052 if (p_dev->ahw->reset.template_end != 1) 2053 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 2054 } 2055 2056 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev) 2057 { 2058 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset); 2059 if (p_dev->ahw->reset.seq_end != 1) 2060 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 2061 } 2062 2063 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter) 2064 { 2065 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info; 2066 int err = -EIO; 2067 2068 if (request_firmware(&fw_info->fw, fw_info->fw_file_name, 2069 &(adapter->pdev->dev))) { 2070 dev_err(&adapter->pdev->dev, 2071 "No file FW image, loading flash FW image.\n"); 2072 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 2073 QLC_83XX_BOOT_FROM_FLASH); 2074 } else { 2075 if (qlcnic_83xx_copy_fw_file(adapter)) 2076 return err; 2077 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 2078 QLC_83XX_BOOT_FROM_FILE); 2079 } 2080 2081 return 0; 2082 } 2083 2084 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter) 2085 { 2086 u32 val; 2087 int err = -EIO; 2088 2089 qlcnic_83xx_stop_hw(adapter); 2090 2091 /* Collect FW register dump if required */ 2092 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 2093 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET)) 2094 qlcnic_dump_fw(adapter); 2095 2096 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 2097 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 2098 __func__); 2099 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 2100 return err; 2101 } 2102 2103 qlcnic_83xx_init_hw(adapter); 2104 2105 if (qlcnic_83xx_copy_bootloader(adapter)) 2106 return err; 2107 /* Boot either flash image or firmware image from host file system */ 2108 if (qlcnic_load_fw_file) { 2109 if (qlcnic_83xx_load_fw_image_from_host(adapter)) 2110 return err; 2111 } else { 2112 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 2113 QLC_83XX_BOOT_FROM_FLASH); 2114 } 2115 2116 qlcnic_83xx_start_hw(adapter); 2117 if (qlcnic_83xx_check_hw_status(adapter)) 2118 return -EIO; 2119 2120 return 0; 2121 } 2122 2123 static int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter) 2124 { 2125 int err; 2126 struct qlcnic_info nic_info; 2127 struct qlcnic_hardware_context *ahw = adapter->ahw; 2128 2129 memset(&nic_info, 0, sizeof(struct qlcnic_info)); 2130 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func); 2131 if (err) 2132 return -EIO; 2133 2134 ahw->physical_port = (u8) nic_info.phys_port; 2135 ahw->switch_mode = nic_info.switch_mode; 2136 ahw->max_tx_ques = nic_info.max_tx_ques; 2137 ahw->max_rx_ques = nic_info.max_rx_ques; 2138 ahw->capabilities = nic_info.capabilities; 2139 ahw->max_mac_filters = nic_info.max_mac_filters; 2140 ahw->max_mtu = nic_info.max_mtu; 2141 2142 /* eSwitch capability indicates vNIC mode. 2143 * vNIC and SRIOV are mutually exclusive operational modes. 2144 * If SR-IOV capability is detected, SR-IOV physical function 2145 * will get initialized in default mode. 2146 * SR-IOV virtual function initialization follows a 2147 * different code path and opmode. 2148 * SRIOV mode has precedence over vNIC mode. 2149 */ 2150 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) 2151 return QLC_83XX_DEFAULT_OPMODE; 2152 2153 if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY) 2154 return QLCNIC_VNIC_MODE; 2155 2156 return QLC_83XX_DEFAULT_OPMODE; 2157 } 2158 2159 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter) 2160 { 2161 struct qlcnic_hardware_context *ahw = adapter->ahw; 2162 u16 max_sds_rings, max_tx_rings; 2163 int ret; 2164 2165 ret = qlcnic_83xx_get_nic_configuration(adapter); 2166 if (ret == -EIO) 2167 return -EIO; 2168 2169 if (ret == QLCNIC_VNIC_MODE) { 2170 ahw->nic_mode = QLCNIC_VNIC_MODE; 2171 2172 if (qlcnic_83xx_config_vnic_opmode(adapter)) 2173 return -EIO; 2174 2175 max_sds_rings = QLCNIC_MAX_VNIC_SDS_RINGS; 2176 max_tx_rings = QLCNIC_MAX_VNIC_TX_RINGS; 2177 } else if (ret == QLC_83XX_DEFAULT_OPMODE) { 2178 ahw->nic_mode = QLCNIC_DEFAULT_MODE; 2179 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver; 2180 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry; 2181 max_sds_rings = QLCNIC_MAX_SDS_RINGS; 2182 max_tx_rings = QLCNIC_MAX_TX_RINGS; 2183 } else { 2184 dev_err(&adapter->pdev->dev, "%s: Invalid opmode %d\n", 2185 __func__, ret); 2186 return -EIO; 2187 } 2188 2189 adapter->max_sds_rings = min(ahw->max_rx_ques, max_sds_rings); 2190 adapter->max_tx_rings = min(ahw->max_tx_ques, max_tx_rings); 2191 2192 return 0; 2193 } 2194 2195 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter) 2196 { 2197 struct qlcnic_hardware_context *ahw = adapter->ahw; 2198 2199 if (ahw->port_type == QLCNIC_XGBE) { 2200 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G; 2201 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G; 2202 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2203 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2204 2205 } else if (ahw->port_type == QLCNIC_GBE) { 2206 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G; 2207 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2208 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2209 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G; 2210 } 2211 adapter->num_txd = MAX_CMD_DESCRIPTORS; 2212 adapter->max_rds_rings = MAX_RDS_RINGS; 2213 } 2214 2215 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter) 2216 { 2217 int err = -EIO; 2218 2219 qlcnic_83xx_get_minidump_template(adapter); 2220 if (qlcnic_83xx_get_port_info(adapter)) 2221 return err; 2222 2223 qlcnic_83xx_config_buff_descriptors(adapter); 2224 adapter->ahw->msix_supported = !!qlcnic_use_msi_x; 2225 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED; 2226 2227 dev_info(&adapter->pdev->dev, "HAL Version: %d\n", 2228 adapter->ahw->fw_hal_version); 2229 2230 return 0; 2231 } 2232 2233 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1)) 2234 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter) 2235 { 2236 struct qlcnic_cmd_args cmd; 2237 u32 presence_mask, audit_mask; 2238 int status; 2239 2240 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 2241 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 2242 2243 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) { 2244 status = qlcnic_alloc_mbx_args(&cmd, adapter, 2245 QLCNIC_CMD_STOP_NIC_FUNC); 2246 if (status) 2247 return; 2248 2249 cmd.req.arg[1] = BIT_31; 2250 status = qlcnic_issue_cmd(adapter, &cmd); 2251 if (status) 2252 dev_err(&adapter->pdev->dev, 2253 "Failed to clean up the function resources\n"); 2254 qlcnic_free_mbx_args(&cmd); 2255 } 2256 } 2257 2258 static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter) 2259 { 2260 struct qlcnic_hardware_context *ahw = adapter->ahw; 2261 struct pci_dev *pdev = adapter->pdev; 2262 struct qlc_83xx_fw_info *fw_info; 2263 int err = 0; 2264 2265 ahw->fw_info = kzalloc(sizeof(*fw_info), GFP_KERNEL); 2266 if (!ahw->fw_info) { 2267 err = -ENOMEM; 2268 } else { 2269 fw_info = ahw->fw_info; 2270 switch (pdev->device) { 2271 case PCI_DEVICE_ID_QLOGIC_QLE834X: 2272 strncpy(fw_info->fw_file_name, QLC_83XX_FW_FILE_NAME, 2273 QLC_FW_FILE_NAME_LEN); 2274 break; 2275 case PCI_DEVICE_ID_QLOGIC_QLE844X: 2276 strncpy(fw_info->fw_file_name, QLC_84XX_FW_FILE_NAME, 2277 QLC_FW_FILE_NAME_LEN); 2278 break; 2279 default: 2280 dev_err(&pdev->dev, "%s: Invalid device id\n", 2281 __func__); 2282 err = -EINVAL; 2283 break; 2284 } 2285 } 2286 2287 return err; 2288 } 2289 2290 static void qlcnic_83xx_init_rings(struct qlcnic_adapter *adapter) 2291 { 2292 u8 rx_cnt = QLCNIC_DEF_SDS_RINGS; 2293 u8 tx_cnt = QLCNIC_DEF_TX_RINGS; 2294 2295 adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS; 2296 adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS; 2297 2298 if (!adapter->ahw->msix_supported) { 2299 rx_cnt = QLCNIC_SINGLE_RING; 2300 tx_cnt = QLCNIC_SINGLE_RING; 2301 } 2302 2303 /* compute and set drv sds rings */ 2304 qlcnic_set_tx_ring_count(adapter, tx_cnt); 2305 qlcnic_set_sds_ring_count(adapter, rx_cnt); 2306 } 2307 2308 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac) 2309 { 2310 struct qlcnic_hardware_context *ahw = adapter->ahw; 2311 int err = 0; 2312 2313 adapter->rx_mac_learn = false; 2314 ahw->msix_supported = !!qlcnic_use_msi_x; 2315 2316 qlcnic_83xx_init_rings(adapter); 2317 2318 err = qlcnic_83xx_init_mailbox_work(adapter); 2319 if (err) 2320 goto exit; 2321 2322 if (qlcnic_sriov_vf_check(adapter)) { 2323 err = qlcnic_sriov_vf_init(adapter, pci_using_dac); 2324 if (err) 2325 goto detach_mbx; 2326 else 2327 return err; 2328 } 2329 2330 if (qlcnic_83xx_read_flash_descriptor_table(adapter) || 2331 qlcnic_83xx_read_flash_mfg_id(adapter)) { 2332 dev_err(&adapter->pdev->dev, "Failed reading flash mfg id\n"); 2333 err = -ENOTRECOVERABLE; 2334 goto detach_mbx; 2335 } 2336 2337 err = qlcnic_83xx_check_hw_status(adapter); 2338 if (err) 2339 goto detach_mbx; 2340 2341 err = qlcnic_83xx_get_fw_info(adapter); 2342 if (err) 2343 goto detach_mbx; 2344 2345 err = qlcnic_83xx_idc_init(adapter); 2346 if (err) 2347 goto detach_mbx; 2348 2349 err = qlcnic_setup_intr(adapter); 2350 if (err) { 2351 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n"); 2352 goto disable_intr; 2353 } 2354 2355 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work); 2356 2357 err = qlcnic_83xx_setup_mbx_intr(adapter); 2358 if (err) 2359 goto disable_mbx_intr; 2360 2361 qlcnic_83xx_clear_function_resources(adapter); 2362 qlcnic_dcb_enable(adapter->dcb); 2363 qlcnic_83xx_initialize_nic(adapter, 1); 2364 qlcnic_dcb_get_info(adapter->dcb); 2365 2366 /* Configure default, SR-IOV or Virtual NIC mode of operation */ 2367 err = qlcnic_83xx_configure_opmode(adapter); 2368 if (err) 2369 goto disable_mbx_intr; 2370 2371 2372 /* Perform operating mode specific initialization */ 2373 err = adapter->nic_ops->init_driver(adapter); 2374 if (err) 2375 goto disable_mbx_intr; 2376 2377 /* Periodically monitor device status */ 2378 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work); 2379 return 0; 2380 2381 disable_mbx_intr: 2382 qlcnic_83xx_free_mbx_intr(adapter); 2383 2384 disable_intr: 2385 qlcnic_teardown_intr(adapter); 2386 2387 detach_mbx: 2388 qlcnic_83xx_detach_mailbox_work(adapter); 2389 qlcnic_83xx_free_mailbox(ahw->mailbox); 2390 ahw->mailbox = NULL; 2391 exit: 2392 return err; 2393 } 2394 2395 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *adapter) 2396 { 2397 struct qlcnic_hardware_context *ahw = adapter->ahw; 2398 struct qlc_83xx_idc *idc = &ahw->idc; 2399 2400 clear_bit(QLC_83XX_MBX_READY, &idc->status); 2401 cancel_delayed_work_sync(&adapter->fw_work); 2402 2403 if (ahw->nic_mode == QLCNIC_VNIC_MODE) 2404 qlcnic_83xx_disable_vnic_mode(adapter, 1); 2405 2406 qlcnic_83xx_idc_detach_driver(adapter); 2407 qlcnic_83xx_initialize_nic(adapter, 0); 2408 2409 cancel_delayed_work_sync(&adapter->idc_aen_work); 2410 } 2411 2412 int qlcnic_83xx_aer_reset(struct qlcnic_adapter *adapter) 2413 { 2414 struct qlcnic_hardware_context *ahw = adapter->ahw; 2415 struct qlc_83xx_idc *idc = &ahw->idc; 2416 int ret = 0; 2417 u32 owner; 2418 2419 /* Mark the previous IDC state as NEED_RESET so 2420 * that state_entry() will perform the reattachment 2421 * and bringup the device 2422 */ 2423 idc->prev_state = QLC_83XX_IDC_DEV_NEED_RESET; 2424 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 2425 if (ahw->pci_func == owner) { 2426 ret = qlcnic_83xx_restart_hw(adapter); 2427 if (ret < 0) 2428 return ret; 2429 qlcnic_83xx_idc_clear_registers(adapter, 0); 2430 } 2431 2432 ret = idc->state_entry(adapter); 2433 return ret; 2434 } 2435 2436 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *adapter) 2437 { 2438 struct qlcnic_hardware_context *ahw = adapter->ahw; 2439 struct qlc_83xx_idc *idc = &ahw->idc; 2440 u32 owner; 2441 2442 idc->prev_state = QLC_83XX_IDC_DEV_READY; 2443 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 2444 if (ahw->pci_func == owner) 2445 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 2446 2447 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 0); 2448 } 2449