1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #include "qlcnic.h" 9 #include "qlcnic_sriov.h" 10 #include <linux/if_vlan.h> 11 #include <linux/ipv6.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/aer.h> 15 16 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *); 17 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8); 18 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8, 19 struct qlcnic_cmd_args *); 20 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *); 21 static irqreturn_t qlcnic_83xx_handle_aen(int, void *); 22 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *, 23 pci_channel_state_t); 24 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *); 25 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *); 26 static void qlcnic_83xx_io_resume(struct pci_dev *); 27 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8); 28 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *); 29 static int qlcnic_83xx_resume(struct qlcnic_adapter *); 30 static int qlcnic_83xx_shutdown(struct pci_dev *); 31 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *); 32 33 #define RSS_HASHTYPE_IP_TCP 0x3 34 #define QLC_83XX_FW_MBX_CMD 0 35 #define QLC_SKIP_INACTIVE_PCI_REGS 7 36 37 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = { 38 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1}, 39 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34}, 40 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27}, 41 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1}, 42 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18}, 43 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1}, 44 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1}, 45 {QLCNIC_CMD_INTRPT_TEST, 22, 12}, 46 {QLCNIC_CMD_SET_MTU, 3, 1}, 47 {QLCNIC_CMD_READ_PHY, 4, 2}, 48 {QLCNIC_CMD_WRITE_PHY, 5, 1}, 49 {QLCNIC_CMD_READ_HW_REG, 4, 1}, 50 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2}, 51 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1}, 52 {QLCNIC_CMD_READ_MAX_MTU, 4, 2}, 53 {QLCNIC_CMD_READ_MAX_LRO, 4, 2}, 54 {QLCNIC_CMD_MAC_ADDRESS, 4, 3}, 55 {QLCNIC_CMD_GET_PCI_INFO, 1, 129}, 56 {QLCNIC_CMD_GET_NIC_INFO, 2, 19}, 57 {QLCNIC_CMD_SET_NIC_INFO, 32, 1}, 58 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3}, 59 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1}, 60 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3}, 61 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1}, 62 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1}, 63 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3}, 64 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1}, 65 {QLCNIC_CMD_CONFIG_PORT, 4, 1}, 66 {QLCNIC_CMD_TEMP_SIZE, 1, 4}, 67 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5}, 68 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1}, 69 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3}, 70 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1}, 71 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1}, 72 {QLCNIC_CMD_CONFIGURE_LED, 2, 1}, 73 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1}, 74 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1}, 75 {QLCNIC_CMD_GET_STATISTICS, 2, 80}, 76 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1}, 77 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2}, 78 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4}, 79 {QLCNIC_CMD_IDC_ACK, 5, 1}, 80 {QLCNIC_CMD_INIT_NIC_FUNC, 3, 1}, 81 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1}, 82 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1}, 83 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5}, 84 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1}, 85 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26}, 86 {QLCNIC_CMD_CONFIG_VPORT, 4, 4}, 87 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1}, 88 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2}, 89 {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50}, 90 {QLCNIC_CMD_SET_INGRESS_ENCAP, 2, 1}, 91 }; 92 93 const u32 qlcnic_83xx_ext_reg_tbl[] = { 94 0x38CC, /* Global Reset */ 95 0x38F0, /* Wildcard */ 96 0x38FC, /* Informant */ 97 0x3038, /* Host MBX ctrl */ 98 0x303C, /* FW MBX ctrl */ 99 0x355C, /* BOOT LOADER ADDRESS REG */ 100 0x3560, /* BOOT LOADER SIZE REG */ 101 0x3564, /* FW IMAGE ADDR REG */ 102 0x1000, /* MBX intr enable */ 103 0x1200, /* Default Intr mask */ 104 0x1204, /* Default Interrupt ID */ 105 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */ 106 0x3784, /* QLC_83XX_IDC_DEV_STATE */ 107 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */ 108 0x378C, /* QLC_83XX_IDC_DRV_ACK */ 109 0x3790, /* QLC_83XX_IDC_CTRL */ 110 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */ 111 0x3798, /* QLC_83XX_IDC_MIN_VERSION */ 112 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */ 113 0x37A0, /* QLC_83XX_IDC_PF_0 */ 114 0x37A4, /* QLC_83XX_IDC_PF_1 */ 115 0x37A8, /* QLC_83XX_IDC_PF_2 */ 116 0x37AC, /* QLC_83XX_IDC_PF_3 */ 117 0x37B0, /* QLC_83XX_IDC_PF_4 */ 118 0x37B4, /* QLC_83XX_IDC_PF_5 */ 119 0x37B8, /* QLC_83XX_IDC_PF_6 */ 120 0x37BC, /* QLC_83XX_IDC_PF_7 */ 121 0x37C0, /* QLC_83XX_IDC_PF_8 */ 122 0x37C4, /* QLC_83XX_IDC_PF_9 */ 123 0x37C8, /* QLC_83XX_IDC_PF_10 */ 124 0x37CC, /* QLC_83XX_IDC_PF_11 */ 125 0x37D0, /* QLC_83XX_IDC_PF_12 */ 126 0x37D4, /* QLC_83XX_IDC_PF_13 */ 127 0x37D8, /* QLC_83XX_IDC_PF_14 */ 128 0x37DC, /* QLC_83XX_IDC_PF_15 */ 129 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */ 130 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */ 131 0x37F0, /* QLC_83XX_DRV_OP_MODE */ 132 0x37F4, /* QLC_83XX_VNIC_STATE */ 133 0x3868, /* QLC_83XX_DRV_LOCK */ 134 0x386C, /* QLC_83XX_DRV_UNLOCK */ 135 0x3504, /* QLC_83XX_DRV_LOCK_ID */ 136 0x34A4, /* QLC_83XX_ASIC_TEMP */ 137 }; 138 139 const u32 qlcnic_83xx_reg_tbl[] = { 140 0x34A8, /* PEG_HALT_STAT1 */ 141 0x34AC, /* PEG_HALT_STAT2 */ 142 0x34B0, /* FW_HEARTBEAT */ 143 0x3500, /* FLASH LOCK_ID */ 144 0x3528, /* FW_CAPABILITIES */ 145 0x3538, /* Driver active, DRV_REG0 */ 146 0x3540, /* Device state, DRV_REG1 */ 147 0x3544, /* Driver state, DRV_REG2 */ 148 0x3548, /* Driver scratch, DRV_REG3 */ 149 0x354C, /* Device partiton info, DRV_REG4 */ 150 0x3524, /* Driver IDC ver, DRV_REG5 */ 151 0x3550, /* FW_VER_MAJOR */ 152 0x3554, /* FW_VER_MINOR */ 153 0x3558, /* FW_VER_SUB */ 154 0x359C, /* NPAR STATE */ 155 0x35FC, /* FW_IMG_VALID */ 156 0x3650, /* CMD_PEG_STATE */ 157 0x373C, /* RCV_PEG_STATE */ 158 0x37B4, /* ASIC TEMP */ 159 0x356C, /* FW API */ 160 0x3570, /* DRV OP MODE */ 161 0x3850, /* FLASH LOCK */ 162 0x3854, /* FLASH UNLOCK */ 163 }; 164 165 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = { 166 .read_crb = qlcnic_83xx_read_crb, 167 .write_crb = qlcnic_83xx_write_crb, 168 .read_reg = qlcnic_83xx_rd_reg_indirect, 169 .write_reg = qlcnic_83xx_wrt_reg_indirect, 170 .get_mac_address = qlcnic_83xx_get_mac_address, 171 .setup_intr = qlcnic_83xx_setup_intr, 172 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args, 173 .mbx_cmd = qlcnic_83xx_issue_cmd, 174 .get_func_no = qlcnic_83xx_get_func_no, 175 .api_lock = qlcnic_83xx_cam_lock, 176 .api_unlock = qlcnic_83xx_cam_unlock, 177 .add_sysfs = qlcnic_83xx_add_sysfs, 178 .remove_sysfs = qlcnic_83xx_remove_sysfs, 179 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag, 180 .create_rx_ctx = qlcnic_83xx_create_rx_ctx, 181 .create_tx_ctx = qlcnic_83xx_create_tx_ctx, 182 .del_rx_ctx = qlcnic_83xx_del_rx_ctx, 183 .del_tx_ctx = qlcnic_83xx_del_tx_ctx, 184 .setup_link_event = qlcnic_83xx_setup_link_event, 185 .get_nic_info = qlcnic_83xx_get_nic_info, 186 .get_pci_info = qlcnic_83xx_get_pci_info, 187 .set_nic_info = qlcnic_83xx_set_nic_info, 188 .change_macvlan = qlcnic_83xx_sre_macaddr_change, 189 .napi_enable = qlcnic_83xx_napi_enable, 190 .napi_disable = qlcnic_83xx_napi_disable, 191 .config_intr_coal = qlcnic_83xx_config_intr_coal, 192 .config_rss = qlcnic_83xx_config_rss, 193 .config_hw_lro = qlcnic_83xx_config_hw_lro, 194 .config_promisc_mode = qlcnic_83xx_nic_set_promisc, 195 .change_l2_filter = qlcnic_83xx_change_l2_filter, 196 .get_board_info = qlcnic_83xx_get_port_info, 197 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count, 198 .free_mac_list = qlcnic_82xx_free_mac_list, 199 .io_error_detected = qlcnic_83xx_io_error_detected, 200 .io_slot_reset = qlcnic_83xx_io_slot_reset, 201 .io_resume = qlcnic_83xx_io_resume, 202 .get_beacon_state = qlcnic_83xx_get_beacon_state, 203 .enable_sds_intr = qlcnic_83xx_enable_sds_intr, 204 .disable_sds_intr = qlcnic_83xx_disable_sds_intr, 205 .enable_tx_intr = qlcnic_83xx_enable_tx_intr, 206 .disable_tx_intr = qlcnic_83xx_disable_tx_intr, 207 .get_saved_state = qlcnic_83xx_get_saved_state, 208 .set_saved_state = qlcnic_83xx_set_saved_state, 209 .cache_tmpl_hdr_values = qlcnic_83xx_cache_tmpl_hdr_values, 210 .get_cap_size = qlcnic_83xx_get_cap_size, 211 .set_sys_info = qlcnic_83xx_set_sys_info, 212 .store_cap_mask = qlcnic_83xx_store_cap_mask, 213 }; 214 215 static struct qlcnic_nic_template qlcnic_83xx_ops = { 216 .config_bridged_mode = qlcnic_config_bridged_mode, 217 .config_led = qlcnic_config_led, 218 .request_reset = qlcnic_83xx_idc_request_reset, 219 .cancel_idc_work = qlcnic_83xx_idc_exit, 220 .napi_add = qlcnic_83xx_napi_add, 221 .napi_del = qlcnic_83xx_napi_del, 222 .config_ipaddr = qlcnic_83xx_config_ipaddr, 223 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr, 224 .shutdown = qlcnic_83xx_shutdown, 225 .resume = qlcnic_83xx_resume, 226 }; 227 228 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw) 229 { 230 ahw->hw_ops = &qlcnic_83xx_hw_ops; 231 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; 232 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl; 233 } 234 235 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter) 236 { 237 u32 fw_major, fw_minor, fw_build; 238 struct pci_dev *pdev = adapter->pdev; 239 240 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR); 241 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR); 242 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB); 243 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build); 244 245 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n", 246 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build); 247 248 return adapter->fw_version; 249 } 250 251 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr) 252 { 253 void __iomem *base; 254 u32 val; 255 256 base = adapter->ahw->pci_base0 + 257 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func); 258 writel(addr, base); 259 val = readl(base); 260 if (val != addr) 261 return -EIO; 262 263 return 0; 264 } 265 266 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr, 267 int *err) 268 { 269 struct qlcnic_hardware_context *ahw = adapter->ahw; 270 271 *err = __qlcnic_set_win_base(adapter, (u32) addr); 272 if (!*err) { 273 return QLCRDX(ahw, QLCNIC_WILDCARD); 274 } else { 275 dev_err(&adapter->pdev->dev, 276 "%s failed, addr = 0x%lx\n", __func__, addr); 277 return -EIO; 278 } 279 } 280 281 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr, 282 u32 data) 283 { 284 int err; 285 struct qlcnic_hardware_context *ahw = adapter->ahw; 286 287 err = __qlcnic_set_win_base(adapter, (u32) addr); 288 if (!err) { 289 QLCWRX(ahw, QLCNIC_WILDCARD, data); 290 return 0; 291 } else { 292 dev_err(&adapter->pdev->dev, 293 "%s failed, addr = 0x%x data = 0x%x\n", 294 __func__, (int)addr, data); 295 return err; 296 } 297 } 298 299 static void qlcnic_83xx_enable_legacy(struct qlcnic_adapter *adapter) 300 { 301 struct qlcnic_hardware_context *ahw = adapter->ahw; 302 303 /* MSI-X enablement failed, use legacy interrupt */ 304 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR; 305 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK; 306 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR; 307 adapter->msix_entries[0].vector = adapter->pdev->irq; 308 dev_info(&adapter->pdev->dev, "using legacy interrupt\n"); 309 } 310 311 static int qlcnic_83xx_calculate_msix_vector(struct qlcnic_adapter *adapter) 312 { 313 int num_msix; 314 315 num_msix = adapter->drv_sds_rings; 316 317 /* account for AEN interrupt MSI-X based interrupts */ 318 num_msix += 1; 319 320 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED)) 321 num_msix += adapter->drv_tx_rings; 322 323 return num_msix; 324 } 325 326 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter) 327 { 328 struct qlcnic_hardware_context *ahw = adapter->ahw; 329 int err, i, num_msix; 330 331 if (adapter->flags & QLCNIC_TSS_RSS) { 332 err = qlcnic_setup_tss_rss_intr(adapter); 333 if (err < 0) 334 return err; 335 num_msix = ahw->num_msix; 336 } else { 337 num_msix = qlcnic_83xx_calculate_msix_vector(adapter); 338 339 err = qlcnic_enable_msix(adapter, num_msix); 340 if (err == -ENOMEM) 341 return err; 342 343 if (adapter->flags & QLCNIC_MSIX_ENABLED) { 344 num_msix = ahw->num_msix; 345 } else { 346 if (qlcnic_sriov_vf_check(adapter)) 347 return -EINVAL; 348 num_msix = 1; 349 adapter->drv_sds_rings = QLCNIC_SINGLE_RING; 350 adapter->drv_tx_rings = QLCNIC_SINGLE_RING; 351 } 352 } 353 354 /* setup interrupt mapping table for fw */ 355 ahw->intr_tbl = vzalloc(num_msix * 356 sizeof(struct qlcnic_intrpt_config)); 357 if (!ahw->intr_tbl) 358 return -ENOMEM; 359 360 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) 361 qlcnic_83xx_enable_legacy(adapter); 362 363 for (i = 0; i < num_msix; i++) { 364 if (adapter->flags & QLCNIC_MSIX_ENABLED) 365 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX; 366 else 367 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX; 368 ahw->intr_tbl[i].id = i; 369 ahw->intr_tbl[i].src = 0; 370 } 371 372 return 0; 373 } 374 375 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter) 376 { 377 writel(0, adapter->tgt_mask_reg); 378 } 379 380 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter) 381 { 382 if (adapter->tgt_mask_reg) 383 writel(1, adapter->tgt_mask_reg); 384 } 385 386 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter 387 *adapter) 388 { 389 u32 mask; 390 391 /* Mailbox in MSI-x mode and Legacy Interrupt share the same 392 * source register. We could be here before contexts are created 393 * and sds_ring->crb_intr_mask has not been initialized, calculate 394 * BAR offset for Interrupt Source Register 395 */ 396 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); 397 writel(0, adapter->ahw->pci_base0 + mask); 398 } 399 400 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter) 401 { 402 u32 mask; 403 404 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); 405 writel(1, adapter->ahw->pci_base0 + mask); 406 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0); 407 } 408 409 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter, 410 struct qlcnic_cmd_args *cmd) 411 { 412 int i; 413 414 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP) 415 return; 416 417 for (i = 0; i < cmd->rsp.num; i++) 418 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i)); 419 } 420 421 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter) 422 { 423 u32 intr_val; 424 struct qlcnic_hardware_context *ahw = adapter->ahw; 425 int retries = 0; 426 427 intr_val = readl(adapter->tgt_status_reg); 428 429 if (!QLC_83XX_VALID_INTX_BIT31(intr_val)) 430 return IRQ_NONE; 431 432 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) { 433 adapter->stats.spurious_intr++; 434 return IRQ_NONE; 435 } 436 /* The barrier is required to ensure writes to the registers */ 437 wmb(); 438 439 /* clear the interrupt trigger control register */ 440 writel(0, adapter->isr_int_vec); 441 intr_val = readl(adapter->isr_int_vec); 442 do { 443 intr_val = readl(adapter->tgt_status_reg); 444 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func) 445 break; 446 retries++; 447 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) && 448 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY)); 449 450 return IRQ_HANDLED; 451 } 452 453 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx) 454 { 455 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED); 456 complete(&mbx->completion); 457 } 458 459 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter) 460 { 461 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED; 462 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 463 unsigned long flags; 464 465 spin_lock_irqsave(&mbx->aen_lock, flags); 466 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL); 467 if (!(resp & QLCNIC_SET_OWNER)) 468 goto out; 469 470 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0)); 471 if (event & QLCNIC_MBX_ASYNC_EVENT) { 472 __qlcnic_83xx_process_aen(adapter); 473 } else { 474 if (atomic_read(&mbx->rsp_status) != rsp_status) 475 qlcnic_83xx_notify_mbx_response(mbx); 476 } 477 out: 478 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 479 spin_unlock_irqrestore(&mbx->aen_lock, flags); 480 } 481 482 irqreturn_t qlcnic_83xx_intr(int irq, void *data) 483 { 484 struct qlcnic_adapter *adapter = data; 485 struct qlcnic_host_sds_ring *sds_ring; 486 struct qlcnic_hardware_context *ahw = adapter->ahw; 487 488 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE) 489 return IRQ_NONE; 490 491 qlcnic_83xx_poll_process_aen(adapter); 492 493 if (ahw->diag_test) { 494 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) 495 ahw->diag_cnt++; 496 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 497 return IRQ_HANDLED; 498 } 499 500 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) { 501 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 502 } else { 503 sds_ring = &adapter->recv_ctx->sds_rings[0]; 504 napi_schedule(&sds_ring->napi); 505 } 506 507 return IRQ_HANDLED; 508 } 509 510 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data) 511 { 512 struct qlcnic_host_sds_ring *sds_ring = data; 513 struct qlcnic_adapter *adapter = sds_ring->adapter; 514 515 if (adapter->flags & QLCNIC_MSIX_ENABLED) 516 goto done; 517 518 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE) 519 return IRQ_NONE; 520 521 done: 522 adapter->ahw->diag_cnt++; 523 qlcnic_enable_sds_intr(adapter, sds_ring); 524 525 return IRQ_HANDLED; 526 } 527 528 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter) 529 { 530 u32 num_msix; 531 532 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) 533 qlcnic_83xx_set_legacy_intr_mask(adapter); 534 535 qlcnic_83xx_disable_mbx_intr(adapter); 536 537 if (adapter->flags & QLCNIC_MSIX_ENABLED) 538 num_msix = adapter->ahw->num_msix - 1; 539 else 540 num_msix = 0; 541 542 msleep(20); 543 544 if (adapter->msix_entries) { 545 synchronize_irq(adapter->msix_entries[num_msix].vector); 546 free_irq(adapter->msix_entries[num_msix].vector, adapter); 547 } 548 } 549 550 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter) 551 { 552 irq_handler_t handler; 553 u32 val; 554 int err = 0; 555 unsigned long flags = 0; 556 557 if (!(adapter->flags & QLCNIC_MSI_ENABLED) && 558 !(adapter->flags & QLCNIC_MSIX_ENABLED)) 559 flags |= IRQF_SHARED; 560 561 if (adapter->flags & QLCNIC_MSIX_ENABLED) { 562 handler = qlcnic_83xx_handle_aen; 563 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector; 564 err = request_irq(val, handler, flags, "qlcnic-MB", adapter); 565 if (err) { 566 dev_err(&adapter->pdev->dev, 567 "failed to register MBX interrupt\n"); 568 return err; 569 } 570 } else { 571 handler = qlcnic_83xx_intr; 572 val = adapter->msix_entries[0].vector; 573 err = request_irq(val, handler, flags, "qlcnic", adapter); 574 if (err) { 575 dev_err(&adapter->pdev->dev, 576 "failed to register INTx interrupt\n"); 577 return err; 578 } 579 qlcnic_83xx_clear_legacy_intr_mask(adapter); 580 } 581 582 /* Enable mailbox interrupt */ 583 qlcnic_83xx_enable_mbx_interrupt(adapter); 584 585 return err; 586 } 587 588 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter) 589 { 590 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT); 591 adapter->ahw->pci_func = (val >> 24) & 0xff; 592 } 593 594 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter) 595 { 596 void __iomem *addr; 597 u32 val, limit = 0; 598 599 struct qlcnic_hardware_context *ahw = adapter->ahw; 600 601 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func); 602 do { 603 val = readl(addr); 604 if (val) { 605 /* write the function number to register */ 606 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 607 ahw->pci_func); 608 return 0; 609 } 610 usleep_range(1000, 2000); 611 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT); 612 613 return -EIO; 614 } 615 616 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter) 617 { 618 void __iomem *addr; 619 u32 val; 620 struct qlcnic_hardware_context *ahw = adapter->ahw; 621 622 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func); 623 val = readl(addr); 624 } 625 626 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf, 627 loff_t offset, size_t size) 628 { 629 int ret = 0; 630 u32 data; 631 632 if (qlcnic_api_lock(adapter)) { 633 dev_err(&adapter->pdev->dev, 634 "%s: failed to acquire lock. addr offset 0x%x\n", 635 __func__, (u32)offset); 636 return; 637 } 638 639 data = QLCRD32(adapter, (u32) offset, &ret); 640 qlcnic_api_unlock(adapter); 641 642 if (ret == -EIO) { 643 dev_err(&adapter->pdev->dev, 644 "%s: failed. addr offset 0x%x\n", 645 __func__, (u32)offset); 646 return; 647 } 648 memcpy(buf, &data, size); 649 } 650 651 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf, 652 loff_t offset, size_t size) 653 { 654 u32 data; 655 656 memcpy(&data, buf, size); 657 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data); 658 } 659 660 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter) 661 { 662 int status; 663 664 status = qlcnic_83xx_get_port_config(adapter); 665 if (status) { 666 dev_err(&adapter->pdev->dev, 667 "Get Port Info failed\n"); 668 } else { 669 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config)) 670 adapter->ahw->port_type = QLCNIC_XGBE; 671 else 672 adapter->ahw->port_type = QLCNIC_GBE; 673 674 if (QLC_83XX_AUTONEG(adapter->ahw->port_config)) 675 adapter->ahw->link_autoneg = AUTONEG_ENABLE; 676 } 677 return status; 678 } 679 680 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter) 681 { 682 struct qlcnic_hardware_context *ahw = adapter->ahw; 683 u16 act_pci_fn = ahw->total_nic_func; 684 u16 count; 685 686 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT; 687 if (act_pci_fn <= 2) 688 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) / 689 act_pci_fn; 690 else 691 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) / 692 act_pci_fn; 693 ahw->max_uc_count = count; 694 } 695 696 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter) 697 { 698 u32 val; 699 700 if (adapter->flags & QLCNIC_MSIX_ENABLED) 701 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8); 702 else 703 val = BIT_2; 704 705 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val); 706 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 707 } 708 709 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter, 710 const struct pci_device_id *ent) 711 { 712 u32 op_mode, priv_level; 713 struct qlcnic_hardware_context *ahw = adapter->ahw; 714 715 ahw->fw_hal_version = 2; 716 qlcnic_get_func_no(adapter); 717 718 if (qlcnic_sriov_vf_check(adapter)) { 719 qlcnic_sriov_vf_set_ops(adapter); 720 return; 721 } 722 723 /* Determine function privilege level */ 724 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE); 725 if (op_mode == QLC_83XX_DEFAULT_OPMODE) 726 priv_level = QLCNIC_MGMT_FUNC; 727 else 728 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode, 729 ahw->pci_func); 730 731 if (priv_level == QLCNIC_NON_PRIV_FUNC) { 732 ahw->op_mode = QLCNIC_NON_PRIV_FUNC; 733 dev_info(&adapter->pdev->dev, 734 "HAL Version: %d Non Privileged function\n", 735 ahw->fw_hal_version); 736 adapter->nic_ops = &qlcnic_vf_ops; 737 } else { 738 if (pci_find_ext_capability(adapter->pdev, 739 PCI_EXT_CAP_ID_SRIOV)) 740 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state); 741 adapter->nic_ops = &qlcnic_83xx_ops; 742 } 743 } 744 745 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter, 746 u32 data[]); 747 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter, 748 u32 data[]); 749 750 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter, 751 struct qlcnic_cmd_args *cmd) 752 { 753 int i; 754 755 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP) 756 return; 757 758 dev_info(&adapter->pdev->dev, 759 "Host MBX regs(%d)\n", cmd->req.num); 760 for (i = 0; i < cmd->req.num; i++) { 761 if (i && !(i % 8)) 762 pr_info("\n"); 763 pr_info("%08x ", cmd->req.arg[i]); 764 } 765 pr_info("\n"); 766 dev_info(&adapter->pdev->dev, 767 "FW MBX regs(%d)\n", cmd->rsp.num); 768 for (i = 0; i < cmd->rsp.num; i++) { 769 if (i && !(i % 8)) 770 pr_info("\n"); 771 pr_info("%08x ", cmd->rsp.arg[i]); 772 } 773 pr_info("\n"); 774 } 775 776 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter, 777 struct qlcnic_cmd_args *cmd) 778 { 779 struct qlcnic_hardware_context *ahw = adapter->ahw; 780 int opcode = LSW(cmd->req.arg[0]); 781 unsigned long max_loops; 782 783 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP; 784 785 for (; max_loops; max_loops--) { 786 if (atomic_read(&cmd->rsp_status) == 787 QLC_83XX_MBX_RESPONSE_ARRIVED) 788 return; 789 790 udelay(1); 791 } 792 793 dev_err(&adapter->pdev->dev, 794 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", 795 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode); 796 flush_workqueue(ahw->mailbox->work_q); 797 return; 798 } 799 800 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter, 801 struct qlcnic_cmd_args *cmd) 802 { 803 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 804 struct qlcnic_hardware_context *ahw = adapter->ahw; 805 int cmd_type, err, opcode; 806 unsigned long timeout; 807 808 if (!mbx) 809 return -EIO; 810 811 opcode = LSW(cmd->req.arg[0]); 812 cmd_type = cmd->type; 813 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout); 814 if (err) { 815 dev_err(&adapter->pdev->dev, 816 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n", 817 __func__, opcode, cmd->type, ahw->pci_func, 818 ahw->op_mode); 819 return err; 820 } 821 822 switch (cmd_type) { 823 case QLC_83XX_MBX_CMD_WAIT: 824 if (!wait_for_completion_timeout(&cmd->completion, timeout)) { 825 dev_err(&adapter->pdev->dev, 826 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", 827 __func__, opcode, cmd_type, ahw->pci_func, 828 ahw->op_mode); 829 flush_workqueue(mbx->work_q); 830 } 831 break; 832 case QLC_83XX_MBX_CMD_NO_WAIT: 833 return 0; 834 case QLC_83XX_MBX_CMD_BUSY_WAIT: 835 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd); 836 break; 837 default: 838 dev_err(&adapter->pdev->dev, 839 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", 840 __func__, opcode, cmd_type, ahw->pci_func, 841 ahw->op_mode); 842 qlcnic_83xx_detach_mailbox_work(adapter); 843 } 844 845 return cmd->rsp_opcode; 846 } 847 848 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx, 849 struct qlcnic_adapter *adapter, u32 type) 850 { 851 int i, size; 852 u32 temp; 853 const struct qlcnic_mailbox_metadata *mbx_tbl; 854 855 memset(mbx, 0, sizeof(struct qlcnic_cmd_args)); 856 mbx_tbl = qlcnic_83xx_mbx_tbl; 857 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl); 858 for (i = 0; i < size; i++) { 859 if (type == mbx_tbl[i].cmd) { 860 mbx->op_type = QLC_83XX_FW_MBX_CMD; 861 mbx->req.num = mbx_tbl[i].in_args; 862 mbx->rsp.num = mbx_tbl[i].out_args; 863 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32), 864 GFP_ATOMIC); 865 if (!mbx->req.arg) 866 return -ENOMEM; 867 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32), 868 GFP_ATOMIC); 869 if (!mbx->rsp.arg) { 870 kfree(mbx->req.arg); 871 mbx->req.arg = NULL; 872 return -ENOMEM; 873 } 874 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num); 875 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num); 876 temp = adapter->ahw->fw_hal_version << 29; 877 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp); 878 mbx->cmd_op = type; 879 return 0; 880 } 881 } 882 return -EINVAL; 883 } 884 885 void qlcnic_83xx_idc_aen_work(struct work_struct *work) 886 { 887 struct qlcnic_adapter *adapter; 888 struct qlcnic_cmd_args cmd; 889 int i, err = 0; 890 891 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work); 892 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK); 893 if (err) 894 return; 895 896 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++) 897 cmd.req.arg[i] = adapter->ahw->mbox_aen[i]; 898 899 err = qlcnic_issue_cmd(adapter, &cmd); 900 if (err) 901 dev_info(&adapter->pdev->dev, 902 "%s: Mailbox IDC ACK failed.\n", __func__); 903 qlcnic_free_mbx_args(&cmd); 904 } 905 906 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter, 907 u32 data[]) 908 { 909 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n", 910 QLCNIC_MBX_RSP(data[0])); 911 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status); 912 return; 913 } 914 915 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter) 916 { 917 struct qlcnic_hardware_context *ahw = adapter->ahw; 918 u32 event[QLC_83XX_MBX_AEN_CNT]; 919 int i; 920 921 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++) 922 event[i] = readl(QLCNIC_MBX_FW(ahw, i)); 923 924 switch (QLCNIC_MBX_RSP(event[0])) { 925 926 case QLCNIC_MBX_LINK_EVENT: 927 qlcnic_83xx_handle_link_aen(adapter, event); 928 break; 929 case QLCNIC_MBX_COMP_EVENT: 930 qlcnic_83xx_handle_idc_comp_aen(adapter, event); 931 break; 932 case QLCNIC_MBX_REQUEST_EVENT: 933 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++) 934 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]); 935 queue_delayed_work(adapter->qlcnic_wq, 936 &adapter->idc_aen_work, 0); 937 break; 938 case QLCNIC_MBX_TIME_EXTEND_EVENT: 939 ahw->extend_lb_time = event[1] >> 8 & 0xf; 940 break; 941 case QLCNIC_MBX_BC_EVENT: 942 qlcnic_sriov_handle_bc_event(adapter, event[1]); 943 break; 944 case QLCNIC_MBX_SFP_INSERT_EVENT: 945 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n", 946 QLCNIC_MBX_RSP(event[0])); 947 break; 948 case QLCNIC_MBX_SFP_REMOVE_EVENT: 949 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n", 950 QLCNIC_MBX_RSP(event[0])); 951 break; 952 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT: 953 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]); 954 break; 955 default: 956 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n", 957 QLCNIC_MBX_RSP(event[0])); 958 break; 959 } 960 961 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER); 962 } 963 964 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter) 965 { 966 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED; 967 struct qlcnic_hardware_context *ahw = adapter->ahw; 968 struct qlcnic_mailbox *mbx = ahw->mailbox; 969 unsigned long flags; 970 971 spin_lock_irqsave(&mbx->aen_lock, flags); 972 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL); 973 if (resp & QLCNIC_SET_OWNER) { 974 event = readl(QLCNIC_MBX_FW(ahw, 0)); 975 if (event & QLCNIC_MBX_ASYNC_EVENT) { 976 __qlcnic_83xx_process_aen(adapter); 977 } else { 978 if (atomic_read(&mbx->rsp_status) != rsp_status) 979 qlcnic_83xx_notify_mbx_response(mbx); 980 } 981 } 982 spin_unlock_irqrestore(&mbx->aen_lock, flags); 983 } 984 985 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work) 986 { 987 struct qlcnic_adapter *adapter; 988 989 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work); 990 991 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) 992 return; 993 994 qlcnic_83xx_process_aen(adapter); 995 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 996 (HZ / 10)); 997 } 998 999 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter) 1000 { 1001 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) 1002 return; 1003 1004 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work); 1005 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0); 1006 } 1007 1008 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter) 1009 { 1010 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) 1011 return; 1012 cancel_delayed_work_sync(&adapter->mbx_poll_work); 1013 } 1014 1015 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter) 1016 { 1017 int index, i, err, sds_mbx_size; 1018 u32 *buf, intrpt_id, intr_mask; 1019 u16 context_id; 1020 u8 num_sds; 1021 struct qlcnic_cmd_args cmd; 1022 struct qlcnic_host_sds_ring *sds; 1023 struct qlcnic_sds_mbx sds_mbx; 1024 struct qlcnic_add_rings_mbx_out *mbx_out; 1025 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; 1026 struct qlcnic_hardware_context *ahw = adapter->ahw; 1027 1028 sds_mbx_size = sizeof(struct qlcnic_sds_mbx); 1029 context_id = recv_ctx->context_id; 1030 num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS; 1031 ahw->hw_ops->alloc_mbx_args(&cmd, adapter, 1032 QLCNIC_CMD_ADD_RCV_RINGS); 1033 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16); 1034 1035 /* set up status rings, mbx 2-81 */ 1036 index = 2; 1037 for (i = 8; i < adapter->drv_sds_rings; i++) { 1038 memset(&sds_mbx, 0, sds_mbx_size); 1039 sds = &recv_ctx->sds_rings[i]; 1040 sds->consumer = 0; 1041 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds)); 1042 sds_mbx.phy_addr_low = LSD(sds->phys_addr); 1043 sds_mbx.phy_addr_high = MSD(sds->phys_addr); 1044 sds_mbx.sds_ring_size = sds->num_desc; 1045 1046 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1047 intrpt_id = ahw->intr_tbl[i].id; 1048 else 1049 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 1050 1051 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) 1052 sds_mbx.intrpt_id = intrpt_id; 1053 else 1054 sds_mbx.intrpt_id = 0xffff; 1055 sds_mbx.intrpt_val = 0; 1056 buf = &cmd.req.arg[index]; 1057 memcpy(buf, &sds_mbx, sds_mbx_size); 1058 index += sds_mbx_size / sizeof(u32); 1059 } 1060 1061 /* send the mailbox command */ 1062 err = ahw->hw_ops->mbx_cmd(adapter, &cmd); 1063 if (err) { 1064 dev_err(&adapter->pdev->dev, 1065 "Failed to add rings %d\n", err); 1066 goto out; 1067 } 1068 1069 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1]; 1070 index = 0; 1071 /* status descriptor ring */ 1072 for (i = 8; i < adapter->drv_sds_rings; i++) { 1073 sds = &recv_ctx->sds_rings[i]; 1074 sds->crb_sts_consumer = ahw->pci_base0 + 1075 mbx_out->host_csmr[index]; 1076 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1077 intr_mask = ahw->intr_tbl[i].src; 1078 else 1079 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK); 1080 1081 sds->crb_intr_mask = ahw->pci_base0 + intr_mask; 1082 index++; 1083 } 1084 out: 1085 qlcnic_free_mbx_args(&cmd); 1086 return err; 1087 } 1088 1089 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter) 1090 { 1091 int err; 1092 u32 temp = 0; 1093 struct qlcnic_cmd_args cmd; 1094 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; 1095 1096 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX)) 1097 return; 1098 1099 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1100 cmd.req.arg[0] |= (0x3 << 29); 1101 1102 if (qlcnic_sriov_pf_check(adapter)) 1103 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp); 1104 1105 cmd.req.arg[1] = recv_ctx->context_id | temp; 1106 err = qlcnic_issue_cmd(adapter, &cmd); 1107 if (err) 1108 dev_err(&adapter->pdev->dev, 1109 "Failed to destroy rx ctx in firmware\n"); 1110 1111 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED; 1112 qlcnic_free_mbx_args(&cmd); 1113 } 1114 1115 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter) 1116 { 1117 int i, err, index, sds_mbx_size, rds_mbx_size; 1118 u8 num_sds, num_rds; 1119 u32 *buf, intrpt_id, intr_mask, cap = 0; 1120 struct qlcnic_host_sds_ring *sds; 1121 struct qlcnic_host_rds_ring *rds; 1122 struct qlcnic_sds_mbx sds_mbx; 1123 struct qlcnic_rds_mbx rds_mbx; 1124 struct qlcnic_cmd_args cmd; 1125 struct qlcnic_rcv_mbx_out *mbx_out; 1126 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; 1127 struct qlcnic_hardware_context *ahw = adapter->ahw; 1128 num_rds = adapter->max_rds_rings; 1129 1130 if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS) 1131 num_sds = adapter->drv_sds_rings; 1132 else 1133 num_sds = QLCNIC_MAX_SDS_RINGS; 1134 1135 sds_mbx_size = sizeof(struct qlcnic_sds_mbx); 1136 rds_mbx_size = sizeof(struct qlcnic_rds_mbx); 1137 cap = QLCNIC_CAP0_LEGACY_CONTEXT; 1138 1139 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP) 1140 cap |= QLC_83XX_FW_CAP_LRO_MSS; 1141 1142 /* set mailbox hdr and capabilities */ 1143 err = qlcnic_alloc_mbx_args(&cmd, adapter, 1144 QLCNIC_CMD_CREATE_RX_CTX); 1145 if (err) 1146 return err; 1147 1148 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1149 cmd.req.arg[0] |= (0x3 << 29); 1150 1151 cmd.req.arg[1] = cap; 1152 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) | 1153 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16); 1154 1155 if (qlcnic_sriov_pf_check(adapter)) 1156 qlcnic_pf_set_interface_id_create_rx_ctx(adapter, 1157 &cmd.req.arg[6]); 1158 /* set up status rings, mbx 8-57/87 */ 1159 index = QLC_83XX_HOST_SDS_MBX_IDX; 1160 for (i = 0; i < num_sds; i++) { 1161 memset(&sds_mbx, 0, sds_mbx_size); 1162 sds = &recv_ctx->sds_rings[i]; 1163 sds->consumer = 0; 1164 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds)); 1165 sds_mbx.phy_addr_low = LSD(sds->phys_addr); 1166 sds_mbx.phy_addr_high = MSD(sds->phys_addr); 1167 sds_mbx.sds_ring_size = sds->num_desc; 1168 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1169 intrpt_id = ahw->intr_tbl[i].id; 1170 else 1171 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 1172 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) 1173 sds_mbx.intrpt_id = intrpt_id; 1174 else 1175 sds_mbx.intrpt_id = 0xffff; 1176 sds_mbx.intrpt_val = 0; 1177 buf = &cmd.req.arg[index]; 1178 memcpy(buf, &sds_mbx, sds_mbx_size); 1179 index += sds_mbx_size / sizeof(u32); 1180 } 1181 /* set up receive rings, mbx 88-111/135 */ 1182 index = QLCNIC_HOST_RDS_MBX_IDX; 1183 rds = &recv_ctx->rds_rings[0]; 1184 rds->producer = 0; 1185 memset(&rds_mbx, 0, rds_mbx_size); 1186 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr); 1187 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr); 1188 rds_mbx.reg_ring_sz = rds->dma_size; 1189 rds_mbx.reg_ring_len = rds->num_desc; 1190 /* Jumbo ring */ 1191 rds = &recv_ctx->rds_rings[1]; 1192 rds->producer = 0; 1193 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr); 1194 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr); 1195 rds_mbx.jmb_ring_sz = rds->dma_size; 1196 rds_mbx.jmb_ring_len = rds->num_desc; 1197 buf = &cmd.req.arg[index]; 1198 memcpy(buf, &rds_mbx, rds_mbx_size); 1199 1200 /* send the mailbox command */ 1201 err = ahw->hw_ops->mbx_cmd(adapter, &cmd); 1202 if (err) { 1203 dev_err(&adapter->pdev->dev, 1204 "Failed to create Rx ctx in firmware%d\n", err); 1205 goto out; 1206 } 1207 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1]; 1208 recv_ctx->context_id = mbx_out->ctx_id; 1209 recv_ctx->state = mbx_out->state; 1210 recv_ctx->virt_port = mbx_out->vport_id; 1211 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n", 1212 recv_ctx->context_id, recv_ctx->state); 1213 /* Receive descriptor ring */ 1214 /* Standard ring */ 1215 rds = &recv_ctx->rds_rings[0]; 1216 rds->crb_rcv_producer = ahw->pci_base0 + 1217 mbx_out->host_prod[0].reg_buf; 1218 /* Jumbo ring */ 1219 rds = &recv_ctx->rds_rings[1]; 1220 rds->crb_rcv_producer = ahw->pci_base0 + 1221 mbx_out->host_prod[0].jmb_buf; 1222 /* status descriptor ring */ 1223 for (i = 0; i < num_sds; i++) { 1224 sds = &recv_ctx->sds_rings[i]; 1225 sds->crb_sts_consumer = ahw->pci_base0 + 1226 mbx_out->host_csmr[i]; 1227 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1228 intr_mask = ahw->intr_tbl[i].src; 1229 else 1230 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK); 1231 sds->crb_intr_mask = ahw->pci_base0 + intr_mask; 1232 } 1233 1234 if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS) 1235 err = qlcnic_83xx_add_rings(adapter); 1236 out: 1237 qlcnic_free_mbx_args(&cmd); 1238 return err; 1239 } 1240 1241 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter, 1242 struct qlcnic_host_tx_ring *tx_ring) 1243 { 1244 struct qlcnic_cmd_args cmd; 1245 u32 temp = 0; 1246 1247 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX)) 1248 return; 1249 1250 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1251 cmd.req.arg[0] |= (0x3 << 29); 1252 1253 if (qlcnic_sriov_pf_check(adapter)) 1254 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp); 1255 1256 cmd.req.arg[1] = tx_ring->ctx_id | temp; 1257 if (qlcnic_issue_cmd(adapter, &cmd)) 1258 dev_err(&adapter->pdev->dev, 1259 "Failed to destroy tx ctx in firmware\n"); 1260 qlcnic_free_mbx_args(&cmd); 1261 } 1262 1263 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter, 1264 struct qlcnic_host_tx_ring *tx, int ring) 1265 { 1266 int err; 1267 u16 msix_id; 1268 u32 *buf, intr_mask, temp = 0; 1269 struct qlcnic_cmd_args cmd; 1270 struct qlcnic_tx_mbx mbx; 1271 struct qlcnic_tx_mbx_out *mbx_out; 1272 struct qlcnic_hardware_context *ahw = adapter->ahw; 1273 u32 msix_vector; 1274 1275 /* Reset host resources */ 1276 tx->producer = 0; 1277 tx->sw_consumer = 0; 1278 *(tx->hw_consumer) = 0; 1279 1280 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx)); 1281 1282 /* setup mailbox inbox registerss */ 1283 mbx.phys_addr_low = LSD(tx->phys_addr); 1284 mbx.phys_addr_high = MSD(tx->phys_addr); 1285 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr); 1286 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr); 1287 mbx.size = tx->num_desc; 1288 if (adapter->flags & QLCNIC_MSIX_ENABLED) { 1289 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED)) 1290 msix_vector = adapter->drv_sds_rings + ring; 1291 else 1292 msix_vector = adapter->drv_sds_rings - 1; 1293 msix_id = ahw->intr_tbl[msix_vector].id; 1294 } else { 1295 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 1296 } 1297 1298 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) 1299 mbx.intr_id = msix_id; 1300 else 1301 mbx.intr_id = 0xffff; 1302 mbx.src = 0; 1303 1304 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX); 1305 if (err) 1306 return err; 1307 1308 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1309 cmd.req.arg[0] |= (0x3 << 29); 1310 1311 if (qlcnic_sriov_pf_check(adapter)) 1312 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp); 1313 1314 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT; 1315 cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp; 1316 1317 buf = &cmd.req.arg[6]; 1318 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx)); 1319 /* send the mailbox command*/ 1320 err = qlcnic_issue_cmd(adapter, &cmd); 1321 if (err) { 1322 netdev_err(adapter->netdev, 1323 "Failed to create Tx ctx in firmware 0x%x\n", err); 1324 goto out; 1325 } 1326 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2]; 1327 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod; 1328 tx->ctx_id = mbx_out->ctx_id; 1329 if ((adapter->flags & QLCNIC_MSIX_ENABLED) && 1330 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) { 1331 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src; 1332 tx->crb_intr_mask = ahw->pci_base0 + intr_mask; 1333 } 1334 netdev_info(adapter->netdev, 1335 "Tx Context[0x%x] Created, state:0x%x\n", 1336 tx->ctx_id, mbx_out->state); 1337 out: 1338 qlcnic_free_mbx_args(&cmd); 1339 return err; 1340 } 1341 1342 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test, 1343 u8 num_sds_ring) 1344 { 1345 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1346 struct qlcnic_host_sds_ring *sds_ring; 1347 struct qlcnic_host_rds_ring *rds_ring; 1348 u16 adapter_state = adapter->is_up; 1349 u8 ring; 1350 int ret; 1351 1352 netif_device_detach(netdev); 1353 1354 if (netif_running(netdev)) 1355 __qlcnic_down(adapter, netdev); 1356 1357 qlcnic_detach(adapter); 1358 1359 adapter->drv_sds_rings = QLCNIC_SINGLE_RING; 1360 adapter->ahw->diag_test = test; 1361 adapter->ahw->linkup = 0; 1362 1363 ret = qlcnic_attach(adapter); 1364 if (ret) { 1365 netif_device_attach(netdev); 1366 return ret; 1367 } 1368 1369 ret = qlcnic_fw_create_ctx(adapter); 1370 if (ret) { 1371 qlcnic_detach(adapter); 1372 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) { 1373 adapter->drv_sds_rings = num_sds_ring; 1374 qlcnic_attach(adapter); 1375 } 1376 netif_device_attach(netdev); 1377 return ret; 1378 } 1379 1380 for (ring = 0; ring < adapter->max_rds_rings; ring++) { 1381 rds_ring = &adapter->recv_ctx->rds_rings[ring]; 1382 qlcnic_post_rx_buffers(adapter, rds_ring, ring); 1383 } 1384 1385 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) { 1386 for (ring = 0; ring < adapter->drv_sds_rings; ring++) { 1387 sds_ring = &adapter->recv_ctx->sds_rings[ring]; 1388 qlcnic_enable_sds_intr(adapter, sds_ring); 1389 } 1390 } 1391 1392 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) { 1393 adapter->ahw->loopback_state = 0; 1394 adapter->ahw->hw_ops->setup_link_event(adapter, 1); 1395 } 1396 1397 set_bit(__QLCNIC_DEV_UP, &adapter->state); 1398 return 0; 1399 } 1400 1401 static void qlcnic_83xx_diag_free_res(struct net_device *netdev, 1402 u8 drv_sds_rings) 1403 { 1404 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1405 struct qlcnic_host_sds_ring *sds_ring; 1406 int ring; 1407 1408 clear_bit(__QLCNIC_DEV_UP, &adapter->state); 1409 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) { 1410 for (ring = 0; ring < adapter->drv_sds_rings; ring++) { 1411 sds_ring = &adapter->recv_ctx->sds_rings[ring]; 1412 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1413 qlcnic_disable_sds_intr(adapter, sds_ring); 1414 } 1415 } 1416 1417 qlcnic_fw_destroy_ctx(adapter); 1418 qlcnic_detach(adapter); 1419 1420 adapter->ahw->diag_test = 0; 1421 adapter->drv_sds_rings = drv_sds_rings; 1422 1423 if (qlcnic_attach(adapter)) 1424 goto out; 1425 1426 if (netif_running(netdev)) 1427 __qlcnic_up(adapter, netdev); 1428 1429 out: 1430 netif_device_attach(netdev); 1431 } 1432 1433 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter) 1434 { 1435 struct qlcnic_hardware_context *ahw = adapter->ahw; 1436 struct qlcnic_cmd_args cmd; 1437 u8 beacon_state; 1438 int err = 0; 1439 1440 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG); 1441 if (!err) { 1442 err = qlcnic_issue_cmd(adapter, &cmd); 1443 if (!err) { 1444 beacon_state = cmd.rsp.arg[4]; 1445 if (beacon_state == QLCNIC_BEACON_DISABLE) 1446 ahw->beacon_state = QLC_83XX_BEACON_OFF; 1447 else if (beacon_state == QLC_83XX_ENABLE_BEACON) 1448 ahw->beacon_state = QLC_83XX_BEACON_ON; 1449 } 1450 } else { 1451 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n", 1452 err); 1453 } 1454 1455 qlcnic_free_mbx_args(&cmd); 1456 1457 return; 1458 } 1459 1460 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state, 1461 u32 beacon) 1462 { 1463 struct qlcnic_cmd_args cmd; 1464 u32 mbx_in; 1465 int i, status = 0; 1466 1467 if (state) { 1468 /* Get LED configuration */ 1469 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1470 QLCNIC_CMD_GET_LED_CONFIG); 1471 if (status) 1472 return status; 1473 1474 status = qlcnic_issue_cmd(adapter, &cmd); 1475 if (status) { 1476 dev_err(&adapter->pdev->dev, 1477 "Get led config failed.\n"); 1478 goto mbx_err; 1479 } else { 1480 for (i = 0; i < 4; i++) 1481 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1]; 1482 } 1483 qlcnic_free_mbx_args(&cmd); 1484 /* Set LED Configuration */ 1485 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) | 1486 LSW(QLC_83XX_LED_CONFIG); 1487 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1488 QLCNIC_CMD_SET_LED_CONFIG); 1489 if (status) 1490 return status; 1491 1492 cmd.req.arg[1] = mbx_in; 1493 cmd.req.arg[2] = mbx_in; 1494 cmd.req.arg[3] = mbx_in; 1495 if (beacon) 1496 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON; 1497 status = qlcnic_issue_cmd(adapter, &cmd); 1498 if (status) { 1499 dev_err(&adapter->pdev->dev, 1500 "Set led config failed.\n"); 1501 } 1502 mbx_err: 1503 qlcnic_free_mbx_args(&cmd); 1504 return status; 1505 1506 } else { 1507 /* Restoring default LED configuration */ 1508 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1509 QLCNIC_CMD_SET_LED_CONFIG); 1510 if (status) 1511 return status; 1512 1513 cmd.req.arg[1] = adapter->ahw->mbox_reg[0]; 1514 cmd.req.arg[2] = adapter->ahw->mbox_reg[1]; 1515 cmd.req.arg[3] = adapter->ahw->mbox_reg[2]; 1516 if (beacon) 1517 cmd.req.arg[4] = adapter->ahw->mbox_reg[3]; 1518 status = qlcnic_issue_cmd(adapter, &cmd); 1519 if (status) 1520 dev_err(&adapter->pdev->dev, 1521 "Restoring led config failed.\n"); 1522 qlcnic_free_mbx_args(&cmd); 1523 return status; 1524 } 1525 } 1526 1527 int qlcnic_83xx_set_led(struct net_device *netdev, 1528 enum ethtool_phys_id_state state) 1529 { 1530 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1531 int err = -EIO, active = 1; 1532 1533 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) { 1534 netdev_warn(netdev, 1535 "LED test is not supported in non-privileged mode\n"); 1536 return -EOPNOTSUPP; 1537 } 1538 1539 switch (state) { 1540 case ETHTOOL_ID_ACTIVE: 1541 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state)) 1542 return -EBUSY; 1543 1544 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) 1545 break; 1546 1547 err = qlcnic_83xx_config_led(adapter, active, 0); 1548 if (err) 1549 netdev_err(netdev, "Failed to set LED blink state\n"); 1550 break; 1551 case ETHTOOL_ID_INACTIVE: 1552 active = 0; 1553 1554 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) 1555 break; 1556 1557 err = qlcnic_83xx_config_led(adapter, active, 0); 1558 if (err) 1559 netdev_err(netdev, "Failed to reset LED blink state\n"); 1560 break; 1561 1562 default: 1563 return -EINVAL; 1564 } 1565 1566 if (!active || err) 1567 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state); 1568 1569 return err; 1570 } 1571 1572 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable) 1573 { 1574 struct qlcnic_cmd_args cmd; 1575 int status; 1576 1577 if (qlcnic_sriov_vf_check(adapter)) 1578 return; 1579 1580 if (enable) 1581 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1582 QLCNIC_CMD_INIT_NIC_FUNC); 1583 else 1584 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1585 QLCNIC_CMD_STOP_NIC_FUNC); 1586 1587 if (status) 1588 return; 1589 1590 cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES; 1591 1592 if (adapter->dcb) 1593 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN; 1594 1595 status = qlcnic_issue_cmd(adapter, &cmd); 1596 if (status) 1597 dev_err(&adapter->pdev->dev, 1598 "Failed to %s in NIC IDC function event.\n", 1599 (enable ? "register" : "unregister")); 1600 1601 qlcnic_free_mbx_args(&cmd); 1602 } 1603 1604 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter) 1605 { 1606 struct qlcnic_cmd_args cmd; 1607 int err; 1608 1609 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG); 1610 if (err) 1611 return err; 1612 1613 cmd.req.arg[1] = adapter->ahw->port_config; 1614 err = qlcnic_issue_cmd(adapter, &cmd); 1615 if (err) 1616 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n"); 1617 qlcnic_free_mbx_args(&cmd); 1618 return err; 1619 } 1620 1621 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter) 1622 { 1623 struct qlcnic_cmd_args cmd; 1624 int err; 1625 1626 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG); 1627 if (err) 1628 return err; 1629 1630 err = qlcnic_issue_cmd(adapter, &cmd); 1631 if (err) 1632 dev_info(&adapter->pdev->dev, "Get Port config failed\n"); 1633 else 1634 adapter->ahw->port_config = cmd.rsp.arg[1]; 1635 qlcnic_free_mbx_args(&cmd); 1636 return err; 1637 } 1638 1639 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable) 1640 { 1641 int err; 1642 u32 temp; 1643 struct qlcnic_cmd_args cmd; 1644 1645 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT); 1646 if (err) 1647 return err; 1648 1649 temp = adapter->recv_ctx->context_id << 16; 1650 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp; 1651 err = qlcnic_issue_cmd(adapter, &cmd); 1652 if (err) 1653 dev_info(&adapter->pdev->dev, 1654 "Setup linkevent mailbox failed\n"); 1655 qlcnic_free_mbx_args(&cmd); 1656 return err; 1657 } 1658 1659 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter, 1660 u32 *interface_id) 1661 { 1662 if (qlcnic_sriov_pf_check(adapter)) { 1663 qlcnic_alloc_lb_filters_mem(adapter); 1664 qlcnic_pf_set_interface_id_promisc(adapter, interface_id); 1665 adapter->rx_mac_learn = true; 1666 } else { 1667 if (!qlcnic_sriov_vf_check(adapter)) 1668 *interface_id = adapter->recv_ctx->context_id << 16; 1669 } 1670 } 1671 1672 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode) 1673 { 1674 struct qlcnic_cmd_args *cmd = NULL; 1675 u32 temp = 0; 1676 int err; 1677 1678 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 1679 return -EIO; 1680 1681 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC); 1682 if (!cmd) 1683 return -ENOMEM; 1684 1685 err = qlcnic_alloc_mbx_args(cmd, adapter, 1686 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE); 1687 if (err) 1688 goto out; 1689 1690 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT; 1691 qlcnic_83xx_set_interface_id_promisc(adapter, &temp); 1692 1693 if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter)) 1694 mode = VPORT_MISS_MODE_ACCEPT_ALL; 1695 1696 cmd->req.arg[1] = mode | temp; 1697 err = qlcnic_issue_cmd(adapter, cmd); 1698 if (!err) 1699 return err; 1700 1701 qlcnic_free_mbx_args(cmd); 1702 1703 out: 1704 kfree(cmd); 1705 return err; 1706 } 1707 1708 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode) 1709 { 1710 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1711 struct qlcnic_hardware_context *ahw = adapter->ahw; 1712 u8 drv_sds_rings = adapter->drv_sds_rings; 1713 u8 drv_tx_rings = adapter->drv_tx_rings; 1714 int ret = 0, loop = 0; 1715 1716 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) { 1717 netdev_warn(netdev, 1718 "Loopback test not supported in non privileged mode\n"); 1719 return -ENOTSUPP; 1720 } 1721 1722 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1723 netdev_info(netdev, "Device is resetting\n"); 1724 return -EBUSY; 1725 } 1726 1727 if (qlcnic_get_diag_lock(adapter)) { 1728 netdev_info(netdev, "Device is in diagnostics mode\n"); 1729 return -EBUSY; 1730 } 1731 1732 netdev_info(netdev, "%s loopback test in progress\n", 1733 mode == QLCNIC_ILB_MODE ? "internal" : "external"); 1734 1735 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST, 1736 drv_sds_rings); 1737 if (ret) 1738 goto fail_diag_alloc; 1739 1740 ret = qlcnic_83xx_set_lb_mode(adapter, mode); 1741 if (ret) 1742 goto free_diag_res; 1743 1744 /* Poll for link up event before running traffic */ 1745 do { 1746 msleep(QLC_83XX_LB_MSLEEP_COUNT); 1747 1748 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1749 netdev_info(netdev, 1750 "Device is resetting, free LB test resources\n"); 1751 ret = -EBUSY; 1752 goto free_diag_res; 1753 } 1754 if (loop++ > QLC_83XX_LB_WAIT_COUNT) { 1755 netdev_info(netdev, 1756 "Firmware didn't sent link up event to loopback request\n"); 1757 ret = -ETIMEDOUT; 1758 qlcnic_83xx_clear_lb_mode(adapter, mode); 1759 goto free_diag_res; 1760 } 1761 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1); 1762 1763 ret = qlcnic_do_lb_test(adapter, mode); 1764 1765 qlcnic_83xx_clear_lb_mode(adapter, mode); 1766 1767 free_diag_res: 1768 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings); 1769 1770 fail_diag_alloc: 1771 adapter->drv_sds_rings = drv_sds_rings; 1772 adapter->drv_tx_rings = drv_tx_rings; 1773 qlcnic_release_diag_lock(adapter); 1774 return ret; 1775 } 1776 1777 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter, 1778 u32 *max_wait_count) 1779 { 1780 struct qlcnic_hardware_context *ahw = adapter->ahw; 1781 int temp; 1782 1783 netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n", 1784 ahw->extend_lb_time); 1785 temp = ahw->extend_lb_time * 1000; 1786 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT; 1787 ahw->extend_lb_time = 0; 1788 } 1789 1790 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1791 { 1792 struct qlcnic_hardware_context *ahw = adapter->ahw; 1793 struct net_device *netdev = adapter->netdev; 1794 u32 config, max_wait_count; 1795 int status = 0, loop = 0; 1796 1797 ahw->extend_lb_time = 0; 1798 max_wait_count = QLC_83XX_LB_WAIT_COUNT; 1799 status = qlcnic_83xx_get_port_config(adapter); 1800 if (status) 1801 return status; 1802 1803 config = ahw->port_config; 1804 1805 /* Check if port is already in loopback mode */ 1806 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) || 1807 (config & QLC_83XX_CFG_LOOPBACK_EXT)) { 1808 netdev_err(netdev, 1809 "Port already in Loopback mode.\n"); 1810 return -EINPROGRESS; 1811 } 1812 1813 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1814 1815 if (mode == QLCNIC_ILB_MODE) 1816 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS; 1817 if (mode == QLCNIC_ELB_MODE) 1818 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT; 1819 1820 status = qlcnic_83xx_set_port_config(adapter); 1821 if (status) { 1822 netdev_err(netdev, 1823 "Failed to Set Loopback Mode = 0x%x.\n", 1824 ahw->port_config); 1825 ahw->port_config = config; 1826 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1827 return status; 1828 } 1829 1830 /* Wait for Link and IDC Completion AEN */ 1831 do { 1832 msleep(QLC_83XX_LB_MSLEEP_COUNT); 1833 1834 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1835 netdev_info(netdev, 1836 "Device is resetting, free LB test resources\n"); 1837 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1838 return -EBUSY; 1839 } 1840 1841 if (ahw->extend_lb_time) 1842 qlcnic_extend_lb_idc_cmpltn_wait(adapter, 1843 &max_wait_count); 1844 1845 if (loop++ > max_wait_count) { 1846 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n", 1847 __func__); 1848 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1849 qlcnic_83xx_clear_lb_mode(adapter, mode); 1850 return -ETIMEDOUT; 1851 } 1852 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status)); 1853 1854 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0, 1855 QLCNIC_MAC_ADD); 1856 return status; 1857 } 1858 1859 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1860 { 1861 struct qlcnic_hardware_context *ahw = adapter->ahw; 1862 u32 config = ahw->port_config, max_wait_count; 1863 struct net_device *netdev = adapter->netdev; 1864 int status = 0, loop = 0; 1865 1866 ahw->extend_lb_time = 0; 1867 max_wait_count = QLC_83XX_LB_WAIT_COUNT; 1868 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1869 if (mode == QLCNIC_ILB_MODE) 1870 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS; 1871 if (mode == QLCNIC_ELB_MODE) 1872 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT; 1873 1874 status = qlcnic_83xx_set_port_config(adapter); 1875 if (status) { 1876 netdev_err(netdev, 1877 "Failed to Clear Loopback Mode = 0x%x.\n", 1878 ahw->port_config); 1879 ahw->port_config = config; 1880 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1881 return status; 1882 } 1883 1884 /* Wait for Link and IDC Completion AEN */ 1885 do { 1886 msleep(QLC_83XX_LB_MSLEEP_COUNT); 1887 1888 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1889 netdev_info(netdev, 1890 "Device is resetting, free LB test resources\n"); 1891 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1892 return -EBUSY; 1893 } 1894 1895 if (ahw->extend_lb_time) 1896 qlcnic_extend_lb_idc_cmpltn_wait(adapter, 1897 &max_wait_count); 1898 1899 if (loop++ > max_wait_count) { 1900 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n", 1901 __func__); 1902 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1903 return -ETIMEDOUT; 1904 } 1905 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status)); 1906 1907 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0, 1908 QLCNIC_MAC_DEL); 1909 return status; 1910 } 1911 1912 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter, 1913 u32 *interface_id) 1914 { 1915 if (qlcnic_sriov_pf_check(adapter)) { 1916 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id); 1917 } else { 1918 if (!qlcnic_sriov_vf_check(adapter)) 1919 *interface_id = adapter->recv_ctx->context_id << 16; 1920 } 1921 } 1922 1923 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, 1924 int mode) 1925 { 1926 int err; 1927 u32 temp = 0, temp_ip; 1928 struct qlcnic_cmd_args cmd; 1929 1930 err = qlcnic_alloc_mbx_args(&cmd, adapter, 1931 QLCNIC_CMD_CONFIGURE_IP_ADDR); 1932 if (err) 1933 return; 1934 1935 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp); 1936 1937 if (mode == QLCNIC_IP_UP) 1938 cmd.req.arg[1] = 1 | temp; 1939 else 1940 cmd.req.arg[1] = 2 | temp; 1941 1942 /* 1943 * Adapter needs IP address in network byte order. 1944 * But hardware mailbox registers go through writel(), hence IP address 1945 * gets swapped on big endian architecture. 1946 * To negate swapping of writel() on big endian architecture 1947 * use swab32(value). 1948 */ 1949 1950 temp_ip = swab32(ntohl(ip)); 1951 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32)); 1952 err = qlcnic_issue_cmd(adapter, &cmd); 1953 if (err != QLCNIC_RCODE_SUCCESS) 1954 dev_err(&adapter->netdev->dev, 1955 "could not notify %s IP 0x%x request\n", 1956 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip); 1957 1958 qlcnic_free_mbx_args(&cmd); 1959 } 1960 1961 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode) 1962 { 1963 int err; 1964 u32 temp, arg1; 1965 struct qlcnic_cmd_args cmd; 1966 int lro_bit_mask; 1967 1968 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); 1969 1970 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 1971 return 0; 1972 1973 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO); 1974 if (err) 1975 return err; 1976 1977 temp = adapter->recv_ctx->context_id << 16; 1978 arg1 = lro_bit_mask | temp; 1979 cmd.req.arg[1] = arg1; 1980 1981 err = qlcnic_issue_cmd(adapter, &cmd); 1982 if (err) 1983 dev_info(&adapter->pdev->dev, "LRO config failed\n"); 1984 qlcnic_free_mbx_args(&cmd); 1985 1986 return err; 1987 } 1988 1989 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable) 1990 { 1991 int err; 1992 u32 word; 1993 struct qlcnic_cmd_args cmd; 1994 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, 1995 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, 1996 0x255b0ec26d5a56daULL }; 1997 1998 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS); 1999 if (err) 2000 return err; 2001 /* 2002 * RSS request: 2003 * bits 3-0: Rsvd 2004 * 5-4: hash_type_ipv4 2005 * 7-6: hash_type_ipv6 2006 * 8: enable 2007 * 9: use indirection table 2008 * 16-31: indirection table mask 2009 */ 2010 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | 2011 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | 2012 ((u32)(enable & 0x1) << 8) | 2013 ((0x7ULL) << 16); 2014 cmd.req.arg[1] = (adapter->recv_ctx->context_id); 2015 cmd.req.arg[2] = word; 2016 memcpy(&cmd.req.arg[4], key, sizeof(key)); 2017 2018 err = qlcnic_issue_cmd(adapter, &cmd); 2019 2020 if (err) 2021 dev_info(&adapter->pdev->dev, "RSS config failed\n"); 2022 qlcnic_free_mbx_args(&cmd); 2023 2024 return err; 2025 2026 } 2027 2028 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter, 2029 u32 *interface_id) 2030 { 2031 if (qlcnic_sriov_pf_check(adapter)) { 2032 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id); 2033 } else { 2034 if (!qlcnic_sriov_vf_check(adapter)) 2035 *interface_id = adapter->recv_ctx->context_id << 16; 2036 } 2037 } 2038 2039 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr, 2040 u16 vlan_id, u8 op) 2041 { 2042 struct qlcnic_cmd_args *cmd = NULL; 2043 struct qlcnic_macvlan_mbx mv; 2044 u32 *buf, temp = 0; 2045 int err; 2046 2047 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 2048 return -EIO; 2049 2050 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC); 2051 if (!cmd) 2052 return -ENOMEM; 2053 2054 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN); 2055 if (err) 2056 goto out; 2057 2058 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT; 2059 2060 if (vlan_id) 2061 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ? 2062 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL; 2063 2064 cmd->req.arg[1] = op | (1 << 8); 2065 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp); 2066 cmd->req.arg[1] |= temp; 2067 mv.vlan = vlan_id; 2068 mv.mac_addr0 = addr[0]; 2069 mv.mac_addr1 = addr[1]; 2070 mv.mac_addr2 = addr[2]; 2071 mv.mac_addr3 = addr[3]; 2072 mv.mac_addr4 = addr[4]; 2073 mv.mac_addr5 = addr[5]; 2074 buf = &cmd->req.arg[2]; 2075 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx)); 2076 err = qlcnic_issue_cmd(adapter, cmd); 2077 if (!err) 2078 return err; 2079 2080 qlcnic_free_mbx_args(cmd); 2081 out: 2082 kfree(cmd); 2083 return err; 2084 } 2085 2086 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr, 2087 u16 vlan_id) 2088 { 2089 u8 mac[ETH_ALEN]; 2090 memcpy(&mac, addr, ETH_ALEN); 2091 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD); 2092 } 2093 2094 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac, 2095 u8 type, struct qlcnic_cmd_args *cmd) 2096 { 2097 switch (type) { 2098 case QLCNIC_SET_STATION_MAC: 2099 case QLCNIC_SET_FAC_DEF_MAC: 2100 memcpy(&cmd->req.arg[2], mac, sizeof(u32)); 2101 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16)); 2102 break; 2103 } 2104 cmd->req.arg[1] = type; 2105 } 2106 2107 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac, 2108 u8 function) 2109 { 2110 int err, i; 2111 struct qlcnic_cmd_args cmd; 2112 u32 mac_low, mac_high; 2113 2114 function = 0; 2115 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS); 2116 if (err) 2117 return err; 2118 2119 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd); 2120 err = qlcnic_issue_cmd(adapter, &cmd); 2121 2122 if (err == QLCNIC_RCODE_SUCCESS) { 2123 mac_low = cmd.rsp.arg[1]; 2124 mac_high = cmd.rsp.arg[2]; 2125 2126 for (i = 0; i < 2; i++) 2127 mac[i] = (u8) (mac_high >> ((1 - i) * 8)); 2128 for (i = 2; i < 6; i++) 2129 mac[i] = (u8) (mac_low >> ((5 - i) * 8)); 2130 } else { 2131 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n", 2132 err); 2133 err = -EIO; 2134 } 2135 qlcnic_free_mbx_args(&cmd); 2136 return err; 2137 } 2138 2139 static int qlcnic_83xx_set_rx_intr_coal(struct qlcnic_adapter *adapter) 2140 { 2141 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal; 2142 struct qlcnic_cmd_args cmd; 2143 u16 temp; 2144 int err; 2145 2146 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL); 2147 if (err) 2148 return err; 2149 2150 temp = adapter->recv_ctx->context_id; 2151 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16; 2152 temp = coal->rx_time_us; 2153 cmd.req.arg[2] = coal->rx_packets | temp << 16; 2154 cmd.req.arg[3] = coal->flag; 2155 2156 err = qlcnic_issue_cmd(adapter, &cmd); 2157 if (err != QLCNIC_RCODE_SUCCESS) 2158 netdev_err(adapter->netdev, 2159 "failed to set interrupt coalescing parameters\n"); 2160 2161 qlcnic_free_mbx_args(&cmd); 2162 2163 return err; 2164 } 2165 2166 static int qlcnic_83xx_set_tx_intr_coal(struct qlcnic_adapter *adapter) 2167 { 2168 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal; 2169 struct qlcnic_cmd_args cmd; 2170 u16 temp; 2171 int err; 2172 2173 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL); 2174 if (err) 2175 return err; 2176 2177 temp = adapter->tx_ring->ctx_id; 2178 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16; 2179 temp = coal->tx_time_us; 2180 cmd.req.arg[2] = coal->tx_packets | temp << 16; 2181 cmd.req.arg[3] = coal->flag; 2182 2183 err = qlcnic_issue_cmd(adapter, &cmd); 2184 if (err != QLCNIC_RCODE_SUCCESS) 2185 netdev_err(adapter->netdev, 2186 "failed to set interrupt coalescing parameters\n"); 2187 2188 qlcnic_free_mbx_args(&cmd); 2189 2190 return err; 2191 } 2192 2193 int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *adapter) 2194 { 2195 int err = 0; 2196 2197 err = qlcnic_83xx_set_rx_intr_coal(adapter); 2198 if (err) 2199 netdev_err(adapter->netdev, 2200 "failed to set Rx coalescing parameters\n"); 2201 2202 err = qlcnic_83xx_set_tx_intr_coal(adapter); 2203 if (err) 2204 netdev_err(adapter->netdev, 2205 "failed to set Tx coalescing parameters\n"); 2206 2207 return err; 2208 } 2209 2210 int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter, 2211 struct ethtool_coalesce *ethcoal) 2212 { 2213 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal; 2214 u32 rx_coalesce_usecs, rx_max_frames; 2215 u32 tx_coalesce_usecs, tx_max_frames; 2216 int err; 2217 2218 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 2219 return -EIO; 2220 2221 tx_coalesce_usecs = ethcoal->tx_coalesce_usecs; 2222 tx_max_frames = ethcoal->tx_max_coalesced_frames; 2223 rx_coalesce_usecs = ethcoal->rx_coalesce_usecs; 2224 rx_max_frames = ethcoal->rx_max_coalesced_frames; 2225 coal->flag = QLCNIC_INTR_DEFAULT; 2226 2227 if ((coal->rx_time_us == rx_coalesce_usecs) && 2228 (coal->rx_packets == rx_max_frames)) { 2229 coal->type = QLCNIC_INTR_COAL_TYPE_TX; 2230 coal->tx_time_us = tx_coalesce_usecs; 2231 coal->tx_packets = tx_max_frames; 2232 } else if ((coal->tx_time_us == tx_coalesce_usecs) && 2233 (coal->tx_packets == tx_max_frames)) { 2234 coal->type = QLCNIC_INTR_COAL_TYPE_RX; 2235 coal->rx_time_us = rx_coalesce_usecs; 2236 coal->rx_packets = rx_max_frames; 2237 } else { 2238 coal->type = QLCNIC_INTR_COAL_TYPE_RX_TX; 2239 coal->rx_time_us = rx_coalesce_usecs; 2240 coal->rx_packets = rx_max_frames; 2241 coal->tx_time_us = tx_coalesce_usecs; 2242 coal->tx_packets = tx_max_frames; 2243 } 2244 2245 switch (coal->type) { 2246 case QLCNIC_INTR_COAL_TYPE_RX: 2247 err = qlcnic_83xx_set_rx_intr_coal(adapter); 2248 break; 2249 case QLCNIC_INTR_COAL_TYPE_TX: 2250 err = qlcnic_83xx_set_tx_intr_coal(adapter); 2251 break; 2252 case QLCNIC_INTR_COAL_TYPE_RX_TX: 2253 err = qlcnic_83xx_set_rx_tx_intr_coal(adapter); 2254 break; 2255 default: 2256 err = -EINVAL; 2257 netdev_err(adapter->netdev, 2258 "Invalid Interrupt coalescing type\n"); 2259 break; 2260 } 2261 2262 return err; 2263 } 2264 2265 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter, 2266 u32 data[]) 2267 { 2268 struct qlcnic_hardware_context *ahw = adapter->ahw; 2269 u8 link_status, duplex; 2270 /* link speed */ 2271 link_status = LSB(data[3]) & 1; 2272 if (link_status) { 2273 ahw->link_speed = MSW(data[2]); 2274 duplex = LSB(MSW(data[3])); 2275 if (duplex) 2276 ahw->link_duplex = DUPLEX_FULL; 2277 else 2278 ahw->link_duplex = DUPLEX_HALF; 2279 } else { 2280 ahw->link_speed = SPEED_UNKNOWN; 2281 ahw->link_duplex = DUPLEX_UNKNOWN; 2282 } 2283 2284 ahw->link_autoneg = MSB(MSW(data[3])); 2285 ahw->module_type = MSB(LSW(data[3])); 2286 ahw->has_link_events = 1; 2287 ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK; 2288 qlcnic_advert_link_change(adapter, link_status); 2289 } 2290 2291 static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data) 2292 { 2293 struct qlcnic_adapter *adapter = data; 2294 struct qlcnic_mailbox *mbx; 2295 u32 mask, resp, event; 2296 unsigned long flags; 2297 2298 mbx = adapter->ahw->mailbox; 2299 spin_lock_irqsave(&mbx->aen_lock, flags); 2300 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL); 2301 if (!(resp & QLCNIC_SET_OWNER)) 2302 goto out; 2303 2304 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0)); 2305 if (event & QLCNIC_MBX_ASYNC_EVENT) 2306 __qlcnic_83xx_process_aen(adapter); 2307 else 2308 qlcnic_83xx_notify_mbx_response(mbx); 2309 2310 out: 2311 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); 2312 writel(0, adapter->ahw->pci_base0 + mask); 2313 spin_unlock_irqrestore(&mbx->aen_lock, flags); 2314 return IRQ_HANDLED; 2315 } 2316 2317 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter, 2318 struct qlcnic_info *nic) 2319 { 2320 int i, err = -EIO; 2321 struct qlcnic_cmd_args cmd; 2322 2323 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) { 2324 dev_err(&adapter->pdev->dev, 2325 "%s: Error, invoked by non management func\n", 2326 __func__); 2327 return err; 2328 } 2329 2330 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO); 2331 if (err) 2332 return err; 2333 2334 cmd.req.arg[1] = (nic->pci_func << 16); 2335 cmd.req.arg[2] = 0x1 << 16; 2336 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16); 2337 cmd.req.arg[4] = nic->capabilities; 2338 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16); 2339 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16); 2340 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16); 2341 for (i = 8; i < 32; i++) 2342 cmd.req.arg[i] = 0; 2343 2344 err = qlcnic_issue_cmd(adapter, &cmd); 2345 2346 if (err != QLCNIC_RCODE_SUCCESS) { 2347 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n", 2348 err); 2349 err = -EIO; 2350 } 2351 2352 qlcnic_free_mbx_args(&cmd); 2353 2354 return err; 2355 } 2356 2357 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter, 2358 struct qlcnic_info *npar_info, u8 func_id) 2359 { 2360 int err; 2361 u32 temp; 2362 u8 op = 0; 2363 struct qlcnic_cmd_args cmd; 2364 struct qlcnic_hardware_context *ahw = adapter->ahw; 2365 2366 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO); 2367 if (err) 2368 return err; 2369 2370 if (func_id != ahw->pci_func) { 2371 temp = func_id << 16; 2372 cmd.req.arg[1] = op | BIT_31 | temp; 2373 } else { 2374 cmd.req.arg[1] = ahw->pci_func << 16; 2375 } 2376 err = qlcnic_issue_cmd(adapter, &cmd); 2377 if (err) { 2378 dev_info(&adapter->pdev->dev, 2379 "Failed to get nic info %d\n", err); 2380 goto out; 2381 } 2382 2383 npar_info->op_type = cmd.rsp.arg[1]; 2384 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF; 2385 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16; 2386 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF; 2387 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16; 2388 npar_info->capabilities = cmd.rsp.arg[4]; 2389 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF; 2390 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16; 2391 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF; 2392 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16; 2393 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF; 2394 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16; 2395 if (cmd.rsp.arg[8] & 0x1) 2396 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1; 2397 if (cmd.rsp.arg[8] & 0x10000) { 2398 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17; 2399 npar_info->max_linkspeed_reg_offset = temp; 2400 } 2401 2402 memcpy(ahw->extra_capability, &cmd.rsp.arg[16], 2403 sizeof(ahw->extra_capability)); 2404 2405 out: 2406 qlcnic_free_mbx_args(&cmd); 2407 return err; 2408 } 2409 2410 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type, 2411 u16 *nic, u16 *fcoe, u16 *iscsi) 2412 { 2413 struct device *dev = &adapter->pdev->dev; 2414 int err = 0; 2415 2416 switch (type) { 2417 case QLCNIC_TYPE_NIC: 2418 (*nic)++; 2419 break; 2420 case QLCNIC_TYPE_FCOE: 2421 (*fcoe)++; 2422 break; 2423 case QLCNIC_TYPE_ISCSI: 2424 (*iscsi)++; 2425 break; 2426 default: 2427 dev_err(dev, "%s: Unknown PCI type[%x]\n", 2428 __func__, type); 2429 err = -EIO; 2430 } 2431 2432 return err; 2433 } 2434 2435 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter, 2436 struct qlcnic_pci_info *pci_info) 2437 { 2438 struct qlcnic_hardware_context *ahw = adapter->ahw; 2439 struct device *dev = &adapter->pdev->dev; 2440 u16 nic = 0, fcoe = 0, iscsi = 0; 2441 struct qlcnic_cmd_args cmd; 2442 int i, err = 0, j = 0; 2443 u32 temp; 2444 2445 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO); 2446 if (err) 2447 return err; 2448 2449 err = qlcnic_issue_cmd(adapter, &cmd); 2450 2451 ahw->total_nic_func = 0; 2452 if (err == QLCNIC_RCODE_SUCCESS) { 2453 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF; 2454 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) { 2455 pci_info->id = cmd.rsp.arg[i] & 0xFFFF; 2456 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; 2457 i++; 2458 if (!pci_info->active) { 2459 i += QLC_SKIP_INACTIVE_PCI_REGS; 2460 continue; 2461 } 2462 pci_info->type = cmd.rsp.arg[i] & 0xFFFF; 2463 err = qlcnic_get_pci_func_type(adapter, pci_info->type, 2464 &nic, &fcoe, &iscsi); 2465 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; 2466 pci_info->default_port = temp; 2467 i++; 2468 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF; 2469 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; 2470 pci_info->tx_max_bw = temp; 2471 i = i + 2; 2472 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2); 2473 i++; 2474 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2); 2475 i = i + 3; 2476 } 2477 } else { 2478 dev_err(dev, "Failed to get PCI Info, error = %d\n", err); 2479 err = -EIO; 2480 } 2481 2482 ahw->total_nic_func = nic; 2483 ahw->total_pci_func = nic + fcoe + iscsi; 2484 if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) { 2485 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n", 2486 __func__, ahw->total_nic_func, ahw->total_pci_func); 2487 err = -EIO; 2488 } 2489 qlcnic_free_mbx_args(&cmd); 2490 2491 return err; 2492 } 2493 2494 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type) 2495 { 2496 int i, index, err; 2497 u8 max_ints; 2498 u32 val, temp, type; 2499 struct qlcnic_cmd_args cmd; 2500 2501 max_ints = adapter->ahw->num_msix - 1; 2502 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT); 2503 if (err) 2504 return err; 2505 2506 cmd.req.arg[1] = max_ints; 2507 2508 if (qlcnic_sriov_vf_check(adapter)) 2509 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16; 2510 2511 for (i = 0, index = 2; i < max_ints; i++) { 2512 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL; 2513 val = type | (adapter->ahw->intr_tbl[i].type << 4); 2514 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX) 2515 val |= (adapter->ahw->intr_tbl[i].id << 16); 2516 cmd.req.arg[index++] = val; 2517 } 2518 err = qlcnic_issue_cmd(adapter, &cmd); 2519 if (err) { 2520 dev_err(&adapter->pdev->dev, 2521 "Failed to configure interrupts 0x%x\n", err); 2522 goto out; 2523 } 2524 2525 max_ints = cmd.rsp.arg[1]; 2526 for (i = 0, index = 2; i < max_ints; i++, index += 2) { 2527 val = cmd.rsp.arg[index]; 2528 if (LSB(val)) { 2529 dev_info(&adapter->pdev->dev, 2530 "Can't configure interrupt %d\n", 2531 adapter->ahw->intr_tbl[i].id); 2532 continue; 2533 } 2534 if (op_type) { 2535 adapter->ahw->intr_tbl[i].id = MSW(val); 2536 adapter->ahw->intr_tbl[i].enabled = 1; 2537 temp = cmd.rsp.arg[index + 1]; 2538 adapter->ahw->intr_tbl[i].src = temp; 2539 } else { 2540 adapter->ahw->intr_tbl[i].id = i; 2541 adapter->ahw->intr_tbl[i].enabled = 0; 2542 adapter->ahw->intr_tbl[i].src = 0; 2543 } 2544 } 2545 out: 2546 qlcnic_free_mbx_args(&cmd); 2547 return err; 2548 } 2549 2550 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter) 2551 { 2552 int id, timeout = 0; 2553 u32 status = 0; 2554 2555 while (status == 0) { 2556 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK); 2557 if (status) 2558 break; 2559 2560 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) { 2561 id = QLC_SHARED_REG_RD32(adapter, 2562 QLCNIC_FLASH_LOCK_OWNER); 2563 dev_err(&adapter->pdev->dev, 2564 "%s: failed, lock held by %d\n", __func__, id); 2565 return -EIO; 2566 } 2567 usleep_range(1000, 2000); 2568 } 2569 2570 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum); 2571 return 0; 2572 } 2573 2574 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter) 2575 { 2576 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK); 2577 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF); 2578 } 2579 2580 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter, 2581 u32 flash_addr, u8 *p_data, 2582 int count) 2583 { 2584 u32 word, range, flash_offset, addr = flash_addr, ret; 2585 ulong indirect_add, direct_window; 2586 int i, err = 0; 2587 2588 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1); 2589 if (addr & 0x3) { 2590 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr); 2591 return -EIO; 2592 } 2593 2594 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW, 2595 (addr)); 2596 2597 range = flash_offset + (count * sizeof(u32)); 2598 /* Check if data is spread across multiple sectors */ 2599 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) { 2600 2601 /* Multi sector read */ 2602 for (i = 0; i < count; i++) { 2603 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr); 2604 ret = QLCRD32(adapter, indirect_add, &err); 2605 if (err == -EIO) 2606 return err; 2607 2608 word = ret; 2609 *(u32 *)p_data = word; 2610 p_data = p_data + 4; 2611 addr = addr + 4; 2612 flash_offset = flash_offset + 4; 2613 2614 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) { 2615 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW; 2616 /* This write is needed once for each sector */ 2617 qlcnic_83xx_wrt_reg_indirect(adapter, 2618 direct_window, 2619 (addr)); 2620 flash_offset = 0; 2621 } 2622 } 2623 } else { 2624 /* Single sector read */ 2625 for (i = 0; i < count; i++) { 2626 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr); 2627 ret = QLCRD32(adapter, indirect_add, &err); 2628 if (err == -EIO) 2629 return err; 2630 2631 word = ret; 2632 *(u32 *)p_data = word; 2633 p_data = p_data + 4; 2634 addr = addr + 4; 2635 } 2636 } 2637 2638 return 0; 2639 } 2640 2641 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter) 2642 { 2643 u32 status; 2644 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT; 2645 int err = 0; 2646 2647 do { 2648 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err); 2649 if (err == -EIO) 2650 return err; 2651 2652 if ((status & QLC_83XX_FLASH_STATUS_READY) == 2653 QLC_83XX_FLASH_STATUS_READY) 2654 break; 2655 2656 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY); 2657 } while (--retries); 2658 2659 if (!retries) 2660 return -EIO; 2661 2662 return 0; 2663 } 2664 2665 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter) 2666 { 2667 int ret; 2668 u32 cmd; 2669 cmd = adapter->ahw->fdt.write_statusreg_cmd; 2670 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2671 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd)); 2672 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2673 adapter->ahw->fdt.write_enable_bits); 2674 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2675 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL); 2676 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2677 if (ret) 2678 return -EIO; 2679 2680 return 0; 2681 } 2682 2683 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter) 2684 { 2685 int ret; 2686 2687 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2688 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | 2689 adapter->ahw->fdt.write_statusreg_cmd)); 2690 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2691 adapter->ahw->fdt.write_disable_bits); 2692 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2693 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL); 2694 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2695 if (ret) 2696 return -EIO; 2697 2698 return 0; 2699 } 2700 2701 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter) 2702 { 2703 int ret, err = 0; 2704 u32 mfg_id; 2705 2706 if (qlcnic_83xx_lock_flash(adapter)) 2707 return -EIO; 2708 2709 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2710 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL); 2711 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2712 QLC_83XX_FLASH_READ_CTRL); 2713 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2714 if (ret) { 2715 qlcnic_83xx_unlock_flash(adapter); 2716 return -EIO; 2717 } 2718 2719 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err); 2720 if (err == -EIO) { 2721 qlcnic_83xx_unlock_flash(adapter); 2722 return err; 2723 } 2724 2725 adapter->flash_mfg_id = (mfg_id & 0xFF); 2726 qlcnic_83xx_unlock_flash(adapter); 2727 2728 return 0; 2729 } 2730 2731 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter) 2732 { 2733 int count, fdt_size, ret = 0; 2734 2735 fdt_size = sizeof(struct qlcnic_fdt); 2736 count = fdt_size / sizeof(u32); 2737 2738 if (qlcnic_83xx_lock_flash(adapter)) 2739 return -EIO; 2740 2741 memset(&adapter->ahw->fdt, 0, fdt_size); 2742 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION, 2743 (u8 *)&adapter->ahw->fdt, 2744 count); 2745 2746 qlcnic_83xx_unlock_flash(adapter); 2747 return ret; 2748 } 2749 2750 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter, 2751 u32 sector_start_addr) 2752 { 2753 u32 reversed_addr, addr1, addr2, cmd; 2754 int ret = -EIO; 2755 2756 if (qlcnic_83xx_lock_flash(adapter) != 0) 2757 return -EIO; 2758 2759 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) { 2760 ret = qlcnic_83xx_enable_flash_write(adapter); 2761 if (ret) { 2762 qlcnic_83xx_unlock_flash(adapter); 2763 dev_err(&adapter->pdev->dev, 2764 "%s failed at %d\n", 2765 __func__, __LINE__); 2766 return ret; 2767 } 2768 } 2769 2770 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2771 if (ret) { 2772 qlcnic_83xx_unlock_flash(adapter); 2773 dev_err(&adapter->pdev->dev, 2774 "%s: failed at %d\n", __func__, __LINE__); 2775 return -EIO; 2776 } 2777 2778 addr1 = (sector_start_addr & 0xFF) << 16; 2779 addr2 = (sector_start_addr & 0xFF0000) >> 16; 2780 reversed_addr = addr1 | addr2; 2781 2782 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2783 reversed_addr); 2784 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd; 2785 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) 2786 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd); 2787 else 2788 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2789 QLC_83XX_FLASH_OEM_ERASE_SIG); 2790 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2791 QLC_83XX_FLASH_LAST_ERASE_MS_VAL); 2792 2793 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2794 if (ret) { 2795 qlcnic_83xx_unlock_flash(adapter); 2796 dev_err(&adapter->pdev->dev, 2797 "%s: failed at %d\n", __func__, __LINE__); 2798 return -EIO; 2799 } 2800 2801 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) { 2802 ret = qlcnic_83xx_disable_flash_write(adapter); 2803 if (ret) { 2804 qlcnic_83xx_unlock_flash(adapter); 2805 dev_err(&adapter->pdev->dev, 2806 "%s: failed at %d\n", __func__, __LINE__); 2807 return ret; 2808 } 2809 } 2810 2811 qlcnic_83xx_unlock_flash(adapter); 2812 2813 return 0; 2814 } 2815 2816 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr, 2817 u32 *p_data) 2818 { 2819 int ret = -EIO; 2820 u32 addr1 = 0x00800000 | (addr >> 2); 2821 2822 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1); 2823 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data); 2824 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2825 QLC_83XX_FLASH_LAST_ERASE_MS_VAL); 2826 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2827 if (ret) { 2828 dev_err(&adapter->pdev->dev, 2829 "%s: failed at %d\n", __func__, __LINE__); 2830 return -EIO; 2831 } 2832 2833 return 0; 2834 } 2835 2836 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr, 2837 u32 *p_data, int count) 2838 { 2839 u32 temp; 2840 int ret = -EIO, err = 0; 2841 2842 if ((count < QLC_83XX_FLASH_WRITE_MIN) || 2843 (count > QLC_83XX_FLASH_WRITE_MAX)) { 2844 dev_err(&adapter->pdev->dev, 2845 "%s: Invalid word count\n", __func__); 2846 return -EIO; 2847 } 2848 2849 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err); 2850 if (err == -EIO) 2851 return err; 2852 2853 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL, 2854 (temp | QLC_83XX_FLASH_SPI_CTRL)); 2855 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2856 QLC_83XX_FLASH_ADDR_TEMP_VAL); 2857 2858 /* First DWORD write */ 2859 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++); 2860 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2861 QLC_83XX_FLASH_FIRST_MS_PATTERN); 2862 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2863 if (ret) { 2864 dev_err(&adapter->pdev->dev, 2865 "%s: failed at %d\n", __func__, __LINE__); 2866 return -EIO; 2867 } 2868 2869 count--; 2870 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2871 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL); 2872 /* Second to N-1 DWORD writes */ 2873 while (count != 1) { 2874 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2875 *p_data++); 2876 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2877 QLC_83XX_FLASH_SECOND_MS_PATTERN); 2878 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2879 if (ret) { 2880 dev_err(&adapter->pdev->dev, 2881 "%s: failed at %d\n", __func__, __LINE__); 2882 return -EIO; 2883 } 2884 count--; 2885 } 2886 2887 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2888 QLC_83XX_FLASH_ADDR_TEMP_VAL | 2889 (addr >> 2)); 2890 /* Last DWORD write */ 2891 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++); 2892 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2893 QLC_83XX_FLASH_LAST_MS_PATTERN); 2894 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2895 if (ret) { 2896 dev_err(&adapter->pdev->dev, 2897 "%s: failed at %d\n", __func__, __LINE__); 2898 return -EIO; 2899 } 2900 2901 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err); 2902 if (err == -EIO) 2903 return err; 2904 2905 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) { 2906 dev_err(&adapter->pdev->dev, "%s: failed at %d\n", 2907 __func__, __LINE__); 2908 /* Operation failed, clear error bit */ 2909 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err); 2910 if (err == -EIO) 2911 return err; 2912 2913 qlcnic_83xx_wrt_reg_indirect(adapter, 2914 QLC_83XX_FLASH_SPI_CONTROL, 2915 (temp | QLC_83XX_FLASH_SPI_CTRL)); 2916 } 2917 2918 return 0; 2919 } 2920 2921 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter) 2922 { 2923 u32 val, id; 2924 2925 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK); 2926 2927 /* Check if recovery need to be performed by the calling function */ 2928 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) { 2929 val = val & ~0x3F; 2930 val = val | ((adapter->portnum << 2) | 2931 QLC_83XX_NEED_DRV_LOCK_RECOVERY); 2932 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); 2933 dev_info(&adapter->pdev->dev, 2934 "%s: lock recovery initiated\n", __func__); 2935 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY); 2936 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK); 2937 id = ((val >> 2) & 0xF); 2938 if (id == adapter->portnum) { 2939 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK; 2940 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS; 2941 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); 2942 /* Force release the lock */ 2943 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK); 2944 /* Clear recovery bits */ 2945 val = val & ~0x3F; 2946 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); 2947 dev_info(&adapter->pdev->dev, 2948 "%s: lock recovery completed\n", __func__); 2949 } else { 2950 dev_info(&adapter->pdev->dev, 2951 "%s: func %d to resume lock recovery process\n", 2952 __func__, id); 2953 } 2954 } else { 2955 dev_info(&adapter->pdev->dev, 2956 "%s: lock recovery initiated by other functions\n", 2957 __func__); 2958 } 2959 } 2960 2961 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter) 2962 { 2963 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0; 2964 int max_attempt = 0; 2965 2966 while (status == 0) { 2967 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK); 2968 if (status) 2969 break; 2970 2971 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY); 2972 i++; 2973 2974 if (i == 1) 2975 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 2976 2977 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) { 2978 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 2979 if (val == temp) { 2980 id = val & 0xFF; 2981 dev_info(&adapter->pdev->dev, 2982 "%s: lock to be recovered from %d\n", 2983 __func__, id); 2984 qlcnic_83xx_recover_driver_lock(adapter); 2985 i = 0; 2986 max_attempt++; 2987 } else { 2988 dev_err(&adapter->pdev->dev, 2989 "%s: failed to get lock\n", __func__); 2990 return -EIO; 2991 } 2992 } 2993 2994 /* Force exit from while loop after few attempts */ 2995 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) { 2996 dev_err(&adapter->pdev->dev, 2997 "%s: failed to get lock\n", __func__); 2998 return -EIO; 2999 } 3000 } 3001 3002 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 3003 lock_alive_counter = val >> 8; 3004 lock_alive_counter++; 3005 val = lock_alive_counter << 8 | adapter->portnum; 3006 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val); 3007 3008 return 0; 3009 } 3010 3011 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter) 3012 { 3013 u32 val, lock_alive_counter, id; 3014 3015 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 3016 id = val & 0xFF; 3017 lock_alive_counter = val >> 8; 3018 3019 if (id != adapter->portnum) 3020 dev_err(&adapter->pdev->dev, 3021 "%s:Warning func %d is unlocking lock owned by %d\n", 3022 __func__, adapter->portnum, id); 3023 3024 val = (lock_alive_counter << 8) | 0xFF; 3025 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val); 3026 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK); 3027 } 3028 3029 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr, 3030 u32 *data, u32 count) 3031 { 3032 int i, j, ret = 0; 3033 u32 temp; 3034 int err = 0; 3035 3036 /* Check alignment */ 3037 if (addr & 0xF) 3038 return -EIO; 3039 3040 mutex_lock(&adapter->ahw->mem_lock); 3041 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0); 3042 3043 for (i = 0; i < count; i++, addr += 16) { 3044 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET, 3045 QLCNIC_ADDR_QDR_NET_MAX)) || 3046 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET, 3047 QLCNIC_ADDR_DDR_NET_MAX)))) { 3048 mutex_unlock(&adapter->ahw->mem_lock); 3049 return -EIO; 3050 } 3051 3052 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr); 3053 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO, 3054 *data++); 3055 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI, 3056 *data++); 3057 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO, 3058 *data++); 3059 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI, 3060 *data++); 3061 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL, 3062 QLCNIC_TA_WRITE_ENABLE); 3063 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL, 3064 QLCNIC_TA_WRITE_START); 3065 3066 for (j = 0; j < MAX_CTL_CHECK; j++) { 3067 temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err); 3068 if (err == -EIO) { 3069 mutex_unlock(&adapter->ahw->mem_lock); 3070 return err; 3071 } 3072 3073 if ((temp & TA_CTL_BUSY) == 0) 3074 break; 3075 } 3076 3077 /* Status check failure */ 3078 if (j >= MAX_CTL_CHECK) { 3079 printk_ratelimited(KERN_WARNING 3080 "MS memory write failed\n"); 3081 mutex_unlock(&adapter->ahw->mem_lock); 3082 return -EIO; 3083 } 3084 } 3085 3086 mutex_unlock(&adapter->ahw->mem_lock); 3087 3088 return ret; 3089 } 3090 3091 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr, 3092 u8 *p_data, int count) 3093 { 3094 u32 word, addr = flash_addr, ret; 3095 ulong indirect_addr; 3096 int i, err = 0; 3097 3098 if (qlcnic_83xx_lock_flash(adapter) != 0) 3099 return -EIO; 3100 3101 if (addr & 0x3) { 3102 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr); 3103 qlcnic_83xx_unlock_flash(adapter); 3104 return -EIO; 3105 } 3106 3107 for (i = 0; i < count; i++) { 3108 if (qlcnic_83xx_wrt_reg_indirect(adapter, 3109 QLC_83XX_FLASH_DIRECT_WINDOW, 3110 (addr))) { 3111 qlcnic_83xx_unlock_flash(adapter); 3112 return -EIO; 3113 } 3114 3115 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr); 3116 ret = QLCRD32(adapter, indirect_addr, &err); 3117 if (err == -EIO) 3118 return err; 3119 3120 word = ret; 3121 *(u32 *)p_data = word; 3122 p_data = p_data + 4; 3123 addr = addr + 4; 3124 } 3125 3126 qlcnic_83xx_unlock_flash(adapter); 3127 3128 return 0; 3129 } 3130 3131 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter) 3132 { 3133 u8 pci_func; 3134 int err; 3135 u32 config = 0, state; 3136 struct qlcnic_cmd_args cmd; 3137 struct qlcnic_hardware_context *ahw = adapter->ahw; 3138 3139 if (qlcnic_sriov_vf_check(adapter)) 3140 pci_func = adapter->portnum; 3141 else 3142 pci_func = ahw->pci_func; 3143 3144 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func)); 3145 if (!QLC_83xx_FUNC_VAL(state, pci_func)) { 3146 dev_info(&adapter->pdev->dev, "link state down\n"); 3147 return config; 3148 } 3149 3150 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS); 3151 if (err) 3152 return err; 3153 3154 err = qlcnic_issue_cmd(adapter, &cmd); 3155 if (err) { 3156 dev_info(&adapter->pdev->dev, 3157 "Get Link Status Command failed: 0x%x\n", err); 3158 goto out; 3159 } else { 3160 config = cmd.rsp.arg[1]; 3161 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) { 3162 case QLC_83XX_10M_LINK: 3163 ahw->link_speed = SPEED_10; 3164 break; 3165 case QLC_83XX_100M_LINK: 3166 ahw->link_speed = SPEED_100; 3167 break; 3168 case QLC_83XX_1G_LINK: 3169 ahw->link_speed = SPEED_1000; 3170 break; 3171 case QLC_83XX_10G_LINK: 3172 ahw->link_speed = SPEED_10000; 3173 break; 3174 default: 3175 ahw->link_speed = 0; 3176 break; 3177 } 3178 config = cmd.rsp.arg[3]; 3179 if (QLC_83XX_SFP_PRESENT(config)) { 3180 switch (ahw->module_type) { 3181 case LINKEVENT_MODULE_OPTICAL_UNKNOWN: 3182 case LINKEVENT_MODULE_OPTICAL_SRLR: 3183 case LINKEVENT_MODULE_OPTICAL_LRM: 3184 case LINKEVENT_MODULE_OPTICAL_SFP_1G: 3185 ahw->supported_type = PORT_FIBRE; 3186 break; 3187 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE: 3188 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN: 3189 case LINKEVENT_MODULE_TWINAX: 3190 ahw->supported_type = PORT_TP; 3191 break; 3192 default: 3193 ahw->supported_type = PORT_OTHER; 3194 } 3195 } 3196 if (config & 1) 3197 err = 1; 3198 } 3199 out: 3200 qlcnic_free_mbx_args(&cmd); 3201 return config; 3202 } 3203 3204 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter, 3205 struct ethtool_cmd *ecmd) 3206 { 3207 u32 config = 0; 3208 int status = 0; 3209 struct qlcnic_hardware_context *ahw = adapter->ahw; 3210 3211 if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) { 3212 /* Get port configuration info */ 3213 status = qlcnic_83xx_get_port_info(adapter); 3214 /* Get Link Status related info */ 3215 config = qlcnic_83xx_test_link(adapter); 3216 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config); 3217 } 3218 3219 /* hard code until there is a way to get it from flash */ 3220 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G; 3221 3222 if (netif_running(adapter->netdev) && ahw->has_link_events) { 3223 ethtool_cmd_speed_set(ecmd, ahw->link_speed); 3224 ecmd->duplex = ahw->link_duplex; 3225 ecmd->autoneg = ahw->link_autoneg; 3226 } else { 3227 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); 3228 ecmd->duplex = DUPLEX_UNKNOWN; 3229 ecmd->autoneg = AUTONEG_DISABLE; 3230 } 3231 3232 if (ahw->port_type == QLCNIC_XGBE) { 3233 ecmd->supported = SUPPORTED_10000baseT_Full; 3234 ecmd->advertising = ADVERTISED_10000baseT_Full; 3235 } else { 3236 ecmd->supported = (SUPPORTED_10baseT_Half | 3237 SUPPORTED_10baseT_Full | 3238 SUPPORTED_100baseT_Half | 3239 SUPPORTED_100baseT_Full | 3240 SUPPORTED_1000baseT_Half | 3241 SUPPORTED_1000baseT_Full); 3242 ecmd->advertising = (ADVERTISED_100baseT_Half | 3243 ADVERTISED_100baseT_Full | 3244 ADVERTISED_1000baseT_Half | 3245 ADVERTISED_1000baseT_Full); 3246 } 3247 3248 switch (ahw->supported_type) { 3249 case PORT_FIBRE: 3250 ecmd->supported |= SUPPORTED_FIBRE; 3251 ecmd->advertising |= ADVERTISED_FIBRE; 3252 ecmd->port = PORT_FIBRE; 3253 ecmd->transceiver = XCVR_EXTERNAL; 3254 break; 3255 case PORT_TP: 3256 ecmd->supported |= SUPPORTED_TP; 3257 ecmd->advertising |= ADVERTISED_TP; 3258 ecmd->port = PORT_TP; 3259 ecmd->transceiver = XCVR_INTERNAL; 3260 break; 3261 default: 3262 ecmd->supported |= SUPPORTED_FIBRE; 3263 ecmd->advertising |= ADVERTISED_FIBRE; 3264 ecmd->port = PORT_OTHER; 3265 ecmd->transceiver = XCVR_EXTERNAL; 3266 break; 3267 } 3268 ecmd->phy_address = ahw->physical_port; 3269 return status; 3270 } 3271 3272 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter, 3273 struct ethtool_cmd *ecmd) 3274 { 3275 int status = 0; 3276 u32 config = adapter->ahw->port_config; 3277 3278 if (ecmd->autoneg) 3279 adapter->ahw->port_config |= BIT_15; 3280 3281 switch (ethtool_cmd_speed(ecmd)) { 3282 case SPEED_10: 3283 adapter->ahw->port_config |= BIT_8; 3284 break; 3285 case SPEED_100: 3286 adapter->ahw->port_config |= BIT_9; 3287 break; 3288 case SPEED_1000: 3289 adapter->ahw->port_config |= BIT_10; 3290 break; 3291 case SPEED_10000: 3292 adapter->ahw->port_config |= BIT_11; 3293 break; 3294 default: 3295 return -EINVAL; 3296 } 3297 3298 status = qlcnic_83xx_set_port_config(adapter); 3299 if (status) { 3300 dev_info(&adapter->pdev->dev, 3301 "Failed to Set Link Speed and autoneg.\n"); 3302 adapter->ahw->port_config = config; 3303 } 3304 return status; 3305 } 3306 3307 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd, 3308 u64 *data, int index) 3309 { 3310 u32 low, hi; 3311 u64 val; 3312 3313 low = cmd->rsp.arg[index]; 3314 hi = cmd->rsp.arg[index + 1]; 3315 val = (((u64) low) | (((u64) hi) << 32)); 3316 *data++ = val; 3317 return data; 3318 } 3319 3320 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter, 3321 struct qlcnic_cmd_args *cmd, u64 *data, 3322 int type, int *ret) 3323 { 3324 int err, k, total_regs; 3325 3326 *ret = 0; 3327 err = qlcnic_issue_cmd(adapter, cmd); 3328 if (err != QLCNIC_RCODE_SUCCESS) { 3329 dev_info(&adapter->pdev->dev, 3330 "Error in get statistics mailbox command\n"); 3331 *ret = -EIO; 3332 return data; 3333 } 3334 total_regs = cmd->rsp.num; 3335 switch (type) { 3336 case QLC_83XX_STAT_MAC: 3337 /* fill in MAC tx counters */ 3338 for (k = 2; k < 28; k += 2) 3339 data = qlcnic_83xx_copy_stats(cmd, data, k); 3340 /* skip 24 bytes of reserved area */ 3341 /* fill in MAC rx counters */ 3342 for (k += 6; k < 60; k += 2) 3343 data = qlcnic_83xx_copy_stats(cmd, data, k); 3344 /* skip 24 bytes of reserved area */ 3345 /* fill in MAC rx frame stats */ 3346 for (k += 6; k < 80; k += 2) 3347 data = qlcnic_83xx_copy_stats(cmd, data, k); 3348 /* fill in eSwitch stats */ 3349 for (; k < total_regs; k += 2) 3350 data = qlcnic_83xx_copy_stats(cmd, data, k); 3351 break; 3352 case QLC_83XX_STAT_RX: 3353 for (k = 2; k < 8; k += 2) 3354 data = qlcnic_83xx_copy_stats(cmd, data, k); 3355 /* skip 8 bytes of reserved data */ 3356 for (k += 2; k < 24; k += 2) 3357 data = qlcnic_83xx_copy_stats(cmd, data, k); 3358 /* skip 8 bytes containing RE1FBQ error data */ 3359 for (k += 2; k < total_regs; k += 2) 3360 data = qlcnic_83xx_copy_stats(cmd, data, k); 3361 break; 3362 case QLC_83XX_STAT_TX: 3363 for (k = 2; k < 10; k += 2) 3364 data = qlcnic_83xx_copy_stats(cmd, data, k); 3365 /* skip 8 bytes of reserved data */ 3366 for (k += 2; k < total_regs; k += 2) 3367 data = qlcnic_83xx_copy_stats(cmd, data, k); 3368 break; 3369 default: 3370 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n"); 3371 *ret = -EIO; 3372 } 3373 return data; 3374 } 3375 3376 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data) 3377 { 3378 struct qlcnic_cmd_args cmd; 3379 struct net_device *netdev = adapter->netdev; 3380 int ret = 0; 3381 3382 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS); 3383 if (ret) 3384 return; 3385 /* Get Tx stats */ 3386 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16); 3387 cmd.rsp.num = QLC_83XX_TX_STAT_REGS; 3388 data = qlcnic_83xx_fill_stats(adapter, &cmd, data, 3389 QLC_83XX_STAT_TX, &ret); 3390 if (ret) { 3391 netdev_err(netdev, "Error getting Tx stats\n"); 3392 goto out; 3393 } 3394 /* Get MAC stats */ 3395 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16); 3396 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS; 3397 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num); 3398 data = qlcnic_83xx_fill_stats(adapter, &cmd, data, 3399 QLC_83XX_STAT_MAC, &ret); 3400 if (ret) { 3401 netdev_err(netdev, "Error getting MAC stats\n"); 3402 goto out; 3403 } 3404 /* Get Rx stats */ 3405 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16; 3406 cmd.rsp.num = QLC_83XX_RX_STAT_REGS; 3407 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num); 3408 data = qlcnic_83xx_fill_stats(adapter, &cmd, data, 3409 QLC_83XX_STAT_RX, &ret); 3410 if (ret) 3411 netdev_err(netdev, "Error getting Rx stats\n"); 3412 out: 3413 qlcnic_free_mbx_args(&cmd); 3414 } 3415 3416 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter) 3417 { 3418 u32 major, minor, sub; 3419 3420 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR); 3421 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR); 3422 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB); 3423 3424 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) { 3425 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n", 3426 __func__); 3427 return 1; 3428 } 3429 return 0; 3430 } 3431 3432 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter) 3433 { 3434 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) * 3435 sizeof(*adapter->ahw->ext_reg_tbl)) + 3436 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) * 3437 sizeof(*adapter->ahw->reg_tbl)); 3438 } 3439 3440 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff) 3441 { 3442 int i, j = 0; 3443 3444 for (i = QLCNIC_DEV_INFO_SIZE + 1; 3445 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++) 3446 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j); 3447 3448 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++) 3449 regs_buff[i++] = QLCRDX(adapter->ahw, j); 3450 return i; 3451 } 3452 3453 int qlcnic_83xx_interrupt_test(struct net_device *netdev) 3454 { 3455 struct qlcnic_adapter *adapter = netdev_priv(netdev); 3456 struct qlcnic_hardware_context *ahw = adapter->ahw; 3457 struct qlcnic_cmd_args cmd; 3458 u8 val, drv_sds_rings = adapter->drv_sds_rings; 3459 u8 drv_tx_rings = adapter->drv_tx_rings; 3460 u32 data; 3461 u16 intrpt_id, id; 3462 int ret; 3463 3464 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 3465 netdev_info(netdev, "Device is resetting\n"); 3466 return -EBUSY; 3467 } 3468 3469 if (qlcnic_get_diag_lock(adapter)) { 3470 netdev_info(netdev, "Device in diagnostics mode\n"); 3471 return -EBUSY; 3472 } 3473 3474 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST, 3475 drv_sds_rings); 3476 if (ret) 3477 goto fail_diag_irq; 3478 3479 ahw->diag_cnt = 0; 3480 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST); 3481 if (ret) 3482 goto fail_diag_irq; 3483 3484 if (adapter->flags & QLCNIC_MSIX_ENABLED) 3485 intrpt_id = ahw->intr_tbl[0].id; 3486 else 3487 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 3488 3489 cmd.req.arg[1] = 1; 3490 cmd.req.arg[2] = intrpt_id; 3491 cmd.req.arg[3] = BIT_0; 3492 3493 ret = qlcnic_issue_cmd(adapter, &cmd); 3494 data = cmd.rsp.arg[2]; 3495 id = LSW(data); 3496 val = LSB(MSW(data)); 3497 if (id != intrpt_id) 3498 dev_info(&adapter->pdev->dev, 3499 "Interrupt generated: 0x%x, requested:0x%x\n", 3500 id, intrpt_id); 3501 if (val) 3502 dev_err(&adapter->pdev->dev, 3503 "Interrupt test error: 0x%x\n", val); 3504 if (ret) 3505 goto done; 3506 3507 msleep(20); 3508 ret = !ahw->diag_cnt; 3509 3510 done: 3511 qlcnic_free_mbx_args(&cmd); 3512 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings); 3513 3514 fail_diag_irq: 3515 adapter->drv_sds_rings = drv_sds_rings; 3516 adapter->drv_tx_rings = drv_tx_rings; 3517 qlcnic_release_diag_lock(adapter); 3518 return ret; 3519 } 3520 3521 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter, 3522 struct ethtool_pauseparam *pause) 3523 { 3524 struct qlcnic_hardware_context *ahw = adapter->ahw; 3525 int status = 0; 3526 u32 config; 3527 3528 status = qlcnic_83xx_get_port_config(adapter); 3529 if (status) { 3530 dev_err(&adapter->pdev->dev, 3531 "%s: Get Pause Config failed\n", __func__); 3532 return; 3533 } 3534 config = ahw->port_config; 3535 if (config & QLC_83XX_CFG_STD_PAUSE) { 3536 switch (MSW(config)) { 3537 case QLC_83XX_TX_PAUSE: 3538 pause->tx_pause = 1; 3539 break; 3540 case QLC_83XX_RX_PAUSE: 3541 pause->rx_pause = 1; 3542 break; 3543 case QLC_83XX_TX_RX_PAUSE: 3544 default: 3545 /* Backward compatibility for existing 3546 * flash definitions 3547 */ 3548 pause->tx_pause = 1; 3549 pause->rx_pause = 1; 3550 } 3551 } 3552 3553 if (QLC_83XX_AUTONEG(config)) 3554 pause->autoneg = 1; 3555 } 3556 3557 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter, 3558 struct ethtool_pauseparam *pause) 3559 { 3560 struct qlcnic_hardware_context *ahw = adapter->ahw; 3561 int status = 0; 3562 u32 config; 3563 3564 status = qlcnic_83xx_get_port_config(adapter); 3565 if (status) { 3566 dev_err(&adapter->pdev->dev, 3567 "%s: Get Pause Config failed.\n", __func__); 3568 return status; 3569 } 3570 config = ahw->port_config; 3571 3572 if (ahw->port_type == QLCNIC_GBE) { 3573 if (pause->autoneg) 3574 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG; 3575 if (!pause->autoneg) 3576 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG; 3577 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) { 3578 return -EOPNOTSUPP; 3579 } 3580 3581 if (!(config & QLC_83XX_CFG_STD_PAUSE)) 3582 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE; 3583 3584 if (pause->rx_pause && pause->tx_pause) { 3585 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE; 3586 } else if (pause->rx_pause && !pause->tx_pause) { 3587 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE; 3588 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE; 3589 } else if (pause->tx_pause && !pause->rx_pause) { 3590 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE; 3591 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE; 3592 } else if (!pause->rx_pause && !pause->tx_pause) { 3593 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE | 3594 QLC_83XX_CFG_STD_PAUSE); 3595 } 3596 status = qlcnic_83xx_set_port_config(adapter); 3597 if (status) { 3598 dev_err(&adapter->pdev->dev, 3599 "%s: Set Pause Config failed.\n", __func__); 3600 ahw->port_config = config; 3601 } 3602 return status; 3603 } 3604 3605 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter) 3606 { 3607 int ret, err = 0; 3608 u32 temp; 3609 3610 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 3611 QLC_83XX_FLASH_OEM_READ_SIG); 3612 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 3613 QLC_83XX_FLASH_READ_CTRL); 3614 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 3615 if (ret) 3616 return -EIO; 3617 3618 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err); 3619 if (err == -EIO) 3620 return err; 3621 3622 return temp & 0xFF; 3623 } 3624 3625 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter) 3626 { 3627 int status; 3628 3629 status = qlcnic_83xx_read_flash_status_reg(adapter); 3630 if (status == -EIO) { 3631 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n", 3632 __func__); 3633 return 1; 3634 } 3635 return 0; 3636 } 3637 3638 static int qlcnic_83xx_shutdown(struct pci_dev *pdev) 3639 { 3640 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 3641 struct net_device *netdev = adapter->netdev; 3642 int retval; 3643 3644 netif_device_detach(netdev); 3645 qlcnic_cancel_idc_work(adapter); 3646 3647 if (netif_running(netdev)) 3648 qlcnic_down(adapter, netdev); 3649 3650 qlcnic_83xx_disable_mbx_intr(adapter); 3651 cancel_delayed_work_sync(&adapter->idc_aen_work); 3652 3653 retval = pci_save_state(pdev); 3654 if (retval) 3655 return retval; 3656 3657 return 0; 3658 } 3659 3660 static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter) 3661 { 3662 struct qlcnic_hardware_context *ahw = adapter->ahw; 3663 struct qlc_83xx_idc *idc = &ahw->idc; 3664 int err = 0; 3665 3666 err = qlcnic_83xx_idc_init(adapter); 3667 if (err) 3668 return err; 3669 3670 if (ahw->nic_mode == QLCNIC_VNIC_MODE) { 3671 if (ahw->op_mode == QLCNIC_MGMT_FUNC) { 3672 qlcnic_83xx_set_vnic_opmode(adapter); 3673 } else { 3674 err = qlcnic_83xx_check_vnic_state(adapter); 3675 if (err) 3676 return err; 3677 } 3678 } 3679 3680 err = qlcnic_83xx_idc_reattach_driver(adapter); 3681 if (err) 3682 return err; 3683 3684 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 3685 idc->delay); 3686 return err; 3687 } 3688 3689 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx) 3690 { 3691 reinit_completion(&mbx->completion); 3692 set_bit(QLC_83XX_MBX_READY, &mbx->status); 3693 } 3694 3695 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx) 3696 { 3697 if (!mbx) 3698 return; 3699 3700 destroy_workqueue(mbx->work_q); 3701 kfree(mbx); 3702 } 3703 3704 static inline void 3705 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter, 3706 struct qlcnic_cmd_args *cmd) 3707 { 3708 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED); 3709 3710 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) { 3711 qlcnic_free_mbx_args(cmd); 3712 kfree(cmd); 3713 return; 3714 } 3715 complete(&cmd->completion); 3716 } 3717 3718 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter) 3719 { 3720 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3721 struct list_head *head = &mbx->cmd_q; 3722 struct qlcnic_cmd_args *cmd = NULL; 3723 3724 spin_lock(&mbx->queue_lock); 3725 3726 while (!list_empty(head)) { 3727 cmd = list_entry(head->next, struct qlcnic_cmd_args, list); 3728 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n", 3729 __func__, cmd->cmd_op); 3730 list_del(&cmd->list); 3731 mbx->num_cmds--; 3732 qlcnic_83xx_notify_cmd_completion(adapter, cmd); 3733 } 3734 3735 spin_unlock(&mbx->queue_lock); 3736 } 3737 3738 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter) 3739 { 3740 struct qlcnic_hardware_context *ahw = adapter->ahw; 3741 struct qlcnic_mailbox *mbx = ahw->mailbox; 3742 u32 host_mbx_ctrl; 3743 3744 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) 3745 return -EBUSY; 3746 3747 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL); 3748 if (host_mbx_ctrl) { 3749 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 3750 ahw->idc.collect_dump = 1; 3751 return -EIO; 3752 } 3753 3754 return 0; 3755 } 3756 3757 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter, 3758 u8 issue_cmd) 3759 { 3760 if (issue_cmd) 3761 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER); 3762 else 3763 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER); 3764 } 3765 3766 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter, 3767 struct qlcnic_cmd_args *cmd) 3768 { 3769 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3770 3771 spin_lock(&mbx->queue_lock); 3772 3773 list_del(&cmd->list); 3774 mbx->num_cmds--; 3775 3776 spin_unlock(&mbx->queue_lock); 3777 3778 qlcnic_83xx_notify_cmd_completion(adapter, cmd); 3779 } 3780 3781 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter, 3782 struct qlcnic_cmd_args *cmd) 3783 { 3784 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp; 3785 struct qlcnic_hardware_context *ahw = adapter->ahw; 3786 int i, j; 3787 3788 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) { 3789 mbx_cmd = cmd->req.arg[0]; 3790 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0)); 3791 for (i = 1; i < cmd->req.num; i++) 3792 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i)); 3793 } else { 3794 fw_hal_version = ahw->fw_hal_version; 3795 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32); 3796 total_size = cmd->pay_size + hdr_size; 3797 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16; 3798 mbx_cmd = tmp | fw_hal_version << 29; 3799 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0)); 3800 3801 /* Back channel specific operations bits */ 3802 mbx_cmd = 0x1 | 1 << 4; 3803 3804 if (qlcnic_sriov_pf_check(adapter)) 3805 mbx_cmd |= cmd->func_num << 5; 3806 3807 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1)); 3808 3809 for (i = 2, j = 0; j < hdr_size; i++, j++) 3810 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i)); 3811 for (j = 0; j < cmd->pay_size; j++, i++) 3812 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i)); 3813 } 3814 } 3815 3816 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter) 3817 { 3818 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3819 3820 if (!mbx) 3821 return; 3822 3823 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 3824 complete(&mbx->completion); 3825 cancel_work_sync(&mbx->work); 3826 flush_workqueue(mbx->work_q); 3827 qlcnic_83xx_flush_mbx_queue(adapter); 3828 } 3829 3830 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter, 3831 struct qlcnic_cmd_args *cmd, 3832 unsigned long *timeout) 3833 { 3834 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3835 3836 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) { 3837 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT); 3838 init_completion(&cmd->completion); 3839 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN; 3840 3841 spin_lock(&mbx->queue_lock); 3842 3843 list_add_tail(&cmd->list, &mbx->cmd_q); 3844 mbx->num_cmds++; 3845 cmd->total_cmds = mbx->num_cmds; 3846 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT; 3847 queue_work(mbx->work_q, &mbx->work); 3848 3849 spin_unlock(&mbx->queue_lock); 3850 3851 return 0; 3852 } 3853 3854 return -EBUSY; 3855 } 3856 3857 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter, 3858 struct qlcnic_cmd_args *cmd) 3859 { 3860 u8 mac_cmd_rcode; 3861 u32 fw_data; 3862 3863 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) { 3864 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2)); 3865 mac_cmd_rcode = (u8)fw_data; 3866 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE || 3867 mac_cmd_rcode == QLC_83XX_MAC_PRESENT || 3868 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) { 3869 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS; 3870 return QLCNIC_RCODE_SUCCESS; 3871 } 3872 } 3873 3874 return -EINVAL; 3875 } 3876 3877 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter, 3878 struct qlcnic_cmd_args *cmd) 3879 { 3880 struct qlcnic_hardware_context *ahw = adapter->ahw; 3881 struct device *dev = &adapter->pdev->dev; 3882 u8 mbx_err_code; 3883 u32 fw_data; 3884 3885 fw_data = readl(QLCNIC_MBX_FW(ahw, 0)); 3886 mbx_err_code = QLCNIC_MBX_STATUS(fw_data); 3887 qlcnic_83xx_get_mbx_data(adapter, cmd); 3888 3889 switch (mbx_err_code) { 3890 case QLCNIC_MBX_RSP_OK: 3891 case QLCNIC_MBX_PORT_RSP_OK: 3892 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS; 3893 break; 3894 default: 3895 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd)) 3896 break; 3897 3898 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n", 3899 __func__, cmd->cmd_op, cmd->type, ahw->pci_func, 3900 ahw->op_mode, mbx_err_code); 3901 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED; 3902 qlcnic_dump_mbx(adapter, cmd); 3903 } 3904 3905 return; 3906 } 3907 3908 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter) 3909 { 3910 struct qlcnic_hardware_context *ahw = adapter->ahw; 3911 u32 offset; 3912 3913 offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK); 3914 dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x", 3915 readl(ahw->pci_base0 + offset), 3916 QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL), 3917 QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL), 3918 QLCRDX(ahw, QLCNIC_FW_MBX_CTRL)); 3919 } 3920 3921 static void qlcnic_83xx_mailbox_worker(struct work_struct *work) 3922 { 3923 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox, 3924 work); 3925 struct qlcnic_adapter *adapter = mbx->adapter; 3926 struct qlcnic_mbx_ops *mbx_ops = mbx->ops; 3927 struct device *dev = &adapter->pdev->dev; 3928 atomic_t *rsp_status = &mbx->rsp_status; 3929 struct list_head *head = &mbx->cmd_q; 3930 struct qlcnic_hardware_context *ahw; 3931 struct qlcnic_cmd_args *cmd = NULL; 3932 3933 ahw = adapter->ahw; 3934 3935 while (true) { 3936 if (qlcnic_83xx_check_mbx_status(adapter)) { 3937 qlcnic_83xx_flush_mbx_queue(adapter); 3938 return; 3939 } 3940 3941 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT); 3942 3943 spin_lock(&mbx->queue_lock); 3944 3945 if (list_empty(head)) { 3946 spin_unlock(&mbx->queue_lock); 3947 return; 3948 } 3949 cmd = list_entry(head->next, struct qlcnic_cmd_args, list); 3950 3951 spin_unlock(&mbx->queue_lock); 3952 3953 mbx_ops->encode_cmd(adapter, cmd); 3954 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST); 3955 3956 if (wait_for_completion_timeout(&mbx->completion, 3957 QLC_83XX_MBX_TIMEOUT)) { 3958 mbx_ops->decode_resp(adapter, cmd); 3959 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION); 3960 } else { 3961 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n", 3962 __func__, cmd->cmd_op, cmd->type, ahw->pci_func, 3963 ahw->op_mode); 3964 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 3965 qlcnic_dump_mailbox_registers(adapter); 3966 qlcnic_83xx_get_mbx_data(adapter, cmd); 3967 qlcnic_dump_mbx(adapter, cmd); 3968 qlcnic_83xx_idc_request_reset(adapter, 3969 QLCNIC_FORCE_FW_DUMP_KEY); 3970 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT; 3971 } 3972 mbx_ops->dequeue_cmd(adapter, cmd); 3973 } 3974 } 3975 3976 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = { 3977 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd, 3978 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd, 3979 .decode_resp = qlcnic_83xx_decode_mbx_rsp, 3980 .encode_cmd = qlcnic_83xx_encode_mbx_cmd, 3981 .nofity_fw = qlcnic_83xx_signal_mbx_cmd, 3982 }; 3983 3984 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter) 3985 { 3986 struct qlcnic_hardware_context *ahw = adapter->ahw; 3987 struct qlcnic_mailbox *mbx; 3988 3989 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL); 3990 if (!ahw->mailbox) 3991 return -ENOMEM; 3992 3993 mbx = ahw->mailbox; 3994 mbx->ops = &qlcnic_83xx_mbx_ops; 3995 mbx->adapter = adapter; 3996 3997 spin_lock_init(&mbx->queue_lock); 3998 spin_lock_init(&mbx->aen_lock); 3999 INIT_LIST_HEAD(&mbx->cmd_q); 4000 init_completion(&mbx->completion); 4001 4002 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox"); 4003 if (mbx->work_q == NULL) { 4004 kfree(mbx); 4005 return -ENOMEM; 4006 } 4007 4008 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker); 4009 set_bit(QLC_83XX_MBX_READY, &mbx->status); 4010 return 0; 4011 } 4012 4013 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev, 4014 pci_channel_state_t state) 4015 { 4016 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 4017 4018 if (state == pci_channel_io_perm_failure) 4019 return PCI_ERS_RESULT_DISCONNECT; 4020 4021 if (state == pci_channel_io_normal) 4022 return PCI_ERS_RESULT_RECOVERED; 4023 4024 set_bit(__QLCNIC_AER, &adapter->state); 4025 set_bit(__QLCNIC_RESETTING, &adapter->state); 4026 4027 qlcnic_83xx_aer_stop_poll_work(adapter); 4028 4029 pci_save_state(pdev); 4030 pci_disable_device(pdev); 4031 4032 return PCI_ERS_RESULT_NEED_RESET; 4033 } 4034 4035 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev) 4036 { 4037 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 4038 int err = 0; 4039 4040 pdev->error_state = pci_channel_io_normal; 4041 err = pci_enable_device(pdev); 4042 if (err) 4043 goto disconnect; 4044 4045 pci_set_power_state(pdev, PCI_D0); 4046 pci_set_master(pdev); 4047 pci_restore_state(pdev); 4048 4049 err = qlcnic_83xx_aer_reset(adapter); 4050 if (err == 0) 4051 return PCI_ERS_RESULT_RECOVERED; 4052 disconnect: 4053 clear_bit(__QLCNIC_AER, &adapter->state); 4054 clear_bit(__QLCNIC_RESETTING, &adapter->state); 4055 return PCI_ERS_RESULT_DISCONNECT; 4056 } 4057 4058 static void qlcnic_83xx_io_resume(struct pci_dev *pdev) 4059 { 4060 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 4061 4062 pci_cleanup_aer_uncorrect_error_status(pdev); 4063 if (test_and_clear_bit(__QLCNIC_AER, &adapter->state)) 4064 qlcnic_83xx_aer_start_poll_work(adapter); 4065 } 4066