1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #include "qlcnic.h" 9 #include "qlcnic_sriov.h" 10 #include <linux/if_vlan.h> 11 #include <linux/ipv6.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/aer.h> 15 16 #define RSS_HASHTYPE_IP_TCP 0x3 17 #define QLC_83XX_FW_MBX_CMD 0 18 19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = { 20 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1}, 21 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34}, 22 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27}, 23 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1}, 24 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18}, 25 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1}, 26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1}, 27 {QLCNIC_CMD_INTRPT_TEST, 22, 12}, 28 {QLCNIC_CMD_SET_MTU, 3, 1}, 29 {QLCNIC_CMD_READ_PHY, 4, 2}, 30 {QLCNIC_CMD_WRITE_PHY, 5, 1}, 31 {QLCNIC_CMD_READ_HW_REG, 4, 1}, 32 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2}, 33 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1}, 34 {QLCNIC_CMD_READ_MAX_MTU, 4, 2}, 35 {QLCNIC_CMD_READ_MAX_LRO, 4, 2}, 36 {QLCNIC_CMD_MAC_ADDRESS, 4, 3}, 37 {QLCNIC_CMD_GET_PCI_INFO, 1, 66}, 38 {QLCNIC_CMD_GET_NIC_INFO, 2, 19}, 39 {QLCNIC_CMD_SET_NIC_INFO, 32, 1}, 40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3}, 41 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1}, 42 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3}, 43 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1}, 44 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1}, 45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3}, 46 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1}, 47 {QLCNIC_CMD_CONFIG_PORT, 4, 1}, 48 {QLCNIC_CMD_TEMP_SIZE, 1, 4}, 49 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5}, 50 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1}, 51 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3}, 52 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1}, 53 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1}, 54 {QLCNIC_CMD_CONFIGURE_LED, 2, 1}, 55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1}, 56 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1}, 57 {QLCNIC_CMD_GET_STATISTICS, 2, 80}, 58 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1}, 59 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2}, 60 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4}, 61 {QLCNIC_CMD_IDC_ACK, 5, 1}, 62 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1}, 63 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1}, 64 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1}, 65 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5}, 66 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1}, 67 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26}, 68 {QLCNIC_CMD_CONFIG_VPORT, 4, 4}, 69 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1}, 70 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2}, 71 {QLCNIC_CMD_DCB_QUERY_PARAM, 2, 50}, 72 }; 73 74 const u32 qlcnic_83xx_ext_reg_tbl[] = { 75 0x38CC, /* Global Reset */ 76 0x38F0, /* Wildcard */ 77 0x38FC, /* Informant */ 78 0x3038, /* Host MBX ctrl */ 79 0x303C, /* FW MBX ctrl */ 80 0x355C, /* BOOT LOADER ADDRESS REG */ 81 0x3560, /* BOOT LOADER SIZE REG */ 82 0x3564, /* FW IMAGE ADDR REG */ 83 0x1000, /* MBX intr enable */ 84 0x1200, /* Default Intr mask */ 85 0x1204, /* Default Interrupt ID */ 86 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */ 87 0x3784, /* QLC_83XX_IDC_DEV_STATE */ 88 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */ 89 0x378C, /* QLC_83XX_IDC_DRV_ACK */ 90 0x3790, /* QLC_83XX_IDC_CTRL */ 91 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */ 92 0x3798, /* QLC_83XX_IDC_MIN_VERSION */ 93 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */ 94 0x37A0, /* QLC_83XX_IDC_PF_0 */ 95 0x37A4, /* QLC_83XX_IDC_PF_1 */ 96 0x37A8, /* QLC_83XX_IDC_PF_2 */ 97 0x37AC, /* QLC_83XX_IDC_PF_3 */ 98 0x37B0, /* QLC_83XX_IDC_PF_4 */ 99 0x37B4, /* QLC_83XX_IDC_PF_5 */ 100 0x37B8, /* QLC_83XX_IDC_PF_6 */ 101 0x37BC, /* QLC_83XX_IDC_PF_7 */ 102 0x37C0, /* QLC_83XX_IDC_PF_8 */ 103 0x37C4, /* QLC_83XX_IDC_PF_9 */ 104 0x37C8, /* QLC_83XX_IDC_PF_10 */ 105 0x37CC, /* QLC_83XX_IDC_PF_11 */ 106 0x37D0, /* QLC_83XX_IDC_PF_12 */ 107 0x37D4, /* QLC_83XX_IDC_PF_13 */ 108 0x37D8, /* QLC_83XX_IDC_PF_14 */ 109 0x37DC, /* QLC_83XX_IDC_PF_15 */ 110 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */ 111 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */ 112 0x37F0, /* QLC_83XX_DRV_OP_MODE */ 113 0x37F4, /* QLC_83XX_VNIC_STATE */ 114 0x3868, /* QLC_83XX_DRV_LOCK */ 115 0x386C, /* QLC_83XX_DRV_UNLOCK */ 116 0x3504, /* QLC_83XX_DRV_LOCK_ID */ 117 0x34A4, /* QLC_83XX_ASIC_TEMP */ 118 }; 119 120 const u32 qlcnic_83xx_reg_tbl[] = { 121 0x34A8, /* PEG_HALT_STAT1 */ 122 0x34AC, /* PEG_HALT_STAT2 */ 123 0x34B0, /* FW_HEARTBEAT */ 124 0x3500, /* FLASH LOCK_ID */ 125 0x3528, /* FW_CAPABILITIES */ 126 0x3538, /* Driver active, DRV_REG0 */ 127 0x3540, /* Device state, DRV_REG1 */ 128 0x3544, /* Driver state, DRV_REG2 */ 129 0x3548, /* Driver scratch, DRV_REG3 */ 130 0x354C, /* Device partiton info, DRV_REG4 */ 131 0x3524, /* Driver IDC ver, DRV_REG5 */ 132 0x3550, /* FW_VER_MAJOR */ 133 0x3554, /* FW_VER_MINOR */ 134 0x3558, /* FW_VER_SUB */ 135 0x359C, /* NPAR STATE */ 136 0x35FC, /* FW_IMG_VALID */ 137 0x3650, /* CMD_PEG_STATE */ 138 0x373C, /* RCV_PEG_STATE */ 139 0x37B4, /* ASIC TEMP */ 140 0x356C, /* FW API */ 141 0x3570, /* DRV OP MODE */ 142 0x3850, /* FLASH LOCK */ 143 0x3854, /* FLASH UNLOCK */ 144 }; 145 146 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = { 147 .read_crb = qlcnic_83xx_read_crb, 148 .write_crb = qlcnic_83xx_write_crb, 149 .read_reg = qlcnic_83xx_rd_reg_indirect, 150 .write_reg = qlcnic_83xx_wrt_reg_indirect, 151 .get_mac_address = qlcnic_83xx_get_mac_address, 152 .setup_intr = qlcnic_83xx_setup_intr, 153 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args, 154 .mbx_cmd = qlcnic_83xx_issue_cmd, 155 .get_func_no = qlcnic_83xx_get_func_no, 156 .api_lock = qlcnic_83xx_cam_lock, 157 .api_unlock = qlcnic_83xx_cam_unlock, 158 .add_sysfs = qlcnic_83xx_add_sysfs, 159 .remove_sysfs = qlcnic_83xx_remove_sysfs, 160 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag, 161 .create_rx_ctx = qlcnic_83xx_create_rx_ctx, 162 .create_tx_ctx = qlcnic_83xx_create_tx_ctx, 163 .del_rx_ctx = qlcnic_83xx_del_rx_ctx, 164 .del_tx_ctx = qlcnic_83xx_del_tx_ctx, 165 .setup_link_event = qlcnic_83xx_setup_link_event, 166 .get_nic_info = qlcnic_83xx_get_nic_info, 167 .get_pci_info = qlcnic_83xx_get_pci_info, 168 .set_nic_info = qlcnic_83xx_set_nic_info, 169 .change_macvlan = qlcnic_83xx_sre_macaddr_change, 170 .napi_enable = qlcnic_83xx_napi_enable, 171 .napi_disable = qlcnic_83xx_napi_disable, 172 .config_intr_coal = qlcnic_83xx_config_intr_coal, 173 .config_rss = qlcnic_83xx_config_rss, 174 .config_hw_lro = qlcnic_83xx_config_hw_lro, 175 .config_promisc_mode = qlcnic_83xx_nic_set_promisc, 176 .change_l2_filter = qlcnic_83xx_change_l2_filter, 177 .get_board_info = qlcnic_83xx_get_port_info, 178 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count, 179 .free_mac_list = qlcnic_82xx_free_mac_list, 180 .io_error_detected = qlcnic_83xx_io_error_detected, 181 .io_slot_reset = qlcnic_83xx_io_slot_reset, 182 .io_resume = qlcnic_83xx_io_resume, 183 184 }; 185 186 static struct qlcnic_nic_template qlcnic_83xx_ops = { 187 .config_bridged_mode = qlcnic_config_bridged_mode, 188 .config_led = qlcnic_config_led, 189 .request_reset = qlcnic_83xx_idc_request_reset, 190 .cancel_idc_work = qlcnic_83xx_idc_exit, 191 .napi_add = qlcnic_83xx_napi_add, 192 .napi_del = qlcnic_83xx_napi_del, 193 .config_ipaddr = qlcnic_83xx_config_ipaddr, 194 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr, 195 .shutdown = qlcnic_83xx_shutdown, 196 .resume = qlcnic_83xx_resume, 197 }; 198 199 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw) 200 { 201 ahw->hw_ops = &qlcnic_83xx_hw_ops; 202 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; 203 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl; 204 } 205 206 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter) 207 { 208 u32 fw_major, fw_minor, fw_build; 209 struct pci_dev *pdev = adapter->pdev; 210 211 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR); 212 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR); 213 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB); 214 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build); 215 216 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n", 217 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build); 218 219 return adapter->fw_version; 220 } 221 222 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr) 223 { 224 void __iomem *base; 225 u32 val; 226 227 base = adapter->ahw->pci_base0 + 228 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func); 229 writel(addr, base); 230 val = readl(base); 231 if (val != addr) 232 return -EIO; 233 234 return 0; 235 } 236 237 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr, 238 int *err) 239 { 240 struct qlcnic_hardware_context *ahw = adapter->ahw; 241 242 *err = __qlcnic_set_win_base(adapter, (u32) addr); 243 if (!*err) { 244 return QLCRDX(ahw, QLCNIC_WILDCARD); 245 } else { 246 dev_err(&adapter->pdev->dev, 247 "%s failed, addr = 0x%lx\n", __func__, addr); 248 return -EIO; 249 } 250 } 251 252 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr, 253 u32 data) 254 { 255 int err; 256 struct qlcnic_hardware_context *ahw = adapter->ahw; 257 258 err = __qlcnic_set_win_base(adapter, (u32) addr); 259 if (!err) { 260 QLCWRX(ahw, QLCNIC_WILDCARD, data); 261 return 0; 262 } else { 263 dev_err(&adapter->pdev->dev, 264 "%s failed, addr = 0x%x data = 0x%x\n", 265 __func__, (int)addr, data); 266 return err; 267 } 268 } 269 270 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter) 271 { 272 int err, i, num_msix; 273 struct qlcnic_hardware_context *ahw = adapter->ahw; 274 275 num_msix = adapter->drv_sds_rings; 276 277 /* account for AEN interrupt MSI-X based interrupts */ 278 num_msix += 1; 279 280 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED)) 281 num_msix += adapter->drv_tx_rings; 282 283 err = qlcnic_enable_msix(adapter, num_msix); 284 if (err == -ENOMEM) 285 return err; 286 if (adapter->flags & QLCNIC_MSIX_ENABLED) 287 num_msix = adapter->ahw->num_msix; 288 else { 289 if (qlcnic_sriov_vf_check(adapter)) 290 return -EINVAL; 291 num_msix = 1; 292 } 293 /* setup interrupt mapping table for fw */ 294 ahw->intr_tbl = vzalloc(num_msix * 295 sizeof(struct qlcnic_intrpt_config)); 296 if (!ahw->intr_tbl) 297 return -ENOMEM; 298 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) { 299 /* MSI-X enablement failed, use legacy interrupt */ 300 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR; 301 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK; 302 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR; 303 adapter->msix_entries[0].vector = adapter->pdev->irq; 304 dev_info(&adapter->pdev->dev, "using legacy interrupt\n"); 305 } 306 307 for (i = 0; i < num_msix; i++) { 308 if (adapter->flags & QLCNIC_MSIX_ENABLED) 309 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX; 310 else 311 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX; 312 ahw->intr_tbl[i].id = i; 313 ahw->intr_tbl[i].src = 0; 314 } 315 return 0; 316 } 317 318 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter) 319 { 320 writel(0, adapter->tgt_mask_reg); 321 } 322 323 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter) 324 { 325 if (adapter->tgt_mask_reg) 326 writel(1, adapter->tgt_mask_reg); 327 } 328 329 /* Enable MSI-x and INT-x interrupts */ 330 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter, 331 struct qlcnic_host_sds_ring *sds_ring) 332 { 333 writel(0, sds_ring->crb_intr_mask); 334 } 335 336 /* Disable MSI-x and INT-x interrupts */ 337 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter, 338 struct qlcnic_host_sds_ring *sds_ring) 339 { 340 writel(1, sds_ring->crb_intr_mask); 341 } 342 343 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter 344 *adapter) 345 { 346 u32 mask; 347 348 /* Mailbox in MSI-x mode and Legacy Interrupt share the same 349 * source register. We could be here before contexts are created 350 * and sds_ring->crb_intr_mask has not been initialized, calculate 351 * BAR offset for Interrupt Source Register 352 */ 353 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); 354 writel(0, adapter->ahw->pci_base0 + mask); 355 } 356 357 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter) 358 { 359 u32 mask; 360 361 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); 362 writel(1, adapter->ahw->pci_base0 + mask); 363 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0); 364 } 365 366 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter, 367 struct qlcnic_cmd_args *cmd) 368 { 369 int i; 370 371 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP) 372 return; 373 374 for (i = 0; i < cmd->rsp.num; i++) 375 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i)); 376 } 377 378 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter) 379 { 380 u32 intr_val; 381 struct qlcnic_hardware_context *ahw = adapter->ahw; 382 int retries = 0; 383 384 intr_val = readl(adapter->tgt_status_reg); 385 386 if (!QLC_83XX_VALID_INTX_BIT31(intr_val)) 387 return IRQ_NONE; 388 389 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) { 390 adapter->stats.spurious_intr++; 391 return IRQ_NONE; 392 } 393 /* The barrier is required to ensure writes to the registers */ 394 wmb(); 395 396 /* clear the interrupt trigger control register */ 397 writel(0, adapter->isr_int_vec); 398 intr_val = readl(adapter->isr_int_vec); 399 do { 400 intr_val = readl(adapter->tgt_status_reg); 401 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func) 402 break; 403 retries++; 404 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) && 405 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY)); 406 407 return IRQ_HANDLED; 408 } 409 410 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx) 411 { 412 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED); 413 complete(&mbx->completion); 414 } 415 416 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter) 417 { 418 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED; 419 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 420 unsigned long flags; 421 422 spin_lock_irqsave(&mbx->aen_lock, flags); 423 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL); 424 if (!(resp & QLCNIC_SET_OWNER)) 425 goto out; 426 427 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0)); 428 if (event & QLCNIC_MBX_ASYNC_EVENT) { 429 __qlcnic_83xx_process_aen(adapter); 430 } else { 431 if (atomic_read(&mbx->rsp_status) != rsp_status) 432 qlcnic_83xx_notify_mbx_response(mbx); 433 } 434 out: 435 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 436 spin_unlock_irqrestore(&mbx->aen_lock, flags); 437 } 438 439 irqreturn_t qlcnic_83xx_intr(int irq, void *data) 440 { 441 struct qlcnic_adapter *adapter = data; 442 struct qlcnic_host_sds_ring *sds_ring; 443 struct qlcnic_hardware_context *ahw = adapter->ahw; 444 445 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE) 446 return IRQ_NONE; 447 448 qlcnic_83xx_poll_process_aen(adapter); 449 450 if (ahw->diag_test) { 451 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) 452 ahw->diag_cnt++; 453 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 454 return IRQ_HANDLED; 455 } 456 457 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) { 458 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 459 } else { 460 sds_ring = &adapter->recv_ctx->sds_rings[0]; 461 napi_schedule(&sds_ring->napi); 462 } 463 464 return IRQ_HANDLED; 465 } 466 467 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data) 468 { 469 struct qlcnic_host_sds_ring *sds_ring = data; 470 struct qlcnic_adapter *adapter = sds_ring->adapter; 471 472 if (adapter->flags & QLCNIC_MSIX_ENABLED) 473 goto done; 474 475 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE) 476 return IRQ_NONE; 477 478 done: 479 adapter->ahw->diag_cnt++; 480 qlcnic_83xx_enable_intr(adapter, sds_ring); 481 482 return IRQ_HANDLED; 483 } 484 485 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter) 486 { 487 u32 num_msix; 488 489 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) 490 qlcnic_83xx_set_legacy_intr_mask(adapter); 491 492 qlcnic_83xx_disable_mbx_intr(adapter); 493 494 if (adapter->flags & QLCNIC_MSIX_ENABLED) 495 num_msix = adapter->ahw->num_msix - 1; 496 else 497 num_msix = 0; 498 499 msleep(20); 500 501 if (adapter->msix_entries) { 502 synchronize_irq(adapter->msix_entries[num_msix].vector); 503 free_irq(adapter->msix_entries[num_msix].vector, adapter); 504 } 505 } 506 507 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter) 508 { 509 irq_handler_t handler; 510 u32 val; 511 int err = 0; 512 unsigned long flags = 0; 513 514 if (!(adapter->flags & QLCNIC_MSI_ENABLED) && 515 !(adapter->flags & QLCNIC_MSIX_ENABLED)) 516 flags |= IRQF_SHARED; 517 518 if (adapter->flags & QLCNIC_MSIX_ENABLED) { 519 handler = qlcnic_83xx_handle_aen; 520 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector; 521 err = request_irq(val, handler, flags, "qlcnic-MB", adapter); 522 if (err) { 523 dev_err(&adapter->pdev->dev, 524 "failed to register MBX interrupt\n"); 525 return err; 526 } 527 } else { 528 handler = qlcnic_83xx_intr; 529 val = adapter->msix_entries[0].vector; 530 err = request_irq(val, handler, flags, "qlcnic", adapter); 531 if (err) { 532 dev_err(&adapter->pdev->dev, 533 "failed to register INTx interrupt\n"); 534 return err; 535 } 536 qlcnic_83xx_clear_legacy_intr_mask(adapter); 537 } 538 539 /* Enable mailbox interrupt */ 540 qlcnic_83xx_enable_mbx_interrupt(adapter); 541 542 return err; 543 } 544 545 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter) 546 { 547 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT); 548 adapter->ahw->pci_func = (val >> 24) & 0xff; 549 } 550 551 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter) 552 { 553 void __iomem *addr; 554 u32 val, limit = 0; 555 556 struct qlcnic_hardware_context *ahw = adapter->ahw; 557 558 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func); 559 do { 560 val = readl(addr); 561 if (val) { 562 /* write the function number to register */ 563 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 564 ahw->pci_func); 565 return 0; 566 } 567 usleep_range(1000, 2000); 568 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT); 569 570 return -EIO; 571 } 572 573 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter) 574 { 575 void __iomem *addr; 576 u32 val; 577 struct qlcnic_hardware_context *ahw = adapter->ahw; 578 579 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func); 580 val = readl(addr); 581 } 582 583 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf, 584 loff_t offset, size_t size) 585 { 586 int ret = 0; 587 u32 data; 588 589 if (qlcnic_api_lock(adapter)) { 590 dev_err(&adapter->pdev->dev, 591 "%s: failed to acquire lock. addr offset 0x%x\n", 592 __func__, (u32)offset); 593 return; 594 } 595 596 data = QLCRD32(adapter, (u32) offset, &ret); 597 qlcnic_api_unlock(adapter); 598 599 if (ret == -EIO) { 600 dev_err(&adapter->pdev->dev, 601 "%s: failed. addr offset 0x%x\n", 602 __func__, (u32)offset); 603 return; 604 } 605 memcpy(buf, &data, size); 606 } 607 608 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf, 609 loff_t offset, size_t size) 610 { 611 u32 data; 612 613 memcpy(&data, buf, size); 614 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data); 615 } 616 617 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter) 618 { 619 int status; 620 621 status = qlcnic_83xx_get_port_config(adapter); 622 if (status) { 623 dev_err(&adapter->pdev->dev, 624 "Get Port Info failed\n"); 625 } else { 626 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config)) 627 adapter->ahw->port_type = QLCNIC_XGBE; 628 else 629 adapter->ahw->port_type = QLCNIC_GBE; 630 631 if (QLC_83XX_AUTONEG(adapter->ahw->port_config)) 632 adapter->ahw->link_autoneg = AUTONEG_ENABLE; 633 } 634 return status; 635 } 636 637 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter) 638 { 639 struct qlcnic_hardware_context *ahw = adapter->ahw; 640 u16 act_pci_fn = ahw->act_pci_func; 641 u16 count; 642 643 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT; 644 if (act_pci_fn <= 2) 645 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) / 646 act_pci_fn; 647 else 648 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) / 649 act_pci_fn; 650 ahw->max_uc_count = count; 651 } 652 653 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter) 654 { 655 u32 val; 656 657 if (adapter->flags & QLCNIC_MSIX_ENABLED) 658 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8); 659 else 660 val = BIT_2; 661 662 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val); 663 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 664 } 665 666 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter, 667 const struct pci_device_id *ent) 668 { 669 u32 op_mode, priv_level; 670 struct qlcnic_hardware_context *ahw = adapter->ahw; 671 672 ahw->fw_hal_version = 2; 673 qlcnic_get_func_no(adapter); 674 675 if (qlcnic_sriov_vf_check(adapter)) { 676 qlcnic_sriov_vf_set_ops(adapter); 677 return; 678 } 679 680 /* Determine function privilege level */ 681 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE); 682 if (op_mode == QLC_83XX_DEFAULT_OPMODE) 683 priv_level = QLCNIC_MGMT_FUNC; 684 else 685 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode, 686 ahw->pci_func); 687 688 if (priv_level == QLCNIC_NON_PRIV_FUNC) { 689 ahw->op_mode = QLCNIC_NON_PRIV_FUNC; 690 dev_info(&adapter->pdev->dev, 691 "HAL Version: %d Non Privileged function\n", 692 ahw->fw_hal_version); 693 adapter->nic_ops = &qlcnic_vf_ops; 694 } else { 695 if (pci_find_ext_capability(adapter->pdev, 696 PCI_EXT_CAP_ID_SRIOV)) 697 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state); 698 adapter->nic_ops = &qlcnic_83xx_ops; 699 } 700 } 701 702 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter, 703 u32 data[]); 704 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter, 705 u32 data[]); 706 707 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter, 708 struct qlcnic_cmd_args *cmd) 709 { 710 int i; 711 712 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP) 713 return; 714 715 dev_info(&adapter->pdev->dev, 716 "Host MBX regs(%d)\n", cmd->req.num); 717 for (i = 0; i < cmd->req.num; i++) { 718 if (i && !(i % 8)) 719 pr_info("\n"); 720 pr_info("%08x ", cmd->req.arg[i]); 721 } 722 pr_info("\n"); 723 dev_info(&adapter->pdev->dev, 724 "FW MBX regs(%d)\n", cmd->rsp.num); 725 for (i = 0; i < cmd->rsp.num; i++) { 726 if (i && !(i % 8)) 727 pr_info("\n"); 728 pr_info("%08x ", cmd->rsp.arg[i]); 729 } 730 pr_info("\n"); 731 } 732 733 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter, 734 struct qlcnic_cmd_args *cmd) 735 { 736 struct qlcnic_hardware_context *ahw = adapter->ahw; 737 int opcode = LSW(cmd->req.arg[0]); 738 unsigned long max_loops; 739 740 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP; 741 742 for (; max_loops; max_loops--) { 743 if (atomic_read(&cmd->rsp_status) == 744 QLC_83XX_MBX_RESPONSE_ARRIVED) 745 return; 746 747 udelay(1); 748 } 749 750 dev_err(&adapter->pdev->dev, 751 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", 752 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode); 753 flush_workqueue(ahw->mailbox->work_q); 754 return; 755 } 756 757 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter, 758 struct qlcnic_cmd_args *cmd) 759 { 760 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 761 struct qlcnic_hardware_context *ahw = adapter->ahw; 762 int cmd_type, err, opcode; 763 unsigned long timeout; 764 765 if (!mbx) 766 return -EIO; 767 768 opcode = LSW(cmd->req.arg[0]); 769 cmd_type = cmd->type; 770 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout); 771 if (err) { 772 dev_err(&adapter->pdev->dev, 773 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n", 774 __func__, opcode, cmd->type, ahw->pci_func, 775 ahw->op_mode); 776 return err; 777 } 778 779 switch (cmd_type) { 780 case QLC_83XX_MBX_CMD_WAIT: 781 if (!wait_for_completion_timeout(&cmd->completion, timeout)) { 782 dev_err(&adapter->pdev->dev, 783 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", 784 __func__, opcode, cmd_type, ahw->pci_func, 785 ahw->op_mode); 786 flush_workqueue(mbx->work_q); 787 } 788 break; 789 case QLC_83XX_MBX_CMD_NO_WAIT: 790 return 0; 791 case QLC_83XX_MBX_CMD_BUSY_WAIT: 792 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd); 793 break; 794 default: 795 dev_err(&adapter->pdev->dev, 796 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", 797 __func__, opcode, cmd_type, ahw->pci_func, 798 ahw->op_mode); 799 qlcnic_83xx_detach_mailbox_work(adapter); 800 } 801 802 return cmd->rsp_opcode; 803 } 804 805 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx, 806 struct qlcnic_adapter *adapter, u32 type) 807 { 808 int i, size; 809 u32 temp; 810 const struct qlcnic_mailbox_metadata *mbx_tbl; 811 812 memset(mbx, 0, sizeof(struct qlcnic_cmd_args)); 813 mbx_tbl = qlcnic_83xx_mbx_tbl; 814 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl); 815 for (i = 0; i < size; i++) { 816 if (type == mbx_tbl[i].cmd) { 817 mbx->op_type = QLC_83XX_FW_MBX_CMD; 818 mbx->req.num = mbx_tbl[i].in_args; 819 mbx->rsp.num = mbx_tbl[i].out_args; 820 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32), 821 GFP_ATOMIC); 822 if (!mbx->req.arg) 823 return -ENOMEM; 824 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32), 825 GFP_ATOMIC); 826 if (!mbx->rsp.arg) { 827 kfree(mbx->req.arg); 828 mbx->req.arg = NULL; 829 return -ENOMEM; 830 } 831 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num); 832 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num); 833 temp = adapter->ahw->fw_hal_version << 29; 834 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp); 835 mbx->cmd_op = type; 836 return 0; 837 } 838 } 839 return -EINVAL; 840 } 841 842 void qlcnic_83xx_idc_aen_work(struct work_struct *work) 843 { 844 struct qlcnic_adapter *adapter; 845 struct qlcnic_cmd_args cmd; 846 int i, err = 0; 847 848 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work); 849 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK); 850 if (err) 851 return; 852 853 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++) 854 cmd.req.arg[i] = adapter->ahw->mbox_aen[i]; 855 856 err = qlcnic_issue_cmd(adapter, &cmd); 857 if (err) 858 dev_info(&adapter->pdev->dev, 859 "%s: Mailbox IDC ACK failed.\n", __func__); 860 qlcnic_free_mbx_args(&cmd); 861 } 862 863 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter, 864 u32 data[]) 865 { 866 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n", 867 QLCNIC_MBX_RSP(data[0])); 868 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status); 869 return; 870 } 871 872 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter) 873 { 874 struct qlcnic_hardware_context *ahw = adapter->ahw; 875 u32 event[QLC_83XX_MBX_AEN_CNT]; 876 int i; 877 878 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++) 879 event[i] = readl(QLCNIC_MBX_FW(ahw, i)); 880 881 switch (QLCNIC_MBX_RSP(event[0])) { 882 883 case QLCNIC_MBX_LINK_EVENT: 884 qlcnic_83xx_handle_link_aen(adapter, event); 885 break; 886 case QLCNIC_MBX_COMP_EVENT: 887 qlcnic_83xx_handle_idc_comp_aen(adapter, event); 888 break; 889 case QLCNIC_MBX_REQUEST_EVENT: 890 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++) 891 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]); 892 queue_delayed_work(adapter->qlcnic_wq, 893 &adapter->idc_aen_work, 0); 894 break; 895 case QLCNIC_MBX_TIME_EXTEND_EVENT: 896 ahw->extend_lb_time = event[1] >> 8 & 0xf; 897 break; 898 case QLCNIC_MBX_BC_EVENT: 899 qlcnic_sriov_handle_bc_event(adapter, event[1]); 900 break; 901 case QLCNIC_MBX_SFP_INSERT_EVENT: 902 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n", 903 QLCNIC_MBX_RSP(event[0])); 904 break; 905 case QLCNIC_MBX_SFP_REMOVE_EVENT: 906 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n", 907 QLCNIC_MBX_RSP(event[0])); 908 break; 909 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT: 910 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]); 911 break; 912 default: 913 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n", 914 QLCNIC_MBX_RSP(event[0])); 915 break; 916 } 917 918 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER); 919 } 920 921 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter) 922 { 923 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED; 924 struct qlcnic_hardware_context *ahw = adapter->ahw; 925 struct qlcnic_mailbox *mbx = ahw->mailbox; 926 unsigned long flags; 927 928 spin_lock_irqsave(&mbx->aen_lock, flags); 929 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL); 930 if (resp & QLCNIC_SET_OWNER) { 931 event = readl(QLCNIC_MBX_FW(ahw, 0)); 932 if (event & QLCNIC_MBX_ASYNC_EVENT) { 933 __qlcnic_83xx_process_aen(adapter); 934 } else { 935 if (atomic_read(&mbx->rsp_status) != rsp_status) 936 qlcnic_83xx_notify_mbx_response(mbx); 937 } 938 } 939 spin_unlock_irqrestore(&mbx->aen_lock, flags); 940 } 941 942 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work) 943 { 944 struct qlcnic_adapter *adapter; 945 946 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work); 947 948 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) 949 return; 950 951 qlcnic_83xx_process_aen(adapter); 952 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 953 (HZ / 10)); 954 } 955 956 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter) 957 { 958 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) 959 return; 960 961 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work); 962 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0); 963 } 964 965 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter) 966 { 967 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) 968 return; 969 cancel_delayed_work_sync(&adapter->mbx_poll_work); 970 } 971 972 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter) 973 { 974 int index, i, err, sds_mbx_size; 975 u32 *buf, intrpt_id, intr_mask; 976 u16 context_id; 977 u8 num_sds; 978 struct qlcnic_cmd_args cmd; 979 struct qlcnic_host_sds_ring *sds; 980 struct qlcnic_sds_mbx sds_mbx; 981 struct qlcnic_add_rings_mbx_out *mbx_out; 982 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; 983 struct qlcnic_hardware_context *ahw = adapter->ahw; 984 985 sds_mbx_size = sizeof(struct qlcnic_sds_mbx); 986 context_id = recv_ctx->context_id; 987 num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS; 988 ahw->hw_ops->alloc_mbx_args(&cmd, adapter, 989 QLCNIC_CMD_ADD_RCV_RINGS); 990 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16); 991 992 /* set up status rings, mbx 2-81 */ 993 index = 2; 994 for (i = 8; i < adapter->drv_sds_rings; i++) { 995 memset(&sds_mbx, 0, sds_mbx_size); 996 sds = &recv_ctx->sds_rings[i]; 997 sds->consumer = 0; 998 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds)); 999 sds_mbx.phy_addr_low = LSD(sds->phys_addr); 1000 sds_mbx.phy_addr_high = MSD(sds->phys_addr); 1001 sds_mbx.sds_ring_size = sds->num_desc; 1002 1003 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1004 intrpt_id = ahw->intr_tbl[i].id; 1005 else 1006 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 1007 1008 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) 1009 sds_mbx.intrpt_id = intrpt_id; 1010 else 1011 sds_mbx.intrpt_id = 0xffff; 1012 sds_mbx.intrpt_val = 0; 1013 buf = &cmd.req.arg[index]; 1014 memcpy(buf, &sds_mbx, sds_mbx_size); 1015 index += sds_mbx_size / sizeof(u32); 1016 } 1017 1018 /* send the mailbox command */ 1019 err = ahw->hw_ops->mbx_cmd(adapter, &cmd); 1020 if (err) { 1021 dev_err(&adapter->pdev->dev, 1022 "Failed to add rings %d\n", err); 1023 goto out; 1024 } 1025 1026 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1]; 1027 index = 0; 1028 /* status descriptor ring */ 1029 for (i = 8; i < adapter->drv_sds_rings; i++) { 1030 sds = &recv_ctx->sds_rings[i]; 1031 sds->crb_sts_consumer = ahw->pci_base0 + 1032 mbx_out->host_csmr[index]; 1033 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1034 intr_mask = ahw->intr_tbl[i].src; 1035 else 1036 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK); 1037 1038 sds->crb_intr_mask = ahw->pci_base0 + intr_mask; 1039 index++; 1040 } 1041 out: 1042 qlcnic_free_mbx_args(&cmd); 1043 return err; 1044 } 1045 1046 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter) 1047 { 1048 int err; 1049 u32 temp = 0; 1050 struct qlcnic_cmd_args cmd; 1051 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; 1052 1053 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX)) 1054 return; 1055 1056 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1057 cmd.req.arg[0] |= (0x3 << 29); 1058 1059 if (qlcnic_sriov_pf_check(adapter)) 1060 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp); 1061 1062 cmd.req.arg[1] = recv_ctx->context_id | temp; 1063 err = qlcnic_issue_cmd(adapter, &cmd); 1064 if (err) 1065 dev_err(&adapter->pdev->dev, 1066 "Failed to destroy rx ctx in firmware\n"); 1067 1068 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED; 1069 qlcnic_free_mbx_args(&cmd); 1070 } 1071 1072 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter) 1073 { 1074 int i, err, index, sds_mbx_size, rds_mbx_size; 1075 u8 num_sds, num_rds; 1076 u32 *buf, intrpt_id, intr_mask, cap = 0; 1077 struct qlcnic_host_sds_ring *sds; 1078 struct qlcnic_host_rds_ring *rds; 1079 struct qlcnic_sds_mbx sds_mbx; 1080 struct qlcnic_rds_mbx rds_mbx; 1081 struct qlcnic_cmd_args cmd; 1082 struct qlcnic_rcv_mbx_out *mbx_out; 1083 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; 1084 struct qlcnic_hardware_context *ahw = adapter->ahw; 1085 num_rds = adapter->max_rds_rings; 1086 1087 if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS) 1088 num_sds = adapter->drv_sds_rings; 1089 else 1090 num_sds = QLCNIC_MAX_SDS_RINGS; 1091 1092 sds_mbx_size = sizeof(struct qlcnic_sds_mbx); 1093 rds_mbx_size = sizeof(struct qlcnic_rds_mbx); 1094 cap = QLCNIC_CAP0_LEGACY_CONTEXT; 1095 1096 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP) 1097 cap |= QLC_83XX_FW_CAP_LRO_MSS; 1098 1099 /* set mailbox hdr and capabilities */ 1100 err = qlcnic_alloc_mbx_args(&cmd, adapter, 1101 QLCNIC_CMD_CREATE_RX_CTX); 1102 if (err) 1103 return err; 1104 1105 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1106 cmd.req.arg[0] |= (0x3 << 29); 1107 1108 cmd.req.arg[1] = cap; 1109 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) | 1110 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16); 1111 1112 if (qlcnic_sriov_pf_check(adapter)) 1113 qlcnic_pf_set_interface_id_create_rx_ctx(adapter, 1114 &cmd.req.arg[6]); 1115 /* set up status rings, mbx 8-57/87 */ 1116 index = QLC_83XX_HOST_SDS_MBX_IDX; 1117 for (i = 0; i < num_sds; i++) { 1118 memset(&sds_mbx, 0, sds_mbx_size); 1119 sds = &recv_ctx->sds_rings[i]; 1120 sds->consumer = 0; 1121 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds)); 1122 sds_mbx.phy_addr_low = LSD(sds->phys_addr); 1123 sds_mbx.phy_addr_high = MSD(sds->phys_addr); 1124 sds_mbx.sds_ring_size = sds->num_desc; 1125 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1126 intrpt_id = ahw->intr_tbl[i].id; 1127 else 1128 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 1129 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) 1130 sds_mbx.intrpt_id = intrpt_id; 1131 else 1132 sds_mbx.intrpt_id = 0xffff; 1133 sds_mbx.intrpt_val = 0; 1134 buf = &cmd.req.arg[index]; 1135 memcpy(buf, &sds_mbx, sds_mbx_size); 1136 index += sds_mbx_size / sizeof(u32); 1137 } 1138 /* set up receive rings, mbx 88-111/135 */ 1139 index = QLCNIC_HOST_RDS_MBX_IDX; 1140 rds = &recv_ctx->rds_rings[0]; 1141 rds->producer = 0; 1142 memset(&rds_mbx, 0, rds_mbx_size); 1143 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr); 1144 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr); 1145 rds_mbx.reg_ring_sz = rds->dma_size; 1146 rds_mbx.reg_ring_len = rds->num_desc; 1147 /* Jumbo ring */ 1148 rds = &recv_ctx->rds_rings[1]; 1149 rds->producer = 0; 1150 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr); 1151 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr); 1152 rds_mbx.jmb_ring_sz = rds->dma_size; 1153 rds_mbx.jmb_ring_len = rds->num_desc; 1154 buf = &cmd.req.arg[index]; 1155 memcpy(buf, &rds_mbx, rds_mbx_size); 1156 1157 /* send the mailbox command */ 1158 err = ahw->hw_ops->mbx_cmd(adapter, &cmd); 1159 if (err) { 1160 dev_err(&adapter->pdev->dev, 1161 "Failed to create Rx ctx in firmware%d\n", err); 1162 goto out; 1163 } 1164 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1]; 1165 recv_ctx->context_id = mbx_out->ctx_id; 1166 recv_ctx->state = mbx_out->state; 1167 recv_ctx->virt_port = mbx_out->vport_id; 1168 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n", 1169 recv_ctx->context_id, recv_ctx->state); 1170 /* Receive descriptor ring */ 1171 /* Standard ring */ 1172 rds = &recv_ctx->rds_rings[0]; 1173 rds->crb_rcv_producer = ahw->pci_base0 + 1174 mbx_out->host_prod[0].reg_buf; 1175 /* Jumbo ring */ 1176 rds = &recv_ctx->rds_rings[1]; 1177 rds->crb_rcv_producer = ahw->pci_base0 + 1178 mbx_out->host_prod[0].jmb_buf; 1179 /* status descriptor ring */ 1180 for (i = 0; i < num_sds; i++) { 1181 sds = &recv_ctx->sds_rings[i]; 1182 sds->crb_sts_consumer = ahw->pci_base0 + 1183 mbx_out->host_csmr[i]; 1184 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1185 intr_mask = ahw->intr_tbl[i].src; 1186 else 1187 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK); 1188 sds->crb_intr_mask = ahw->pci_base0 + intr_mask; 1189 } 1190 1191 if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS) 1192 err = qlcnic_83xx_add_rings(adapter); 1193 out: 1194 qlcnic_free_mbx_args(&cmd); 1195 return err; 1196 } 1197 1198 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter, 1199 struct qlcnic_host_tx_ring *tx_ring) 1200 { 1201 struct qlcnic_cmd_args cmd; 1202 u32 temp = 0; 1203 1204 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX)) 1205 return; 1206 1207 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1208 cmd.req.arg[0] |= (0x3 << 29); 1209 1210 if (qlcnic_sriov_pf_check(adapter)) 1211 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp); 1212 1213 cmd.req.arg[1] = tx_ring->ctx_id | temp; 1214 if (qlcnic_issue_cmd(adapter, &cmd)) 1215 dev_err(&adapter->pdev->dev, 1216 "Failed to destroy tx ctx in firmware\n"); 1217 qlcnic_free_mbx_args(&cmd); 1218 } 1219 1220 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter, 1221 struct qlcnic_host_tx_ring *tx, int ring) 1222 { 1223 int err; 1224 u16 msix_id; 1225 u32 *buf, intr_mask, temp = 0; 1226 struct qlcnic_cmd_args cmd; 1227 struct qlcnic_tx_mbx mbx; 1228 struct qlcnic_tx_mbx_out *mbx_out; 1229 struct qlcnic_hardware_context *ahw = adapter->ahw; 1230 u32 msix_vector; 1231 1232 /* Reset host resources */ 1233 tx->producer = 0; 1234 tx->sw_consumer = 0; 1235 *(tx->hw_consumer) = 0; 1236 1237 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx)); 1238 1239 /* setup mailbox inbox registerss */ 1240 mbx.phys_addr_low = LSD(tx->phys_addr); 1241 mbx.phys_addr_high = MSD(tx->phys_addr); 1242 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr); 1243 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr); 1244 mbx.size = tx->num_desc; 1245 if (adapter->flags & QLCNIC_MSIX_ENABLED) { 1246 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED)) 1247 msix_vector = adapter->drv_sds_rings + ring; 1248 else 1249 msix_vector = adapter->drv_sds_rings - 1; 1250 msix_id = ahw->intr_tbl[msix_vector].id; 1251 } else { 1252 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 1253 } 1254 1255 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) 1256 mbx.intr_id = msix_id; 1257 else 1258 mbx.intr_id = 0xffff; 1259 mbx.src = 0; 1260 1261 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX); 1262 if (err) 1263 return err; 1264 1265 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1266 cmd.req.arg[0] |= (0x3 << 29); 1267 1268 if (qlcnic_sriov_pf_check(adapter)) 1269 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp); 1270 1271 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT; 1272 cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp; 1273 1274 buf = &cmd.req.arg[6]; 1275 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx)); 1276 /* send the mailbox command*/ 1277 err = qlcnic_issue_cmd(adapter, &cmd); 1278 if (err) { 1279 dev_err(&adapter->pdev->dev, 1280 "Failed to create Tx ctx in firmware 0x%x\n", err); 1281 goto out; 1282 } 1283 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2]; 1284 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod; 1285 tx->ctx_id = mbx_out->ctx_id; 1286 if ((adapter->flags & QLCNIC_MSIX_ENABLED) && 1287 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) { 1288 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src; 1289 tx->crb_intr_mask = ahw->pci_base0 + intr_mask; 1290 } 1291 dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n", 1292 tx->ctx_id, mbx_out->state); 1293 out: 1294 qlcnic_free_mbx_args(&cmd); 1295 return err; 1296 } 1297 1298 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test, 1299 u8 num_sds_ring) 1300 { 1301 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1302 struct qlcnic_host_sds_ring *sds_ring; 1303 struct qlcnic_host_rds_ring *rds_ring; 1304 u16 adapter_state = adapter->is_up; 1305 u8 ring; 1306 int ret; 1307 1308 netif_device_detach(netdev); 1309 1310 if (netif_running(netdev)) 1311 __qlcnic_down(adapter, netdev); 1312 1313 qlcnic_detach(adapter); 1314 1315 adapter->drv_sds_rings = QLCNIC_SINGLE_RING; 1316 adapter->ahw->diag_test = test; 1317 adapter->ahw->linkup = 0; 1318 1319 ret = qlcnic_attach(adapter); 1320 if (ret) { 1321 netif_device_attach(netdev); 1322 return ret; 1323 } 1324 1325 ret = qlcnic_fw_create_ctx(adapter); 1326 if (ret) { 1327 qlcnic_detach(adapter); 1328 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) { 1329 adapter->drv_sds_rings = num_sds_ring; 1330 qlcnic_attach(adapter); 1331 } 1332 netif_device_attach(netdev); 1333 return ret; 1334 } 1335 1336 for (ring = 0; ring < adapter->max_rds_rings; ring++) { 1337 rds_ring = &adapter->recv_ctx->rds_rings[ring]; 1338 qlcnic_post_rx_buffers(adapter, rds_ring, ring); 1339 } 1340 1341 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) { 1342 for (ring = 0; ring < adapter->drv_sds_rings; ring++) { 1343 sds_ring = &adapter->recv_ctx->sds_rings[ring]; 1344 qlcnic_83xx_enable_intr(adapter, sds_ring); 1345 } 1346 } 1347 1348 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) { 1349 adapter->ahw->loopback_state = 0; 1350 adapter->ahw->hw_ops->setup_link_event(adapter, 1); 1351 } 1352 1353 set_bit(__QLCNIC_DEV_UP, &adapter->state); 1354 return 0; 1355 } 1356 1357 static void qlcnic_83xx_diag_free_res(struct net_device *netdev, 1358 u8 drv_sds_rings) 1359 { 1360 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1361 struct qlcnic_host_sds_ring *sds_ring; 1362 int ring; 1363 1364 clear_bit(__QLCNIC_DEV_UP, &adapter->state); 1365 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) { 1366 for (ring = 0; ring < adapter->drv_sds_rings; ring++) { 1367 sds_ring = &adapter->recv_ctx->sds_rings[ring]; 1368 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1369 qlcnic_83xx_disable_intr(adapter, sds_ring); 1370 } 1371 } 1372 1373 qlcnic_fw_destroy_ctx(adapter); 1374 qlcnic_detach(adapter); 1375 1376 adapter->ahw->diag_test = 0; 1377 adapter->drv_sds_rings = drv_sds_rings; 1378 1379 if (qlcnic_attach(adapter)) 1380 goto out; 1381 1382 if (netif_running(netdev)) 1383 __qlcnic_up(adapter, netdev); 1384 1385 out: 1386 netif_device_attach(netdev); 1387 } 1388 1389 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state, 1390 u32 beacon) 1391 { 1392 struct qlcnic_cmd_args cmd; 1393 u32 mbx_in; 1394 int i, status = 0; 1395 1396 if (state) { 1397 /* Get LED configuration */ 1398 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1399 QLCNIC_CMD_GET_LED_CONFIG); 1400 if (status) 1401 return status; 1402 1403 status = qlcnic_issue_cmd(adapter, &cmd); 1404 if (status) { 1405 dev_err(&adapter->pdev->dev, 1406 "Get led config failed.\n"); 1407 goto mbx_err; 1408 } else { 1409 for (i = 0; i < 4; i++) 1410 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1]; 1411 } 1412 qlcnic_free_mbx_args(&cmd); 1413 /* Set LED Configuration */ 1414 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) | 1415 LSW(QLC_83XX_LED_CONFIG); 1416 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1417 QLCNIC_CMD_SET_LED_CONFIG); 1418 if (status) 1419 return status; 1420 1421 cmd.req.arg[1] = mbx_in; 1422 cmd.req.arg[2] = mbx_in; 1423 cmd.req.arg[3] = mbx_in; 1424 if (beacon) 1425 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON; 1426 status = qlcnic_issue_cmd(adapter, &cmd); 1427 if (status) { 1428 dev_err(&adapter->pdev->dev, 1429 "Set led config failed.\n"); 1430 } 1431 mbx_err: 1432 qlcnic_free_mbx_args(&cmd); 1433 return status; 1434 1435 } else { 1436 /* Restoring default LED configuration */ 1437 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1438 QLCNIC_CMD_SET_LED_CONFIG); 1439 if (status) 1440 return status; 1441 1442 cmd.req.arg[1] = adapter->ahw->mbox_reg[0]; 1443 cmd.req.arg[2] = adapter->ahw->mbox_reg[1]; 1444 cmd.req.arg[3] = adapter->ahw->mbox_reg[2]; 1445 if (beacon) 1446 cmd.req.arg[4] = adapter->ahw->mbox_reg[3]; 1447 status = qlcnic_issue_cmd(adapter, &cmd); 1448 if (status) 1449 dev_err(&adapter->pdev->dev, 1450 "Restoring led config failed.\n"); 1451 qlcnic_free_mbx_args(&cmd); 1452 return status; 1453 } 1454 } 1455 1456 int qlcnic_83xx_set_led(struct net_device *netdev, 1457 enum ethtool_phys_id_state state) 1458 { 1459 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1460 int err = -EIO, active = 1; 1461 1462 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) { 1463 netdev_warn(netdev, 1464 "LED test is not supported in non-privileged mode\n"); 1465 return -EOPNOTSUPP; 1466 } 1467 1468 switch (state) { 1469 case ETHTOOL_ID_ACTIVE: 1470 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state)) 1471 return -EBUSY; 1472 1473 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) 1474 break; 1475 1476 err = qlcnic_83xx_config_led(adapter, active, 0); 1477 if (err) 1478 netdev_err(netdev, "Failed to set LED blink state\n"); 1479 break; 1480 case ETHTOOL_ID_INACTIVE: 1481 active = 0; 1482 1483 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) 1484 break; 1485 1486 err = qlcnic_83xx_config_led(adapter, active, 0); 1487 if (err) 1488 netdev_err(netdev, "Failed to reset LED blink state\n"); 1489 break; 1490 1491 default: 1492 return -EINVAL; 1493 } 1494 1495 if (!active || err) 1496 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state); 1497 1498 return err; 1499 } 1500 1501 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter, 1502 int enable) 1503 { 1504 struct qlcnic_cmd_args cmd; 1505 int status; 1506 1507 if (qlcnic_sriov_vf_check(adapter)) 1508 return; 1509 1510 if (enable) { 1511 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1512 QLCNIC_CMD_INIT_NIC_FUNC); 1513 if (status) 1514 return; 1515 1516 cmd.req.arg[1] = BIT_0 | BIT_31; 1517 } else { 1518 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1519 QLCNIC_CMD_STOP_NIC_FUNC); 1520 if (status) 1521 return; 1522 1523 cmd.req.arg[1] = BIT_0 | BIT_31; 1524 } 1525 status = qlcnic_issue_cmd(adapter, &cmd); 1526 if (status) 1527 dev_err(&adapter->pdev->dev, 1528 "Failed to %s in NIC IDC function event.\n", 1529 (enable ? "register" : "unregister")); 1530 1531 qlcnic_free_mbx_args(&cmd); 1532 } 1533 1534 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter) 1535 { 1536 struct qlcnic_cmd_args cmd; 1537 int err; 1538 1539 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG); 1540 if (err) 1541 return err; 1542 1543 cmd.req.arg[1] = adapter->ahw->port_config; 1544 err = qlcnic_issue_cmd(adapter, &cmd); 1545 if (err) 1546 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n"); 1547 qlcnic_free_mbx_args(&cmd); 1548 return err; 1549 } 1550 1551 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter) 1552 { 1553 struct qlcnic_cmd_args cmd; 1554 int err; 1555 1556 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG); 1557 if (err) 1558 return err; 1559 1560 err = qlcnic_issue_cmd(adapter, &cmd); 1561 if (err) 1562 dev_info(&adapter->pdev->dev, "Get Port config failed\n"); 1563 else 1564 adapter->ahw->port_config = cmd.rsp.arg[1]; 1565 qlcnic_free_mbx_args(&cmd); 1566 return err; 1567 } 1568 1569 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable) 1570 { 1571 int err; 1572 u32 temp; 1573 struct qlcnic_cmd_args cmd; 1574 1575 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT); 1576 if (err) 1577 return err; 1578 1579 temp = adapter->recv_ctx->context_id << 16; 1580 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp; 1581 err = qlcnic_issue_cmd(adapter, &cmd); 1582 if (err) 1583 dev_info(&adapter->pdev->dev, 1584 "Setup linkevent mailbox failed\n"); 1585 qlcnic_free_mbx_args(&cmd); 1586 return err; 1587 } 1588 1589 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter, 1590 u32 *interface_id) 1591 { 1592 if (qlcnic_sriov_pf_check(adapter)) { 1593 qlcnic_pf_set_interface_id_promisc(adapter, interface_id); 1594 } else { 1595 if (!qlcnic_sriov_vf_check(adapter)) 1596 *interface_id = adapter->recv_ctx->context_id << 16; 1597 } 1598 } 1599 1600 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode) 1601 { 1602 struct qlcnic_cmd_args *cmd = NULL; 1603 u32 temp = 0; 1604 int err; 1605 1606 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 1607 return -EIO; 1608 1609 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC); 1610 if (!cmd) 1611 return -ENOMEM; 1612 1613 err = qlcnic_alloc_mbx_args(cmd, adapter, 1614 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE); 1615 if (err) 1616 goto out; 1617 1618 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT; 1619 qlcnic_83xx_set_interface_id_promisc(adapter, &temp); 1620 cmd->req.arg[1] = (mode ? 1 : 0) | temp; 1621 err = qlcnic_issue_cmd(adapter, cmd); 1622 if (!err) 1623 return err; 1624 1625 qlcnic_free_mbx_args(cmd); 1626 1627 out: 1628 kfree(cmd); 1629 return err; 1630 } 1631 1632 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode) 1633 { 1634 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1635 struct qlcnic_hardware_context *ahw = adapter->ahw; 1636 u8 drv_sds_rings = adapter->drv_sds_rings; 1637 u8 drv_tx_rings = adapter->drv_tx_rings; 1638 int ret = 0, loop = 0; 1639 1640 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) { 1641 netdev_warn(netdev, 1642 "Loopback test not supported in non privileged mode\n"); 1643 return -ENOTSUPP; 1644 } 1645 1646 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1647 netdev_info(netdev, "Device is resetting\n"); 1648 return -EBUSY; 1649 } 1650 1651 if (qlcnic_get_diag_lock(adapter)) { 1652 netdev_info(netdev, "Device is in diagnostics mode\n"); 1653 return -EBUSY; 1654 } 1655 1656 netdev_info(netdev, "%s loopback test in progress\n", 1657 mode == QLCNIC_ILB_MODE ? "internal" : "external"); 1658 1659 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST, 1660 drv_sds_rings); 1661 if (ret) 1662 goto fail_diag_alloc; 1663 1664 ret = qlcnic_83xx_set_lb_mode(adapter, mode); 1665 if (ret) 1666 goto free_diag_res; 1667 1668 /* Poll for link up event before running traffic */ 1669 do { 1670 msleep(QLC_83XX_LB_MSLEEP_COUNT); 1671 1672 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1673 netdev_info(netdev, 1674 "Device is resetting, free LB test resources\n"); 1675 ret = -EBUSY; 1676 goto free_diag_res; 1677 } 1678 if (loop++ > QLC_83XX_LB_WAIT_COUNT) { 1679 netdev_info(netdev, 1680 "Firmware didn't sent link up event to loopback request\n"); 1681 ret = -ETIMEDOUT; 1682 qlcnic_83xx_clear_lb_mode(adapter, mode); 1683 goto free_diag_res; 1684 } 1685 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1); 1686 1687 ret = qlcnic_do_lb_test(adapter, mode); 1688 1689 qlcnic_83xx_clear_lb_mode(adapter, mode); 1690 1691 free_diag_res: 1692 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings); 1693 1694 fail_diag_alloc: 1695 adapter->drv_sds_rings = drv_sds_rings; 1696 adapter->drv_tx_rings = drv_tx_rings; 1697 qlcnic_release_diag_lock(adapter); 1698 return ret; 1699 } 1700 1701 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter, 1702 u32 *max_wait_count) 1703 { 1704 struct qlcnic_hardware_context *ahw = adapter->ahw; 1705 int temp; 1706 1707 netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n", 1708 ahw->extend_lb_time); 1709 temp = ahw->extend_lb_time * 1000; 1710 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT; 1711 ahw->extend_lb_time = 0; 1712 } 1713 1714 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1715 { 1716 struct qlcnic_hardware_context *ahw = adapter->ahw; 1717 struct net_device *netdev = adapter->netdev; 1718 u32 config, max_wait_count; 1719 int status = 0, loop = 0; 1720 1721 ahw->extend_lb_time = 0; 1722 max_wait_count = QLC_83XX_LB_WAIT_COUNT; 1723 status = qlcnic_83xx_get_port_config(adapter); 1724 if (status) 1725 return status; 1726 1727 config = ahw->port_config; 1728 1729 /* Check if port is already in loopback mode */ 1730 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) || 1731 (config & QLC_83XX_CFG_LOOPBACK_EXT)) { 1732 netdev_err(netdev, 1733 "Port already in Loopback mode.\n"); 1734 return -EINPROGRESS; 1735 } 1736 1737 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1738 1739 if (mode == QLCNIC_ILB_MODE) 1740 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS; 1741 if (mode == QLCNIC_ELB_MODE) 1742 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT; 1743 1744 status = qlcnic_83xx_set_port_config(adapter); 1745 if (status) { 1746 netdev_err(netdev, 1747 "Failed to Set Loopback Mode = 0x%x.\n", 1748 ahw->port_config); 1749 ahw->port_config = config; 1750 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1751 return status; 1752 } 1753 1754 /* Wait for Link and IDC Completion AEN */ 1755 do { 1756 msleep(QLC_83XX_LB_MSLEEP_COUNT); 1757 1758 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1759 netdev_info(netdev, 1760 "Device is resetting, free LB test resources\n"); 1761 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1762 return -EBUSY; 1763 } 1764 1765 if (ahw->extend_lb_time) 1766 qlcnic_extend_lb_idc_cmpltn_wait(adapter, 1767 &max_wait_count); 1768 1769 if (loop++ > max_wait_count) { 1770 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n", 1771 __func__); 1772 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1773 qlcnic_83xx_clear_lb_mode(adapter, mode); 1774 return -ETIMEDOUT; 1775 } 1776 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status)); 1777 1778 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0, 1779 QLCNIC_MAC_ADD); 1780 return status; 1781 } 1782 1783 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1784 { 1785 struct qlcnic_hardware_context *ahw = adapter->ahw; 1786 u32 config = ahw->port_config, max_wait_count; 1787 struct net_device *netdev = adapter->netdev; 1788 int status = 0, loop = 0; 1789 1790 ahw->extend_lb_time = 0; 1791 max_wait_count = QLC_83XX_LB_WAIT_COUNT; 1792 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1793 if (mode == QLCNIC_ILB_MODE) 1794 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS; 1795 if (mode == QLCNIC_ELB_MODE) 1796 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT; 1797 1798 status = qlcnic_83xx_set_port_config(adapter); 1799 if (status) { 1800 netdev_err(netdev, 1801 "Failed to Clear Loopback Mode = 0x%x.\n", 1802 ahw->port_config); 1803 ahw->port_config = config; 1804 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1805 return status; 1806 } 1807 1808 /* Wait for Link and IDC Completion AEN */ 1809 do { 1810 msleep(QLC_83XX_LB_MSLEEP_COUNT); 1811 1812 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1813 netdev_info(netdev, 1814 "Device is resetting, free LB test resources\n"); 1815 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1816 return -EBUSY; 1817 } 1818 1819 if (ahw->extend_lb_time) 1820 qlcnic_extend_lb_idc_cmpltn_wait(adapter, 1821 &max_wait_count); 1822 1823 if (loop++ > max_wait_count) { 1824 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n", 1825 __func__); 1826 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1827 return -ETIMEDOUT; 1828 } 1829 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status)); 1830 1831 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0, 1832 QLCNIC_MAC_DEL); 1833 return status; 1834 } 1835 1836 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter, 1837 u32 *interface_id) 1838 { 1839 if (qlcnic_sriov_pf_check(adapter)) { 1840 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id); 1841 } else { 1842 if (!qlcnic_sriov_vf_check(adapter)) 1843 *interface_id = adapter->recv_ctx->context_id << 16; 1844 } 1845 } 1846 1847 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, 1848 int mode) 1849 { 1850 int err; 1851 u32 temp = 0, temp_ip; 1852 struct qlcnic_cmd_args cmd; 1853 1854 err = qlcnic_alloc_mbx_args(&cmd, adapter, 1855 QLCNIC_CMD_CONFIGURE_IP_ADDR); 1856 if (err) 1857 return; 1858 1859 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp); 1860 1861 if (mode == QLCNIC_IP_UP) 1862 cmd.req.arg[1] = 1 | temp; 1863 else 1864 cmd.req.arg[1] = 2 | temp; 1865 1866 /* 1867 * Adapter needs IP address in network byte order. 1868 * But hardware mailbox registers go through writel(), hence IP address 1869 * gets swapped on big endian architecture. 1870 * To negate swapping of writel() on big endian architecture 1871 * use swab32(value). 1872 */ 1873 1874 temp_ip = swab32(ntohl(ip)); 1875 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32)); 1876 err = qlcnic_issue_cmd(adapter, &cmd); 1877 if (err != QLCNIC_RCODE_SUCCESS) 1878 dev_err(&adapter->netdev->dev, 1879 "could not notify %s IP 0x%x request\n", 1880 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip); 1881 1882 qlcnic_free_mbx_args(&cmd); 1883 } 1884 1885 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode) 1886 { 1887 int err; 1888 u32 temp, arg1; 1889 struct qlcnic_cmd_args cmd; 1890 int lro_bit_mask; 1891 1892 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); 1893 1894 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 1895 return 0; 1896 1897 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO); 1898 if (err) 1899 return err; 1900 1901 temp = adapter->recv_ctx->context_id << 16; 1902 arg1 = lro_bit_mask | temp; 1903 cmd.req.arg[1] = arg1; 1904 1905 err = qlcnic_issue_cmd(adapter, &cmd); 1906 if (err) 1907 dev_info(&adapter->pdev->dev, "LRO config failed\n"); 1908 qlcnic_free_mbx_args(&cmd); 1909 1910 return err; 1911 } 1912 1913 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable) 1914 { 1915 int err; 1916 u32 word; 1917 struct qlcnic_cmd_args cmd; 1918 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, 1919 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, 1920 0x255b0ec26d5a56daULL }; 1921 1922 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS); 1923 if (err) 1924 return err; 1925 /* 1926 * RSS request: 1927 * bits 3-0: Rsvd 1928 * 5-4: hash_type_ipv4 1929 * 7-6: hash_type_ipv6 1930 * 8: enable 1931 * 9: use indirection table 1932 * 16-31: indirection table mask 1933 */ 1934 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | 1935 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | 1936 ((u32)(enable & 0x1) << 8) | 1937 ((0x7ULL) << 16); 1938 cmd.req.arg[1] = (adapter->recv_ctx->context_id); 1939 cmd.req.arg[2] = word; 1940 memcpy(&cmd.req.arg[4], key, sizeof(key)); 1941 1942 err = qlcnic_issue_cmd(adapter, &cmd); 1943 1944 if (err) 1945 dev_info(&adapter->pdev->dev, "RSS config failed\n"); 1946 qlcnic_free_mbx_args(&cmd); 1947 1948 return err; 1949 1950 } 1951 1952 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter, 1953 u32 *interface_id) 1954 { 1955 if (qlcnic_sriov_pf_check(adapter)) { 1956 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id); 1957 } else { 1958 if (!qlcnic_sriov_vf_check(adapter)) 1959 *interface_id = adapter->recv_ctx->context_id << 16; 1960 } 1961 } 1962 1963 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr, 1964 u16 vlan_id, u8 op) 1965 { 1966 struct qlcnic_cmd_args *cmd = NULL; 1967 struct qlcnic_macvlan_mbx mv; 1968 u32 *buf, temp = 0; 1969 int err; 1970 1971 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 1972 return -EIO; 1973 1974 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC); 1975 if (!cmd) 1976 return -ENOMEM; 1977 1978 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN); 1979 if (err) 1980 goto out; 1981 1982 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT; 1983 1984 if (vlan_id) 1985 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ? 1986 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL; 1987 1988 cmd->req.arg[1] = op | (1 << 8); 1989 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp); 1990 cmd->req.arg[1] |= temp; 1991 mv.vlan = vlan_id; 1992 mv.mac_addr0 = addr[0]; 1993 mv.mac_addr1 = addr[1]; 1994 mv.mac_addr2 = addr[2]; 1995 mv.mac_addr3 = addr[3]; 1996 mv.mac_addr4 = addr[4]; 1997 mv.mac_addr5 = addr[5]; 1998 buf = &cmd->req.arg[2]; 1999 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx)); 2000 err = qlcnic_issue_cmd(adapter, cmd); 2001 if (!err) 2002 return err; 2003 2004 qlcnic_free_mbx_args(cmd); 2005 out: 2006 kfree(cmd); 2007 return err; 2008 } 2009 2010 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr, 2011 u16 vlan_id) 2012 { 2013 u8 mac[ETH_ALEN]; 2014 memcpy(&mac, addr, ETH_ALEN); 2015 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD); 2016 } 2017 2018 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac, 2019 u8 type, struct qlcnic_cmd_args *cmd) 2020 { 2021 switch (type) { 2022 case QLCNIC_SET_STATION_MAC: 2023 case QLCNIC_SET_FAC_DEF_MAC: 2024 memcpy(&cmd->req.arg[2], mac, sizeof(u32)); 2025 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16)); 2026 break; 2027 } 2028 cmd->req.arg[1] = type; 2029 } 2030 2031 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac, 2032 u8 function) 2033 { 2034 int err, i; 2035 struct qlcnic_cmd_args cmd; 2036 u32 mac_low, mac_high; 2037 2038 function = 0; 2039 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS); 2040 if (err) 2041 return err; 2042 2043 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd); 2044 err = qlcnic_issue_cmd(adapter, &cmd); 2045 2046 if (err == QLCNIC_RCODE_SUCCESS) { 2047 mac_low = cmd.rsp.arg[1]; 2048 mac_high = cmd.rsp.arg[2]; 2049 2050 for (i = 0; i < 2; i++) 2051 mac[i] = (u8) (mac_high >> ((1 - i) * 8)); 2052 for (i = 2; i < 6; i++) 2053 mac[i] = (u8) (mac_low >> ((5 - i) * 8)); 2054 } else { 2055 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n", 2056 err); 2057 err = -EIO; 2058 } 2059 qlcnic_free_mbx_args(&cmd); 2060 return err; 2061 } 2062 2063 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter) 2064 { 2065 int err; 2066 u16 temp; 2067 struct qlcnic_cmd_args cmd; 2068 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal; 2069 2070 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 2071 return; 2072 2073 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL); 2074 if (err) 2075 return; 2076 2077 if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) { 2078 temp = adapter->recv_ctx->context_id; 2079 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16; 2080 temp = coal->rx_time_us; 2081 cmd.req.arg[2] = coal->rx_packets | temp << 16; 2082 } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) { 2083 temp = adapter->tx_ring->ctx_id; 2084 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16; 2085 temp = coal->tx_time_us; 2086 cmd.req.arg[2] = coal->tx_packets | temp << 16; 2087 } 2088 cmd.req.arg[3] = coal->flag; 2089 err = qlcnic_issue_cmd(adapter, &cmd); 2090 if (err != QLCNIC_RCODE_SUCCESS) 2091 dev_info(&adapter->pdev->dev, 2092 "Failed to send interrupt coalescence parameters\n"); 2093 qlcnic_free_mbx_args(&cmd); 2094 } 2095 2096 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter, 2097 u32 data[]) 2098 { 2099 struct qlcnic_hardware_context *ahw = adapter->ahw; 2100 u8 link_status, duplex; 2101 /* link speed */ 2102 link_status = LSB(data[3]) & 1; 2103 if (link_status) { 2104 ahw->link_speed = MSW(data[2]); 2105 duplex = LSB(MSW(data[3])); 2106 if (duplex) 2107 ahw->link_duplex = DUPLEX_FULL; 2108 else 2109 ahw->link_duplex = DUPLEX_HALF; 2110 } else { 2111 ahw->link_speed = SPEED_UNKNOWN; 2112 ahw->link_duplex = DUPLEX_UNKNOWN; 2113 } 2114 2115 ahw->link_autoneg = MSB(MSW(data[3])); 2116 ahw->module_type = MSB(LSW(data[3])); 2117 ahw->has_link_events = 1; 2118 ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK; 2119 qlcnic_advert_link_change(adapter, link_status); 2120 } 2121 2122 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data) 2123 { 2124 struct qlcnic_adapter *adapter = data; 2125 struct qlcnic_mailbox *mbx; 2126 u32 mask, resp, event; 2127 unsigned long flags; 2128 2129 mbx = adapter->ahw->mailbox; 2130 spin_lock_irqsave(&mbx->aen_lock, flags); 2131 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL); 2132 if (!(resp & QLCNIC_SET_OWNER)) 2133 goto out; 2134 2135 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0)); 2136 if (event & QLCNIC_MBX_ASYNC_EVENT) 2137 __qlcnic_83xx_process_aen(adapter); 2138 else 2139 qlcnic_83xx_notify_mbx_response(mbx); 2140 2141 out: 2142 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); 2143 writel(0, adapter->ahw->pci_base0 + mask); 2144 spin_unlock_irqrestore(&mbx->aen_lock, flags); 2145 return IRQ_HANDLED; 2146 } 2147 2148 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable) 2149 { 2150 int err = -EIO; 2151 struct qlcnic_cmd_args cmd; 2152 2153 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) { 2154 dev_err(&adapter->pdev->dev, 2155 "%s: Error, invoked by non management func\n", 2156 __func__); 2157 return err; 2158 } 2159 2160 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH); 2161 if (err) 2162 return err; 2163 2164 cmd.req.arg[1] = (port & 0xf) | BIT_4; 2165 err = qlcnic_issue_cmd(adapter, &cmd); 2166 2167 if (err != QLCNIC_RCODE_SUCCESS) { 2168 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n", 2169 err); 2170 err = -EIO; 2171 } 2172 qlcnic_free_mbx_args(&cmd); 2173 2174 return err; 2175 2176 } 2177 2178 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter, 2179 struct qlcnic_info *nic) 2180 { 2181 int i, err = -EIO; 2182 struct qlcnic_cmd_args cmd; 2183 2184 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) { 2185 dev_err(&adapter->pdev->dev, 2186 "%s: Error, invoked by non management func\n", 2187 __func__); 2188 return err; 2189 } 2190 2191 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO); 2192 if (err) 2193 return err; 2194 2195 cmd.req.arg[1] = (nic->pci_func << 16); 2196 cmd.req.arg[2] = 0x1 << 16; 2197 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16); 2198 cmd.req.arg[4] = nic->capabilities; 2199 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16); 2200 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16); 2201 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16); 2202 for (i = 8; i < 32; i++) 2203 cmd.req.arg[i] = 0; 2204 2205 err = qlcnic_issue_cmd(adapter, &cmd); 2206 2207 if (err != QLCNIC_RCODE_SUCCESS) { 2208 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n", 2209 err); 2210 err = -EIO; 2211 } 2212 2213 qlcnic_free_mbx_args(&cmd); 2214 2215 return err; 2216 } 2217 2218 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter, 2219 struct qlcnic_info *npar_info, u8 func_id) 2220 { 2221 int err; 2222 u32 temp; 2223 u8 op = 0; 2224 struct qlcnic_cmd_args cmd; 2225 struct qlcnic_hardware_context *ahw = adapter->ahw; 2226 2227 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO); 2228 if (err) 2229 return err; 2230 2231 if (func_id != ahw->pci_func) { 2232 temp = func_id << 16; 2233 cmd.req.arg[1] = op | BIT_31 | temp; 2234 } else { 2235 cmd.req.arg[1] = ahw->pci_func << 16; 2236 } 2237 err = qlcnic_issue_cmd(adapter, &cmd); 2238 if (err) { 2239 dev_info(&adapter->pdev->dev, 2240 "Failed to get nic info %d\n", err); 2241 goto out; 2242 } 2243 2244 npar_info->op_type = cmd.rsp.arg[1]; 2245 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF; 2246 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16; 2247 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF; 2248 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16; 2249 npar_info->capabilities = cmd.rsp.arg[4]; 2250 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF; 2251 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16; 2252 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF; 2253 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16; 2254 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF; 2255 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16; 2256 if (cmd.rsp.arg[8] & 0x1) 2257 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1; 2258 if (cmd.rsp.arg[8] & 0x10000) { 2259 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17; 2260 npar_info->max_linkspeed_reg_offset = temp; 2261 } 2262 2263 memcpy(ahw->extra_capability, &cmd.rsp.arg[16], 2264 sizeof(ahw->extra_capability)); 2265 2266 out: 2267 qlcnic_free_mbx_args(&cmd); 2268 return err; 2269 } 2270 2271 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter, 2272 struct qlcnic_pci_info *pci_info) 2273 { 2274 struct qlcnic_hardware_context *ahw = adapter->ahw; 2275 struct device *dev = &adapter->pdev->dev; 2276 struct qlcnic_cmd_args cmd; 2277 int i, err = 0, j = 0; 2278 u32 temp; 2279 2280 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO); 2281 if (err) 2282 return err; 2283 2284 err = qlcnic_issue_cmd(adapter, &cmd); 2285 2286 ahw->act_pci_func = 0; 2287 if (err == QLCNIC_RCODE_SUCCESS) { 2288 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF; 2289 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) { 2290 pci_info->id = cmd.rsp.arg[i] & 0xFFFF; 2291 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; 2292 i++; 2293 pci_info->type = cmd.rsp.arg[i] & 0xFFFF; 2294 if (pci_info->type == QLCNIC_TYPE_NIC) 2295 ahw->act_pci_func++; 2296 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; 2297 pci_info->default_port = temp; 2298 i++; 2299 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF; 2300 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; 2301 pci_info->tx_max_bw = temp; 2302 i = i + 2; 2303 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2); 2304 i++; 2305 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2); 2306 i = i + 3; 2307 } 2308 } else { 2309 dev_err(dev, "Failed to get PCI Info, error = %d\n", err); 2310 err = -EIO; 2311 } 2312 2313 qlcnic_free_mbx_args(&cmd); 2314 2315 return err; 2316 } 2317 2318 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type) 2319 { 2320 int i, index, err; 2321 u8 max_ints; 2322 u32 val, temp, type; 2323 struct qlcnic_cmd_args cmd; 2324 2325 max_ints = adapter->ahw->num_msix - 1; 2326 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT); 2327 if (err) 2328 return err; 2329 2330 cmd.req.arg[1] = max_ints; 2331 2332 if (qlcnic_sriov_vf_check(adapter)) 2333 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16; 2334 2335 for (i = 0, index = 2; i < max_ints; i++) { 2336 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL; 2337 val = type | (adapter->ahw->intr_tbl[i].type << 4); 2338 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX) 2339 val |= (adapter->ahw->intr_tbl[i].id << 16); 2340 cmd.req.arg[index++] = val; 2341 } 2342 err = qlcnic_issue_cmd(adapter, &cmd); 2343 if (err) { 2344 dev_err(&adapter->pdev->dev, 2345 "Failed to configure interrupts 0x%x\n", err); 2346 goto out; 2347 } 2348 2349 max_ints = cmd.rsp.arg[1]; 2350 for (i = 0, index = 2; i < max_ints; i++, index += 2) { 2351 val = cmd.rsp.arg[index]; 2352 if (LSB(val)) { 2353 dev_info(&adapter->pdev->dev, 2354 "Can't configure interrupt %d\n", 2355 adapter->ahw->intr_tbl[i].id); 2356 continue; 2357 } 2358 if (op_type) { 2359 adapter->ahw->intr_tbl[i].id = MSW(val); 2360 adapter->ahw->intr_tbl[i].enabled = 1; 2361 temp = cmd.rsp.arg[index + 1]; 2362 adapter->ahw->intr_tbl[i].src = temp; 2363 } else { 2364 adapter->ahw->intr_tbl[i].id = i; 2365 adapter->ahw->intr_tbl[i].enabled = 0; 2366 adapter->ahw->intr_tbl[i].src = 0; 2367 } 2368 } 2369 out: 2370 qlcnic_free_mbx_args(&cmd); 2371 return err; 2372 } 2373 2374 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter) 2375 { 2376 int id, timeout = 0; 2377 u32 status = 0; 2378 2379 while (status == 0) { 2380 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK); 2381 if (status) 2382 break; 2383 2384 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) { 2385 id = QLC_SHARED_REG_RD32(adapter, 2386 QLCNIC_FLASH_LOCK_OWNER); 2387 dev_err(&adapter->pdev->dev, 2388 "%s: failed, lock held by %d\n", __func__, id); 2389 return -EIO; 2390 } 2391 usleep_range(1000, 2000); 2392 } 2393 2394 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum); 2395 return 0; 2396 } 2397 2398 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter) 2399 { 2400 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK); 2401 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF); 2402 } 2403 2404 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter, 2405 u32 flash_addr, u8 *p_data, 2406 int count) 2407 { 2408 u32 word, range, flash_offset, addr = flash_addr, ret; 2409 ulong indirect_add, direct_window; 2410 int i, err = 0; 2411 2412 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1); 2413 if (addr & 0x3) { 2414 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr); 2415 return -EIO; 2416 } 2417 2418 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW, 2419 (addr)); 2420 2421 range = flash_offset + (count * sizeof(u32)); 2422 /* Check if data is spread across multiple sectors */ 2423 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) { 2424 2425 /* Multi sector read */ 2426 for (i = 0; i < count; i++) { 2427 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr); 2428 ret = QLCRD32(adapter, indirect_add, &err); 2429 if (err == -EIO) 2430 return err; 2431 2432 word = ret; 2433 *(u32 *)p_data = word; 2434 p_data = p_data + 4; 2435 addr = addr + 4; 2436 flash_offset = flash_offset + 4; 2437 2438 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) { 2439 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW; 2440 /* This write is needed once for each sector */ 2441 qlcnic_83xx_wrt_reg_indirect(adapter, 2442 direct_window, 2443 (addr)); 2444 flash_offset = 0; 2445 } 2446 } 2447 } else { 2448 /* Single sector read */ 2449 for (i = 0; i < count; i++) { 2450 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr); 2451 ret = QLCRD32(adapter, indirect_add, &err); 2452 if (err == -EIO) 2453 return err; 2454 2455 word = ret; 2456 *(u32 *)p_data = word; 2457 p_data = p_data + 4; 2458 addr = addr + 4; 2459 } 2460 } 2461 2462 return 0; 2463 } 2464 2465 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter) 2466 { 2467 u32 status; 2468 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT; 2469 int err = 0; 2470 2471 do { 2472 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err); 2473 if (err == -EIO) 2474 return err; 2475 2476 if ((status & QLC_83XX_FLASH_STATUS_READY) == 2477 QLC_83XX_FLASH_STATUS_READY) 2478 break; 2479 2480 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY); 2481 } while (--retries); 2482 2483 if (!retries) 2484 return -EIO; 2485 2486 return 0; 2487 } 2488 2489 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter) 2490 { 2491 int ret; 2492 u32 cmd; 2493 cmd = adapter->ahw->fdt.write_statusreg_cmd; 2494 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2495 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd)); 2496 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2497 adapter->ahw->fdt.write_enable_bits); 2498 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2499 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL); 2500 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2501 if (ret) 2502 return -EIO; 2503 2504 return 0; 2505 } 2506 2507 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter) 2508 { 2509 int ret; 2510 2511 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2512 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | 2513 adapter->ahw->fdt.write_statusreg_cmd)); 2514 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2515 adapter->ahw->fdt.write_disable_bits); 2516 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2517 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL); 2518 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2519 if (ret) 2520 return -EIO; 2521 2522 return 0; 2523 } 2524 2525 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter) 2526 { 2527 int ret, err = 0; 2528 u32 mfg_id; 2529 2530 if (qlcnic_83xx_lock_flash(adapter)) 2531 return -EIO; 2532 2533 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2534 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL); 2535 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2536 QLC_83XX_FLASH_READ_CTRL); 2537 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2538 if (ret) { 2539 qlcnic_83xx_unlock_flash(adapter); 2540 return -EIO; 2541 } 2542 2543 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err); 2544 if (err == -EIO) { 2545 qlcnic_83xx_unlock_flash(adapter); 2546 return err; 2547 } 2548 2549 adapter->flash_mfg_id = (mfg_id & 0xFF); 2550 qlcnic_83xx_unlock_flash(adapter); 2551 2552 return 0; 2553 } 2554 2555 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter) 2556 { 2557 int count, fdt_size, ret = 0; 2558 2559 fdt_size = sizeof(struct qlcnic_fdt); 2560 count = fdt_size / sizeof(u32); 2561 2562 if (qlcnic_83xx_lock_flash(adapter)) 2563 return -EIO; 2564 2565 memset(&adapter->ahw->fdt, 0, fdt_size); 2566 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION, 2567 (u8 *)&adapter->ahw->fdt, 2568 count); 2569 2570 qlcnic_83xx_unlock_flash(adapter); 2571 return ret; 2572 } 2573 2574 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter, 2575 u32 sector_start_addr) 2576 { 2577 u32 reversed_addr, addr1, addr2, cmd; 2578 int ret = -EIO; 2579 2580 if (qlcnic_83xx_lock_flash(adapter) != 0) 2581 return -EIO; 2582 2583 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) { 2584 ret = qlcnic_83xx_enable_flash_write(adapter); 2585 if (ret) { 2586 qlcnic_83xx_unlock_flash(adapter); 2587 dev_err(&adapter->pdev->dev, 2588 "%s failed at %d\n", 2589 __func__, __LINE__); 2590 return ret; 2591 } 2592 } 2593 2594 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2595 if (ret) { 2596 qlcnic_83xx_unlock_flash(adapter); 2597 dev_err(&adapter->pdev->dev, 2598 "%s: failed at %d\n", __func__, __LINE__); 2599 return -EIO; 2600 } 2601 2602 addr1 = (sector_start_addr & 0xFF) << 16; 2603 addr2 = (sector_start_addr & 0xFF0000) >> 16; 2604 reversed_addr = addr1 | addr2; 2605 2606 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2607 reversed_addr); 2608 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd; 2609 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) 2610 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd); 2611 else 2612 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2613 QLC_83XX_FLASH_OEM_ERASE_SIG); 2614 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2615 QLC_83XX_FLASH_LAST_ERASE_MS_VAL); 2616 2617 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2618 if (ret) { 2619 qlcnic_83xx_unlock_flash(adapter); 2620 dev_err(&adapter->pdev->dev, 2621 "%s: failed at %d\n", __func__, __LINE__); 2622 return -EIO; 2623 } 2624 2625 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) { 2626 ret = qlcnic_83xx_disable_flash_write(adapter); 2627 if (ret) { 2628 qlcnic_83xx_unlock_flash(adapter); 2629 dev_err(&adapter->pdev->dev, 2630 "%s: failed at %d\n", __func__, __LINE__); 2631 return ret; 2632 } 2633 } 2634 2635 qlcnic_83xx_unlock_flash(adapter); 2636 2637 return 0; 2638 } 2639 2640 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr, 2641 u32 *p_data) 2642 { 2643 int ret = -EIO; 2644 u32 addr1 = 0x00800000 | (addr >> 2); 2645 2646 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1); 2647 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data); 2648 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2649 QLC_83XX_FLASH_LAST_ERASE_MS_VAL); 2650 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2651 if (ret) { 2652 dev_err(&adapter->pdev->dev, 2653 "%s: failed at %d\n", __func__, __LINE__); 2654 return -EIO; 2655 } 2656 2657 return 0; 2658 } 2659 2660 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr, 2661 u32 *p_data, int count) 2662 { 2663 u32 temp; 2664 int ret = -EIO, err = 0; 2665 2666 if ((count < QLC_83XX_FLASH_WRITE_MIN) || 2667 (count > QLC_83XX_FLASH_WRITE_MAX)) { 2668 dev_err(&adapter->pdev->dev, 2669 "%s: Invalid word count\n", __func__); 2670 return -EIO; 2671 } 2672 2673 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err); 2674 if (err == -EIO) 2675 return err; 2676 2677 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL, 2678 (temp | QLC_83XX_FLASH_SPI_CTRL)); 2679 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2680 QLC_83XX_FLASH_ADDR_TEMP_VAL); 2681 2682 /* First DWORD write */ 2683 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++); 2684 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2685 QLC_83XX_FLASH_FIRST_MS_PATTERN); 2686 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2687 if (ret) { 2688 dev_err(&adapter->pdev->dev, 2689 "%s: failed at %d\n", __func__, __LINE__); 2690 return -EIO; 2691 } 2692 2693 count--; 2694 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2695 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL); 2696 /* Second to N-1 DWORD writes */ 2697 while (count != 1) { 2698 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2699 *p_data++); 2700 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2701 QLC_83XX_FLASH_SECOND_MS_PATTERN); 2702 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2703 if (ret) { 2704 dev_err(&adapter->pdev->dev, 2705 "%s: failed at %d\n", __func__, __LINE__); 2706 return -EIO; 2707 } 2708 count--; 2709 } 2710 2711 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2712 QLC_83XX_FLASH_ADDR_TEMP_VAL | 2713 (addr >> 2)); 2714 /* Last DWORD write */ 2715 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++); 2716 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2717 QLC_83XX_FLASH_LAST_MS_PATTERN); 2718 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2719 if (ret) { 2720 dev_err(&adapter->pdev->dev, 2721 "%s: failed at %d\n", __func__, __LINE__); 2722 return -EIO; 2723 } 2724 2725 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err); 2726 if (err == -EIO) 2727 return err; 2728 2729 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) { 2730 dev_err(&adapter->pdev->dev, "%s: failed at %d\n", 2731 __func__, __LINE__); 2732 /* Operation failed, clear error bit */ 2733 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err); 2734 if (err == -EIO) 2735 return err; 2736 2737 qlcnic_83xx_wrt_reg_indirect(adapter, 2738 QLC_83XX_FLASH_SPI_CONTROL, 2739 (temp | QLC_83XX_FLASH_SPI_CTRL)); 2740 } 2741 2742 return 0; 2743 } 2744 2745 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter) 2746 { 2747 u32 val, id; 2748 2749 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK); 2750 2751 /* Check if recovery need to be performed by the calling function */ 2752 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) { 2753 val = val & ~0x3F; 2754 val = val | ((adapter->portnum << 2) | 2755 QLC_83XX_NEED_DRV_LOCK_RECOVERY); 2756 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); 2757 dev_info(&adapter->pdev->dev, 2758 "%s: lock recovery initiated\n", __func__); 2759 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY); 2760 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK); 2761 id = ((val >> 2) & 0xF); 2762 if (id == adapter->portnum) { 2763 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK; 2764 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS; 2765 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); 2766 /* Force release the lock */ 2767 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK); 2768 /* Clear recovery bits */ 2769 val = val & ~0x3F; 2770 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); 2771 dev_info(&adapter->pdev->dev, 2772 "%s: lock recovery completed\n", __func__); 2773 } else { 2774 dev_info(&adapter->pdev->dev, 2775 "%s: func %d to resume lock recovery process\n", 2776 __func__, id); 2777 } 2778 } else { 2779 dev_info(&adapter->pdev->dev, 2780 "%s: lock recovery initiated by other functions\n", 2781 __func__); 2782 } 2783 } 2784 2785 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter) 2786 { 2787 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0; 2788 int max_attempt = 0; 2789 2790 while (status == 0) { 2791 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK); 2792 if (status) 2793 break; 2794 2795 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY); 2796 i++; 2797 2798 if (i == 1) 2799 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 2800 2801 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) { 2802 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 2803 if (val == temp) { 2804 id = val & 0xFF; 2805 dev_info(&adapter->pdev->dev, 2806 "%s: lock to be recovered from %d\n", 2807 __func__, id); 2808 qlcnic_83xx_recover_driver_lock(adapter); 2809 i = 0; 2810 max_attempt++; 2811 } else { 2812 dev_err(&adapter->pdev->dev, 2813 "%s: failed to get lock\n", __func__); 2814 return -EIO; 2815 } 2816 } 2817 2818 /* Force exit from while loop after few attempts */ 2819 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) { 2820 dev_err(&adapter->pdev->dev, 2821 "%s: failed to get lock\n", __func__); 2822 return -EIO; 2823 } 2824 } 2825 2826 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 2827 lock_alive_counter = val >> 8; 2828 lock_alive_counter++; 2829 val = lock_alive_counter << 8 | adapter->portnum; 2830 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val); 2831 2832 return 0; 2833 } 2834 2835 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter) 2836 { 2837 u32 val, lock_alive_counter, id; 2838 2839 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 2840 id = val & 0xFF; 2841 lock_alive_counter = val >> 8; 2842 2843 if (id != adapter->portnum) 2844 dev_err(&adapter->pdev->dev, 2845 "%s:Warning func %d is unlocking lock owned by %d\n", 2846 __func__, adapter->portnum, id); 2847 2848 val = (lock_alive_counter << 8) | 0xFF; 2849 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val); 2850 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK); 2851 } 2852 2853 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr, 2854 u32 *data, u32 count) 2855 { 2856 int i, j, ret = 0; 2857 u32 temp; 2858 int err = 0; 2859 2860 /* Check alignment */ 2861 if (addr & 0xF) 2862 return -EIO; 2863 2864 mutex_lock(&adapter->ahw->mem_lock); 2865 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0); 2866 2867 for (i = 0; i < count; i++, addr += 16) { 2868 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET, 2869 QLCNIC_ADDR_QDR_NET_MAX)) || 2870 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET, 2871 QLCNIC_ADDR_DDR_NET_MAX)))) { 2872 mutex_unlock(&adapter->ahw->mem_lock); 2873 return -EIO; 2874 } 2875 2876 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr); 2877 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO, 2878 *data++); 2879 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI, 2880 *data++); 2881 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO, 2882 *data++); 2883 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI, 2884 *data++); 2885 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL, 2886 QLCNIC_TA_WRITE_ENABLE); 2887 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL, 2888 QLCNIC_TA_WRITE_START); 2889 2890 for (j = 0; j < MAX_CTL_CHECK; j++) { 2891 temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err); 2892 if (err == -EIO) { 2893 mutex_unlock(&adapter->ahw->mem_lock); 2894 return err; 2895 } 2896 2897 if ((temp & TA_CTL_BUSY) == 0) 2898 break; 2899 } 2900 2901 /* Status check failure */ 2902 if (j >= MAX_CTL_CHECK) { 2903 printk_ratelimited(KERN_WARNING 2904 "MS memory write failed\n"); 2905 mutex_unlock(&adapter->ahw->mem_lock); 2906 return -EIO; 2907 } 2908 } 2909 2910 mutex_unlock(&adapter->ahw->mem_lock); 2911 2912 return ret; 2913 } 2914 2915 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr, 2916 u8 *p_data, int count) 2917 { 2918 u32 word, addr = flash_addr, ret; 2919 ulong indirect_addr; 2920 int i, err = 0; 2921 2922 if (qlcnic_83xx_lock_flash(adapter) != 0) 2923 return -EIO; 2924 2925 if (addr & 0x3) { 2926 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr); 2927 qlcnic_83xx_unlock_flash(adapter); 2928 return -EIO; 2929 } 2930 2931 for (i = 0; i < count; i++) { 2932 if (qlcnic_83xx_wrt_reg_indirect(adapter, 2933 QLC_83XX_FLASH_DIRECT_WINDOW, 2934 (addr))) { 2935 qlcnic_83xx_unlock_flash(adapter); 2936 return -EIO; 2937 } 2938 2939 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr); 2940 ret = QLCRD32(adapter, indirect_addr, &err); 2941 if (err == -EIO) 2942 return err; 2943 2944 word = ret; 2945 *(u32 *)p_data = word; 2946 p_data = p_data + 4; 2947 addr = addr + 4; 2948 } 2949 2950 qlcnic_83xx_unlock_flash(adapter); 2951 2952 return 0; 2953 } 2954 2955 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter) 2956 { 2957 u8 pci_func; 2958 int err; 2959 u32 config = 0, state; 2960 struct qlcnic_cmd_args cmd; 2961 struct qlcnic_hardware_context *ahw = adapter->ahw; 2962 2963 if (qlcnic_sriov_vf_check(adapter)) 2964 pci_func = adapter->portnum; 2965 else 2966 pci_func = ahw->pci_func; 2967 2968 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func)); 2969 if (!QLC_83xx_FUNC_VAL(state, pci_func)) { 2970 dev_info(&adapter->pdev->dev, "link state down\n"); 2971 return config; 2972 } 2973 2974 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS); 2975 if (err) 2976 return err; 2977 2978 err = qlcnic_issue_cmd(adapter, &cmd); 2979 if (err) { 2980 dev_info(&adapter->pdev->dev, 2981 "Get Link Status Command failed: 0x%x\n", err); 2982 goto out; 2983 } else { 2984 config = cmd.rsp.arg[1]; 2985 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) { 2986 case QLC_83XX_10M_LINK: 2987 ahw->link_speed = SPEED_10; 2988 break; 2989 case QLC_83XX_100M_LINK: 2990 ahw->link_speed = SPEED_100; 2991 break; 2992 case QLC_83XX_1G_LINK: 2993 ahw->link_speed = SPEED_1000; 2994 break; 2995 case QLC_83XX_10G_LINK: 2996 ahw->link_speed = SPEED_10000; 2997 break; 2998 default: 2999 ahw->link_speed = 0; 3000 break; 3001 } 3002 config = cmd.rsp.arg[3]; 3003 if (QLC_83XX_SFP_PRESENT(config)) { 3004 switch (ahw->module_type) { 3005 case LINKEVENT_MODULE_OPTICAL_UNKNOWN: 3006 case LINKEVENT_MODULE_OPTICAL_SRLR: 3007 case LINKEVENT_MODULE_OPTICAL_LRM: 3008 case LINKEVENT_MODULE_OPTICAL_SFP_1G: 3009 ahw->supported_type = PORT_FIBRE; 3010 break; 3011 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE: 3012 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN: 3013 case LINKEVENT_MODULE_TWINAX: 3014 ahw->supported_type = PORT_TP; 3015 break; 3016 default: 3017 ahw->supported_type = PORT_OTHER; 3018 } 3019 } 3020 if (config & 1) 3021 err = 1; 3022 } 3023 out: 3024 qlcnic_free_mbx_args(&cmd); 3025 return config; 3026 } 3027 3028 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter, 3029 struct ethtool_cmd *ecmd) 3030 { 3031 u32 config = 0; 3032 int status = 0; 3033 struct qlcnic_hardware_context *ahw = adapter->ahw; 3034 3035 if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) { 3036 /* Get port configuration info */ 3037 status = qlcnic_83xx_get_port_info(adapter); 3038 /* Get Link Status related info */ 3039 config = qlcnic_83xx_test_link(adapter); 3040 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config); 3041 } 3042 3043 /* hard code until there is a way to get it from flash */ 3044 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G; 3045 3046 if (netif_running(adapter->netdev) && ahw->has_link_events) { 3047 ethtool_cmd_speed_set(ecmd, ahw->link_speed); 3048 ecmd->duplex = ahw->link_duplex; 3049 ecmd->autoneg = ahw->link_autoneg; 3050 } else { 3051 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); 3052 ecmd->duplex = DUPLEX_UNKNOWN; 3053 ecmd->autoneg = AUTONEG_DISABLE; 3054 } 3055 3056 if (ahw->port_type == QLCNIC_XGBE) { 3057 ecmd->supported = SUPPORTED_10000baseT_Full; 3058 ecmd->advertising = ADVERTISED_10000baseT_Full; 3059 } else { 3060 ecmd->supported = (SUPPORTED_10baseT_Half | 3061 SUPPORTED_10baseT_Full | 3062 SUPPORTED_100baseT_Half | 3063 SUPPORTED_100baseT_Full | 3064 SUPPORTED_1000baseT_Half | 3065 SUPPORTED_1000baseT_Full); 3066 ecmd->advertising = (ADVERTISED_100baseT_Half | 3067 ADVERTISED_100baseT_Full | 3068 ADVERTISED_1000baseT_Half | 3069 ADVERTISED_1000baseT_Full); 3070 } 3071 3072 switch (ahw->supported_type) { 3073 case PORT_FIBRE: 3074 ecmd->supported |= SUPPORTED_FIBRE; 3075 ecmd->advertising |= ADVERTISED_FIBRE; 3076 ecmd->port = PORT_FIBRE; 3077 ecmd->transceiver = XCVR_EXTERNAL; 3078 break; 3079 case PORT_TP: 3080 ecmd->supported |= SUPPORTED_TP; 3081 ecmd->advertising |= ADVERTISED_TP; 3082 ecmd->port = PORT_TP; 3083 ecmd->transceiver = XCVR_INTERNAL; 3084 break; 3085 default: 3086 ecmd->supported |= SUPPORTED_FIBRE; 3087 ecmd->advertising |= ADVERTISED_FIBRE; 3088 ecmd->port = PORT_OTHER; 3089 ecmd->transceiver = XCVR_EXTERNAL; 3090 break; 3091 } 3092 ecmd->phy_address = ahw->physical_port; 3093 return status; 3094 } 3095 3096 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter, 3097 struct ethtool_cmd *ecmd) 3098 { 3099 int status = 0; 3100 u32 config = adapter->ahw->port_config; 3101 3102 if (ecmd->autoneg) 3103 adapter->ahw->port_config |= BIT_15; 3104 3105 switch (ethtool_cmd_speed(ecmd)) { 3106 case SPEED_10: 3107 adapter->ahw->port_config |= BIT_8; 3108 break; 3109 case SPEED_100: 3110 adapter->ahw->port_config |= BIT_9; 3111 break; 3112 case SPEED_1000: 3113 adapter->ahw->port_config |= BIT_10; 3114 break; 3115 case SPEED_10000: 3116 adapter->ahw->port_config |= BIT_11; 3117 break; 3118 default: 3119 return -EINVAL; 3120 } 3121 3122 status = qlcnic_83xx_set_port_config(adapter); 3123 if (status) { 3124 dev_info(&adapter->pdev->dev, 3125 "Failed to Set Link Speed and autoneg.\n"); 3126 adapter->ahw->port_config = config; 3127 } 3128 return status; 3129 } 3130 3131 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd, 3132 u64 *data, int index) 3133 { 3134 u32 low, hi; 3135 u64 val; 3136 3137 low = cmd->rsp.arg[index]; 3138 hi = cmd->rsp.arg[index + 1]; 3139 val = (((u64) low) | (((u64) hi) << 32)); 3140 *data++ = val; 3141 return data; 3142 } 3143 3144 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter, 3145 struct qlcnic_cmd_args *cmd, u64 *data, 3146 int type, int *ret) 3147 { 3148 int err, k, total_regs; 3149 3150 *ret = 0; 3151 err = qlcnic_issue_cmd(adapter, cmd); 3152 if (err != QLCNIC_RCODE_SUCCESS) { 3153 dev_info(&adapter->pdev->dev, 3154 "Error in get statistics mailbox command\n"); 3155 *ret = -EIO; 3156 return data; 3157 } 3158 total_regs = cmd->rsp.num; 3159 switch (type) { 3160 case QLC_83XX_STAT_MAC: 3161 /* fill in MAC tx counters */ 3162 for (k = 2; k < 28; k += 2) 3163 data = qlcnic_83xx_copy_stats(cmd, data, k); 3164 /* skip 24 bytes of reserved area */ 3165 /* fill in MAC rx counters */ 3166 for (k += 6; k < 60; k += 2) 3167 data = qlcnic_83xx_copy_stats(cmd, data, k); 3168 /* skip 24 bytes of reserved area */ 3169 /* fill in MAC rx frame stats */ 3170 for (k += 6; k < 80; k += 2) 3171 data = qlcnic_83xx_copy_stats(cmd, data, k); 3172 /* fill in eSwitch stats */ 3173 for (; k < total_regs; k += 2) 3174 data = qlcnic_83xx_copy_stats(cmd, data, k); 3175 break; 3176 case QLC_83XX_STAT_RX: 3177 for (k = 2; k < 8; k += 2) 3178 data = qlcnic_83xx_copy_stats(cmd, data, k); 3179 /* skip 8 bytes of reserved data */ 3180 for (k += 2; k < 24; k += 2) 3181 data = qlcnic_83xx_copy_stats(cmd, data, k); 3182 /* skip 8 bytes containing RE1FBQ error data */ 3183 for (k += 2; k < total_regs; k += 2) 3184 data = qlcnic_83xx_copy_stats(cmd, data, k); 3185 break; 3186 case QLC_83XX_STAT_TX: 3187 for (k = 2; k < 10; k += 2) 3188 data = qlcnic_83xx_copy_stats(cmd, data, k); 3189 /* skip 8 bytes of reserved data */ 3190 for (k += 2; k < total_regs; k += 2) 3191 data = qlcnic_83xx_copy_stats(cmd, data, k); 3192 break; 3193 default: 3194 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n"); 3195 *ret = -EIO; 3196 } 3197 return data; 3198 } 3199 3200 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data) 3201 { 3202 struct qlcnic_cmd_args cmd; 3203 struct net_device *netdev = adapter->netdev; 3204 int ret = 0; 3205 3206 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS); 3207 if (ret) 3208 return; 3209 /* Get Tx stats */ 3210 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16); 3211 cmd.rsp.num = QLC_83XX_TX_STAT_REGS; 3212 data = qlcnic_83xx_fill_stats(adapter, &cmd, data, 3213 QLC_83XX_STAT_TX, &ret); 3214 if (ret) { 3215 netdev_err(netdev, "Error getting Tx stats\n"); 3216 goto out; 3217 } 3218 /* Get MAC stats */ 3219 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16); 3220 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS; 3221 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num); 3222 data = qlcnic_83xx_fill_stats(adapter, &cmd, data, 3223 QLC_83XX_STAT_MAC, &ret); 3224 if (ret) { 3225 netdev_err(netdev, "Error getting MAC stats\n"); 3226 goto out; 3227 } 3228 /* Get Rx stats */ 3229 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16; 3230 cmd.rsp.num = QLC_83XX_RX_STAT_REGS; 3231 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num); 3232 data = qlcnic_83xx_fill_stats(adapter, &cmd, data, 3233 QLC_83XX_STAT_RX, &ret); 3234 if (ret) 3235 netdev_err(netdev, "Error getting Rx stats\n"); 3236 out: 3237 qlcnic_free_mbx_args(&cmd); 3238 } 3239 3240 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter) 3241 { 3242 u32 major, minor, sub; 3243 3244 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR); 3245 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR); 3246 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB); 3247 3248 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) { 3249 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n", 3250 __func__); 3251 return 1; 3252 } 3253 return 0; 3254 } 3255 3256 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter) 3257 { 3258 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) * 3259 sizeof(*adapter->ahw->ext_reg_tbl)) + 3260 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) * 3261 sizeof(*adapter->ahw->reg_tbl)); 3262 } 3263 3264 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff) 3265 { 3266 int i, j = 0; 3267 3268 for (i = QLCNIC_DEV_INFO_SIZE + 1; 3269 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++) 3270 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j); 3271 3272 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++) 3273 regs_buff[i++] = QLCRDX(adapter->ahw, j); 3274 return i; 3275 } 3276 3277 int qlcnic_83xx_interrupt_test(struct net_device *netdev) 3278 { 3279 struct qlcnic_adapter *adapter = netdev_priv(netdev); 3280 struct qlcnic_hardware_context *ahw = adapter->ahw; 3281 struct qlcnic_cmd_args cmd; 3282 u8 val, drv_sds_rings = adapter->drv_sds_rings; 3283 u8 drv_tx_rings = adapter->drv_tx_rings; 3284 u32 data; 3285 u16 intrpt_id, id; 3286 int ret; 3287 3288 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 3289 netdev_info(netdev, "Device is resetting\n"); 3290 return -EBUSY; 3291 } 3292 3293 if (qlcnic_get_diag_lock(adapter)) { 3294 netdev_info(netdev, "Device in diagnostics mode\n"); 3295 return -EBUSY; 3296 } 3297 3298 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST, 3299 drv_sds_rings); 3300 if (ret) 3301 goto fail_diag_irq; 3302 3303 ahw->diag_cnt = 0; 3304 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST); 3305 if (ret) 3306 goto fail_diag_irq; 3307 3308 if (adapter->flags & QLCNIC_MSIX_ENABLED) 3309 intrpt_id = ahw->intr_tbl[0].id; 3310 else 3311 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 3312 3313 cmd.req.arg[1] = 1; 3314 cmd.req.arg[2] = intrpt_id; 3315 cmd.req.arg[3] = BIT_0; 3316 3317 ret = qlcnic_issue_cmd(adapter, &cmd); 3318 data = cmd.rsp.arg[2]; 3319 id = LSW(data); 3320 val = LSB(MSW(data)); 3321 if (id != intrpt_id) 3322 dev_info(&adapter->pdev->dev, 3323 "Interrupt generated: 0x%x, requested:0x%x\n", 3324 id, intrpt_id); 3325 if (val) 3326 dev_err(&adapter->pdev->dev, 3327 "Interrupt test error: 0x%x\n", val); 3328 if (ret) 3329 goto done; 3330 3331 msleep(20); 3332 ret = !ahw->diag_cnt; 3333 3334 done: 3335 qlcnic_free_mbx_args(&cmd); 3336 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings); 3337 3338 fail_diag_irq: 3339 adapter->drv_sds_rings = drv_sds_rings; 3340 adapter->drv_tx_rings = drv_tx_rings; 3341 qlcnic_release_diag_lock(adapter); 3342 return ret; 3343 } 3344 3345 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter, 3346 struct ethtool_pauseparam *pause) 3347 { 3348 struct qlcnic_hardware_context *ahw = adapter->ahw; 3349 int status = 0; 3350 u32 config; 3351 3352 status = qlcnic_83xx_get_port_config(adapter); 3353 if (status) { 3354 dev_err(&adapter->pdev->dev, 3355 "%s: Get Pause Config failed\n", __func__); 3356 return; 3357 } 3358 config = ahw->port_config; 3359 if (config & QLC_83XX_CFG_STD_PAUSE) { 3360 switch (MSW(config)) { 3361 case QLC_83XX_TX_PAUSE: 3362 pause->tx_pause = 1; 3363 break; 3364 case QLC_83XX_RX_PAUSE: 3365 pause->rx_pause = 1; 3366 break; 3367 case QLC_83XX_TX_RX_PAUSE: 3368 default: 3369 /* Backward compatibility for existing 3370 * flash definitions 3371 */ 3372 pause->tx_pause = 1; 3373 pause->rx_pause = 1; 3374 } 3375 } 3376 3377 if (QLC_83XX_AUTONEG(config)) 3378 pause->autoneg = 1; 3379 } 3380 3381 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter, 3382 struct ethtool_pauseparam *pause) 3383 { 3384 struct qlcnic_hardware_context *ahw = adapter->ahw; 3385 int status = 0; 3386 u32 config; 3387 3388 status = qlcnic_83xx_get_port_config(adapter); 3389 if (status) { 3390 dev_err(&adapter->pdev->dev, 3391 "%s: Get Pause Config failed.\n", __func__); 3392 return status; 3393 } 3394 config = ahw->port_config; 3395 3396 if (ahw->port_type == QLCNIC_GBE) { 3397 if (pause->autoneg) 3398 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG; 3399 if (!pause->autoneg) 3400 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG; 3401 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) { 3402 return -EOPNOTSUPP; 3403 } 3404 3405 if (!(config & QLC_83XX_CFG_STD_PAUSE)) 3406 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE; 3407 3408 if (pause->rx_pause && pause->tx_pause) { 3409 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE; 3410 } else if (pause->rx_pause && !pause->tx_pause) { 3411 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE; 3412 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE; 3413 } else if (pause->tx_pause && !pause->rx_pause) { 3414 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE; 3415 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE; 3416 } else if (!pause->rx_pause && !pause->tx_pause) { 3417 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE | 3418 QLC_83XX_CFG_STD_PAUSE); 3419 } 3420 status = qlcnic_83xx_set_port_config(adapter); 3421 if (status) { 3422 dev_err(&adapter->pdev->dev, 3423 "%s: Set Pause Config failed.\n", __func__); 3424 ahw->port_config = config; 3425 } 3426 return status; 3427 } 3428 3429 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter) 3430 { 3431 int ret, err = 0; 3432 u32 temp; 3433 3434 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 3435 QLC_83XX_FLASH_OEM_READ_SIG); 3436 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 3437 QLC_83XX_FLASH_READ_CTRL); 3438 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 3439 if (ret) 3440 return -EIO; 3441 3442 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err); 3443 if (err == -EIO) 3444 return err; 3445 3446 return temp & 0xFF; 3447 } 3448 3449 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter) 3450 { 3451 int status; 3452 3453 status = qlcnic_83xx_read_flash_status_reg(adapter); 3454 if (status == -EIO) { 3455 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n", 3456 __func__); 3457 return 1; 3458 } 3459 return 0; 3460 } 3461 3462 int qlcnic_83xx_shutdown(struct pci_dev *pdev) 3463 { 3464 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 3465 struct net_device *netdev = adapter->netdev; 3466 int retval; 3467 3468 netif_device_detach(netdev); 3469 qlcnic_cancel_idc_work(adapter); 3470 3471 if (netif_running(netdev)) 3472 qlcnic_down(adapter, netdev); 3473 3474 qlcnic_83xx_disable_mbx_intr(adapter); 3475 cancel_delayed_work_sync(&adapter->idc_aen_work); 3476 3477 retval = pci_save_state(pdev); 3478 if (retval) 3479 return retval; 3480 3481 return 0; 3482 } 3483 3484 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter) 3485 { 3486 struct qlcnic_hardware_context *ahw = adapter->ahw; 3487 struct qlc_83xx_idc *idc = &ahw->idc; 3488 int err = 0; 3489 3490 err = qlcnic_83xx_idc_init(adapter); 3491 if (err) 3492 return err; 3493 3494 if (ahw->nic_mode == QLCNIC_VNIC_MODE) { 3495 if (ahw->op_mode == QLCNIC_MGMT_FUNC) { 3496 qlcnic_83xx_set_vnic_opmode(adapter); 3497 } else { 3498 err = qlcnic_83xx_check_vnic_state(adapter); 3499 if (err) 3500 return err; 3501 } 3502 } 3503 3504 err = qlcnic_83xx_idc_reattach_driver(adapter); 3505 if (err) 3506 return err; 3507 3508 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 3509 idc->delay); 3510 return err; 3511 } 3512 3513 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx) 3514 { 3515 reinit_completion(&mbx->completion); 3516 set_bit(QLC_83XX_MBX_READY, &mbx->status); 3517 } 3518 3519 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx) 3520 { 3521 if (!mbx) 3522 return; 3523 3524 destroy_workqueue(mbx->work_q); 3525 kfree(mbx); 3526 } 3527 3528 static inline void 3529 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter, 3530 struct qlcnic_cmd_args *cmd) 3531 { 3532 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED); 3533 3534 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) { 3535 qlcnic_free_mbx_args(cmd); 3536 kfree(cmd); 3537 return; 3538 } 3539 complete(&cmd->completion); 3540 } 3541 3542 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter) 3543 { 3544 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3545 struct list_head *head = &mbx->cmd_q; 3546 struct qlcnic_cmd_args *cmd = NULL; 3547 3548 spin_lock(&mbx->queue_lock); 3549 3550 while (!list_empty(head)) { 3551 cmd = list_entry(head->next, struct qlcnic_cmd_args, list); 3552 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n", 3553 __func__, cmd->cmd_op); 3554 list_del(&cmd->list); 3555 mbx->num_cmds--; 3556 qlcnic_83xx_notify_cmd_completion(adapter, cmd); 3557 } 3558 3559 spin_unlock(&mbx->queue_lock); 3560 } 3561 3562 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter) 3563 { 3564 struct qlcnic_hardware_context *ahw = adapter->ahw; 3565 struct qlcnic_mailbox *mbx = ahw->mailbox; 3566 u32 host_mbx_ctrl; 3567 3568 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) 3569 return -EBUSY; 3570 3571 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL); 3572 if (host_mbx_ctrl) { 3573 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 3574 ahw->idc.collect_dump = 1; 3575 return -EIO; 3576 } 3577 3578 return 0; 3579 } 3580 3581 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter, 3582 u8 issue_cmd) 3583 { 3584 if (issue_cmd) 3585 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER); 3586 else 3587 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER); 3588 } 3589 3590 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter, 3591 struct qlcnic_cmd_args *cmd) 3592 { 3593 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3594 3595 spin_lock(&mbx->queue_lock); 3596 3597 list_del(&cmd->list); 3598 mbx->num_cmds--; 3599 3600 spin_unlock(&mbx->queue_lock); 3601 3602 qlcnic_83xx_notify_cmd_completion(adapter, cmd); 3603 } 3604 3605 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter, 3606 struct qlcnic_cmd_args *cmd) 3607 { 3608 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp; 3609 struct qlcnic_hardware_context *ahw = adapter->ahw; 3610 int i, j; 3611 3612 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) { 3613 mbx_cmd = cmd->req.arg[0]; 3614 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0)); 3615 for (i = 1; i < cmd->req.num; i++) 3616 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i)); 3617 } else { 3618 fw_hal_version = ahw->fw_hal_version; 3619 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32); 3620 total_size = cmd->pay_size + hdr_size; 3621 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16; 3622 mbx_cmd = tmp | fw_hal_version << 29; 3623 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0)); 3624 3625 /* Back channel specific operations bits */ 3626 mbx_cmd = 0x1 | 1 << 4; 3627 3628 if (qlcnic_sriov_pf_check(adapter)) 3629 mbx_cmd |= cmd->func_num << 5; 3630 3631 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1)); 3632 3633 for (i = 2, j = 0; j < hdr_size; i++, j++) 3634 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i)); 3635 for (j = 0; j < cmd->pay_size; j++, i++) 3636 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i)); 3637 } 3638 } 3639 3640 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter) 3641 { 3642 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3643 3644 if (!mbx) 3645 return; 3646 3647 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 3648 complete(&mbx->completion); 3649 cancel_work_sync(&mbx->work); 3650 flush_workqueue(mbx->work_q); 3651 qlcnic_83xx_flush_mbx_queue(adapter); 3652 } 3653 3654 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter, 3655 struct qlcnic_cmd_args *cmd, 3656 unsigned long *timeout) 3657 { 3658 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3659 3660 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) { 3661 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT); 3662 init_completion(&cmd->completion); 3663 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN; 3664 3665 spin_lock(&mbx->queue_lock); 3666 3667 list_add_tail(&cmd->list, &mbx->cmd_q); 3668 mbx->num_cmds++; 3669 cmd->total_cmds = mbx->num_cmds; 3670 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT; 3671 queue_work(mbx->work_q, &mbx->work); 3672 3673 spin_unlock(&mbx->queue_lock); 3674 3675 return 0; 3676 } 3677 3678 return -EBUSY; 3679 } 3680 3681 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter, 3682 struct qlcnic_cmd_args *cmd) 3683 { 3684 u8 mac_cmd_rcode; 3685 u32 fw_data; 3686 3687 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) { 3688 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2)); 3689 mac_cmd_rcode = (u8)fw_data; 3690 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE || 3691 mac_cmd_rcode == QLC_83XX_MAC_PRESENT || 3692 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) { 3693 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS; 3694 return QLCNIC_RCODE_SUCCESS; 3695 } 3696 } 3697 3698 return -EINVAL; 3699 } 3700 3701 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter, 3702 struct qlcnic_cmd_args *cmd) 3703 { 3704 struct qlcnic_hardware_context *ahw = adapter->ahw; 3705 struct device *dev = &adapter->pdev->dev; 3706 u8 mbx_err_code; 3707 u32 fw_data; 3708 3709 fw_data = readl(QLCNIC_MBX_FW(ahw, 0)); 3710 mbx_err_code = QLCNIC_MBX_STATUS(fw_data); 3711 qlcnic_83xx_get_mbx_data(adapter, cmd); 3712 3713 switch (mbx_err_code) { 3714 case QLCNIC_MBX_RSP_OK: 3715 case QLCNIC_MBX_PORT_RSP_OK: 3716 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS; 3717 break; 3718 default: 3719 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd)) 3720 break; 3721 3722 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n", 3723 __func__, cmd->cmd_op, cmd->type, ahw->pci_func, 3724 ahw->op_mode, mbx_err_code); 3725 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED; 3726 qlcnic_dump_mbx(adapter, cmd); 3727 } 3728 3729 return; 3730 } 3731 3732 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter) 3733 { 3734 struct qlcnic_hardware_context *ahw = adapter->ahw; 3735 u32 offset; 3736 3737 offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK); 3738 dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x", 3739 readl(ahw->pci_base0 + offset), 3740 QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL), 3741 QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL), 3742 QLCRDX(ahw, QLCNIC_FW_MBX_CTRL)); 3743 } 3744 3745 static void qlcnic_83xx_mailbox_worker(struct work_struct *work) 3746 { 3747 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox, 3748 work); 3749 struct qlcnic_adapter *adapter = mbx->adapter; 3750 struct qlcnic_mbx_ops *mbx_ops = mbx->ops; 3751 struct device *dev = &adapter->pdev->dev; 3752 atomic_t *rsp_status = &mbx->rsp_status; 3753 struct list_head *head = &mbx->cmd_q; 3754 struct qlcnic_hardware_context *ahw; 3755 struct qlcnic_cmd_args *cmd = NULL; 3756 3757 ahw = adapter->ahw; 3758 3759 while (true) { 3760 if (qlcnic_83xx_check_mbx_status(adapter)) { 3761 qlcnic_83xx_flush_mbx_queue(adapter); 3762 return; 3763 } 3764 3765 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT); 3766 3767 spin_lock(&mbx->queue_lock); 3768 3769 if (list_empty(head)) { 3770 spin_unlock(&mbx->queue_lock); 3771 return; 3772 } 3773 cmd = list_entry(head->next, struct qlcnic_cmd_args, list); 3774 3775 spin_unlock(&mbx->queue_lock); 3776 3777 mbx_ops->encode_cmd(adapter, cmd); 3778 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST); 3779 3780 if (wait_for_completion_timeout(&mbx->completion, 3781 QLC_83XX_MBX_TIMEOUT)) { 3782 mbx_ops->decode_resp(adapter, cmd); 3783 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION); 3784 } else { 3785 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n", 3786 __func__, cmd->cmd_op, cmd->type, ahw->pci_func, 3787 ahw->op_mode); 3788 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 3789 qlcnic_dump_mailbox_registers(adapter); 3790 qlcnic_83xx_get_mbx_data(adapter, cmd); 3791 qlcnic_dump_mbx(adapter, cmd); 3792 qlcnic_83xx_idc_request_reset(adapter, 3793 QLCNIC_FORCE_FW_DUMP_KEY); 3794 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT; 3795 } 3796 mbx_ops->dequeue_cmd(adapter, cmd); 3797 } 3798 } 3799 3800 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = { 3801 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd, 3802 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd, 3803 .decode_resp = qlcnic_83xx_decode_mbx_rsp, 3804 .encode_cmd = qlcnic_83xx_encode_mbx_cmd, 3805 .nofity_fw = qlcnic_83xx_signal_mbx_cmd, 3806 }; 3807 3808 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter) 3809 { 3810 struct qlcnic_hardware_context *ahw = adapter->ahw; 3811 struct qlcnic_mailbox *mbx; 3812 3813 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL); 3814 if (!ahw->mailbox) 3815 return -ENOMEM; 3816 3817 mbx = ahw->mailbox; 3818 mbx->ops = &qlcnic_83xx_mbx_ops; 3819 mbx->adapter = adapter; 3820 3821 spin_lock_init(&mbx->queue_lock); 3822 spin_lock_init(&mbx->aen_lock); 3823 INIT_LIST_HEAD(&mbx->cmd_q); 3824 init_completion(&mbx->completion); 3825 3826 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox"); 3827 if (mbx->work_q == NULL) { 3828 kfree(mbx); 3829 return -ENOMEM; 3830 } 3831 3832 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker); 3833 set_bit(QLC_83XX_MBX_READY, &mbx->status); 3834 return 0; 3835 } 3836 3837 pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev, 3838 pci_channel_state_t state) 3839 { 3840 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 3841 3842 if (state == pci_channel_io_perm_failure) 3843 return PCI_ERS_RESULT_DISCONNECT; 3844 3845 if (state == pci_channel_io_normal) 3846 return PCI_ERS_RESULT_RECOVERED; 3847 3848 set_bit(__QLCNIC_AER, &adapter->state); 3849 set_bit(__QLCNIC_RESETTING, &adapter->state); 3850 3851 qlcnic_83xx_aer_stop_poll_work(adapter); 3852 3853 pci_save_state(pdev); 3854 pci_disable_device(pdev); 3855 3856 return PCI_ERS_RESULT_NEED_RESET; 3857 } 3858 3859 pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev) 3860 { 3861 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 3862 int err = 0; 3863 3864 pdev->error_state = pci_channel_io_normal; 3865 err = pci_enable_device(pdev); 3866 if (err) 3867 goto disconnect; 3868 3869 pci_set_power_state(pdev, PCI_D0); 3870 pci_set_master(pdev); 3871 pci_restore_state(pdev); 3872 3873 err = qlcnic_83xx_aer_reset(adapter); 3874 if (err == 0) 3875 return PCI_ERS_RESULT_RECOVERED; 3876 disconnect: 3877 clear_bit(__QLCNIC_AER, &adapter->state); 3878 clear_bit(__QLCNIC_RESETTING, &adapter->state); 3879 return PCI_ERS_RESULT_DISCONNECT; 3880 } 3881 3882 void qlcnic_83xx_io_resume(struct pci_dev *pdev) 3883 { 3884 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 3885 3886 pci_cleanup_aer_uncorrect_error_status(pdev); 3887 if (test_and_clear_bit(__QLCNIC_AER, &adapter->state)) 3888 qlcnic_83xx_aer_start_poll_work(adapter); 3889 } 3890