1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #ifndef _QLCNIC_H_ 9 #define _QLCNIC_H_ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/ioport.h> 15 #include <linux/pci.h> 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ip.h> 19 #include <linux/in.h> 20 #include <linux/tcp.h> 21 #include <linux/skbuff.h> 22 #include <linux/firmware.h> 23 #include <linux/ethtool.h> 24 #include <linux/mii.h> 25 #include <linux/timer.h> 26 27 #include <linux/vmalloc.h> 28 29 #include <linux/io.h> 30 #include <asm/byteorder.h> 31 #include <linux/bitops.h> 32 #include <linux/if_vlan.h> 33 34 #include "qlcnic_hdr.h" 35 #include "qlcnic_hw.h" 36 #include "qlcnic_83xx_hw.h" 37 #include "qlcnic_dcb.h" 38 39 #define _QLCNIC_LINUX_MAJOR 5 40 #define _QLCNIC_LINUX_MINOR 3 41 #define _QLCNIC_LINUX_SUBVERSION 50 42 #define QLCNIC_LINUX_VERSIONID "5.3.50" 43 #define QLCNIC_DRV_IDC_VER 0x01 44 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ 45 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) 46 47 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) 48 #define _major(v) (((v) >> 24) & 0xff) 49 #define _minor(v) (((v) >> 16) & 0xff) 50 #define _build(v) ((v) & 0xffff) 51 52 /* version in image has weird encoding: 53 * 7:0 - major 54 * 15:8 - minor 55 * 31:16 - build (little endian) 56 */ 57 #define QLCNIC_DECODE_VERSION(v) \ 58 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) 59 60 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) 61 #define QLCNIC_NUM_FLASH_SECTORS (64) 62 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) 63 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ 64 * QLCNIC_FLASH_SECTOR_SIZE) 65 66 #define RCV_DESC_RINGSIZE(rds_ring) \ 67 (sizeof(struct rcv_desc) * (rds_ring)->num_desc) 68 #define RCV_BUFF_RINGSIZE(rds_ring) \ 69 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) 70 #define STATUS_DESC_RINGSIZE(sds_ring) \ 71 (sizeof(struct status_desc) * (sds_ring)->num_desc) 72 #define TX_BUFF_RINGSIZE(tx_ring) \ 73 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) 74 #define TX_DESC_RINGSIZE(tx_ring) \ 75 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) 76 77 #define QLCNIC_P3P_A0 0x50 78 #define QLCNIC_P3P_C0 0x58 79 80 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) 81 82 #define FIRST_PAGE_GROUP_START 0 83 #define FIRST_PAGE_GROUP_END 0x100000 84 85 #define P3P_MAX_MTU (9600) 86 #define P3P_MIN_MTU (68) 87 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ 88 89 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) 90 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) 91 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 92 #define QLCNIC_LRO_BUFFER_EXTRA 2048 93 94 /* Tx defines */ 95 #define QLCNIC_MAX_FRAGS_PER_TX 14 96 #define MAX_TSO_HEADER_DESC 2 97 #define MGMT_CMD_DESC_RESV 4 98 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ 99 + MGMT_CMD_DESC_RESV) 100 #define QLCNIC_MAX_TX_TIMEOUTS 2 101 #define QLCNIC_MAX_TX_RINGS 8 102 #define QLCNIC_MAX_SDS_RINGS 8 103 104 /* 105 * Following are the states of the Phantom. Phantom will set them and 106 * Host will read to check if the fields are correct. 107 */ 108 #define PHAN_INITIALIZE_FAILED 0xffff 109 #define PHAN_INITIALIZE_COMPLETE 0xff01 110 111 /* Host writes the following to notify that it has done the init-handshake */ 112 #define PHAN_INITIALIZE_ACK 0xf00f 113 #define PHAN_PEG_RCV_INITIALIZED 0xff01 114 115 #define NUM_RCV_DESC_RINGS 3 116 117 #define RCV_RING_NORMAL 0 118 #define RCV_RING_JUMBO 1 119 120 #define MIN_CMD_DESCRIPTORS 64 121 #define MIN_RCV_DESCRIPTORS 64 122 #define MIN_JUMBO_DESCRIPTORS 32 123 124 #define MAX_CMD_DESCRIPTORS 1024 125 #define MAX_RCV_DESCRIPTORS_1G 4096 126 #define MAX_RCV_DESCRIPTORS_10G 8192 127 #define MAX_RCV_DESCRIPTORS_VF 2048 128 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 129 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 130 131 #define DEFAULT_RCV_DESCRIPTORS_1G 2048 132 #define DEFAULT_RCV_DESCRIPTORS_10G 4096 133 #define DEFAULT_RCV_DESCRIPTORS_VF 1024 134 #define MAX_RDS_RINGS 2 135 136 #define get_next_index(index, length) \ 137 (((index) + 1) & ((length) - 1)) 138 139 /* 140 * Following data structures describe the descriptors that will be used. 141 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when 142 * we are doing LSO (above the 1500 size packet) only. 143 */ 144 struct cmd_desc_type0 { 145 u8 tcp_hdr_offset; /* For LSO only */ 146 u8 ip_hdr_offset; /* For LSO only */ 147 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ 148 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ 149 150 __le64 addr_buffer2; 151 152 __le16 reference_handle; 153 __le16 mss; 154 u8 port_ctxid; /* 7:4 ctxid 3:0 port */ 155 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ 156 __le16 conn_id; /* IPSec offoad only */ 157 158 __le64 addr_buffer3; 159 __le64 addr_buffer1; 160 161 __le16 buffer_length[4]; 162 163 __le64 addr_buffer4; 164 165 u8 eth_addr[ETH_ALEN]; 166 __le16 vlan_TCI; 167 168 } __attribute__ ((aligned(64))); 169 170 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ 171 struct rcv_desc { 172 __le16 reference_handle; 173 __le16 reserved; 174 __le32 buffer_length; /* allocated buffer length (usually 2K) */ 175 __le64 addr_buffer; 176 } __packed; 177 178 struct status_desc { 179 __le64 status_desc_data[2]; 180 } __attribute__ ((aligned(16))); 181 182 /* UNIFIED ROMIMAGE */ 183 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 184 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 185 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 186 #define QLCNIC_UNI_DIR_SECT_FW 0x7 187 188 /*Offsets */ 189 #define QLCNIC_UNI_CHIP_REV_OFF 10 190 #define QLCNIC_UNI_FLAGS_OFF 11 191 #define QLCNIC_UNI_BIOS_VERSION_OFF 12 192 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 193 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 194 195 struct uni_table_desc{ 196 __le32 findex; 197 __le32 num_entries; 198 __le32 entry_size; 199 __le32 reserved[5]; 200 }; 201 202 struct uni_data_desc{ 203 __le32 findex; 204 __le32 size; 205 __le32 reserved[5]; 206 }; 207 208 /* Flash Defines and Structures */ 209 #define QLCNIC_FLT_LOCATION 0x3F1000 210 #define QLCNIC_FDT_LOCATION 0x3F0000 211 #define QLCNIC_B0_FW_IMAGE_REGION 0x74 212 #define QLCNIC_C0_FW_IMAGE_REGION 0x97 213 #define QLCNIC_BOOTLD_REGION 0X72 214 struct qlcnic_flt_header { 215 u16 version; 216 u16 len; 217 u16 checksum; 218 u16 reserved; 219 }; 220 221 struct qlcnic_flt_entry { 222 u8 region; 223 u8 reserved0; 224 u8 attrib; 225 u8 reserved1; 226 u32 size; 227 u32 start_addr; 228 u32 end_addr; 229 }; 230 231 /* Flash Descriptor Table */ 232 struct qlcnic_fdt { 233 u32 valid; 234 u16 ver; 235 u16 len; 236 u16 cksum; 237 u16 unused; 238 u8 model[16]; 239 u16 mfg_id; 240 u16 id; 241 u8 flag; 242 u8 erase_cmd; 243 u8 alt_erase_cmd; 244 u8 write_enable_cmd; 245 u8 write_enable_bits; 246 u8 write_statusreg_cmd; 247 u8 unprotected_sec_cmd; 248 u8 read_manuf_cmd; 249 u32 block_size; 250 u32 alt_block_size; 251 u32 flash_size; 252 u32 write_enable_data; 253 u8 readid_addr_len; 254 u8 write_disable_bits; 255 u8 read_dev_id_len; 256 u8 chip_erase_cmd; 257 u16 read_timeo; 258 u8 protected_sec_cmd; 259 u8 resvd[65]; 260 }; 261 /* Magic number to let user know flash is programmed */ 262 #define QLCNIC_BDINFO_MAGIC 0x12345678 263 264 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 265 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 266 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 267 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 268 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 269 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 270 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 271 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 272 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 273 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a 274 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b 275 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 276 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 277 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 278 279 #define QLCNIC_MSIX_TABLE_OFFSET 0x44 280 281 /* Flash memory map */ 282 #define QLCNIC_BRDCFG_START 0x4000 /* board config */ 283 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ 284 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ 285 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ 286 287 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) 288 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) 289 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) 290 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) 291 292 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) 293 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) 294 295 #define QLCNIC_FW_MIN_SIZE (0x3fffff) 296 #define QLCNIC_UNIFIED_ROMIMAGE 0 297 #define QLCNIC_FLASH_ROMIMAGE 1 298 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff 299 300 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" 301 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" 302 303 extern char qlcnic_driver_name[]; 304 305 extern int qlcnic_use_msi; 306 extern int qlcnic_use_msi_x; 307 extern int qlcnic_auto_fw_reset; 308 extern int qlcnic_load_fw_file; 309 310 /* Number of status descriptors to handle per interrupt */ 311 #define MAX_STATUS_HANDLE (64) 312 313 /* 314 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This 315 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. 316 */ 317 struct qlcnic_skb_frag { 318 u64 dma; 319 u64 length; 320 }; 321 322 /* Following defines are for the state of the buffers */ 323 #define QLCNIC_BUFFER_FREE 0 324 #define QLCNIC_BUFFER_BUSY 1 325 326 /* 327 * There will be one qlcnic_buffer per skb packet. These will be 328 * used to save the dma info for pci_unmap_page() 329 */ 330 struct qlcnic_cmd_buffer { 331 struct sk_buff *skb; 332 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; 333 u32 frag_count; 334 }; 335 336 /* In rx_buffer, we do not need multiple fragments as is a single buffer */ 337 struct qlcnic_rx_buffer { 338 u16 ref_handle; 339 struct sk_buff *skb; 340 struct list_head list; 341 u64 dma; 342 }; 343 344 /* Board types */ 345 #define QLCNIC_GBE 0x01 346 #define QLCNIC_XGBE 0x02 347 348 /* 349 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is 350 * adjusted based on configured MTU. 351 */ 352 #define QLCNIC_INTR_COAL_TYPE_RX 1 353 #define QLCNIC_INTR_COAL_TYPE_TX 2 354 355 #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3 356 #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256 357 358 #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64 359 #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64 360 361 #define QLCNIC_INTR_DEFAULT 0x04 362 #define QLCNIC_CONFIG_INTR_COALESCE 3 363 #define QLCNIC_DEV_INFO_SIZE 1 364 365 struct qlcnic_nic_intr_coalesce { 366 u8 type; 367 u8 sts_ring_mask; 368 u16 rx_packets; 369 u16 rx_time_us; 370 u16 tx_packets; 371 u16 tx_time_us; 372 u16 flag; 373 u32 timer_out; 374 }; 375 376 struct qlcnic_dump_template_hdr { 377 u32 type; 378 u32 offset; 379 u32 size; 380 u32 cap_mask; 381 u32 num_entries; 382 u32 version; 383 u32 timestamp; 384 u32 checksum; 385 u32 drv_cap_mask; 386 u32 sys_info[3]; 387 u32 saved_state[16]; 388 u32 cap_sizes[8]; 389 u32 ocm_wnd_reg[16]; 390 u32 rsvd[0]; 391 }; 392 393 struct qlcnic_fw_dump { 394 u8 clr; /* flag to indicate if dump is cleared */ 395 bool enable; /* enable/disable dump */ 396 u32 size; /* total size of the dump */ 397 void *data; /* dump data area */ 398 struct qlcnic_dump_template_hdr *tmpl_hdr; 399 dma_addr_t phys_addr; 400 void *dma_buffer; 401 bool use_pex_dma; 402 }; 403 404 /* 405 * One hardware_context{} per adapter 406 * contains interrupt info as well shared hardware info. 407 */ 408 struct qlcnic_hardware_context { 409 void __iomem *pci_base0; 410 void __iomem *ocm_win_crb; 411 412 unsigned long pci_len0; 413 414 rwlock_t crb_lock; 415 struct mutex mem_lock; 416 417 u8 revision_id; 418 u8 pci_func; 419 u8 linkup; 420 u8 loopback_state; 421 u8 beacon_state; 422 u8 has_link_events; 423 u8 fw_type; 424 u8 physical_port; 425 u8 reset_context; 426 u8 msix_supported; 427 u8 max_mac_filters; 428 u8 mc_enabled; 429 u8 max_mc_count; 430 u8 diag_test; 431 u8 num_msix; 432 u8 nic_mode; 433 char diag_cnt; 434 435 u16 max_uc_count; 436 u16 port_type; 437 u16 board_type; 438 u16 supported_type; 439 440 u16 link_speed; 441 u16 link_duplex; 442 u16 link_autoneg; 443 u16 module_type; 444 445 u16 op_mode; 446 u16 switch_mode; 447 u16 max_tx_ques; 448 u16 max_rx_ques; 449 u16 max_mtu; 450 u32 msg_enable; 451 u16 act_pci_func; 452 u16 max_pci_func; 453 454 u32 capabilities; 455 u32 extra_capability[3]; 456 u32 temp; 457 u32 int_vec_bit; 458 u32 fw_hal_version; 459 u32 port_config; 460 struct qlcnic_hardware_ops *hw_ops; 461 struct qlcnic_nic_intr_coalesce coal; 462 struct qlcnic_fw_dump fw_dump; 463 struct qlcnic_fdt fdt; 464 struct qlc_83xx_reset reset; 465 struct qlc_83xx_idc idc; 466 struct qlc_83xx_fw_info *fw_info; 467 struct qlcnic_intrpt_config *intr_tbl; 468 struct qlcnic_sriov *sriov; 469 u32 *reg_tbl; 470 u32 *ext_reg_tbl; 471 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; 472 u32 mbox_reg[4]; 473 struct qlcnic_mailbox *mailbox; 474 u8 extend_lb_time; 475 u8 phys_port_id[ETH_ALEN]; 476 }; 477 478 struct qlcnic_adapter_stats { 479 u64 xmitcalled; 480 u64 xmitfinished; 481 u64 rxdropped; 482 u64 txdropped; 483 u64 csummed; 484 u64 rx_pkts; 485 u64 lro_pkts; 486 u64 rxbytes; 487 u64 txbytes; 488 u64 lrobytes; 489 u64 lso_frames; 490 u64 xmit_on; 491 u64 xmit_off; 492 u64 skb_alloc_failure; 493 u64 null_rxbuf; 494 u64 rx_dma_map_error; 495 u64 tx_dma_map_error; 496 u64 spurious_intr; 497 u64 mac_filter_limit_overrun; 498 }; 499 500 /* 501 * Rcv Descriptor Context. One such per Rcv Descriptor. There may 502 * be one Rcv Descriptor for normal packets, one for jumbo and may be others. 503 */ 504 struct qlcnic_host_rds_ring { 505 void __iomem *crb_rcv_producer; 506 struct rcv_desc *desc_head; 507 struct qlcnic_rx_buffer *rx_buf_arr; 508 u32 num_desc; 509 u32 producer; 510 u32 dma_size; 511 u32 skb_size; 512 u32 flags; 513 struct list_head free_list; 514 spinlock_t lock; 515 dma_addr_t phys_addr; 516 } ____cacheline_internodealigned_in_smp; 517 518 struct qlcnic_host_sds_ring { 519 u32 consumer; 520 u32 num_desc; 521 void __iomem *crb_sts_consumer; 522 523 struct qlcnic_host_tx_ring *tx_ring; 524 struct status_desc *desc_head; 525 struct qlcnic_adapter *adapter; 526 struct napi_struct napi; 527 struct list_head free_list[NUM_RCV_DESC_RINGS]; 528 529 void __iomem *crb_intr_mask; 530 int irq; 531 532 dma_addr_t phys_addr; 533 char name[IFNAMSIZ + 12]; 534 } ____cacheline_internodealigned_in_smp; 535 536 struct qlcnic_host_tx_ring { 537 int irq; 538 void __iomem *crb_intr_mask; 539 char name[IFNAMSIZ + 12]; 540 u16 ctx_id; 541 542 u32 state; 543 u32 producer; 544 u32 sw_consumer; 545 u32 num_desc; 546 547 u64 xmit_on; 548 u64 xmit_off; 549 u64 xmit_called; 550 u64 xmit_finished; 551 552 void __iomem *crb_cmd_producer; 553 struct cmd_desc_type0 *desc_head; 554 struct qlcnic_adapter *adapter; 555 struct napi_struct napi; 556 struct qlcnic_cmd_buffer *cmd_buf_arr; 557 __le32 *hw_consumer; 558 559 dma_addr_t phys_addr; 560 dma_addr_t hw_cons_phys_addr; 561 struct netdev_queue *txq; 562 } ____cacheline_internodealigned_in_smp; 563 564 /* 565 * Receive context. There is one such structure per instance of the 566 * receive processing. Any state information that is relevant to 567 * the receive, and is must be in this structure. The global data may be 568 * present elsewhere. 569 */ 570 struct qlcnic_recv_context { 571 struct qlcnic_host_rds_ring *rds_rings; 572 struct qlcnic_host_sds_ring *sds_rings; 573 u32 state; 574 u16 context_id; 575 u16 virt_port; 576 }; 577 578 /* HW context creation */ 579 580 #define QLCNIC_OS_CRB_RETRY_COUNT 4000 581 582 #define QLCNIC_CDRP_CMD_BIT 0x80000000 583 584 /* 585 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared 586 * in the crb QLCNIC_CDRP_CRB_OFFSET. 587 */ 588 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) 589 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) 590 591 #define QLCNIC_CDRP_RSP_OK 0x00000001 592 #define QLCNIC_CDRP_RSP_FAIL 0x00000002 593 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 594 595 /* 596 * All commands must have the QLCNIC_CDRP_CMD_BIT set in 597 * the crb QLCNIC_CDRP_CRB_OFFSET. 598 */ 599 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) 600 601 #define QLCNIC_RCODE_SUCCESS 0 602 #define QLCNIC_RCODE_INVALID_ARGS 6 603 #define QLCNIC_RCODE_NOT_SUPPORTED 9 604 #define QLCNIC_RCODE_NOT_PERMITTED 10 605 #define QLCNIC_RCODE_NOT_IMPL 15 606 #define QLCNIC_RCODE_INVALID 16 607 #define QLCNIC_RCODE_TIMEOUT 17 608 #define QLCNIC_DESTROY_CTX_RESET 0 609 610 /* 611 * Capabilities Announced 612 */ 613 #define QLCNIC_CAP0_LEGACY_CONTEXT (1) 614 #define QLCNIC_CAP0_LEGACY_MN (1 << 2) 615 #define QLCNIC_CAP0_LSO (1 << 6) 616 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) 617 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) 618 #define QLCNIC_CAP0_VALIDOFF (1 << 11) 619 #define QLCNIC_CAP0_LRO_MSS (1 << 21) 620 #define QLCNIC_CAP0_TX_MULTI (1 << 22) 621 622 /* 623 * Context state 624 */ 625 #define QLCNIC_HOST_CTX_STATE_FREED 0 626 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 627 628 /* 629 * Rx context 630 */ 631 632 struct qlcnic_hostrq_sds_ring { 633 __le64 host_phys_addr; /* Ring base addr */ 634 __le32 ring_size; /* Ring entries */ 635 __le16 msi_index; 636 __le16 rsvd; /* Padding */ 637 } __packed; 638 639 struct qlcnic_hostrq_rds_ring { 640 __le64 host_phys_addr; /* Ring base addr */ 641 __le64 buff_size; /* Packet buffer size */ 642 __le32 ring_size; /* Ring entries */ 643 __le32 ring_kind; /* Class of ring */ 644 } __packed; 645 646 struct qlcnic_hostrq_rx_ctx { 647 __le64 host_rsp_dma_addr; /* Response dma'd here */ 648 __le32 capabilities[4]; /* Flag bit vector */ 649 __le32 host_int_crb_mode; /* Interrupt crb usage */ 650 __le32 host_rds_crb_mode; /* RDS crb usage */ 651 /* These ring offsets are relative to data[0] below */ 652 __le32 rds_ring_offset; /* Offset to RDS config */ 653 __le32 sds_ring_offset; /* Offset to SDS config */ 654 __le16 num_rds_rings; /* Count of RDS rings */ 655 __le16 num_sds_rings; /* Count of SDS rings */ 656 __le16 valid_field_offset; 657 u8 txrx_sds_binding; 658 u8 msix_handler; 659 u8 reserved[128]; /* reserve space for future expansion*/ 660 /* MUST BE 64-bit aligned. 661 The following is packed: 662 - N hostrq_rds_rings 663 - N hostrq_sds_rings */ 664 char data[0]; 665 } __packed; 666 667 struct qlcnic_cardrsp_rds_ring{ 668 __le32 host_producer_crb; /* Crb to use */ 669 __le32 rsvd1; /* Padding */ 670 } __packed; 671 672 struct qlcnic_cardrsp_sds_ring { 673 __le32 host_consumer_crb; /* Crb to use */ 674 __le32 interrupt_crb; /* Crb to use */ 675 } __packed; 676 677 struct qlcnic_cardrsp_rx_ctx { 678 /* These ring offsets are relative to data[0] below */ 679 __le32 rds_ring_offset; /* Offset to RDS config */ 680 __le32 sds_ring_offset; /* Offset to SDS config */ 681 __le32 host_ctx_state; /* Starting State */ 682 __le32 num_fn_per_port; /* How many PCI fn share the port */ 683 __le16 num_rds_rings; /* Count of RDS rings */ 684 __le16 num_sds_rings; /* Count of SDS rings */ 685 __le16 context_id; /* Handle for context */ 686 u8 phys_port; /* Physical id of port */ 687 u8 virt_port; /* Virtual/Logical id of port */ 688 u8 reserved[128]; /* save space for future expansion */ 689 /* MUST BE 64-bit aligned. 690 The following is packed: 691 - N cardrsp_rds_rings 692 - N cardrs_sds_rings */ 693 char data[0]; 694 } __packed; 695 696 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ 697 (sizeof(HOSTRQ_RX) + \ 698 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ 699 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) 700 701 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ 702 (sizeof(CARDRSP_RX) + \ 703 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ 704 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) 705 706 /* 707 * Tx context 708 */ 709 710 struct qlcnic_hostrq_cds_ring { 711 __le64 host_phys_addr; /* Ring base addr */ 712 __le32 ring_size; /* Ring entries */ 713 __le32 rsvd; /* Padding */ 714 } __packed; 715 716 struct qlcnic_hostrq_tx_ctx { 717 __le64 host_rsp_dma_addr; /* Response dma'd here */ 718 __le64 cmd_cons_dma_addr; /* */ 719 __le64 dummy_dma_addr; /* */ 720 __le32 capabilities[4]; /* Flag bit vector */ 721 __le32 host_int_crb_mode; /* Interrupt crb usage */ 722 __le32 rsvd1; /* Padding */ 723 __le16 rsvd2; /* Padding */ 724 __le16 interrupt_ctl; 725 __le16 msi_index; 726 __le16 rsvd3; /* Padding */ 727 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ 728 u8 reserved[128]; /* future expansion */ 729 } __packed; 730 731 struct qlcnic_cardrsp_cds_ring { 732 __le32 host_producer_crb; /* Crb to use */ 733 __le32 interrupt_crb; /* Crb to use */ 734 } __packed; 735 736 struct qlcnic_cardrsp_tx_ctx { 737 __le32 host_ctx_state; /* Starting state */ 738 __le16 context_id; /* Handle for context */ 739 u8 phys_port; /* Physical id of port */ 740 u8 virt_port; /* Virtual/Logical id of port */ 741 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ 742 u8 reserved[128]; /* future expansion */ 743 } __packed; 744 745 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) 746 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) 747 748 /* CRB */ 749 750 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 751 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 752 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 753 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 754 755 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 756 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 757 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 758 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 759 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 760 761 762 /* MAC */ 763 764 #define MC_COUNT_P3P 38 765 766 #define QLCNIC_MAC_NOOP 0 767 #define QLCNIC_MAC_ADD 1 768 #define QLCNIC_MAC_DEL 2 769 #define QLCNIC_MAC_VLAN_ADD 3 770 #define QLCNIC_MAC_VLAN_DEL 4 771 772 struct qlcnic_mac_list_s { 773 struct list_head list; 774 uint8_t mac_addr[ETH_ALEN+2]; 775 }; 776 777 /* MAC Learn */ 778 #define NO_MAC_LEARN 0 779 #define DRV_MAC_LEARN 1 780 #define FDB_MAC_LEARN 2 781 782 #define QLCNIC_HOST_REQUEST 0x13 783 #define QLCNIC_REQUEST 0x14 784 785 #define QLCNIC_MAC_EVENT 0x1 786 787 #define QLCNIC_IP_UP 2 788 #define QLCNIC_IP_DOWN 3 789 790 #define QLCNIC_ILB_MODE 0x1 791 #define QLCNIC_ELB_MODE 0x2 792 793 #define QLCNIC_LINKEVENT 0x1 794 #define QLCNIC_LB_RESPONSE 0x2 795 #define QLCNIC_IS_LB_CONFIGURED(VAL) \ 796 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) 797 798 /* 799 * Driver --> Firmware 800 */ 801 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 802 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 803 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 804 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 805 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc 806 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 807 808 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 809 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 810 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 811 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 812 813 /* 814 * Firmware --> Driver 815 */ 816 817 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f 818 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D 819 #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90 820 821 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ 822 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ 823 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ 824 825 #define QLCNIC_LRO_REQUEST_CLEANUP 4 826 827 /* Capabilites received */ 828 #define QLCNIC_FW_CAPABILITY_TSO BIT_1 829 #define QLCNIC_FW_CAPABILITY_BDG BIT_8 830 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 831 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 832 #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4 833 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 834 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 835 836 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 837 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3 838 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5 839 #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7 840 #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_8 841 842 /* module types */ 843 #define LINKEVENT_MODULE_NOT_PRESENT 1 844 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 845 #define LINKEVENT_MODULE_OPTICAL_SRLR 3 846 #define LINKEVENT_MODULE_OPTICAL_LRM 4 847 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 848 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 849 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 850 #define LINKEVENT_MODULE_TWINAX 8 851 852 #define LINKSPEED_10GBPS 10000 853 #define LINKSPEED_1GBPS 1000 854 #define LINKSPEED_100MBPS 100 855 #define LINKSPEED_10MBPS 10 856 857 #define LINKSPEED_ENCODED_10MBPS 0 858 #define LINKSPEED_ENCODED_100MBPS 1 859 #define LINKSPEED_ENCODED_1GBPS 2 860 861 #define LINKEVENT_AUTONEG_DISABLED 0 862 #define LINKEVENT_AUTONEG_ENABLED 1 863 864 #define LINKEVENT_HALF_DUPLEX 0 865 #define LINKEVENT_FULL_DUPLEX 1 866 867 #define LINKEVENT_LINKSPEED_MBPS 0 868 #define LINKEVENT_LINKSPEED_ENCODED 1 869 870 /* firmware response header: 871 * 63:58 - message type 872 * 57:56 - owner 873 * 55:53 - desc count 874 * 52:48 - reserved 875 * 47:40 - completion id 876 * 39:32 - opcode 877 * 31:16 - error code 878 * 15:00 - reserved 879 */ 880 #define qlcnic_get_nic_msg_opcode(msg_hdr) \ 881 ((msg_hdr >> 32) & 0xFF) 882 883 struct qlcnic_fw_msg { 884 union { 885 struct { 886 u64 hdr; 887 u64 body[7]; 888 }; 889 u64 words[8]; 890 }; 891 }; 892 893 struct qlcnic_nic_req { 894 __le64 qhdr; 895 __le64 req_hdr; 896 __le64 words[6]; 897 } __packed; 898 899 struct qlcnic_mac_req { 900 u8 op; 901 u8 tag; 902 u8 mac_addr[6]; 903 }; 904 905 struct qlcnic_vlan_req { 906 __le16 vlan_id; 907 __le16 rsvd[3]; 908 } __packed; 909 910 struct qlcnic_ipaddr { 911 __be32 ipv4; 912 __be32 ipv6[4]; 913 }; 914 915 #define QLCNIC_MSI_ENABLED 0x02 916 #define QLCNIC_MSIX_ENABLED 0x04 917 #define QLCNIC_LRO_ENABLED 0x01 918 #define QLCNIC_LRO_DISABLED 0x00 919 #define QLCNIC_BRIDGE_ENABLED 0X10 920 #define QLCNIC_DIAG_ENABLED 0x20 921 #define QLCNIC_ESWITCH_ENABLED 0x40 922 #define QLCNIC_ADAPTER_INITIALIZED 0x80 923 #define QLCNIC_TAGGING_ENABLED 0x100 924 #define QLCNIC_MACSPOOF 0x200 925 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 926 #define QLCNIC_PROMISC_DISABLED 0x800 927 #define QLCNIC_NEED_FLR 0x1000 928 #define QLCNIC_FW_RESET_OWNER 0x2000 929 #define QLCNIC_FW_HANG 0x4000 930 #define QLCNIC_FW_LRO_MSS_CAP 0x8000 931 #define QLCNIC_TX_INTR_SHARED 0x10000 932 #define QLCNIC_APP_CHANGED_FLAGS 0x20000 933 #define QLCNIC_HAS_PHYS_PORT_ID 0x40000 934 935 #define QLCNIC_IS_MSI_FAMILY(adapter) \ 936 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) 937 #define QLCNIC_IS_TSO_CAPABLE(adapter) \ 938 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO) 939 940 #define QLCNIC_BEACON_EANBLE 0xC 941 #define QLCNIC_BEACON_DISABLE 0xD 942 943 #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4 944 #define QLCNIC_DEF_NUM_TX_RINGS 4 945 #define QLCNIC_MSIX_TBL_SPACE 8192 946 #define QLCNIC_PCI_REG_MSIX_TBL 0x44 947 #define QLCNIC_MSIX_TBL_PGSIZE 4096 948 949 #define QLCNIC_ADAPTER_UP_MAGIC 777 950 951 #define __QLCNIC_FW_ATTACHED 0 952 #define __QLCNIC_DEV_UP 1 953 #define __QLCNIC_RESETTING 2 954 #define __QLCNIC_START_FW 4 955 #define __QLCNIC_AER 5 956 #define __QLCNIC_DIAG_RES_ALLOC 6 957 #define __QLCNIC_LED_ENABLE 7 958 #define __QLCNIC_ELB_INPROGRESS 8 959 #define __QLCNIC_MULTI_TX_UNIQUE 9 960 #define __QLCNIC_SRIOV_ENABLE 10 961 #define __QLCNIC_SRIOV_CAPABLE 11 962 #define __QLCNIC_MBX_POLL_ENABLE 12 963 #define __QLCNIC_DIAG_MODE 13 964 #define __QLCNIC_DCB_STATE 14 965 #define __QLCNIC_DCB_IN_AEN 15 966 967 #define QLCNIC_INTERRUPT_TEST 1 968 #define QLCNIC_LOOPBACK_TEST 2 969 #define QLCNIC_LED_TEST 3 970 971 #define QLCNIC_FILTER_AGE 80 972 #define QLCNIC_READD_AGE 20 973 #define QLCNIC_LB_MAX_FILTERS 64 974 #define QLCNIC_LB_BUCKET_SIZE 32 975 #define QLCNIC_ILB_MAX_RCV_LOOP 10 976 977 struct qlcnic_filter { 978 struct hlist_node fnode; 979 u8 faddr[ETH_ALEN]; 980 u16 vlan_id; 981 unsigned long ftime; 982 }; 983 984 struct qlcnic_filter_hash { 985 struct hlist_head *fhead; 986 u8 fnum; 987 u16 fmax; 988 u16 fbucket_size; 989 }; 990 991 /* Mailbox specific data structures */ 992 struct qlcnic_mailbox { 993 struct workqueue_struct *work_q; 994 struct qlcnic_adapter *adapter; 995 struct qlcnic_mbx_ops *ops; 996 struct work_struct work; 997 struct completion completion; 998 struct list_head cmd_q; 999 unsigned long status; 1000 spinlock_t queue_lock; /* Mailbox queue lock */ 1001 spinlock_t aen_lock; /* Mailbox response/AEN lock */ 1002 atomic_t rsp_status; 1003 u32 num_cmds; 1004 }; 1005 1006 struct qlcnic_adapter { 1007 struct qlcnic_hardware_context *ahw; 1008 struct qlcnic_recv_context *recv_ctx; 1009 struct qlcnic_host_tx_ring *tx_ring; 1010 struct net_device *netdev; 1011 struct pci_dev *pdev; 1012 1013 unsigned long state; 1014 u32 flags; 1015 1016 int max_drv_tx_rings; 1017 u16 num_txd; 1018 u16 num_rxd; 1019 u16 num_jumbo_rxd; 1020 u16 max_rxd; 1021 u16 max_jumbo_rxd; 1022 1023 u8 max_rds_rings; 1024 u8 max_sds_rings; 1025 u8 rx_csum; 1026 u8 portnum; 1027 1028 u8 fw_wait_cnt; 1029 u8 fw_fail_cnt; 1030 u8 tx_timeo_cnt; 1031 u8 need_fw_reset; 1032 u8 reset_ctx_cnt; 1033 1034 u16 is_up; 1035 u16 rx_pvid; 1036 u16 tx_pvid; 1037 1038 u32 irq; 1039 u32 heartbeat; 1040 1041 u8 dev_state; 1042 u8 reset_ack_timeo; 1043 u8 dev_init_timeo; 1044 1045 u8 mac_addr[ETH_ALEN]; 1046 1047 u64 dev_rst_time; 1048 bool drv_mac_learn; 1049 bool fdb_mac_learn; 1050 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1051 u8 flash_mfg_id; 1052 struct qlcnic_npar_info *npars; 1053 struct qlcnic_eswitch *eswitch; 1054 struct qlcnic_nic_template *nic_ops; 1055 1056 struct qlcnic_adapter_stats stats; 1057 struct list_head mac_list; 1058 1059 void __iomem *tgt_mask_reg; 1060 void __iomem *tgt_status_reg; 1061 void __iomem *crb_int_state_reg; 1062 void __iomem *isr_int_vec; 1063 1064 struct msix_entry *msix_entries; 1065 struct workqueue_struct *qlcnic_wq; 1066 struct delayed_work fw_work; 1067 struct delayed_work idc_aen_work; 1068 struct delayed_work mbx_poll_work; 1069 struct qlcnic_dcb *dcb; 1070 1071 struct qlcnic_filter_hash fhash; 1072 struct qlcnic_filter_hash rx_fhash; 1073 struct list_head vf_mc_list; 1074 1075 spinlock_t tx_clean_lock; 1076 spinlock_t mac_learn_lock; 1077 /* spinlock for catching rcv filters for eswitch traffic */ 1078 spinlock_t rx_mac_learn_lock; 1079 u32 file_prd_off; /*File fw product offset*/ 1080 u32 fw_version; 1081 u32 offload_flags; 1082 const struct firmware *fw; 1083 }; 1084 1085 struct qlcnic_info_le { 1086 __le16 pci_func; 1087 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ 1088 __le16 phys_port; 1089 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ 1090 1091 __le32 capabilities; 1092 u8 max_mac_filters; 1093 u8 reserved1; 1094 __le16 max_mtu; 1095 1096 __le16 max_tx_ques; 1097 __le16 max_rx_ques; 1098 __le16 min_tx_bw; 1099 __le16 max_tx_bw; 1100 __le32 op_type; 1101 __le16 max_bw_reg_offset; 1102 __le16 max_linkspeed_reg_offset; 1103 __le32 capability1; 1104 __le32 capability2; 1105 __le32 capability3; 1106 __le16 max_tx_mac_filters; 1107 __le16 max_rx_mcast_mac_filters; 1108 __le16 max_rx_ucast_mac_filters; 1109 __le16 max_rx_ip_addr; 1110 __le16 max_rx_lro_flow; 1111 __le16 max_rx_status_rings; 1112 __le16 max_rx_buf_rings; 1113 __le16 max_tx_vlan_keys; 1114 u8 total_pf; 1115 u8 total_rss_engines; 1116 __le16 max_vports; 1117 __le16 linkstate_reg_offset; 1118 __le16 bit_offsets; 1119 __le16 max_local_ipv6_addrs; 1120 __le16 max_remote_ipv6_addrs; 1121 u8 reserved2[56]; 1122 } __packed; 1123 1124 struct qlcnic_info { 1125 u16 pci_func; 1126 u16 op_mode; 1127 u16 phys_port; 1128 u16 switch_mode; 1129 u32 capabilities; 1130 u8 max_mac_filters; 1131 u16 max_mtu; 1132 u16 max_tx_ques; 1133 u16 max_rx_ques; 1134 u16 min_tx_bw; 1135 u16 max_tx_bw; 1136 u32 op_type; 1137 u16 max_bw_reg_offset; 1138 u16 max_linkspeed_reg_offset; 1139 u32 capability1; 1140 u32 capability2; 1141 u32 capability3; 1142 u16 max_tx_mac_filters; 1143 u16 max_rx_mcast_mac_filters; 1144 u16 max_rx_ucast_mac_filters; 1145 u16 max_rx_ip_addr; 1146 u16 max_rx_lro_flow; 1147 u16 max_rx_status_rings; 1148 u16 max_rx_buf_rings; 1149 u16 max_tx_vlan_keys; 1150 u8 total_pf; 1151 u8 total_rss_engines; 1152 u16 max_vports; 1153 u16 linkstate_reg_offset; 1154 u16 bit_offsets; 1155 u16 max_local_ipv6_addrs; 1156 u16 max_remote_ipv6_addrs; 1157 }; 1158 1159 struct qlcnic_pci_info_le { 1160 __le16 id; /* pci function id */ 1161 __le16 active; /* 1 = Enabled */ 1162 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ 1163 __le16 default_port; /* default port number */ 1164 1165 __le16 tx_min_bw; /* Multiple of 100mbpc */ 1166 __le16 tx_max_bw; 1167 __le16 reserved1[2]; 1168 1169 u8 mac[ETH_ALEN]; 1170 __le16 func_count; 1171 u8 reserved2[104]; 1172 1173 } __packed; 1174 1175 struct qlcnic_pci_info { 1176 u16 id; 1177 u16 active; 1178 u16 type; 1179 u16 default_port; 1180 u16 tx_min_bw; 1181 u16 tx_max_bw; 1182 u8 mac[ETH_ALEN]; 1183 u16 func_count; 1184 }; 1185 1186 struct qlcnic_npar_info { 1187 bool eswitch_status; 1188 u16 pvid; 1189 u16 min_bw; 1190 u16 max_bw; 1191 u8 phy_port; 1192 u8 type; 1193 u8 active; 1194 u8 enable_pm; 1195 u8 dest_npar; 1196 u8 discard_tagged; 1197 u8 mac_override; 1198 u8 mac_anti_spoof; 1199 u8 promisc_mode; 1200 u8 offload_flags; 1201 u8 pci_func; 1202 }; 1203 1204 struct qlcnic_eswitch { 1205 u8 port; 1206 u8 active_vports; 1207 u8 active_vlans; 1208 u8 active_ucast_filters; 1209 u8 max_ucast_filters; 1210 u8 max_active_vlans; 1211 1212 u32 flags; 1213 #define QLCNIC_SWITCH_ENABLE BIT_1 1214 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 1215 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 1216 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 1217 }; 1218 1219 1220 /* Return codes for Error handling */ 1221 #define QL_STATUS_INVALID_PARAM -1 1222 1223 #define MAX_BW 100 /* % of link speed */ 1224 #define MAX_VLAN_ID 4095 1225 #define MIN_VLAN_ID 2 1226 #define DEFAULT_MAC_LEARN 1 1227 1228 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) 1229 #define IS_VALID_BW(bw) (bw <= MAX_BW) 1230 1231 struct qlcnic_pci_func_cfg { 1232 u16 func_type; 1233 u16 min_bw; 1234 u16 max_bw; 1235 u16 port_num; 1236 u8 pci_func; 1237 u8 func_state; 1238 u8 def_mac_addr[6]; 1239 }; 1240 1241 struct qlcnic_npar_func_cfg { 1242 u32 fw_capab; 1243 u16 port_num; 1244 u16 min_bw; 1245 u16 max_bw; 1246 u16 max_tx_queues; 1247 u16 max_rx_queues; 1248 u8 pci_func; 1249 u8 op_mode; 1250 }; 1251 1252 struct qlcnic_pm_func_cfg { 1253 u8 pci_func; 1254 u8 action; 1255 u8 dest_npar; 1256 u8 reserved[5]; 1257 }; 1258 1259 struct qlcnic_esw_func_cfg { 1260 u16 vlan_id; 1261 u8 op_mode; 1262 u8 op_type; 1263 u8 pci_func; 1264 u8 host_vlan_tag; 1265 u8 promisc_mode; 1266 u8 discard_tagged; 1267 u8 mac_override; 1268 u8 mac_anti_spoof; 1269 u8 offload_flags; 1270 u8 reserved[5]; 1271 }; 1272 1273 #define QLCNIC_STATS_VERSION 1 1274 #define QLCNIC_STATS_PORT 1 1275 #define QLCNIC_STATS_ESWITCH 2 1276 #define QLCNIC_QUERY_RX_COUNTER 0 1277 #define QLCNIC_QUERY_TX_COUNTER 1 1278 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL 1279 #define QLCNIC_FILL_STATS(VAL1) \ 1280 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) 1281 #define QLCNIC_MAC_STATS 1 1282 #define QLCNIC_ESW_STATS 2 1283 1284 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ 1285 do { \ 1286 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ 1287 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1288 (VAL1) = (VAL2); \ 1289 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ 1290 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1291 (VAL1) += (VAL2); \ 1292 } while (0) 1293 1294 struct qlcnic_mac_statistics_le { 1295 __le64 mac_tx_frames; 1296 __le64 mac_tx_bytes; 1297 __le64 mac_tx_mcast_pkts; 1298 __le64 mac_tx_bcast_pkts; 1299 __le64 mac_tx_pause_cnt; 1300 __le64 mac_tx_ctrl_pkt; 1301 __le64 mac_tx_lt_64b_pkts; 1302 __le64 mac_tx_lt_127b_pkts; 1303 __le64 mac_tx_lt_255b_pkts; 1304 __le64 mac_tx_lt_511b_pkts; 1305 __le64 mac_tx_lt_1023b_pkts; 1306 __le64 mac_tx_lt_1518b_pkts; 1307 __le64 mac_tx_gt_1518b_pkts; 1308 __le64 rsvd1[3]; 1309 1310 __le64 mac_rx_frames; 1311 __le64 mac_rx_bytes; 1312 __le64 mac_rx_mcast_pkts; 1313 __le64 mac_rx_bcast_pkts; 1314 __le64 mac_rx_pause_cnt; 1315 __le64 mac_rx_ctrl_pkt; 1316 __le64 mac_rx_lt_64b_pkts; 1317 __le64 mac_rx_lt_127b_pkts; 1318 __le64 mac_rx_lt_255b_pkts; 1319 __le64 mac_rx_lt_511b_pkts; 1320 __le64 mac_rx_lt_1023b_pkts; 1321 __le64 mac_rx_lt_1518b_pkts; 1322 __le64 mac_rx_gt_1518b_pkts; 1323 __le64 rsvd2[3]; 1324 1325 __le64 mac_rx_length_error; 1326 __le64 mac_rx_length_small; 1327 __le64 mac_rx_length_large; 1328 __le64 mac_rx_jabber; 1329 __le64 mac_rx_dropped; 1330 __le64 mac_rx_crc_error; 1331 __le64 mac_align_error; 1332 } __packed; 1333 1334 struct qlcnic_mac_statistics { 1335 u64 mac_tx_frames; 1336 u64 mac_tx_bytes; 1337 u64 mac_tx_mcast_pkts; 1338 u64 mac_tx_bcast_pkts; 1339 u64 mac_tx_pause_cnt; 1340 u64 mac_tx_ctrl_pkt; 1341 u64 mac_tx_lt_64b_pkts; 1342 u64 mac_tx_lt_127b_pkts; 1343 u64 mac_tx_lt_255b_pkts; 1344 u64 mac_tx_lt_511b_pkts; 1345 u64 mac_tx_lt_1023b_pkts; 1346 u64 mac_tx_lt_1518b_pkts; 1347 u64 mac_tx_gt_1518b_pkts; 1348 u64 rsvd1[3]; 1349 u64 mac_rx_frames; 1350 u64 mac_rx_bytes; 1351 u64 mac_rx_mcast_pkts; 1352 u64 mac_rx_bcast_pkts; 1353 u64 mac_rx_pause_cnt; 1354 u64 mac_rx_ctrl_pkt; 1355 u64 mac_rx_lt_64b_pkts; 1356 u64 mac_rx_lt_127b_pkts; 1357 u64 mac_rx_lt_255b_pkts; 1358 u64 mac_rx_lt_511b_pkts; 1359 u64 mac_rx_lt_1023b_pkts; 1360 u64 mac_rx_lt_1518b_pkts; 1361 u64 mac_rx_gt_1518b_pkts; 1362 u64 rsvd2[3]; 1363 u64 mac_rx_length_error; 1364 u64 mac_rx_length_small; 1365 u64 mac_rx_length_large; 1366 u64 mac_rx_jabber; 1367 u64 mac_rx_dropped; 1368 u64 mac_rx_crc_error; 1369 u64 mac_align_error; 1370 }; 1371 1372 struct qlcnic_esw_stats_le { 1373 __le16 context_id; 1374 __le16 version; 1375 __le16 size; 1376 __le16 unused; 1377 __le64 unicast_frames; 1378 __le64 multicast_frames; 1379 __le64 broadcast_frames; 1380 __le64 dropped_frames; 1381 __le64 errors; 1382 __le64 local_frames; 1383 __le64 numbytes; 1384 __le64 rsvd[3]; 1385 } __packed; 1386 1387 struct __qlcnic_esw_statistics { 1388 u16 context_id; 1389 u16 version; 1390 u16 size; 1391 u16 unused; 1392 u64 unicast_frames; 1393 u64 multicast_frames; 1394 u64 broadcast_frames; 1395 u64 dropped_frames; 1396 u64 errors; 1397 u64 local_frames; 1398 u64 numbytes; 1399 u64 rsvd[3]; 1400 }; 1401 1402 struct qlcnic_esw_statistics { 1403 struct __qlcnic_esw_statistics rx; 1404 struct __qlcnic_esw_statistics tx; 1405 }; 1406 1407 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed 1408 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed 1409 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed 1410 #define QLCNIC_FORCE_FW_RESET 0xdeaddead 1411 #define QLCNIC_SET_QUIESCENT 0xadd00010 1412 #define QLCNIC_RESET_QUIESCENT 0xadd00020 1413 1414 struct _cdrp_cmd { 1415 u32 num; 1416 u32 *arg; 1417 }; 1418 1419 struct qlcnic_cmd_args { 1420 struct completion completion; 1421 struct list_head list; 1422 struct _cdrp_cmd req; 1423 struct _cdrp_cmd rsp; 1424 atomic_t rsp_status; 1425 int pay_size; 1426 u32 rsp_opcode; 1427 u32 total_cmds; 1428 u32 op_type; 1429 u32 type; 1430 u32 cmd_op; 1431 u32 *hdr; /* Back channel message header */ 1432 u32 *pay; /* Back channel message payload */ 1433 u8 func_num; 1434 }; 1435 1436 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); 1437 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); 1438 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); 1439 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); 1440 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); 1441 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); 1442 1443 #define ADDR_IN_RANGE(addr, low, high) \ 1444 (((addr) < (high)) && ((addr) >= (low))) 1445 1446 #define QLCRD32(adapter, off, err) \ 1447 (adapter->ahw->hw_ops->read_reg)(adapter, off, err) 1448 1449 #define QLCWR32(adapter, off, val) \ 1450 adapter->ahw->hw_ops->write_reg(adapter, off, val) 1451 1452 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); 1453 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); 1454 1455 #define qlcnic_rom_lock(a) \ 1456 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) 1457 #define qlcnic_rom_unlock(a) \ 1458 qlcnic_pcie_sem_unlock((a), 2) 1459 #define qlcnic_phy_lock(a) \ 1460 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) 1461 #define qlcnic_phy_unlock(a) \ 1462 qlcnic_pcie_sem_unlock((a), 3) 1463 #define qlcnic_sw_lock(a) \ 1464 qlcnic_pcie_sem_lock((a), 6, 0) 1465 #define qlcnic_sw_unlock(a) \ 1466 qlcnic_pcie_sem_unlock((a), 6) 1467 #define crb_win_lock(a) \ 1468 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) 1469 #define crb_win_unlock(a) \ 1470 qlcnic_pcie_sem_unlock((a), 7) 1471 1472 #define __QLCNIC_MAX_LED_RATE 0xf 1473 #define __QLCNIC_MAX_LED_STATE 0x2 1474 1475 #define MAX_CTL_CHECK 1000 1476 1477 int qlcnic_wol_supported(struct qlcnic_adapter *adapter); 1478 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); 1479 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); 1480 int qlcnic_dump_fw(struct qlcnic_adapter *); 1481 int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *); 1482 bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *); 1483 pci_ers_result_t qlcnic_82xx_io_error_detected(struct pci_dev *, 1484 pci_channel_state_t); 1485 pci_ers_result_t qlcnic_82xx_io_slot_reset(struct pci_dev *); 1486 void qlcnic_82xx_io_resume(struct pci_dev *); 1487 1488 /* Functions from qlcnic_init.c */ 1489 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int); 1490 int qlcnic_load_firmware(struct qlcnic_adapter *adapter); 1491 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); 1492 void qlcnic_request_firmware(struct qlcnic_adapter *adapter); 1493 void qlcnic_release_firmware(struct qlcnic_adapter *adapter); 1494 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); 1495 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); 1496 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); 1497 1498 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); 1499 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, 1500 u8 *bytes, size_t size); 1501 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); 1502 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); 1503 1504 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); 1505 1506 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); 1507 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); 1508 1509 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); 1510 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); 1511 1512 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); 1513 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); 1514 void qlcnic_release_tx_buffers(struct qlcnic_adapter *, 1515 struct qlcnic_host_tx_ring *); 1516 1517 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); 1518 void qlcnic_watchdog_task(struct work_struct *work); 1519 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, 1520 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id); 1521 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); 1522 void qlcnic_set_multi(struct net_device *netdev); 1523 void __qlcnic_set_multi(struct net_device *, u16); 1524 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16); 1525 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *); 1526 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter); 1527 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *); 1528 1529 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); 1530 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32); 1531 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); 1532 netdev_features_t qlcnic_fix_features(struct net_device *netdev, 1533 netdev_features_t features); 1534 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); 1535 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); 1536 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); 1537 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); 1538 1539 /* Functions from qlcnic_ethtool.c */ 1540 int qlcnic_check_loopback_buff(unsigned char *, u8 []); 1541 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8); 1542 int qlcnic_loopback_test(struct net_device *, u8); 1543 1544 /* Functions from qlcnic_main.c */ 1545 int qlcnic_reset_context(struct qlcnic_adapter *); 1546 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); 1547 int qlcnic_diag_alloc_res(struct net_device *netdev, int test); 1548 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 1549 int qlcnic_set_max_rss(struct qlcnic_adapter *, u8, int); 1550 int qlcnic_validate_max_rss(struct qlcnic_adapter *, __u32); 1551 int qlcnic_validate_max_tx_rings(struct qlcnic_adapter *, u32 txq); 1552 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); 1553 void qlcnic_82xx_set_mac_filter_count(struct qlcnic_adapter *); 1554 int qlcnic_enable_msix(struct qlcnic_adapter *, u32); 1555 void qlcnic_set_drv_version(struct qlcnic_adapter *); 1556 1557 /* eSwitch management functions */ 1558 int qlcnic_config_switch_port(struct qlcnic_adapter *, 1559 struct qlcnic_esw_func_cfg *); 1560 1561 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, 1562 struct qlcnic_esw_func_cfg *); 1563 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); 1564 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, 1565 struct __qlcnic_esw_statistics *); 1566 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, 1567 struct __qlcnic_esw_statistics *); 1568 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); 1569 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); 1570 1571 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); 1572 1573 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); 1574 void qlcnic_free_sds_rings(struct qlcnic_recv_context *); 1575 void qlcnic_advert_link_change(struct qlcnic_adapter *, int); 1576 void qlcnic_free_tx_rings(struct qlcnic_adapter *); 1577 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); 1578 void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1579 1580 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); 1581 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); 1582 void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter); 1583 void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter); 1584 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); 1585 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); 1586 int qlcnic_82xx_get_settings(struct qlcnic_adapter *, struct ethtool_cmd *); 1587 1588 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); 1589 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); 1590 void qlcnic_set_vlan_config(struct qlcnic_adapter *, 1591 struct qlcnic_esw_func_cfg *); 1592 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, 1593 struct qlcnic_esw_func_cfg *); 1594 1595 void qlcnic_down(struct qlcnic_adapter *, struct net_device *); 1596 int qlcnic_up(struct qlcnic_adapter *, struct net_device *); 1597 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *); 1598 void qlcnic_detach(struct qlcnic_adapter *); 1599 void qlcnic_teardown_intr(struct qlcnic_adapter *); 1600 int qlcnic_attach(struct qlcnic_adapter *); 1601 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *); 1602 void qlcnic_restore_indev_addr(struct net_device *, unsigned long); 1603 1604 int qlcnic_check_temp(struct qlcnic_adapter *); 1605 int qlcnic_init_pci_info(struct qlcnic_adapter *); 1606 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *); 1607 int qlcnic_reset_npar_config(struct qlcnic_adapter *); 1608 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *); 1609 void qlcnic_add_lb_filter(struct qlcnic_adapter *, struct sk_buff *, int, u16); 1610 int qlcnic_get_beacon_state(struct qlcnic_adapter *, u8 *); 1611 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter); 1612 int qlcnic_read_mac_addr(struct qlcnic_adapter *); 1613 int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int); 1614 void qlcnic_set_netdev_features(struct qlcnic_adapter *, 1615 struct qlcnic_esw_func_cfg *); 1616 void qlcnic_sriov_vf_schedule_multi(struct net_device *); 1617 void qlcnic_vf_add_mc_list(struct net_device *, u16); 1618 1619 /* 1620 * QLOGIC Board information 1621 */ 1622 1623 #define QLCNIC_MAX_BOARD_NAME_LEN 100 1624 struct qlcnic_board_info { 1625 unsigned short vendor; 1626 unsigned short device; 1627 unsigned short sub_vendor; 1628 unsigned short sub_device; 1629 char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; 1630 }; 1631 1632 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) 1633 { 1634 if (likely(tx_ring->producer < tx_ring->sw_consumer)) 1635 return tx_ring->sw_consumer - tx_ring->producer; 1636 else 1637 return tx_ring->sw_consumer + tx_ring->num_desc - 1638 tx_ring->producer; 1639 } 1640 1641 static inline int qlcnic_set_real_num_queues(struct qlcnic_adapter *adapter, 1642 struct net_device *netdev) 1643 { 1644 int err, tx_q; 1645 1646 tx_q = adapter->max_drv_tx_rings; 1647 1648 netdev->num_tx_queues = tx_q; 1649 netdev->real_num_tx_queues = tx_q; 1650 1651 err = netif_set_real_num_tx_queues(netdev, tx_q); 1652 if (err) 1653 dev_err(&adapter->pdev->dev, "failed to set %d Tx queues\n", 1654 tx_q); 1655 else 1656 dev_info(&adapter->pdev->dev, "set %d Tx queues\n", tx_q); 1657 1658 return err; 1659 } 1660 1661 struct qlcnic_nic_template { 1662 int (*config_bridged_mode) (struct qlcnic_adapter *, u32); 1663 int (*config_led) (struct qlcnic_adapter *, u32, u32); 1664 int (*start_firmware) (struct qlcnic_adapter *); 1665 int (*init_driver) (struct qlcnic_adapter *); 1666 void (*request_reset) (struct qlcnic_adapter *, u32); 1667 void (*cancel_idc_work) (struct qlcnic_adapter *); 1668 int (*napi_add)(struct qlcnic_adapter *, struct net_device *); 1669 void (*napi_del)(struct qlcnic_adapter *); 1670 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); 1671 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); 1672 int (*shutdown)(struct pci_dev *); 1673 int (*resume)(struct qlcnic_adapter *); 1674 }; 1675 1676 struct qlcnic_mbx_ops { 1677 int (*enqueue_cmd) (struct qlcnic_adapter *, 1678 struct qlcnic_cmd_args *, unsigned long *); 1679 void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1680 void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1681 void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1682 void (*nofity_fw) (struct qlcnic_adapter *, u8); 1683 }; 1684 1685 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *); 1686 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *); 1687 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx); 1688 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx); 1689 1690 /* Adapter hardware abstraction */ 1691 struct qlcnic_hardware_ops { 1692 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); 1693 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); 1694 int (*read_reg) (struct qlcnic_adapter *, ulong, int *); 1695 int (*write_reg) (struct qlcnic_adapter *, ulong, u32); 1696 void (*get_ocm_win) (struct qlcnic_hardware_context *); 1697 int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8); 1698 int (*setup_intr) (struct qlcnic_adapter *, u8, int); 1699 int (*alloc_mbx_args)(struct qlcnic_cmd_args *, 1700 struct qlcnic_adapter *, u32); 1701 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1702 void (*get_func_no) (struct qlcnic_adapter *); 1703 int (*api_lock) (struct qlcnic_adapter *); 1704 void (*api_unlock) (struct qlcnic_adapter *); 1705 void (*add_sysfs) (struct qlcnic_adapter *); 1706 void (*remove_sysfs) (struct qlcnic_adapter *); 1707 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); 1708 int (*create_rx_ctx) (struct qlcnic_adapter *); 1709 int (*create_tx_ctx) (struct qlcnic_adapter *, 1710 struct qlcnic_host_tx_ring *, int); 1711 void (*del_rx_ctx) (struct qlcnic_adapter *); 1712 void (*del_tx_ctx) (struct qlcnic_adapter *, 1713 struct qlcnic_host_tx_ring *); 1714 int (*setup_link_event) (struct qlcnic_adapter *, int); 1715 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); 1716 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); 1717 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); 1718 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8); 1719 void (*napi_enable) (struct qlcnic_adapter *); 1720 void (*napi_disable) (struct qlcnic_adapter *); 1721 void (*config_intr_coal) (struct qlcnic_adapter *); 1722 int (*config_rss) (struct qlcnic_adapter *, int); 1723 int (*config_hw_lro) (struct qlcnic_adapter *, int); 1724 int (*config_loopback) (struct qlcnic_adapter *, u8); 1725 int (*clear_loopback) (struct qlcnic_adapter *, u8); 1726 int (*config_promisc_mode) (struct qlcnic_adapter *, u32); 1727 void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16); 1728 int (*get_board_info) (struct qlcnic_adapter *); 1729 void (*set_mac_filter_count) (struct qlcnic_adapter *); 1730 void (*free_mac_list) (struct qlcnic_adapter *); 1731 int (*read_phys_port_id) (struct qlcnic_adapter *); 1732 pci_ers_result_t (*io_error_detected) (struct pci_dev *, 1733 pci_channel_state_t); 1734 pci_ers_result_t (*io_slot_reset) (struct pci_dev *); 1735 void (*io_resume) (struct pci_dev *); 1736 }; 1737 1738 extern struct qlcnic_nic_template qlcnic_vf_ops; 1739 1740 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) 1741 { 1742 return adapter->nic_ops->start_firmware(adapter); 1743 } 1744 1745 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, 1746 loff_t offset, size_t size) 1747 { 1748 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); 1749 } 1750 1751 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, 1752 loff_t offset, size_t size) 1753 { 1754 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); 1755 } 1756 1757 static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, 1758 ulong off, u32 data) 1759 { 1760 return adapter->ahw->hw_ops->write_reg(adapter, off, data); 1761 } 1762 1763 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, 1764 u8 *mac, u8 function) 1765 { 1766 return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function); 1767 } 1768 1769 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter, 1770 u8 num_intr, int txq) 1771 { 1772 return adapter->ahw->hw_ops->setup_intr(adapter, num_intr, txq); 1773 } 1774 1775 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, 1776 struct qlcnic_adapter *adapter, u32 arg) 1777 { 1778 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); 1779 } 1780 1781 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, 1782 struct qlcnic_cmd_args *cmd) 1783 { 1784 if (adapter->ahw->hw_ops->mbx_cmd) 1785 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); 1786 1787 return -EIO; 1788 } 1789 1790 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) 1791 { 1792 adapter->ahw->hw_ops->get_func_no(adapter); 1793 } 1794 1795 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) 1796 { 1797 return adapter->ahw->hw_ops->api_lock(adapter); 1798 } 1799 1800 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) 1801 { 1802 adapter->ahw->hw_ops->api_unlock(adapter); 1803 } 1804 1805 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) 1806 { 1807 if (adapter->ahw->hw_ops->add_sysfs) 1808 adapter->ahw->hw_ops->add_sysfs(adapter); 1809 } 1810 1811 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) 1812 { 1813 if (adapter->ahw->hw_ops->remove_sysfs) 1814 adapter->ahw->hw_ops->remove_sysfs(adapter); 1815 } 1816 1817 static inline void 1818 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) 1819 { 1820 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); 1821 } 1822 1823 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) 1824 { 1825 return adapter->ahw->hw_ops->create_rx_ctx(adapter); 1826 } 1827 1828 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, 1829 struct qlcnic_host_tx_ring *ptr, 1830 int ring) 1831 { 1832 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); 1833 } 1834 1835 static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter) 1836 { 1837 return adapter->ahw->hw_ops->del_rx_ctx(adapter); 1838 } 1839 1840 static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter, 1841 struct qlcnic_host_tx_ring *ptr) 1842 { 1843 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr); 1844 } 1845 1846 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, 1847 int enable) 1848 { 1849 return adapter->ahw->hw_ops->setup_link_event(adapter, enable); 1850 } 1851 1852 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, 1853 struct qlcnic_info *info, u8 id) 1854 { 1855 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); 1856 } 1857 1858 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, 1859 struct qlcnic_pci_info *info) 1860 { 1861 return adapter->ahw->hw_ops->get_pci_info(adapter, info); 1862 } 1863 1864 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, 1865 struct qlcnic_info *info) 1866 { 1867 return adapter->ahw->hw_ops->set_nic_info(adapter, info); 1868 } 1869 1870 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, 1871 u8 *addr, u16 id, u8 cmd) 1872 { 1873 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); 1874 } 1875 1876 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, 1877 struct net_device *netdev) 1878 { 1879 return adapter->nic_ops->napi_add(adapter, netdev); 1880 } 1881 1882 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter) 1883 { 1884 adapter->nic_ops->napi_del(adapter); 1885 } 1886 1887 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) 1888 { 1889 adapter->ahw->hw_ops->napi_enable(adapter); 1890 } 1891 1892 static inline int __qlcnic_shutdown(struct pci_dev *pdev) 1893 { 1894 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 1895 1896 return adapter->nic_ops->shutdown(pdev); 1897 } 1898 1899 static inline int __qlcnic_resume(struct qlcnic_adapter *adapter) 1900 { 1901 return adapter->nic_ops->resume(adapter); 1902 } 1903 1904 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) 1905 { 1906 adapter->ahw->hw_ops->napi_disable(adapter); 1907 } 1908 1909 static inline void qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter) 1910 { 1911 adapter->ahw->hw_ops->config_intr_coal(adapter); 1912 } 1913 1914 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) 1915 { 1916 return adapter->ahw->hw_ops->config_rss(adapter, enable); 1917 } 1918 1919 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, 1920 int enable) 1921 { 1922 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); 1923 } 1924 1925 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1926 { 1927 return adapter->ahw->hw_ops->config_loopback(adapter, mode); 1928 } 1929 1930 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1931 { 1932 return adapter->ahw->hw_ops->clear_loopback(adapter, mode); 1933 } 1934 1935 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, 1936 u32 mode) 1937 { 1938 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); 1939 } 1940 1941 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, 1942 u64 *addr, u16 id) 1943 { 1944 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id); 1945 } 1946 1947 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) 1948 { 1949 return adapter->ahw->hw_ops->get_board_info(adapter); 1950 } 1951 1952 static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter) 1953 { 1954 return adapter->ahw->hw_ops->free_mac_list(adapter); 1955 } 1956 1957 static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter) 1958 { 1959 if (adapter->ahw->hw_ops->set_mac_filter_count) 1960 adapter->ahw->hw_ops->set_mac_filter_count(adapter); 1961 } 1962 1963 static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter) 1964 { 1965 if (adapter->ahw->hw_ops->read_phys_port_id) 1966 adapter->ahw->hw_ops->read_phys_port_id(adapter); 1967 } 1968 1969 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, 1970 u32 key) 1971 { 1972 if (adapter->nic_ops->request_reset) 1973 adapter->nic_ops->request_reset(adapter, key); 1974 } 1975 1976 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) 1977 { 1978 if (adapter->nic_ops->cancel_idc_work) 1979 adapter->nic_ops->cancel_idc_work(adapter); 1980 } 1981 1982 static inline irqreturn_t 1983 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) 1984 { 1985 return adapter->nic_ops->clear_legacy_intr(adapter); 1986 } 1987 1988 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, 1989 u32 rate) 1990 { 1991 return adapter->nic_ops->config_led(adapter, state, rate); 1992 } 1993 1994 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, 1995 __be32 ip, int cmd) 1996 { 1997 adapter->nic_ops->config_ipaddr(adapter, ip, cmd); 1998 } 1999 2000 static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter) 2001 { 2002 return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); 2003 } 2004 2005 static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter) 2006 { 2007 test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); 2008 adapter->max_drv_tx_rings = 1; 2009 } 2010 2011 /* When operating in a muti tx mode, driver needs to write 0x1 2012 * to src register, instead of 0x0 to disable receiving interrupt. 2013 */ 2014 static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring) 2015 { 2016 struct qlcnic_adapter *adapter = sds_ring->adapter; 2017 2018 if (qlcnic_check_multi_tx(adapter) && 2019 !adapter->ahw->diag_test && 2020 (adapter->flags & QLCNIC_MSIX_ENABLED)) 2021 writel(0x1, sds_ring->crb_intr_mask); 2022 else 2023 writel(0, sds_ring->crb_intr_mask); 2024 } 2025 2026 /* When operating in a muti tx mode, driver needs to write 0x0 2027 * to src register, instead of 0x1 to enable receiving interrupts. 2028 */ 2029 static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring) 2030 { 2031 struct qlcnic_adapter *adapter = sds_ring->adapter; 2032 2033 if (qlcnic_check_multi_tx(adapter) && 2034 !adapter->ahw->diag_test && 2035 (adapter->flags & QLCNIC_MSIX_ENABLED)) 2036 writel(0, sds_ring->crb_intr_mask); 2037 else 2038 writel(0x1, sds_ring->crb_intr_mask); 2039 2040 if (!QLCNIC_IS_MSI_FAMILY(adapter)) 2041 writel(0xfbff, adapter->tgt_mask_reg); 2042 } 2043 2044 static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter) 2045 { 2046 return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2047 } 2048 2049 static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter) 2050 { 2051 clear_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2052 } 2053 2054 static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter) 2055 { 2056 return test_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2057 } 2058 2059 extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops; 2060 extern const struct ethtool_ops qlcnic_ethtool_ops; 2061 extern const struct ethtool_ops qlcnic_ethtool_failed_ops; 2062 2063 #define QLCDB(adapter, lvl, _fmt, _args...) do { \ 2064 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ 2065 printk(KERN_INFO "%s: %s: " _fmt, \ 2066 dev_name(&adapter->pdev->dev), \ 2067 __func__, ##_args); \ 2068 } while (0) 2069 2070 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 2071 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 2072 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430 2073 #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040 2074 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440 2075 2076 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) 2077 { 2078 unsigned short device = adapter->pdev->device; 2079 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; 2080 } 2081 2082 static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter) 2083 { 2084 unsigned short device = adapter->pdev->device; 2085 2086 return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) || 2087 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; 2088 } 2089 2090 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) 2091 { 2092 unsigned short device = adapter->pdev->device; 2093 bool status; 2094 2095 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) || 2096 (device == PCI_DEVICE_ID_QLOGIC_QLE844X) || 2097 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) || 2098 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false; 2099 2100 return status; 2101 } 2102 2103 static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter) 2104 { 2105 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false; 2106 } 2107 2108 static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter) 2109 { 2110 unsigned short device = adapter->pdev->device; 2111 bool status; 2112 2113 status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || 2114 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; 2115 2116 return status; 2117 } 2118 2119 static inline int qlcnic_dcb_get_hw_capability(struct qlcnic_adapter *adapter) 2120 { 2121 struct qlcnic_dcb *dcb = adapter->dcb; 2122 2123 if (dcb && dcb->ops->get_hw_capability) 2124 return dcb->ops->get_hw_capability(adapter); 2125 2126 return 0; 2127 } 2128 2129 static inline void qlcnic_dcb_free(struct qlcnic_adapter *adapter) 2130 { 2131 struct qlcnic_dcb *dcb = adapter->dcb; 2132 2133 if (dcb && dcb->ops->free) 2134 dcb->ops->free(adapter); 2135 } 2136 2137 static inline int qlcnic_dcb_attach(struct qlcnic_adapter *adapter) 2138 { 2139 struct qlcnic_dcb *dcb = adapter->dcb; 2140 2141 if (dcb && dcb->ops->attach) 2142 return dcb->ops->attach(adapter); 2143 2144 return 0; 2145 } 2146 2147 static inline int 2148 qlcnic_dcb_query_hw_capability(struct qlcnic_adapter *adapter, char *buf) 2149 { 2150 struct qlcnic_dcb *dcb = adapter->dcb; 2151 2152 if (dcb && dcb->ops->query_hw_capability) 2153 return dcb->ops->query_hw_capability(adapter, buf); 2154 2155 return 0; 2156 } 2157 2158 static inline void qlcnic_dcb_get_info(struct qlcnic_adapter *adapter) 2159 { 2160 struct qlcnic_dcb *dcb = adapter->dcb; 2161 2162 if (dcb && dcb->ops->get_info) 2163 dcb->ops->get_info(adapter); 2164 } 2165 2166 static inline int 2167 qlcnic_dcb_query_cee_param(struct qlcnic_adapter *adapter, char *buf, u8 type) 2168 { 2169 struct qlcnic_dcb *dcb = adapter->dcb; 2170 2171 if (dcb && dcb->ops->query_cee_param) 2172 return dcb->ops->query_cee_param(adapter, buf, type); 2173 2174 return 0; 2175 } 2176 2177 static inline int qlcnic_dcb_get_cee_cfg(struct qlcnic_adapter *adapter) 2178 { 2179 struct qlcnic_dcb *dcb = adapter->dcb; 2180 2181 if (dcb && dcb->ops->get_cee_cfg) 2182 return dcb->ops->get_cee_cfg(adapter); 2183 2184 return 0; 2185 } 2186 2187 static inline void 2188 qlcnic_dcb_register_aen(struct qlcnic_adapter *adapter, u8 flag) 2189 { 2190 struct qlcnic_dcb *dcb = adapter->dcb; 2191 2192 if (dcb && dcb->ops->register_aen) 2193 dcb->ops->register_aen(adapter, flag); 2194 } 2195 2196 static inline void qlcnic_dcb_handle_aen(struct qlcnic_adapter *adapter, 2197 void *msg) 2198 { 2199 struct qlcnic_dcb *dcb = adapter->dcb; 2200 2201 if (dcb && dcb->ops->handle_aen) 2202 dcb->ops->handle_aen(adapter, msg); 2203 } 2204 2205 static inline void qlcnic_dcb_init_dcbnl_ops(struct qlcnic_adapter *adapter) 2206 { 2207 struct qlcnic_dcb *dcb = adapter->dcb; 2208 2209 if (dcb && dcb->ops->init_dcbnl_ops) 2210 dcb->ops->init_dcbnl_ops(adapter); 2211 } 2212 #endif /* __QLCNIC_H_ */ 2213