1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #ifndef _QLCNIC_H_ 9 #define _QLCNIC_H_ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/ioport.h> 15 #include <linux/pci.h> 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ip.h> 19 #include <linux/in.h> 20 #include <linux/tcp.h> 21 #include <linux/skbuff.h> 22 #include <linux/firmware.h> 23 24 #include <linux/ethtool.h> 25 #include <linux/mii.h> 26 #include <linux/timer.h> 27 28 #include <linux/vmalloc.h> 29 30 #include <linux/io.h> 31 #include <asm/byteorder.h> 32 #include <linux/bitops.h> 33 #include <linux/if_vlan.h> 34 35 #include "qlcnic_hdr.h" 36 #include "qlcnic_hw.h" 37 #include "qlcnic_83xx_hw.h" 38 39 #define _QLCNIC_LINUX_MAJOR 5 40 #define _QLCNIC_LINUX_MINOR 1 41 #define _QLCNIC_LINUX_SUBVERSION 34 42 #define QLCNIC_LINUX_VERSIONID "5.1.34" 43 #define QLCNIC_DRV_IDC_VER 0x01 44 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ 45 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) 46 47 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) 48 #define _major(v) (((v) >> 24) & 0xff) 49 #define _minor(v) (((v) >> 16) & 0xff) 50 #define _build(v) ((v) & 0xffff) 51 52 /* version in image has weird encoding: 53 * 7:0 - major 54 * 15:8 - minor 55 * 31:16 - build (little endian) 56 */ 57 #define QLCNIC_DECODE_VERSION(v) \ 58 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) 59 60 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) 61 #define QLCNIC_NUM_FLASH_SECTORS (64) 62 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) 63 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ 64 * QLCNIC_FLASH_SECTOR_SIZE) 65 66 #define RCV_DESC_RINGSIZE(rds_ring) \ 67 (sizeof(struct rcv_desc) * (rds_ring)->num_desc) 68 #define RCV_BUFF_RINGSIZE(rds_ring) \ 69 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) 70 #define STATUS_DESC_RINGSIZE(sds_ring) \ 71 (sizeof(struct status_desc) * (sds_ring)->num_desc) 72 #define TX_BUFF_RINGSIZE(tx_ring) \ 73 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) 74 #define TX_DESC_RINGSIZE(tx_ring) \ 75 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) 76 77 #define QLCNIC_P3P_A0 0x50 78 #define QLCNIC_P3P_C0 0x58 79 80 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) 81 82 #define FIRST_PAGE_GROUP_START 0 83 #define FIRST_PAGE_GROUP_END 0x100000 84 85 #define P3P_MAX_MTU (9600) 86 #define P3P_MIN_MTU (68) 87 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ 88 89 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) 90 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) 91 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 92 #define QLCNIC_LRO_BUFFER_EXTRA 2048 93 94 /* Tx defines */ 95 #define QLCNIC_MAX_FRAGS_PER_TX 14 96 #define MAX_TSO_HEADER_DESC 2 97 #define MGMT_CMD_DESC_RESV 4 98 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ 99 + MGMT_CMD_DESC_RESV) 100 #define QLCNIC_MAX_TX_TIMEOUTS 2 101 /* 102 * Following are the states of the Phantom. Phantom will set them and 103 * Host will read to check if the fields are correct. 104 */ 105 #define PHAN_INITIALIZE_FAILED 0xffff 106 #define PHAN_INITIALIZE_COMPLETE 0xff01 107 108 /* Host writes the following to notify that it has done the init-handshake */ 109 #define PHAN_INITIALIZE_ACK 0xf00f 110 #define PHAN_PEG_RCV_INITIALIZED 0xff01 111 112 #define NUM_RCV_DESC_RINGS 3 113 114 #define RCV_RING_NORMAL 0 115 #define RCV_RING_JUMBO 1 116 117 #define MIN_CMD_DESCRIPTORS 64 118 #define MIN_RCV_DESCRIPTORS 64 119 #define MIN_JUMBO_DESCRIPTORS 32 120 121 #define MAX_CMD_DESCRIPTORS 1024 122 #define MAX_RCV_DESCRIPTORS_1G 4096 123 #define MAX_RCV_DESCRIPTORS_10G 8192 124 #define MAX_RCV_DESCRIPTORS_VF 2048 125 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 126 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 127 128 #define DEFAULT_RCV_DESCRIPTORS_1G 2048 129 #define DEFAULT_RCV_DESCRIPTORS_10G 4096 130 #define DEFAULT_RCV_DESCRIPTORS_VF 1024 131 #define MAX_RDS_RINGS 2 132 133 #define get_next_index(index, length) \ 134 (((index) + 1) & ((length) - 1)) 135 136 /* 137 * Following data structures describe the descriptors that will be used. 138 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when 139 * we are doing LSO (above the 1500 size packet) only. 140 */ 141 struct cmd_desc_type0 { 142 u8 tcp_hdr_offset; /* For LSO only */ 143 u8 ip_hdr_offset; /* For LSO only */ 144 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ 145 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ 146 147 __le64 addr_buffer2; 148 149 __le16 reference_handle; 150 __le16 mss; 151 u8 port_ctxid; /* 7:4 ctxid 3:0 port */ 152 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ 153 __le16 conn_id; /* IPSec offoad only */ 154 155 __le64 addr_buffer3; 156 __le64 addr_buffer1; 157 158 __le16 buffer_length[4]; 159 160 __le64 addr_buffer4; 161 162 u8 eth_addr[ETH_ALEN]; 163 __le16 vlan_TCI; 164 165 } __attribute__ ((aligned(64))); 166 167 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ 168 struct rcv_desc { 169 __le16 reference_handle; 170 __le16 reserved; 171 __le32 buffer_length; /* allocated buffer length (usually 2K) */ 172 __le64 addr_buffer; 173 } __packed; 174 175 struct status_desc { 176 __le64 status_desc_data[2]; 177 } __attribute__ ((aligned(16))); 178 179 /* UNIFIED ROMIMAGE */ 180 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 181 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 182 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 183 #define QLCNIC_UNI_DIR_SECT_FW 0x7 184 185 /*Offsets */ 186 #define QLCNIC_UNI_CHIP_REV_OFF 10 187 #define QLCNIC_UNI_FLAGS_OFF 11 188 #define QLCNIC_UNI_BIOS_VERSION_OFF 12 189 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 190 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 191 192 struct uni_table_desc{ 193 __le32 findex; 194 __le32 num_entries; 195 __le32 entry_size; 196 __le32 reserved[5]; 197 }; 198 199 struct uni_data_desc{ 200 __le32 findex; 201 __le32 size; 202 __le32 reserved[5]; 203 }; 204 205 /* Flash Defines and Structures */ 206 #define QLCNIC_FLT_LOCATION 0x3F1000 207 #define QLCNIC_FDT_LOCATION 0x3F0000 208 #define QLCNIC_B0_FW_IMAGE_REGION 0x74 209 #define QLCNIC_C0_FW_IMAGE_REGION 0x97 210 #define QLCNIC_BOOTLD_REGION 0X72 211 struct qlcnic_flt_header { 212 u16 version; 213 u16 len; 214 u16 checksum; 215 u16 reserved; 216 }; 217 218 struct qlcnic_flt_entry { 219 u8 region; 220 u8 reserved0; 221 u8 attrib; 222 u8 reserved1; 223 u32 size; 224 u32 start_addr; 225 u32 end_addr; 226 }; 227 228 /* Flash Descriptor Table */ 229 struct qlcnic_fdt { 230 u32 valid; 231 u16 ver; 232 u16 len; 233 u16 cksum; 234 u16 unused; 235 u8 model[16]; 236 u16 mfg_id; 237 u16 id; 238 u8 flag; 239 u8 erase_cmd; 240 u8 alt_erase_cmd; 241 u8 write_enable_cmd; 242 u8 write_enable_bits; 243 u8 write_statusreg_cmd; 244 u8 unprotected_sec_cmd; 245 u8 read_manuf_cmd; 246 u32 block_size; 247 u32 alt_block_size; 248 u32 flash_size; 249 u32 write_enable_data; 250 u8 readid_addr_len; 251 u8 write_disable_bits; 252 u8 read_dev_id_len; 253 u8 chip_erase_cmd; 254 u16 read_timeo; 255 u8 protected_sec_cmd; 256 u8 resvd[65]; 257 }; 258 /* Magic number to let user know flash is programmed */ 259 #define QLCNIC_BDINFO_MAGIC 0x12345678 260 261 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 262 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 263 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 264 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 265 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 266 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 267 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 268 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 269 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 270 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a 271 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b 272 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 273 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 274 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 275 276 #define QLCNIC_MSIX_TABLE_OFFSET 0x44 277 278 /* Flash memory map */ 279 #define QLCNIC_BRDCFG_START 0x4000 /* board config */ 280 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ 281 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ 282 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ 283 284 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) 285 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) 286 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) 287 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) 288 289 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) 290 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) 291 292 #define QLCNIC_FW_MIN_SIZE (0x3fffff) 293 #define QLCNIC_UNIFIED_ROMIMAGE 0 294 #define QLCNIC_FLASH_ROMIMAGE 1 295 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff 296 297 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" 298 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" 299 300 extern char qlcnic_driver_name[]; 301 302 extern int qlcnic_use_msi; 303 extern int qlcnic_use_msi_x; 304 extern int qlcnic_auto_fw_reset; 305 extern int qlcnic_load_fw_file; 306 extern int qlcnic_config_npars; 307 308 /* Number of status descriptors to handle per interrupt */ 309 #define MAX_STATUS_HANDLE (64) 310 311 /* 312 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This 313 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. 314 */ 315 struct qlcnic_skb_frag { 316 u64 dma; 317 u64 length; 318 }; 319 320 /* Following defines are for the state of the buffers */ 321 #define QLCNIC_BUFFER_FREE 0 322 #define QLCNIC_BUFFER_BUSY 1 323 324 /* 325 * There will be one qlcnic_buffer per skb packet. These will be 326 * used to save the dma info for pci_unmap_page() 327 */ 328 struct qlcnic_cmd_buffer { 329 struct sk_buff *skb; 330 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; 331 u32 frag_count; 332 }; 333 334 /* In rx_buffer, we do not need multiple fragments as is a single buffer */ 335 struct qlcnic_rx_buffer { 336 u16 ref_handle; 337 struct sk_buff *skb; 338 struct list_head list; 339 u64 dma; 340 }; 341 342 /* Board types */ 343 #define QLCNIC_GBE 0x01 344 #define QLCNIC_XGBE 0x02 345 346 /* 347 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is 348 * adjusted based on configured MTU. 349 */ 350 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3 351 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256 352 353 #define QLCNIC_INTR_DEFAULT 0x04 354 #define QLCNIC_CONFIG_INTR_COALESCE 3 355 #define QLCNIC_DEV_INFO_SIZE 1 356 357 struct qlcnic_nic_intr_coalesce { 358 u8 type; 359 u8 sts_ring_mask; 360 u16 rx_packets; 361 u16 rx_time_us; 362 u16 flag; 363 u32 timer_out; 364 }; 365 366 struct qlcnic_dump_template_hdr { 367 u32 type; 368 u32 offset; 369 u32 size; 370 u32 cap_mask; 371 u32 num_entries; 372 u32 version; 373 u32 timestamp; 374 u32 checksum; 375 u32 drv_cap_mask; 376 u32 sys_info[3]; 377 u32 saved_state[16]; 378 u32 cap_sizes[8]; 379 u32 ocm_wnd_reg[16]; 380 u32 rsvd[0]; 381 }; 382 383 struct qlcnic_fw_dump { 384 u8 clr; /* flag to indicate if dump is cleared */ 385 u8 enable; /* enable/disable dump */ 386 u32 size; /* total size of the dump */ 387 void *data; /* dump data area */ 388 struct qlcnic_dump_template_hdr *tmpl_hdr; 389 }; 390 391 /* 392 * One hardware_context{} per adapter 393 * contains interrupt info as well shared hardware info. 394 */ 395 struct qlcnic_hardware_context { 396 void __iomem *pci_base0; 397 void __iomem *ocm_win_crb; 398 399 unsigned long pci_len0; 400 401 rwlock_t crb_lock; 402 struct mutex mem_lock; 403 404 u8 revision_id; 405 u8 pci_func; 406 u8 linkup; 407 u8 loopback_state; 408 u8 beacon_state; 409 u8 has_link_events; 410 u8 fw_type; 411 u8 physical_port; 412 u8 reset_context; 413 u8 msix_supported; 414 u8 max_mac_filters; 415 u8 mc_enabled; 416 u8 max_mc_count; 417 u8 diag_test; 418 u8 num_msix; 419 u8 nic_mode; 420 char diag_cnt; 421 422 u16 port_type; 423 u16 board_type; 424 425 u16 link_speed; 426 u16 link_duplex; 427 u16 link_autoneg; 428 u16 module_type; 429 430 u16 op_mode; 431 u16 switch_mode; 432 u16 max_tx_ques; 433 u16 max_rx_ques; 434 u16 max_mtu; 435 u32 msg_enable; 436 u16 act_pci_func; 437 438 u32 capabilities; 439 u32 capabilities2; 440 u32 temp; 441 u32 int_vec_bit; 442 u32 fw_hal_version; 443 u32 port_config; 444 struct qlcnic_hardware_ops *hw_ops; 445 struct qlcnic_nic_intr_coalesce coal; 446 struct qlcnic_fw_dump fw_dump; 447 struct qlcnic_fdt fdt; 448 struct qlc_83xx_reset reset; 449 struct qlc_83xx_idc idc; 450 struct qlc_83xx_fw_info fw_info; 451 struct qlcnic_intrpt_config *intr_tbl; 452 u32 *reg_tbl; 453 u32 *ext_reg_tbl; 454 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; 455 u32 mbox_reg[4]; 456 spinlock_t mbx_lock; 457 }; 458 459 struct qlcnic_adapter_stats { 460 u64 xmitcalled; 461 u64 xmitfinished; 462 u64 rxdropped; 463 u64 txdropped; 464 u64 csummed; 465 u64 rx_pkts; 466 u64 lro_pkts; 467 u64 rxbytes; 468 u64 txbytes; 469 u64 lrobytes; 470 u64 lso_frames; 471 u64 xmit_on; 472 u64 xmit_off; 473 u64 skb_alloc_failure; 474 u64 null_rxbuf; 475 u64 rx_dma_map_error; 476 u64 tx_dma_map_error; 477 u64 spurious_intr; 478 u64 mac_filter_limit_overrun; 479 }; 480 481 /* 482 * Rcv Descriptor Context. One such per Rcv Descriptor. There may 483 * be one Rcv Descriptor for normal packets, one for jumbo and may be others. 484 */ 485 struct qlcnic_host_rds_ring { 486 void __iomem *crb_rcv_producer; 487 struct rcv_desc *desc_head; 488 struct qlcnic_rx_buffer *rx_buf_arr; 489 u32 num_desc; 490 u32 producer; 491 u32 dma_size; 492 u32 skb_size; 493 u32 flags; 494 struct list_head free_list; 495 spinlock_t lock; 496 dma_addr_t phys_addr; 497 } ____cacheline_internodealigned_in_smp; 498 499 struct qlcnic_host_sds_ring { 500 u32 consumer; 501 u32 num_desc; 502 void __iomem *crb_sts_consumer; 503 504 struct status_desc *desc_head; 505 struct qlcnic_adapter *adapter; 506 struct napi_struct napi; 507 struct list_head free_list[NUM_RCV_DESC_RINGS]; 508 509 void __iomem *crb_intr_mask; 510 int irq; 511 512 dma_addr_t phys_addr; 513 char name[IFNAMSIZ+4]; 514 } ____cacheline_internodealigned_in_smp; 515 516 struct qlcnic_host_tx_ring { 517 int irq; 518 void __iomem *crb_intr_mask; 519 char name[IFNAMSIZ+4]; 520 u16 ctx_id; 521 u32 producer; 522 u32 sw_consumer; 523 u32 num_desc; 524 void __iomem *crb_cmd_producer; 525 struct cmd_desc_type0 *desc_head; 526 struct qlcnic_adapter *adapter; 527 struct napi_struct napi; 528 struct qlcnic_cmd_buffer *cmd_buf_arr; 529 __le32 *hw_consumer; 530 531 dma_addr_t phys_addr; 532 dma_addr_t hw_cons_phys_addr; 533 struct netdev_queue *txq; 534 } ____cacheline_internodealigned_in_smp; 535 536 /* 537 * Receive context. There is one such structure per instance of the 538 * receive processing. Any state information that is relevant to 539 * the receive, and is must be in this structure. The global data may be 540 * present elsewhere. 541 */ 542 struct qlcnic_recv_context { 543 struct qlcnic_host_rds_ring *rds_rings; 544 struct qlcnic_host_sds_ring *sds_rings; 545 u32 state; 546 u16 context_id; 547 u16 virt_port; 548 549 }; 550 551 /* HW context creation */ 552 553 #define QLCNIC_OS_CRB_RETRY_COUNT 4000 554 555 #define QLCNIC_CDRP_CMD_BIT 0x80000000 556 557 /* 558 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared 559 * in the crb QLCNIC_CDRP_CRB_OFFSET. 560 */ 561 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) 562 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) 563 564 #define QLCNIC_CDRP_RSP_OK 0x00000001 565 #define QLCNIC_CDRP_RSP_FAIL 0x00000002 566 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 567 568 /* 569 * All commands must have the QLCNIC_CDRP_CMD_BIT set in 570 * the crb QLCNIC_CDRP_CRB_OFFSET. 571 */ 572 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) 573 574 #define QLCNIC_RCODE_SUCCESS 0 575 #define QLCNIC_RCODE_INVALID_ARGS 6 576 #define QLCNIC_RCODE_NOT_SUPPORTED 9 577 #define QLCNIC_RCODE_NOT_PERMITTED 10 578 #define QLCNIC_RCODE_NOT_IMPL 15 579 #define QLCNIC_RCODE_INVALID 16 580 #define QLCNIC_RCODE_TIMEOUT 17 581 #define QLCNIC_DESTROY_CTX_RESET 0 582 583 /* 584 * Capabilities Announced 585 */ 586 #define QLCNIC_CAP0_LEGACY_CONTEXT (1) 587 #define QLCNIC_CAP0_LEGACY_MN (1 << 2) 588 #define QLCNIC_CAP0_LSO (1 << 6) 589 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) 590 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) 591 #define QLCNIC_CAP0_VALIDOFF (1 << 11) 592 #define QLCNIC_CAP0_LRO_MSS (1 << 21) 593 594 /* 595 * Context state 596 */ 597 #define QLCNIC_HOST_CTX_STATE_FREED 0 598 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 599 600 /* 601 * Rx context 602 */ 603 604 struct qlcnic_hostrq_sds_ring { 605 __le64 host_phys_addr; /* Ring base addr */ 606 __le32 ring_size; /* Ring entries */ 607 __le16 msi_index; 608 __le16 rsvd; /* Padding */ 609 } __packed; 610 611 struct qlcnic_hostrq_rds_ring { 612 __le64 host_phys_addr; /* Ring base addr */ 613 __le64 buff_size; /* Packet buffer size */ 614 __le32 ring_size; /* Ring entries */ 615 __le32 ring_kind; /* Class of ring */ 616 } __packed; 617 618 struct qlcnic_hostrq_rx_ctx { 619 __le64 host_rsp_dma_addr; /* Response dma'd here */ 620 __le32 capabilities[4]; /* Flag bit vector */ 621 __le32 host_int_crb_mode; /* Interrupt crb usage */ 622 __le32 host_rds_crb_mode; /* RDS crb usage */ 623 /* These ring offsets are relative to data[0] below */ 624 __le32 rds_ring_offset; /* Offset to RDS config */ 625 __le32 sds_ring_offset; /* Offset to SDS config */ 626 __le16 num_rds_rings; /* Count of RDS rings */ 627 __le16 num_sds_rings; /* Count of SDS rings */ 628 __le16 valid_field_offset; 629 u8 txrx_sds_binding; 630 u8 msix_handler; 631 u8 reserved[128]; /* reserve space for future expansion*/ 632 /* MUST BE 64-bit aligned. 633 The following is packed: 634 - N hostrq_rds_rings 635 - N hostrq_sds_rings */ 636 char data[0]; 637 } __packed; 638 639 struct qlcnic_cardrsp_rds_ring{ 640 __le32 host_producer_crb; /* Crb to use */ 641 __le32 rsvd1; /* Padding */ 642 } __packed; 643 644 struct qlcnic_cardrsp_sds_ring { 645 __le32 host_consumer_crb; /* Crb to use */ 646 __le32 interrupt_crb; /* Crb to use */ 647 } __packed; 648 649 struct qlcnic_cardrsp_rx_ctx { 650 /* These ring offsets are relative to data[0] below */ 651 __le32 rds_ring_offset; /* Offset to RDS config */ 652 __le32 sds_ring_offset; /* Offset to SDS config */ 653 __le32 host_ctx_state; /* Starting State */ 654 __le32 num_fn_per_port; /* How many PCI fn share the port */ 655 __le16 num_rds_rings; /* Count of RDS rings */ 656 __le16 num_sds_rings; /* Count of SDS rings */ 657 __le16 context_id; /* Handle for context */ 658 u8 phys_port; /* Physical id of port */ 659 u8 virt_port; /* Virtual/Logical id of port */ 660 u8 reserved[128]; /* save space for future expansion */ 661 /* MUST BE 64-bit aligned. 662 The following is packed: 663 - N cardrsp_rds_rings 664 - N cardrs_sds_rings */ 665 char data[0]; 666 } __packed; 667 668 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ 669 (sizeof(HOSTRQ_RX) + \ 670 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ 671 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) 672 673 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ 674 (sizeof(CARDRSP_RX) + \ 675 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ 676 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) 677 678 /* 679 * Tx context 680 */ 681 682 struct qlcnic_hostrq_cds_ring { 683 __le64 host_phys_addr; /* Ring base addr */ 684 __le32 ring_size; /* Ring entries */ 685 __le32 rsvd; /* Padding */ 686 } __packed; 687 688 struct qlcnic_hostrq_tx_ctx { 689 __le64 host_rsp_dma_addr; /* Response dma'd here */ 690 __le64 cmd_cons_dma_addr; /* */ 691 __le64 dummy_dma_addr; /* */ 692 __le32 capabilities[4]; /* Flag bit vector */ 693 __le32 host_int_crb_mode; /* Interrupt crb usage */ 694 __le32 rsvd1; /* Padding */ 695 __le16 rsvd2; /* Padding */ 696 __le16 interrupt_ctl; 697 __le16 msi_index; 698 __le16 rsvd3; /* Padding */ 699 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ 700 u8 reserved[128]; /* future expansion */ 701 } __packed; 702 703 struct qlcnic_cardrsp_cds_ring { 704 __le32 host_producer_crb; /* Crb to use */ 705 __le32 interrupt_crb; /* Crb to use */ 706 } __packed; 707 708 struct qlcnic_cardrsp_tx_ctx { 709 __le32 host_ctx_state; /* Starting state */ 710 __le16 context_id; /* Handle for context */ 711 u8 phys_port; /* Physical id of port */ 712 u8 virt_port; /* Virtual/Logical id of port */ 713 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ 714 u8 reserved[128]; /* future expansion */ 715 } __packed; 716 717 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) 718 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) 719 720 /* CRB */ 721 722 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 723 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 724 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 725 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 726 727 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 728 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 729 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 730 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 731 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 732 733 734 /* MAC */ 735 736 #define MC_COUNT_P3P 38 737 738 #define QLCNIC_MAC_NOOP 0 739 #define QLCNIC_MAC_ADD 1 740 #define QLCNIC_MAC_DEL 2 741 #define QLCNIC_MAC_VLAN_ADD 3 742 #define QLCNIC_MAC_VLAN_DEL 4 743 744 struct qlcnic_mac_list_s { 745 struct list_head list; 746 uint8_t mac_addr[ETH_ALEN+2]; 747 }; 748 749 /* MAC Learn */ 750 #define NO_MAC_LEARN 0 751 #define DRV_MAC_LEARN 1 752 #define FDB_MAC_LEARN 2 753 754 #define QLCNIC_HOST_REQUEST 0x13 755 #define QLCNIC_REQUEST 0x14 756 757 #define QLCNIC_MAC_EVENT 0x1 758 759 #define QLCNIC_IP_UP 2 760 #define QLCNIC_IP_DOWN 3 761 762 #define QLCNIC_ILB_MODE 0x1 763 #define QLCNIC_ELB_MODE 0x2 764 765 #define QLCNIC_LINKEVENT 0x1 766 #define QLCNIC_LB_RESPONSE 0x2 767 #define QLCNIC_IS_LB_CONFIGURED(VAL) \ 768 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) 769 770 /* 771 * Driver --> Firmware 772 */ 773 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 774 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 775 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 776 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 777 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc 778 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 779 780 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 781 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 782 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 783 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 784 785 /* 786 * Firmware --> Driver 787 */ 788 789 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f 790 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D 791 792 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ 793 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ 794 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ 795 796 #define QLCNIC_LRO_REQUEST_CLEANUP 4 797 798 /* Capabilites received */ 799 #define QLCNIC_FW_CAPABILITY_TSO BIT_1 800 #define QLCNIC_FW_CAPABILITY_BDG BIT_8 801 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 802 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 803 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 804 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 805 806 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 807 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3 808 #define QLCNIC_FW_CAPABILITY_2_OCBB BIT_5 809 810 /* module types */ 811 #define LINKEVENT_MODULE_NOT_PRESENT 1 812 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 813 #define LINKEVENT_MODULE_OPTICAL_SRLR 3 814 #define LINKEVENT_MODULE_OPTICAL_LRM 4 815 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 816 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 817 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 818 #define LINKEVENT_MODULE_TWINAX 8 819 820 #define LINKSPEED_10GBPS 10000 821 #define LINKSPEED_1GBPS 1000 822 #define LINKSPEED_100MBPS 100 823 #define LINKSPEED_10MBPS 10 824 825 #define LINKSPEED_ENCODED_10MBPS 0 826 #define LINKSPEED_ENCODED_100MBPS 1 827 #define LINKSPEED_ENCODED_1GBPS 2 828 829 #define LINKEVENT_AUTONEG_DISABLED 0 830 #define LINKEVENT_AUTONEG_ENABLED 1 831 832 #define LINKEVENT_HALF_DUPLEX 0 833 #define LINKEVENT_FULL_DUPLEX 1 834 835 #define LINKEVENT_LINKSPEED_MBPS 0 836 #define LINKEVENT_LINKSPEED_ENCODED 1 837 838 /* firmware response header: 839 * 63:58 - message type 840 * 57:56 - owner 841 * 55:53 - desc count 842 * 52:48 - reserved 843 * 47:40 - completion id 844 * 39:32 - opcode 845 * 31:16 - error code 846 * 15:00 - reserved 847 */ 848 #define qlcnic_get_nic_msg_opcode(msg_hdr) \ 849 ((msg_hdr >> 32) & 0xFF) 850 851 struct qlcnic_fw_msg { 852 union { 853 struct { 854 u64 hdr; 855 u64 body[7]; 856 }; 857 u64 words[8]; 858 }; 859 }; 860 861 struct qlcnic_nic_req { 862 __le64 qhdr; 863 __le64 req_hdr; 864 __le64 words[6]; 865 } __packed; 866 867 struct qlcnic_mac_req { 868 u8 op; 869 u8 tag; 870 u8 mac_addr[6]; 871 }; 872 873 struct qlcnic_vlan_req { 874 __le16 vlan_id; 875 __le16 rsvd[3]; 876 } __packed; 877 878 struct qlcnic_ipaddr { 879 __be32 ipv4; 880 __be32 ipv6[4]; 881 }; 882 883 #define QLCNIC_MSI_ENABLED 0x02 884 #define QLCNIC_MSIX_ENABLED 0x04 885 #define QLCNIC_LRO_ENABLED 0x01 886 #define QLCNIC_LRO_DISABLED 0x00 887 #define QLCNIC_BRIDGE_ENABLED 0X10 888 #define QLCNIC_DIAG_ENABLED 0x20 889 #define QLCNIC_ESWITCH_ENABLED 0x40 890 #define QLCNIC_ADAPTER_INITIALIZED 0x80 891 #define QLCNIC_TAGGING_ENABLED 0x100 892 #define QLCNIC_MACSPOOF 0x200 893 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 894 #define QLCNIC_PROMISC_DISABLED 0x800 895 #define QLCNIC_NEED_FLR 0x1000 896 #define QLCNIC_FW_RESET_OWNER 0x2000 897 #define QLCNIC_FW_HANG 0x4000 898 #define QLCNIC_FW_LRO_MSS_CAP 0x8000 899 #define QLCNIC_IS_MSI_FAMILY(adapter) \ 900 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) 901 902 #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4 903 #define QLCNIC_MSIX_TBL_SPACE 8192 904 #define QLCNIC_PCI_REG_MSIX_TBL 0x44 905 #define QLCNIC_MSIX_TBL_PGSIZE 4096 906 907 #define QLCNIC_NETDEV_WEIGHT 128 908 #define QLCNIC_ADAPTER_UP_MAGIC 777 909 910 #define __QLCNIC_FW_ATTACHED 0 911 #define __QLCNIC_DEV_UP 1 912 #define __QLCNIC_RESETTING 2 913 #define __QLCNIC_START_FW 4 914 #define __QLCNIC_AER 5 915 #define __QLCNIC_DIAG_RES_ALLOC 6 916 #define __QLCNIC_LED_ENABLE 7 917 #define __QLCNIC_ELB_INPROGRESS 8 918 919 #define QLCNIC_INTERRUPT_TEST 1 920 #define QLCNIC_LOOPBACK_TEST 2 921 #define QLCNIC_LED_TEST 3 922 923 #define QLCNIC_FILTER_AGE 80 924 #define QLCNIC_READD_AGE 20 925 #define QLCNIC_LB_MAX_FILTERS 64 926 #define QLCNIC_LB_BUCKET_SIZE 32 927 928 /* QLCNIC Driver Error Code */ 929 #define QLCNIC_FW_NOT_RESPOND 51 930 #define QLCNIC_TEST_IN_PROGRESS 52 931 #define QLCNIC_UNDEFINED_ERROR 53 932 #define QLCNIC_LB_CABLE_NOT_CONN 54 933 #define QLCNIC_ILB_MAX_RCV_LOOP 10 934 935 struct qlcnic_filter { 936 struct hlist_node fnode; 937 u8 faddr[ETH_ALEN]; 938 __le16 vlan_id; 939 unsigned long ftime; 940 }; 941 942 struct qlcnic_filter_hash { 943 struct hlist_head *fhead; 944 u8 fnum; 945 u16 fmax; 946 u16 fbucket_size; 947 }; 948 949 struct qlcnic_adapter { 950 struct qlcnic_hardware_context *ahw; 951 struct qlcnic_recv_context *recv_ctx; 952 struct qlcnic_host_tx_ring *tx_ring; 953 struct net_device *netdev; 954 struct pci_dev *pdev; 955 956 unsigned long state; 957 u32 flags; 958 959 int max_drv_tx_rings; 960 u16 num_txd; 961 u16 num_rxd; 962 u16 num_jumbo_rxd; 963 u16 max_rxd; 964 u16 max_jumbo_rxd; 965 966 u8 max_rds_rings; 967 u8 max_sds_rings; 968 u8 rx_csum; 969 u8 portnum; 970 971 u8 fw_wait_cnt; 972 u8 fw_fail_cnt; 973 u8 tx_timeo_cnt; 974 u8 need_fw_reset; 975 976 u16 is_up; 977 u16 pvid; 978 979 u32 irq; 980 u32 heartbeat; 981 982 u8 dev_state; 983 u8 reset_ack_timeo; 984 u8 dev_init_timeo; 985 986 u8 mac_addr[ETH_ALEN]; 987 988 u64 dev_rst_time; 989 bool drv_mac_learn; 990 bool fdb_mac_learn; 991 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; 992 u8 flash_mfg_id; 993 struct qlcnic_npar_info *npars; 994 struct qlcnic_eswitch *eswitch; 995 struct qlcnic_nic_template *nic_ops; 996 997 struct qlcnic_adapter_stats stats; 998 struct list_head mac_list; 999 1000 void __iomem *tgt_mask_reg; 1001 void __iomem *tgt_status_reg; 1002 void __iomem *crb_int_state_reg; 1003 void __iomem *isr_int_vec; 1004 1005 struct msix_entry *msix_entries; 1006 struct workqueue_struct *qlcnic_wq; 1007 struct delayed_work fw_work; 1008 struct delayed_work idc_aen_work; 1009 1010 struct qlcnic_filter_hash fhash; 1011 struct qlcnic_filter_hash rx_fhash; 1012 1013 spinlock_t tx_clean_lock; 1014 spinlock_t mac_learn_lock; 1015 /* spinlock for catching rcv filters for eswitch traffic */ 1016 spinlock_t rx_mac_learn_lock; 1017 u32 file_prd_off; /*File fw product offset*/ 1018 u32 fw_version; 1019 const struct firmware *fw; 1020 }; 1021 1022 struct qlcnic_info_le { 1023 __le16 pci_func; 1024 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ 1025 __le16 phys_port; 1026 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ 1027 1028 __le32 capabilities; 1029 u8 max_mac_filters; 1030 u8 reserved1; 1031 __le16 max_mtu; 1032 1033 __le16 max_tx_ques; 1034 __le16 max_rx_ques; 1035 __le16 min_tx_bw; 1036 __le16 max_tx_bw; 1037 __le32 op_type; 1038 __le16 max_bw_reg_offset; 1039 __le16 max_linkspeed_reg_offset; 1040 __le32 capability1; 1041 __le32 capability2; 1042 __le32 capability3; 1043 __le16 max_tx_mac_filters; 1044 __le16 max_rx_mcast_mac_filters; 1045 __le16 max_rx_ucast_mac_filters; 1046 __le16 max_rx_ip_addr; 1047 __le16 max_rx_lro_flow; 1048 __le16 max_rx_status_rings; 1049 __le16 max_rx_buf_rings; 1050 __le16 max_tx_vlan_keys; 1051 u8 total_pf; 1052 u8 total_rss_engines; 1053 __le16 max_vports; 1054 u8 reserved2[64]; 1055 } __packed; 1056 1057 struct qlcnic_info { 1058 u16 pci_func; 1059 u16 op_mode; 1060 u16 phys_port; 1061 u16 switch_mode; 1062 u32 capabilities; 1063 u8 max_mac_filters; 1064 u16 max_mtu; 1065 u16 max_tx_ques; 1066 u16 max_rx_ques; 1067 u16 min_tx_bw; 1068 u16 max_tx_bw; 1069 u32 op_type; 1070 u16 max_bw_reg_offset; 1071 u16 max_linkspeed_reg_offset; 1072 u32 capability1; 1073 u32 capability2; 1074 u32 capability3; 1075 u16 max_tx_mac_filters; 1076 u16 max_rx_mcast_mac_filters; 1077 u16 max_rx_ucast_mac_filters; 1078 u16 max_rx_ip_addr; 1079 u16 max_rx_lro_flow; 1080 u16 max_rx_status_rings; 1081 u16 max_rx_buf_rings; 1082 u16 max_tx_vlan_keys; 1083 u8 total_pf; 1084 u8 total_rss_engines; 1085 u16 max_vports; 1086 }; 1087 1088 struct qlcnic_pci_info_le { 1089 __le16 id; /* pci function id */ 1090 __le16 active; /* 1 = Enabled */ 1091 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ 1092 __le16 default_port; /* default port number */ 1093 1094 __le16 tx_min_bw; /* Multiple of 100mbpc */ 1095 __le16 tx_max_bw; 1096 __le16 reserved1[2]; 1097 1098 u8 mac[ETH_ALEN]; 1099 __le16 func_count; 1100 u8 reserved2[104]; 1101 1102 } __packed; 1103 1104 struct qlcnic_pci_info { 1105 u16 id; 1106 u16 active; 1107 u16 type; 1108 u16 default_port; 1109 u16 tx_min_bw; 1110 u16 tx_max_bw; 1111 u8 mac[ETH_ALEN]; 1112 u16 func_count; 1113 }; 1114 1115 struct qlcnic_npar_info { 1116 u16 pvid; 1117 u16 min_bw; 1118 u16 max_bw; 1119 u8 phy_port; 1120 u8 type; 1121 u8 active; 1122 u8 enable_pm; 1123 u8 dest_npar; 1124 u8 discard_tagged; 1125 u8 mac_override; 1126 u8 mac_anti_spoof; 1127 u8 promisc_mode; 1128 u8 offload_flags; 1129 u8 pci_func; 1130 }; 1131 1132 struct qlcnic_eswitch { 1133 u8 port; 1134 u8 active_vports; 1135 u8 active_vlans; 1136 u8 active_ucast_filters; 1137 u8 max_ucast_filters; 1138 u8 max_active_vlans; 1139 1140 u32 flags; 1141 #define QLCNIC_SWITCH_ENABLE BIT_1 1142 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 1143 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 1144 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 1145 }; 1146 1147 1148 /* Return codes for Error handling */ 1149 #define QL_STATUS_INVALID_PARAM -1 1150 1151 #define MAX_BW 100 /* % of link speed */ 1152 #define MAX_VLAN_ID 4095 1153 #define MIN_VLAN_ID 2 1154 #define DEFAULT_MAC_LEARN 1 1155 1156 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) 1157 #define IS_VALID_BW(bw) (bw <= MAX_BW) 1158 1159 struct qlcnic_pci_func_cfg { 1160 u16 func_type; 1161 u16 min_bw; 1162 u16 max_bw; 1163 u16 port_num; 1164 u8 pci_func; 1165 u8 func_state; 1166 u8 def_mac_addr[6]; 1167 }; 1168 1169 struct qlcnic_npar_func_cfg { 1170 u32 fw_capab; 1171 u16 port_num; 1172 u16 min_bw; 1173 u16 max_bw; 1174 u16 max_tx_queues; 1175 u16 max_rx_queues; 1176 u8 pci_func; 1177 u8 op_mode; 1178 }; 1179 1180 struct qlcnic_pm_func_cfg { 1181 u8 pci_func; 1182 u8 action; 1183 u8 dest_npar; 1184 u8 reserved[5]; 1185 }; 1186 1187 struct qlcnic_esw_func_cfg { 1188 u16 vlan_id; 1189 u8 op_mode; 1190 u8 op_type; 1191 u8 pci_func; 1192 u8 host_vlan_tag; 1193 u8 promisc_mode; 1194 u8 discard_tagged; 1195 u8 mac_override; 1196 u8 mac_anti_spoof; 1197 u8 offload_flags; 1198 u8 reserved[5]; 1199 }; 1200 1201 #define QLCNIC_STATS_VERSION 1 1202 #define QLCNIC_STATS_PORT 1 1203 #define QLCNIC_STATS_ESWITCH 2 1204 #define QLCNIC_QUERY_RX_COUNTER 0 1205 #define QLCNIC_QUERY_TX_COUNTER 1 1206 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL 1207 #define QLCNIC_FILL_STATS(VAL1) \ 1208 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) 1209 #define QLCNIC_MAC_STATS 1 1210 #define QLCNIC_ESW_STATS 2 1211 1212 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ 1213 do { \ 1214 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ 1215 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1216 (VAL1) = (VAL2); \ 1217 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ 1218 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1219 (VAL1) += (VAL2); \ 1220 } while (0) 1221 1222 struct qlcnic_mac_statistics_le { 1223 __le64 mac_tx_frames; 1224 __le64 mac_tx_bytes; 1225 __le64 mac_tx_mcast_pkts; 1226 __le64 mac_tx_bcast_pkts; 1227 __le64 mac_tx_pause_cnt; 1228 __le64 mac_tx_ctrl_pkt; 1229 __le64 mac_tx_lt_64b_pkts; 1230 __le64 mac_tx_lt_127b_pkts; 1231 __le64 mac_tx_lt_255b_pkts; 1232 __le64 mac_tx_lt_511b_pkts; 1233 __le64 mac_tx_lt_1023b_pkts; 1234 __le64 mac_tx_lt_1518b_pkts; 1235 __le64 mac_tx_gt_1518b_pkts; 1236 __le64 rsvd1[3]; 1237 1238 __le64 mac_rx_frames; 1239 __le64 mac_rx_bytes; 1240 __le64 mac_rx_mcast_pkts; 1241 __le64 mac_rx_bcast_pkts; 1242 __le64 mac_rx_pause_cnt; 1243 __le64 mac_rx_ctrl_pkt; 1244 __le64 mac_rx_lt_64b_pkts; 1245 __le64 mac_rx_lt_127b_pkts; 1246 __le64 mac_rx_lt_255b_pkts; 1247 __le64 mac_rx_lt_511b_pkts; 1248 __le64 mac_rx_lt_1023b_pkts; 1249 __le64 mac_rx_lt_1518b_pkts; 1250 __le64 mac_rx_gt_1518b_pkts; 1251 __le64 rsvd2[3]; 1252 1253 __le64 mac_rx_length_error; 1254 __le64 mac_rx_length_small; 1255 __le64 mac_rx_length_large; 1256 __le64 mac_rx_jabber; 1257 __le64 mac_rx_dropped; 1258 __le64 mac_rx_crc_error; 1259 __le64 mac_align_error; 1260 } __packed; 1261 1262 struct qlcnic_mac_statistics { 1263 u64 mac_tx_frames; 1264 u64 mac_tx_bytes; 1265 u64 mac_tx_mcast_pkts; 1266 u64 mac_tx_bcast_pkts; 1267 u64 mac_tx_pause_cnt; 1268 u64 mac_tx_ctrl_pkt; 1269 u64 mac_tx_lt_64b_pkts; 1270 u64 mac_tx_lt_127b_pkts; 1271 u64 mac_tx_lt_255b_pkts; 1272 u64 mac_tx_lt_511b_pkts; 1273 u64 mac_tx_lt_1023b_pkts; 1274 u64 mac_tx_lt_1518b_pkts; 1275 u64 mac_tx_gt_1518b_pkts; 1276 u64 rsvd1[3]; 1277 u64 mac_rx_frames; 1278 u64 mac_rx_bytes; 1279 u64 mac_rx_mcast_pkts; 1280 u64 mac_rx_bcast_pkts; 1281 u64 mac_rx_pause_cnt; 1282 u64 mac_rx_ctrl_pkt; 1283 u64 mac_rx_lt_64b_pkts; 1284 u64 mac_rx_lt_127b_pkts; 1285 u64 mac_rx_lt_255b_pkts; 1286 u64 mac_rx_lt_511b_pkts; 1287 u64 mac_rx_lt_1023b_pkts; 1288 u64 mac_rx_lt_1518b_pkts; 1289 u64 mac_rx_gt_1518b_pkts; 1290 u64 rsvd2[3]; 1291 u64 mac_rx_length_error; 1292 u64 mac_rx_length_small; 1293 u64 mac_rx_length_large; 1294 u64 mac_rx_jabber; 1295 u64 mac_rx_dropped; 1296 u64 mac_rx_crc_error; 1297 u64 mac_align_error; 1298 }; 1299 1300 struct qlcnic_esw_stats_le { 1301 __le16 context_id; 1302 __le16 version; 1303 __le16 size; 1304 __le16 unused; 1305 __le64 unicast_frames; 1306 __le64 multicast_frames; 1307 __le64 broadcast_frames; 1308 __le64 dropped_frames; 1309 __le64 errors; 1310 __le64 local_frames; 1311 __le64 numbytes; 1312 __le64 rsvd[3]; 1313 } __packed; 1314 1315 struct __qlcnic_esw_statistics { 1316 u16 context_id; 1317 u16 version; 1318 u16 size; 1319 u16 unused; 1320 u64 unicast_frames; 1321 u64 multicast_frames; 1322 u64 broadcast_frames; 1323 u64 dropped_frames; 1324 u64 errors; 1325 u64 local_frames; 1326 u64 numbytes; 1327 u64 rsvd[3]; 1328 }; 1329 1330 struct qlcnic_esw_statistics { 1331 struct __qlcnic_esw_statistics rx; 1332 struct __qlcnic_esw_statistics tx; 1333 }; 1334 1335 #define QLCNIC_DUMP_MASK_DEF 0x1f 1336 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed 1337 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed 1338 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed 1339 #define QLCNIC_FORCE_FW_RESET 0xdeaddead 1340 #define QLCNIC_SET_QUIESCENT 0xadd00010 1341 #define QLCNIC_RESET_QUIESCENT 0xadd00020 1342 1343 struct _cdrp_cmd { 1344 u32 num; 1345 u32 *arg; 1346 }; 1347 1348 struct qlcnic_cmd_args { 1349 struct _cdrp_cmd req; 1350 struct _cdrp_cmd rsp; 1351 }; 1352 1353 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); 1354 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); 1355 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); 1356 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); 1357 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); 1358 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); 1359 1360 #define ADDR_IN_RANGE(addr, low, high) \ 1361 (((addr) < (high)) && ((addr) >= (low))) 1362 1363 #define QLCRD32(adapter, off) \ 1364 (adapter->ahw->hw_ops->read_reg)(adapter, off) 1365 1366 #define QLCWR32(adapter, off, val) \ 1367 adapter->ahw->hw_ops->write_reg(adapter, off, val) 1368 1369 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); 1370 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); 1371 1372 #define qlcnic_rom_lock(a) \ 1373 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) 1374 #define qlcnic_rom_unlock(a) \ 1375 qlcnic_pcie_sem_unlock((a), 2) 1376 #define qlcnic_phy_lock(a) \ 1377 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) 1378 #define qlcnic_phy_unlock(a) \ 1379 qlcnic_pcie_sem_unlock((a), 3) 1380 #define qlcnic_sw_lock(a) \ 1381 qlcnic_pcie_sem_lock((a), 6, 0) 1382 #define qlcnic_sw_unlock(a) \ 1383 qlcnic_pcie_sem_unlock((a), 6) 1384 #define crb_win_lock(a) \ 1385 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) 1386 #define crb_win_unlock(a) \ 1387 qlcnic_pcie_sem_unlock((a), 7) 1388 1389 #define __QLCNIC_MAX_LED_RATE 0xf 1390 #define __QLCNIC_MAX_LED_STATE 0x2 1391 1392 #define MAX_CTL_CHECK 1000 1393 1394 int qlcnic_wol_supported(struct qlcnic_adapter *adapter); 1395 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); 1396 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); 1397 int qlcnic_dump_fw(struct qlcnic_adapter *); 1398 1399 /* Functions from qlcnic_init.c */ 1400 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int); 1401 int qlcnic_load_firmware(struct qlcnic_adapter *adapter); 1402 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); 1403 void qlcnic_request_firmware(struct qlcnic_adapter *adapter); 1404 void qlcnic_release_firmware(struct qlcnic_adapter *adapter); 1405 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); 1406 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); 1407 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); 1408 1409 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); 1410 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, 1411 u8 *bytes, size_t size); 1412 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); 1413 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); 1414 1415 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); 1416 1417 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); 1418 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); 1419 1420 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); 1421 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); 1422 1423 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); 1424 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); 1425 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter); 1426 1427 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); 1428 void qlcnic_watchdog_task(struct work_struct *work); 1429 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, 1430 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id); 1431 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); 1432 void qlcnic_set_multi(struct net_device *netdev); 1433 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *); 1434 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *); 1435 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter); 1436 1437 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); 1438 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *); 1439 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); 1440 netdev_features_t qlcnic_fix_features(struct net_device *netdev, 1441 netdev_features_t features); 1442 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); 1443 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); 1444 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); 1445 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); 1446 1447 /* Functions from qlcnic_ethtool.c */ 1448 int qlcnic_check_loopback_buff(unsigned char *, u8 []); 1449 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8); 1450 int qlcnic_loopback_test(struct net_device *, u8); 1451 1452 /* Functions from qlcnic_main.c */ 1453 int qlcnic_reset_context(struct qlcnic_adapter *); 1454 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); 1455 int qlcnic_diag_alloc_res(struct net_device *netdev, int test); 1456 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 1457 int qlcnic_set_max_rss(struct qlcnic_adapter *, u8, size_t); 1458 int qlcnic_validate_max_rss(u8, u8); 1459 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); 1460 int qlcnic_enable_msix(struct qlcnic_adapter *, u32); 1461 1462 /* eSwitch management functions */ 1463 int qlcnic_config_switch_port(struct qlcnic_adapter *, 1464 struct qlcnic_esw_func_cfg *); 1465 1466 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, 1467 struct qlcnic_esw_func_cfg *); 1468 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); 1469 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, 1470 struct __qlcnic_esw_statistics *); 1471 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, 1472 struct __qlcnic_esw_statistics *); 1473 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); 1474 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); 1475 1476 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); 1477 1478 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); 1479 void qlcnic_free_sds_rings(struct qlcnic_recv_context *); 1480 void qlcnic_advert_link_change(struct qlcnic_adapter *, int); 1481 void qlcnic_free_tx_rings(struct qlcnic_adapter *); 1482 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); 1483 1484 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); 1485 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); 1486 void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter); 1487 void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter); 1488 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); 1489 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); 1490 1491 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); 1492 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); 1493 void qlcnic_set_vlan_config(struct qlcnic_adapter *, 1494 struct qlcnic_esw_func_cfg *); 1495 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, 1496 struct qlcnic_esw_func_cfg *); 1497 1498 void qlcnic_down(struct qlcnic_adapter *, struct net_device *); 1499 int qlcnic_up(struct qlcnic_adapter *, struct net_device *); 1500 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *); 1501 void qlcnic_detach(struct qlcnic_adapter *); 1502 void qlcnic_teardown_intr(struct qlcnic_adapter *); 1503 int qlcnic_attach(struct qlcnic_adapter *); 1504 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *); 1505 void qlcnic_restore_indev_addr(struct net_device *, unsigned long); 1506 1507 int qlcnic_check_temp(struct qlcnic_adapter *); 1508 int qlcnic_init_pci_info(struct qlcnic_adapter *); 1509 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *); 1510 int qlcnic_reset_npar_config(struct qlcnic_adapter *); 1511 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *); 1512 void qlcnic_add_lb_filter(struct qlcnic_adapter *, struct sk_buff *, int, 1513 __le16); 1514 /* 1515 * QLOGIC Board information 1516 */ 1517 1518 #define QLCNIC_MAX_BOARD_NAME_LEN 100 1519 struct qlcnic_board_info { 1520 unsigned short vendor; 1521 unsigned short device; 1522 unsigned short sub_vendor; 1523 unsigned short sub_device; 1524 char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; 1525 }; 1526 1527 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) 1528 { 1529 if (likely(tx_ring->producer < tx_ring->sw_consumer)) 1530 return tx_ring->sw_consumer - tx_ring->producer; 1531 else 1532 return tx_ring->sw_consumer + tx_ring->num_desc - 1533 tx_ring->producer; 1534 } 1535 1536 struct qlcnic_nic_template { 1537 int (*config_bridged_mode) (struct qlcnic_adapter *, u32); 1538 int (*config_led) (struct qlcnic_adapter *, u32, u32); 1539 int (*start_firmware) (struct qlcnic_adapter *); 1540 int (*init_driver) (struct qlcnic_adapter *); 1541 void (*request_reset) (struct qlcnic_adapter *, u32); 1542 void (*cancel_idc_work) (struct qlcnic_adapter *); 1543 int (*napi_add)(struct qlcnic_adapter *, struct net_device *); 1544 void (*napi_del)(struct qlcnic_adapter *); 1545 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); 1546 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); 1547 }; 1548 1549 /* Adapter hardware abstraction */ 1550 struct qlcnic_hardware_ops { 1551 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); 1552 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); 1553 int (*read_reg) (struct qlcnic_adapter *, ulong); 1554 int (*write_reg) (struct qlcnic_adapter *, ulong, u32); 1555 void (*get_ocm_win) (struct qlcnic_hardware_context *); 1556 int (*get_mac_address) (struct qlcnic_adapter *, u8 *); 1557 int (*setup_intr) (struct qlcnic_adapter *, u8); 1558 int (*alloc_mbx_args)(struct qlcnic_cmd_args *, 1559 struct qlcnic_adapter *, u32); 1560 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1561 void (*get_func_no) (struct qlcnic_adapter *); 1562 int (*api_lock) (struct qlcnic_adapter *); 1563 void (*api_unlock) (struct qlcnic_adapter *); 1564 void (*add_sysfs) (struct qlcnic_adapter *); 1565 void (*remove_sysfs) (struct qlcnic_adapter *); 1566 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); 1567 int (*create_rx_ctx) (struct qlcnic_adapter *); 1568 int (*create_tx_ctx) (struct qlcnic_adapter *, 1569 struct qlcnic_host_tx_ring *, int); 1570 int (*setup_link_event) (struct qlcnic_adapter *, int); 1571 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); 1572 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); 1573 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); 1574 int (*change_macvlan) (struct qlcnic_adapter *, u8*, __le16, u8); 1575 void (*napi_enable) (struct qlcnic_adapter *); 1576 void (*napi_disable) (struct qlcnic_adapter *); 1577 void (*config_intr_coal) (struct qlcnic_adapter *); 1578 int (*config_rss) (struct qlcnic_adapter *, int); 1579 int (*config_hw_lro) (struct qlcnic_adapter *, int); 1580 int (*config_loopback) (struct qlcnic_adapter *, u8); 1581 int (*clear_loopback) (struct qlcnic_adapter *, u8); 1582 int (*config_promisc_mode) (struct qlcnic_adapter *, u32); 1583 void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, __le16); 1584 int (*get_board_info) (struct qlcnic_adapter *); 1585 }; 1586 1587 extern struct qlcnic_nic_template qlcnic_vf_ops; 1588 1589 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) 1590 { 1591 return adapter->nic_ops->start_firmware(adapter); 1592 } 1593 1594 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, 1595 loff_t offset, size_t size) 1596 { 1597 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); 1598 } 1599 1600 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, 1601 loff_t offset, size_t size) 1602 { 1603 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); 1604 } 1605 1606 static inline int qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, 1607 ulong off) 1608 { 1609 return adapter->ahw->hw_ops->read_reg(adapter, off); 1610 } 1611 1612 static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, 1613 ulong off, u32 data) 1614 { 1615 return adapter->ahw->hw_ops->write_reg(adapter, off, data); 1616 } 1617 1618 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, 1619 u8 *mac) 1620 { 1621 return adapter->ahw->hw_ops->get_mac_address(adapter, mac); 1622 } 1623 1624 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr) 1625 { 1626 return adapter->ahw->hw_ops->setup_intr(adapter, num_intr); 1627 } 1628 1629 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, 1630 struct qlcnic_adapter *adapter, u32 arg) 1631 { 1632 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); 1633 } 1634 1635 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, 1636 struct qlcnic_cmd_args *cmd) 1637 { 1638 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); 1639 } 1640 1641 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) 1642 { 1643 adapter->ahw->hw_ops->get_func_no(adapter); 1644 } 1645 1646 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) 1647 { 1648 return adapter->ahw->hw_ops->api_lock(adapter); 1649 } 1650 1651 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) 1652 { 1653 adapter->ahw->hw_ops->api_unlock(adapter); 1654 } 1655 1656 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) 1657 { 1658 adapter->ahw->hw_ops->add_sysfs(adapter); 1659 } 1660 1661 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) 1662 { 1663 adapter->ahw->hw_ops->remove_sysfs(adapter); 1664 } 1665 1666 static inline void 1667 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) 1668 { 1669 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); 1670 } 1671 1672 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) 1673 { 1674 return adapter->ahw->hw_ops->create_rx_ctx(adapter); 1675 } 1676 1677 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, 1678 struct qlcnic_host_tx_ring *ptr, 1679 int ring) 1680 { 1681 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); 1682 } 1683 1684 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, 1685 int enable) 1686 { 1687 return adapter->ahw->hw_ops->setup_link_event(adapter, enable); 1688 } 1689 1690 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, 1691 struct qlcnic_info *info, u8 id) 1692 { 1693 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); 1694 } 1695 1696 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, 1697 struct qlcnic_pci_info *info) 1698 { 1699 return adapter->ahw->hw_ops->get_pci_info(adapter, info); 1700 } 1701 1702 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, 1703 struct qlcnic_info *info) 1704 { 1705 return adapter->ahw->hw_ops->set_nic_info(adapter, info); 1706 } 1707 1708 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, 1709 u8 *addr, __le16 id, u8 cmd) 1710 { 1711 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); 1712 } 1713 1714 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, 1715 struct net_device *netdev) 1716 { 1717 return adapter->nic_ops->napi_add(adapter, netdev); 1718 } 1719 1720 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter) 1721 { 1722 adapter->nic_ops->napi_del(adapter); 1723 } 1724 1725 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) 1726 { 1727 adapter->ahw->hw_ops->napi_enable(adapter); 1728 } 1729 1730 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) 1731 { 1732 adapter->ahw->hw_ops->napi_disable(adapter); 1733 } 1734 1735 static inline void qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter) 1736 { 1737 adapter->ahw->hw_ops->config_intr_coal(adapter); 1738 } 1739 1740 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) 1741 { 1742 return adapter->ahw->hw_ops->config_rss(adapter, enable); 1743 } 1744 1745 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, 1746 int enable) 1747 { 1748 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); 1749 } 1750 1751 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1752 { 1753 return adapter->ahw->hw_ops->config_loopback(adapter, mode); 1754 } 1755 1756 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1757 { 1758 return adapter->ahw->hw_ops->config_loopback(adapter, mode); 1759 } 1760 1761 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, 1762 u32 mode) 1763 { 1764 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); 1765 } 1766 1767 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, 1768 u64 *addr, __le16 id) 1769 { 1770 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id); 1771 } 1772 1773 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) 1774 { 1775 return adapter->ahw->hw_ops->get_board_info(adapter); 1776 } 1777 1778 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, 1779 u32 key) 1780 { 1781 adapter->nic_ops->request_reset(adapter, key); 1782 } 1783 1784 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) 1785 { 1786 adapter->nic_ops->cancel_idc_work(adapter); 1787 } 1788 1789 static inline irqreturn_t 1790 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) 1791 { 1792 return adapter->nic_ops->clear_legacy_intr(adapter); 1793 } 1794 1795 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, 1796 u32 rate) 1797 { 1798 return adapter->nic_ops->config_led(adapter, state, rate); 1799 } 1800 1801 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, 1802 __be32 ip, int cmd) 1803 { 1804 adapter->nic_ops->config_ipaddr(adapter, ip, cmd); 1805 } 1806 1807 static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring) 1808 { 1809 writel(0, sds_ring->crb_intr_mask); 1810 } 1811 1812 static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring) 1813 { 1814 struct qlcnic_adapter *adapter = sds_ring->adapter; 1815 1816 writel(0x1, sds_ring->crb_intr_mask); 1817 1818 if (!QLCNIC_IS_MSI_FAMILY(adapter)) 1819 writel(0xfbff, adapter->tgt_mask_reg); 1820 } 1821 1822 extern const struct ethtool_ops qlcnic_ethtool_ops; 1823 extern const struct ethtool_ops qlcnic_ethtool_failed_ops; 1824 1825 #define QLCDB(adapter, lvl, _fmt, _args...) do { \ 1826 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ 1827 printk(KERN_INFO "%s: %s: " _fmt, \ 1828 dev_name(&adapter->pdev->dev), \ 1829 __func__, ##_args); \ 1830 } while (0) 1831 1832 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 1833 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 1834 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) 1835 { 1836 unsigned short device = adapter->pdev->device; 1837 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; 1838 } 1839 1840 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) 1841 { 1842 unsigned short device = adapter->pdev->device; 1843 return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false; 1844 } 1845 1846 1847 #endif /* __QLCNIC_H_ */ 1848