1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2010 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #ifndef _QLCNIC_H_ 9 #define _QLCNIC_H_ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/ioport.h> 15 #include <linux/pci.h> 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ip.h> 19 #include <linux/in.h> 20 #include <linux/tcp.h> 21 #include <linux/skbuff.h> 22 #include <linux/firmware.h> 23 24 #include <linux/ethtool.h> 25 #include <linux/mii.h> 26 #include <linux/timer.h> 27 28 #include <linux/vmalloc.h> 29 30 #include <linux/io.h> 31 #include <asm/byteorder.h> 32 #include <linux/bitops.h> 33 #include <linux/if_vlan.h> 34 35 #include "qlcnic_hdr.h" 36 37 #define _QLCNIC_LINUX_MAJOR 5 38 #define _QLCNIC_LINUX_MINOR 0 39 #define _QLCNIC_LINUX_SUBVERSION 29 40 #define QLCNIC_LINUX_VERSIONID "5.0.29" 41 #define QLCNIC_DRV_IDC_VER 0x01 42 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ 43 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) 44 45 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) 46 #define _major(v) (((v) >> 24) & 0xff) 47 #define _minor(v) (((v) >> 16) & 0xff) 48 #define _build(v) ((v) & 0xffff) 49 50 /* version in image has weird encoding: 51 * 7:0 - major 52 * 15:8 - minor 53 * 31:16 - build (little endian) 54 */ 55 #define QLCNIC_DECODE_VERSION(v) \ 56 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) 57 58 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) 59 #define QLCNIC_NUM_FLASH_SECTORS (64) 60 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) 61 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ 62 * QLCNIC_FLASH_SECTOR_SIZE) 63 64 #define RCV_DESC_RINGSIZE(rds_ring) \ 65 (sizeof(struct rcv_desc) * (rds_ring)->num_desc) 66 #define RCV_BUFF_RINGSIZE(rds_ring) \ 67 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) 68 #define STATUS_DESC_RINGSIZE(sds_ring) \ 69 (sizeof(struct status_desc) * (sds_ring)->num_desc) 70 #define TX_BUFF_RINGSIZE(tx_ring) \ 71 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) 72 #define TX_DESC_RINGSIZE(tx_ring) \ 73 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) 74 75 #define QLCNIC_P3P_A0 0x50 76 #define QLCNIC_P3P_C0 0x58 77 78 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) 79 80 #define FIRST_PAGE_GROUP_START 0 81 #define FIRST_PAGE_GROUP_END 0x100000 82 83 #define P3P_MAX_MTU (9600) 84 #define P3P_MIN_MTU (68) 85 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ 86 87 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) 88 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) 89 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 90 #define QLCNIC_LRO_BUFFER_EXTRA 2048 91 92 /* Opcodes to be used with the commands */ 93 #define TX_ETHER_PKT 0x01 94 #define TX_TCP_PKT 0x02 95 #define TX_UDP_PKT 0x03 96 #define TX_IP_PKT 0x04 97 #define TX_TCP_LSO 0x05 98 #define TX_TCP_LSO6 0x06 99 #define TX_TCPV6_PKT 0x0b 100 #define TX_UDPV6_PKT 0x0c 101 102 /* Tx defines */ 103 #define QLCNIC_MAX_FRAGS_PER_TX 14 104 #define MAX_TSO_HEADER_DESC 2 105 #define MGMT_CMD_DESC_RESV 4 106 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ 107 + MGMT_CMD_DESC_RESV) 108 #define QLCNIC_MAX_TX_TIMEOUTS 2 109 110 /* 111 * Following are the states of the Phantom. Phantom will set them and 112 * Host will read to check if the fields are correct. 113 */ 114 #define PHAN_INITIALIZE_FAILED 0xffff 115 #define PHAN_INITIALIZE_COMPLETE 0xff01 116 117 /* Host writes the following to notify that it has done the init-handshake */ 118 #define PHAN_INITIALIZE_ACK 0xf00f 119 #define PHAN_PEG_RCV_INITIALIZED 0xff01 120 121 #define NUM_RCV_DESC_RINGS 3 122 123 #define RCV_RING_NORMAL 0 124 #define RCV_RING_JUMBO 1 125 126 #define MIN_CMD_DESCRIPTORS 64 127 #define MIN_RCV_DESCRIPTORS 64 128 #define MIN_JUMBO_DESCRIPTORS 32 129 130 #define MAX_CMD_DESCRIPTORS 1024 131 #define MAX_RCV_DESCRIPTORS_1G 4096 132 #define MAX_RCV_DESCRIPTORS_10G 8192 133 #define MAX_RCV_DESCRIPTORS_VF 2048 134 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 135 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 136 137 #define DEFAULT_RCV_DESCRIPTORS_1G 2048 138 #define DEFAULT_RCV_DESCRIPTORS_10G 4096 139 #define DEFAULT_RCV_DESCRIPTORS_VF 1024 140 #define MAX_RDS_RINGS 2 141 142 #define get_next_index(index, length) \ 143 (((index) + 1) & ((length) - 1)) 144 145 /* 146 * Following data structures describe the descriptors that will be used. 147 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when 148 * we are doing LSO (above the 1500 size packet) only. 149 */ 150 151 #define FLAGS_VLAN_TAGGED 0x10 152 #define FLAGS_VLAN_OOB 0x40 153 154 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \ 155 (cmd_desc)->vlan_TCI = cpu_to_le16(v); 156 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \ 157 ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) 158 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \ 159 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) 160 161 #define qlcnic_set_tx_port(_desc, _port) \ 162 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)) 163 164 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \ 165 ((_desc)->flags_opcode |= \ 166 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))) 167 168 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \ 169 ((_desc)->nfrags__length = \ 170 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))) 171 172 struct cmd_desc_type0 { 173 u8 tcp_hdr_offset; /* For LSO only */ 174 u8 ip_hdr_offset; /* For LSO only */ 175 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ 176 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ 177 178 __le64 addr_buffer2; 179 180 __le16 reference_handle; 181 __le16 mss; 182 u8 port_ctxid; /* 7:4 ctxid 3:0 port */ 183 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ 184 __le16 conn_id; /* IPSec offoad only */ 185 186 __le64 addr_buffer3; 187 __le64 addr_buffer1; 188 189 __le16 buffer_length[4]; 190 191 __le64 addr_buffer4; 192 193 u8 eth_addr[ETH_ALEN]; 194 __le16 vlan_TCI; 195 196 } __attribute__ ((aligned(64))); 197 198 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ 199 struct rcv_desc { 200 __le16 reference_handle; 201 __le16 reserved; 202 __le32 buffer_length; /* allocated buffer length (usually 2K) */ 203 __le64 addr_buffer; 204 } __packed; 205 206 /* opcode field in status_desc */ 207 #define QLCNIC_SYN_OFFLOAD 0x03 208 #define QLCNIC_RXPKT_DESC 0x04 209 #define QLCNIC_OLD_RXPKT_DESC 0x3f 210 #define QLCNIC_RESPONSE_DESC 0x05 211 #define QLCNIC_LRO_DESC 0x12 212 213 /* for status field in status_desc */ 214 #define STATUS_CKSUM_LOOP 0 215 #define STATUS_CKSUM_OK 2 216 217 /* owner bits of status_desc */ 218 #define STATUS_OWNER_HOST (0x1ULL << 56) 219 #define STATUS_OWNER_PHANTOM (0x2ULL << 56) 220 221 /* Status descriptor: 222 0-3 port, 4-7 status, 8-11 type, 12-27 total_length 223 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset 224 53-55 desc_cnt, 56-57 owner, 58-63 opcode 225 */ 226 #define qlcnic_get_sts_port(sts_data) \ 227 ((sts_data) & 0x0F) 228 #define qlcnic_get_sts_status(sts_data) \ 229 (((sts_data) >> 4) & 0x0F) 230 #define qlcnic_get_sts_type(sts_data) \ 231 (((sts_data) >> 8) & 0x0F) 232 #define qlcnic_get_sts_totallength(sts_data) \ 233 (((sts_data) >> 12) & 0xFFFF) 234 #define qlcnic_get_sts_refhandle(sts_data) \ 235 (((sts_data) >> 28) & 0xFFFF) 236 #define qlcnic_get_sts_prot(sts_data) \ 237 (((sts_data) >> 44) & 0x0F) 238 #define qlcnic_get_sts_pkt_offset(sts_data) \ 239 (((sts_data) >> 48) & 0x1F) 240 #define qlcnic_get_sts_desc_cnt(sts_data) \ 241 (((sts_data) >> 53) & 0x7) 242 #define qlcnic_get_sts_opcode(sts_data) \ 243 (((sts_data) >> 58) & 0x03F) 244 245 #define qlcnic_get_lro_sts_refhandle(sts_data) \ 246 ((sts_data) & 0x0FFFF) 247 #define qlcnic_get_lro_sts_length(sts_data) \ 248 (((sts_data) >> 16) & 0x0FFFF) 249 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \ 250 (((sts_data) >> 32) & 0x0FF) 251 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \ 252 (((sts_data) >> 40) & 0x0FF) 253 #define qlcnic_get_lro_sts_timestamp(sts_data) \ 254 (((sts_data) >> 48) & 0x1) 255 #define qlcnic_get_lro_sts_type(sts_data) \ 256 (((sts_data) >> 49) & 0x7) 257 #define qlcnic_get_lro_sts_push_flag(sts_data) \ 258 (((sts_data) >> 52) & 0x1) 259 #define qlcnic_get_lro_sts_seq_number(sts_data) \ 260 ((sts_data) & 0x0FFFFFFFF) 261 #define qlcnic_get_lro_sts_mss(sts_data1) \ 262 ((sts_data1 >> 32) & 0x0FFFF) 263 264 265 struct status_desc { 266 __le64 status_desc_data[2]; 267 } __attribute__ ((aligned(16))); 268 269 /* UNIFIED ROMIMAGE */ 270 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 271 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 272 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 273 #define QLCNIC_UNI_DIR_SECT_FW 0x7 274 275 /*Offsets */ 276 #define QLCNIC_UNI_CHIP_REV_OFF 10 277 #define QLCNIC_UNI_FLAGS_OFF 11 278 #define QLCNIC_UNI_BIOS_VERSION_OFF 12 279 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 280 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 281 282 struct uni_table_desc{ 283 u32 findex; 284 u32 num_entries; 285 u32 entry_size; 286 u32 reserved[5]; 287 }; 288 289 struct uni_data_desc{ 290 u32 findex; 291 u32 size; 292 u32 reserved[5]; 293 }; 294 295 /* Flash Defines and Structures */ 296 #define QLCNIC_FLT_LOCATION 0x3F1000 297 #define QLCNIC_B0_FW_IMAGE_REGION 0x74 298 #define QLCNIC_C0_FW_IMAGE_REGION 0x97 299 #define QLCNIC_BOOTLD_REGION 0X72 300 struct qlcnic_flt_header { 301 u16 version; 302 u16 len; 303 u16 checksum; 304 u16 reserved; 305 }; 306 307 struct qlcnic_flt_entry { 308 u8 region; 309 u8 reserved0; 310 u8 attrib; 311 u8 reserved1; 312 u32 size; 313 u32 start_addr; 314 u32 end_addr; 315 }; 316 317 /* Magic number to let user know flash is programmed */ 318 #define QLCNIC_BDINFO_MAGIC 0x12345678 319 320 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 321 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 322 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 323 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 324 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 325 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 326 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 327 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 328 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 329 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a 330 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b 331 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 332 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 333 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 334 335 #define QLCNIC_MSIX_TABLE_OFFSET 0x44 336 337 /* Flash memory map */ 338 #define QLCNIC_BRDCFG_START 0x4000 /* board config */ 339 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ 340 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ 341 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ 342 343 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) 344 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) 345 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) 346 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) 347 348 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) 349 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) 350 351 #define QLCNIC_FW_MIN_SIZE (0x3fffff) 352 #define QLCNIC_UNIFIED_ROMIMAGE 0 353 #define QLCNIC_FLASH_ROMIMAGE 1 354 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff 355 356 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" 357 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" 358 359 extern char qlcnic_driver_name[]; 360 361 /* Number of status descriptors to handle per interrupt */ 362 #define MAX_STATUS_HANDLE (64) 363 364 /* 365 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This 366 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. 367 */ 368 struct qlcnic_skb_frag { 369 u64 dma; 370 u64 length; 371 }; 372 373 /* Following defines are for the state of the buffers */ 374 #define QLCNIC_BUFFER_FREE 0 375 #define QLCNIC_BUFFER_BUSY 1 376 377 /* 378 * There will be one qlcnic_buffer per skb packet. These will be 379 * used to save the dma info for pci_unmap_page() 380 */ 381 struct qlcnic_cmd_buffer { 382 struct sk_buff *skb; 383 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; 384 u32 frag_count; 385 }; 386 387 /* In rx_buffer, we do not need multiple fragments as is a single buffer */ 388 struct qlcnic_rx_buffer { 389 u16 ref_handle; 390 struct sk_buff *skb; 391 struct list_head list; 392 u64 dma; 393 }; 394 395 /* Board types */ 396 #define QLCNIC_GBE 0x01 397 #define QLCNIC_XGBE 0x02 398 399 /* 400 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is 401 * adjusted based on configured MTU. 402 */ 403 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3 404 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256 405 406 #define QLCNIC_INTR_DEFAULT 0x04 407 #define QLCNIC_CONFIG_INTR_COALESCE 3 408 409 struct qlcnic_nic_intr_coalesce { 410 u8 type; 411 u8 sts_ring_mask; 412 u16 rx_packets; 413 u16 rx_time_us; 414 u16 flag; 415 u32 timer_out; 416 }; 417 418 struct qlcnic_dump_template_hdr { 419 __le32 type; 420 __le32 offset; 421 __le32 size; 422 __le32 cap_mask; 423 __le32 num_entries; 424 __le32 version; 425 __le32 timestamp; 426 __le32 checksum; 427 __le32 drv_cap_mask; 428 __le32 sys_info[3]; 429 __le32 saved_state[16]; 430 __le32 cap_sizes[8]; 431 __le32 rsvd[0]; 432 }; 433 434 struct qlcnic_fw_dump { 435 u8 clr; /* flag to indicate if dump is cleared */ 436 u8 enable; /* enable/disable dump */ 437 u32 size; /* total size of the dump */ 438 void *data; /* dump data area */ 439 struct qlcnic_dump_template_hdr *tmpl_hdr; 440 }; 441 442 /* 443 * One hardware_context{} per adapter 444 * contains interrupt info as well shared hardware info. 445 */ 446 struct qlcnic_hardware_context { 447 void __iomem *pci_base0; 448 void __iomem *ocm_win_crb; 449 450 unsigned long pci_len0; 451 452 rwlock_t crb_lock; 453 struct mutex mem_lock; 454 455 u8 revision_id; 456 u8 pci_func; 457 u8 linkup; 458 u8 loopback_state; 459 u16 port_type; 460 u16 board_type; 461 462 u8 beacon_state; 463 464 struct qlcnic_nic_intr_coalesce coal; 465 struct qlcnic_fw_dump fw_dump; 466 }; 467 468 struct qlcnic_adapter_stats { 469 u64 xmitcalled; 470 u64 xmitfinished; 471 u64 rxdropped; 472 u64 txdropped; 473 u64 csummed; 474 u64 rx_pkts; 475 u64 lro_pkts; 476 u64 rxbytes; 477 u64 txbytes; 478 u64 lrobytes; 479 u64 lso_frames; 480 u64 xmit_on; 481 u64 xmit_off; 482 u64 skb_alloc_failure; 483 u64 null_rxbuf; 484 u64 rx_dma_map_error; 485 u64 tx_dma_map_error; 486 }; 487 488 /* 489 * Rcv Descriptor Context. One such per Rcv Descriptor. There may 490 * be one Rcv Descriptor for normal packets, one for jumbo and may be others. 491 */ 492 struct qlcnic_host_rds_ring { 493 void __iomem *crb_rcv_producer; 494 struct rcv_desc *desc_head; 495 struct qlcnic_rx_buffer *rx_buf_arr; 496 u32 num_desc; 497 u32 producer; 498 u32 dma_size; 499 u32 skb_size; 500 u32 flags; 501 struct list_head free_list; 502 spinlock_t lock; 503 dma_addr_t phys_addr; 504 } ____cacheline_internodealigned_in_smp; 505 506 struct qlcnic_host_sds_ring { 507 u32 consumer; 508 u32 num_desc; 509 void __iomem *crb_sts_consumer; 510 511 struct status_desc *desc_head; 512 struct qlcnic_adapter *adapter; 513 struct napi_struct napi; 514 struct list_head free_list[NUM_RCV_DESC_RINGS]; 515 516 void __iomem *crb_intr_mask; 517 int irq; 518 519 dma_addr_t phys_addr; 520 char name[IFNAMSIZ+4]; 521 } ____cacheline_internodealigned_in_smp; 522 523 struct qlcnic_host_tx_ring { 524 u32 producer; 525 u32 sw_consumer; 526 u32 num_desc; 527 void __iomem *crb_cmd_producer; 528 struct cmd_desc_type0 *desc_head; 529 struct qlcnic_cmd_buffer *cmd_buf_arr; 530 __le32 *hw_consumer; 531 532 dma_addr_t phys_addr; 533 dma_addr_t hw_cons_phys_addr; 534 struct netdev_queue *txq; 535 } ____cacheline_internodealigned_in_smp; 536 537 /* 538 * Receive context. There is one such structure per instance of the 539 * receive processing. Any state information that is relevant to 540 * the receive, and is must be in this structure. The global data may be 541 * present elsewhere. 542 */ 543 struct qlcnic_recv_context { 544 struct qlcnic_host_rds_ring *rds_rings; 545 struct qlcnic_host_sds_ring *sds_rings; 546 u32 state; 547 u16 context_id; 548 u16 virt_port; 549 550 }; 551 552 /* HW context creation */ 553 554 #define QLCNIC_OS_CRB_RETRY_COUNT 4000 555 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \ 556 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) 557 558 #define QLCNIC_CDRP_CMD_BIT 0x80000000 559 560 /* 561 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared 562 * in the crb QLCNIC_CDRP_CRB_OFFSET. 563 */ 564 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) 565 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) 566 567 #define QLCNIC_CDRP_RSP_OK 0x00000001 568 #define QLCNIC_CDRP_RSP_FAIL 0x00000002 569 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 570 571 /* 572 * All commands must have the QLCNIC_CDRP_CMD_BIT set in 573 * the crb QLCNIC_CDRP_CRB_OFFSET. 574 */ 575 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) 576 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0) 577 578 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 579 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 580 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 581 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 582 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 583 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 584 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007 585 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008 586 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009 587 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a 588 #define QLCNIC_CDRP_CMD_INTRPT_TEST 0x00000011 589 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012 590 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013 591 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014 592 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015 593 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016 594 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017 595 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018 596 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019 597 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f 598 599 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020 600 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021 601 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022 602 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024 603 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025 604 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026 605 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027 606 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028 607 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029 608 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a 609 #define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E 610 #define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f 611 #define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030 612 #define QLCNIC_CDRP_CMD_GET_MAC_STATS 0x00000037 613 614 #define QLCNIC_RCODE_SUCCESS 0 615 #define QLCNIC_RCODE_INVALID_ARGS 6 616 #define QLCNIC_RCODE_NOT_SUPPORTED 9 617 #define QLCNIC_RCODE_NOT_PERMITTED 10 618 #define QLCNIC_RCODE_NOT_IMPL 15 619 #define QLCNIC_RCODE_INVALID 16 620 #define QLCNIC_RCODE_TIMEOUT 17 621 #define QLCNIC_DESTROY_CTX_RESET 0 622 623 /* 624 * Capabilities Announced 625 */ 626 #define QLCNIC_CAP0_LEGACY_CONTEXT (1) 627 #define QLCNIC_CAP0_LEGACY_MN (1 << 2) 628 #define QLCNIC_CAP0_LSO (1 << 6) 629 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) 630 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) 631 #define QLCNIC_CAP0_VALIDOFF (1 << 11) 632 #define QLCNIC_CAP0_LRO_MSS (1 << 21) 633 634 /* 635 * Context state 636 */ 637 #define QLCNIC_HOST_CTX_STATE_FREED 0 638 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 639 640 /* 641 * Rx context 642 */ 643 644 struct qlcnic_hostrq_sds_ring { 645 __le64 host_phys_addr; /* Ring base addr */ 646 __le32 ring_size; /* Ring entries */ 647 __le16 msi_index; 648 __le16 rsvd; /* Padding */ 649 } __packed; 650 651 struct qlcnic_hostrq_rds_ring { 652 __le64 host_phys_addr; /* Ring base addr */ 653 __le64 buff_size; /* Packet buffer size */ 654 __le32 ring_size; /* Ring entries */ 655 __le32 ring_kind; /* Class of ring */ 656 } __packed; 657 658 struct qlcnic_hostrq_rx_ctx { 659 __le64 host_rsp_dma_addr; /* Response dma'd here */ 660 __le32 capabilities[4]; /* Flag bit vector */ 661 __le32 host_int_crb_mode; /* Interrupt crb usage */ 662 __le32 host_rds_crb_mode; /* RDS crb usage */ 663 /* These ring offsets are relative to data[0] below */ 664 __le32 rds_ring_offset; /* Offset to RDS config */ 665 __le32 sds_ring_offset; /* Offset to SDS config */ 666 __le16 num_rds_rings; /* Count of RDS rings */ 667 __le16 num_sds_rings; /* Count of SDS rings */ 668 __le16 valid_field_offset; 669 u8 txrx_sds_binding; 670 u8 msix_handler; 671 u8 reserved[128]; /* reserve space for future expansion*/ 672 /* MUST BE 64-bit aligned. 673 The following is packed: 674 - N hostrq_rds_rings 675 - N hostrq_sds_rings */ 676 char data[0]; 677 } __packed; 678 679 struct qlcnic_cardrsp_rds_ring{ 680 __le32 host_producer_crb; /* Crb to use */ 681 __le32 rsvd1; /* Padding */ 682 } __packed; 683 684 struct qlcnic_cardrsp_sds_ring { 685 __le32 host_consumer_crb; /* Crb to use */ 686 __le32 interrupt_crb; /* Crb to use */ 687 } __packed; 688 689 struct qlcnic_cardrsp_rx_ctx { 690 /* These ring offsets are relative to data[0] below */ 691 __le32 rds_ring_offset; /* Offset to RDS config */ 692 __le32 sds_ring_offset; /* Offset to SDS config */ 693 __le32 host_ctx_state; /* Starting State */ 694 __le32 num_fn_per_port; /* How many PCI fn share the port */ 695 __le16 num_rds_rings; /* Count of RDS rings */ 696 __le16 num_sds_rings; /* Count of SDS rings */ 697 __le16 context_id; /* Handle for context */ 698 u8 phys_port; /* Physical id of port */ 699 u8 virt_port; /* Virtual/Logical id of port */ 700 u8 reserved[128]; /* save space for future expansion */ 701 /* MUST BE 64-bit aligned. 702 The following is packed: 703 - N cardrsp_rds_rings 704 - N cardrs_sds_rings */ 705 char data[0]; 706 } __packed; 707 708 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ 709 (sizeof(HOSTRQ_RX) + \ 710 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ 711 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) 712 713 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ 714 (sizeof(CARDRSP_RX) + \ 715 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ 716 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) 717 718 /* 719 * Tx context 720 */ 721 722 struct qlcnic_hostrq_cds_ring { 723 __le64 host_phys_addr; /* Ring base addr */ 724 __le32 ring_size; /* Ring entries */ 725 __le32 rsvd; /* Padding */ 726 } __packed; 727 728 struct qlcnic_hostrq_tx_ctx { 729 __le64 host_rsp_dma_addr; /* Response dma'd here */ 730 __le64 cmd_cons_dma_addr; /* */ 731 __le64 dummy_dma_addr; /* */ 732 __le32 capabilities[4]; /* Flag bit vector */ 733 __le32 host_int_crb_mode; /* Interrupt crb usage */ 734 __le32 rsvd1; /* Padding */ 735 __le16 rsvd2; /* Padding */ 736 __le16 interrupt_ctl; 737 __le16 msi_index; 738 __le16 rsvd3; /* Padding */ 739 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ 740 u8 reserved[128]; /* future expansion */ 741 } __packed; 742 743 struct qlcnic_cardrsp_cds_ring { 744 __le32 host_producer_crb; /* Crb to use */ 745 __le32 interrupt_crb; /* Crb to use */ 746 } __packed; 747 748 struct qlcnic_cardrsp_tx_ctx { 749 __le32 host_ctx_state; /* Starting state */ 750 __le16 context_id; /* Handle for context */ 751 u8 phys_port; /* Physical id of port */ 752 u8 virt_port; /* Virtual/Logical id of port */ 753 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ 754 u8 reserved[128]; /* future expansion */ 755 } __packed; 756 757 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) 758 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) 759 760 /* CRB */ 761 762 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 763 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 764 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 765 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 766 767 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 768 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 769 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 770 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 771 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 772 773 774 /* MAC */ 775 776 #define MC_COUNT_P3P 38 777 778 #define QLCNIC_MAC_NOOP 0 779 #define QLCNIC_MAC_ADD 1 780 #define QLCNIC_MAC_DEL 2 781 #define QLCNIC_MAC_VLAN_ADD 3 782 #define QLCNIC_MAC_VLAN_DEL 4 783 784 struct qlcnic_mac_list_s { 785 struct list_head list; 786 uint8_t mac_addr[ETH_ALEN+2]; 787 }; 788 789 #define QLCNIC_HOST_REQUEST 0x13 790 #define QLCNIC_REQUEST 0x14 791 792 #define QLCNIC_MAC_EVENT 0x1 793 794 #define QLCNIC_IP_UP 2 795 #define QLCNIC_IP_DOWN 3 796 797 #define QLCNIC_ILB_MODE 0x1 798 #define QLCNIC_ELB_MODE 0x2 799 800 #define QLCNIC_LINKEVENT 0x1 801 #define QLCNIC_LB_RESPONSE 0x2 802 #define QLCNIC_IS_LB_CONFIGURED(VAL) \ 803 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) 804 805 /* 806 * Driver --> Firmware 807 */ 808 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 809 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 810 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 811 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 812 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc 813 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 814 815 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 816 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 817 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 818 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 819 820 /* 821 * Firmware --> Driver 822 */ 823 824 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f 825 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 826 827 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ 828 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ 829 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ 830 831 #define QLCNIC_LRO_REQUEST_CLEANUP 4 832 833 /* Capabilites received */ 834 #define QLCNIC_FW_CAPABILITY_TSO BIT_1 835 #define QLCNIC_FW_CAPABILITY_BDG BIT_8 836 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 837 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 838 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 839 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 840 841 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 842 843 /* module types */ 844 #define LINKEVENT_MODULE_NOT_PRESENT 1 845 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 846 #define LINKEVENT_MODULE_OPTICAL_SRLR 3 847 #define LINKEVENT_MODULE_OPTICAL_LRM 4 848 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 849 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 850 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 851 #define LINKEVENT_MODULE_TWINAX 8 852 853 #define LINKSPEED_10GBPS 10000 854 #define LINKSPEED_1GBPS 1000 855 #define LINKSPEED_100MBPS 100 856 #define LINKSPEED_10MBPS 10 857 858 #define LINKSPEED_ENCODED_10MBPS 0 859 #define LINKSPEED_ENCODED_100MBPS 1 860 #define LINKSPEED_ENCODED_1GBPS 2 861 862 #define LINKEVENT_AUTONEG_DISABLED 0 863 #define LINKEVENT_AUTONEG_ENABLED 1 864 865 #define LINKEVENT_HALF_DUPLEX 0 866 #define LINKEVENT_FULL_DUPLEX 1 867 868 #define LINKEVENT_LINKSPEED_MBPS 0 869 #define LINKEVENT_LINKSPEED_ENCODED 1 870 871 /* firmware response header: 872 * 63:58 - message type 873 * 57:56 - owner 874 * 55:53 - desc count 875 * 52:48 - reserved 876 * 47:40 - completion id 877 * 39:32 - opcode 878 * 31:16 - error code 879 * 15:00 - reserved 880 */ 881 #define qlcnic_get_nic_msg_opcode(msg_hdr) \ 882 ((msg_hdr >> 32) & 0xFF) 883 884 struct qlcnic_fw_msg { 885 union { 886 struct { 887 u64 hdr; 888 u64 body[7]; 889 }; 890 u64 words[8]; 891 }; 892 }; 893 894 struct qlcnic_nic_req { 895 __le64 qhdr; 896 __le64 req_hdr; 897 __le64 words[6]; 898 } __packed; 899 900 struct qlcnic_mac_req { 901 u8 op; 902 u8 tag; 903 u8 mac_addr[6]; 904 }; 905 906 struct qlcnic_vlan_req { 907 __le16 vlan_id; 908 __le16 rsvd[3]; 909 } __packed; 910 911 struct qlcnic_ipaddr { 912 __be32 ipv4; 913 __be32 ipv6[4]; 914 }; 915 916 #define QLCNIC_MSI_ENABLED 0x02 917 #define QLCNIC_MSIX_ENABLED 0x04 918 #define QLCNIC_LRO_ENABLED 0x08 919 #define QLCNIC_LRO_DISABLED 0x00 920 #define QLCNIC_BRIDGE_ENABLED 0X10 921 #define QLCNIC_DIAG_ENABLED 0x20 922 #define QLCNIC_ESWITCH_ENABLED 0x40 923 #define QLCNIC_ADAPTER_INITIALIZED 0x80 924 #define QLCNIC_TAGGING_ENABLED 0x100 925 #define QLCNIC_MACSPOOF 0x200 926 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 927 #define QLCNIC_PROMISC_DISABLED 0x800 928 #define QLCNIC_NEED_FLR 0x1000 929 #define QLCNIC_FW_RESET_OWNER 0x2000 930 #define QLCNIC_FW_HANG 0x4000 931 #define QLCNIC_FW_LRO_MSS_CAP 0x8000 932 #define QLCNIC_IS_MSI_FAMILY(adapter) \ 933 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) 934 935 #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4 936 #define QLCNIC_MSIX_TBL_SPACE 8192 937 #define QLCNIC_PCI_REG_MSIX_TBL 0x44 938 #define QLCNIC_MSIX_TBL_PGSIZE 4096 939 940 #define QLCNIC_NETDEV_WEIGHT 128 941 #define QLCNIC_ADAPTER_UP_MAGIC 777 942 943 #define __QLCNIC_FW_ATTACHED 0 944 #define __QLCNIC_DEV_UP 1 945 #define __QLCNIC_RESETTING 2 946 #define __QLCNIC_START_FW 4 947 #define __QLCNIC_AER 5 948 #define __QLCNIC_DIAG_RES_ALLOC 6 949 #define __QLCNIC_LED_ENABLE 7 950 951 #define QLCNIC_INTERRUPT_TEST 1 952 #define QLCNIC_LOOPBACK_TEST 2 953 #define QLCNIC_LED_TEST 3 954 955 #define QLCNIC_FILTER_AGE 80 956 #define QLCNIC_READD_AGE 20 957 #define QLCNIC_LB_MAX_FILTERS 64 958 959 /* QLCNIC Driver Error Code */ 960 #define QLCNIC_FW_NOT_RESPOND 51 961 #define QLCNIC_TEST_IN_PROGRESS 52 962 #define QLCNIC_UNDEFINED_ERROR 53 963 #define QLCNIC_LB_CABLE_NOT_CONN 54 964 965 struct qlcnic_filter { 966 struct hlist_node fnode; 967 u8 faddr[ETH_ALEN]; 968 __le16 vlan_id; 969 unsigned long ftime; 970 }; 971 972 struct qlcnic_filter_hash { 973 struct hlist_head *fhead; 974 u8 fnum; 975 u8 fmax; 976 }; 977 978 struct qlcnic_adapter { 979 struct qlcnic_hardware_context *ahw; 980 struct qlcnic_recv_context *recv_ctx; 981 struct qlcnic_host_tx_ring *tx_ring; 982 struct net_device *netdev; 983 struct pci_dev *pdev; 984 985 unsigned long state; 986 u32 flags; 987 988 u16 num_txd; 989 u16 num_rxd; 990 u16 num_jumbo_rxd; 991 u16 max_rxd; 992 u16 max_jumbo_rxd; 993 994 u8 max_rds_rings; 995 u8 max_sds_rings; 996 u8 msix_supported; 997 u8 portnum; 998 u8 physical_port; 999 u8 reset_context; 1000 1001 u8 mc_enabled; 1002 u8 max_mc_count; 1003 u8 fw_wait_cnt; 1004 u8 fw_fail_cnt; 1005 u8 tx_timeo_cnt; 1006 u8 need_fw_reset; 1007 1008 u8 has_link_events; 1009 u8 fw_type; 1010 u16 tx_context_id; 1011 u16 is_up; 1012 1013 u16 link_speed; 1014 u16 link_duplex; 1015 u16 link_autoneg; 1016 u16 module_type; 1017 1018 u16 op_mode; 1019 u16 switch_mode; 1020 u16 max_tx_ques; 1021 u16 max_rx_ques; 1022 u16 max_mtu; 1023 u16 pvid; 1024 1025 u32 fw_hal_version; 1026 u32 capabilities; 1027 u32 irq; 1028 u32 temp; 1029 1030 u32 int_vec_bit; 1031 u32 heartbeat; 1032 1033 u8 max_mac_filters; 1034 u8 dev_state; 1035 u8 diag_test; 1036 char diag_cnt; 1037 u8 reset_ack_timeo; 1038 u8 dev_init_timeo; 1039 u16 msg_enable; 1040 1041 u8 mac_addr[ETH_ALEN]; 1042 1043 u64 dev_rst_time; 1044 u8 mac_learn; 1045 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1046 1047 struct qlcnic_npar_info *npars; 1048 struct qlcnic_eswitch *eswitch; 1049 struct qlcnic_nic_template *nic_ops; 1050 1051 struct qlcnic_adapter_stats stats; 1052 struct list_head mac_list; 1053 1054 void __iomem *tgt_mask_reg; 1055 void __iomem *tgt_status_reg; 1056 void __iomem *crb_int_state_reg; 1057 void __iomem *isr_int_vec; 1058 1059 struct msix_entry *msix_entries; 1060 1061 struct delayed_work fw_work; 1062 1063 1064 struct qlcnic_filter_hash fhash; 1065 1066 spinlock_t tx_clean_lock; 1067 spinlock_t mac_learn_lock; 1068 __le32 file_prd_off; /*File fw product offset*/ 1069 u32 fw_version; 1070 const struct firmware *fw; 1071 }; 1072 1073 struct qlcnic_info { 1074 __le16 pci_func; 1075 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ 1076 __le16 phys_port; 1077 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ 1078 1079 __le32 capabilities; 1080 u8 max_mac_filters; 1081 u8 reserved1; 1082 __le16 max_mtu; 1083 1084 __le16 max_tx_ques; 1085 __le16 max_rx_ques; 1086 __le16 min_tx_bw; 1087 __le16 max_tx_bw; 1088 u8 reserved2[104]; 1089 } __packed; 1090 1091 struct qlcnic_pci_info { 1092 __le16 id; /* pci function id */ 1093 __le16 active; /* 1 = Enabled */ 1094 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ 1095 __le16 default_port; /* default port number */ 1096 1097 __le16 tx_min_bw; /* Multiple of 100mbpc */ 1098 __le16 tx_max_bw; 1099 __le16 reserved1[2]; 1100 1101 u8 mac[ETH_ALEN]; 1102 u8 reserved2[106]; 1103 } __packed; 1104 1105 struct qlcnic_npar_info { 1106 u16 pvid; 1107 u16 min_bw; 1108 u16 max_bw; 1109 u8 phy_port; 1110 u8 type; 1111 u8 active; 1112 u8 enable_pm; 1113 u8 dest_npar; 1114 u8 discard_tagged; 1115 u8 mac_override; 1116 u8 mac_anti_spoof; 1117 u8 promisc_mode; 1118 u8 offload_flags; 1119 }; 1120 1121 struct qlcnic_eswitch { 1122 u8 port; 1123 u8 active_vports; 1124 u8 active_vlans; 1125 u8 active_ucast_filters; 1126 u8 max_ucast_filters; 1127 u8 max_active_vlans; 1128 1129 u32 flags; 1130 #define QLCNIC_SWITCH_ENABLE BIT_1 1131 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 1132 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 1133 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 1134 }; 1135 1136 1137 /* Return codes for Error handling */ 1138 #define QL_STATUS_INVALID_PARAM -1 1139 1140 #define MAX_BW 100 /* % of link speed */ 1141 #define MAX_VLAN_ID 4095 1142 #define MIN_VLAN_ID 2 1143 #define DEFAULT_MAC_LEARN 1 1144 1145 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) 1146 #define IS_VALID_BW(bw) (bw <= MAX_BW) 1147 1148 struct qlcnic_pci_func_cfg { 1149 u16 func_type; 1150 u16 min_bw; 1151 u16 max_bw; 1152 u16 port_num; 1153 u8 pci_func; 1154 u8 func_state; 1155 u8 def_mac_addr[6]; 1156 }; 1157 1158 struct qlcnic_npar_func_cfg { 1159 u32 fw_capab; 1160 u16 port_num; 1161 u16 min_bw; 1162 u16 max_bw; 1163 u16 max_tx_queues; 1164 u16 max_rx_queues; 1165 u8 pci_func; 1166 u8 op_mode; 1167 }; 1168 1169 struct qlcnic_pm_func_cfg { 1170 u8 pci_func; 1171 u8 action; 1172 u8 dest_npar; 1173 u8 reserved[5]; 1174 }; 1175 1176 struct qlcnic_esw_func_cfg { 1177 u16 vlan_id; 1178 u8 op_mode; 1179 u8 op_type; 1180 u8 pci_func; 1181 u8 host_vlan_tag; 1182 u8 promisc_mode; 1183 u8 discard_tagged; 1184 u8 mac_override; 1185 u8 mac_anti_spoof; 1186 u8 offload_flags; 1187 u8 reserved[5]; 1188 }; 1189 1190 #define QLCNIC_STATS_VERSION 1 1191 #define QLCNIC_STATS_PORT 1 1192 #define QLCNIC_STATS_ESWITCH 2 1193 #define QLCNIC_QUERY_RX_COUNTER 0 1194 #define QLCNIC_QUERY_TX_COUNTER 1 1195 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL 1196 #define QLCNIC_FILL_STATS(VAL1) \ 1197 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) 1198 #define QLCNIC_MAC_STATS 1 1199 #define QLCNIC_ESW_STATS 2 1200 1201 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ 1202 do { \ 1203 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ 1204 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1205 (VAL1) = (VAL2); \ 1206 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ 1207 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1208 (VAL1) += (VAL2); \ 1209 } while (0) 1210 1211 struct qlcnic_mac_statistics{ 1212 __le64 mac_tx_frames; 1213 __le64 mac_tx_bytes; 1214 __le64 mac_tx_mcast_pkts; 1215 __le64 mac_tx_bcast_pkts; 1216 __le64 mac_tx_pause_cnt; 1217 __le64 mac_tx_ctrl_pkt; 1218 __le64 mac_tx_lt_64b_pkts; 1219 __le64 mac_tx_lt_127b_pkts; 1220 __le64 mac_tx_lt_255b_pkts; 1221 __le64 mac_tx_lt_511b_pkts; 1222 __le64 mac_tx_lt_1023b_pkts; 1223 __le64 mac_tx_lt_1518b_pkts; 1224 __le64 mac_tx_gt_1518b_pkts; 1225 __le64 rsvd1[3]; 1226 1227 __le64 mac_rx_frames; 1228 __le64 mac_rx_bytes; 1229 __le64 mac_rx_mcast_pkts; 1230 __le64 mac_rx_bcast_pkts; 1231 __le64 mac_rx_pause_cnt; 1232 __le64 mac_rx_ctrl_pkt; 1233 __le64 mac_rx_lt_64b_pkts; 1234 __le64 mac_rx_lt_127b_pkts; 1235 __le64 mac_rx_lt_255b_pkts; 1236 __le64 mac_rx_lt_511b_pkts; 1237 __le64 mac_rx_lt_1023b_pkts; 1238 __le64 mac_rx_lt_1518b_pkts; 1239 __le64 mac_rx_gt_1518b_pkts; 1240 __le64 rsvd2[3]; 1241 1242 __le64 mac_rx_length_error; 1243 __le64 mac_rx_length_small; 1244 __le64 mac_rx_length_large; 1245 __le64 mac_rx_jabber; 1246 __le64 mac_rx_dropped; 1247 __le64 mac_rx_crc_error; 1248 __le64 mac_align_error; 1249 } __packed; 1250 1251 struct __qlcnic_esw_statistics { 1252 __le16 context_id; 1253 __le16 version; 1254 __le16 size; 1255 __le16 unused; 1256 __le64 unicast_frames; 1257 __le64 multicast_frames; 1258 __le64 broadcast_frames; 1259 __le64 dropped_frames; 1260 __le64 errors; 1261 __le64 local_frames; 1262 __le64 numbytes; 1263 __le64 rsvd[3]; 1264 } __packed; 1265 1266 struct qlcnic_esw_statistics { 1267 struct __qlcnic_esw_statistics rx; 1268 struct __qlcnic_esw_statistics tx; 1269 }; 1270 1271 struct qlcnic_common_entry_hdr { 1272 __le32 type; 1273 __le32 offset; 1274 __le32 cap_size; 1275 u8 mask; 1276 u8 rsvd[2]; 1277 u8 flags; 1278 } __packed; 1279 1280 struct __crb { 1281 __le32 addr; 1282 u8 stride; 1283 u8 rsvd1[3]; 1284 __le32 data_size; 1285 __le32 no_ops; 1286 __le32 rsvd2[4]; 1287 } __packed; 1288 1289 struct __ctrl { 1290 __le32 addr; 1291 u8 stride; 1292 u8 index_a; 1293 __le16 timeout; 1294 __le32 data_size; 1295 __le32 no_ops; 1296 u8 opcode; 1297 u8 index_v; 1298 u8 shl_val; 1299 u8 shr_val; 1300 __le32 val1; 1301 __le32 val2; 1302 __le32 val3; 1303 } __packed; 1304 1305 struct __cache { 1306 __le32 addr; 1307 __le16 stride; 1308 __le16 init_tag_val; 1309 __le32 size; 1310 __le32 no_ops; 1311 __le32 ctrl_addr; 1312 __le32 ctrl_val; 1313 __le32 read_addr; 1314 u8 read_addr_stride; 1315 u8 read_addr_num; 1316 u8 rsvd1[2]; 1317 } __packed; 1318 1319 struct __ocm { 1320 u8 rsvd[8]; 1321 __le32 size; 1322 __le32 no_ops; 1323 u8 rsvd1[8]; 1324 __le32 read_addr; 1325 __le32 read_addr_stride; 1326 } __packed; 1327 1328 struct __mem { 1329 u8 rsvd[24]; 1330 __le32 addr; 1331 __le32 size; 1332 } __packed; 1333 1334 struct __mux { 1335 __le32 addr; 1336 u8 rsvd[4]; 1337 __le32 size; 1338 __le32 no_ops; 1339 __le32 val; 1340 __le32 val_stride; 1341 __le32 read_addr; 1342 u8 rsvd2[4]; 1343 } __packed; 1344 1345 struct __queue { 1346 __le32 sel_addr; 1347 __le16 stride; 1348 u8 rsvd[2]; 1349 __le32 size; 1350 __le32 no_ops; 1351 u8 rsvd2[8]; 1352 __le32 read_addr; 1353 u8 read_addr_stride; 1354 u8 read_addr_cnt; 1355 u8 rsvd3[2]; 1356 } __packed; 1357 1358 struct qlcnic_dump_entry { 1359 struct qlcnic_common_entry_hdr hdr; 1360 union { 1361 struct __crb crb; 1362 struct __cache cache; 1363 struct __ocm ocm; 1364 struct __mem mem; 1365 struct __mux mux; 1366 struct __queue que; 1367 struct __ctrl ctrl; 1368 } region; 1369 } __packed; 1370 1371 enum op_codes { 1372 QLCNIC_DUMP_NOP = 0, 1373 QLCNIC_DUMP_READ_CRB = 1, 1374 QLCNIC_DUMP_READ_MUX = 2, 1375 QLCNIC_DUMP_QUEUE = 3, 1376 QLCNIC_DUMP_BRD_CONFIG = 4, 1377 QLCNIC_DUMP_READ_OCM = 6, 1378 QLCNIC_DUMP_PEG_REG = 7, 1379 QLCNIC_DUMP_L1_DTAG = 8, 1380 QLCNIC_DUMP_L1_ITAG = 9, 1381 QLCNIC_DUMP_L1_DATA = 11, 1382 QLCNIC_DUMP_L1_INST = 12, 1383 QLCNIC_DUMP_L2_DTAG = 21, 1384 QLCNIC_DUMP_L2_ITAG = 22, 1385 QLCNIC_DUMP_L2_DATA = 23, 1386 QLCNIC_DUMP_L2_INST = 24, 1387 QLCNIC_DUMP_READ_ROM = 71, 1388 QLCNIC_DUMP_READ_MEM = 72, 1389 QLCNIC_DUMP_READ_CTRL = 98, 1390 QLCNIC_DUMP_TLHDR = 99, 1391 QLCNIC_DUMP_RDEND = 255 1392 }; 1393 1394 #define QLCNIC_DUMP_WCRB BIT_0 1395 #define QLCNIC_DUMP_RWCRB BIT_1 1396 #define QLCNIC_DUMP_ANDCRB BIT_2 1397 #define QLCNIC_DUMP_ORCRB BIT_3 1398 #define QLCNIC_DUMP_POLLCRB BIT_4 1399 #define QLCNIC_DUMP_RD_SAVE BIT_5 1400 #define QLCNIC_DUMP_WRT_SAVED BIT_6 1401 #define QLCNIC_DUMP_MOD_SAVE_ST BIT_7 1402 #define QLCNIC_DUMP_SKIP BIT_7 1403 1404 #define QLCNIC_DUMP_MASK_MIN 3 1405 #define QLCNIC_DUMP_MASK_DEF 0x1f 1406 #define QLCNIC_DUMP_MASK_MAX 0xff 1407 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed 1408 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed 1409 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed 1410 #define QLCNIC_FORCE_FW_RESET 0xdeaddead 1411 #define QLCNIC_SET_QUIESCENT 0xadd00010 1412 #define QLCNIC_RESET_QUIESCENT 0xadd00020 1413 1414 struct qlcnic_dump_operations { 1415 enum op_codes opcode; 1416 u32 (*handler)(struct qlcnic_adapter *, 1417 struct qlcnic_dump_entry *, u32 *); 1418 }; 1419 1420 struct _cdrp_cmd { 1421 u32 cmd; 1422 u32 arg1; 1423 u32 arg2; 1424 u32 arg3; 1425 }; 1426 1427 struct qlcnic_cmd_args { 1428 struct _cdrp_cmd req; 1429 struct _cdrp_cmd rsp; 1430 }; 1431 1432 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); 1433 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); 1434 1435 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off); 1436 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data); 1437 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); 1438 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); 1439 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); 1440 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); 1441 1442 #define ADDR_IN_RANGE(addr, low, high) \ 1443 (((addr) < (high)) && ((addr) >= (low))) 1444 1445 #define QLCRD32(adapter, off) \ 1446 (qlcnic_hw_read_wx_2M(adapter, off)) 1447 #define QLCWR32(adapter, off, val) \ 1448 (qlcnic_hw_write_wx_2M(adapter, off, val)) 1449 1450 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); 1451 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); 1452 1453 #define qlcnic_rom_lock(a) \ 1454 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) 1455 #define qlcnic_rom_unlock(a) \ 1456 qlcnic_pcie_sem_unlock((a), 2) 1457 #define qlcnic_phy_lock(a) \ 1458 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) 1459 #define qlcnic_phy_unlock(a) \ 1460 qlcnic_pcie_sem_unlock((a), 3) 1461 #define qlcnic_api_lock(a) \ 1462 qlcnic_pcie_sem_lock((a), 5, 0) 1463 #define qlcnic_api_unlock(a) \ 1464 qlcnic_pcie_sem_unlock((a), 5) 1465 #define qlcnic_sw_lock(a) \ 1466 qlcnic_pcie_sem_lock((a), 6, 0) 1467 #define qlcnic_sw_unlock(a) \ 1468 qlcnic_pcie_sem_unlock((a), 6) 1469 #define crb_win_lock(a) \ 1470 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) 1471 #define crb_win_unlock(a) \ 1472 qlcnic_pcie_sem_unlock((a), 7) 1473 1474 #define __QLCNIC_MAX_LED_RATE 0xf 1475 #define __QLCNIC_MAX_LED_STATE 0x2 1476 1477 int qlcnic_get_board_info(struct qlcnic_adapter *adapter); 1478 int qlcnic_wol_supported(struct qlcnic_adapter *adapter); 1479 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate); 1480 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); 1481 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); 1482 int qlcnic_dump_fw(struct qlcnic_adapter *); 1483 1484 /* Functions from qlcnic_init.c */ 1485 int qlcnic_load_firmware(struct qlcnic_adapter *adapter); 1486 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); 1487 void qlcnic_request_firmware(struct qlcnic_adapter *adapter); 1488 void qlcnic_release_firmware(struct qlcnic_adapter *adapter); 1489 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); 1490 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); 1491 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); 1492 1493 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); 1494 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, 1495 u8 *bytes, size_t size); 1496 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); 1497 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); 1498 1499 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32); 1500 1501 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); 1502 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); 1503 1504 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); 1505 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); 1506 1507 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); 1508 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); 1509 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter); 1510 1511 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); 1512 void qlcnic_watchdog_task(struct work_struct *work); 1513 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, 1514 struct qlcnic_host_rds_ring *rds_ring); 1515 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); 1516 void qlcnic_set_multi(struct net_device *netdev); 1517 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter); 1518 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32); 1519 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter); 1520 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable); 1521 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd); 1522 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable); 1523 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup); 1524 1525 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); 1526 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); 1527 netdev_features_t qlcnic_fix_features(struct net_device *netdev, 1528 netdev_features_t features); 1529 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); 1530 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable); 1531 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); 1532 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); 1533 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter, 1534 struct qlcnic_host_tx_ring *tx_ring); 1535 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *); 1536 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring); 1537 void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter); 1538 int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode); 1539 1540 /* Functions from qlcnic_ethtool.c */ 1541 int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[]); 1542 1543 /* Functions from qlcnic_main.c */ 1544 int qlcnic_reset_context(struct qlcnic_adapter *); 1545 void qlcnic_issue_cmd(struct qlcnic_adapter *adapter, struct qlcnic_cmd_args *); 1546 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); 1547 int qlcnic_diag_alloc_res(struct net_device *netdev, int test); 1548 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 1549 int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val); 1550 int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data); 1551 void qlcnic_dev_request_reset(struct qlcnic_adapter *); 1552 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); 1553 1554 /* Management functions */ 1555 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*); 1556 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); 1557 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); 1558 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*); 1559 1560 /* eSwitch management functions */ 1561 int qlcnic_config_switch_port(struct qlcnic_adapter *, 1562 struct qlcnic_esw_func_cfg *); 1563 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, 1564 struct qlcnic_esw_func_cfg *); 1565 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); 1566 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, 1567 struct __qlcnic_esw_statistics *); 1568 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, 1569 struct __qlcnic_esw_statistics *); 1570 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); 1571 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); 1572 extern int qlcnic_config_tso; 1573 1574 /* 1575 * QLOGIC Board information 1576 */ 1577 1578 #define QLCNIC_MAX_BOARD_NAME_LEN 100 1579 struct qlcnic_brdinfo { 1580 unsigned short vendor; 1581 unsigned short device; 1582 unsigned short sub_vendor; 1583 unsigned short sub_device; 1584 char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; 1585 }; 1586 1587 static const struct qlcnic_brdinfo qlcnic_boards[] = { 1588 {0x1077, 0x8020, 0x1077, 0x203, 1589 "8200 Series Single Port 10GbE Converged Network Adapter " 1590 "(TCP/IP Networking)"}, 1591 {0x1077, 0x8020, 0x1077, 0x207, 1592 "8200 Series Dual Port 10GbE Converged Network Adapter " 1593 "(TCP/IP Networking)"}, 1594 {0x1077, 0x8020, 0x1077, 0x20b, 1595 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"}, 1596 {0x1077, 0x8020, 0x1077, 0x20c, 1597 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"}, 1598 {0x1077, 0x8020, 0x1077, 0x20f, 1599 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"}, 1600 {0x1077, 0x8020, 0x103c, 0x3733, 1601 "NC523SFP 10Gb 2-port Server Adapter"}, 1602 {0x1077, 0x8020, 0x103c, 0x3346, 1603 "CN1000Q Dual Port Converged Network Adapter"}, 1604 {0x1077, 0x8020, 0x1077, 0x210, 1605 "QME8242-k 10GbE Dual Port Mezzanine Card"}, 1606 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"}, 1607 }; 1608 1609 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards) 1610 1611 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) 1612 { 1613 if (likely(tx_ring->producer < tx_ring->sw_consumer)) 1614 return tx_ring->sw_consumer - tx_ring->producer; 1615 else 1616 return tx_ring->sw_consumer + tx_ring->num_desc - 1617 tx_ring->producer; 1618 } 1619 1620 extern const struct ethtool_ops qlcnic_ethtool_ops; 1621 extern const struct ethtool_ops qlcnic_ethtool_failed_ops; 1622 1623 struct qlcnic_nic_template { 1624 int (*config_bridged_mode) (struct qlcnic_adapter *, u32); 1625 int (*config_led) (struct qlcnic_adapter *, u32, u32); 1626 int (*start_firmware) (struct qlcnic_adapter *); 1627 }; 1628 1629 #define QLCDB(adapter, lvl, _fmt, _args...) do { \ 1630 if (NETIF_MSG_##lvl & adapter->msg_enable) \ 1631 printk(KERN_INFO "%s: %s: " _fmt, \ 1632 dev_name(&adapter->pdev->dev), \ 1633 __func__, ##_args); \ 1634 } while (0) 1635 1636 #endif /* __QLCNIC_H_ */ 1637