1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #ifndef _QLCNIC_H_ 9 #define _QLCNIC_H_ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/ioport.h> 15 #include <linux/pci.h> 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ip.h> 19 #include <linux/in.h> 20 #include <linux/tcp.h> 21 #include <linux/skbuff.h> 22 #include <linux/firmware.h> 23 #include <linux/ethtool.h> 24 #include <linux/mii.h> 25 #include <linux/timer.h> 26 27 #include <linux/vmalloc.h> 28 29 #include <linux/io.h> 30 #include <asm/byteorder.h> 31 #include <linux/bitops.h> 32 #include <linux/if_vlan.h> 33 34 #include "qlcnic_hdr.h" 35 #include "qlcnic_hw.h" 36 #include "qlcnic_83xx_hw.h" 37 #include "qlcnic_dcb.h" 38 39 #define _QLCNIC_LINUX_MAJOR 5 40 #define _QLCNIC_LINUX_MINOR 3 41 #define _QLCNIC_LINUX_SUBVERSION 52 42 #define QLCNIC_LINUX_VERSIONID "5.3.52" 43 #define QLCNIC_DRV_IDC_VER 0x01 44 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ 45 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) 46 47 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) 48 #define _major(v) (((v) >> 24) & 0xff) 49 #define _minor(v) (((v) >> 16) & 0xff) 50 #define _build(v) ((v) & 0xffff) 51 52 /* version in image has weird encoding: 53 * 7:0 - major 54 * 15:8 - minor 55 * 31:16 - build (little endian) 56 */ 57 #define QLCNIC_DECODE_VERSION(v) \ 58 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) 59 60 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) 61 #define QLCNIC_NUM_FLASH_SECTORS (64) 62 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) 63 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ 64 * QLCNIC_FLASH_SECTOR_SIZE) 65 66 #define RCV_DESC_RINGSIZE(rds_ring) \ 67 (sizeof(struct rcv_desc) * (rds_ring)->num_desc) 68 #define RCV_BUFF_RINGSIZE(rds_ring) \ 69 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) 70 #define STATUS_DESC_RINGSIZE(sds_ring) \ 71 (sizeof(struct status_desc) * (sds_ring)->num_desc) 72 #define TX_BUFF_RINGSIZE(tx_ring) \ 73 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) 74 #define TX_DESC_RINGSIZE(tx_ring) \ 75 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) 76 77 #define QLCNIC_P3P_A0 0x50 78 #define QLCNIC_P3P_C0 0x58 79 80 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) 81 82 #define FIRST_PAGE_GROUP_START 0 83 #define FIRST_PAGE_GROUP_END 0x100000 84 85 #define P3P_MAX_MTU (9600) 86 #define P3P_MIN_MTU (68) 87 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ 88 89 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) 90 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) 91 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 92 #define QLCNIC_LRO_BUFFER_EXTRA 2048 93 94 /* Tx defines */ 95 #define QLCNIC_MAX_FRAGS_PER_TX 14 96 #define MAX_TSO_HEADER_DESC 2 97 #define MGMT_CMD_DESC_RESV 4 98 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ 99 + MGMT_CMD_DESC_RESV) 100 #define QLCNIC_MAX_TX_TIMEOUTS 2 101 102 /* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */ 103 #define QLCNIC_SINGLE_RING 1 104 #define QLCNIC_DEF_SDS_RINGS 4 105 #define QLCNIC_DEF_TX_RINGS 4 106 #define QLCNIC_MAX_VNIC_TX_RINGS 4 107 #define QLCNIC_MAX_VNIC_SDS_RINGS 4 108 109 enum qlcnic_queue_type { 110 QLCNIC_TX_QUEUE = 1, 111 QLCNIC_RX_QUEUE, 112 }; 113 114 /* Operational mode for driver */ 115 #define QLCNIC_VNIC_MODE 0xFF 116 #define QLCNIC_DEFAULT_MODE 0x0 117 118 /* 119 * Following are the states of the Phantom. Phantom will set them and 120 * Host will read to check if the fields are correct. 121 */ 122 #define PHAN_INITIALIZE_FAILED 0xffff 123 #define PHAN_INITIALIZE_COMPLETE 0xff01 124 125 /* Host writes the following to notify that it has done the init-handshake */ 126 #define PHAN_INITIALIZE_ACK 0xf00f 127 #define PHAN_PEG_RCV_INITIALIZED 0xff01 128 129 #define NUM_RCV_DESC_RINGS 3 130 131 #define RCV_RING_NORMAL 0 132 #define RCV_RING_JUMBO 1 133 134 #define MIN_CMD_DESCRIPTORS 64 135 #define MIN_RCV_DESCRIPTORS 64 136 #define MIN_JUMBO_DESCRIPTORS 32 137 138 #define MAX_CMD_DESCRIPTORS 1024 139 #define MAX_RCV_DESCRIPTORS_1G 4096 140 #define MAX_RCV_DESCRIPTORS_10G 8192 141 #define MAX_RCV_DESCRIPTORS_VF 2048 142 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 143 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 144 145 #define DEFAULT_RCV_DESCRIPTORS_1G 2048 146 #define DEFAULT_RCV_DESCRIPTORS_10G 4096 147 #define DEFAULT_RCV_DESCRIPTORS_VF 1024 148 #define MAX_RDS_RINGS 2 149 150 #define get_next_index(index, length) \ 151 (((index) + 1) & ((length) - 1)) 152 153 /* 154 * Following data structures describe the descriptors that will be used. 155 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when 156 * we are doing LSO (above the 1500 size packet) only. 157 */ 158 struct cmd_desc_type0 { 159 u8 tcp_hdr_offset; /* For LSO only */ 160 u8 ip_hdr_offset; /* For LSO only */ 161 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ 162 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ 163 164 __le64 addr_buffer2; 165 166 __le16 reference_handle; 167 __le16 mss; 168 u8 port_ctxid; /* 7:4 ctxid 3:0 port */ 169 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ 170 __le16 conn_id; /* IPSec offoad only */ 171 172 __le64 addr_buffer3; 173 __le64 addr_buffer1; 174 175 __le16 buffer_length[4]; 176 177 __le64 addr_buffer4; 178 179 u8 eth_addr[ETH_ALEN]; 180 __le16 vlan_TCI; 181 182 } __attribute__ ((aligned(64))); 183 184 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ 185 struct rcv_desc { 186 __le16 reference_handle; 187 __le16 reserved; 188 __le32 buffer_length; /* allocated buffer length (usually 2K) */ 189 __le64 addr_buffer; 190 } __packed; 191 192 struct status_desc { 193 __le64 status_desc_data[2]; 194 } __attribute__ ((aligned(16))); 195 196 /* UNIFIED ROMIMAGE */ 197 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 198 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 199 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 200 #define QLCNIC_UNI_DIR_SECT_FW 0x7 201 202 /*Offsets */ 203 #define QLCNIC_UNI_CHIP_REV_OFF 10 204 #define QLCNIC_UNI_FLAGS_OFF 11 205 #define QLCNIC_UNI_BIOS_VERSION_OFF 12 206 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 207 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 208 209 struct uni_table_desc{ 210 __le32 findex; 211 __le32 num_entries; 212 __le32 entry_size; 213 __le32 reserved[5]; 214 }; 215 216 struct uni_data_desc{ 217 __le32 findex; 218 __le32 size; 219 __le32 reserved[5]; 220 }; 221 222 /* Flash Defines and Structures */ 223 #define QLCNIC_FLT_LOCATION 0x3F1000 224 #define QLCNIC_FDT_LOCATION 0x3F0000 225 #define QLCNIC_B0_FW_IMAGE_REGION 0x74 226 #define QLCNIC_C0_FW_IMAGE_REGION 0x97 227 #define QLCNIC_BOOTLD_REGION 0X72 228 struct qlcnic_flt_header { 229 u16 version; 230 u16 len; 231 u16 checksum; 232 u16 reserved; 233 }; 234 235 struct qlcnic_flt_entry { 236 u8 region; 237 u8 reserved0; 238 u8 attrib; 239 u8 reserved1; 240 u32 size; 241 u32 start_addr; 242 u32 end_addr; 243 }; 244 245 /* Flash Descriptor Table */ 246 struct qlcnic_fdt { 247 u32 valid; 248 u16 ver; 249 u16 len; 250 u16 cksum; 251 u16 unused; 252 u8 model[16]; 253 u16 mfg_id; 254 u16 id; 255 u8 flag; 256 u8 erase_cmd; 257 u8 alt_erase_cmd; 258 u8 write_enable_cmd; 259 u8 write_enable_bits; 260 u8 write_statusreg_cmd; 261 u8 unprotected_sec_cmd; 262 u8 read_manuf_cmd; 263 u32 block_size; 264 u32 alt_block_size; 265 u32 flash_size; 266 u32 write_enable_data; 267 u8 readid_addr_len; 268 u8 write_disable_bits; 269 u8 read_dev_id_len; 270 u8 chip_erase_cmd; 271 u16 read_timeo; 272 u8 protected_sec_cmd; 273 u8 resvd[65]; 274 }; 275 /* Magic number to let user know flash is programmed */ 276 #define QLCNIC_BDINFO_MAGIC 0x12345678 277 278 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 279 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 280 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 281 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 282 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 283 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 284 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 285 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 286 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 287 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a 288 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b 289 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 290 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 291 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 292 293 #define QLCNIC_MSIX_TABLE_OFFSET 0x44 294 295 /* Flash memory map */ 296 #define QLCNIC_BRDCFG_START 0x4000 /* board config */ 297 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ 298 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ 299 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ 300 301 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) 302 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) 303 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) 304 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) 305 306 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) 307 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) 308 309 #define QLCNIC_FW_MIN_SIZE (0x3fffff) 310 #define QLCNIC_UNIFIED_ROMIMAGE 0 311 #define QLCNIC_FLASH_ROMIMAGE 1 312 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff 313 314 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" 315 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" 316 317 extern char qlcnic_driver_name[]; 318 319 extern int qlcnic_use_msi; 320 extern int qlcnic_use_msi_x; 321 extern int qlcnic_auto_fw_reset; 322 extern int qlcnic_load_fw_file; 323 324 /* Number of status descriptors to handle per interrupt */ 325 #define MAX_STATUS_HANDLE (64) 326 327 /* 328 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This 329 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. 330 */ 331 struct qlcnic_skb_frag { 332 u64 dma; 333 u64 length; 334 }; 335 336 /* Following defines are for the state of the buffers */ 337 #define QLCNIC_BUFFER_FREE 0 338 #define QLCNIC_BUFFER_BUSY 1 339 340 /* 341 * There will be one qlcnic_buffer per skb packet. These will be 342 * used to save the dma info for pci_unmap_page() 343 */ 344 struct qlcnic_cmd_buffer { 345 struct sk_buff *skb; 346 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; 347 u32 frag_count; 348 }; 349 350 /* In rx_buffer, we do not need multiple fragments as is a single buffer */ 351 struct qlcnic_rx_buffer { 352 u16 ref_handle; 353 struct sk_buff *skb; 354 struct list_head list; 355 u64 dma; 356 }; 357 358 /* Board types */ 359 #define QLCNIC_GBE 0x01 360 #define QLCNIC_XGBE 0x02 361 362 /* 363 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is 364 * adjusted based on configured MTU. 365 */ 366 #define QLCNIC_INTR_COAL_TYPE_RX 1 367 #define QLCNIC_INTR_COAL_TYPE_TX 2 368 369 #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3 370 #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256 371 372 #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64 373 #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64 374 375 #define QLCNIC_INTR_DEFAULT 0x04 376 #define QLCNIC_CONFIG_INTR_COALESCE 3 377 #define QLCNIC_DEV_INFO_SIZE 1 378 379 struct qlcnic_nic_intr_coalesce { 380 u8 type; 381 u8 sts_ring_mask; 382 u16 rx_packets; 383 u16 rx_time_us; 384 u16 tx_packets; 385 u16 tx_time_us; 386 u16 flag; 387 u32 timer_out; 388 }; 389 390 struct qlcnic_dump_template_hdr { 391 u32 type; 392 u32 offset; 393 u32 size; 394 u32 cap_mask; 395 u32 num_entries; 396 u32 version; 397 u32 timestamp; 398 u32 checksum; 399 u32 drv_cap_mask; 400 u32 sys_info[3]; 401 u32 saved_state[16]; 402 u32 cap_sizes[8]; 403 u32 ocm_wnd_reg[16]; 404 u32 rsvd[0]; 405 }; 406 407 struct qlcnic_fw_dump { 408 u8 clr; /* flag to indicate if dump is cleared */ 409 bool enable; /* enable/disable dump */ 410 u32 size; /* total size of the dump */ 411 void *data; /* dump data area */ 412 struct qlcnic_dump_template_hdr *tmpl_hdr; 413 dma_addr_t phys_addr; 414 void *dma_buffer; 415 bool use_pex_dma; 416 }; 417 418 /* 419 * One hardware_context{} per adapter 420 * contains interrupt info as well shared hardware info. 421 */ 422 struct qlcnic_hardware_context { 423 void __iomem *pci_base0; 424 void __iomem *ocm_win_crb; 425 426 unsigned long pci_len0; 427 428 rwlock_t crb_lock; 429 struct mutex mem_lock; 430 431 u8 revision_id; 432 u8 pci_func; 433 u8 linkup; 434 u8 loopback_state; 435 u8 beacon_state; 436 u8 has_link_events; 437 u8 fw_type; 438 u8 physical_port; 439 u8 reset_context; 440 u8 msix_supported; 441 u8 max_mac_filters; 442 u8 mc_enabled; 443 u8 max_mc_count; 444 u8 diag_test; 445 u8 num_msix; 446 u8 nic_mode; 447 int diag_cnt; 448 449 u16 max_uc_count; 450 u16 port_type; 451 u16 board_type; 452 u16 supported_type; 453 454 u16 link_speed; 455 u16 link_duplex; 456 u16 link_autoneg; 457 u16 module_type; 458 459 u16 op_mode; 460 u16 switch_mode; 461 u16 max_tx_ques; 462 u16 max_rx_ques; 463 u16 max_mtu; 464 u32 msg_enable; 465 u16 act_pci_func; 466 u16 max_pci_func; 467 468 u32 capabilities; 469 u32 extra_capability[3]; 470 u32 temp; 471 u32 int_vec_bit; 472 u32 fw_hal_version; 473 u32 port_config; 474 struct qlcnic_hardware_ops *hw_ops; 475 struct qlcnic_nic_intr_coalesce coal; 476 struct qlcnic_fw_dump fw_dump; 477 struct qlcnic_fdt fdt; 478 struct qlc_83xx_reset reset; 479 struct qlc_83xx_idc idc; 480 struct qlc_83xx_fw_info *fw_info; 481 struct qlcnic_intrpt_config *intr_tbl; 482 struct qlcnic_sriov *sriov; 483 u32 *reg_tbl; 484 u32 *ext_reg_tbl; 485 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; 486 u32 mbox_reg[4]; 487 struct qlcnic_mailbox *mailbox; 488 u8 extend_lb_time; 489 u8 phys_port_id[ETH_ALEN]; 490 }; 491 492 struct qlcnic_adapter_stats { 493 u64 xmitcalled; 494 u64 xmitfinished; 495 u64 rxdropped; 496 u64 txdropped; 497 u64 csummed; 498 u64 rx_pkts; 499 u64 lro_pkts; 500 u64 rxbytes; 501 u64 txbytes; 502 u64 lrobytes; 503 u64 lso_frames; 504 u64 xmit_on; 505 u64 xmit_off; 506 u64 skb_alloc_failure; 507 u64 null_rxbuf; 508 u64 rx_dma_map_error; 509 u64 tx_dma_map_error; 510 u64 spurious_intr; 511 u64 mac_filter_limit_overrun; 512 }; 513 514 /* 515 * Rcv Descriptor Context. One such per Rcv Descriptor. There may 516 * be one Rcv Descriptor for normal packets, one for jumbo and may be others. 517 */ 518 struct qlcnic_host_rds_ring { 519 void __iomem *crb_rcv_producer; 520 struct rcv_desc *desc_head; 521 struct qlcnic_rx_buffer *rx_buf_arr; 522 u32 num_desc; 523 u32 producer; 524 u32 dma_size; 525 u32 skb_size; 526 u32 flags; 527 struct list_head free_list; 528 spinlock_t lock; 529 dma_addr_t phys_addr; 530 } ____cacheline_internodealigned_in_smp; 531 532 struct qlcnic_host_sds_ring { 533 u32 consumer; 534 u32 num_desc; 535 void __iomem *crb_sts_consumer; 536 537 struct qlcnic_host_tx_ring *tx_ring; 538 struct status_desc *desc_head; 539 struct qlcnic_adapter *adapter; 540 struct napi_struct napi; 541 struct list_head free_list[NUM_RCV_DESC_RINGS]; 542 543 void __iomem *crb_intr_mask; 544 int irq; 545 546 dma_addr_t phys_addr; 547 char name[IFNAMSIZ + 12]; 548 } ____cacheline_internodealigned_in_smp; 549 550 struct qlcnic_tx_queue_stats { 551 u64 xmit_on; 552 u64 xmit_off; 553 u64 xmit_called; 554 u64 xmit_finished; 555 u64 tx_bytes; 556 }; 557 558 struct qlcnic_host_tx_ring { 559 int irq; 560 void __iomem *crb_intr_mask; 561 char name[IFNAMSIZ + 12]; 562 u16 ctx_id; 563 564 u32 state; 565 u32 producer; 566 u32 sw_consumer; 567 u32 num_desc; 568 569 struct qlcnic_tx_queue_stats tx_stats; 570 571 void __iomem *crb_cmd_producer; 572 struct cmd_desc_type0 *desc_head; 573 struct qlcnic_adapter *adapter; 574 struct napi_struct napi; 575 struct qlcnic_cmd_buffer *cmd_buf_arr; 576 __le32 *hw_consumer; 577 578 dma_addr_t phys_addr; 579 dma_addr_t hw_cons_phys_addr; 580 struct netdev_queue *txq; 581 } ____cacheline_internodealigned_in_smp; 582 583 /* 584 * Receive context. There is one such structure per instance of the 585 * receive processing. Any state information that is relevant to 586 * the receive, and is must be in this structure. The global data may be 587 * present elsewhere. 588 */ 589 struct qlcnic_recv_context { 590 struct qlcnic_host_rds_ring *rds_rings; 591 struct qlcnic_host_sds_ring *sds_rings; 592 u32 state; 593 u16 context_id; 594 u16 virt_port; 595 }; 596 597 /* HW context creation */ 598 599 #define QLCNIC_OS_CRB_RETRY_COUNT 4000 600 601 #define QLCNIC_CDRP_CMD_BIT 0x80000000 602 603 /* 604 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared 605 * in the crb QLCNIC_CDRP_CRB_OFFSET. 606 */ 607 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) 608 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) 609 610 #define QLCNIC_CDRP_RSP_OK 0x00000001 611 #define QLCNIC_CDRP_RSP_FAIL 0x00000002 612 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 613 614 /* 615 * All commands must have the QLCNIC_CDRP_CMD_BIT set in 616 * the crb QLCNIC_CDRP_CRB_OFFSET. 617 */ 618 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) 619 620 #define QLCNIC_RCODE_SUCCESS 0 621 #define QLCNIC_RCODE_INVALID_ARGS 6 622 #define QLCNIC_RCODE_NOT_SUPPORTED 9 623 #define QLCNIC_RCODE_NOT_PERMITTED 10 624 #define QLCNIC_RCODE_NOT_IMPL 15 625 #define QLCNIC_RCODE_INVALID 16 626 #define QLCNIC_RCODE_TIMEOUT 17 627 #define QLCNIC_DESTROY_CTX_RESET 0 628 629 /* 630 * Capabilities Announced 631 */ 632 #define QLCNIC_CAP0_LEGACY_CONTEXT (1) 633 #define QLCNIC_CAP0_LEGACY_MN (1 << 2) 634 #define QLCNIC_CAP0_LSO (1 << 6) 635 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) 636 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) 637 #define QLCNIC_CAP0_VALIDOFF (1 << 11) 638 #define QLCNIC_CAP0_LRO_MSS (1 << 21) 639 #define QLCNIC_CAP0_TX_MULTI (1 << 22) 640 641 /* 642 * Context state 643 */ 644 #define QLCNIC_HOST_CTX_STATE_FREED 0 645 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 646 647 /* 648 * Rx context 649 */ 650 651 struct qlcnic_hostrq_sds_ring { 652 __le64 host_phys_addr; /* Ring base addr */ 653 __le32 ring_size; /* Ring entries */ 654 __le16 msi_index; 655 __le16 rsvd; /* Padding */ 656 } __packed; 657 658 struct qlcnic_hostrq_rds_ring { 659 __le64 host_phys_addr; /* Ring base addr */ 660 __le64 buff_size; /* Packet buffer size */ 661 __le32 ring_size; /* Ring entries */ 662 __le32 ring_kind; /* Class of ring */ 663 } __packed; 664 665 struct qlcnic_hostrq_rx_ctx { 666 __le64 host_rsp_dma_addr; /* Response dma'd here */ 667 __le32 capabilities[4]; /* Flag bit vector */ 668 __le32 host_int_crb_mode; /* Interrupt crb usage */ 669 __le32 host_rds_crb_mode; /* RDS crb usage */ 670 /* These ring offsets are relative to data[0] below */ 671 __le32 rds_ring_offset; /* Offset to RDS config */ 672 __le32 sds_ring_offset; /* Offset to SDS config */ 673 __le16 num_rds_rings; /* Count of RDS rings */ 674 __le16 num_sds_rings; /* Count of SDS rings */ 675 __le16 valid_field_offset; 676 u8 txrx_sds_binding; 677 u8 msix_handler; 678 u8 reserved[128]; /* reserve space for future expansion*/ 679 /* MUST BE 64-bit aligned. 680 The following is packed: 681 - N hostrq_rds_rings 682 - N hostrq_sds_rings */ 683 char data[0]; 684 } __packed; 685 686 struct qlcnic_cardrsp_rds_ring{ 687 __le32 host_producer_crb; /* Crb to use */ 688 __le32 rsvd1; /* Padding */ 689 } __packed; 690 691 struct qlcnic_cardrsp_sds_ring { 692 __le32 host_consumer_crb; /* Crb to use */ 693 __le32 interrupt_crb; /* Crb to use */ 694 } __packed; 695 696 struct qlcnic_cardrsp_rx_ctx { 697 /* These ring offsets are relative to data[0] below */ 698 __le32 rds_ring_offset; /* Offset to RDS config */ 699 __le32 sds_ring_offset; /* Offset to SDS config */ 700 __le32 host_ctx_state; /* Starting State */ 701 __le32 num_fn_per_port; /* How many PCI fn share the port */ 702 __le16 num_rds_rings; /* Count of RDS rings */ 703 __le16 num_sds_rings; /* Count of SDS rings */ 704 __le16 context_id; /* Handle for context */ 705 u8 phys_port; /* Physical id of port */ 706 u8 virt_port; /* Virtual/Logical id of port */ 707 u8 reserved[128]; /* save space for future expansion */ 708 /* MUST BE 64-bit aligned. 709 The following is packed: 710 - N cardrsp_rds_rings 711 - N cardrs_sds_rings */ 712 char data[0]; 713 } __packed; 714 715 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ 716 (sizeof(HOSTRQ_RX) + \ 717 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ 718 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) 719 720 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ 721 (sizeof(CARDRSP_RX) + \ 722 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ 723 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) 724 725 /* 726 * Tx context 727 */ 728 729 struct qlcnic_hostrq_cds_ring { 730 __le64 host_phys_addr; /* Ring base addr */ 731 __le32 ring_size; /* Ring entries */ 732 __le32 rsvd; /* Padding */ 733 } __packed; 734 735 struct qlcnic_hostrq_tx_ctx { 736 __le64 host_rsp_dma_addr; /* Response dma'd here */ 737 __le64 cmd_cons_dma_addr; /* */ 738 __le64 dummy_dma_addr; /* */ 739 __le32 capabilities[4]; /* Flag bit vector */ 740 __le32 host_int_crb_mode; /* Interrupt crb usage */ 741 __le32 rsvd1; /* Padding */ 742 __le16 rsvd2; /* Padding */ 743 __le16 interrupt_ctl; 744 __le16 msi_index; 745 __le16 rsvd3; /* Padding */ 746 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ 747 u8 reserved[128]; /* future expansion */ 748 } __packed; 749 750 struct qlcnic_cardrsp_cds_ring { 751 __le32 host_producer_crb; /* Crb to use */ 752 __le32 interrupt_crb; /* Crb to use */ 753 } __packed; 754 755 struct qlcnic_cardrsp_tx_ctx { 756 __le32 host_ctx_state; /* Starting state */ 757 __le16 context_id; /* Handle for context */ 758 u8 phys_port; /* Physical id of port */ 759 u8 virt_port; /* Virtual/Logical id of port */ 760 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ 761 u8 reserved[128]; /* future expansion */ 762 } __packed; 763 764 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) 765 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) 766 767 /* CRB */ 768 769 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 770 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 771 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 772 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 773 774 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 775 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 776 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 777 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 778 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 779 780 781 /* MAC */ 782 783 #define MC_COUNT_P3P 38 784 785 #define QLCNIC_MAC_NOOP 0 786 #define QLCNIC_MAC_ADD 1 787 #define QLCNIC_MAC_DEL 2 788 #define QLCNIC_MAC_VLAN_ADD 3 789 #define QLCNIC_MAC_VLAN_DEL 4 790 791 struct qlcnic_mac_list_s { 792 struct list_head list; 793 uint8_t mac_addr[ETH_ALEN+2]; 794 }; 795 796 /* MAC Learn */ 797 #define NO_MAC_LEARN 0 798 #define DRV_MAC_LEARN 1 799 #define FDB_MAC_LEARN 2 800 801 #define QLCNIC_HOST_REQUEST 0x13 802 #define QLCNIC_REQUEST 0x14 803 804 #define QLCNIC_MAC_EVENT 0x1 805 806 #define QLCNIC_IP_UP 2 807 #define QLCNIC_IP_DOWN 3 808 809 #define QLCNIC_ILB_MODE 0x1 810 #define QLCNIC_ELB_MODE 0x2 811 812 #define QLCNIC_LINKEVENT 0x1 813 #define QLCNIC_LB_RESPONSE 0x2 814 #define QLCNIC_IS_LB_CONFIGURED(VAL) \ 815 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) 816 817 /* 818 * Driver --> Firmware 819 */ 820 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 821 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 822 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 823 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 824 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc 825 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 826 827 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 828 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 829 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 830 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 831 832 /* 833 * Firmware --> Driver 834 */ 835 836 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f 837 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D 838 #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90 839 840 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ 841 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ 842 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ 843 844 #define QLCNIC_LRO_REQUEST_CLEANUP 4 845 846 /* Capabilites received */ 847 #define QLCNIC_FW_CAPABILITY_TSO BIT_1 848 #define QLCNIC_FW_CAPABILITY_BDG BIT_8 849 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 850 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 851 #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4 852 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 853 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 854 855 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 856 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3 857 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5 858 #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7 859 #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_8 860 861 /* module types */ 862 #define LINKEVENT_MODULE_NOT_PRESENT 1 863 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 864 #define LINKEVENT_MODULE_OPTICAL_SRLR 3 865 #define LINKEVENT_MODULE_OPTICAL_LRM 4 866 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 867 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 868 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 869 #define LINKEVENT_MODULE_TWINAX 8 870 871 #define LINKSPEED_10GBPS 10000 872 #define LINKSPEED_1GBPS 1000 873 #define LINKSPEED_100MBPS 100 874 #define LINKSPEED_10MBPS 10 875 876 #define LINKSPEED_ENCODED_10MBPS 0 877 #define LINKSPEED_ENCODED_100MBPS 1 878 #define LINKSPEED_ENCODED_1GBPS 2 879 880 #define LINKEVENT_AUTONEG_DISABLED 0 881 #define LINKEVENT_AUTONEG_ENABLED 1 882 883 #define LINKEVENT_HALF_DUPLEX 0 884 #define LINKEVENT_FULL_DUPLEX 1 885 886 #define LINKEVENT_LINKSPEED_MBPS 0 887 #define LINKEVENT_LINKSPEED_ENCODED 1 888 889 /* firmware response header: 890 * 63:58 - message type 891 * 57:56 - owner 892 * 55:53 - desc count 893 * 52:48 - reserved 894 * 47:40 - completion id 895 * 39:32 - opcode 896 * 31:16 - error code 897 * 15:00 - reserved 898 */ 899 #define qlcnic_get_nic_msg_opcode(msg_hdr) \ 900 ((msg_hdr >> 32) & 0xFF) 901 902 struct qlcnic_fw_msg { 903 union { 904 struct { 905 u64 hdr; 906 u64 body[7]; 907 }; 908 u64 words[8]; 909 }; 910 }; 911 912 struct qlcnic_nic_req { 913 __le64 qhdr; 914 __le64 req_hdr; 915 __le64 words[6]; 916 } __packed; 917 918 struct qlcnic_mac_req { 919 u8 op; 920 u8 tag; 921 u8 mac_addr[6]; 922 }; 923 924 struct qlcnic_vlan_req { 925 __le16 vlan_id; 926 __le16 rsvd[3]; 927 } __packed; 928 929 struct qlcnic_ipaddr { 930 __be32 ipv4; 931 __be32 ipv6[4]; 932 }; 933 934 #define QLCNIC_MSI_ENABLED 0x02 935 #define QLCNIC_MSIX_ENABLED 0x04 936 #define QLCNIC_LRO_ENABLED 0x01 937 #define QLCNIC_LRO_DISABLED 0x00 938 #define QLCNIC_BRIDGE_ENABLED 0X10 939 #define QLCNIC_DIAG_ENABLED 0x20 940 #define QLCNIC_ESWITCH_ENABLED 0x40 941 #define QLCNIC_ADAPTER_INITIALIZED 0x80 942 #define QLCNIC_TAGGING_ENABLED 0x100 943 #define QLCNIC_MACSPOOF 0x200 944 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 945 #define QLCNIC_PROMISC_DISABLED 0x800 946 #define QLCNIC_NEED_FLR 0x1000 947 #define QLCNIC_FW_RESET_OWNER 0x2000 948 #define QLCNIC_FW_HANG 0x4000 949 #define QLCNIC_FW_LRO_MSS_CAP 0x8000 950 #define QLCNIC_TX_INTR_SHARED 0x10000 951 #define QLCNIC_APP_CHANGED_FLAGS 0x20000 952 #define QLCNIC_HAS_PHYS_PORT_ID 0x40000 953 954 #define QLCNIC_IS_MSI_FAMILY(adapter) \ 955 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) 956 #define QLCNIC_IS_TSO_CAPABLE(adapter) \ 957 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO) 958 959 #define QLCNIC_BEACON_EANBLE 0xC 960 #define QLCNIC_BEACON_DISABLE 0xD 961 962 #define QLCNIC_MSIX_TBL_SPACE 8192 963 #define QLCNIC_PCI_REG_MSIX_TBL 0x44 964 #define QLCNIC_MSIX_TBL_PGSIZE 4096 965 966 #define QLCNIC_ADAPTER_UP_MAGIC 777 967 968 #define __QLCNIC_FW_ATTACHED 0 969 #define __QLCNIC_DEV_UP 1 970 #define __QLCNIC_RESETTING 2 971 #define __QLCNIC_START_FW 4 972 #define __QLCNIC_AER 5 973 #define __QLCNIC_DIAG_RES_ALLOC 6 974 #define __QLCNIC_LED_ENABLE 7 975 #define __QLCNIC_ELB_INPROGRESS 8 976 #define __QLCNIC_MULTI_TX_UNIQUE 9 977 #define __QLCNIC_SRIOV_ENABLE 10 978 #define __QLCNIC_SRIOV_CAPABLE 11 979 #define __QLCNIC_MBX_POLL_ENABLE 12 980 #define __QLCNIC_DIAG_MODE 13 981 #define __QLCNIC_MAINTENANCE_MODE 16 982 983 #define QLCNIC_INTERRUPT_TEST 1 984 #define QLCNIC_LOOPBACK_TEST 2 985 #define QLCNIC_LED_TEST 3 986 987 #define QLCNIC_FILTER_AGE 80 988 #define QLCNIC_READD_AGE 20 989 #define QLCNIC_LB_MAX_FILTERS 64 990 #define QLCNIC_LB_BUCKET_SIZE 32 991 #define QLCNIC_ILB_MAX_RCV_LOOP 10 992 993 struct qlcnic_filter { 994 struct hlist_node fnode; 995 u8 faddr[ETH_ALEN]; 996 u16 vlan_id; 997 unsigned long ftime; 998 }; 999 1000 struct qlcnic_filter_hash { 1001 struct hlist_head *fhead; 1002 u8 fnum; 1003 u16 fmax; 1004 u16 fbucket_size; 1005 }; 1006 1007 /* Mailbox specific data structures */ 1008 struct qlcnic_mailbox { 1009 struct workqueue_struct *work_q; 1010 struct qlcnic_adapter *adapter; 1011 struct qlcnic_mbx_ops *ops; 1012 struct work_struct work; 1013 struct completion completion; 1014 struct list_head cmd_q; 1015 unsigned long status; 1016 spinlock_t queue_lock; /* Mailbox queue lock */ 1017 spinlock_t aen_lock; /* Mailbox response/AEN lock */ 1018 atomic_t rsp_status; 1019 u32 num_cmds; 1020 }; 1021 1022 struct qlcnic_adapter { 1023 struct qlcnic_hardware_context *ahw; 1024 struct qlcnic_recv_context *recv_ctx; 1025 struct qlcnic_host_tx_ring *tx_ring; 1026 struct net_device *netdev; 1027 struct pci_dev *pdev; 1028 1029 unsigned long state; 1030 u32 flags; 1031 1032 u16 num_txd; 1033 u16 num_rxd; 1034 u16 num_jumbo_rxd; 1035 u16 max_rxd; 1036 u16 max_jumbo_rxd; 1037 1038 u8 max_rds_rings; 1039 1040 u8 max_sds_rings; /* max sds rings supported by adapter */ 1041 u8 max_tx_rings; /* max tx rings supported by adapter */ 1042 1043 u8 drv_tx_rings; /* max tx rings supported by driver */ 1044 u8 drv_sds_rings; /* max sds rings supported by driver */ 1045 1046 u8 rx_csum; 1047 u8 portnum; 1048 1049 u8 fw_wait_cnt; 1050 u8 fw_fail_cnt; 1051 u8 tx_timeo_cnt; 1052 u8 need_fw_reset; 1053 u8 reset_ctx_cnt; 1054 1055 u16 is_up; 1056 u16 rx_pvid; 1057 u16 tx_pvid; 1058 1059 u32 irq; 1060 u32 heartbeat; 1061 1062 u8 dev_state; 1063 u8 reset_ack_timeo; 1064 u8 dev_init_timeo; 1065 1066 u8 mac_addr[ETH_ALEN]; 1067 1068 u64 dev_rst_time; 1069 bool drv_mac_learn; 1070 bool fdb_mac_learn; 1071 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1072 u8 flash_mfg_id; 1073 struct qlcnic_npar_info *npars; 1074 struct qlcnic_eswitch *eswitch; 1075 struct qlcnic_nic_template *nic_ops; 1076 1077 struct qlcnic_adapter_stats stats; 1078 struct list_head mac_list; 1079 1080 void __iomem *tgt_mask_reg; 1081 void __iomem *tgt_status_reg; 1082 void __iomem *crb_int_state_reg; 1083 void __iomem *isr_int_vec; 1084 1085 struct msix_entry *msix_entries; 1086 struct workqueue_struct *qlcnic_wq; 1087 struct delayed_work fw_work; 1088 struct delayed_work idc_aen_work; 1089 struct delayed_work mbx_poll_work; 1090 struct qlcnic_dcb *dcb; 1091 1092 struct qlcnic_filter_hash fhash; 1093 struct qlcnic_filter_hash rx_fhash; 1094 struct list_head vf_mc_list; 1095 1096 spinlock_t tx_clean_lock; 1097 spinlock_t mac_learn_lock; 1098 /* spinlock for catching rcv filters for eswitch traffic */ 1099 spinlock_t rx_mac_learn_lock; 1100 u32 file_prd_off; /*File fw product offset*/ 1101 u32 fw_version; 1102 u32 offload_flags; 1103 const struct firmware *fw; 1104 }; 1105 1106 struct qlcnic_info_le { 1107 __le16 pci_func; 1108 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ 1109 __le16 phys_port; 1110 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ 1111 1112 __le32 capabilities; 1113 u8 max_mac_filters; 1114 u8 reserved1; 1115 __le16 max_mtu; 1116 1117 __le16 max_tx_ques; 1118 __le16 max_rx_ques; 1119 __le16 min_tx_bw; 1120 __le16 max_tx_bw; 1121 __le32 op_type; 1122 __le16 max_bw_reg_offset; 1123 __le16 max_linkspeed_reg_offset; 1124 __le32 capability1; 1125 __le32 capability2; 1126 __le32 capability3; 1127 __le16 max_tx_mac_filters; 1128 __le16 max_rx_mcast_mac_filters; 1129 __le16 max_rx_ucast_mac_filters; 1130 __le16 max_rx_ip_addr; 1131 __le16 max_rx_lro_flow; 1132 __le16 max_rx_status_rings; 1133 __le16 max_rx_buf_rings; 1134 __le16 max_tx_vlan_keys; 1135 u8 total_pf; 1136 u8 total_rss_engines; 1137 __le16 max_vports; 1138 __le16 linkstate_reg_offset; 1139 __le16 bit_offsets; 1140 __le16 max_local_ipv6_addrs; 1141 __le16 max_remote_ipv6_addrs; 1142 u8 reserved2[56]; 1143 } __packed; 1144 1145 struct qlcnic_info { 1146 u16 pci_func; 1147 u16 op_mode; 1148 u16 phys_port; 1149 u16 switch_mode; 1150 u32 capabilities; 1151 u8 max_mac_filters; 1152 u16 max_mtu; 1153 u16 max_tx_ques; 1154 u16 max_rx_ques; 1155 u16 min_tx_bw; 1156 u16 max_tx_bw; 1157 u32 op_type; 1158 u16 max_bw_reg_offset; 1159 u16 max_linkspeed_reg_offset; 1160 u32 capability1; 1161 u32 capability2; 1162 u32 capability3; 1163 u16 max_tx_mac_filters; 1164 u16 max_rx_mcast_mac_filters; 1165 u16 max_rx_ucast_mac_filters; 1166 u16 max_rx_ip_addr; 1167 u16 max_rx_lro_flow; 1168 u16 max_rx_status_rings; 1169 u16 max_rx_buf_rings; 1170 u16 max_tx_vlan_keys; 1171 u8 total_pf; 1172 u8 total_rss_engines; 1173 u16 max_vports; 1174 u16 linkstate_reg_offset; 1175 u16 bit_offsets; 1176 u16 max_local_ipv6_addrs; 1177 u16 max_remote_ipv6_addrs; 1178 }; 1179 1180 struct qlcnic_pci_info_le { 1181 __le16 id; /* pci function id */ 1182 __le16 active; /* 1 = Enabled */ 1183 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ 1184 __le16 default_port; /* default port number */ 1185 1186 __le16 tx_min_bw; /* Multiple of 100mbpc */ 1187 __le16 tx_max_bw; 1188 __le16 reserved1[2]; 1189 1190 u8 mac[ETH_ALEN]; 1191 __le16 func_count; 1192 u8 reserved2[104]; 1193 1194 } __packed; 1195 1196 struct qlcnic_pci_info { 1197 u16 id; 1198 u16 active; 1199 u16 type; 1200 u16 default_port; 1201 u16 tx_min_bw; 1202 u16 tx_max_bw; 1203 u8 mac[ETH_ALEN]; 1204 u16 func_count; 1205 }; 1206 1207 struct qlcnic_npar_info { 1208 bool eswitch_status; 1209 u16 pvid; 1210 u16 min_bw; 1211 u16 max_bw; 1212 u8 phy_port; 1213 u8 type; 1214 u8 active; 1215 u8 enable_pm; 1216 u8 dest_npar; 1217 u8 discard_tagged; 1218 u8 mac_override; 1219 u8 mac_anti_spoof; 1220 u8 promisc_mode; 1221 u8 offload_flags; 1222 u8 pci_func; 1223 u8 mac[ETH_ALEN]; 1224 }; 1225 1226 struct qlcnic_eswitch { 1227 u8 port; 1228 u8 active_vports; 1229 u8 active_vlans; 1230 u8 active_ucast_filters; 1231 u8 max_ucast_filters; 1232 u8 max_active_vlans; 1233 1234 u32 flags; 1235 #define QLCNIC_SWITCH_ENABLE BIT_1 1236 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 1237 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 1238 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 1239 }; 1240 1241 1242 /* Return codes for Error handling */ 1243 #define QL_STATUS_INVALID_PARAM -1 1244 1245 #define MAX_BW 100 /* % of link speed */ 1246 #define MAX_VLAN_ID 4095 1247 #define MIN_VLAN_ID 2 1248 #define DEFAULT_MAC_LEARN 1 1249 1250 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) 1251 #define IS_VALID_BW(bw) (bw <= MAX_BW) 1252 1253 struct qlcnic_pci_func_cfg { 1254 u16 func_type; 1255 u16 min_bw; 1256 u16 max_bw; 1257 u16 port_num; 1258 u8 pci_func; 1259 u8 func_state; 1260 u8 def_mac_addr[6]; 1261 }; 1262 1263 struct qlcnic_npar_func_cfg { 1264 u32 fw_capab; 1265 u16 port_num; 1266 u16 min_bw; 1267 u16 max_bw; 1268 u16 max_tx_queues; 1269 u16 max_rx_queues; 1270 u8 pci_func; 1271 u8 op_mode; 1272 }; 1273 1274 struct qlcnic_pm_func_cfg { 1275 u8 pci_func; 1276 u8 action; 1277 u8 dest_npar; 1278 u8 reserved[5]; 1279 }; 1280 1281 struct qlcnic_esw_func_cfg { 1282 u16 vlan_id; 1283 u8 op_mode; 1284 u8 op_type; 1285 u8 pci_func; 1286 u8 host_vlan_tag; 1287 u8 promisc_mode; 1288 u8 discard_tagged; 1289 u8 mac_override; 1290 u8 mac_anti_spoof; 1291 u8 offload_flags; 1292 u8 reserved[5]; 1293 }; 1294 1295 #define QLCNIC_STATS_VERSION 1 1296 #define QLCNIC_STATS_PORT 1 1297 #define QLCNIC_STATS_ESWITCH 2 1298 #define QLCNIC_QUERY_RX_COUNTER 0 1299 #define QLCNIC_QUERY_TX_COUNTER 1 1300 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL 1301 #define QLCNIC_FILL_STATS(VAL1) \ 1302 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) 1303 #define QLCNIC_MAC_STATS 1 1304 #define QLCNIC_ESW_STATS 2 1305 1306 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ 1307 do { \ 1308 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ 1309 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1310 (VAL1) = (VAL2); \ 1311 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ 1312 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1313 (VAL1) += (VAL2); \ 1314 } while (0) 1315 1316 struct qlcnic_mac_statistics_le { 1317 __le64 mac_tx_frames; 1318 __le64 mac_tx_bytes; 1319 __le64 mac_tx_mcast_pkts; 1320 __le64 mac_tx_bcast_pkts; 1321 __le64 mac_tx_pause_cnt; 1322 __le64 mac_tx_ctrl_pkt; 1323 __le64 mac_tx_lt_64b_pkts; 1324 __le64 mac_tx_lt_127b_pkts; 1325 __le64 mac_tx_lt_255b_pkts; 1326 __le64 mac_tx_lt_511b_pkts; 1327 __le64 mac_tx_lt_1023b_pkts; 1328 __le64 mac_tx_lt_1518b_pkts; 1329 __le64 mac_tx_gt_1518b_pkts; 1330 __le64 rsvd1[3]; 1331 1332 __le64 mac_rx_frames; 1333 __le64 mac_rx_bytes; 1334 __le64 mac_rx_mcast_pkts; 1335 __le64 mac_rx_bcast_pkts; 1336 __le64 mac_rx_pause_cnt; 1337 __le64 mac_rx_ctrl_pkt; 1338 __le64 mac_rx_lt_64b_pkts; 1339 __le64 mac_rx_lt_127b_pkts; 1340 __le64 mac_rx_lt_255b_pkts; 1341 __le64 mac_rx_lt_511b_pkts; 1342 __le64 mac_rx_lt_1023b_pkts; 1343 __le64 mac_rx_lt_1518b_pkts; 1344 __le64 mac_rx_gt_1518b_pkts; 1345 __le64 rsvd2[3]; 1346 1347 __le64 mac_rx_length_error; 1348 __le64 mac_rx_length_small; 1349 __le64 mac_rx_length_large; 1350 __le64 mac_rx_jabber; 1351 __le64 mac_rx_dropped; 1352 __le64 mac_rx_crc_error; 1353 __le64 mac_align_error; 1354 } __packed; 1355 1356 struct qlcnic_mac_statistics { 1357 u64 mac_tx_frames; 1358 u64 mac_tx_bytes; 1359 u64 mac_tx_mcast_pkts; 1360 u64 mac_tx_bcast_pkts; 1361 u64 mac_tx_pause_cnt; 1362 u64 mac_tx_ctrl_pkt; 1363 u64 mac_tx_lt_64b_pkts; 1364 u64 mac_tx_lt_127b_pkts; 1365 u64 mac_tx_lt_255b_pkts; 1366 u64 mac_tx_lt_511b_pkts; 1367 u64 mac_tx_lt_1023b_pkts; 1368 u64 mac_tx_lt_1518b_pkts; 1369 u64 mac_tx_gt_1518b_pkts; 1370 u64 rsvd1[3]; 1371 u64 mac_rx_frames; 1372 u64 mac_rx_bytes; 1373 u64 mac_rx_mcast_pkts; 1374 u64 mac_rx_bcast_pkts; 1375 u64 mac_rx_pause_cnt; 1376 u64 mac_rx_ctrl_pkt; 1377 u64 mac_rx_lt_64b_pkts; 1378 u64 mac_rx_lt_127b_pkts; 1379 u64 mac_rx_lt_255b_pkts; 1380 u64 mac_rx_lt_511b_pkts; 1381 u64 mac_rx_lt_1023b_pkts; 1382 u64 mac_rx_lt_1518b_pkts; 1383 u64 mac_rx_gt_1518b_pkts; 1384 u64 rsvd2[3]; 1385 u64 mac_rx_length_error; 1386 u64 mac_rx_length_small; 1387 u64 mac_rx_length_large; 1388 u64 mac_rx_jabber; 1389 u64 mac_rx_dropped; 1390 u64 mac_rx_crc_error; 1391 u64 mac_align_error; 1392 }; 1393 1394 struct qlcnic_esw_stats_le { 1395 __le16 context_id; 1396 __le16 version; 1397 __le16 size; 1398 __le16 unused; 1399 __le64 unicast_frames; 1400 __le64 multicast_frames; 1401 __le64 broadcast_frames; 1402 __le64 dropped_frames; 1403 __le64 errors; 1404 __le64 local_frames; 1405 __le64 numbytes; 1406 __le64 rsvd[3]; 1407 } __packed; 1408 1409 struct __qlcnic_esw_statistics { 1410 u16 context_id; 1411 u16 version; 1412 u16 size; 1413 u16 unused; 1414 u64 unicast_frames; 1415 u64 multicast_frames; 1416 u64 broadcast_frames; 1417 u64 dropped_frames; 1418 u64 errors; 1419 u64 local_frames; 1420 u64 numbytes; 1421 u64 rsvd[3]; 1422 }; 1423 1424 struct qlcnic_esw_statistics { 1425 struct __qlcnic_esw_statistics rx; 1426 struct __qlcnic_esw_statistics tx; 1427 }; 1428 1429 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed 1430 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed 1431 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed 1432 #define QLCNIC_FORCE_FW_RESET 0xdeaddead 1433 #define QLCNIC_SET_QUIESCENT 0xadd00010 1434 #define QLCNIC_RESET_QUIESCENT 0xadd00020 1435 1436 struct _cdrp_cmd { 1437 u32 num; 1438 u32 *arg; 1439 }; 1440 1441 struct qlcnic_cmd_args { 1442 struct completion completion; 1443 struct list_head list; 1444 struct _cdrp_cmd req; 1445 struct _cdrp_cmd rsp; 1446 atomic_t rsp_status; 1447 int pay_size; 1448 u32 rsp_opcode; 1449 u32 total_cmds; 1450 u32 op_type; 1451 u32 type; 1452 u32 cmd_op; 1453 u32 *hdr; /* Back channel message header */ 1454 u32 *pay; /* Back channel message payload */ 1455 u8 func_num; 1456 }; 1457 1458 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); 1459 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); 1460 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); 1461 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); 1462 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); 1463 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); 1464 1465 #define ADDR_IN_RANGE(addr, low, high) \ 1466 (((addr) < (high)) && ((addr) >= (low))) 1467 1468 #define QLCRD32(adapter, off, err) \ 1469 (adapter->ahw->hw_ops->read_reg)(adapter, off, err) 1470 1471 #define QLCWR32(adapter, off, val) \ 1472 adapter->ahw->hw_ops->write_reg(adapter, off, val) 1473 1474 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); 1475 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); 1476 1477 #define qlcnic_rom_lock(a) \ 1478 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) 1479 #define qlcnic_rom_unlock(a) \ 1480 qlcnic_pcie_sem_unlock((a), 2) 1481 #define qlcnic_phy_lock(a) \ 1482 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) 1483 #define qlcnic_phy_unlock(a) \ 1484 qlcnic_pcie_sem_unlock((a), 3) 1485 #define qlcnic_sw_lock(a) \ 1486 qlcnic_pcie_sem_lock((a), 6, 0) 1487 #define qlcnic_sw_unlock(a) \ 1488 qlcnic_pcie_sem_unlock((a), 6) 1489 #define crb_win_lock(a) \ 1490 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) 1491 #define crb_win_unlock(a) \ 1492 qlcnic_pcie_sem_unlock((a), 7) 1493 1494 #define __QLCNIC_MAX_LED_RATE 0xf 1495 #define __QLCNIC_MAX_LED_STATE 0x2 1496 1497 #define MAX_CTL_CHECK 1000 1498 1499 int qlcnic_wol_supported(struct qlcnic_adapter *adapter); 1500 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); 1501 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); 1502 int qlcnic_dump_fw(struct qlcnic_adapter *); 1503 int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *); 1504 bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *); 1505 pci_ers_result_t qlcnic_82xx_io_error_detected(struct pci_dev *, 1506 pci_channel_state_t); 1507 pci_ers_result_t qlcnic_82xx_io_slot_reset(struct pci_dev *); 1508 void qlcnic_82xx_io_resume(struct pci_dev *); 1509 1510 /* Functions from qlcnic_init.c */ 1511 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int); 1512 int qlcnic_load_firmware(struct qlcnic_adapter *adapter); 1513 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); 1514 void qlcnic_request_firmware(struct qlcnic_adapter *adapter); 1515 void qlcnic_release_firmware(struct qlcnic_adapter *adapter); 1516 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); 1517 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); 1518 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); 1519 1520 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); 1521 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, 1522 u8 *bytes, size_t size); 1523 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); 1524 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); 1525 1526 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); 1527 1528 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); 1529 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); 1530 1531 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); 1532 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); 1533 1534 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); 1535 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); 1536 void qlcnic_release_tx_buffers(struct qlcnic_adapter *, 1537 struct qlcnic_host_tx_ring *); 1538 1539 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); 1540 void qlcnic_watchdog_task(struct work_struct *work); 1541 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, 1542 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id); 1543 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); 1544 void qlcnic_set_multi(struct net_device *netdev); 1545 void __qlcnic_set_multi(struct net_device *, u16); 1546 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16); 1547 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *); 1548 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter); 1549 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *); 1550 1551 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); 1552 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32); 1553 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); 1554 netdev_features_t qlcnic_fix_features(struct net_device *netdev, 1555 netdev_features_t features); 1556 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); 1557 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); 1558 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); 1559 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); 1560 1561 /* Functions from qlcnic_ethtool.c */ 1562 int qlcnic_check_loopback_buff(unsigned char *, u8 []); 1563 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8); 1564 int qlcnic_loopback_test(struct net_device *, u8); 1565 1566 /* Functions from qlcnic_main.c */ 1567 int qlcnic_reset_context(struct qlcnic_adapter *); 1568 void qlcnic_diag_free_res(struct net_device *netdev, int); 1569 int qlcnic_diag_alloc_res(struct net_device *netdev, int); 1570 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *, struct net_device *); 1571 void qlcnic_set_tx_ring_count(struct qlcnic_adapter *, u8); 1572 void qlcnic_set_sds_ring_count(struct qlcnic_adapter *, u8); 1573 int qlcnic_setup_rings(struct qlcnic_adapter *, u8, u8); 1574 int qlcnic_validate_rings(struct qlcnic_adapter *, __u32, int); 1575 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); 1576 void qlcnic_82xx_set_mac_filter_count(struct qlcnic_adapter *); 1577 int qlcnic_enable_msix(struct qlcnic_adapter *, u32); 1578 void qlcnic_set_drv_version(struct qlcnic_adapter *); 1579 1580 /* eSwitch management functions */ 1581 int qlcnic_config_switch_port(struct qlcnic_adapter *, 1582 struct qlcnic_esw_func_cfg *); 1583 1584 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, 1585 struct qlcnic_esw_func_cfg *); 1586 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); 1587 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, 1588 struct __qlcnic_esw_statistics *); 1589 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, 1590 struct __qlcnic_esw_statistics *); 1591 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); 1592 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); 1593 1594 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); 1595 1596 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); 1597 void qlcnic_free_sds_rings(struct qlcnic_recv_context *); 1598 void qlcnic_advert_link_change(struct qlcnic_adapter *, int); 1599 void qlcnic_free_tx_rings(struct qlcnic_adapter *); 1600 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); 1601 void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1602 1603 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); 1604 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); 1605 void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter); 1606 void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter); 1607 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); 1608 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); 1609 int qlcnic_82xx_get_settings(struct qlcnic_adapter *, struct ethtool_cmd *); 1610 1611 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); 1612 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); 1613 void qlcnic_set_vlan_config(struct qlcnic_adapter *, 1614 struct qlcnic_esw_func_cfg *); 1615 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, 1616 struct qlcnic_esw_func_cfg *); 1617 1618 void qlcnic_down(struct qlcnic_adapter *, struct net_device *); 1619 int qlcnic_up(struct qlcnic_adapter *, struct net_device *); 1620 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *); 1621 void qlcnic_detach(struct qlcnic_adapter *); 1622 void qlcnic_teardown_intr(struct qlcnic_adapter *); 1623 int qlcnic_attach(struct qlcnic_adapter *); 1624 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *); 1625 void qlcnic_restore_indev_addr(struct net_device *, unsigned long); 1626 1627 int qlcnic_check_temp(struct qlcnic_adapter *); 1628 int qlcnic_init_pci_info(struct qlcnic_adapter *); 1629 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *); 1630 int qlcnic_reset_npar_config(struct qlcnic_adapter *); 1631 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *); 1632 void qlcnic_add_lb_filter(struct qlcnic_adapter *, struct sk_buff *, int, u16); 1633 int qlcnic_get_beacon_state(struct qlcnic_adapter *, u8 *); 1634 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter); 1635 int qlcnic_read_mac_addr(struct qlcnic_adapter *); 1636 int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int); 1637 void qlcnic_set_netdev_features(struct qlcnic_adapter *, 1638 struct qlcnic_esw_func_cfg *); 1639 void qlcnic_sriov_vf_schedule_multi(struct net_device *); 1640 void qlcnic_vf_add_mc_list(struct net_device *, u16); 1641 1642 /* 1643 * QLOGIC Board information 1644 */ 1645 1646 #define QLCNIC_MAX_BOARD_NAME_LEN 100 1647 struct qlcnic_board_info { 1648 unsigned short vendor; 1649 unsigned short device; 1650 unsigned short sub_vendor; 1651 unsigned short sub_device; 1652 char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; 1653 }; 1654 1655 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) 1656 { 1657 if (likely(tx_ring->producer < tx_ring->sw_consumer)) 1658 return tx_ring->sw_consumer - tx_ring->producer; 1659 else 1660 return tx_ring->sw_consumer + tx_ring->num_desc - 1661 tx_ring->producer; 1662 } 1663 1664 static inline int qlcnic_set_real_num_queues(struct qlcnic_adapter *adapter, 1665 struct net_device *netdev) 1666 { 1667 int err; 1668 1669 netdev->num_tx_queues = adapter->drv_tx_rings; 1670 netdev->real_num_tx_queues = adapter->drv_tx_rings; 1671 1672 err = netif_set_real_num_tx_queues(netdev, adapter->drv_tx_rings); 1673 if (err) 1674 dev_err(&adapter->pdev->dev, "failed to set %d Tx queues\n", 1675 adapter->drv_tx_rings); 1676 else 1677 dev_info(&adapter->pdev->dev, "Set %d Tx queues\n", 1678 adapter->drv_tx_rings); 1679 1680 return err; 1681 } 1682 1683 struct qlcnic_nic_template { 1684 int (*config_bridged_mode) (struct qlcnic_adapter *, u32); 1685 int (*config_led) (struct qlcnic_adapter *, u32, u32); 1686 int (*start_firmware) (struct qlcnic_adapter *); 1687 int (*init_driver) (struct qlcnic_adapter *); 1688 void (*request_reset) (struct qlcnic_adapter *, u32); 1689 void (*cancel_idc_work) (struct qlcnic_adapter *); 1690 int (*napi_add)(struct qlcnic_adapter *, struct net_device *); 1691 void (*napi_del)(struct qlcnic_adapter *); 1692 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); 1693 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); 1694 int (*shutdown)(struct pci_dev *); 1695 int (*resume)(struct qlcnic_adapter *); 1696 }; 1697 1698 struct qlcnic_mbx_ops { 1699 int (*enqueue_cmd) (struct qlcnic_adapter *, 1700 struct qlcnic_cmd_args *, unsigned long *); 1701 void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1702 void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1703 void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1704 void (*nofity_fw) (struct qlcnic_adapter *, u8); 1705 }; 1706 1707 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *); 1708 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *); 1709 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx); 1710 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx); 1711 1712 /* Adapter hardware abstraction */ 1713 struct qlcnic_hardware_ops { 1714 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); 1715 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); 1716 int (*read_reg) (struct qlcnic_adapter *, ulong, int *); 1717 int (*write_reg) (struct qlcnic_adapter *, ulong, u32); 1718 void (*get_ocm_win) (struct qlcnic_hardware_context *); 1719 int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8); 1720 int (*setup_intr) (struct qlcnic_adapter *); 1721 int (*alloc_mbx_args)(struct qlcnic_cmd_args *, 1722 struct qlcnic_adapter *, u32); 1723 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1724 void (*get_func_no) (struct qlcnic_adapter *); 1725 int (*api_lock) (struct qlcnic_adapter *); 1726 void (*api_unlock) (struct qlcnic_adapter *); 1727 void (*add_sysfs) (struct qlcnic_adapter *); 1728 void (*remove_sysfs) (struct qlcnic_adapter *); 1729 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); 1730 int (*create_rx_ctx) (struct qlcnic_adapter *); 1731 int (*create_tx_ctx) (struct qlcnic_adapter *, 1732 struct qlcnic_host_tx_ring *, int); 1733 void (*del_rx_ctx) (struct qlcnic_adapter *); 1734 void (*del_tx_ctx) (struct qlcnic_adapter *, 1735 struct qlcnic_host_tx_ring *); 1736 int (*setup_link_event) (struct qlcnic_adapter *, int); 1737 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); 1738 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); 1739 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); 1740 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8); 1741 void (*napi_enable) (struct qlcnic_adapter *); 1742 void (*napi_disable) (struct qlcnic_adapter *); 1743 void (*config_intr_coal) (struct qlcnic_adapter *); 1744 int (*config_rss) (struct qlcnic_adapter *, int); 1745 int (*config_hw_lro) (struct qlcnic_adapter *, int); 1746 int (*config_loopback) (struct qlcnic_adapter *, u8); 1747 int (*clear_loopback) (struct qlcnic_adapter *, u8); 1748 int (*config_promisc_mode) (struct qlcnic_adapter *, u32); 1749 void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16); 1750 int (*get_board_info) (struct qlcnic_adapter *); 1751 void (*set_mac_filter_count) (struct qlcnic_adapter *); 1752 void (*free_mac_list) (struct qlcnic_adapter *); 1753 int (*read_phys_port_id) (struct qlcnic_adapter *); 1754 pci_ers_result_t (*io_error_detected) (struct pci_dev *, 1755 pci_channel_state_t); 1756 pci_ers_result_t (*io_slot_reset) (struct pci_dev *); 1757 void (*io_resume) (struct pci_dev *); 1758 }; 1759 1760 extern struct qlcnic_nic_template qlcnic_vf_ops; 1761 1762 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) 1763 { 1764 return adapter->nic_ops->start_firmware(adapter); 1765 } 1766 1767 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, 1768 loff_t offset, size_t size) 1769 { 1770 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); 1771 } 1772 1773 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, 1774 loff_t offset, size_t size) 1775 { 1776 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); 1777 } 1778 1779 static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, 1780 ulong off, u32 data) 1781 { 1782 return adapter->ahw->hw_ops->write_reg(adapter, off, data); 1783 } 1784 1785 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, 1786 u8 *mac, u8 function) 1787 { 1788 return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function); 1789 } 1790 1791 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter) 1792 { 1793 return adapter->ahw->hw_ops->setup_intr(adapter); 1794 } 1795 1796 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, 1797 struct qlcnic_adapter *adapter, u32 arg) 1798 { 1799 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); 1800 } 1801 1802 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, 1803 struct qlcnic_cmd_args *cmd) 1804 { 1805 if (adapter->ahw->hw_ops->mbx_cmd) 1806 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); 1807 1808 return -EIO; 1809 } 1810 1811 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) 1812 { 1813 adapter->ahw->hw_ops->get_func_no(adapter); 1814 } 1815 1816 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) 1817 { 1818 return adapter->ahw->hw_ops->api_lock(adapter); 1819 } 1820 1821 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) 1822 { 1823 adapter->ahw->hw_ops->api_unlock(adapter); 1824 } 1825 1826 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) 1827 { 1828 if (adapter->ahw->hw_ops->add_sysfs) 1829 adapter->ahw->hw_ops->add_sysfs(adapter); 1830 } 1831 1832 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) 1833 { 1834 if (adapter->ahw->hw_ops->remove_sysfs) 1835 adapter->ahw->hw_ops->remove_sysfs(adapter); 1836 } 1837 1838 static inline void 1839 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) 1840 { 1841 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); 1842 } 1843 1844 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) 1845 { 1846 return adapter->ahw->hw_ops->create_rx_ctx(adapter); 1847 } 1848 1849 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, 1850 struct qlcnic_host_tx_ring *ptr, 1851 int ring) 1852 { 1853 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); 1854 } 1855 1856 static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter) 1857 { 1858 return adapter->ahw->hw_ops->del_rx_ctx(adapter); 1859 } 1860 1861 static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter, 1862 struct qlcnic_host_tx_ring *ptr) 1863 { 1864 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr); 1865 } 1866 1867 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, 1868 int enable) 1869 { 1870 return adapter->ahw->hw_ops->setup_link_event(adapter, enable); 1871 } 1872 1873 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, 1874 struct qlcnic_info *info, u8 id) 1875 { 1876 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); 1877 } 1878 1879 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, 1880 struct qlcnic_pci_info *info) 1881 { 1882 return adapter->ahw->hw_ops->get_pci_info(adapter, info); 1883 } 1884 1885 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, 1886 struct qlcnic_info *info) 1887 { 1888 return adapter->ahw->hw_ops->set_nic_info(adapter, info); 1889 } 1890 1891 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, 1892 u8 *addr, u16 id, u8 cmd) 1893 { 1894 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); 1895 } 1896 1897 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, 1898 struct net_device *netdev) 1899 { 1900 return adapter->nic_ops->napi_add(adapter, netdev); 1901 } 1902 1903 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter) 1904 { 1905 adapter->nic_ops->napi_del(adapter); 1906 } 1907 1908 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) 1909 { 1910 adapter->ahw->hw_ops->napi_enable(adapter); 1911 } 1912 1913 static inline int __qlcnic_shutdown(struct pci_dev *pdev) 1914 { 1915 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 1916 1917 return adapter->nic_ops->shutdown(pdev); 1918 } 1919 1920 static inline int __qlcnic_resume(struct qlcnic_adapter *adapter) 1921 { 1922 return adapter->nic_ops->resume(adapter); 1923 } 1924 1925 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) 1926 { 1927 adapter->ahw->hw_ops->napi_disable(adapter); 1928 } 1929 1930 static inline void qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter) 1931 { 1932 adapter->ahw->hw_ops->config_intr_coal(adapter); 1933 } 1934 1935 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) 1936 { 1937 return adapter->ahw->hw_ops->config_rss(adapter, enable); 1938 } 1939 1940 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, 1941 int enable) 1942 { 1943 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); 1944 } 1945 1946 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1947 { 1948 return adapter->ahw->hw_ops->config_loopback(adapter, mode); 1949 } 1950 1951 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1952 { 1953 return adapter->ahw->hw_ops->clear_loopback(adapter, mode); 1954 } 1955 1956 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, 1957 u32 mode) 1958 { 1959 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); 1960 } 1961 1962 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, 1963 u64 *addr, u16 id) 1964 { 1965 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id); 1966 } 1967 1968 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) 1969 { 1970 return adapter->ahw->hw_ops->get_board_info(adapter); 1971 } 1972 1973 static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter) 1974 { 1975 return adapter->ahw->hw_ops->free_mac_list(adapter); 1976 } 1977 1978 static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter) 1979 { 1980 if (adapter->ahw->hw_ops->set_mac_filter_count) 1981 adapter->ahw->hw_ops->set_mac_filter_count(adapter); 1982 } 1983 1984 static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter) 1985 { 1986 if (adapter->ahw->hw_ops->read_phys_port_id) 1987 adapter->ahw->hw_ops->read_phys_port_id(adapter); 1988 } 1989 1990 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, 1991 u32 key) 1992 { 1993 if (adapter->nic_ops->request_reset) 1994 adapter->nic_ops->request_reset(adapter, key); 1995 } 1996 1997 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) 1998 { 1999 if (adapter->nic_ops->cancel_idc_work) 2000 adapter->nic_ops->cancel_idc_work(adapter); 2001 } 2002 2003 static inline irqreturn_t 2004 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) 2005 { 2006 return adapter->nic_ops->clear_legacy_intr(adapter); 2007 } 2008 2009 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, 2010 u32 rate) 2011 { 2012 return adapter->nic_ops->config_led(adapter, state, rate); 2013 } 2014 2015 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, 2016 __be32 ip, int cmd) 2017 { 2018 adapter->nic_ops->config_ipaddr(adapter, ip, cmd); 2019 } 2020 2021 static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter) 2022 { 2023 return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); 2024 } 2025 2026 static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter) 2027 { 2028 test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); 2029 adapter->drv_tx_rings = QLCNIC_SINGLE_RING; 2030 } 2031 2032 /* When operating in a muti tx mode, driver needs to write 0x1 2033 * to src register, instead of 0x0 to disable receiving interrupt. 2034 */ 2035 static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring) 2036 { 2037 struct qlcnic_adapter *adapter = sds_ring->adapter; 2038 2039 if (qlcnic_check_multi_tx(adapter) && 2040 !adapter->ahw->diag_test && 2041 (adapter->flags & QLCNIC_MSIX_ENABLED)) 2042 writel(0x1, sds_ring->crb_intr_mask); 2043 else 2044 writel(0, sds_ring->crb_intr_mask); 2045 } 2046 2047 /* When operating in a muti tx mode, driver needs to write 0x0 2048 * to src register, instead of 0x1 to enable receiving interrupts. 2049 */ 2050 static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring) 2051 { 2052 struct qlcnic_adapter *adapter = sds_ring->adapter; 2053 2054 if (qlcnic_check_multi_tx(adapter) && 2055 !adapter->ahw->diag_test && 2056 (adapter->flags & QLCNIC_MSIX_ENABLED)) 2057 writel(0, sds_ring->crb_intr_mask); 2058 else 2059 writel(0x1, sds_ring->crb_intr_mask); 2060 2061 if (!QLCNIC_IS_MSI_FAMILY(adapter)) 2062 writel(0xfbff, adapter->tgt_mask_reg); 2063 } 2064 2065 static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter) 2066 { 2067 return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2068 } 2069 2070 static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter) 2071 { 2072 clear_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2073 } 2074 2075 static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter) 2076 { 2077 return test_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2078 } 2079 2080 extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops; 2081 extern const struct ethtool_ops qlcnic_ethtool_ops; 2082 extern const struct ethtool_ops qlcnic_ethtool_failed_ops; 2083 2084 #define QLCDB(adapter, lvl, _fmt, _args...) do { \ 2085 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ 2086 printk(KERN_INFO "%s: %s: " _fmt, \ 2087 dev_name(&adapter->pdev->dev), \ 2088 __func__, ##_args); \ 2089 } while (0) 2090 2091 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 2092 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 2093 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430 2094 #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040 2095 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440 2096 2097 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) 2098 { 2099 unsigned short device = adapter->pdev->device; 2100 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; 2101 } 2102 2103 static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter) 2104 { 2105 unsigned short device = adapter->pdev->device; 2106 2107 return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) || 2108 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; 2109 } 2110 2111 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) 2112 { 2113 unsigned short device = adapter->pdev->device; 2114 bool status; 2115 2116 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) || 2117 (device == PCI_DEVICE_ID_QLOGIC_QLE844X) || 2118 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) || 2119 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false; 2120 2121 return status; 2122 } 2123 2124 static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter) 2125 { 2126 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false; 2127 } 2128 2129 static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter) 2130 { 2131 unsigned short device = adapter->pdev->device; 2132 bool status; 2133 2134 status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || 2135 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; 2136 2137 return status; 2138 } 2139 #endif /* __QLCNIC_H_ */ 2140