1 /*
2  * QLogic QLA3xxx NIC HBA Driver
3  * Copyright (c)  2003-2006 QLogic Corporation
4  *
5  * See LICENSE.qla3xxx for copyright and licensing details.
6  */
7 
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 
10 #include <linux/kernel.h>
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/list.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/ip.h>
26 #include <linux/in.h>
27 #include <linux/if_arp.h>
28 #include <linux/if_ether.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/skbuff.h>
33 #include <linux/rtnetlink.h>
34 #include <linux/if_vlan.h>
35 #include <linux/delay.h>
36 #include <linux/mm.h>
37 #include <linux/prefetch.h>
38 
39 #include "qla3xxx.h"
40 
41 #define DRV_NAME	"qla3xxx"
42 #define DRV_STRING	"QLogic ISP3XXX Network Driver"
43 #define DRV_VERSION	"v2.03.00-k5"
44 
45 static const char ql3xxx_driver_name[] = DRV_NAME;
46 static const char ql3xxx_driver_version[] = DRV_VERSION;
47 
48 #define TIMED_OUT_MSG							\
49 "Timed out waiting for management port to get free before issuing command\n"
50 
51 MODULE_AUTHOR("QLogic Corporation");
52 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
53 MODULE_LICENSE("GPL");
54 MODULE_VERSION(DRV_VERSION);
55 
56 static const u32 default_msg
57     = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
58     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
59 
60 static int debug = -1;		/* defaults above */
61 module_param(debug, int, 0);
62 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
63 
64 static int msi;
65 module_param(msi, int, 0);
66 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
67 
68 static const struct pci_device_id ql3xxx_pci_tbl[] = {
69 	{PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
70 	{PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
71 	/* required last entry */
72 	{0,}
73 };
74 
75 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
76 
77 /*
78  *  These are the known PHY's which are used
79  */
80 enum PHY_DEVICE_TYPE {
81    PHY_TYPE_UNKNOWN   = 0,
82    PHY_VITESSE_VSC8211,
83    PHY_AGERE_ET1011C,
84    MAX_PHY_DEV_TYPES
85 };
86 
87 struct PHY_DEVICE_INFO {
88 	const enum PHY_DEVICE_TYPE	phyDevice;
89 	const u32		phyIdOUI;
90 	const u16		phyIdModel;
91 	const char		*name;
92 };
93 
94 static const struct PHY_DEVICE_INFO PHY_DEVICES[] = {
95 	{PHY_TYPE_UNKNOWN,    0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
96 	{PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
97 	{PHY_AGERE_ET1011C,   0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
98 };
99 
100 
101 /*
102  * Caller must take hw_lock.
103  */
104 static int ql_sem_spinlock(struct ql3_adapter *qdev,
105 			    u32 sem_mask, u32 sem_bits)
106 {
107 	struct ql3xxx_port_registers __iomem *port_regs =
108 		qdev->mem_map_registers;
109 	u32 value;
110 	unsigned int seconds = 3;
111 
112 	do {
113 		writel((sem_mask | sem_bits),
114 		       &port_regs->CommonRegs.semaphoreReg);
115 		value = readl(&port_regs->CommonRegs.semaphoreReg);
116 		if ((value & (sem_mask >> 16)) == sem_bits)
117 			return 0;
118 		ssleep(1);
119 	} while (--seconds);
120 	return -1;
121 }
122 
123 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
124 {
125 	struct ql3xxx_port_registers __iomem *port_regs =
126 		qdev->mem_map_registers;
127 	writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
128 	readl(&port_regs->CommonRegs.semaphoreReg);
129 }
130 
131 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
132 {
133 	struct ql3xxx_port_registers __iomem *port_regs =
134 		qdev->mem_map_registers;
135 	u32 value;
136 
137 	writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
138 	value = readl(&port_regs->CommonRegs.semaphoreReg);
139 	return ((value & (sem_mask >> 16)) == sem_bits);
140 }
141 
142 /*
143  * Caller holds hw_lock.
144  */
145 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
146 {
147 	int i = 0;
148 
149 	do {
150 		if (ql_sem_lock(qdev,
151 				QL_DRVR_SEM_MASK,
152 				(QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
153 				 * 2) << 1)) {
154 			netdev_printk(KERN_DEBUG, qdev->ndev,
155 				      "driver lock acquired\n");
156 			return 1;
157 		}
158 		ssleep(1);
159 	} while (++i < 10);
160 
161 	netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n");
162 	return 0;
163 }
164 
165 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
166 {
167 	struct ql3xxx_port_registers __iomem *port_regs =
168 		qdev->mem_map_registers;
169 
170 	writel(((ISP_CONTROL_NP_MASK << 16) | page),
171 			&port_regs->CommonRegs.ispControlStatus);
172 	readl(&port_regs->CommonRegs.ispControlStatus);
173 	qdev->current_page = page;
174 }
175 
176 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
177 {
178 	u32 value;
179 	unsigned long hw_flags;
180 
181 	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
182 	value = readl(reg);
183 	spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
184 
185 	return value;
186 }
187 
188 static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
189 {
190 	return readl(reg);
191 }
192 
193 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
194 {
195 	u32 value;
196 	unsigned long hw_flags;
197 
198 	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
199 
200 	if (qdev->current_page != 0)
201 		ql_set_register_page(qdev, 0);
202 	value = readl(reg);
203 
204 	spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
205 	return value;
206 }
207 
208 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
209 {
210 	if (qdev->current_page != 0)
211 		ql_set_register_page(qdev, 0);
212 	return readl(reg);
213 }
214 
215 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
216 				u32 __iomem *reg, u32 value)
217 {
218 	unsigned long hw_flags;
219 
220 	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
221 	writel(value, reg);
222 	readl(reg);
223 	spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
224 }
225 
226 static void ql_write_common_reg(struct ql3_adapter *qdev,
227 				u32 __iomem *reg, u32 value)
228 {
229 	writel(value, reg);
230 	readl(reg);
231 }
232 
233 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
234 				u32 __iomem *reg, u32 value)
235 {
236 	writel(value, reg);
237 	readl(reg);
238 	udelay(1);
239 }
240 
241 static void ql_write_page0_reg(struct ql3_adapter *qdev,
242 			       u32 __iomem *reg, u32 value)
243 {
244 	if (qdev->current_page != 0)
245 		ql_set_register_page(qdev, 0);
246 	writel(value, reg);
247 	readl(reg);
248 }
249 
250 /*
251  * Caller holds hw_lock. Only called during init.
252  */
253 static void ql_write_page1_reg(struct ql3_adapter *qdev,
254 			       u32 __iomem *reg, u32 value)
255 {
256 	if (qdev->current_page != 1)
257 		ql_set_register_page(qdev, 1);
258 	writel(value, reg);
259 	readl(reg);
260 }
261 
262 /*
263  * Caller holds hw_lock. Only called during init.
264  */
265 static void ql_write_page2_reg(struct ql3_adapter *qdev,
266 			       u32 __iomem *reg, u32 value)
267 {
268 	if (qdev->current_page != 2)
269 		ql_set_register_page(qdev, 2);
270 	writel(value, reg);
271 	readl(reg);
272 }
273 
274 static void ql_disable_interrupts(struct ql3_adapter *qdev)
275 {
276 	struct ql3xxx_port_registers __iomem *port_regs =
277 		qdev->mem_map_registers;
278 
279 	ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
280 			    (ISP_IMR_ENABLE_INT << 16));
281 
282 }
283 
284 static void ql_enable_interrupts(struct ql3_adapter *qdev)
285 {
286 	struct ql3xxx_port_registers __iomem *port_regs =
287 		qdev->mem_map_registers;
288 
289 	ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
290 			    ((0xff << 16) | ISP_IMR_ENABLE_INT));
291 
292 }
293 
294 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
295 					    struct ql_rcv_buf_cb *lrg_buf_cb)
296 {
297 	dma_addr_t map;
298 	int err;
299 	lrg_buf_cb->next = NULL;
300 
301 	if (qdev->lrg_buf_free_tail == NULL) {	/* The list is empty  */
302 		qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
303 	} else {
304 		qdev->lrg_buf_free_tail->next = lrg_buf_cb;
305 		qdev->lrg_buf_free_tail = lrg_buf_cb;
306 	}
307 
308 	if (!lrg_buf_cb->skb) {
309 		lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
310 						   qdev->lrg_buffer_len);
311 		if (unlikely(!lrg_buf_cb->skb)) {
312 			qdev->lrg_buf_skb_check++;
313 		} else {
314 			/*
315 			 * We save some space to copy the ethhdr from first
316 			 * buffer
317 			 */
318 			skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
319 			map = pci_map_single(qdev->pdev,
320 					     lrg_buf_cb->skb->data,
321 					     qdev->lrg_buffer_len -
322 					     QL_HEADER_SPACE,
323 					     PCI_DMA_FROMDEVICE);
324 			err = pci_dma_mapping_error(qdev->pdev, map);
325 			if (err) {
326 				netdev_err(qdev->ndev,
327 					   "PCI mapping failed with error: %d\n",
328 					   err);
329 				dev_kfree_skb(lrg_buf_cb->skb);
330 				lrg_buf_cb->skb = NULL;
331 
332 				qdev->lrg_buf_skb_check++;
333 				return;
334 			}
335 
336 			lrg_buf_cb->buf_phy_addr_low =
337 			    cpu_to_le32(LS_64BITS(map));
338 			lrg_buf_cb->buf_phy_addr_high =
339 			    cpu_to_le32(MS_64BITS(map));
340 			dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
341 			dma_unmap_len_set(lrg_buf_cb, maplen,
342 					  qdev->lrg_buffer_len -
343 					  QL_HEADER_SPACE);
344 		}
345 	}
346 
347 	qdev->lrg_buf_free_count++;
348 }
349 
350 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
351 							   *qdev)
352 {
353 	struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
354 
355 	if (lrg_buf_cb != NULL) {
356 		qdev->lrg_buf_free_head = lrg_buf_cb->next;
357 		if (qdev->lrg_buf_free_head == NULL)
358 			qdev->lrg_buf_free_tail = NULL;
359 		qdev->lrg_buf_free_count--;
360 	}
361 
362 	return lrg_buf_cb;
363 }
364 
365 static u32 addrBits = EEPROM_NO_ADDR_BITS;
366 static u32 dataBits = EEPROM_NO_DATA_BITS;
367 
368 static void fm93c56a_deselect(struct ql3_adapter *qdev);
369 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
370 			    unsigned short *value);
371 
372 /*
373  * Caller holds hw_lock.
374  */
375 static void fm93c56a_select(struct ql3_adapter *qdev)
376 {
377 	struct ql3xxx_port_registers __iomem *port_regs =
378 			qdev->mem_map_registers;
379 	__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
380 
381 	qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
382 	ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
383 	ql_write_nvram_reg(qdev, spir,
384 			   ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
385 }
386 
387 /*
388  * Caller holds hw_lock.
389  */
390 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
391 {
392 	int i;
393 	u32 mask;
394 	u32 dataBit;
395 	u32 previousBit;
396 	struct ql3xxx_port_registers __iomem *port_regs =
397 			qdev->mem_map_registers;
398 	__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
399 
400 	/* Clock in a zero, then do the start bit */
401 	ql_write_nvram_reg(qdev, spir,
402 			   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
403 			    AUBURN_EEPROM_DO_1));
404 	ql_write_nvram_reg(qdev, spir,
405 			   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
406 			    AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE));
407 	ql_write_nvram_reg(qdev, spir,
408 			   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
409 			    AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL));
410 
411 	mask = 1 << (FM93C56A_CMD_BITS - 1);
412 	/* Force the previous data bit to be different */
413 	previousBit = 0xffff;
414 	for (i = 0; i < FM93C56A_CMD_BITS; i++) {
415 		dataBit = (cmd & mask)
416 			? AUBURN_EEPROM_DO_1
417 			: AUBURN_EEPROM_DO_0;
418 		if (previousBit != dataBit) {
419 			/* If the bit changed, change the DO state to match */
420 			ql_write_nvram_reg(qdev, spir,
421 					   (ISP_NVRAM_MASK |
422 					    qdev->eeprom_cmd_data | dataBit));
423 			previousBit = dataBit;
424 		}
425 		ql_write_nvram_reg(qdev, spir,
426 				   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
427 				    dataBit | AUBURN_EEPROM_CLK_RISE));
428 		ql_write_nvram_reg(qdev, spir,
429 				   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
430 				    dataBit | AUBURN_EEPROM_CLK_FALL));
431 		cmd = cmd << 1;
432 	}
433 
434 	mask = 1 << (addrBits - 1);
435 	/* Force the previous data bit to be different */
436 	previousBit = 0xffff;
437 	for (i = 0; i < addrBits; i++) {
438 		dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1
439 			: AUBURN_EEPROM_DO_0;
440 		if (previousBit != dataBit) {
441 			/*
442 			 * If the bit changed, then change the DO state to
443 			 * match
444 			 */
445 			ql_write_nvram_reg(qdev, spir,
446 					   (ISP_NVRAM_MASK |
447 					    qdev->eeprom_cmd_data | dataBit));
448 			previousBit = dataBit;
449 		}
450 		ql_write_nvram_reg(qdev, spir,
451 				   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
452 				    dataBit | AUBURN_EEPROM_CLK_RISE));
453 		ql_write_nvram_reg(qdev, spir,
454 				   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
455 				    dataBit | AUBURN_EEPROM_CLK_FALL));
456 		eepromAddr = eepromAddr << 1;
457 	}
458 }
459 
460 /*
461  * Caller holds hw_lock.
462  */
463 static void fm93c56a_deselect(struct ql3_adapter *qdev)
464 {
465 	struct ql3xxx_port_registers __iomem *port_regs =
466 			qdev->mem_map_registers;
467 	__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
468 
469 	qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
470 	ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
471 }
472 
473 /*
474  * Caller holds hw_lock.
475  */
476 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
477 {
478 	int i;
479 	u32 data = 0;
480 	u32 dataBit;
481 	struct ql3xxx_port_registers __iomem *port_regs =
482 			qdev->mem_map_registers;
483 	__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
484 
485 	/* Read the data bits */
486 	/* The first bit is a dummy.  Clock right over it. */
487 	for (i = 0; i < dataBits; i++) {
488 		ql_write_nvram_reg(qdev, spir,
489 				   ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
490 				   AUBURN_EEPROM_CLK_RISE);
491 		ql_write_nvram_reg(qdev, spir,
492 				   ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
493 				   AUBURN_EEPROM_CLK_FALL);
494 		dataBit = (ql_read_common_reg(qdev, spir) &
495 			   AUBURN_EEPROM_DI_1) ? 1 : 0;
496 		data = (data << 1) | dataBit;
497 	}
498 	*value = (u16)data;
499 }
500 
501 /*
502  * Caller holds hw_lock.
503  */
504 static void eeprom_readword(struct ql3_adapter *qdev,
505 			    u32 eepromAddr, unsigned short *value)
506 {
507 	fm93c56a_select(qdev);
508 	fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
509 	fm93c56a_datain(qdev, value);
510 	fm93c56a_deselect(qdev);
511 }
512 
513 static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
514 {
515 	__le16 *p = (__le16 *)ndev->dev_addr;
516 	p[0] = cpu_to_le16(addr[0]);
517 	p[1] = cpu_to_le16(addr[1]);
518 	p[2] = cpu_to_le16(addr[2]);
519 }
520 
521 static int ql_get_nvram_params(struct ql3_adapter *qdev)
522 {
523 	u16 *pEEPROMData;
524 	u16 checksum = 0;
525 	u32 index;
526 	unsigned long hw_flags;
527 
528 	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
529 
530 	pEEPROMData = (u16 *)&qdev->nvram_data;
531 	qdev->eeprom_cmd_data = 0;
532 	if (ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
533 			(QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
534 			 2) << 10)) {
535 		pr_err("%s: Failed ql_sem_spinlock()\n", __func__);
536 		spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
537 		return -1;
538 	}
539 
540 	for (index = 0; index < EEPROM_SIZE; index++) {
541 		eeprom_readword(qdev, index, pEEPROMData);
542 		checksum += *pEEPROMData;
543 		pEEPROMData++;
544 	}
545 	ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
546 
547 	if (checksum != 0) {
548 		netdev_err(qdev->ndev, "checksum should be zero, is %x!!\n",
549 			   checksum);
550 		spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
551 		return -1;
552 	}
553 
554 	spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
555 	return checksum;
556 }
557 
558 static const u32 PHYAddr[2] = {
559 	PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
560 };
561 
562 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
563 {
564 	struct ql3xxx_port_registers __iomem *port_regs =
565 			qdev->mem_map_registers;
566 	u32 temp;
567 	int count = 1000;
568 
569 	while (count) {
570 		temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
571 		if (!(temp & MAC_MII_STATUS_BSY))
572 			return 0;
573 		udelay(10);
574 		count--;
575 	}
576 	return -1;
577 }
578 
579 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
580 {
581 	struct ql3xxx_port_registers __iomem *port_regs =
582 			qdev->mem_map_registers;
583 	u32 scanControl;
584 
585 	if (qdev->numPorts > 1) {
586 		/* Auto scan will cycle through multiple ports */
587 		scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
588 	} else {
589 		scanControl = MAC_MII_CONTROL_SC;
590 	}
591 
592 	/*
593 	 * Scan register 1 of PHY/PETBI,
594 	 * Set up to scan both devices
595 	 * The autoscan starts from the first register, completes
596 	 * the last one before rolling over to the first
597 	 */
598 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
599 			   PHYAddr[0] | MII_SCAN_REGISTER);
600 
601 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
602 			   (scanControl) |
603 			   ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
604 }
605 
606 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
607 {
608 	u8 ret;
609 	struct ql3xxx_port_registers __iomem *port_regs =
610 					qdev->mem_map_registers;
611 
612 	/* See if scan mode is enabled before we turn it off */
613 	if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
614 	    (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
615 		/* Scan is enabled */
616 		ret = 1;
617 	} else {
618 		/* Scan is disabled */
619 		ret = 0;
620 	}
621 
622 	/*
623 	 * When disabling scan mode you must first change the MII register
624 	 * address
625 	 */
626 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
627 			   PHYAddr[0] | MII_SCAN_REGISTER);
628 
629 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
630 			   ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
631 			     MAC_MII_CONTROL_RC) << 16));
632 
633 	return ret;
634 }
635 
636 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
637 			       u16 regAddr, u16 value, u32 phyAddr)
638 {
639 	struct ql3xxx_port_registers __iomem *port_regs =
640 			qdev->mem_map_registers;
641 	u8 scanWasEnabled;
642 
643 	scanWasEnabled = ql_mii_disable_scan_mode(qdev);
644 
645 	if (ql_wait_for_mii_ready(qdev)) {
646 		netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
647 		return -1;
648 	}
649 
650 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
651 			   phyAddr | regAddr);
652 
653 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
654 
655 	/* Wait for write to complete 9/10/04 SJP */
656 	if (ql_wait_for_mii_ready(qdev)) {
657 		netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
658 		return -1;
659 	}
660 
661 	if (scanWasEnabled)
662 		ql_mii_enable_scan_mode(qdev);
663 
664 	return 0;
665 }
666 
667 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
668 			      u16 *value, u32 phyAddr)
669 {
670 	struct ql3xxx_port_registers __iomem *port_regs =
671 			qdev->mem_map_registers;
672 	u8 scanWasEnabled;
673 	u32 temp;
674 
675 	scanWasEnabled = ql_mii_disable_scan_mode(qdev);
676 
677 	if (ql_wait_for_mii_ready(qdev)) {
678 		netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
679 		return -1;
680 	}
681 
682 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
683 			   phyAddr | regAddr);
684 
685 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
686 			   (MAC_MII_CONTROL_RC << 16));
687 
688 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
689 			   (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
690 
691 	/* Wait for the read to complete */
692 	if (ql_wait_for_mii_ready(qdev)) {
693 		netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
694 		return -1;
695 	}
696 
697 	temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
698 	*value = (u16) temp;
699 
700 	if (scanWasEnabled)
701 		ql_mii_enable_scan_mode(qdev);
702 
703 	return 0;
704 }
705 
706 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
707 {
708 	struct ql3xxx_port_registers __iomem *port_regs =
709 			qdev->mem_map_registers;
710 
711 	ql_mii_disable_scan_mode(qdev);
712 
713 	if (ql_wait_for_mii_ready(qdev)) {
714 		netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
715 		return -1;
716 	}
717 
718 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
719 			   qdev->PHYAddr | regAddr);
720 
721 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
722 
723 	/* Wait for write to complete. */
724 	if (ql_wait_for_mii_ready(qdev)) {
725 		netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
726 		return -1;
727 	}
728 
729 	ql_mii_enable_scan_mode(qdev);
730 
731 	return 0;
732 }
733 
734 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
735 {
736 	u32 temp;
737 	struct ql3xxx_port_registers __iomem *port_regs =
738 			qdev->mem_map_registers;
739 
740 	ql_mii_disable_scan_mode(qdev);
741 
742 	if (ql_wait_for_mii_ready(qdev)) {
743 		netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
744 		return -1;
745 	}
746 
747 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
748 			   qdev->PHYAddr | regAddr);
749 
750 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
751 			   (MAC_MII_CONTROL_RC << 16));
752 
753 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
754 			   (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
755 
756 	/* Wait for the read to complete */
757 	if (ql_wait_for_mii_ready(qdev)) {
758 		netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
759 		return -1;
760 	}
761 
762 	temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
763 	*value = (u16) temp;
764 
765 	ql_mii_enable_scan_mode(qdev);
766 
767 	return 0;
768 }
769 
770 static void ql_petbi_reset(struct ql3_adapter *qdev)
771 {
772 	ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
773 }
774 
775 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
776 {
777 	u16 reg;
778 
779 	/* Enable Auto-negotiation sense */
780 	ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
781 	reg |= PETBI_TBI_AUTO_SENSE;
782 	ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
783 
784 	ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
785 			 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
786 
787 	ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
788 			 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
789 			 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
790 
791 }
792 
793 static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
794 {
795 	ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
796 			    PHYAddr[qdev->mac_index]);
797 }
798 
799 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
800 {
801 	u16 reg;
802 
803 	/* Enable Auto-negotiation sense */
804 	ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg,
805 			   PHYAddr[qdev->mac_index]);
806 	reg |= PETBI_TBI_AUTO_SENSE;
807 	ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
808 			    PHYAddr[qdev->mac_index]);
809 
810 	ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
811 			    PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
812 			    PHYAddr[qdev->mac_index]);
813 
814 	ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
815 			    PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
816 			    PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
817 			    PHYAddr[qdev->mac_index]);
818 }
819 
820 static void ql_petbi_init(struct ql3_adapter *qdev)
821 {
822 	ql_petbi_reset(qdev);
823 	ql_petbi_start_neg(qdev);
824 }
825 
826 static void ql_petbi_init_ex(struct ql3_adapter *qdev)
827 {
828 	ql_petbi_reset_ex(qdev);
829 	ql_petbi_start_neg_ex(qdev);
830 }
831 
832 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
833 {
834 	u16 reg;
835 
836 	if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
837 		return 0;
838 
839 	return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
840 }
841 
842 static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
843 {
844 	netdev_info(qdev->ndev, "enabling Agere specific PHY\n");
845 	/* power down device bit 11 = 1 */
846 	ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
847 	/* enable diagnostic mode bit 2 = 1 */
848 	ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
849 	/* 1000MB amplitude adjust (see Agere errata) */
850 	ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
851 	/* 1000MB amplitude adjust (see Agere errata) */
852 	ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
853 	/* 100MB amplitude adjust (see Agere errata) */
854 	ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
855 	/* 100MB amplitude adjust (see Agere errata) */
856 	ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
857 	/* 10MB amplitude adjust (see Agere errata) */
858 	ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
859 	/* 10MB amplitude adjust (see Agere errata) */
860 	ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
861 	/* point to hidden reg 0x2806 */
862 	ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
863 	/* Write new PHYAD w/bit 5 set */
864 	ql_mii_write_reg_ex(qdev, 0x11,
865 			    0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
866 	/*
867 	 * Disable diagnostic mode bit 2 = 0
868 	 * Power up device bit 11 = 0
869 	 * Link up (on) and activity (blink)
870 	 */
871 	ql_mii_write_reg(qdev, 0x12, 0x840a);
872 	ql_mii_write_reg(qdev, 0x00, 0x1140);
873 	ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
874 }
875 
876 static enum PHY_DEVICE_TYPE getPhyType(struct ql3_adapter *qdev,
877 				       u16 phyIdReg0, u16 phyIdReg1)
878 {
879 	enum PHY_DEVICE_TYPE result = PHY_TYPE_UNKNOWN;
880 	u32   oui;
881 	u16   model;
882 	int i;
883 
884 	if (phyIdReg0 == 0xffff)
885 		return result;
886 
887 	if (phyIdReg1 == 0xffff)
888 		return result;
889 
890 	/* oui is split between two registers */
891 	oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
892 
893 	model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
894 
895 	/* Scan table for this PHY */
896 	for (i = 0; i < MAX_PHY_DEV_TYPES; i++) {
897 		if ((oui == PHY_DEVICES[i].phyIdOUI) &&
898 		    (model == PHY_DEVICES[i].phyIdModel)) {
899 			netdev_info(qdev->ndev, "Phy: %s\n",
900 				    PHY_DEVICES[i].name);
901 			result = PHY_DEVICES[i].phyDevice;
902 			break;
903 		}
904 	}
905 
906 	return result;
907 }
908 
909 static int ql_phy_get_speed(struct ql3_adapter *qdev)
910 {
911 	u16 reg;
912 
913 	switch (qdev->phyType) {
914 	case PHY_AGERE_ET1011C: {
915 		if (ql_mii_read_reg(qdev, 0x1A, &reg) < 0)
916 			return 0;
917 
918 		reg = (reg >> 8) & 3;
919 		break;
920 	}
921 	default:
922 		if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
923 			return 0;
924 
925 		reg = (((reg & 0x18) >> 3) & 3);
926 	}
927 
928 	switch (reg) {
929 	case 2:
930 		return SPEED_1000;
931 	case 1:
932 		return SPEED_100;
933 	case 0:
934 		return SPEED_10;
935 	default:
936 		return -1;
937 	}
938 }
939 
940 static int ql_is_full_dup(struct ql3_adapter *qdev)
941 {
942 	u16 reg;
943 
944 	switch (qdev->phyType) {
945 	case PHY_AGERE_ET1011C: {
946 		if (ql_mii_read_reg(qdev, 0x1A, &reg))
947 			return 0;
948 
949 		return ((reg & 0x0080) && (reg & 0x1000)) != 0;
950 	}
951 	case PHY_VITESSE_VSC8211:
952 	default: {
953 		if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
954 			return 0;
955 		return (reg & PHY_AUX_DUPLEX_STAT) != 0;
956 	}
957 	}
958 }
959 
960 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
961 {
962 	u16 reg;
963 
964 	if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
965 		return 0;
966 
967 	return (reg & PHY_NEG_PAUSE) != 0;
968 }
969 
970 static int PHY_Setup(struct ql3_adapter *qdev)
971 {
972 	u16   reg1;
973 	u16   reg2;
974 	bool  agereAddrChangeNeeded = false;
975 	u32 miiAddr = 0;
976 	int err;
977 
978 	/*  Determine the PHY we are using by reading the ID's */
979 	err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
980 	if (err != 0) {
981 		netdev_err(qdev->ndev, "Could not read from reg PHY_ID_0_REG\n");
982 		return err;
983 	}
984 
985 	err = ql_mii_read_reg(qdev, PHY_ID_1_REG, &reg2);
986 	if (err != 0) {
987 		netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG\n");
988 		return err;
989 	}
990 
991 	/*  Check if we have a Agere PHY */
992 	if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
993 
994 		/* Determine which MII address we should be using
995 		   determined by the index of the card */
996 		if (qdev->mac_index == 0)
997 			miiAddr = MII_AGERE_ADDR_1;
998 		else
999 			miiAddr = MII_AGERE_ADDR_2;
1000 
1001 		err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
1002 		if (err != 0) {
1003 			netdev_err(qdev->ndev,
1004 				   "Could not read from reg PHY_ID_0_REG after Agere detected\n");
1005 			return err;
1006 		}
1007 
1008 		err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, &reg2, miiAddr);
1009 		if (err != 0) {
1010 			netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG after Agere detected\n");
1011 			return err;
1012 		}
1013 
1014 		/*  We need to remember to initialize the Agere PHY */
1015 		agereAddrChangeNeeded = true;
1016 	}
1017 
1018 	/*  Determine the particular PHY we have on board to apply
1019 	    PHY specific initializations */
1020 	qdev->phyType = getPhyType(qdev, reg1, reg2);
1021 
1022 	if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1023 		/* need this here so address gets changed */
1024 		phyAgereSpecificInit(qdev, miiAddr);
1025 	} else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1026 		netdev_err(qdev->ndev, "PHY is unknown\n");
1027 		return -EIO;
1028 	}
1029 
1030 	return 0;
1031 }
1032 
1033 /*
1034  * Caller holds hw_lock.
1035  */
1036 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1037 {
1038 	struct ql3xxx_port_registers __iomem *port_regs =
1039 			qdev->mem_map_registers;
1040 	u32 value;
1041 
1042 	if (enable)
1043 		value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1044 	else
1045 		value = (MAC_CONFIG_REG_PE << 16);
1046 
1047 	if (qdev->mac_index)
1048 		ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1049 	else
1050 		ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1051 }
1052 
1053 /*
1054  * Caller holds hw_lock.
1055  */
1056 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1057 {
1058 	struct ql3xxx_port_registers __iomem *port_regs =
1059 			qdev->mem_map_registers;
1060 	u32 value;
1061 
1062 	if (enable)
1063 		value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1064 	else
1065 		value = (MAC_CONFIG_REG_SR << 16);
1066 
1067 	if (qdev->mac_index)
1068 		ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1069 	else
1070 		ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1071 }
1072 
1073 /*
1074  * Caller holds hw_lock.
1075  */
1076 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1077 {
1078 	struct ql3xxx_port_registers __iomem *port_regs =
1079 			qdev->mem_map_registers;
1080 	u32 value;
1081 
1082 	if (enable)
1083 		value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1084 	else
1085 		value = (MAC_CONFIG_REG_GM << 16);
1086 
1087 	if (qdev->mac_index)
1088 		ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1089 	else
1090 		ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1091 }
1092 
1093 /*
1094  * Caller holds hw_lock.
1095  */
1096 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1097 {
1098 	struct ql3xxx_port_registers __iomem *port_regs =
1099 			qdev->mem_map_registers;
1100 	u32 value;
1101 
1102 	if (enable)
1103 		value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1104 	else
1105 		value = (MAC_CONFIG_REG_FD << 16);
1106 
1107 	if (qdev->mac_index)
1108 		ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1109 	else
1110 		ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1111 }
1112 
1113 /*
1114  * Caller holds hw_lock.
1115  */
1116 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1117 {
1118 	struct ql3xxx_port_registers __iomem *port_regs =
1119 			qdev->mem_map_registers;
1120 	u32 value;
1121 
1122 	if (enable)
1123 		value =
1124 		    ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1125 		     ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1126 	else
1127 		value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1128 
1129 	if (qdev->mac_index)
1130 		ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1131 	else
1132 		ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1133 }
1134 
1135 /*
1136  * Caller holds hw_lock.
1137  */
1138 static int ql_is_fiber(struct ql3_adapter *qdev)
1139 {
1140 	struct ql3xxx_port_registers __iomem *port_regs =
1141 			qdev->mem_map_registers;
1142 	u32 bitToCheck = 0;
1143 	u32 temp;
1144 
1145 	switch (qdev->mac_index) {
1146 	case 0:
1147 		bitToCheck = PORT_STATUS_SM0;
1148 		break;
1149 	case 1:
1150 		bitToCheck = PORT_STATUS_SM1;
1151 		break;
1152 	}
1153 
1154 	temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1155 	return (temp & bitToCheck) != 0;
1156 }
1157 
1158 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1159 {
1160 	u16 reg;
1161 	ql_mii_read_reg(qdev, 0x00, &reg);
1162 	return (reg & 0x1000) != 0;
1163 }
1164 
1165 /*
1166  * Caller holds hw_lock.
1167  */
1168 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1169 {
1170 	struct ql3xxx_port_registers __iomem *port_regs =
1171 			qdev->mem_map_registers;
1172 	u32 bitToCheck = 0;
1173 	u32 temp;
1174 
1175 	switch (qdev->mac_index) {
1176 	case 0:
1177 		bitToCheck = PORT_STATUS_AC0;
1178 		break;
1179 	case 1:
1180 		bitToCheck = PORT_STATUS_AC1;
1181 		break;
1182 	}
1183 
1184 	temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1185 	if (temp & bitToCheck) {
1186 		netif_info(qdev, link, qdev->ndev, "Auto-Negotiate complete\n");
1187 		return 1;
1188 	}
1189 	netif_info(qdev, link, qdev->ndev, "Auto-Negotiate incomplete\n");
1190 	return 0;
1191 }
1192 
1193 /*
1194  *  ql_is_neg_pause() returns 1 if pause was negotiated to be on
1195  */
1196 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1197 {
1198 	if (ql_is_fiber(qdev))
1199 		return ql_is_petbi_neg_pause(qdev);
1200 	else
1201 		return ql_is_phy_neg_pause(qdev);
1202 }
1203 
1204 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1205 {
1206 	struct ql3xxx_port_registers __iomem *port_regs =
1207 			qdev->mem_map_registers;
1208 	u32 bitToCheck = 0;
1209 	u32 temp;
1210 
1211 	switch (qdev->mac_index) {
1212 	case 0:
1213 		bitToCheck = PORT_STATUS_AE0;
1214 		break;
1215 	case 1:
1216 		bitToCheck = PORT_STATUS_AE1;
1217 		break;
1218 	}
1219 	temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1220 	return (temp & bitToCheck) != 0;
1221 }
1222 
1223 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1224 {
1225 	if (ql_is_fiber(qdev))
1226 		return SPEED_1000;
1227 	else
1228 		return ql_phy_get_speed(qdev);
1229 }
1230 
1231 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1232 {
1233 	if (ql_is_fiber(qdev))
1234 		return 1;
1235 	else
1236 		return ql_is_full_dup(qdev);
1237 }
1238 
1239 /*
1240  * Caller holds hw_lock.
1241  */
1242 static int ql_link_down_detect(struct ql3_adapter *qdev)
1243 {
1244 	struct ql3xxx_port_registers __iomem *port_regs =
1245 			qdev->mem_map_registers;
1246 	u32 bitToCheck = 0;
1247 	u32 temp;
1248 
1249 	switch (qdev->mac_index) {
1250 	case 0:
1251 		bitToCheck = ISP_CONTROL_LINK_DN_0;
1252 		break;
1253 	case 1:
1254 		bitToCheck = ISP_CONTROL_LINK_DN_1;
1255 		break;
1256 	}
1257 
1258 	temp =
1259 	    ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1260 	return (temp & bitToCheck) != 0;
1261 }
1262 
1263 /*
1264  * Caller holds hw_lock.
1265  */
1266 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1267 {
1268 	struct ql3xxx_port_registers __iomem *port_regs =
1269 			qdev->mem_map_registers;
1270 
1271 	switch (qdev->mac_index) {
1272 	case 0:
1273 		ql_write_common_reg(qdev,
1274 				    &port_regs->CommonRegs.ispControlStatus,
1275 				    (ISP_CONTROL_LINK_DN_0) |
1276 				    (ISP_CONTROL_LINK_DN_0 << 16));
1277 		break;
1278 
1279 	case 1:
1280 		ql_write_common_reg(qdev,
1281 				    &port_regs->CommonRegs.ispControlStatus,
1282 				    (ISP_CONTROL_LINK_DN_1) |
1283 				    (ISP_CONTROL_LINK_DN_1 << 16));
1284 		break;
1285 
1286 	default:
1287 		return 1;
1288 	}
1289 
1290 	return 0;
1291 }
1292 
1293 /*
1294  * Caller holds hw_lock.
1295  */
1296 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1297 {
1298 	struct ql3xxx_port_registers __iomem *port_regs =
1299 			qdev->mem_map_registers;
1300 	u32 bitToCheck = 0;
1301 	u32 temp;
1302 
1303 	switch (qdev->mac_index) {
1304 	case 0:
1305 		bitToCheck = PORT_STATUS_F1_ENABLED;
1306 		break;
1307 	case 1:
1308 		bitToCheck = PORT_STATUS_F3_ENABLED;
1309 		break;
1310 	default:
1311 		break;
1312 	}
1313 
1314 	temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1315 	if (temp & bitToCheck) {
1316 		netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1317 			     "not link master\n");
1318 		return 0;
1319 	}
1320 
1321 	netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, "link master\n");
1322 	return 1;
1323 }
1324 
1325 static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1326 {
1327 	ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1328 			    PHYAddr[qdev->mac_index]);
1329 }
1330 
1331 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1332 {
1333 	u16 reg;
1334 	u16 portConfiguration;
1335 
1336 	if (qdev->phyType == PHY_AGERE_ET1011C)
1337 		ql_mii_write_reg(qdev, 0x13, 0x0000);
1338 					/* turn off external loopback */
1339 
1340 	if (qdev->mac_index == 0)
1341 		portConfiguration =
1342 			qdev->nvram_data.macCfg_port0.portConfiguration;
1343 	else
1344 		portConfiguration =
1345 			qdev->nvram_data.macCfg_port1.portConfiguration;
1346 
1347 	/*  Some HBA's in the field are set to 0 and they need to
1348 	    be reinterpreted with a default value */
1349 	if (portConfiguration == 0)
1350 		portConfiguration = PORT_CONFIG_DEFAULT;
1351 
1352 	/* Set the 1000 advertisements */
1353 	ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, &reg,
1354 			   PHYAddr[qdev->mac_index]);
1355 	reg &= ~PHY_GIG_ALL_PARAMS;
1356 
1357 	if (portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1358 		if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1359 			reg |= PHY_GIG_ADV_1000F;
1360 		else
1361 			reg |= PHY_GIG_ADV_1000H;
1362 	}
1363 
1364 	ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1365 			    PHYAddr[qdev->mac_index]);
1366 
1367 	/* Set the 10/100 & pause negotiation advertisements */
1368 	ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, &reg,
1369 			   PHYAddr[qdev->mac_index]);
1370 	reg &= ~PHY_NEG_ALL_PARAMS;
1371 
1372 	if (portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1373 		reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1374 
1375 	if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1376 		if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1377 			reg |= PHY_NEG_ADV_100F;
1378 
1379 		if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1380 			reg |= PHY_NEG_ADV_10F;
1381 	}
1382 
1383 	if (portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1384 		if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1385 			reg |= PHY_NEG_ADV_100H;
1386 
1387 		if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1388 			reg |= PHY_NEG_ADV_10H;
1389 	}
1390 
1391 	if (portConfiguration & PORT_CONFIG_1000MB_SPEED)
1392 		reg |= 1;
1393 
1394 	ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1395 			    PHYAddr[qdev->mac_index]);
1396 
1397 	ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]);
1398 
1399 	ql_mii_write_reg_ex(qdev, CONTROL_REG,
1400 			    reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1401 			    PHYAddr[qdev->mac_index]);
1402 }
1403 
1404 static void ql_phy_init_ex(struct ql3_adapter *qdev)
1405 {
1406 	ql_phy_reset_ex(qdev);
1407 	PHY_Setup(qdev);
1408 	ql_phy_start_neg_ex(qdev);
1409 }
1410 
1411 /*
1412  * Caller holds hw_lock.
1413  */
1414 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1415 {
1416 	struct ql3xxx_port_registers __iomem *port_regs =
1417 			qdev->mem_map_registers;
1418 	u32 bitToCheck = 0;
1419 	u32 temp, linkState;
1420 
1421 	switch (qdev->mac_index) {
1422 	case 0:
1423 		bitToCheck = PORT_STATUS_UP0;
1424 		break;
1425 	case 1:
1426 		bitToCheck = PORT_STATUS_UP1;
1427 		break;
1428 	}
1429 
1430 	temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1431 	if (temp & bitToCheck)
1432 		linkState = LS_UP;
1433 	else
1434 		linkState = LS_DOWN;
1435 
1436 	return linkState;
1437 }
1438 
1439 static int ql_port_start(struct ql3_adapter *qdev)
1440 {
1441 	if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1442 		(QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1443 			 2) << 7)) {
1444 		netdev_err(qdev->ndev, "Could not get hw lock for GIO\n");
1445 		return -1;
1446 	}
1447 
1448 	if (ql_is_fiber(qdev)) {
1449 		ql_petbi_init(qdev);
1450 	} else {
1451 		/* Copper port */
1452 		ql_phy_init_ex(qdev);
1453 	}
1454 
1455 	ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1456 	return 0;
1457 }
1458 
1459 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1460 {
1461 
1462 	if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1463 		(QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1464 			 2) << 7))
1465 		return -1;
1466 
1467 	if (!ql_auto_neg_error(qdev)) {
1468 		if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1469 			/* configure the MAC */
1470 			netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1471 				     "Configuring link\n");
1472 			ql_mac_cfg_soft_reset(qdev, 1);
1473 			ql_mac_cfg_gig(qdev,
1474 				       (ql_get_link_speed
1475 					(qdev) ==
1476 					SPEED_1000));
1477 			ql_mac_cfg_full_dup(qdev,
1478 					    ql_is_link_full_dup
1479 					    (qdev));
1480 			ql_mac_cfg_pause(qdev,
1481 					 ql_is_neg_pause
1482 					 (qdev));
1483 			ql_mac_cfg_soft_reset(qdev, 0);
1484 
1485 			/* enable the MAC */
1486 			netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1487 				     "Enabling mac\n");
1488 			ql_mac_enable(qdev, 1);
1489 		}
1490 
1491 		qdev->port_link_state = LS_UP;
1492 		netif_start_queue(qdev->ndev);
1493 		netif_carrier_on(qdev->ndev);
1494 		netif_info(qdev, link, qdev->ndev,
1495 			   "Link is up at %d Mbps, %s duplex\n",
1496 			   ql_get_link_speed(qdev),
1497 			   ql_is_link_full_dup(qdev) ? "full" : "half");
1498 
1499 	} else {	/* Remote error detected */
1500 
1501 		if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1502 			netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1503 				     "Remote error detected. Calling ql_port_start()\n");
1504 			/*
1505 			 * ql_port_start() is shared code and needs
1506 			 * to lock the PHY on it's own.
1507 			 */
1508 			ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1509 			if (ql_port_start(qdev))	/* Restart port */
1510 				return -1;
1511 			return 0;
1512 		}
1513 	}
1514 	ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1515 	return 0;
1516 }
1517 
1518 static void ql_link_state_machine_work(struct work_struct *work)
1519 {
1520 	struct ql3_adapter *qdev =
1521 		container_of(work, struct ql3_adapter, link_state_work.work);
1522 
1523 	u32 curr_link_state;
1524 	unsigned long hw_flags;
1525 
1526 	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1527 
1528 	curr_link_state = ql_get_link_state(qdev);
1529 
1530 	if (test_bit(QL_RESET_ACTIVE, &qdev->flags)) {
1531 		netif_info(qdev, link, qdev->ndev,
1532 			   "Reset in progress, skip processing link state\n");
1533 
1534 		spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1535 
1536 		/* Restart timer on 2 second interval. */
1537 		mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1538 
1539 		return;
1540 	}
1541 
1542 	switch (qdev->port_link_state) {
1543 	default:
1544 		if (test_bit(QL_LINK_MASTER, &qdev->flags))
1545 			ql_port_start(qdev);
1546 		qdev->port_link_state = LS_DOWN;
1547 		/* Fall Through */
1548 
1549 	case LS_DOWN:
1550 		if (curr_link_state == LS_UP) {
1551 			netif_info(qdev, link, qdev->ndev, "Link is up\n");
1552 			if (ql_is_auto_neg_complete(qdev))
1553 				ql_finish_auto_neg(qdev);
1554 
1555 			if (qdev->port_link_state == LS_UP)
1556 				ql_link_down_detect_clear(qdev);
1557 
1558 			qdev->port_link_state = LS_UP;
1559 		}
1560 		break;
1561 
1562 	case LS_UP:
1563 		/*
1564 		 * See if the link is currently down or went down and came
1565 		 * back up
1566 		 */
1567 		if (curr_link_state == LS_DOWN) {
1568 			netif_info(qdev, link, qdev->ndev, "Link is down\n");
1569 			qdev->port_link_state = LS_DOWN;
1570 		}
1571 		if (ql_link_down_detect(qdev))
1572 			qdev->port_link_state = LS_DOWN;
1573 		break;
1574 	}
1575 	spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1576 
1577 	/* Restart timer on 2 second interval. */
1578 	mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1579 }
1580 
1581 /*
1582  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1583  */
1584 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1585 {
1586 	if (ql_this_adapter_controls_port(qdev))
1587 		set_bit(QL_LINK_MASTER, &qdev->flags);
1588 	else
1589 		clear_bit(QL_LINK_MASTER, &qdev->flags);
1590 }
1591 
1592 /*
1593  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1594  */
1595 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1596 {
1597 	ql_mii_enable_scan_mode(qdev);
1598 
1599 	if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1600 		if (ql_this_adapter_controls_port(qdev))
1601 			ql_petbi_init_ex(qdev);
1602 	} else {
1603 		if (ql_this_adapter_controls_port(qdev))
1604 			ql_phy_init_ex(qdev);
1605 	}
1606 }
1607 
1608 /*
1609  * MII_Setup needs to be called before taking the PHY out of reset
1610  * so that the management interface clock speed can be set properly.
1611  * It would be better if we had a way to disable MDC until after the
1612  * PHY is out of reset, but we don't have that capability.
1613  */
1614 static int ql_mii_setup(struct ql3_adapter *qdev)
1615 {
1616 	u32 reg;
1617 	struct ql3xxx_port_registers __iomem *port_regs =
1618 			qdev->mem_map_registers;
1619 
1620 	if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1621 			(QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1622 			 2) << 7))
1623 		return -1;
1624 
1625 	if (qdev->device_id == QL3032_DEVICE_ID)
1626 		ql_write_page0_reg(qdev,
1627 			&port_regs->macMIIMgmtControlReg, 0x0f00000);
1628 
1629 	/* Divide 125MHz clock by 28 to meet PHY timing requirements */
1630 	reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1631 
1632 	ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1633 			   reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1634 
1635 	ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1636 	return 0;
1637 }
1638 
1639 #define SUPPORTED_OPTICAL_MODES	(SUPPORTED_1000baseT_Full |	\
1640 				 SUPPORTED_FIBRE |		\
1641 				 SUPPORTED_Autoneg)
1642 #define SUPPORTED_TP_MODES	(SUPPORTED_10baseT_Half |	\
1643 				 SUPPORTED_10baseT_Full |	\
1644 				 SUPPORTED_100baseT_Half |	\
1645 				 SUPPORTED_100baseT_Full |	\
1646 				 SUPPORTED_1000baseT_Half |	\
1647 				 SUPPORTED_1000baseT_Full |	\
1648 				 SUPPORTED_Autoneg |		\
1649 				 SUPPORTED_TP)			\
1650 
1651 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1652 {
1653 	if (test_bit(QL_LINK_OPTICAL, &qdev->flags))
1654 		return SUPPORTED_OPTICAL_MODES;
1655 
1656 	return SUPPORTED_TP_MODES;
1657 }
1658 
1659 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1660 {
1661 	int status;
1662 	unsigned long hw_flags;
1663 	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1664 	if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1665 			    (QL_RESOURCE_BITS_BASE_CODE |
1666 			     (qdev->mac_index) * 2) << 7)) {
1667 		spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1668 		return 0;
1669 	}
1670 	status = ql_is_auto_cfg(qdev);
1671 	ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1672 	spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1673 	return status;
1674 }
1675 
1676 static u32 ql_get_speed(struct ql3_adapter *qdev)
1677 {
1678 	u32 status;
1679 	unsigned long hw_flags;
1680 	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1681 	if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1682 			    (QL_RESOURCE_BITS_BASE_CODE |
1683 			     (qdev->mac_index) * 2) << 7)) {
1684 		spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1685 		return 0;
1686 	}
1687 	status = ql_get_link_speed(qdev);
1688 	ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1689 	spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1690 	return status;
1691 }
1692 
1693 static int ql_get_full_dup(struct ql3_adapter *qdev)
1694 {
1695 	int status;
1696 	unsigned long hw_flags;
1697 	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1698 	if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1699 			    (QL_RESOURCE_BITS_BASE_CODE |
1700 			     (qdev->mac_index) * 2) << 7)) {
1701 		spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1702 		return 0;
1703 	}
1704 	status = ql_is_link_full_dup(qdev);
1705 	ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1706 	spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1707 	return status;
1708 }
1709 
1710 static int ql_get_link_ksettings(struct net_device *ndev,
1711 				 struct ethtool_link_ksettings *cmd)
1712 {
1713 	struct ql3_adapter *qdev = netdev_priv(ndev);
1714 	u32 supported, advertising;
1715 
1716 	supported = ql_supported_modes(qdev);
1717 
1718 	if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1719 		cmd->base.port = PORT_FIBRE;
1720 	} else {
1721 		cmd->base.port = PORT_TP;
1722 		cmd->base.phy_address = qdev->PHYAddr;
1723 	}
1724 	advertising = ql_supported_modes(qdev);
1725 	cmd->base.autoneg = ql_get_auto_cfg_status(qdev);
1726 	cmd->base.speed = ql_get_speed(qdev);
1727 	cmd->base.duplex = ql_get_full_dup(qdev);
1728 
1729 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1730 						supported);
1731 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1732 						advertising);
1733 
1734 	return 0;
1735 }
1736 
1737 static void ql_get_drvinfo(struct net_device *ndev,
1738 			   struct ethtool_drvinfo *drvinfo)
1739 {
1740 	struct ql3_adapter *qdev = netdev_priv(ndev);
1741 	strlcpy(drvinfo->driver, ql3xxx_driver_name, sizeof(drvinfo->driver));
1742 	strlcpy(drvinfo->version, ql3xxx_driver_version,
1743 		sizeof(drvinfo->version));
1744 	strlcpy(drvinfo->bus_info, pci_name(qdev->pdev),
1745 		sizeof(drvinfo->bus_info));
1746 }
1747 
1748 static u32 ql_get_msglevel(struct net_device *ndev)
1749 {
1750 	struct ql3_adapter *qdev = netdev_priv(ndev);
1751 	return qdev->msg_enable;
1752 }
1753 
1754 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1755 {
1756 	struct ql3_adapter *qdev = netdev_priv(ndev);
1757 	qdev->msg_enable = value;
1758 }
1759 
1760 static void ql_get_pauseparam(struct net_device *ndev,
1761 			      struct ethtool_pauseparam *pause)
1762 {
1763 	struct ql3_adapter *qdev = netdev_priv(ndev);
1764 	struct ql3xxx_port_registers __iomem *port_regs =
1765 		qdev->mem_map_registers;
1766 
1767 	u32 reg;
1768 	if (qdev->mac_index == 0)
1769 		reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1770 	else
1771 		reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1772 
1773 	pause->autoneg  = ql_get_auto_cfg_status(qdev);
1774 	pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1775 	pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1776 }
1777 
1778 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1779 	.get_drvinfo = ql_get_drvinfo,
1780 	.get_link = ethtool_op_get_link,
1781 	.get_msglevel = ql_get_msglevel,
1782 	.set_msglevel = ql_set_msglevel,
1783 	.get_pauseparam = ql_get_pauseparam,
1784 	.get_link_ksettings = ql_get_link_ksettings,
1785 };
1786 
1787 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1788 {
1789 	struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1790 	dma_addr_t map;
1791 	int err;
1792 
1793 	while (lrg_buf_cb) {
1794 		if (!lrg_buf_cb->skb) {
1795 			lrg_buf_cb->skb =
1796 				netdev_alloc_skb(qdev->ndev,
1797 						 qdev->lrg_buffer_len);
1798 			if (unlikely(!lrg_buf_cb->skb)) {
1799 				netdev_printk(KERN_DEBUG, qdev->ndev,
1800 					      "Failed netdev_alloc_skb()\n");
1801 				break;
1802 			} else {
1803 				/*
1804 				 * We save some space to copy the ethhdr from
1805 				 * first buffer
1806 				 */
1807 				skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1808 				map = pci_map_single(qdev->pdev,
1809 						     lrg_buf_cb->skb->data,
1810 						     qdev->lrg_buffer_len -
1811 						     QL_HEADER_SPACE,
1812 						     PCI_DMA_FROMDEVICE);
1813 
1814 				err = pci_dma_mapping_error(qdev->pdev, map);
1815 				if (err) {
1816 					netdev_err(qdev->ndev,
1817 						   "PCI mapping failed with error: %d\n",
1818 						   err);
1819 					dev_kfree_skb(lrg_buf_cb->skb);
1820 					lrg_buf_cb->skb = NULL;
1821 					break;
1822 				}
1823 
1824 
1825 				lrg_buf_cb->buf_phy_addr_low =
1826 					cpu_to_le32(LS_64BITS(map));
1827 				lrg_buf_cb->buf_phy_addr_high =
1828 					cpu_to_le32(MS_64BITS(map));
1829 				dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1830 				dma_unmap_len_set(lrg_buf_cb, maplen,
1831 						  qdev->lrg_buffer_len -
1832 						  QL_HEADER_SPACE);
1833 				--qdev->lrg_buf_skb_check;
1834 				if (!qdev->lrg_buf_skb_check)
1835 					return 1;
1836 			}
1837 		}
1838 		lrg_buf_cb = lrg_buf_cb->next;
1839 	}
1840 	return 0;
1841 }
1842 
1843 /*
1844  * Caller holds hw_lock.
1845  */
1846 static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1847 {
1848 	struct ql3xxx_port_registers __iomem *port_regs =
1849 		qdev->mem_map_registers;
1850 
1851 	if (qdev->small_buf_release_cnt >= 16) {
1852 		while (qdev->small_buf_release_cnt >= 16) {
1853 			qdev->small_buf_q_producer_index++;
1854 
1855 			if (qdev->small_buf_q_producer_index ==
1856 			    NUM_SBUFQ_ENTRIES)
1857 				qdev->small_buf_q_producer_index = 0;
1858 			qdev->small_buf_release_cnt -= 8;
1859 		}
1860 		wmb();
1861 		writel_relaxed(qdev->small_buf_q_producer_index,
1862 			       &port_regs->CommonRegs.rxSmallQProducerIndex);
1863 		mmiowb();
1864 	}
1865 }
1866 
1867 /*
1868  * Caller holds hw_lock.
1869  */
1870 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1871 {
1872 	struct bufq_addr_element *lrg_buf_q_ele;
1873 	int i;
1874 	struct ql_rcv_buf_cb *lrg_buf_cb;
1875 	struct ql3xxx_port_registers __iomem *port_regs =
1876 		qdev->mem_map_registers;
1877 
1878 	if ((qdev->lrg_buf_free_count >= 8) &&
1879 	    (qdev->lrg_buf_release_cnt >= 16)) {
1880 
1881 		if (qdev->lrg_buf_skb_check)
1882 			if (!ql_populate_free_queue(qdev))
1883 				return;
1884 
1885 		lrg_buf_q_ele = qdev->lrg_buf_next_free;
1886 
1887 		while ((qdev->lrg_buf_release_cnt >= 16) &&
1888 		       (qdev->lrg_buf_free_count >= 8)) {
1889 
1890 			for (i = 0; i < 8; i++) {
1891 				lrg_buf_cb =
1892 				    ql_get_from_lrg_buf_free_list(qdev);
1893 				lrg_buf_q_ele->addr_high =
1894 				    lrg_buf_cb->buf_phy_addr_high;
1895 				lrg_buf_q_ele->addr_low =
1896 				    lrg_buf_cb->buf_phy_addr_low;
1897 				lrg_buf_q_ele++;
1898 
1899 				qdev->lrg_buf_release_cnt--;
1900 			}
1901 
1902 			qdev->lrg_buf_q_producer_index++;
1903 
1904 			if (qdev->lrg_buf_q_producer_index ==
1905 			    qdev->num_lbufq_entries)
1906 				qdev->lrg_buf_q_producer_index = 0;
1907 
1908 			if (qdev->lrg_buf_q_producer_index ==
1909 			    (qdev->num_lbufq_entries - 1)) {
1910 				lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1911 			}
1912 		}
1913 		wmb();
1914 		qdev->lrg_buf_next_free = lrg_buf_q_ele;
1915 		writel(qdev->lrg_buf_q_producer_index,
1916 			&port_regs->CommonRegs.rxLargeQProducerIndex);
1917 	}
1918 }
1919 
1920 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1921 				   struct ob_mac_iocb_rsp *mac_rsp)
1922 {
1923 	struct ql_tx_buf_cb *tx_cb;
1924 	int i;
1925 
1926 	if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1927 		netdev_warn(qdev->ndev,
1928 			    "Frame too short but it was padded and sent\n");
1929 	}
1930 
1931 	tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1932 
1933 	/*  Check the transmit response flags for any errors */
1934 	if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1935 		netdev_err(qdev->ndev,
1936 			   "Frame too short to be legal, frame not sent\n");
1937 
1938 		qdev->ndev->stats.tx_errors++;
1939 		goto frame_not_sent;
1940 	}
1941 
1942 	if (tx_cb->seg_count == 0) {
1943 		netdev_err(qdev->ndev, "tx_cb->seg_count == 0: %d\n",
1944 			   mac_rsp->transaction_id);
1945 
1946 		qdev->ndev->stats.tx_errors++;
1947 		goto invalid_seg_count;
1948 	}
1949 
1950 	pci_unmap_single(qdev->pdev,
1951 			 dma_unmap_addr(&tx_cb->map[0], mapaddr),
1952 			 dma_unmap_len(&tx_cb->map[0], maplen),
1953 			 PCI_DMA_TODEVICE);
1954 	tx_cb->seg_count--;
1955 	if (tx_cb->seg_count) {
1956 		for (i = 1; i < tx_cb->seg_count; i++) {
1957 			pci_unmap_page(qdev->pdev,
1958 				       dma_unmap_addr(&tx_cb->map[i],
1959 						      mapaddr),
1960 				       dma_unmap_len(&tx_cb->map[i], maplen),
1961 				       PCI_DMA_TODEVICE);
1962 		}
1963 	}
1964 	qdev->ndev->stats.tx_packets++;
1965 	qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
1966 
1967 frame_not_sent:
1968 	dev_kfree_skb_irq(tx_cb->skb);
1969 	tx_cb->skb = NULL;
1970 
1971 invalid_seg_count:
1972 	atomic_inc(&qdev->tx_count);
1973 }
1974 
1975 static void ql_get_sbuf(struct ql3_adapter *qdev)
1976 {
1977 	if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1978 		qdev->small_buf_index = 0;
1979 	qdev->small_buf_release_cnt++;
1980 }
1981 
1982 static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1983 {
1984 	struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1985 	lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1986 	qdev->lrg_buf_release_cnt++;
1987 	if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1988 		qdev->lrg_buf_index = 0;
1989 	return lrg_buf_cb;
1990 }
1991 
1992 /*
1993  * The difference between 3022 and 3032 for inbound completions:
1994  * 3022 uses two buffers per completion.  The first buffer contains
1995  * (some) header info, the second the remainder of the headers plus
1996  * the data.  For this chip we reserve some space at the top of the
1997  * receive buffer so that the header info in buffer one can be
1998  * prepended to the buffer two.  Buffer two is the sent up while
1999  * buffer one is returned to the hardware to be reused.
2000  * 3032 receives all of it's data and headers in one buffer for a
2001  * simpler process.  3032 also supports checksum verification as
2002  * can be seen in ql_process_macip_rx_intr().
2003  */
2004 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2005 				   struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2006 {
2007 	struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2008 	struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2009 	struct sk_buff *skb;
2010 	u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2011 
2012 	/*
2013 	 * Get the inbound address list (small buffer).
2014 	 */
2015 	ql_get_sbuf(qdev);
2016 
2017 	if (qdev->device_id == QL3022_DEVICE_ID)
2018 		lrg_buf_cb1 = ql_get_lbuf(qdev);
2019 
2020 	/* start of second buffer */
2021 	lrg_buf_cb2 = ql_get_lbuf(qdev);
2022 	skb = lrg_buf_cb2->skb;
2023 
2024 	qdev->ndev->stats.rx_packets++;
2025 	qdev->ndev->stats.rx_bytes += length;
2026 
2027 	skb_put(skb, length);
2028 	pci_unmap_single(qdev->pdev,
2029 			 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2030 			 dma_unmap_len(lrg_buf_cb2, maplen),
2031 			 PCI_DMA_FROMDEVICE);
2032 	prefetch(skb->data);
2033 	skb_checksum_none_assert(skb);
2034 	skb->protocol = eth_type_trans(skb, qdev->ndev);
2035 
2036 	napi_gro_receive(&qdev->napi, skb);
2037 	lrg_buf_cb2->skb = NULL;
2038 
2039 	if (qdev->device_id == QL3022_DEVICE_ID)
2040 		ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2041 	ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2042 }
2043 
2044 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2045 				     struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2046 {
2047 	struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2048 	struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2049 	struct sk_buff *skb1 = NULL, *skb2;
2050 	struct net_device *ndev = qdev->ndev;
2051 	u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2052 	u16 size = 0;
2053 
2054 	/*
2055 	 * Get the inbound address list (small buffer).
2056 	 */
2057 
2058 	ql_get_sbuf(qdev);
2059 
2060 	if (qdev->device_id == QL3022_DEVICE_ID) {
2061 		/* start of first buffer on 3022 */
2062 		lrg_buf_cb1 = ql_get_lbuf(qdev);
2063 		skb1 = lrg_buf_cb1->skb;
2064 		size = ETH_HLEN;
2065 		if (*((u16 *) skb1->data) != 0xFFFF)
2066 			size += VLAN_ETH_HLEN - ETH_HLEN;
2067 	}
2068 
2069 	/* start of second buffer */
2070 	lrg_buf_cb2 = ql_get_lbuf(qdev);
2071 	skb2 = lrg_buf_cb2->skb;
2072 
2073 	skb_put(skb2, length);	/* Just the second buffer length here. */
2074 	pci_unmap_single(qdev->pdev,
2075 			 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2076 			 dma_unmap_len(lrg_buf_cb2, maplen),
2077 			 PCI_DMA_FROMDEVICE);
2078 	prefetch(skb2->data);
2079 
2080 	skb_checksum_none_assert(skb2);
2081 	if (qdev->device_id == QL3022_DEVICE_ID) {
2082 		/*
2083 		 * Copy the ethhdr from first buffer to second. This
2084 		 * is necessary for 3022 IP completions.
2085 		 */
2086 		skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2087 						 skb_push(skb2, size), size);
2088 	} else {
2089 		u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2090 		if (checksum &
2091 			(IB_IP_IOCB_RSP_3032_ICE |
2092 			 IB_IP_IOCB_RSP_3032_CE)) {
2093 			netdev_err(ndev,
2094 				   "%s: Bad checksum for this %s packet, checksum = %x\n",
2095 				   __func__,
2096 				   ((checksum & IB_IP_IOCB_RSP_3032_TCP) ?
2097 				    "TCP" : "UDP"), checksum);
2098 		} else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2099 				(checksum & IB_IP_IOCB_RSP_3032_UDP &&
2100 				!(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2101 			skb2->ip_summed = CHECKSUM_UNNECESSARY;
2102 		}
2103 	}
2104 	skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2105 
2106 	napi_gro_receive(&qdev->napi, skb2);
2107 	ndev->stats.rx_packets++;
2108 	ndev->stats.rx_bytes += length;
2109 	lrg_buf_cb2->skb = NULL;
2110 
2111 	if (qdev->device_id == QL3022_DEVICE_ID)
2112 		ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2113 	ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2114 }
2115 
2116 static int ql_tx_rx_clean(struct ql3_adapter *qdev, int budget)
2117 {
2118 	struct net_rsp_iocb *net_rsp;
2119 	struct net_device *ndev = qdev->ndev;
2120 	int work_done = 0;
2121 
2122 	/* While there are entries in the completion queue. */
2123 	while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2124 		qdev->rsp_consumer_index) && (work_done < budget)) {
2125 
2126 		net_rsp = qdev->rsp_current;
2127 		rmb();
2128 		/*
2129 		 * Fix 4032 chip's undocumented "feature" where bit-8 is set
2130 		 * if the inbound completion is for a VLAN.
2131 		 */
2132 		if (qdev->device_id == QL3032_DEVICE_ID)
2133 			net_rsp->opcode &= 0x7f;
2134 		switch (net_rsp->opcode) {
2135 
2136 		case OPCODE_OB_MAC_IOCB_FN0:
2137 		case OPCODE_OB_MAC_IOCB_FN2:
2138 			ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2139 					       net_rsp);
2140 			break;
2141 
2142 		case OPCODE_IB_MAC_IOCB:
2143 		case OPCODE_IB_3032_MAC_IOCB:
2144 			ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2145 					       net_rsp);
2146 			work_done++;
2147 			break;
2148 
2149 		case OPCODE_IB_IP_IOCB:
2150 		case OPCODE_IB_3032_IP_IOCB:
2151 			ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2152 						 net_rsp);
2153 			work_done++;
2154 			break;
2155 		default: {
2156 			u32 *tmp = (u32 *)net_rsp;
2157 			netdev_err(ndev,
2158 				   "Hit default case, not handled!\n"
2159 				   "	dropping the packet, opcode = %x\n"
2160 				   "0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
2161 				   net_rsp->opcode,
2162 				   (unsigned long int)tmp[0],
2163 				   (unsigned long int)tmp[1],
2164 				   (unsigned long int)tmp[2],
2165 				   (unsigned long int)tmp[3]);
2166 		}
2167 		}
2168 
2169 		qdev->rsp_consumer_index++;
2170 
2171 		if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2172 			qdev->rsp_consumer_index = 0;
2173 			qdev->rsp_current = qdev->rsp_q_virt_addr;
2174 		} else {
2175 			qdev->rsp_current++;
2176 		}
2177 
2178 	}
2179 
2180 	return work_done;
2181 }
2182 
2183 static int ql_poll(struct napi_struct *napi, int budget)
2184 {
2185 	struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2186 	struct ql3xxx_port_registers __iomem *port_regs =
2187 		qdev->mem_map_registers;
2188 	int work_done;
2189 
2190 	work_done = ql_tx_rx_clean(qdev, budget);
2191 
2192 	if (work_done < budget && napi_complete_done(napi, work_done)) {
2193 		unsigned long flags;
2194 
2195 		spin_lock_irqsave(&qdev->hw_lock, flags);
2196 		ql_update_small_bufq_prod_index(qdev);
2197 		ql_update_lrg_bufq_prod_index(qdev);
2198 		writel(qdev->rsp_consumer_index,
2199 			    &port_regs->CommonRegs.rspQConsumerIndex);
2200 		spin_unlock_irqrestore(&qdev->hw_lock, flags);
2201 
2202 		ql_enable_interrupts(qdev);
2203 	}
2204 	return work_done;
2205 }
2206 
2207 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2208 {
2209 
2210 	struct net_device *ndev = dev_id;
2211 	struct ql3_adapter *qdev = netdev_priv(ndev);
2212 	struct ql3xxx_port_registers __iomem *port_regs =
2213 		qdev->mem_map_registers;
2214 	u32 value;
2215 	int handled = 1;
2216 	u32 var;
2217 
2218 	value = ql_read_common_reg_l(qdev,
2219 				     &port_regs->CommonRegs.ispControlStatus);
2220 
2221 	if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2222 		spin_lock(&qdev->adapter_lock);
2223 		netif_stop_queue(qdev->ndev);
2224 		netif_carrier_off(qdev->ndev);
2225 		ql_disable_interrupts(qdev);
2226 		qdev->port_link_state = LS_DOWN;
2227 		set_bit(QL_RESET_ACTIVE, &qdev->flags) ;
2228 
2229 		if (value & ISP_CONTROL_FE) {
2230 			/*
2231 			 * Chip Fatal Error.
2232 			 */
2233 			var =
2234 			    ql_read_page0_reg_l(qdev,
2235 					      &port_regs->PortFatalErrStatus);
2236 			netdev_warn(ndev,
2237 				    "Resetting chip. PortFatalErrStatus register = 0x%x\n",
2238 				    var);
2239 			set_bit(QL_RESET_START, &qdev->flags) ;
2240 		} else {
2241 			/*
2242 			 * Soft Reset Requested.
2243 			 */
2244 			set_bit(QL_RESET_PER_SCSI, &qdev->flags) ;
2245 			netdev_err(ndev,
2246 				   "Another function issued a reset to the chip. ISR value = %x\n",
2247 				   value);
2248 		}
2249 		queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2250 		spin_unlock(&qdev->adapter_lock);
2251 	} else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2252 		ql_disable_interrupts(qdev);
2253 		if (likely(napi_schedule_prep(&qdev->napi)))
2254 			__napi_schedule(&qdev->napi);
2255 	} else
2256 		return IRQ_NONE;
2257 
2258 	return IRQ_RETVAL(handled);
2259 }
2260 
2261 /*
2262  * Get the total number of segments needed for the given number of fragments.
2263  * This is necessary because outbound address lists (OAL) will be used when
2264  * more than two frags are given.  Each address list has 5 addr/len pairs.
2265  * The 5th pair in each OAL is used to  point to the next OAL if more frags
2266  * are coming.  That is why the frags:segment count ratio is not linear.
2267  */
2268 static int ql_get_seg_count(struct ql3_adapter *qdev, unsigned short frags)
2269 {
2270 	if (qdev->device_id == QL3022_DEVICE_ID)
2271 		return 1;
2272 
2273 	if (frags <= 2)
2274 		return frags + 1;
2275 	else if (frags <= 6)
2276 		return frags + 2;
2277 	else if (frags <= 10)
2278 		return frags + 3;
2279 	else if (frags <= 14)
2280 		return frags + 4;
2281 	else if (frags <= 18)
2282 		return frags + 5;
2283 	return -1;
2284 }
2285 
2286 static void ql_hw_csum_setup(const struct sk_buff *skb,
2287 			     struct ob_mac_iocb_req *mac_iocb_ptr)
2288 {
2289 	const struct iphdr *ip = ip_hdr(skb);
2290 
2291 	mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2292 	mac_iocb_ptr->ip_hdr_len = ip->ihl;
2293 
2294 	if (ip->protocol == IPPROTO_TCP) {
2295 		mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2296 			OB_3032MAC_IOCB_REQ_IC;
2297 	} else {
2298 		mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2299 			OB_3032MAC_IOCB_REQ_IC;
2300 	}
2301 
2302 }
2303 
2304 /*
2305  * Map the buffers for this transmit.
2306  * This will return NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2307  */
2308 static int ql_send_map(struct ql3_adapter *qdev,
2309 				struct ob_mac_iocb_req *mac_iocb_ptr,
2310 				struct ql_tx_buf_cb *tx_cb,
2311 				struct sk_buff *skb)
2312 {
2313 	struct oal *oal;
2314 	struct oal_entry *oal_entry;
2315 	int len = skb_headlen(skb);
2316 	dma_addr_t map;
2317 	int err;
2318 	int completed_segs, i;
2319 	int seg_cnt, seg = 0;
2320 	int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2321 
2322 	seg_cnt = tx_cb->seg_count;
2323 	/*
2324 	 * Map the skb buffer first.
2325 	 */
2326 	map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2327 
2328 	err = pci_dma_mapping_error(qdev->pdev, map);
2329 	if (err) {
2330 		netdev_err(qdev->ndev, "PCI mapping failed with error: %d\n",
2331 			   err);
2332 
2333 		return NETDEV_TX_BUSY;
2334 	}
2335 
2336 	oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2337 	oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2338 	oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2339 	oal_entry->len = cpu_to_le32(len);
2340 	dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2341 	dma_unmap_len_set(&tx_cb->map[seg], maplen, len);
2342 	seg++;
2343 
2344 	if (seg_cnt == 1) {
2345 		/* Terminate the last segment. */
2346 		oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2347 		return NETDEV_TX_OK;
2348 	}
2349 	oal = tx_cb->oal;
2350 	for (completed_segs = 0;
2351 	     completed_segs < frag_cnt;
2352 	     completed_segs++, seg++) {
2353 		skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2354 		oal_entry++;
2355 		/*
2356 		 * Check for continuation requirements.
2357 		 * It's strange but necessary.
2358 		 * Continuation entry points to outbound address list.
2359 		 */
2360 		if ((seg == 2 && seg_cnt > 3) ||
2361 		    (seg == 7 && seg_cnt > 8) ||
2362 		    (seg == 12 && seg_cnt > 13) ||
2363 		    (seg == 17 && seg_cnt > 18)) {
2364 			map = pci_map_single(qdev->pdev, oal,
2365 					     sizeof(struct oal),
2366 					     PCI_DMA_TODEVICE);
2367 
2368 			err = pci_dma_mapping_error(qdev->pdev, map);
2369 			if (err) {
2370 				netdev_err(qdev->ndev,
2371 					   "PCI mapping outbound address list with error: %d\n",
2372 					   err);
2373 				goto map_error;
2374 			}
2375 
2376 			oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2377 			oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2378 			oal_entry->len = cpu_to_le32(sizeof(struct oal) |
2379 						     OAL_CONT_ENTRY);
2380 			dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2381 			dma_unmap_len_set(&tx_cb->map[seg], maplen,
2382 					  sizeof(struct oal));
2383 			oal_entry = (struct oal_entry *)oal;
2384 			oal++;
2385 			seg++;
2386 		}
2387 
2388 		map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
2389 				       DMA_TO_DEVICE);
2390 
2391 		err = dma_mapping_error(&qdev->pdev->dev, map);
2392 		if (err) {
2393 			netdev_err(qdev->ndev,
2394 				   "PCI mapping frags failed with error: %d\n",
2395 				   err);
2396 			goto map_error;
2397 		}
2398 
2399 		oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2400 		oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2401 		oal_entry->len = cpu_to_le32(skb_frag_size(frag));
2402 		dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2403 		dma_unmap_len_set(&tx_cb->map[seg], maplen, skb_frag_size(frag));
2404 		}
2405 	/* Terminate the last segment. */
2406 	oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2407 	return NETDEV_TX_OK;
2408 
2409 map_error:
2410 	/* A PCI mapping failed and now we will need to back out
2411 	 * We need to traverse through the oal's and associated pages which
2412 	 * have been mapped and now we must unmap them to clean up properly
2413 	 */
2414 
2415 	seg = 1;
2416 	oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2417 	oal = tx_cb->oal;
2418 	for (i = 0; i < completed_segs; i++, seg++) {
2419 		oal_entry++;
2420 
2421 		/*
2422 		 * Check for continuation requirements.
2423 		 * It's strange but necessary.
2424 		 */
2425 
2426 		if ((seg == 2 && seg_cnt > 3) ||
2427 		    (seg == 7 && seg_cnt > 8) ||
2428 		    (seg == 12 && seg_cnt > 13) ||
2429 		    (seg == 17 && seg_cnt > 18)) {
2430 			pci_unmap_single(qdev->pdev,
2431 				dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2432 				dma_unmap_len(&tx_cb->map[seg], maplen),
2433 				 PCI_DMA_TODEVICE);
2434 			oal++;
2435 			seg++;
2436 		}
2437 
2438 		pci_unmap_page(qdev->pdev,
2439 			       dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2440 			       dma_unmap_len(&tx_cb->map[seg], maplen),
2441 			       PCI_DMA_TODEVICE);
2442 	}
2443 
2444 	pci_unmap_single(qdev->pdev,
2445 			 dma_unmap_addr(&tx_cb->map[0], mapaddr),
2446 			 dma_unmap_addr(&tx_cb->map[0], maplen),
2447 			 PCI_DMA_TODEVICE);
2448 
2449 	return NETDEV_TX_BUSY;
2450 
2451 }
2452 
2453 /*
2454  * The difference between 3022 and 3032 sends:
2455  * 3022 only supports a simple single segment transmission.
2456  * 3032 supports checksumming and scatter/gather lists (fragments).
2457  * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2458  * in the IOCB plus a chain of outbound address lists (OAL) that
2459  * each contain 5 ALPs.  The last ALP of the IOCB (3rd) or OAL (5th)
2460  * will be used to point to an OAL when more ALP entries are required.
2461  * The IOCB is always the top of the chain followed by one or more
2462  * OALs (when necessary).
2463  */
2464 static netdev_tx_t ql3xxx_send(struct sk_buff *skb,
2465 			       struct net_device *ndev)
2466 {
2467 	struct ql3_adapter *qdev = netdev_priv(ndev);
2468 	struct ql3xxx_port_registers __iomem *port_regs =
2469 			qdev->mem_map_registers;
2470 	struct ql_tx_buf_cb *tx_cb;
2471 	u32 tot_len = skb->len;
2472 	struct ob_mac_iocb_req *mac_iocb_ptr;
2473 
2474 	if (unlikely(atomic_read(&qdev->tx_count) < 2))
2475 		return NETDEV_TX_BUSY;
2476 
2477 	tx_cb = &qdev->tx_buf[qdev->req_producer_index];
2478 	tx_cb->seg_count = ql_get_seg_count(qdev,
2479 					     skb_shinfo(skb)->nr_frags);
2480 	if (tx_cb->seg_count == -1) {
2481 		netdev_err(ndev, "%s: invalid segment count!\n", __func__);
2482 		return NETDEV_TX_OK;
2483 	}
2484 
2485 	mac_iocb_ptr = tx_cb->queue_entry;
2486 	memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2487 	mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2488 	mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2489 	mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2490 	mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2491 	mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2492 	tx_cb->skb = skb;
2493 	if (qdev->device_id == QL3032_DEVICE_ID &&
2494 	    skb->ip_summed == CHECKSUM_PARTIAL)
2495 		ql_hw_csum_setup(skb, mac_iocb_ptr);
2496 
2497 	if (ql_send_map(qdev, mac_iocb_ptr, tx_cb, skb) != NETDEV_TX_OK) {
2498 		netdev_err(ndev, "%s: Could not map the segments!\n", __func__);
2499 		return NETDEV_TX_BUSY;
2500 	}
2501 
2502 	wmb();
2503 	qdev->req_producer_index++;
2504 	if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2505 		qdev->req_producer_index = 0;
2506 	wmb();
2507 	ql_write_common_reg_l(qdev,
2508 			    &port_regs->CommonRegs.reqQProducerIndex,
2509 			    qdev->req_producer_index);
2510 
2511 	netif_printk(qdev, tx_queued, KERN_DEBUG, ndev,
2512 		     "tx queued, slot %d, len %d\n",
2513 		     qdev->req_producer_index, skb->len);
2514 
2515 	atomic_dec(&qdev->tx_count);
2516 	return NETDEV_TX_OK;
2517 }
2518 
2519 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2520 {
2521 	qdev->req_q_size =
2522 	    (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2523 
2524 	qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2525 
2526 	/* The barrier is required to ensure request and response queue
2527 	 * addr writes to the registers.
2528 	 */
2529 	wmb();
2530 
2531 	qdev->req_q_virt_addr =
2532 	    pci_alloc_consistent(qdev->pdev,
2533 				 (size_t) qdev->req_q_size,
2534 				 &qdev->req_q_phy_addr);
2535 
2536 	if ((qdev->req_q_virt_addr == NULL) ||
2537 	    LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2538 		netdev_err(qdev->ndev, "reqQ failed\n");
2539 		return -ENOMEM;
2540 	}
2541 
2542 	qdev->rsp_q_virt_addr =
2543 	    pci_alloc_consistent(qdev->pdev,
2544 				 (size_t) qdev->rsp_q_size,
2545 				 &qdev->rsp_q_phy_addr);
2546 
2547 	if ((qdev->rsp_q_virt_addr == NULL) ||
2548 	    LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2549 		netdev_err(qdev->ndev, "rspQ allocation failed\n");
2550 		pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2551 				    qdev->req_q_virt_addr,
2552 				    qdev->req_q_phy_addr);
2553 		return -ENOMEM;
2554 	}
2555 
2556 	set_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2557 
2558 	return 0;
2559 }
2560 
2561 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2562 {
2563 	if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags)) {
2564 		netdev_info(qdev->ndev, "Already done\n");
2565 		return;
2566 	}
2567 
2568 	pci_free_consistent(qdev->pdev,
2569 			    qdev->req_q_size,
2570 			    qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2571 
2572 	qdev->req_q_virt_addr = NULL;
2573 
2574 	pci_free_consistent(qdev->pdev,
2575 			    qdev->rsp_q_size,
2576 			    qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2577 
2578 	qdev->rsp_q_virt_addr = NULL;
2579 
2580 	clear_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2581 }
2582 
2583 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2584 {
2585 	/* Create Large Buffer Queue */
2586 	qdev->lrg_buf_q_size =
2587 		qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2588 	if (qdev->lrg_buf_q_size < PAGE_SIZE)
2589 		qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2590 	else
2591 		qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2592 
2593 	qdev->lrg_buf = kmalloc_array(qdev->num_large_buffers,
2594 				      sizeof(struct ql_rcv_buf_cb),
2595 				      GFP_KERNEL);
2596 	if (qdev->lrg_buf == NULL)
2597 		return -ENOMEM;
2598 
2599 	qdev->lrg_buf_q_alloc_virt_addr =
2600 		pci_alloc_consistent(qdev->pdev,
2601 				     qdev->lrg_buf_q_alloc_size,
2602 				     &qdev->lrg_buf_q_alloc_phy_addr);
2603 
2604 	if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2605 		netdev_err(qdev->ndev, "lBufQ failed\n");
2606 		return -ENOMEM;
2607 	}
2608 	qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2609 	qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2610 
2611 	/* Create Small Buffer Queue */
2612 	qdev->small_buf_q_size =
2613 		NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2614 	if (qdev->small_buf_q_size < PAGE_SIZE)
2615 		qdev->small_buf_q_alloc_size = PAGE_SIZE;
2616 	else
2617 		qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2618 
2619 	qdev->small_buf_q_alloc_virt_addr =
2620 		pci_alloc_consistent(qdev->pdev,
2621 				     qdev->small_buf_q_alloc_size,
2622 				     &qdev->small_buf_q_alloc_phy_addr);
2623 
2624 	if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2625 		netdev_err(qdev->ndev, "Small Buffer Queue allocation failed\n");
2626 		pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2627 				    qdev->lrg_buf_q_alloc_virt_addr,
2628 				    qdev->lrg_buf_q_alloc_phy_addr);
2629 		return -ENOMEM;
2630 	}
2631 
2632 	qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2633 	qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2634 	set_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2635 	return 0;
2636 }
2637 
2638 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2639 {
2640 	if (!test_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags)) {
2641 		netdev_info(qdev->ndev, "Already done\n");
2642 		return;
2643 	}
2644 	kfree(qdev->lrg_buf);
2645 	pci_free_consistent(qdev->pdev,
2646 			    qdev->lrg_buf_q_alloc_size,
2647 			    qdev->lrg_buf_q_alloc_virt_addr,
2648 			    qdev->lrg_buf_q_alloc_phy_addr);
2649 
2650 	qdev->lrg_buf_q_virt_addr = NULL;
2651 
2652 	pci_free_consistent(qdev->pdev,
2653 			    qdev->small_buf_q_alloc_size,
2654 			    qdev->small_buf_q_alloc_virt_addr,
2655 			    qdev->small_buf_q_alloc_phy_addr);
2656 
2657 	qdev->small_buf_q_virt_addr = NULL;
2658 
2659 	clear_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2660 }
2661 
2662 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2663 {
2664 	int i;
2665 	struct bufq_addr_element *small_buf_q_entry;
2666 
2667 	/* Currently we allocate on one of memory and use it for smallbuffers */
2668 	qdev->small_buf_total_size =
2669 		(QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2670 		 QL_SMALL_BUFFER_SIZE);
2671 
2672 	qdev->small_buf_virt_addr =
2673 		pci_alloc_consistent(qdev->pdev,
2674 				     qdev->small_buf_total_size,
2675 				     &qdev->small_buf_phy_addr);
2676 
2677 	if (qdev->small_buf_virt_addr == NULL) {
2678 		netdev_err(qdev->ndev, "Failed to get small buffer memory\n");
2679 		return -ENOMEM;
2680 	}
2681 
2682 	qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2683 	qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2684 
2685 	small_buf_q_entry = qdev->small_buf_q_virt_addr;
2686 
2687 	/* Initialize the small buffer queue. */
2688 	for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2689 		small_buf_q_entry->addr_high =
2690 		    cpu_to_le32(qdev->small_buf_phy_addr_high);
2691 		small_buf_q_entry->addr_low =
2692 		    cpu_to_le32(qdev->small_buf_phy_addr_low +
2693 				(i * QL_SMALL_BUFFER_SIZE));
2694 		small_buf_q_entry++;
2695 	}
2696 	qdev->small_buf_index = 0;
2697 	set_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags);
2698 	return 0;
2699 }
2700 
2701 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2702 {
2703 	if (!test_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags)) {
2704 		netdev_info(qdev->ndev, "Already done\n");
2705 		return;
2706 	}
2707 	if (qdev->small_buf_virt_addr != NULL) {
2708 		pci_free_consistent(qdev->pdev,
2709 				    qdev->small_buf_total_size,
2710 				    qdev->small_buf_virt_addr,
2711 				    qdev->small_buf_phy_addr);
2712 
2713 		qdev->small_buf_virt_addr = NULL;
2714 	}
2715 }
2716 
2717 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2718 {
2719 	int i = 0;
2720 	struct ql_rcv_buf_cb *lrg_buf_cb;
2721 
2722 	for (i = 0; i < qdev->num_large_buffers; i++) {
2723 		lrg_buf_cb = &qdev->lrg_buf[i];
2724 		if (lrg_buf_cb->skb) {
2725 			dev_kfree_skb(lrg_buf_cb->skb);
2726 			pci_unmap_single(qdev->pdev,
2727 					 dma_unmap_addr(lrg_buf_cb, mapaddr),
2728 					 dma_unmap_len(lrg_buf_cb, maplen),
2729 					 PCI_DMA_FROMDEVICE);
2730 			memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2731 		} else {
2732 			break;
2733 		}
2734 	}
2735 }
2736 
2737 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2738 {
2739 	int i;
2740 	struct ql_rcv_buf_cb *lrg_buf_cb;
2741 	struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2742 
2743 	for (i = 0; i < qdev->num_large_buffers; i++) {
2744 		lrg_buf_cb = &qdev->lrg_buf[i];
2745 		buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2746 		buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2747 		buf_addr_ele++;
2748 	}
2749 	qdev->lrg_buf_index = 0;
2750 	qdev->lrg_buf_skb_check = 0;
2751 }
2752 
2753 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2754 {
2755 	int i;
2756 	struct ql_rcv_buf_cb *lrg_buf_cb;
2757 	struct sk_buff *skb;
2758 	dma_addr_t map;
2759 	int err;
2760 
2761 	for (i = 0; i < qdev->num_large_buffers; i++) {
2762 		skb = netdev_alloc_skb(qdev->ndev,
2763 				       qdev->lrg_buffer_len);
2764 		if (unlikely(!skb)) {
2765 			/* Better luck next round */
2766 			netdev_err(qdev->ndev,
2767 				   "large buff alloc failed for %d bytes at index %d\n",
2768 				   qdev->lrg_buffer_len * 2, i);
2769 			ql_free_large_buffers(qdev);
2770 			return -ENOMEM;
2771 		} else {
2772 
2773 			lrg_buf_cb = &qdev->lrg_buf[i];
2774 			memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2775 			lrg_buf_cb->index = i;
2776 			lrg_buf_cb->skb = skb;
2777 			/*
2778 			 * We save some space to copy the ethhdr from first
2779 			 * buffer
2780 			 */
2781 			skb_reserve(skb, QL_HEADER_SPACE);
2782 			map = pci_map_single(qdev->pdev,
2783 					     skb->data,
2784 					     qdev->lrg_buffer_len -
2785 					     QL_HEADER_SPACE,
2786 					     PCI_DMA_FROMDEVICE);
2787 
2788 			err = pci_dma_mapping_error(qdev->pdev, map);
2789 			if (err) {
2790 				netdev_err(qdev->ndev,
2791 					   "PCI mapping failed with error: %d\n",
2792 					   err);
2793 				ql_free_large_buffers(qdev);
2794 				return -ENOMEM;
2795 			}
2796 
2797 			dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2798 			dma_unmap_len_set(lrg_buf_cb, maplen,
2799 					  qdev->lrg_buffer_len -
2800 					  QL_HEADER_SPACE);
2801 			lrg_buf_cb->buf_phy_addr_low =
2802 			    cpu_to_le32(LS_64BITS(map));
2803 			lrg_buf_cb->buf_phy_addr_high =
2804 			    cpu_to_le32(MS_64BITS(map));
2805 		}
2806 	}
2807 	return 0;
2808 }
2809 
2810 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2811 {
2812 	struct ql_tx_buf_cb *tx_cb;
2813 	int i;
2814 
2815 	tx_cb = &qdev->tx_buf[0];
2816 	for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2817 		kfree(tx_cb->oal);
2818 		tx_cb->oal = NULL;
2819 		tx_cb++;
2820 	}
2821 }
2822 
2823 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2824 {
2825 	struct ql_tx_buf_cb *tx_cb;
2826 	int i;
2827 	struct ob_mac_iocb_req *req_q_curr = qdev->req_q_virt_addr;
2828 
2829 	/* Create free list of transmit buffers */
2830 	for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2831 
2832 		tx_cb = &qdev->tx_buf[i];
2833 		tx_cb->skb = NULL;
2834 		tx_cb->queue_entry = req_q_curr;
2835 		req_q_curr++;
2836 		tx_cb->oal = kmalloc(512, GFP_KERNEL);
2837 		if (tx_cb->oal == NULL)
2838 			return -ENOMEM;
2839 	}
2840 	return 0;
2841 }
2842 
2843 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2844 {
2845 	if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2846 		qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2847 		qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2848 	} else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2849 		/*
2850 		 * Bigger buffers, so less of them.
2851 		 */
2852 		qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2853 		qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2854 	} else {
2855 		netdev_err(qdev->ndev, "Invalid mtu size: %d.  Only %d and %d are accepted.\n",
2856 			   qdev->ndev->mtu, NORMAL_MTU_SIZE, JUMBO_MTU_SIZE);
2857 		return -ENOMEM;
2858 	}
2859 	qdev->num_large_buffers =
2860 		qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2861 	qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2862 	qdev->max_frame_size =
2863 		(qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2864 
2865 	/*
2866 	 * First allocate a page of shared memory and use it for shadow
2867 	 * locations of Network Request Queue Consumer Address Register and
2868 	 * Network Completion Queue Producer Index Register
2869 	 */
2870 	qdev->shadow_reg_virt_addr =
2871 		pci_alloc_consistent(qdev->pdev,
2872 				     PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2873 
2874 	if (qdev->shadow_reg_virt_addr != NULL) {
2875 		qdev->preq_consumer_index = qdev->shadow_reg_virt_addr;
2876 		qdev->req_consumer_index_phy_addr_high =
2877 			MS_64BITS(qdev->shadow_reg_phy_addr);
2878 		qdev->req_consumer_index_phy_addr_low =
2879 			LS_64BITS(qdev->shadow_reg_phy_addr);
2880 
2881 		qdev->prsp_producer_index =
2882 			(__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2883 		qdev->rsp_producer_index_phy_addr_high =
2884 			qdev->req_consumer_index_phy_addr_high;
2885 		qdev->rsp_producer_index_phy_addr_low =
2886 			qdev->req_consumer_index_phy_addr_low + 8;
2887 	} else {
2888 		netdev_err(qdev->ndev, "shadowReg Alloc failed\n");
2889 		return -ENOMEM;
2890 	}
2891 
2892 	if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2893 		netdev_err(qdev->ndev, "ql_alloc_net_req_rsp_queues failed\n");
2894 		goto err_req_rsp;
2895 	}
2896 
2897 	if (ql_alloc_buffer_queues(qdev) != 0) {
2898 		netdev_err(qdev->ndev, "ql_alloc_buffer_queues failed\n");
2899 		goto err_buffer_queues;
2900 	}
2901 
2902 	if (ql_alloc_small_buffers(qdev) != 0) {
2903 		netdev_err(qdev->ndev, "ql_alloc_small_buffers failed\n");
2904 		goto err_small_buffers;
2905 	}
2906 
2907 	if (ql_alloc_large_buffers(qdev) != 0) {
2908 		netdev_err(qdev->ndev, "ql_alloc_large_buffers failed\n");
2909 		goto err_small_buffers;
2910 	}
2911 
2912 	/* Initialize the large buffer queue. */
2913 	ql_init_large_buffers(qdev);
2914 	if (ql_create_send_free_list(qdev))
2915 		goto err_free_list;
2916 
2917 	qdev->rsp_current = qdev->rsp_q_virt_addr;
2918 
2919 	return 0;
2920 err_free_list:
2921 	ql_free_send_free_list(qdev);
2922 err_small_buffers:
2923 	ql_free_buffer_queues(qdev);
2924 err_buffer_queues:
2925 	ql_free_net_req_rsp_queues(qdev);
2926 err_req_rsp:
2927 	pci_free_consistent(qdev->pdev,
2928 			    PAGE_SIZE,
2929 			    qdev->shadow_reg_virt_addr,
2930 			    qdev->shadow_reg_phy_addr);
2931 
2932 	return -ENOMEM;
2933 }
2934 
2935 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2936 {
2937 	ql_free_send_free_list(qdev);
2938 	ql_free_large_buffers(qdev);
2939 	ql_free_small_buffers(qdev);
2940 	ql_free_buffer_queues(qdev);
2941 	ql_free_net_req_rsp_queues(qdev);
2942 	if (qdev->shadow_reg_virt_addr != NULL) {
2943 		pci_free_consistent(qdev->pdev,
2944 				    PAGE_SIZE,
2945 				    qdev->shadow_reg_virt_addr,
2946 				    qdev->shadow_reg_phy_addr);
2947 		qdev->shadow_reg_virt_addr = NULL;
2948 	}
2949 }
2950 
2951 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2952 {
2953 	struct ql3xxx_local_ram_registers __iomem *local_ram =
2954 	    (void __iomem *)qdev->mem_map_registers;
2955 
2956 	if (ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2957 			(QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2958 			 2) << 4))
2959 		return -1;
2960 
2961 	ql_write_page2_reg(qdev,
2962 			   &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2963 
2964 	ql_write_page2_reg(qdev,
2965 			   &local_ram->maxBufletCount,
2966 			   qdev->nvram_data.bufletCount);
2967 
2968 	ql_write_page2_reg(qdev,
2969 			   &local_ram->freeBufletThresholdLow,
2970 			   (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2971 			   (qdev->nvram_data.tcpWindowThreshold0));
2972 
2973 	ql_write_page2_reg(qdev,
2974 			   &local_ram->freeBufletThresholdHigh,
2975 			   qdev->nvram_data.tcpWindowThreshold50);
2976 
2977 	ql_write_page2_reg(qdev,
2978 			   &local_ram->ipHashTableBase,
2979 			   (qdev->nvram_data.ipHashTableBaseHi << 16) |
2980 			   qdev->nvram_data.ipHashTableBaseLo);
2981 	ql_write_page2_reg(qdev,
2982 			   &local_ram->ipHashTableCount,
2983 			   qdev->nvram_data.ipHashTableSize);
2984 	ql_write_page2_reg(qdev,
2985 			   &local_ram->tcpHashTableBase,
2986 			   (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2987 			   qdev->nvram_data.tcpHashTableBaseLo);
2988 	ql_write_page2_reg(qdev,
2989 			   &local_ram->tcpHashTableCount,
2990 			   qdev->nvram_data.tcpHashTableSize);
2991 	ql_write_page2_reg(qdev,
2992 			   &local_ram->ncbBase,
2993 			   (qdev->nvram_data.ncbTableBaseHi << 16) |
2994 			   qdev->nvram_data.ncbTableBaseLo);
2995 	ql_write_page2_reg(qdev,
2996 			   &local_ram->maxNcbCount,
2997 			   qdev->nvram_data.ncbTableSize);
2998 	ql_write_page2_reg(qdev,
2999 			   &local_ram->drbBase,
3000 			   (qdev->nvram_data.drbTableBaseHi << 16) |
3001 			   qdev->nvram_data.drbTableBaseLo);
3002 	ql_write_page2_reg(qdev,
3003 			   &local_ram->maxDrbCount,
3004 			   qdev->nvram_data.drbTableSize);
3005 	ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3006 	return 0;
3007 }
3008 
3009 static int ql_adapter_initialize(struct ql3_adapter *qdev)
3010 {
3011 	u32 value;
3012 	struct ql3xxx_port_registers __iomem *port_regs =
3013 		qdev->mem_map_registers;
3014 	__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
3015 	struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3016 		(void __iomem *)port_regs;
3017 	u32 delay = 10;
3018 	int status = 0;
3019 
3020 	if (ql_mii_setup(qdev))
3021 		return -1;
3022 
3023 	/* Bring out PHY out of reset */
3024 	ql_write_common_reg(qdev, spir,
3025 			    (ISP_SERIAL_PORT_IF_WE |
3026 			     (ISP_SERIAL_PORT_IF_WE << 16)));
3027 	/* Give the PHY time to come out of reset. */
3028 	mdelay(100);
3029 	qdev->port_link_state = LS_DOWN;
3030 	netif_carrier_off(qdev->ndev);
3031 
3032 	/* V2 chip fix for ARS-39168. */
3033 	ql_write_common_reg(qdev, spir,
3034 			    (ISP_SERIAL_PORT_IF_SDE |
3035 			     (ISP_SERIAL_PORT_IF_SDE << 16)));
3036 
3037 	/* Request Queue Registers */
3038 	*((u32 *)(qdev->preq_consumer_index)) = 0;
3039 	atomic_set(&qdev->tx_count, NUM_REQ_Q_ENTRIES);
3040 	qdev->req_producer_index = 0;
3041 
3042 	ql_write_page1_reg(qdev,
3043 			   &hmem_regs->reqConsumerIndexAddrHigh,
3044 			   qdev->req_consumer_index_phy_addr_high);
3045 	ql_write_page1_reg(qdev,
3046 			   &hmem_regs->reqConsumerIndexAddrLow,
3047 			   qdev->req_consumer_index_phy_addr_low);
3048 
3049 	ql_write_page1_reg(qdev,
3050 			   &hmem_regs->reqBaseAddrHigh,
3051 			   MS_64BITS(qdev->req_q_phy_addr));
3052 	ql_write_page1_reg(qdev,
3053 			   &hmem_regs->reqBaseAddrLow,
3054 			   LS_64BITS(qdev->req_q_phy_addr));
3055 	ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3056 
3057 	/* Response Queue Registers */
3058 	*((__le16 *) (qdev->prsp_producer_index)) = 0;
3059 	qdev->rsp_consumer_index = 0;
3060 	qdev->rsp_current = qdev->rsp_q_virt_addr;
3061 
3062 	ql_write_page1_reg(qdev,
3063 			   &hmem_regs->rspProducerIndexAddrHigh,
3064 			   qdev->rsp_producer_index_phy_addr_high);
3065 
3066 	ql_write_page1_reg(qdev,
3067 			   &hmem_regs->rspProducerIndexAddrLow,
3068 			   qdev->rsp_producer_index_phy_addr_low);
3069 
3070 	ql_write_page1_reg(qdev,
3071 			   &hmem_regs->rspBaseAddrHigh,
3072 			   MS_64BITS(qdev->rsp_q_phy_addr));
3073 
3074 	ql_write_page1_reg(qdev,
3075 			   &hmem_regs->rspBaseAddrLow,
3076 			   LS_64BITS(qdev->rsp_q_phy_addr));
3077 
3078 	ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3079 
3080 	/* Large Buffer Queue */
3081 	ql_write_page1_reg(qdev,
3082 			   &hmem_regs->rxLargeQBaseAddrHigh,
3083 			   MS_64BITS(qdev->lrg_buf_q_phy_addr));
3084 
3085 	ql_write_page1_reg(qdev,
3086 			   &hmem_regs->rxLargeQBaseAddrLow,
3087 			   LS_64BITS(qdev->lrg_buf_q_phy_addr));
3088 
3089 	ql_write_page1_reg(qdev,
3090 			   &hmem_regs->rxLargeQLength,
3091 			   qdev->num_lbufq_entries);
3092 
3093 	ql_write_page1_reg(qdev,
3094 			   &hmem_regs->rxLargeBufferLength,
3095 			   qdev->lrg_buffer_len);
3096 
3097 	/* Small Buffer Queue */
3098 	ql_write_page1_reg(qdev,
3099 			   &hmem_regs->rxSmallQBaseAddrHigh,
3100 			   MS_64BITS(qdev->small_buf_q_phy_addr));
3101 
3102 	ql_write_page1_reg(qdev,
3103 			   &hmem_regs->rxSmallQBaseAddrLow,
3104 			   LS_64BITS(qdev->small_buf_q_phy_addr));
3105 
3106 	ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3107 	ql_write_page1_reg(qdev,
3108 			   &hmem_regs->rxSmallBufferLength,
3109 			   QL_SMALL_BUFFER_SIZE);
3110 
3111 	qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3112 	qdev->small_buf_release_cnt = 8;
3113 	qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3114 	qdev->lrg_buf_release_cnt = 8;
3115 	qdev->lrg_buf_next_free = qdev->lrg_buf_q_virt_addr;
3116 	qdev->small_buf_index = 0;
3117 	qdev->lrg_buf_index = 0;
3118 	qdev->lrg_buf_free_count = 0;
3119 	qdev->lrg_buf_free_head = NULL;
3120 	qdev->lrg_buf_free_tail = NULL;
3121 
3122 	ql_write_common_reg(qdev,
3123 			    &port_regs->CommonRegs.
3124 			    rxSmallQProducerIndex,
3125 			    qdev->small_buf_q_producer_index);
3126 	ql_write_common_reg(qdev,
3127 			    &port_regs->CommonRegs.
3128 			    rxLargeQProducerIndex,
3129 			    qdev->lrg_buf_q_producer_index);
3130 
3131 	/*
3132 	 * Find out if the chip has already been initialized.  If it has, then
3133 	 * we skip some of the initialization.
3134 	 */
3135 	clear_bit(QL_LINK_MASTER, &qdev->flags);
3136 	value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3137 	if ((value & PORT_STATUS_IC) == 0) {
3138 
3139 		/* Chip has not been configured yet, so let it rip. */
3140 		if (ql_init_misc_registers(qdev)) {
3141 			status = -1;
3142 			goto out;
3143 		}
3144 
3145 		value = qdev->nvram_data.tcpMaxWindowSize;
3146 		ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3147 
3148 		value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3149 
3150 		if (ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3151 				(QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3152 				 * 2) << 13)) {
3153 			status = -1;
3154 			goto out;
3155 		}
3156 		ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3157 		ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3158 				   (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3159 				     16) | (INTERNAL_CHIP_SD |
3160 					    INTERNAL_CHIP_WE)));
3161 		ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3162 	}
3163 
3164 	if (qdev->mac_index)
3165 		ql_write_page0_reg(qdev,
3166 				   &port_regs->mac1MaxFrameLengthReg,
3167 				   qdev->max_frame_size);
3168 	else
3169 		ql_write_page0_reg(qdev,
3170 					   &port_regs->mac0MaxFrameLengthReg,
3171 					   qdev->max_frame_size);
3172 
3173 	if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3174 			(QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3175 			 2) << 7)) {
3176 		status = -1;
3177 		goto out;
3178 	}
3179 
3180 	PHY_Setup(qdev);
3181 	ql_init_scan_mode(qdev);
3182 	ql_get_phy_owner(qdev);
3183 
3184 	/* Load the MAC Configuration */
3185 
3186 	/* Program lower 32 bits of the MAC address */
3187 	ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3188 			   (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3189 	ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3190 			   ((qdev->ndev->dev_addr[2] << 24)
3191 			    | (qdev->ndev->dev_addr[3] << 16)
3192 			    | (qdev->ndev->dev_addr[4] << 8)
3193 			    | qdev->ndev->dev_addr[5]));
3194 
3195 	/* Program top 16 bits of the MAC address */
3196 	ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3197 			   ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3198 	ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3199 			   ((qdev->ndev->dev_addr[0] << 8)
3200 			    | qdev->ndev->dev_addr[1]));
3201 
3202 	/* Enable Primary MAC */
3203 	ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3204 			   ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3205 			    MAC_ADDR_INDIRECT_PTR_REG_PE));
3206 
3207 	/* Clear Primary and Secondary IP addresses */
3208 	ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3209 			   ((IP_ADDR_INDEX_REG_MASK << 16) |
3210 			    (qdev->mac_index << 2)));
3211 	ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3212 
3213 	ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3214 			   ((IP_ADDR_INDEX_REG_MASK << 16) |
3215 			    ((qdev->mac_index << 2) + 1)));
3216 	ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3217 
3218 	ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3219 
3220 	/* Indicate Configuration Complete */
3221 	ql_write_page0_reg(qdev,
3222 			   &port_regs->portControl,
3223 			   ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3224 
3225 	do {
3226 		value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3227 		if (value & PORT_STATUS_IC)
3228 			break;
3229 		spin_unlock_irq(&qdev->hw_lock);
3230 		msleep(500);
3231 		spin_lock_irq(&qdev->hw_lock);
3232 	} while (--delay);
3233 
3234 	if (delay == 0) {
3235 		netdev_err(qdev->ndev, "Hw Initialization timeout\n");
3236 		status = -1;
3237 		goto out;
3238 	}
3239 
3240 	/* Enable Ethernet Function */
3241 	if (qdev->device_id == QL3032_DEVICE_ID) {
3242 		value =
3243 		    (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3244 		     QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3245 			QL3032_PORT_CONTROL_ET);
3246 		ql_write_page0_reg(qdev, &port_regs->functionControl,
3247 				   ((value << 16) | value));
3248 	} else {
3249 		value =
3250 		    (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3251 		     PORT_CONTROL_HH);
3252 		ql_write_page0_reg(qdev, &port_regs->portControl,
3253 				   ((value << 16) | value));
3254 	}
3255 
3256 
3257 out:
3258 	return status;
3259 }
3260 
3261 /*
3262  * Caller holds hw_lock.
3263  */
3264 static int ql_adapter_reset(struct ql3_adapter *qdev)
3265 {
3266 	struct ql3xxx_port_registers __iomem *port_regs =
3267 		qdev->mem_map_registers;
3268 	int status = 0;
3269 	u16 value;
3270 	int max_wait_time;
3271 
3272 	set_bit(QL_RESET_ACTIVE, &qdev->flags);
3273 	clear_bit(QL_RESET_DONE, &qdev->flags);
3274 
3275 	/*
3276 	 * Issue soft reset to chip.
3277 	 */
3278 	netdev_printk(KERN_DEBUG, qdev->ndev, "Issue soft reset to chip\n");
3279 	ql_write_common_reg(qdev,
3280 			    &port_regs->CommonRegs.ispControlStatus,
3281 			    ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3282 
3283 	/* Wait 3 seconds for reset to complete. */
3284 	netdev_printk(KERN_DEBUG, qdev->ndev,
3285 		      "Wait 10 milliseconds for reset to complete\n");
3286 
3287 	/* Wait until the firmware tells us the Soft Reset is done */
3288 	max_wait_time = 5;
3289 	do {
3290 		value =
3291 		    ql_read_common_reg(qdev,
3292 				       &port_regs->CommonRegs.ispControlStatus);
3293 		if ((value & ISP_CONTROL_SR) == 0)
3294 			break;
3295 
3296 		ssleep(1);
3297 	} while ((--max_wait_time));
3298 
3299 	/*
3300 	 * Also, make sure that the Network Reset Interrupt bit has been
3301 	 * cleared after the soft reset has taken place.
3302 	 */
3303 	value =
3304 	    ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3305 	if (value & ISP_CONTROL_RI) {
3306 		netdev_printk(KERN_DEBUG, qdev->ndev,
3307 			      "clearing RI after reset\n");
3308 		ql_write_common_reg(qdev,
3309 				    &port_regs->CommonRegs.
3310 				    ispControlStatus,
3311 				    ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3312 	}
3313 
3314 	if (max_wait_time == 0) {
3315 		/* Issue Force Soft Reset */
3316 		ql_write_common_reg(qdev,
3317 				    &port_regs->CommonRegs.
3318 				    ispControlStatus,
3319 				    ((ISP_CONTROL_FSR << 16) |
3320 				     ISP_CONTROL_FSR));
3321 		/*
3322 		 * Wait until the firmware tells us the Force Soft Reset is
3323 		 * done
3324 		 */
3325 		max_wait_time = 5;
3326 		do {
3327 			value = ql_read_common_reg(qdev,
3328 						   &port_regs->CommonRegs.
3329 						   ispControlStatus);
3330 			if ((value & ISP_CONTROL_FSR) == 0)
3331 				break;
3332 			ssleep(1);
3333 		} while ((--max_wait_time));
3334 	}
3335 	if (max_wait_time == 0)
3336 		status = 1;
3337 
3338 	clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3339 	set_bit(QL_RESET_DONE, &qdev->flags);
3340 	return status;
3341 }
3342 
3343 static void ql_set_mac_info(struct ql3_adapter *qdev)
3344 {
3345 	struct ql3xxx_port_registers __iomem *port_regs =
3346 		qdev->mem_map_registers;
3347 	u32 value, port_status;
3348 	u8 func_number;
3349 
3350 	/* Get the function number */
3351 	value =
3352 	    ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3353 	func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3354 	port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3355 	switch (value & ISP_CONTROL_FN_MASK) {
3356 	case ISP_CONTROL_FN0_NET:
3357 		qdev->mac_index = 0;
3358 		qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3359 		qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3360 		qdev->PHYAddr = PORT0_PHY_ADDRESS;
3361 		if (port_status & PORT_STATUS_SM0)
3362 			set_bit(QL_LINK_OPTICAL, &qdev->flags);
3363 		else
3364 			clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3365 		break;
3366 
3367 	case ISP_CONTROL_FN1_NET:
3368 		qdev->mac_index = 1;
3369 		qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3370 		qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3371 		qdev->PHYAddr = PORT1_PHY_ADDRESS;
3372 		if (port_status & PORT_STATUS_SM1)
3373 			set_bit(QL_LINK_OPTICAL, &qdev->flags);
3374 		else
3375 			clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3376 		break;
3377 
3378 	case ISP_CONTROL_FN0_SCSI:
3379 	case ISP_CONTROL_FN1_SCSI:
3380 	default:
3381 		netdev_printk(KERN_DEBUG, qdev->ndev,
3382 			      "Invalid function number, ispControlStatus = 0x%x\n",
3383 			      value);
3384 		break;
3385 	}
3386 	qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
3387 }
3388 
3389 static void ql_display_dev_info(struct net_device *ndev)
3390 {
3391 	struct ql3_adapter *qdev = netdev_priv(ndev);
3392 	struct pci_dev *pdev = qdev->pdev;
3393 
3394 	netdev_info(ndev,
3395 		    "%s Adapter %d RevisionID %d found %s on PCI slot %d\n",
3396 		    DRV_NAME, qdev->index, qdev->chip_rev_id,
3397 		    qdev->device_id == QL3032_DEVICE_ID ? "QLA3032" : "QLA3022",
3398 		    qdev->pci_slot);
3399 	netdev_info(ndev, "%s Interface\n",
3400 		test_bit(QL_LINK_OPTICAL, &qdev->flags) ? "OPTICAL" : "COPPER");
3401 
3402 	/*
3403 	 * Print PCI bus width/type.
3404 	 */
3405 	netdev_info(ndev, "Bus interface is %s %s\n",
3406 		    ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3407 		    ((qdev->pci_x) ? "PCI-X" : "PCI"));
3408 
3409 	netdev_info(ndev, "mem  IO base address adjusted = 0x%p\n",
3410 		    qdev->mem_map_registers);
3411 	netdev_info(ndev, "Interrupt number = %d\n", pdev->irq);
3412 
3413 	netif_info(qdev, probe, ndev, "MAC address %pM\n", ndev->dev_addr);
3414 }
3415 
3416 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3417 {
3418 	struct net_device *ndev = qdev->ndev;
3419 	int retval = 0;
3420 
3421 	netif_stop_queue(ndev);
3422 	netif_carrier_off(ndev);
3423 
3424 	clear_bit(QL_ADAPTER_UP, &qdev->flags);
3425 	clear_bit(QL_LINK_MASTER, &qdev->flags);
3426 
3427 	ql_disable_interrupts(qdev);
3428 
3429 	free_irq(qdev->pdev->irq, ndev);
3430 
3431 	if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3432 		netdev_info(qdev->ndev, "calling pci_disable_msi()\n");
3433 		clear_bit(QL_MSI_ENABLED, &qdev->flags);
3434 		pci_disable_msi(qdev->pdev);
3435 	}
3436 
3437 	del_timer_sync(&qdev->adapter_timer);
3438 
3439 	napi_disable(&qdev->napi);
3440 
3441 	if (do_reset) {
3442 		int soft_reset;
3443 		unsigned long hw_flags;
3444 
3445 		spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3446 		if (ql_wait_for_drvr_lock(qdev)) {
3447 			soft_reset = ql_adapter_reset(qdev);
3448 			if (soft_reset) {
3449 				netdev_err(ndev, "ql_adapter_reset(%d) FAILED!\n",
3450 					   qdev->index);
3451 			}
3452 			netdev_err(ndev,
3453 				   "Releasing driver lock via chip reset\n");
3454 		} else {
3455 			netdev_err(ndev,
3456 				   "Could not acquire driver lock to do reset!\n");
3457 			retval = -1;
3458 		}
3459 		spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3460 	}
3461 	ql_free_mem_resources(qdev);
3462 	return retval;
3463 }
3464 
3465 static int ql_adapter_up(struct ql3_adapter *qdev)
3466 {
3467 	struct net_device *ndev = qdev->ndev;
3468 	int err;
3469 	unsigned long irq_flags = IRQF_SHARED;
3470 	unsigned long hw_flags;
3471 
3472 	if (ql_alloc_mem_resources(qdev)) {
3473 		netdev_err(ndev, "Unable to  allocate buffers\n");
3474 		return -ENOMEM;
3475 	}
3476 
3477 	if (qdev->msi) {
3478 		if (pci_enable_msi(qdev->pdev)) {
3479 			netdev_err(ndev,
3480 				   "User requested MSI, but MSI failed to initialize.  Continuing without MSI.\n");
3481 			qdev->msi = 0;
3482 		} else {
3483 			netdev_info(ndev, "MSI Enabled...\n");
3484 			set_bit(QL_MSI_ENABLED, &qdev->flags);
3485 			irq_flags &= ~IRQF_SHARED;
3486 		}
3487 	}
3488 
3489 	err = request_irq(qdev->pdev->irq, ql3xxx_isr,
3490 			  irq_flags, ndev->name, ndev);
3491 	if (err) {
3492 		netdev_err(ndev,
3493 			   "Failed to reserve interrupt %d - already in use\n",
3494 			   qdev->pdev->irq);
3495 		goto err_irq;
3496 	}
3497 
3498 	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3499 
3500 	err = ql_wait_for_drvr_lock(qdev);
3501 	if (err) {
3502 		err = ql_adapter_initialize(qdev);
3503 		if (err) {
3504 			netdev_err(ndev, "Unable to initialize adapter\n");
3505 			goto err_init;
3506 		}
3507 		netdev_err(ndev, "Releasing driver lock\n");
3508 		ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3509 	} else {
3510 		netdev_err(ndev, "Could not acquire driver lock\n");
3511 		goto err_lock;
3512 	}
3513 
3514 	spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3515 
3516 	set_bit(QL_ADAPTER_UP, &qdev->flags);
3517 
3518 	mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3519 
3520 	napi_enable(&qdev->napi);
3521 	ql_enable_interrupts(qdev);
3522 	return 0;
3523 
3524 err_init:
3525 	ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3526 err_lock:
3527 	spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3528 	free_irq(qdev->pdev->irq, ndev);
3529 err_irq:
3530 	if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3531 		netdev_info(ndev, "calling pci_disable_msi()\n");
3532 		clear_bit(QL_MSI_ENABLED, &qdev->flags);
3533 		pci_disable_msi(qdev->pdev);
3534 	}
3535 	return err;
3536 }
3537 
3538 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3539 {
3540 	if (ql_adapter_down(qdev, reset) || ql_adapter_up(qdev)) {
3541 		netdev_err(qdev->ndev,
3542 			   "Driver up/down cycle failed, closing device\n");
3543 		rtnl_lock();
3544 		dev_close(qdev->ndev);
3545 		rtnl_unlock();
3546 		return -1;
3547 	}
3548 	return 0;
3549 }
3550 
3551 static int ql3xxx_close(struct net_device *ndev)
3552 {
3553 	struct ql3_adapter *qdev = netdev_priv(ndev);
3554 
3555 	/*
3556 	 * Wait for device to recover from a reset.
3557 	 * (Rarely happens, but possible.)
3558 	 */
3559 	while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3560 		msleep(50);
3561 
3562 	ql_adapter_down(qdev, QL_DO_RESET);
3563 	return 0;
3564 }
3565 
3566 static int ql3xxx_open(struct net_device *ndev)
3567 {
3568 	struct ql3_adapter *qdev = netdev_priv(ndev);
3569 	return ql_adapter_up(qdev);
3570 }
3571 
3572 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3573 {
3574 	struct ql3_adapter *qdev = netdev_priv(ndev);
3575 	struct ql3xxx_port_registers __iomem *port_regs =
3576 			qdev->mem_map_registers;
3577 	struct sockaddr *addr = p;
3578 	unsigned long hw_flags;
3579 
3580 	if (netif_running(ndev))
3581 		return -EBUSY;
3582 
3583 	if (!is_valid_ether_addr(addr->sa_data))
3584 		return -EADDRNOTAVAIL;
3585 
3586 	memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3587 
3588 	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3589 	/* Program lower 32 bits of the MAC address */
3590 	ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3591 			   (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3592 	ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3593 			   ((ndev->dev_addr[2] << 24) | (ndev->
3594 							 dev_addr[3] << 16) |
3595 			    (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3596 
3597 	/* Program top 16 bits of the MAC address */
3598 	ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3599 			   ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3600 	ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3601 			   ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3602 	spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3603 
3604 	return 0;
3605 }
3606 
3607 static void ql3xxx_tx_timeout(struct net_device *ndev)
3608 {
3609 	struct ql3_adapter *qdev = netdev_priv(ndev);
3610 
3611 	netdev_err(ndev, "Resetting...\n");
3612 	/*
3613 	 * Stop the queues, we've got a problem.
3614 	 */
3615 	netif_stop_queue(ndev);
3616 
3617 	/*
3618 	 * Wake up the worker to process this event.
3619 	 */
3620 	queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3621 }
3622 
3623 static void ql_reset_work(struct work_struct *work)
3624 {
3625 	struct ql3_adapter *qdev =
3626 		container_of(work, struct ql3_adapter, reset_work.work);
3627 	struct net_device *ndev = qdev->ndev;
3628 	u32 value;
3629 	struct ql_tx_buf_cb *tx_cb;
3630 	int max_wait_time, i;
3631 	struct ql3xxx_port_registers __iomem *port_regs =
3632 		qdev->mem_map_registers;
3633 	unsigned long hw_flags;
3634 
3635 	if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START), &qdev->flags)) {
3636 		clear_bit(QL_LINK_MASTER, &qdev->flags);
3637 
3638 		/*
3639 		 * Loop through the active list and return the skb.
3640 		 */
3641 		for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3642 			int j;
3643 			tx_cb = &qdev->tx_buf[i];
3644 			if (tx_cb->skb) {
3645 				netdev_printk(KERN_DEBUG, ndev,
3646 					      "Freeing lost SKB\n");
3647 				pci_unmap_single(qdev->pdev,
3648 					 dma_unmap_addr(&tx_cb->map[0],
3649 							mapaddr),
3650 					 dma_unmap_len(&tx_cb->map[0], maplen),
3651 					 PCI_DMA_TODEVICE);
3652 				for (j = 1; j < tx_cb->seg_count; j++) {
3653 					pci_unmap_page(qdev->pdev,
3654 					       dma_unmap_addr(&tx_cb->map[j],
3655 							      mapaddr),
3656 					       dma_unmap_len(&tx_cb->map[j],
3657 							     maplen),
3658 					       PCI_DMA_TODEVICE);
3659 				}
3660 				dev_kfree_skb(tx_cb->skb);
3661 				tx_cb->skb = NULL;
3662 			}
3663 		}
3664 
3665 		netdev_err(ndev, "Clearing NRI after reset\n");
3666 		spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3667 		ql_write_common_reg(qdev,
3668 				    &port_regs->CommonRegs.
3669 				    ispControlStatus,
3670 				    ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3671 		/*
3672 		 * Wait the for Soft Reset to Complete.
3673 		 */
3674 		max_wait_time = 10;
3675 		do {
3676 			value = ql_read_common_reg(qdev,
3677 						   &port_regs->CommonRegs.
3678 
3679 						   ispControlStatus);
3680 			if ((value & ISP_CONTROL_SR) == 0) {
3681 				netdev_printk(KERN_DEBUG, ndev,
3682 					      "reset completed\n");
3683 				break;
3684 			}
3685 
3686 			if (value & ISP_CONTROL_RI) {
3687 				netdev_printk(KERN_DEBUG, ndev,
3688 					      "clearing NRI after reset\n");
3689 				ql_write_common_reg(qdev,
3690 						    &port_regs->
3691 						    CommonRegs.
3692 						    ispControlStatus,
3693 						    ((ISP_CONTROL_RI <<
3694 						      16) | ISP_CONTROL_RI));
3695 			}
3696 
3697 			spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3698 			ssleep(1);
3699 			spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3700 		} while (--max_wait_time);
3701 		spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3702 
3703 		if (value & ISP_CONTROL_SR) {
3704 
3705 			/*
3706 			 * Set the reset flags and clear the board again.
3707 			 * Nothing else to do...
3708 			 */
3709 			netdev_err(ndev,
3710 				   "Timed out waiting for reset to complete\n");
3711 			netdev_err(ndev, "Do a reset\n");
3712 			clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3713 			clear_bit(QL_RESET_START, &qdev->flags);
3714 			ql_cycle_adapter(qdev, QL_DO_RESET);
3715 			return;
3716 		}
3717 
3718 		clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3719 		clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3720 		clear_bit(QL_RESET_START, &qdev->flags);
3721 		ql_cycle_adapter(qdev, QL_NO_RESET);
3722 	}
3723 }
3724 
3725 static void ql_tx_timeout_work(struct work_struct *work)
3726 {
3727 	struct ql3_adapter *qdev =
3728 		container_of(work, struct ql3_adapter, tx_timeout_work.work);
3729 
3730 	ql_cycle_adapter(qdev, QL_DO_RESET);
3731 }
3732 
3733 static void ql_get_board_info(struct ql3_adapter *qdev)
3734 {
3735 	struct ql3xxx_port_registers __iomem *port_regs =
3736 		qdev->mem_map_registers;
3737 	u32 value;
3738 
3739 	value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3740 
3741 	qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3742 	if (value & PORT_STATUS_64)
3743 		qdev->pci_width = 64;
3744 	else
3745 		qdev->pci_width = 32;
3746 	if (value & PORT_STATUS_X)
3747 		qdev->pci_x = 1;
3748 	else
3749 		qdev->pci_x = 0;
3750 	qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3751 }
3752 
3753 static void ql3xxx_timer(struct timer_list *t)
3754 {
3755 	struct ql3_adapter *qdev = from_timer(qdev, t, adapter_timer);
3756 	queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
3757 }
3758 
3759 static const struct net_device_ops ql3xxx_netdev_ops = {
3760 	.ndo_open		= ql3xxx_open,
3761 	.ndo_start_xmit		= ql3xxx_send,
3762 	.ndo_stop		= ql3xxx_close,
3763 	.ndo_validate_addr	= eth_validate_addr,
3764 	.ndo_set_mac_address	= ql3xxx_set_mac_address,
3765 	.ndo_tx_timeout		= ql3xxx_tx_timeout,
3766 };
3767 
3768 static int ql3xxx_probe(struct pci_dev *pdev,
3769 			const struct pci_device_id *pci_entry)
3770 {
3771 	struct net_device *ndev = NULL;
3772 	struct ql3_adapter *qdev = NULL;
3773 	static int cards_found;
3774 	int uninitialized_var(pci_using_dac), err;
3775 
3776 	err = pci_enable_device(pdev);
3777 	if (err) {
3778 		pr_err("%s cannot enable PCI device\n", pci_name(pdev));
3779 		goto err_out;
3780 	}
3781 
3782 	err = pci_request_regions(pdev, DRV_NAME);
3783 	if (err) {
3784 		pr_err("%s cannot obtain PCI resources\n", pci_name(pdev));
3785 		goto err_out_disable_pdev;
3786 	}
3787 
3788 	pci_set_master(pdev);
3789 
3790 	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3791 		pci_using_dac = 1;
3792 		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3793 	} else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3794 		pci_using_dac = 0;
3795 		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3796 	}
3797 
3798 	if (err) {
3799 		pr_err("%s no usable DMA configuration\n", pci_name(pdev));
3800 		goto err_out_free_regions;
3801 	}
3802 
3803 	ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3804 	if (!ndev) {
3805 		err = -ENOMEM;
3806 		goto err_out_free_regions;
3807 	}
3808 
3809 	SET_NETDEV_DEV(ndev, &pdev->dev);
3810 
3811 	pci_set_drvdata(pdev, ndev);
3812 
3813 	qdev = netdev_priv(ndev);
3814 	qdev->index = cards_found;
3815 	qdev->ndev = ndev;
3816 	qdev->pdev = pdev;
3817 	qdev->device_id = pci_entry->device;
3818 	qdev->port_link_state = LS_DOWN;
3819 	if (msi)
3820 		qdev->msi = 1;
3821 
3822 	qdev->msg_enable = netif_msg_init(debug, default_msg);
3823 
3824 	if (pci_using_dac)
3825 		ndev->features |= NETIF_F_HIGHDMA;
3826 	if (qdev->device_id == QL3032_DEVICE_ID)
3827 		ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3828 
3829 	qdev->mem_map_registers = pci_ioremap_bar(pdev, 1);
3830 	if (!qdev->mem_map_registers) {
3831 		pr_err("%s: cannot map device registers\n", pci_name(pdev));
3832 		err = -EIO;
3833 		goto err_out_free_ndev;
3834 	}
3835 
3836 	spin_lock_init(&qdev->adapter_lock);
3837 	spin_lock_init(&qdev->hw_lock);
3838 
3839 	/* Set driver entry points */
3840 	ndev->netdev_ops = &ql3xxx_netdev_ops;
3841 	ndev->ethtool_ops = &ql3xxx_ethtool_ops;
3842 	ndev->watchdog_timeo = 5 * HZ;
3843 
3844 	netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
3845 
3846 	ndev->irq = pdev->irq;
3847 
3848 	/* make sure the EEPROM is good */
3849 	if (ql_get_nvram_params(qdev)) {
3850 		pr_alert("%s: Adapter #%d, Invalid NVRAM parameters\n",
3851 			 __func__, qdev->index);
3852 		err = -EIO;
3853 		goto err_out_iounmap;
3854 	}
3855 
3856 	ql_set_mac_info(qdev);
3857 
3858 	/* Validate and set parameters */
3859 	if (qdev->mac_index) {
3860 		ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3861 		ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
3862 	} else {
3863 		ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3864 		ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
3865 	}
3866 
3867 	ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3868 
3869 	/* Record PCI bus information. */
3870 	ql_get_board_info(qdev);
3871 
3872 	/*
3873 	 * Set the Maximum Memory Read Byte Count value. We do this to handle
3874 	 * jumbo frames.
3875 	 */
3876 	if (qdev->pci_x)
3877 		pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3878 
3879 	err = register_netdev(ndev);
3880 	if (err) {
3881 		pr_err("%s: cannot register net device\n", pci_name(pdev));
3882 		goto err_out_iounmap;
3883 	}
3884 
3885 	/* we're going to reset, so assume we have no link for now */
3886 
3887 	netif_carrier_off(ndev);
3888 	netif_stop_queue(ndev);
3889 
3890 	qdev->workqueue = create_singlethread_workqueue(ndev->name);
3891 	INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3892 	INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3893 	INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
3894 
3895 	timer_setup(&qdev->adapter_timer, ql3xxx_timer, 0);
3896 	qdev->adapter_timer.expires = jiffies + HZ * 2;	/* two second delay */
3897 
3898 	if (!cards_found) {
3899 		pr_alert("%s\n", DRV_STRING);
3900 		pr_alert("Driver name: %s, Version: %s\n",
3901 			 DRV_NAME, DRV_VERSION);
3902 	}
3903 	ql_display_dev_info(ndev);
3904 
3905 	cards_found++;
3906 	return 0;
3907 
3908 err_out_iounmap:
3909 	iounmap(qdev->mem_map_registers);
3910 err_out_free_ndev:
3911 	free_netdev(ndev);
3912 err_out_free_regions:
3913 	pci_release_regions(pdev);
3914 err_out_disable_pdev:
3915 	pci_disable_device(pdev);
3916 err_out:
3917 	return err;
3918 }
3919 
3920 static void ql3xxx_remove(struct pci_dev *pdev)
3921 {
3922 	struct net_device *ndev = pci_get_drvdata(pdev);
3923 	struct ql3_adapter *qdev = netdev_priv(ndev);
3924 
3925 	unregister_netdev(ndev);
3926 
3927 	ql_disable_interrupts(qdev);
3928 
3929 	if (qdev->workqueue) {
3930 		cancel_delayed_work(&qdev->reset_work);
3931 		cancel_delayed_work(&qdev->tx_timeout_work);
3932 		destroy_workqueue(qdev->workqueue);
3933 		qdev->workqueue = NULL;
3934 	}
3935 
3936 	iounmap(qdev->mem_map_registers);
3937 	pci_release_regions(pdev);
3938 	free_netdev(ndev);
3939 }
3940 
3941 static struct pci_driver ql3xxx_driver = {
3942 
3943 	.name = DRV_NAME,
3944 	.id_table = ql3xxx_pci_tbl,
3945 	.probe = ql3xxx_probe,
3946 	.remove = ql3xxx_remove,
3947 };
3948 
3949 module_pci_driver(ql3xxx_driver);
3950