1 /* 2 * QLogic QLA3xxx NIC HBA Driver 3 * Copyright (c) 2003-2006 QLogic Corporation 4 * 5 * See LICENSE.qla3xxx for copyright and licensing details. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/kernel.h> 11 #include <linux/types.h> 12 #include <linux/module.h> 13 #include <linux/list.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/sched.h> 17 #include <linux/slab.h> 18 #include <linux/dmapool.h> 19 #include <linux/mempool.h> 20 #include <linux/spinlock.h> 21 #include <linux/kthread.h> 22 #include <linux/interrupt.h> 23 #include <linux/errno.h> 24 #include <linux/ioport.h> 25 #include <linux/ip.h> 26 #include <linux/in.h> 27 #include <linux/if_arp.h> 28 #include <linux/if_ether.h> 29 #include <linux/netdevice.h> 30 #include <linux/etherdevice.h> 31 #include <linux/ethtool.h> 32 #include <linux/skbuff.h> 33 #include <linux/rtnetlink.h> 34 #include <linux/if_vlan.h> 35 #include <linux/delay.h> 36 #include <linux/mm.h> 37 #include <linux/prefetch.h> 38 39 #include "qla3xxx.h" 40 41 #define DRV_NAME "qla3xxx" 42 #define DRV_STRING "QLogic ISP3XXX Network Driver" 43 #define DRV_VERSION "v2.03.00-k5" 44 45 static const char ql3xxx_driver_name[] = DRV_NAME; 46 static const char ql3xxx_driver_version[] = DRV_VERSION; 47 48 #define TIMED_OUT_MSG \ 49 "Timed out waiting for management port to get free before issuing command\n" 50 51 MODULE_AUTHOR("QLogic Corporation"); 52 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " "); 53 MODULE_LICENSE("GPL"); 54 MODULE_VERSION(DRV_VERSION); 55 56 static const u32 default_msg 57 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 58 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; 59 60 static int debug = -1; /* defaults above */ 61 module_param(debug, int, 0); 62 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 63 64 static int msi; 65 module_param(msi, int, 0); 66 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts."); 67 68 static const struct pci_device_id ql3xxx_pci_tbl[] = { 69 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)}, 70 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)}, 71 /* required last entry */ 72 {0,} 73 }; 74 75 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl); 76 77 /* 78 * These are the known PHY's which are used 79 */ 80 enum PHY_DEVICE_TYPE { 81 PHY_TYPE_UNKNOWN = 0, 82 PHY_VITESSE_VSC8211, 83 PHY_AGERE_ET1011C, 84 MAX_PHY_DEV_TYPES 85 }; 86 87 struct PHY_DEVICE_INFO { 88 const enum PHY_DEVICE_TYPE phyDevice; 89 const u32 phyIdOUI; 90 const u16 phyIdModel; 91 const char *name; 92 }; 93 94 static const struct PHY_DEVICE_INFO PHY_DEVICES[] = { 95 {PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"}, 96 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"}, 97 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"}, 98 }; 99 100 101 /* 102 * Caller must take hw_lock. 103 */ 104 static int ql_sem_spinlock(struct ql3_adapter *qdev, 105 u32 sem_mask, u32 sem_bits) 106 { 107 struct ql3xxx_port_registers __iomem *port_regs = 108 qdev->mem_map_registers; 109 u32 value; 110 unsigned int seconds = 3; 111 112 do { 113 writel((sem_mask | sem_bits), 114 &port_regs->CommonRegs.semaphoreReg); 115 value = readl(&port_regs->CommonRegs.semaphoreReg); 116 if ((value & (sem_mask >> 16)) == sem_bits) 117 return 0; 118 ssleep(1); 119 } while (--seconds); 120 return -1; 121 } 122 123 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask) 124 { 125 struct ql3xxx_port_registers __iomem *port_regs = 126 qdev->mem_map_registers; 127 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg); 128 readl(&port_regs->CommonRegs.semaphoreReg); 129 } 130 131 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits) 132 { 133 struct ql3xxx_port_registers __iomem *port_regs = 134 qdev->mem_map_registers; 135 u32 value; 136 137 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg); 138 value = readl(&port_regs->CommonRegs.semaphoreReg); 139 return ((value & (sem_mask >> 16)) == sem_bits); 140 } 141 142 /* 143 * Caller holds hw_lock. 144 */ 145 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev) 146 { 147 int i = 0; 148 149 do { 150 if (ql_sem_lock(qdev, 151 QL_DRVR_SEM_MASK, 152 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) 153 * 2) << 1)) { 154 netdev_printk(KERN_DEBUG, qdev->ndev, 155 "driver lock acquired\n"); 156 return 1; 157 } 158 ssleep(1); 159 } while (++i < 10); 160 161 netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n"); 162 return 0; 163 } 164 165 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page) 166 { 167 struct ql3xxx_port_registers __iomem *port_regs = 168 qdev->mem_map_registers; 169 170 writel(((ISP_CONTROL_NP_MASK << 16) | page), 171 &port_regs->CommonRegs.ispControlStatus); 172 readl(&port_regs->CommonRegs.ispControlStatus); 173 qdev->current_page = page; 174 } 175 176 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg) 177 { 178 u32 value; 179 unsigned long hw_flags; 180 181 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 182 value = readl(reg); 183 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 184 185 return value; 186 } 187 188 static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg) 189 { 190 return readl(reg); 191 } 192 193 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg) 194 { 195 u32 value; 196 unsigned long hw_flags; 197 198 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 199 200 if (qdev->current_page != 0) 201 ql_set_register_page(qdev, 0); 202 value = readl(reg); 203 204 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 205 return value; 206 } 207 208 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg) 209 { 210 if (qdev->current_page != 0) 211 ql_set_register_page(qdev, 0); 212 return readl(reg); 213 } 214 215 static void ql_write_common_reg_l(struct ql3_adapter *qdev, 216 u32 __iomem *reg, u32 value) 217 { 218 unsigned long hw_flags; 219 220 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 221 writel(value, reg); 222 readl(reg); 223 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 224 } 225 226 static void ql_write_common_reg(struct ql3_adapter *qdev, 227 u32 __iomem *reg, u32 value) 228 { 229 writel(value, reg); 230 readl(reg); 231 } 232 233 static void ql_write_nvram_reg(struct ql3_adapter *qdev, 234 u32 __iomem *reg, u32 value) 235 { 236 writel(value, reg); 237 readl(reg); 238 udelay(1); 239 } 240 241 static void ql_write_page0_reg(struct ql3_adapter *qdev, 242 u32 __iomem *reg, u32 value) 243 { 244 if (qdev->current_page != 0) 245 ql_set_register_page(qdev, 0); 246 writel(value, reg); 247 readl(reg); 248 } 249 250 /* 251 * Caller holds hw_lock. Only called during init. 252 */ 253 static void ql_write_page1_reg(struct ql3_adapter *qdev, 254 u32 __iomem *reg, u32 value) 255 { 256 if (qdev->current_page != 1) 257 ql_set_register_page(qdev, 1); 258 writel(value, reg); 259 readl(reg); 260 } 261 262 /* 263 * Caller holds hw_lock. Only called during init. 264 */ 265 static void ql_write_page2_reg(struct ql3_adapter *qdev, 266 u32 __iomem *reg, u32 value) 267 { 268 if (qdev->current_page != 2) 269 ql_set_register_page(qdev, 2); 270 writel(value, reg); 271 readl(reg); 272 } 273 274 static void ql_disable_interrupts(struct ql3_adapter *qdev) 275 { 276 struct ql3xxx_port_registers __iomem *port_regs = 277 qdev->mem_map_registers; 278 279 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg, 280 (ISP_IMR_ENABLE_INT << 16)); 281 282 } 283 284 static void ql_enable_interrupts(struct ql3_adapter *qdev) 285 { 286 struct ql3xxx_port_registers __iomem *port_regs = 287 qdev->mem_map_registers; 288 289 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg, 290 ((0xff << 16) | ISP_IMR_ENABLE_INT)); 291 292 } 293 294 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev, 295 struct ql_rcv_buf_cb *lrg_buf_cb) 296 { 297 dma_addr_t map; 298 int err; 299 lrg_buf_cb->next = NULL; 300 301 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */ 302 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb; 303 } else { 304 qdev->lrg_buf_free_tail->next = lrg_buf_cb; 305 qdev->lrg_buf_free_tail = lrg_buf_cb; 306 } 307 308 if (!lrg_buf_cb->skb) { 309 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev, 310 qdev->lrg_buffer_len); 311 if (unlikely(!lrg_buf_cb->skb)) { 312 qdev->lrg_buf_skb_check++; 313 } else { 314 /* 315 * We save some space to copy the ethhdr from first 316 * buffer 317 */ 318 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE); 319 map = pci_map_single(qdev->pdev, 320 lrg_buf_cb->skb->data, 321 qdev->lrg_buffer_len - 322 QL_HEADER_SPACE, 323 PCI_DMA_FROMDEVICE); 324 err = pci_dma_mapping_error(qdev->pdev, map); 325 if (err) { 326 netdev_err(qdev->ndev, 327 "PCI mapping failed with error: %d\n", 328 err); 329 dev_kfree_skb(lrg_buf_cb->skb); 330 lrg_buf_cb->skb = NULL; 331 332 qdev->lrg_buf_skb_check++; 333 return; 334 } 335 336 lrg_buf_cb->buf_phy_addr_low = 337 cpu_to_le32(LS_64BITS(map)); 338 lrg_buf_cb->buf_phy_addr_high = 339 cpu_to_le32(MS_64BITS(map)); 340 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map); 341 dma_unmap_len_set(lrg_buf_cb, maplen, 342 qdev->lrg_buffer_len - 343 QL_HEADER_SPACE); 344 } 345 } 346 347 qdev->lrg_buf_free_count++; 348 } 349 350 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter 351 *qdev) 352 { 353 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head; 354 355 if (lrg_buf_cb != NULL) { 356 qdev->lrg_buf_free_head = lrg_buf_cb->next; 357 if (qdev->lrg_buf_free_head == NULL) 358 qdev->lrg_buf_free_tail = NULL; 359 qdev->lrg_buf_free_count--; 360 } 361 362 return lrg_buf_cb; 363 } 364 365 static u32 addrBits = EEPROM_NO_ADDR_BITS; 366 static u32 dataBits = EEPROM_NO_DATA_BITS; 367 368 static void fm93c56a_deselect(struct ql3_adapter *qdev); 369 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr, 370 unsigned short *value); 371 372 /* 373 * Caller holds hw_lock. 374 */ 375 static void fm93c56a_select(struct ql3_adapter *qdev) 376 { 377 struct ql3xxx_port_registers __iomem *port_regs = 378 qdev->mem_map_registers; 379 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg; 380 381 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1; 382 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data); 383 ql_write_nvram_reg(qdev, spir, 384 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data)); 385 } 386 387 /* 388 * Caller holds hw_lock. 389 */ 390 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr) 391 { 392 int i; 393 u32 mask; 394 u32 dataBit; 395 u32 previousBit; 396 struct ql3xxx_port_registers __iomem *port_regs = 397 qdev->mem_map_registers; 398 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg; 399 400 /* Clock in a zero, then do the start bit */ 401 ql_write_nvram_reg(qdev, spir, 402 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data | 403 AUBURN_EEPROM_DO_1)); 404 ql_write_nvram_reg(qdev, spir, 405 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data | 406 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE)); 407 ql_write_nvram_reg(qdev, spir, 408 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data | 409 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL)); 410 411 mask = 1 << (FM93C56A_CMD_BITS - 1); 412 /* Force the previous data bit to be different */ 413 previousBit = 0xffff; 414 for (i = 0; i < FM93C56A_CMD_BITS; i++) { 415 dataBit = (cmd & mask) 416 ? AUBURN_EEPROM_DO_1 417 : AUBURN_EEPROM_DO_0; 418 if (previousBit != dataBit) { 419 /* If the bit changed, change the DO state to match */ 420 ql_write_nvram_reg(qdev, spir, 421 (ISP_NVRAM_MASK | 422 qdev->eeprom_cmd_data | dataBit)); 423 previousBit = dataBit; 424 } 425 ql_write_nvram_reg(qdev, spir, 426 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data | 427 dataBit | AUBURN_EEPROM_CLK_RISE)); 428 ql_write_nvram_reg(qdev, spir, 429 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data | 430 dataBit | AUBURN_EEPROM_CLK_FALL)); 431 cmd = cmd << 1; 432 } 433 434 mask = 1 << (addrBits - 1); 435 /* Force the previous data bit to be different */ 436 previousBit = 0xffff; 437 for (i = 0; i < addrBits; i++) { 438 dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 439 : AUBURN_EEPROM_DO_0; 440 if (previousBit != dataBit) { 441 /* 442 * If the bit changed, then change the DO state to 443 * match 444 */ 445 ql_write_nvram_reg(qdev, spir, 446 (ISP_NVRAM_MASK | 447 qdev->eeprom_cmd_data | dataBit)); 448 previousBit = dataBit; 449 } 450 ql_write_nvram_reg(qdev, spir, 451 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data | 452 dataBit | AUBURN_EEPROM_CLK_RISE)); 453 ql_write_nvram_reg(qdev, spir, 454 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data | 455 dataBit | AUBURN_EEPROM_CLK_FALL)); 456 eepromAddr = eepromAddr << 1; 457 } 458 } 459 460 /* 461 * Caller holds hw_lock. 462 */ 463 static void fm93c56a_deselect(struct ql3_adapter *qdev) 464 { 465 struct ql3xxx_port_registers __iomem *port_regs = 466 qdev->mem_map_registers; 467 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg; 468 469 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0; 470 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data); 471 } 472 473 /* 474 * Caller holds hw_lock. 475 */ 476 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value) 477 { 478 int i; 479 u32 data = 0; 480 u32 dataBit; 481 struct ql3xxx_port_registers __iomem *port_regs = 482 qdev->mem_map_registers; 483 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg; 484 485 /* Read the data bits */ 486 /* The first bit is a dummy. Clock right over it. */ 487 for (i = 0; i < dataBits; i++) { 488 ql_write_nvram_reg(qdev, spir, 489 ISP_NVRAM_MASK | qdev->eeprom_cmd_data | 490 AUBURN_EEPROM_CLK_RISE); 491 ql_write_nvram_reg(qdev, spir, 492 ISP_NVRAM_MASK | qdev->eeprom_cmd_data | 493 AUBURN_EEPROM_CLK_FALL); 494 dataBit = (ql_read_common_reg(qdev, spir) & 495 AUBURN_EEPROM_DI_1) ? 1 : 0; 496 data = (data << 1) | dataBit; 497 } 498 *value = (u16)data; 499 } 500 501 /* 502 * Caller holds hw_lock. 503 */ 504 static void eeprom_readword(struct ql3_adapter *qdev, 505 u32 eepromAddr, unsigned short *value) 506 { 507 fm93c56a_select(qdev); 508 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr); 509 fm93c56a_datain(qdev, value); 510 fm93c56a_deselect(qdev); 511 } 512 513 static void ql_set_mac_addr(struct net_device *ndev, u16 *addr) 514 { 515 __le16 *p = (__le16 *)ndev->dev_addr; 516 p[0] = cpu_to_le16(addr[0]); 517 p[1] = cpu_to_le16(addr[1]); 518 p[2] = cpu_to_le16(addr[2]); 519 } 520 521 static int ql_get_nvram_params(struct ql3_adapter *qdev) 522 { 523 u16 *pEEPROMData; 524 u16 checksum = 0; 525 u32 index; 526 unsigned long hw_flags; 527 528 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 529 530 pEEPROMData = (u16 *)&qdev->nvram_data; 531 qdev->eeprom_cmd_data = 0; 532 if (ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK, 533 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * 534 2) << 10)) { 535 pr_err("%s: Failed ql_sem_spinlock()\n", __func__); 536 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 537 return -1; 538 } 539 540 for (index = 0; index < EEPROM_SIZE; index++) { 541 eeprom_readword(qdev, index, pEEPROMData); 542 checksum += *pEEPROMData; 543 pEEPROMData++; 544 } 545 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK); 546 547 if (checksum != 0) { 548 netdev_err(qdev->ndev, "checksum should be zero, is %x!!\n", 549 checksum); 550 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 551 return -1; 552 } 553 554 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 555 return checksum; 556 } 557 558 static const u32 PHYAddr[2] = { 559 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS 560 }; 561 562 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev) 563 { 564 struct ql3xxx_port_registers __iomem *port_regs = 565 qdev->mem_map_registers; 566 u32 temp; 567 int count = 1000; 568 569 while (count) { 570 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg); 571 if (!(temp & MAC_MII_STATUS_BSY)) 572 return 0; 573 udelay(10); 574 count--; 575 } 576 return -1; 577 } 578 579 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev) 580 { 581 struct ql3xxx_port_registers __iomem *port_regs = 582 qdev->mem_map_registers; 583 u32 scanControl; 584 585 if (qdev->numPorts > 1) { 586 /* Auto scan will cycle through multiple ports */ 587 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC; 588 } else { 589 scanControl = MAC_MII_CONTROL_SC; 590 } 591 592 /* 593 * Scan register 1 of PHY/PETBI, 594 * Set up to scan both devices 595 * The autoscan starts from the first register, completes 596 * the last one before rolling over to the first 597 */ 598 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, 599 PHYAddr[0] | MII_SCAN_REGISTER); 600 601 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, 602 (scanControl) | 603 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16)); 604 } 605 606 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev) 607 { 608 u8 ret; 609 struct ql3xxx_port_registers __iomem *port_regs = 610 qdev->mem_map_registers; 611 612 /* See if scan mode is enabled before we turn it off */ 613 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) & 614 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) { 615 /* Scan is enabled */ 616 ret = 1; 617 } else { 618 /* Scan is disabled */ 619 ret = 0; 620 } 621 622 /* 623 * When disabling scan mode you must first change the MII register 624 * address 625 */ 626 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, 627 PHYAddr[0] | MII_SCAN_REGISTER); 628 629 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, 630 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS | 631 MAC_MII_CONTROL_RC) << 16)); 632 633 return ret; 634 } 635 636 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev, 637 u16 regAddr, u16 value, u32 phyAddr) 638 { 639 struct ql3xxx_port_registers __iomem *port_regs = 640 qdev->mem_map_registers; 641 u8 scanWasEnabled; 642 643 scanWasEnabled = ql_mii_disable_scan_mode(qdev); 644 645 if (ql_wait_for_mii_ready(qdev)) { 646 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG); 647 return -1; 648 } 649 650 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, 651 phyAddr | regAddr); 652 653 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value); 654 655 /* Wait for write to complete 9/10/04 SJP */ 656 if (ql_wait_for_mii_ready(qdev)) { 657 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG); 658 return -1; 659 } 660 661 if (scanWasEnabled) 662 ql_mii_enable_scan_mode(qdev); 663 664 return 0; 665 } 666 667 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr, 668 u16 *value, u32 phyAddr) 669 { 670 struct ql3xxx_port_registers __iomem *port_regs = 671 qdev->mem_map_registers; 672 u8 scanWasEnabled; 673 u32 temp; 674 675 scanWasEnabled = ql_mii_disable_scan_mode(qdev); 676 677 if (ql_wait_for_mii_ready(qdev)) { 678 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG); 679 return -1; 680 } 681 682 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, 683 phyAddr | regAddr); 684 685 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, 686 (MAC_MII_CONTROL_RC << 16)); 687 688 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, 689 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC); 690 691 /* Wait for the read to complete */ 692 if (ql_wait_for_mii_ready(qdev)) { 693 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG); 694 return -1; 695 } 696 697 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg); 698 *value = (u16) temp; 699 700 if (scanWasEnabled) 701 ql_mii_enable_scan_mode(qdev); 702 703 return 0; 704 } 705 706 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value) 707 { 708 struct ql3xxx_port_registers __iomem *port_regs = 709 qdev->mem_map_registers; 710 711 ql_mii_disable_scan_mode(qdev); 712 713 if (ql_wait_for_mii_ready(qdev)) { 714 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG); 715 return -1; 716 } 717 718 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, 719 qdev->PHYAddr | regAddr); 720 721 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value); 722 723 /* Wait for write to complete. */ 724 if (ql_wait_for_mii_ready(qdev)) { 725 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG); 726 return -1; 727 } 728 729 ql_mii_enable_scan_mode(qdev); 730 731 return 0; 732 } 733 734 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value) 735 { 736 u32 temp; 737 struct ql3xxx_port_registers __iomem *port_regs = 738 qdev->mem_map_registers; 739 740 ql_mii_disable_scan_mode(qdev); 741 742 if (ql_wait_for_mii_ready(qdev)) { 743 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG); 744 return -1; 745 } 746 747 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, 748 qdev->PHYAddr | regAddr); 749 750 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, 751 (MAC_MII_CONTROL_RC << 16)); 752 753 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, 754 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC); 755 756 /* Wait for the read to complete */ 757 if (ql_wait_for_mii_ready(qdev)) { 758 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG); 759 return -1; 760 } 761 762 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg); 763 *value = (u16) temp; 764 765 ql_mii_enable_scan_mode(qdev); 766 767 return 0; 768 } 769 770 static void ql_petbi_reset(struct ql3_adapter *qdev) 771 { 772 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET); 773 } 774 775 static void ql_petbi_start_neg(struct ql3_adapter *qdev) 776 { 777 u16 reg; 778 779 /* Enable Auto-negotiation sense */ 780 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, ®); 781 reg |= PETBI_TBI_AUTO_SENSE; 782 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg); 783 784 ql_mii_write_reg(qdev, PETBI_NEG_ADVER, 785 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX); 786 787 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, 788 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG | 789 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000); 790 791 } 792 793 static void ql_petbi_reset_ex(struct ql3_adapter *qdev) 794 { 795 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET, 796 PHYAddr[qdev->mac_index]); 797 } 798 799 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev) 800 { 801 u16 reg; 802 803 /* Enable Auto-negotiation sense */ 804 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®, 805 PHYAddr[qdev->mac_index]); 806 reg |= PETBI_TBI_AUTO_SENSE; 807 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, 808 PHYAddr[qdev->mac_index]); 809 810 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER, 811 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, 812 PHYAddr[qdev->mac_index]); 813 814 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, 815 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG | 816 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000, 817 PHYAddr[qdev->mac_index]); 818 } 819 820 static void ql_petbi_init(struct ql3_adapter *qdev) 821 { 822 ql_petbi_reset(qdev); 823 ql_petbi_start_neg(qdev); 824 } 825 826 static void ql_petbi_init_ex(struct ql3_adapter *qdev) 827 { 828 ql_petbi_reset_ex(qdev); 829 ql_petbi_start_neg_ex(qdev); 830 } 831 832 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev) 833 { 834 u16 reg; 835 836 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, ®) < 0) 837 return 0; 838 839 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE; 840 } 841 842 static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr) 843 { 844 netdev_info(qdev->ndev, "enabling Agere specific PHY\n"); 845 /* power down device bit 11 = 1 */ 846 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr); 847 /* enable diagnostic mode bit 2 = 1 */ 848 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr); 849 /* 1000MB amplitude adjust (see Agere errata) */ 850 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr); 851 /* 1000MB amplitude adjust (see Agere errata) */ 852 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr); 853 /* 100MB amplitude adjust (see Agere errata) */ 854 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr); 855 /* 100MB amplitude adjust (see Agere errata) */ 856 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr); 857 /* 10MB amplitude adjust (see Agere errata) */ 858 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr); 859 /* 10MB amplitude adjust (see Agere errata) */ 860 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr); 861 /* point to hidden reg 0x2806 */ 862 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr); 863 /* Write new PHYAD w/bit 5 set */ 864 ql_mii_write_reg_ex(qdev, 0x11, 865 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr); 866 /* 867 * Disable diagnostic mode bit 2 = 0 868 * Power up device bit 11 = 0 869 * Link up (on) and activity (blink) 870 */ 871 ql_mii_write_reg(qdev, 0x12, 0x840a); 872 ql_mii_write_reg(qdev, 0x00, 0x1140); 873 ql_mii_write_reg(qdev, 0x1c, 0xfaf0); 874 } 875 876 static enum PHY_DEVICE_TYPE getPhyType(struct ql3_adapter *qdev, 877 u16 phyIdReg0, u16 phyIdReg1) 878 { 879 enum PHY_DEVICE_TYPE result = PHY_TYPE_UNKNOWN; 880 u32 oui; 881 u16 model; 882 int i; 883 884 if (phyIdReg0 == 0xffff) 885 return result; 886 887 if (phyIdReg1 == 0xffff) 888 return result; 889 890 /* oui is split between two registers */ 891 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10); 892 893 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4; 894 895 /* Scan table for this PHY */ 896 for (i = 0; i < MAX_PHY_DEV_TYPES; i++) { 897 if ((oui == PHY_DEVICES[i].phyIdOUI) && 898 (model == PHY_DEVICES[i].phyIdModel)) { 899 netdev_info(qdev->ndev, "Phy: %s\n", 900 PHY_DEVICES[i].name); 901 result = PHY_DEVICES[i].phyDevice; 902 break; 903 } 904 } 905 906 return result; 907 } 908 909 static int ql_phy_get_speed(struct ql3_adapter *qdev) 910 { 911 u16 reg; 912 913 switch (qdev->phyType) { 914 case PHY_AGERE_ET1011C: { 915 if (ql_mii_read_reg(qdev, 0x1A, ®) < 0) 916 return 0; 917 918 reg = (reg >> 8) & 3; 919 break; 920 } 921 default: 922 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0) 923 return 0; 924 925 reg = (((reg & 0x18) >> 3) & 3); 926 } 927 928 switch (reg) { 929 case 2: 930 return SPEED_1000; 931 case 1: 932 return SPEED_100; 933 case 0: 934 return SPEED_10; 935 default: 936 return -1; 937 } 938 } 939 940 static int ql_is_full_dup(struct ql3_adapter *qdev) 941 { 942 u16 reg; 943 944 switch (qdev->phyType) { 945 case PHY_AGERE_ET1011C: { 946 if (ql_mii_read_reg(qdev, 0x1A, ®)) 947 return 0; 948 949 return ((reg & 0x0080) && (reg & 0x1000)) != 0; 950 } 951 case PHY_VITESSE_VSC8211: 952 default: { 953 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0) 954 return 0; 955 return (reg & PHY_AUX_DUPLEX_STAT) != 0; 956 } 957 } 958 } 959 960 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev) 961 { 962 u16 reg; 963 964 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, ®) < 0) 965 return 0; 966 967 return (reg & PHY_NEG_PAUSE) != 0; 968 } 969 970 static int PHY_Setup(struct ql3_adapter *qdev) 971 { 972 u16 reg1; 973 u16 reg2; 974 bool agereAddrChangeNeeded = false; 975 u32 miiAddr = 0; 976 int err; 977 978 /* Determine the PHY we are using by reading the ID's */ 979 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, ®1); 980 if (err != 0) { 981 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_0_REG\n"); 982 return err; 983 } 984 985 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, ®2); 986 if (err != 0) { 987 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG\n"); 988 return err; 989 } 990 991 /* Check if we have a Agere PHY */ 992 if ((reg1 == 0xffff) || (reg2 == 0xffff)) { 993 994 /* Determine which MII address we should be using 995 determined by the index of the card */ 996 if (qdev->mac_index == 0) 997 miiAddr = MII_AGERE_ADDR_1; 998 else 999 miiAddr = MII_AGERE_ADDR_2; 1000 1001 err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, ®1, miiAddr); 1002 if (err != 0) { 1003 netdev_err(qdev->ndev, 1004 "Could not read from reg PHY_ID_0_REG after Agere detected\n"); 1005 return err; 1006 } 1007 1008 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, ®2, miiAddr); 1009 if (err != 0) { 1010 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG after Agere detected\n"); 1011 return err; 1012 } 1013 1014 /* We need to remember to initialize the Agere PHY */ 1015 agereAddrChangeNeeded = true; 1016 } 1017 1018 /* Determine the particular PHY we have on board to apply 1019 PHY specific initializations */ 1020 qdev->phyType = getPhyType(qdev, reg1, reg2); 1021 1022 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) { 1023 /* need this here so address gets changed */ 1024 phyAgereSpecificInit(qdev, miiAddr); 1025 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) { 1026 netdev_err(qdev->ndev, "PHY is unknown\n"); 1027 return -EIO; 1028 } 1029 1030 return 0; 1031 } 1032 1033 /* 1034 * Caller holds hw_lock. 1035 */ 1036 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable) 1037 { 1038 struct ql3xxx_port_registers __iomem *port_regs = 1039 qdev->mem_map_registers; 1040 u32 value; 1041 1042 if (enable) 1043 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16)); 1044 else 1045 value = (MAC_CONFIG_REG_PE << 16); 1046 1047 if (qdev->mac_index) 1048 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value); 1049 else 1050 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value); 1051 } 1052 1053 /* 1054 * Caller holds hw_lock. 1055 */ 1056 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable) 1057 { 1058 struct ql3xxx_port_registers __iomem *port_regs = 1059 qdev->mem_map_registers; 1060 u32 value; 1061 1062 if (enable) 1063 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16)); 1064 else 1065 value = (MAC_CONFIG_REG_SR << 16); 1066 1067 if (qdev->mac_index) 1068 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value); 1069 else 1070 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value); 1071 } 1072 1073 /* 1074 * Caller holds hw_lock. 1075 */ 1076 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable) 1077 { 1078 struct ql3xxx_port_registers __iomem *port_regs = 1079 qdev->mem_map_registers; 1080 u32 value; 1081 1082 if (enable) 1083 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16)); 1084 else 1085 value = (MAC_CONFIG_REG_GM << 16); 1086 1087 if (qdev->mac_index) 1088 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value); 1089 else 1090 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value); 1091 } 1092 1093 /* 1094 * Caller holds hw_lock. 1095 */ 1096 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable) 1097 { 1098 struct ql3xxx_port_registers __iomem *port_regs = 1099 qdev->mem_map_registers; 1100 u32 value; 1101 1102 if (enable) 1103 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16)); 1104 else 1105 value = (MAC_CONFIG_REG_FD << 16); 1106 1107 if (qdev->mac_index) 1108 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value); 1109 else 1110 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value); 1111 } 1112 1113 /* 1114 * Caller holds hw_lock. 1115 */ 1116 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable) 1117 { 1118 struct ql3xxx_port_registers __iomem *port_regs = 1119 qdev->mem_map_registers; 1120 u32 value; 1121 1122 if (enable) 1123 value = 1124 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) | 1125 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16)); 1126 else 1127 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16); 1128 1129 if (qdev->mac_index) 1130 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value); 1131 else 1132 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value); 1133 } 1134 1135 /* 1136 * Caller holds hw_lock. 1137 */ 1138 static int ql_is_fiber(struct ql3_adapter *qdev) 1139 { 1140 struct ql3xxx_port_registers __iomem *port_regs = 1141 qdev->mem_map_registers; 1142 u32 bitToCheck = 0; 1143 u32 temp; 1144 1145 switch (qdev->mac_index) { 1146 case 0: 1147 bitToCheck = PORT_STATUS_SM0; 1148 break; 1149 case 1: 1150 bitToCheck = PORT_STATUS_SM1; 1151 break; 1152 } 1153 1154 temp = ql_read_page0_reg(qdev, &port_regs->portStatus); 1155 return (temp & bitToCheck) != 0; 1156 } 1157 1158 static int ql_is_auto_cfg(struct ql3_adapter *qdev) 1159 { 1160 u16 reg; 1161 ql_mii_read_reg(qdev, 0x00, ®); 1162 return (reg & 0x1000) != 0; 1163 } 1164 1165 /* 1166 * Caller holds hw_lock. 1167 */ 1168 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev) 1169 { 1170 struct ql3xxx_port_registers __iomem *port_regs = 1171 qdev->mem_map_registers; 1172 u32 bitToCheck = 0; 1173 u32 temp; 1174 1175 switch (qdev->mac_index) { 1176 case 0: 1177 bitToCheck = PORT_STATUS_AC0; 1178 break; 1179 case 1: 1180 bitToCheck = PORT_STATUS_AC1; 1181 break; 1182 } 1183 1184 temp = ql_read_page0_reg(qdev, &port_regs->portStatus); 1185 if (temp & bitToCheck) { 1186 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate complete\n"); 1187 return 1; 1188 } 1189 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate incomplete\n"); 1190 return 0; 1191 } 1192 1193 /* 1194 * ql_is_neg_pause() returns 1 if pause was negotiated to be on 1195 */ 1196 static int ql_is_neg_pause(struct ql3_adapter *qdev) 1197 { 1198 if (ql_is_fiber(qdev)) 1199 return ql_is_petbi_neg_pause(qdev); 1200 else 1201 return ql_is_phy_neg_pause(qdev); 1202 } 1203 1204 static int ql_auto_neg_error(struct ql3_adapter *qdev) 1205 { 1206 struct ql3xxx_port_registers __iomem *port_regs = 1207 qdev->mem_map_registers; 1208 u32 bitToCheck = 0; 1209 u32 temp; 1210 1211 switch (qdev->mac_index) { 1212 case 0: 1213 bitToCheck = PORT_STATUS_AE0; 1214 break; 1215 case 1: 1216 bitToCheck = PORT_STATUS_AE1; 1217 break; 1218 } 1219 temp = ql_read_page0_reg(qdev, &port_regs->portStatus); 1220 return (temp & bitToCheck) != 0; 1221 } 1222 1223 static u32 ql_get_link_speed(struct ql3_adapter *qdev) 1224 { 1225 if (ql_is_fiber(qdev)) 1226 return SPEED_1000; 1227 else 1228 return ql_phy_get_speed(qdev); 1229 } 1230 1231 static int ql_is_link_full_dup(struct ql3_adapter *qdev) 1232 { 1233 if (ql_is_fiber(qdev)) 1234 return 1; 1235 else 1236 return ql_is_full_dup(qdev); 1237 } 1238 1239 /* 1240 * Caller holds hw_lock. 1241 */ 1242 static int ql_link_down_detect(struct ql3_adapter *qdev) 1243 { 1244 struct ql3xxx_port_registers __iomem *port_regs = 1245 qdev->mem_map_registers; 1246 u32 bitToCheck = 0; 1247 u32 temp; 1248 1249 switch (qdev->mac_index) { 1250 case 0: 1251 bitToCheck = ISP_CONTROL_LINK_DN_0; 1252 break; 1253 case 1: 1254 bitToCheck = ISP_CONTROL_LINK_DN_1; 1255 break; 1256 } 1257 1258 temp = 1259 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus); 1260 return (temp & bitToCheck) != 0; 1261 } 1262 1263 /* 1264 * Caller holds hw_lock. 1265 */ 1266 static int ql_link_down_detect_clear(struct ql3_adapter *qdev) 1267 { 1268 struct ql3xxx_port_registers __iomem *port_regs = 1269 qdev->mem_map_registers; 1270 1271 switch (qdev->mac_index) { 1272 case 0: 1273 ql_write_common_reg(qdev, 1274 &port_regs->CommonRegs.ispControlStatus, 1275 (ISP_CONTROL_LINK_DN_0) | 1276 (ISP_CONTROL_LINK_DN_0 << 16)); 1277 break; 1278 1279 case 1: 1280 ql_write_common_reg(qdev, 1281 &port_regs->CommonRegs.ispControlStatus, 1282 (ISP_CONTROL_LINK_DN_1) | 1283 (ISP_CONTROL_LINK_DN_1 << 16)); 1284 break; 1285 1286 default: 1287 return 1; 1288 } 1289 1290 return 0; 1291 } 1292 1293 /* 1294 * Caller holds hw_lock. 1295 */ 1296 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev) 1297 { 1298 struct ql3xxx_port_registers __iomem *port_regs = 1299 qdev->mem_map_registers; 1300 u32 bitToCheck = 0; 1301 u32 temp; 1302 1303 switch (qdev->mac_index) { 1304 case 0: 1305 bitToCheck = PORT_STATUS_F1_ENABLED; 1306 break; 1307 case 1: 1308 bitToCheck = PORT_STATUS_F3_ENABLED; 1309 break; 1310 default: 1311 break; 1312 } 1313 1314 temp = ql_read_page0_reg(qdev, &port_regs->portStatus); 1315 if (temp & bitToCheck) { 1316 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, 1317 "not link master\n"); 1318 return 0; 1319 } 1320 1321 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, "link master\n"); 1322 return 1; 1323 } 1324 1325 static void ql_phy_reset_ex(struct ql3_adapter *qdev) 1326 { 1327 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, 1328 PHYAddr[qdev->mac_index]); 1329 } 1330 1331 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev) 1332 { 1333 u16 reg; 1334 u16 portConfiguration; 1335 1336 if (qdev->phyType == PHY_AGERE_ET1011C) 1337 ql_mii_write_reg(qdev, 0x13, 0x0000); 1338 /* turn off external loopback */ 1339 1340 if (qdev->mac_index == 0) 1341 portConfiguration = 1342 qdev->nvram_data.macCfg_port0.portConfiguration; 1343 else 1344 portConfiguration = 1345 qdev->nvram_data.macCfg_port1.portConfiguration; 1346 1347 /* Some HBA's in the field are set to 0 and they need to 1348 be reinterpreted with a default value */ 1349 if (portConfiguration == 0) 1350 portConfiguration = PORT_CONFIG_DEFAULT; 1351 1352 /* Set the 1000 advertisements */ 1353 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, ®, 1354 PHYAddr[qdev->mac_index]); 1355 reg &= ~PHY_GIG_ALL_PARAMS; 1356 1357 if (portConfiguration & PORT_CONFIG_1000MB_SPEED) { 1358 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) 1359 reg |= PHY_GIG_ADV_1000F; 1360 else 1361 reg |= PHY_GIG_ADV_1000H; 1362 } 1363 1364 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg, 1365 PHYAddr[qdev->mac_index]); 1366 1367 /* Set the 10/100 & pause negotiation advertisements */ 1368 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, ®, 1369 PHYAddr[qdev->mac_index]); 1370 reg &= ~PHY_NEG_ALL_PARAMS; 1371 1372 if (portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED) 1373 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE; 1374 1375 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) { 1376 if (portConfiguration & PORT_CONFIG_100MB_SPEED) 1377 reg |= PHY_NEG_ADV_100F; 1378 1379 if (portConfiguration & PORT_CONFIG_10MB_SPEED) 1380 reg |= PHY_NEG_ADV_10F; 1381 } 1382 1383 if (portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) { 1384 if (portConfiguration & PORT_CONFIG_100MB_SPEED) 1385 reg |= PHY_NEG_ADV_100H; 1386 1387 if (portConfiguration & PORT_CONFIG_10MB_SPEED) 1388 reg |= PHY_NEG_ADV_10H; 1389 } 1390 1391 if (portConfiguration & PORT_CONFIG_1000MB_SPEED) 1392 reg |= 1; 1393 1394 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg, 1395 PHYAddr[qdev->mac_index]); 1396 1397 ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]); 1398 1399 ql_mii_write_reg_ex(qdev, CONTROL_REG, 1400 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG, 1401 PHYAddr[qdev->mac_index]); 1402 } 1403 1404 static void ql_phy_init_ex(struct ql3_adapter *qdev) 1405 { 1406 ql_phy_reset_ex(qdev); 1407 PHY_Setup(qdev); 1408 ql_phy_start_neg_ex(qdev); 1409 } 1410 1411 /* 1412 * Caller holds hw_lock. 1413 */ 1414 static u32 ql_get_link_state(struct ql3_adapter *qdev) 1415 { 1416 struct ql3xxx_port_registers __iomem *port_regs = 1417 qdev->mem_map_registers; 1418 u32 bitToCheck = 0; 1419 u32 temp, linkState; 1420 1421 switch (qdev->mac_index) { 1422 case 0: 1423 bitToCheck = PORT_STATUS_UP0; 1424 break; 1425 case 1: 1426 bitToCheck = PORT_STATUS_UP1; 1427 break; 1428 } 1429 1430 temp = ql_read_page0_reg(qdev, &port_regs->portStatus); 1431 if (temp & bitToCheck) 1432 linkState = LS_UP; 1433 else 1434 linkState = LS_DOWN; 1435 1436 return linkState; 1437 } 1438 1439 static int ql_port_start(struct ql3_adapter *qdev) 1440 { 1441 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, 1442 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * 1443 2) << 7)) { 1444 netdev_err(qdev->ndev, "Could not get hw lock for GIO\n"); 1445 return -1; 1446 } 1447 1448 if (ql_is_fiber(qdev)) { 1449 ql_petbi_init(qdev); 1450 } else { 1451 /* Copper port */ 1452 ql_phy_init_ex(qdev); 1453 } 1454 1455 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); 1456 return 0; 1457 } 1458 1459 static int ql_finish_auto_neg(struct ql3_adapter *qdev) 1460 { 1461 1462 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, 1463 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * 1464 2) << 7)) 1465 return -1; 1466 1467 if (!ql_auto_neg_error(qdev)) { 1468 if (test_bit(QL_LINK_MASTER, &qdev->flags)) { 1469 /* configure the MAC */ 1470 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, 1471 "Configuring link\n"); 1472 ql_mac_cfg_soft_reset(qdev, 1); 1473 ql_mac_cfg_gig(qdev, 1474 (ql_get_link_speed 1475 (qdev) == 1476 SPEED_1000)); 1477 ql_mac_cfg_full_dup(qdev, 1478 ql_is_link_full_dup 1479 (qdev)); 1480 ql_mac_cfg_pause(qdev, 1481 ql_is_neg_pause 1482 (qdev)); 1483 ql_mac_cfg_soft_reset(qdev, 0); 1484 1485 /* enable the MAC */ 1486 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, 1487 "Enabling mac\n"); 1488 ql_mac_enable(qdev, 1); 1489 } 1490 1491 qdev->port_link_state = LS_UP; 1492 netif_start_queue(qdev->ndev); 1493 netif_carrier_on(qdev->ndev); 1494 netif_info(qdev, link, qdev->ndev, 1495 "Link is up at %d Mbps, %s duplex\n", 1496 ql_get_link_speed(qdev), 1497 ql_is_link_full_dup(qdev) ? "full" : "half"); 1498 1499 } else { /* Remote error detected */ 1500 1501 if (test_bit(QL_LINK_MASTER, &qdev->flags)) { 1502 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, 1503 "Remote error detected. Calling ql_port_start()\n"); 1504 /* 1505 * ql_port_start() is shared code and needs 1506 * to lock the PHY on it's own. 1507 */ 1508 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); 1509 if (ql_port_start(qdev)) /* Restart port */ 1510 return -1; 1511 return 0; 1512 } 1513 } 1514 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); 1515 return 0; 1516 } 1517 1518 static void ql_link_state_machine_work(struct work_struct *work) 1519 { 1520 struct ql3_adapter *qdev = 1521 container_of(work, struct ql3_adapter, link_state_work.work); 1522 1523 u32 curr_link_state; 1524 unsigned long hw_flags; 1525 1526 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 1527 1528 curr_link_state = ql_get_link_state(qdev); 1529 1530 if (test_bit(QL_RESET_ACTIVE, &qdev->flags)) { 1531 netif_info(qdev, link, qdev->ndev, 1532 "Reset in progress, skip processing link state\n"); 1533 1534 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 1535 1536 /* Restart timer on 2 second interval. */ 1537 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1); 1538 1539 return; 1540 } 1541 1542 switch (qdev->port_link_state) { 1543 default: 1544 if (test_bit(QL_LINK_MASTER, &qdev->flags)) 1545 ql_port_start(qdev); 1546 qdev->port_link_state = LS_DOWN; 1547 /* Fall Through */ 1548 1549 case LS_DOWN: 1550 if (curr_link_state == LS_UP) { 1551 netif_info(qdev, link, qdev->ndev, "Link is up\n"); 1552 if (ql_is_auto_neg_complete(qdev)) 1553 ql_finish_auto_neg(qdev); 1554 1555 if (qdev->port_link_state == LS_UP) 1556 ql_link_down_detect_clear(qdev); 1557 1558 qdev->port_link_state = LS_UP; 1559 } 1560 break; 1561 1562 case LS_UP: 1563 /* 1564 * See if the link is currently down or went down and came 1565 * back up 1566 */ 1567 if (curr_link_state == LS_DOWN) { 1568 netif_info(qdev, link, qdev->ndev, "Link is down\n"); 1569 qdev->port_link_state = LS_DOWN; 1570 } 1571 if (ql_link_down_detect(qdev)) 1572 qdev->port_link_state = LS_DOWN; 1573 break; 1574 } 1575 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 1576 1577 /* Restart timer on 2 second interval. */ 1578 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1); 1579 } 1580 1581 /* 1582 * Caller must take hw_lock and QL_PHY_GIO_SEM. 1583 */ 1584 static void ql_get_phy_owner(struct ql3_adapter *qdev) 1585 { 1586 if (ql_this_adapter_controls_port(qdev)) 1587 set_bit(QL_LINK_MASTER, &qdev->flags); 1588 else 1589 clear_bit(QL_LINK_MASTER, &qdev->flags); 1590 } 1591 1592 /* 1593 * Caller must take hw_lock and QL_PHY_GIO_SEM. 1594 */ 1595 static void ql_init_scan_mode(struct ql3_adapter *qdev) 1596 { 1597 ql_mii_enable_scan_mode(qdev); 1598 1599 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) { 1600 if (ql_this_adapter_controls_port(qdev)) 1601 ql_petbi_init_ex(qdev); 1602 } else { 1603 if (ql_this_adapter_controls_port(qdev)) 1604 ql_phy_init_ex(qdev); 1605 } 1606 } 1607 1608 /* 1609 * MII_Setup needs to be called before taking the PHY out of reset 1610 * so that the management interface clock speed can be set properly. 1611 * It would be better if we had a way to disable MDC until after the 1612 * PHY is out of reset, but we don't have that capability. 1613 */ 1614 static int ql_mii_setup(struct ql3_adapter *qdev) 1615 { 1616 u32 reg; 1617 struct ql3xxx_port_registers __iomem *port_regs = 1618 qdev->mem_map_registers; 1619 1620 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, 1621 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * 1622 2) << 7)) 1623 return -1; 1624 1625 if (qdev->device_id == QL3032_DEVICE_ID) 1626 ql_write_page0_reg(qdev, 1627 &port_regs->macMIIMgmtControlReg, 0x0f00000); 1628 1629 /* Divide 125MHz clock by 28 to meet PHY timing requirements */ 1630 reg = MAC_MII_CONTROL_CLK_SEL_DIV28; 1631 1632 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, 1633 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16)); 1634 1635 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); 1636 return 0; 1637 } 1638 1639 #define SUPPORTED_OPTICAL_MODES (SUPPORTED_1000baseT_Full | \ 1640 SUPPORTED_FIBRE | \ 1641 SUPPORTED_Autoneg) 1642 #define SUPPORTED_TP_MODES (SUPPORTED_10baseT_Half | \ 1643 SUPPORTED_10baseT_Full | \ 1644 SUPPORTED_100baseT_Half | \ 1645 SUPPORTED_100baseT_Full | \ 1646 SUPPORTED_1000baseT_Half | \ 1647 SUPPORTED_1000baseT_Full | \ 1648 SUPPORTED_Autoneg | \ 1649 SUPPORTED_TP) \ 1650 1651 static u32 ql_supported_modes(struct ql3_adapter *qdev) 1652 { 1653 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) 1654 return SUPPORTED_OPTICAL_MODES; 1655 1656 return SUPPORTED_TP_MODES; 1657 } 1658 1659 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev) 1660 { 1661 int status; 1662 unsigned long hw_flags; 1663 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 1664 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, 1665 (QL_RESOURCE_BITS_BASE_CODE | 1666 (qdev->mac_index) * 2) << 7)) { 1667 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 1668 return 0; 1669 } 1670 status = ql_is_auto_cfg(qdev); 1671 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); 1672 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 1673 return status; 1674 } 1675 1676 static u32 ql_get_speed(struct ql3_adapter *qdev) 1677 { 1678 u32 status; 1679 unsigned long hw_flags; 1680 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 1681 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, 1682 (QL_RESOURCE_BITS_BASE_CODE | 1683 (qdev->mac_index) * 2) << 7)) { 1684 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 1685 return 0; 1686 } 1687 status = ql_get_link_speed(qdev); 1688 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); 1689 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 1690 return status; 1691 } 1692 1693 static int ql_get_full_dup(struct ql3_adapter *qdev) 1694 { 1695 int status; 1696 unsigned long hw_flags; 1697 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 1698 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, 1699 (QL_RESOURCE_BITS_BASE_CODE | 1700 (qdev->mac_index) * 2) << 7)) { 1701 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 1702 return 0; 1703 } 1704 status = ql_is_link_full_dup(qdev); 1705 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); 1706 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 1707 return status; 1708 } 1709 1710 static int ql_get_link_ksettings(struct net_device *ndev, 1711 struct ethtool_link_ksettings *cmd) 1712 { 1713 struct ql3_adapter *qdev = netdev_priv(ndev); 1714 u32 supported, advertising; 1715 1716 supported = ql_supported_modes(qdev); 1717 1718 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) { 1719 cmd->base.port = PORT_FIBRE; 1720 } else { 1721 cmd->base.port = PORT_TP; 1722 cmd->base.phy_address = qdev->PHYAddr; 1723 } 1724 advertising = ql_supported_modes(qdev); 1725 cmd->base.autoneg = ql_get_auto_cfg_status(qdev); 1726 cmd->base.speed = ql_get_speed(qdev); 1727 cmd->base.duplex = ql_get_full_dup(qdev); 1728 1729 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 1730 supported); 1731 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 1732 advertising); 1733 1734 return 0; 1735 } 1736 1737 static void ql_get_drvinfo(struct net_device *ndev, 1738 struct ethtool_drvinfo *drvinfo) 1739 { 1740 struct ql3_adapter *qdev = netdev_priv(ndev); 1741 strlcpy(drvinfo->driver, ql3xxx_driver_name, sizeof(drvinfo->driver)); 1742 strlcpy(drvinfo->version, ql3xxx_driver_version, 1743 sizeof(drvinfo->version)); 1744 strlcpy(drvinfo->bus_info, pci_name(qdev->pdev), 1745 sizeof(drvinfo->bus_info)); 1746 } 1747 1748 static u32 ql_get_msglevel(struct net_device *ndev) 1749 { 1750 struct ql3_adapter *qdev = netdev_priv(ndev); 1751 return qdev->msg_enable; 1752 } 1753 1754 static void ql_set_msglevel(struct net_device *ndev, u32 value) 1755 { 1756 struct ql3_adapter *qdev = netdev_priv(ndev); 1757 qdev->msg_enable = value; 1758 } 1759 1760 static void ql_get_pauseparam(struct net_device *ndev, 1761 struct ethtool_pauseparam *pause) 1762 { 1763 struct ql3_adapter *qdev = netdev_priv(ndev); 1764 struct ql3xxx_port_registers __iomem *port_regs = 1765 qdev->mem_map_registers; 1766 1767 u32 reg; 1768 if (qdev->mac_index == 0) 1769 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg); 1770 else 1771 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg); 1772 1773 pause->autoneg = ql_get_auto_cfg_status(qdev); 1774 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2; 1775 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1; 1776 } 1777 1778 static const struct ethtool_ops ql3xxx_ethtool_ops = { 1779 .get_drvinfo = ql_get_drvinfo, 1780 .get_link = ethtool_op_get_link, 1781 .get_msglevel = ql_get_msglevel, 1782 .set_msglevel = ql_set_msglevel, 1783 .get_pauseparam = ql_get_pauseparam, 1784 .get_link_ksettings = ql_get_link_ksettings, 1785 }; 1786 1787 static int ql_populate_free_queue(struct ql3_adapter *qdev) 1788 { 1789 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head; 1790 dma_addr_t map; 1791 int err; 1792 1793 while (lrg_buf_cb) { 1794 if (!lrg_buf_cb->skb) { 1795 lrg_buf_cb->skb = 1796 netdev_alloc_skb(qdev->ndev, 1797 qdev->lrg_buffer_len); 1798 if (unlikely(!lrg_buf_cb->skb)) { 1799 netdev_printk(KERN_DEBUG, qdev->ndev, 1800 "Failed netdev_alloc_skb()\n"); 1801 break; 1802 } else { 1803 /* 1804 * We save some space to copy the ethhdr from 1805 * first buffer 1806 */ 1807 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE); 1808 map = pci_map_single(qdev->pdev, 1809 lrg_buf_cb->skb->data, 1810 qdev->lrg_buffer_len - 1811 QL_HEADER_SPACE, 1812 PCI_DMA_FROMDEVICE); 1813 1814 err = pci_dma_mapping_error(qdev->pdev, map); 1815 if (err) { 1816 netdev_err(qdev->ndev, 1817 "PCI mapping failed with error: %d\n", 1818 err); 1819 dev_kfree_skb(lrg_buf_cb->skb); 1820 lrg_buf_cb->skb = NULL; 1821 break; 1822 } 1823 1824 1825 lrg_buf_cb->buf_phy_addr_low = 1826 cpu_to_le32(LS_64BITS(map)); 1827 lrg_buf_cb->buf_phy_addr_high = 1828 cpu_to_le32(MS_64BITS(map)); 1829 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map); 1830 dma_unmap_len_set(lrg_buf_cb, maplen, 1831 qdev->lrg_buffer_len - 1832 QL_HEADER_SPACE); 1833 --qdev->lrg_buf_skb_check; 1834 if (!qdev->lrg_buf_skb_check) 1835 return 1; 1836 } 1837 } 1838 lrg_buf_cb = lrg_buf_cb->next; 1839 } 1840 return 0; 1841 } 1842 1843 /* 1844 * Caller holds hw_lock. 1845 */ 1846 static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev) 1847 { 1848 struct ql3xxx_port_registers __iomem *port_regs = 1849 qdev->mem_map_registers; 1850 1851 if (qdev->small_buf_release_cnt >= 16) { 1852 while (qdev->small_buf_release_cnt >= 16) { 1853 qdev->small_buf_q_producer_index++; 1854 1855 if (qdev->small_buf_q_producer_index == 1856 NUM_SBUFQ_ENTRIES) 1857 qdev->small_buf_q_producer_index = 0; 1858 qdev->small_buf_release_cnt -= 8; 1859 } 1860 wmb(); 1861 writel(qdev->small_buf_q_producer_index, 1862 &port_regs->CommonRegs.rxSmallQProducerIndex); 1863 } 1864 } 1865 1866 /* 1867 * Caller holds hw_lock. 1868 */ 1869 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev) 1870 { 1871 struct bufq_addr_element *lrg_buf_q_ele; 1872 int i; 1873 struct ql_rcv_buf_cb *lrg_buf_cb; 1874 struct ql3xxx_port_registers __iomem *port_regs = 1875 qdev->mem_map_registers; 1876 1877 if ((qdev->lrg_buf_free_count >= 8) && 1878 (qdev->lrg_buf_release_cnt >= 16)) { 1879 1880 if (qdev->lrg_buf_skb_check) 1881 if (!ql_populate_free_queue(qdev)) 1882 return; 1883 1884 lrg_buf_q_ele = qdev->lrg_buf_next_free; 1885 1886 while ((qdev->lrg_buf_release_cnt >= 16) && 1887 (qdev->lrg_buf_free_count >= 8)) { 1888 1889 for (i = 0; i < 8; i++) { 1890 lrg_buf_cb = 1891 ql_get_from_lrg_buf_free_list(qdev); 1892 lrg_buf_q_ele->addr_high = 1893 lrg_buf_cb->buf_phy_addr_high; 1894 lrg_buf_q_ele->addr_low = 1895 lrg_buf_cb->buf_phy_addr_low; 1896 lrg_buf_q_ele++; 1897 1898 qdev->lrg_buf_release_cnt--; 1899 } 1900 1901 qdev->lrg_buf_q_producer_index++; 1902 1903 if (qdev->lrg_buf_q_producer_index == 1904 qdev->num_lbufq_entries) 1905 qdev->lrg_buf_q_producer_index = 0; 1906 1907 if (qdev->lrg_buf_q_producer_index == 1908 (qdev->num_lbufq_entries - 1)) { 1909 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr; 1910 } 1911 } 1912 wmb(); 1913 qdev->lrg_buf_next_free = lrg_buf_q_ele; 1914 writel(qdev->lrg_buf_q_producer_index, 1915 &port_regs->CommonRegs.rxLargeQProducerIndex); 1916 } 1917 } 1918 1919 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev, 1920 struct ob_mac_iocb_rsp *mac_rsp) 1921 { 1922 struct ql_tx_buf_cb *tx_cb; 1923 int i; 1924 1925 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) { 1926 netdev_warn(qdev->ndev, 1927 "Frame too short but it was padded and sent\n"); 1928 } 1929 1930 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id]; 1931 1932 /* Check the transmit response flags for any errors */ 1933 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) { 1934 netdev_err(qdev->ndev, 1935 "Frame too short to be legal, frame not sent\n"); 1936 1937 qdev->ndev->stats.tx_errors++; 1938 goto frame_not_sent; 1939 } 1940 1941 if (tx_cb->seg_count == 0) { 1942 netdev_err(qdev->ndev, "tx_cb->seg_count == 0: %d\n", 1943 mac_rsp->transaction_id); 1944 1945 qdev->ndev->stats.tx_errors++; 1946 goto invalid_seg_count; 1947 } 1948 1949 pci_unmap_single(qdev->pdev, 1950 dma_unmap_addr(&tx_cb->map[0], mapaddr), 1951 dma_unmap_len(&tx_cb->map[0], maplen), 1952 PCI_DMA_TODEVICE); 1953 tx_cb->seg_count--; 1954 if (tx_cb->seg_count) { 1955 for (i = 1; i < tx_cb->seg_count; i++) { 1956 pci_unmap_page(qdev->pdev, 1957 dma_unmap_addr(&tx_cb->map[i], 1958 mapaddr), 1959 dma_unmap_len(&tx_cb->map[i], maplen), 1960 PCI_DMA_TODEVICE); 1961 } 1962 } 1963 qdev->ndev->stats.tx_packets++; 1964 qdev->ndev->stats.tx_bytes += tx_cb->skb->len; 1965 1966 frame_not_sent: 1967 dev_kfree_skb_irq(tx_cb->skb); 1968 tx_cb->skb = NULL; 1969 1970 invalid_seg_count: 1971 atomic_inc(&qdev->tx_count); 1972 } 1973 1974 static void ql_get_sbuf(struct ql3_adapter *qdev) 1975 { 1976 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS) 1977 qdev->small_buf_index = 0; 1978 qdev->small_buf_release_cnt++; 1979 } 1980 1981 static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev) 1982 { 1983 struct ql_rcv_buf_cb *lrg_buf_cb = NULL; 1984 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index]; 1985 qdev->lrg_buf_release_cnt++; 1986 if (++qdev->lrg_buf_index == qdev->num_large_buffers) 1987 qdev->lrg_buf_index = 0; 1988 return lrg_buf_cb; 1989 } 1990 1991 /* 1992 * The difference between 3022 and 3032 for inbound completions: 1993 * 3022 uses two buffers per completion. The first buffer contains 1994 * (some) header info, the second the remainder of the headers plus 1995 * the data. For this chip we reserve some space at the top of the 1996 * receive buffer so that the header info in buffer one can be 1997 * prepended to the buffer two. Buffer two is the sent up while 1998 * buffer one is returned to the hardware to be reused. 1999 * 3032 receives all of it's data and headers in one buffer for a 2000 * simpler process. 3032 also supports checksum verification as 2001 * can be seen in ql_process_macip_rx_intr(). 2002 */ 2003 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev, 2004 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr) 2005 { 2006 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL; 2007 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL; 2008 struct sk_buff *skb; 2009 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length); 2010 2011 /* 2012 * Get the inbound address list (small buffer). 2013 */ 2014 ql_get_sbuf(qdev); 2015 2016 if (qdev->device_id == QL3022_DEVICE_ID) 2017 lrg_buf_cb1 = ql_get_lbuf(qdev); 2018 2019 /* start of second buffer */ 2020 lrg_buf_cb2 = ql_get_lbuf(qdev); 2021 skb = lrg_buf_cb2->skb; 2022 2023 qdev->ndev->stats.rx_packets++; 2024 qdev->ndev->stats.rx_bytes += length; 2025 2026 skb_put(skb, length); 2027 pci_unmap_single(qdev->pdev, 2028 dma_unmap_addr(lrg_buf_cb2, mapaddr), 2029 dma_unmap_len(lrg_buf_cb2, maplen), 2030 PCI_DMA_FROMDEVICE); 2031 prefetch(skb->data); 2032 skb_checksum_none_assert(skb); 2033 skb->protocol = eth_type_trans(skb, qdev->ndev); 2034 2035 napi_gro_receive(&qdev->napi, skb); 2036 lrg_buf_cb2->skb = NULL; 2037 2038 if (qdev->device_id == QL3022_DEVICE_ID) 2039 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1); 2040 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2); 2041 } 2042 2043 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev, 2044 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr) 2045 { 2046 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL; 2047 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL; 2048 struct sk_buff *skb1 = NULL, *skb2; 2049 struct net_device *ndev = qdev->ndev; 2050 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length); 2051 u16 size = 0; 2052 2053 /* 2054 * Get the inbound address list (small buffer). 2055 */ 2056 2057 ql_get_sbuf(qdev); 2058 2059 if (qdev->device_id == QL3022_DEVICE_ID) { 2060 /* start of first buffer on 3022 */ 2061 lrg_buf_cb1 = ql_get_lbuf(qdev); 2062 skb1 = lrg_buf_cb1->skb; 2063 size = ETH_HLEN; 2064 if (*((u16 *) skb1->data) != 0xFFFF) 2065 size += VLAN_ETH_HLEN - ETH_HLEN; 2066 } 2067 2068 /* start of second buffer */ 2069 lrg_buf_cb2 = ql_get_lbuf(qdev); 2070 skb2 = lrg_buf_cb2->skb; 2071 2072 skb_put(skb2, length); /* Just the second buffer length here. */ 2073 pci_unmap_single(qdev->pdev, 2074 dma_unmap_addr(lrg_buf_cb2, mapaddr), 2075 dma_unmap_len(lrg_buf_cb2, maplen), 2076 PCI_DMA_FROMDEVICE); 2077 prefetch(skb2->data); 2078 2079 skb_checksum_none_assert(skb2); 2080 if (qdev->device_id == QL3022_DEVICE_ID) { 2081 /* 2082 * Copy the ethhdr from first buffer to second. This 2083 * is necessary for 3022 IP completions. 2084 */ 2085 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN, 2086 skb_push(skb2, size), size); 2087 } else { 2088 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum); 2089 if (checksum & 2090 (IB_IP_IOCB_RSP_3032_ICE | 2091 IB_IP_IOCB_RSP_3032_CE)) { 2092 netdev_err(ndev, 2093 "%s: Bad checksum for this %s packet, checksum = %x\n", 2094 __func__, 2095 ((checksum & IB_IP_IOCB_RSP_3032_TCP) ? 2096 "TCP" : "UDP"), checksum); 2097 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) || 2098 (checksum & IB_IP_IOCB_RSP_3032_UDP && 2099 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) { 2100 skb2->ip_summed = CHECKSUM_UNNECESSARY; 2101 } 2102 } 2103 skb2->protocol = eth_type_trans(skb2, qdev->ndev); 2104 2105 napi_gro_receive(&qdev->napi, skb2); 2106 ndev->stats.rx_packets++; 2107 ndev->stats.rx_bytes += length; 2108 lrg_buf_cb2->skb = NULL; 2109 2110 if (qdev->device_id == QL3022_DEVICE_ID) 2111 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1); 2112 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2); 2113 } 2114 2115 static int ql_tx_rx_clean(struct ql3_adapter *qdev, int budget) 2116 { 2117 struct net_rsp_iocb *net_rsp; 2118 struct net_device *ndev = qdev->ndev; 2119 int work_done = 0; 2120 2121 /* While there are entries in the completion queue. */ 2122 while ((le32_to_cpu(*(qdev->prsp_producer_index)) != 2123 qdev->rsp_consumer_index) && (work_done < budget)) { 2124 2125 net_rsp = qdev->rsp_current; 2126 rmb(); 2127 /* 2128 * Fix 4032 chip's undocumented "feature" where bit-8 is set 2129 * if the inbound completion is for a VLAN. 2130 */ 2131 if (qdev->device_id == QL3032_DEVICE_ID) 2132 net_rsp->opcode &= 0x7f; 2133 switch (net_rsp->opcode) { 2134 2135 case OPCODE_OB_MAC_IOCB_FN0: 2136 case OPCODE_OB_MAC_IOCB_FN2: 2137 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *) 2138 net_rsp); 2139 break; 2140 2141 case OPCODE_IB_MAC_IOCB: 2142 case OPCODE_IB_3032_MAC_IOCB: 2143 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *) 2144 net_rsp); 2145 work_done++; 2146 break; 2147 2148 case OPCODE_IB_IP_IOCB: 2149 case OPCODE_IB_3032_IP_IOCB: 2150 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *) 2151 net_rsp); 2152 work_done++; 2153 break; 2154 default: { 2155 u32 *tmp = (u32 *)net_rsp; 2156 netdev_err(ndev, 2157 "Hit default case, not handled!\n" 2158 " dropping the packet, opcode = %x\n" 2159 "0x%08lx 0x%08lx 0x%08lx 0x%08lx\n", 2160 net_rsp->opcode, 2161 (unsigned long int)tmp[0], 2162 (unsigned long int)tmp[1], 2163 (unsigned long int)tmp[2], 2164 (unsigned long int)tmp[3]); 2165 } 2166 } 2167 2168 qdev->rsp_consumer_index++; 2169 2170 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) { 2171 qdev->rsp_consumer_index = 0; 2172 qdev->rsp_current = qdev->rsp_q_virt_addr; 2173 } else { 2174 qdev->rsp_current++; 2175 } 2176 2177 } 2178 2179 return work_done; 2180 } 2181 2182 static int ql_poll(struct napi_struct *napi, int budget) 2183 { 2184 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi); 2185 struct ql3xxx_port_registers __iomem *port_regs = 2186 qdev->mem_map_registers; 2187 int work_done; 2188 2189 work_done = ql_tx_rx_clean(qdev, budget); 2190 2191 if (work_done < budget && napi_complete_done(napi, work_done)) { 2192 unsigned long flags; 2193 2194 spin_lock_irqsave(&qdev->hw_lock, flags); 2195 ql_update_small_bufq_prod_index(qdev); 2196 ql_update_lrg_bufq_prod_index(qdev); 2197 writel(qdev->rsp_consumer_index, 2198 &port_regs->CommonRegs.rspQConsumerIndex); 2199 spin_unlock_irqrestore(&qdev->hw_lock, flags); 2200 2201 ql_enable_interrupts(qdev); 2202 } 2203 return work_done; 2204 } 2205 2206 static irqreturn_t ql3xxx_isr(int irq, void *dev_id) 2207 { 2208 2209 struct net_device *ndev = dev_id; 2210 struct ql3_adapter *qdev = netdev_priv(ndev); 2211 struct ql3xxx_port_registers __iomem *port_regs = 2212 qdev->mem_map_registers; 2213 u32 value; 2214 int handled = 1; 2215 u32 var; 2216 2217 value = ql_read_common_reg_l(qdev, 2218 &port_regs->CommonRegs.ispControlStatus); 2219 2220 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) { 2221 spin_lock(&qdev->adapter_lock); 2222 netif_stop_queue(qdev->ndev); 2223 netif_carrier_off(qdev->ndev); 2224 ql_disable_interrupts(qdev); 2225 qdev->port_link_state = LS_DOWN; 2226 set_bit(QL_RESET_ACTIVE, &qdev->flags) ; 2227 2228 if (value & ISP_CONTROL_FE) { 2229 /* 2230 * Chip Fatal Error. 2231 */ 2232 var = 2233 ql_read_page0_reg_l(qdev, 2234 &port_regs->PortFatalErrStatus); 2235 netdev_warn(ndev, 2236 "Resetting chip. PortFatalErrStatus register = 0x%x\n", 2237 var); 2238 set_bit(QL_RESET_START, &qdev->flags) ; 2239 } else { 2240 /* 2241 * Soft Reset Requested. 2242 */ 2243 set_bit(QL_RESET_PER_SCSI, &qdev->flags) ; 2244 netdev_err(ndev, 2245 "Another function issued a reset to the chip. ISR value = %x\n", 2246 value); 2247 } 2248 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0); 2249 spin_unlock(&qdev->adapter_lock); 2250 } else if (value & ISP_IMR_DISABLE_CMPL_INT) { 2251 ql_disable_interrupts(qdev); 2252 if (likely(napi_schedule_prep(&qdev->napi))) 2253 __napi_schedule(&qdev->napi); 2254 } else 2255 return IRQ_NONE; 2256 2257 return IRQ_RETVAL(handled); 2258 } 2259 2260 /* 2261 * Get the total number of segments needed for the given number of fragments. 2262 * This is necessary because outbound address lists (OAL) will be used when 2263 * more than two frags are given. Each address list has 5 addr/len pairs. 2264 * The 5th pair in each OAL is used to point to the next OAL if more frags 2265 * are coming. That is why the frags:segment count ratio is not linear. 2266 */ 2267 static int ql_get_seg_count(struct ql3_adapter *qdev, unsigned short frags) 2268 { 2269 if (qdev->device_id == QL3022_DEVICE_ID) 2270 return 1; 2271 2272 if (frags <= 2) 2273 return frags + 1; 2274 else if (frags <= 6) 2275 return frags + 2; 2276 else if (frags <= 10) 2277 return frags + 3; 2278 else if (frags <= 14) 2279 return frags + 4; 2280 else if (frags <= 18) 2281 return frags + 5; 2282 return -1; 2283 } 2284 2285 static void ql_hw_csum_setup(const struct sk_buff *skb, 2286 struct ob_mac_iocb_req *mac_iocb_ptr) 2287 { 2288 const struct iphdr *ip = ip_hdr(skb); 2289 2290 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb); 2291 mac_iocb_ptr->ip_hdr_len = ip->ihl; 2292 2293 if (ip->protocol == IPPROTO_TCP) { 2294 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC | 2295 OB_3032MAC_IOCB_REQ_IC; 2296 } else { 2297 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC | 2298 OB_3032MAC_IOCB_REQ_IC; 2299 } 2300 2301 } 2302 2303 /* 2304 * Map the buffers for this transmit. 2305 * This will return NETDEV_TX_BUSY or NETDEV_TX_OK based on success. 2306 */ 2307 static int ql_send_map(struct ql3_adapter *qdev, 2308 struct ob_mac_iocb_req *mac_iocb_ptr, 2309 struct ql_tx_buf_cb *tx_cb, 2310 struct sk_buff *skb) 2311 { 2312 struct oal *oal; 2313 struct oal_entry *oal_entry; 2314 int len = skb_headlen(skb); 2315 dma_addr_t map; 2316 int err; 2317 int completed_segs, i; 2318 int seg_cnt, seg = 0; 2319 int frag_cnt = (int)skb_shinfo(skb)->nr_frags; 2320 2321 seg_cnt = tx_cb->seg_count; 2322 /* 2323 * Map the skb buffer first. 2324 */ 2325 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE); 2326 2327 err = pci_dma_mapping_error(qdev->pdev, map); 2328 if (err) { 2329 netdev_err(qdev->ndev, "PCI mapping failed with error: %d\n", 2330 err); 2331 2332 return NETDEV_TX_BUSY; 2333 } 2334 2335 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low; 2336 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map)); 2337 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map)); 2338 oal_entry->len = cpu_to_le32(len); 2339 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map); 2340 dma_unmap_len_set(&tx_cb->map[seg], maplen, len); 2341 seg++; 2342 2343 if (seg_cnt == 1) { 2344 /* Terminate the last segment. */ 2345 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY); 2346 return NETDEV_TX_OK; 2347 } 2348 oal = tx_cb->oal; 2349 for (completed_segs = 0; 2350 completed_segs < frag_cnt; 2351 completed_segs++, seg++) { 2352 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs]; 2353 oal_entry++; 2354 /* 2355 * Check for continuation requirements. 2356 * It's strange but necessary. 2357 * Continuation entry points to outbound address list. 2358 */ 2359 if ((seg == 2 && seg_cnt > 3) || 2360 (seg == 7 && seg_cnt > 8) || 2361 (seg == 12 && seg_cnt > 13) || 2362 (seg == 17 && seg_cnt > 18)) { 2363 map = pci_map_single(qdev->pdev, oal, 2364 sizeof(struct oal), 2365 PCI_DMA_TODEVICE); 2366 2367 err = pci_dma_mapping_error(qdev->pdev, map); 2368 if (err) { 2369 netdev_err(qdev->ndev, 2370 "PCI mapping outbound address list with error: %d\n", 2371 err); 2372 goto map_error; 2373 } 2374 2375 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map)); 2376 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map)); 2377 oal_entry->len = cpu_to_le32(sizeof(struct oal) | 2378 OAL_CONT_ENTRY); 2379 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map); 2380 dma_unmap_len_set(&tx_cb->map[seg], maplen, 2381 sizeof(struct oal)); 2382 oal_entry = (struct oal_entry *)oal; 2383 oal++; 2384 seg++; 2385 } 2386 2387 map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag), 2388 DMA_TO_DEVICE); 2389 2390 err = dma_mapping_error(&qdev->pdev->dev, map); 2391 if (err) { 2392 netdev_err(qdev->ndev, 2393 "PCI mapping frags failed with error: %d\n", 2394 err); 2395 goto map_error; 2396 } 2397 2398 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map)); 2399 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map)); 2400 oal_entry->len = cpu_to_le32(skb_frag_size(frag)); 2401 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map); 2402 dma_unmap_len_set(&tx_cb->map[seg], maplen, skb_frag_size(frag)); 2403 } 2404 /* Terminate the last segment. */ 2405 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY); 2406 return NETDEV_TX_OK; 2407 2408 map_error: 2409 /* A PCI mapping failed and now we will need to back out 2410 * We need to traverse through the oal's and associated pages which 2411 * have been mapped and now we must unmap them to clean up properly 2412 */ 2413 2414 seg = 1; 2415 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low; 2416 oal = tx_cb->oal; 2417 for (i = 0; i < completed_segs; i++, seg++) { 2418 oal_entry++; 2419 2420 /* 2421 * Check for continuation requirements. 2422 * It's strange but necessary. 2423 */ 2424 2425 if ((seg == 2 && seg_cnt > 3) || 2426 (seg == 7 && seg_cnt > 8) || 2427 (seg == 12 && seg_cnt > 13) || 2428 (seg == 17 && seg_cnt > 18)) { 2429 pci_unmap_single(qdev->pdev, 2430 dma_unmap_addr(&tx_cb->map[seg], mapaddr), 2431 dma_unmap_len(&tx_cb->map[seg], maplen), 2432 PCI_DMA_TODEVICE); 2433 oal++; 2434 seg++; 2435 } 2436 2437 pci_unmap_page(qdev->pdev, 2438 dma_unmap_addr(&tx_cb->map[seg], mapaddr), 2439 dma_unmap_len(&tx_cb->map[seg], maplen), 2440 PCI_DMA_TODEVICE); 2441 } 2442 2443 pci_unmap_single(qdev->pdev, 2444 dma_unmap_addr(&tx_cb->map[0], mapaddr), 2445 dma_unmap_addr(&tx_cb->map[0], maplen), 2446 PCI_DMA_TODEVICE); 2447 2448 return NETDEV_TX_BUSY; 2449 2450 } 2451 2452 /* 2453 * The difference between 3022 and 3032 sends: 2454 * 3022 only supports a simple single segment transmission. 2455 * 3032 supports checksumming and scatter/gather lists (fragments). 2456 * The 3032 supports sglists by using the 3 addr/len pairs (ALP) 2457 * in the IOCB plus a chain of outbound address lists (OAL) that 2458 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th) 2459 * will be used to point to an OAL when more ALP entries are required. 2460 * The IOCB is always the top of the chain followed by one or more 2461 * OALs (when necessary). 2462 */ 2463 static netdev_tx_t ql3xxx_send(struct sk_buff *skb, 2464 struct net_device *ndev) 2465 { 2466 struct ql3_adapter *qdev = netdev_priv(ndev); 2467 struct ql3xxx_port_registers __iomem *port_regs = 2468 qdev->mem_map_registers; 2469 struct ql_tx_buf_cb *tx_cb; 2470 u32 tot_len = skb->len; 2471 struct ob_mac_iocb_req *mac_iocb_ptr; 2472 2473 if (unlikely(atomic_read(&qdev->tx_count) < 2)) 2474 return NETDEV_TX_BUSY; 2475 2476 tx_cb = &qdev->tx_buf[qdev->req_producer_index]; 2477 tx_cb->seg_count = ql_get_seg_count(qdev, 2478 skb_shinfo(skb)->nr_frags); 2479 if (tx_cb->seg_count == -1) { 2480 netdev_err(ndev, "%s: invalid segment count!\n", __func__); 2481 return NETDEV_TX_OK; 2482 } 2483 2484 mac_iocb_ptr = tx_cb->queue_entry; 2485 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req)); 2486 mac_iocb_ptr->opcode = qdev->mac_ob_opcode; 2487 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X; 2488 mac_iocb_ptr->flags |= qdev->mb_bit_mask; 2489 mac_iocb_ptr->transaction_id = qdev->req_producer_index; 2490 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len); 2491 tx_cb->skb = skb; 2492 if (qdev->device_id == QL3032_DEVICE_ID && 2493 skb->ip_summed == CHECKSUM_PARTIAL) 2494 ql_hw_csum_setup(skb, mac_iocb_ptr); 2495 2496 if (ql_send_map(qdev, mac_iocb_ptr, tx_cb, skb) != NETDEV_TX_OK) { 2497 netdev_err(ndev, "%s: Could not map the segments!\n", __func__); 2498 return NETDEV_TX_BUSY; 2499 } 2500 2501 wmb(); 2502 qdev->req_producer_index++; 2503 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES) 2504 qdev->req_producer_index = 0; 2505 wmb(); 2506 ql_write_common_reg_l(qdev, 2507 &port_regs->CommonRegs.reqQProducerIndex, 2508 qdev->req_producer_index); 2509 2510 netif_printk(qdev, tx_queued, KERN_DEBUG, ndev, 2511 "tx queued, slot %d, len %d\n", 2512 qdev->req_producer_index, skb->len); 2513 2514 atomic_dec(&qdev->tx_count); 2515 return NETDEV_TX_OK; 2516 } 2517 2518 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev) 2519 { 2520 qdev->req_q_size = 2521 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req)); 2522 2523 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb); 2524 2525 /* The barrier is required to ensure request and response queue 2526 * addr writes to the registers. 2527 */ 2528 wmb(); 2529 2530 qdev->req_q_virt_addr = 2531 pci_alloc_consistent(qdev->pdev, 2532 (size_t) qdev->req_q_size, 2533 &qdev->req_q_phy_addr); 2534 2535 if ((qdev->req_q_virt_addr == NULL) || 2536 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) { 2537 netdev_err(qdev->ndev, "reqQ failed\n"); 2538 return -ENOMEM; 2539 } 2540 2541 qdev->rsp_q_virt_addr = 2542 pci_alloc_consistent(qdev->pdev, 2543 (size_t) qdev->rsp_q_size, 2544 &qdev->rsp_q_phy_addr); 2545 2546 if ((qdev->rsp_q_virt_addr == NULL) || 2547 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) { 2548 netdev_err(qdev->ndev, "rspQ allocation failed\n"); 2549 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size, 2550 qdev->req_q_virt_addr, 2551 qdev->req_q_phy_addr); 2552 return -ENOMEM; 2553 } 2554 2555 set_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags); 2556 2557 return 0; 2558 } 2559 2560 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev) 2561 { 2562 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags)) { 2563 netdev_info(qdev->ndev, "Already done\n"); 2564 return; 2565 } 2566 2567 pci_free_consistent(qdev->pdev, 2568 qdev->req_q_size, 2569 qdev->req_q_virt_addr, qdev->req_q_phy_addr); 2570 2571 qdev->req_q_virt_addr = NULL; 2572 2573 pci_free_consistent(qdev->pdev, 2574 qdev->rsp_q_size, 2575 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr); 2576 2577 qdev->rsp_q_virt_addr = NULL; 2578 2579 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags); 2580 } 2581 2582 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev) 2583 { 2584 /* Create Large Buffer Queue */ 2585 qdev->lrg_buf_q_size = 2586 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry); 2587 if (qdev->lrg_buf_q_size < PAGE_SIZE) 2588 qdev->lrg_buf_q_alloc_size = PAGE_SIZE; 2589 else 2590 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2; 2591 2592 qdev->lrg_buf = kmalloc_array(qdev->num_large_buffers, 2593 sizeof(struct ql_rcv_buf_cb), 2594 GFP_KERNEL); 2595 if (qdev->lrg_buf == NULL) 2596 return -ENOMEM; 2597 2598 qdev->lrg_buf_q_alloc_virt_addr = 2599 pci_alloc_consistent(qdev->pdev, 2600 qdev->lrg_buf_q_alloc_size, 2601 &qdev->lrg_buf_q_alloc_phy_addr); 2602 2603 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) { 2604 netdev_err(qdev->ndev, "lBufQ failed\n"); 2605 return -ENOMEM; 2606 } 2607 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr; 2608 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr; 2609 2610 /* Create Small Buffer Queue */ 2611 qdev->small_buf_q_size = 2612 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry); 2613 if (qdev->small_buf_q_size < PAGE_SIZE) 2614 qdev->small_buf_q_alloc_size = PAGE_SIZE; 2615 else 2616 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2; 2617 2618 qdev->small_buf_q_alloc_virt_addr = 2619 pci_alloc_consistent(qdev->pdev, 2620 qdev->small_buf_q_alloc_size, 2621 &qdev->small_buf_q_alloc_phy_addr); 2622 2623 if (qdev->small_buf_q_alloc_virt_addr == NULL) { 2624 netdev_err(qdev->ndev, "Small Buffer Queue allocation failed\n"); 2625 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size, 2626 qdev->lrg_buf_q_alloc_virt_addr, 2627 qdev->lrg_buf_q_alloc_phy_addr); 2628 return -ENOMEM; 2629 } 2630 2631 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr; 2632 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr; 2633 set_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags); 2634 return 0; 2635 } 2636 2637 static void ql_free_buffer_queues(struct ql3_adapter *qdev) 2638 { 2639 if (!test_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags)) { 2640 netdev_info(qdev->ndev, "Already done\n"); 2641 return; 2642 } 2643 kfree(qdev->lrg_buf); 2644 pci_free_consistent(qdev->pdev, 2645 qdev->lrg_buf_q_alloc_size, 2646 qdev->lrg_buf_q_alloc_virt_addr, 2647 qdev->lrg_buf_q_alloc_phy_addr); 2648 2649 qdev->lrg_buf_q_virt_addr = NULL; 2650 2651 pci_free_consistent(qdev->pdev, 2652 qdev->small_buf_q_alloc_size, 2653 qdev->small_buf_q_alloc_virt_addr, 2654 qdev->small_buf_q_alloc_phy_addr); 2655 2656 qdev->small_buf_q_virt_addr = NULL; 2657 2658 clear_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags); 2659 } 2660 2661 static int ql_alloc_small_buffers(struct ql3_adapter *qdev) 2662 { 2663 int i; 2664 struct bufq_addr_element *small_buf_q_entry; 2665 2666 /* Currently we allocate on one of memory and use it for smallbuffers */ 2667 qdev->small_buf_total_size = 2668 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES * 2669 QL_SMALL_BUFFER_SIZE); 2670 2671 qdev->small_buf_virt_addr = 2672 pci_alloc_consistent(qdev->pdev, 2673 qdev->small_buf_total_size, 2674 &qdev->small_buf_phy_addr); 2675 2676 if (qdev->small_buf_virt_addr == NULL) { 2677 netdev_err(qdev->ndev, "Failed to get small buffer memory\n"); 2678 return -ENOMEM; 2679 } 2680 2681 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr); 2682 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr); 2683 2684 small_buf_q_entry = qdev->small_buf_q_virt_addr; 2685 2686 /* Initialize the small buffer queue. */ 2687 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) { 2688 small_buf_q_entry->addr_high = 2689 cpu_to_le32(qdev->small_buf_phy_addr_high); 2690 small_buf_q_entry->addr_low = 2691 cpu_to_le32(qdev->small_buf_phy_addr_low + 2692 (i * QL_SMALL_BUFFER_SIZE)); 2693 small_buf_q_entry++; 2694 } 2695 qdev->small_buf_index = 0; 2696 set_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags); 2697 return 0; 2698 } 2699 2700 static void ql_free_small_buffers(struct ql3_adapter *qdev) 2701 { 2702 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags)) { 2703 netdev_info(qdev->ndev, "Already done\n"); 2704 return; 2705 } 2706 if (qdev->small_buf_virt_addr != NULL) { 2707 pci_free_consistent(qdev->pdev, 2708 qdev->small_buf_total_size, 2709 qdev->small_buf_virt_addr, 2710 qdev->small_buf_phy_addr); 2711 2712 qdev->small_buf_virt_addr = NULL; 2713 } 2714 } 2715 2716 static void ql_free_large_buffers(struct ql3_adapter *qdev) 2717 { 2718 int i = 0; 2719 struct ql_rcv_buf_cb *lrg_buf_cb; 2720 2721 for (i = 0; i < qdev->num_large_buffers; i++) { 2722 lrg_buf_cb = &qdev->lrg_buf[i]; 2723 if (lrg_buf_cb->skb) { 2724 dev_kfree_skb(lrg_buf_cb->skb); 2725 pci_unmap_single(qdev->pdev, 2726 dma_unmap_addr(lrg_buf_cb, mapaddr), 2727 dma_unmap_len(lrg_buf_cb, maplen), 2728 PCI_DMA_FROMDEVICE); 2729 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb)); 2730 } else { 2731 break; 2732 } 2733 } 2734 } 2735 2736 static void ql_init_large_buffers(struct ql3_adapter *qdev) 2737 { 2738 int i; 2739 struct ql_rcv_buf_cb *lrg_buf_cb; 2740 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr; 2741 2742 for (i = 0; i < qdev->num_large_buffers; i++) { 2743 lrg_buf_cb = &qdev->lrg_buf[i]; 2744 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high; 2745 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low; 2746 buf_addr_ele++; 2747 } 2748 qdev->lrg_buf_index = 0; 2749 qdev->lrg_buf_skb_check = 0; 2750 } 2751 2752 static int ql_alloc_large_buffers(struct ql3_adapter *qdev) 2753 { 2754 int i; 2755 struct ql_rcv_buf_cb *lrg_buf_cb; 2756 struct sk_buff *skb; 2757 dma_addr_t map; 2758 int err; 2759 2760 for (i = 0; i < qdev->num_large_buffers; i++) { 2761 skb = netdev_alloc_skb(qdev->ndev, 2762 qdev->lrg_buffer_len); 2763 if (unlikely(!skb)) { 2764 /* Better luck next round */ 2765 netdev_err(qdev->ndev, 2766 "large buff alloc failed for %d bytes at index %d\n", 2767 qdev->lrg_buffer_len * 2, i); 2768 ql_free_large_buffers(qdev); 2769 return -ENOMEM; 2770 } else { 2771 2772 lrg_buf_cb = &qdev->lrg_buf[i]; 2773 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb)); 2774 lrg_buf_cb->index = i; 2775 lrg_buf_cb->skb = skb; 2776 /* 2777 * We save some space to copy the ethhdr from first 2778 * buffer 2779 */ 2780 skb_reserve(skb, QL_HEADER_SPACE); 2781 map = pci_map_single(qdev->pdev, 2782 skb->data, 2783 qdev->lrg_buffer_len - 2784 QL_HEADER_SPACE, 2785 PCI_DMA_FROMDEVICE); 2786 2787 err = pci_dma_mapping_error(qdev->pdev, map); 2788 if (err) { 2789 netdev_err(qdev->ndev, 2790 "PCI mapping failed with error: %d\n", 2791 err); 2792 ql_free_large_buffers(qdev); 2793 return -ENOMEM; 2794 } 2795 2796 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map); 2797 dma_unmap_len_set(lrg_buf_cb, maplen, 2798 qdev->lrg_buffer_len - 2799 QL_HEADER_SPACE); 2800 lrg_buf_cb->buf_phy_addr_low = 2801 cpu_to_le32(LS_64BITS(map)); 2802 lrg_buf_cb->buf_phy_addr_high = 2803 cpu_to_le32(MS_64BITS(map)); 2804 } 2805 } 2806 return 0; 2807 } 2808 2809 static void ql_free_send_free_list(struct ql3_adapter *qdev) 2810 { 2811 struct ql_tx_buf_cb *tx_cb; 2812 int i; 2813 2814 tx_cb = &qdev->tx_buf[0]; 2815 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) { 2816 kfree(tx_cb->oal); 2817 tx_cb->oal = NULL; 2818 tx_cb++; 2819 } 2820 } 2821 2822 static int ql_create_send_free_list(struct ql3_adapter *qdev) 2823 { 2824 struct ql_tx_buf_cb *tx_cb; 2825 int i; 2826 struct ob_mac_iocb_req *req_q_curr = qdev->req_q_virt_addr; 2827 2828 /* Create free list of transmit buffers */ 2829 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) { 2830 2831 tx_cb = &qdev->tx_buf[i]; 2832 tx_cb->skb = NULL; 2833 tx_cb->queue_entry = req_q_curr; 2834 req_q_curr++; 2835 tx_cb->oal = kmalloc(512, GFP_KERNEL); 2836 if (tx_cb->oal == NULL) 2837 return -ENOMEM; 2838 } 2839 return 0; 2840 } 2841 2842 static int ql_alloc_mem_resources(struct ql3_adapter *qdev) 2843 { 2844 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) { 2845 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES; 2846 qdev->lrg_buffer_len = NORMAL_MTU_SIZE; 2847 } else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) { 2848 /* 2849 * Bigger buffers, so less of them. 2850 */ 2851 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES; 2852 qdev->lrg_buffer_len = JUMBO_MTU_SIZE; 2853 } else { 2854 netdev_err(qdev->ndev, "Invalid mtu size: %d. Only %d and %d are accepted.\n", 2855 qdev->ndev->mtu, NORMAL_MTU_SIZE, JUMBO_MTU_SIZE); 2856 return -ENOMEM; 2857 } 2858 qdev->num_large_buffers = 2859 qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY; 2860 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE; 2861 qdev->max_frame_size = 2862 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE; 2863 2864 /* 2865 * First allocate a page of shared memory and use it for shadow 2866 * locations of Network Request Queue Consumer Address Register and 2867 * Network Completion Queue Producer Index Register 2868 */ 2869 qdev->shadow_reg_virt_addr = 2870 pci_alloc_consistent(qdev->pdev, 2871 PAGE_SIZE, &qdev->shadow_reg_phy_addr); 2872 2873 if (qdev->shadow_reg_virt_addr != NULL) { 2874 qdev->preq_consumer_index = qdev->shadow_reg_virt_addr; 2875 qdev->req_consumer_index_phy_addr_high = 2876 MS_64BITS(qdev->shadow_reg_phy_addr); 2877 qdev->req_consumer_index_phy_addr_low = 2878 LS_64BITS(qdev->shadow_reg_phy_addr); 2879 2880 qdev->prsp_producer_index = 2881 (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8); 2882 qdev->rsp_producer_index_phy_addr_high = 2883 qdev->req_consumer_index_phy_addr_high; 2884 qdev->rsp_producer_index_phy_addr_low = 2885 qdev->req_consumer_index_phy_addr_low + 8; 2886 } else { 2887 netdev_err(qdev->ndev, "shadowReg Alloc failed\n"); 2888 return -ENOMEM; 2889 } 2890 2891 if (ql_alloc_net_req_rsp_queues(qdev) != 0) { 2892 netdev_err(qdev->ndev, "ql_alloc_net_req_rsp_queues failed\n"); 2893 goto err_req_rsp; 2894 } 2895 2896 if (ql_alloc_buffer_queues(qdev) != 0) { 2897 netdev_err(qdev->ndev, "ql_alloc_buffer_queues failed\n"); 2898 goto err_buffer_queues; 2899 } 2900 2901 if (ql_alloc_small_buffers(qdev) != 0) { 2902 netdev_err(qdev->ndev, "ql_alloc_small_buffers failed\n"); 2903 goto err_small_buffers; 2904 } 2905 2906 if (ql_alloc_large_buffers(qdev) != 0) { 2907 netdev_err(qdev->ndev, "ql_alloc_large_buffers failed\n"); 2908 goto err_small_buffers; 2909 } 2910 2911 /* Initialize the large buffer queue. */ 2912 ql_init_large_buffers(qdev); 2913 if (ql_create_send_free_list(qdev)) 2914 goto err_free_list; 2915 2916 qdev->rsp_current = qdev->rsp_q_virt_addr; 2917 2918 return 0; 2919 err_free_list: 2920 ql_free_send_free_list(qdev); 2921 err_small_buffers: 2922 ql_free_buffer_queues(qdev); 2923 err_buffer_queues: 2924 ql_free_net_req_rsp_queues(qdev); 2925 err_req_rsp: 2926 pci_free_consistent(qdev->pdev, 2927 PAGE_SIZE, 2928 qdev->shadow_reg_virt_addr, 2929 qdev->shadow_reg_phy_addr); 2930 2931 return -ENOMEM; 2932 } 2933 2934 static void ql_free_mem_resources(struct ql3_adapter *qdev) 2935 { 2936 ql_free_send_free_list(qdev); 2937 ql_free_large_buffers(qdev); 2938 ql_free_small_buffers(qdev); 2939 ql_free_buffer_queues(qdev); 2940 ql_free_net_req_rsp_queues(qdev); 2941 if (qdev->shadow_reg_virt_addr != NULL) { 2942 pci_free_consistent(qdev->pdev, 2943 PAGE_SIZE, 2944 qdev->shadow_reg_virt_addr, 2945 qdev->shadow_reg_phy_addr); 2946 qdev->shadow_reg_virt_addr = NULL; 2947 } 2948 } 2949 2950 static int ql_init_misc_registers(struct ql3_adapter *qdev) 2951 { 2952 struct ql3xxx_local_ram_registers __iomem *local_ram = 2953 (void __iomem *)qdev->mem_map_registers; 2954 2955 if (ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK, 2956 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * 2957 2) << 4)) 2958 return -1; 2959 2960 ql_write_page2_reg(qdev, 2961 &local_ram->bufletSize, qdev->nvram_data.bufletSize); 2962 2963 ql_write_page2_reg(qdev, 2964 &local_ram->maxBufletCount, 2965 qdev->nvram_data.bufletCount); 2966 2967 ql_write_page2_reg(qdev, 2968 &local_ram->freeBufletThresholdLow, 2969 (qdev->nvram_data.tcpWindowThreshold25 << 16) | 2970 (qdev->nvram_data.tcpWindowThreshold0)); 2971 2972 ql_write_page2_reg(qdev, 2973 &local_ram->freeBufletThresholdHigh, 2974 qdev->nvram_data.tcpWindowThreshold50); 2975 2976 ql_write_page2_reg(qdev, 2977 &local_ram->ipHashTableBase, 2978 (qdev->nvram_data.ipHashTableBaseHi << 16) | 2979 qdev->nvram_data.ipHashTableBaseLo); 2980 ql_write_page2_reg(qdev, 2981 &local_ram->ipHashTableCount, 2982 qdev->nvram_data.ipHashTableSize); 2983 ql_write_page2_reg(qdev, 2984 &local_ram->tcpHashTableBase, 2985 (qdev->nvram_data.tcpHashTableBaseHi << 16) | 2986 qdev->nvram_data.tcpHashTableBaseLo); 2987 ql_write_page2_reg(qdev, 2988 &local_ram->tcpHashTableCount, 2989 qdev->nvram_data.tcpHashTableSize); 2990 ql_write_page2_reg(qdev, 2991 &local_ram->ncbBase, 2992 (qdev->nvram_data.ncbTableBaseHi << 16) | 2993 qdev->nvram_data.ncbTableBaseLo); 2994 ql_write_page2_reg(qdev, 2995 &local_ram->maxNcbCount, 2996 qdev->nvram_data.ncbTableSize); 2997 ql_write_page2_reg(qdev, 2998 &local_ram->drbBase, 2999 (qdev->nvram_data.drbTableBaseHi << 16) | 3000 qdev->nvram_data.drbTableBaseLo); 3001 ql_write_page2_reg(qdev, 3002 &local_ram->maxDrbCount, 3003 qdev->nvram_data.drbTableSize); 3004 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK); 3005 return 0; 3006 } 3007 3008 static int ql_adapter_initialize(struct ql3_adapter *qdev) 3009 { 3010 u32 value; 3011 struct ql3xxx_port_registers __iomem *port_regs = 3012 qdev->mem_map_registers; 3013 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg; 3014 struct ql3xxx_host_memory_registers __iomem *hmem_regs = 3015 (void __iomem *)port_regs; 3016 u32 delay = 10; 3017 int status = 0; 3018 3019 if (ql_mii_setup(qdev)) 3020 return -1; 3021 3022 /* Bring out PHY out of reset */ 3023 ql_write_common_reg(qdev, spir, 3024 (ISP_SERIAL_PORT_IF_WE | 3025 (ISP_SERIAL_PORT_IF_WE << 16))); 3026 /* Give the PHY time to come out of reset. */ 3027 mdelay(100); 3028 qdev->port_link_state = LS_DOWN; 3029 netif_carrier_off(qdev->ndev); 3030 3031 /* V2 chip fix for ARS-39168. */ 3032 ql_write_common_reg(qdev, spir, 3033 (ISP_SERIAL_PORT_IF_SDE | 3034 (ISP_SERIAL_PORT_IF_SDE << 16))); 3035 3036 /* Request Queue Registers */ 3037 *((u32 *)(qdev->preq_consumer_index)) = 0; 3038 atomic_set(&qdev->tx_count, NUM_REQ_Q_ENTRIES); 3039 qdev->req_producer_index = 0; 3040 3041 ql_write_page1_reg(qdev, 3042 &hmem_regs->reqConsumerIndexAddrHigh, 3043 qdev->req_consumer_index_phy_addr_high); 3044 ql_write_page1_reg(qdev, 3045 &hmem_regs->reqConsumerIndexAddrLow, 3046 qdev->req_consumer_index_phy_addr_low); 3047 3048 ql_write_page1_reg(qdev, 3049 &hmem_regs->reqBaseAddrHigh, 3050 MS_64BITS(qdev->req_q_phy_addr)); 3051 ql_write_page1_reg(qdev, 3052 &hmem_regs->reqBaseAddrLow, 3053 LS_64BITS(qdev->req_q_phy_addr)); 3054 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES); 3055 3056 /* Response Queue Registers */ 3057 *((__le16 *) (qdev->prsp_producer_index)) = 0; 3058 qdev->rsp_consumer_index = 0; 3059 qdev->rsp_current = qdev->rsp_q_virt_addr; 3060 3061 ql_write_page1_reg(qdev, 3062 &hmem_regs->rspProducerIndexAddrHigh, 3063 qdev->rsp_producer_index_phy_addr_high); 3064 3065 ql_write_page1_reg(qdev, 3066 &hmem_regs->rspProducerIndexAddrLow, 3067 qdev->rsp_producer_index_phy_addr_low); 3068 3069 ql_write_page1_reg(qdev, 3070 &hmem_regs->rspBaseAddrHigh, 3071 MS_64BITS(qdev->rsp_q_phy_addr)); 3072 3073 ql_write_page1_reg(qdev, 3074 &hmem_regs->rspBaseAddrLow, 3075 LS_64BITS(qdev->rsp_q_phy_addr)); 3076 3077 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES); 3078 3079 /* Large Buffer Queue */ 3080 ql_write_page1_reg(qdev, 3081 &hmem_regs->rxLargeQBaseAddrHigh, 3082 MS_64BITS(qdev->lrg_buf_q_phy_addr)); 3083 3084 ql_write_page1_reg(qdev, 3085 &hmem_regs->rxLargeQBaseAddrLow, 3086 LS_64BITS(qdev->lrg_buf_q_phy_addr)); 3087 3088 ql_write_page1_reg(qdev, 3089 &hmem_regs->rxLargeQLength, 3090 qdev->num_lbufq_entries); 3091 3092 ql_write_page1_reg(qdev, 3093 &hmem_regs->rxLargeBufferLength, 3094 qdev->lrg_buffer_len); 3095 3096 /* Small Buffer Queue */ 3097 ql_write_page1_reg(qdev, 3098 &hmem_regs->rxSmallQBaseAddrHigh, 3099 MS_64BITS(qdev->small_buf_q_phy_addr)); 3100 3101 ql_write_page1_reg(qdev, 3102 &hmem_regs->rxSmallQBaseAddrLow, 3103 LS_64BITS(qdev->small_buf_q_phy_addr)); 3104 3105 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES); 3106 ql_write_page1_reg(qdev, 3107 &hmem_regs->rxSmallBufferLength, 3108 QL_SMALL_BUFFER_SIZE); 3109 3110 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1; 3111 qdev->small_buf_release_cnt = 8; 3112 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1; 3113 qdev->lrg_buf_release_cnt = 8; 3114 qdev->lrg_buf_next_free = qdev->lrg_buf_q_virt_addr; 3115 qdev->small_buf_index = 0; 3116 qdev->lrg_buf_index = 0; 3117 qdev->lrg_buf_free_count = 0; 3118 qdev->lrg_buf_free_head = NULL; 3119 qdev->lrg_buf_free_tail = NULL; 3120 3121 ql_write_common_reg(qdev, 3122 &port_regs->CommonRegs. 3123 rxSmallQProducerIndex, 3124 qdev->small_buf_q_producer_index); 3125 ql_write_common_reg(qdev, 3126 &port_regs->CommonRegs. 3127 rxLargeQProducerIndex, 3128 qdev->lrg_buf_q_producer_index); 3129 3130 /* 3131 * Find out if the chip has already been initialized. If it has, then 3132 * we skip some of the initialization. 3133 */ 3134 clear_bit(QL_LINK_MASTER, &qdev->flags); 3135 value = ql_read_page0_reg(qdev, &port_regs->portStatus); 3136 if ((value & PORT_STATUS_IC) == 0) { 3137 3138 /* Chip has not been configured yet, so let it rip. */ 3139 if (ql_init_misc_registers(qdev)) { 3140 status = -1; 3141 goto out; 3142 } 3143 3144 value = qdev->nvram_data.tcpMaxWindowSize; 3145 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value); 3146 3147 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig; 3148 3149 if (ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK, 3150 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) 3151 * 2) << 13)) { 3152 status = -1; 3153 goto out; 3154 } 3155 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value); 3156 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig, 3157 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) << 3158 16) | (INTERNAL_CHIP_SD | 3159 INTERNAL_CHIP_WE))); 3160 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK); 3161 } 3162 3163 if (qdev->mac_index) 3164 ql_write_page0_reg(qdev, 3165 &port_regs->mac1MaxFrameLengthReg, 3166 qdev->max_frame_size); 3167 else 3168 ql_write_page0_reg(qdev, 3169 &port_regs->mac0MaxFrameLengthReg, 3170 qdev->max_frame_size); 3171 3172 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, 3173 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * 3174 2) << 7)) { 3175 status = -1; 3176 goto out; 3177 } 3178 3179 PHY_Setup(qdev); 3180 ql_init_scan_mode(qdev); 3181 ql_get_phy_owner(qdev); 3182 3183 /* Load the MAC Configuration */ 3184 3185 /* Program lower 32 bits of the MAC address */ 3186 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg, 3187 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16)); 3188 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg, 3189 ((qdev->ndev->dev_addr[2] << 24) 3190 | (qdev->ndev->dev_addr[3] << 16) 3191 | (qdev->ndev->dev_addr[4] << 8) 3192 | qdev->ndev->dev_addr[5])); 3193 3194 /* Program top 16 bits of the MAC address */ 3195 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg, 3196 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1)); 3197 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg, 3198 ((qdev->ndev->dev_addr[0] << 8) 3199 | qdev->ndev->dev_addr[1])); 3200 3201 /* Enable Primary MAC */ 3202 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg, 3203 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) | 3204 MAC_ADDR_INDIRECT_PTR_REG_PE)); 3205 3206 /* Clear Primary and Secondary IP addresses */ 3207 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg, 3208 ((IP_ADDR_INDEX_REG_MASK << 16) | 3209 (qdev->mac_index << 2))); 3210 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0); 3211 3212 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg, 3213 ((IP_ADDR_INDEX_REG_MASK << 16) | 3214 ((qdev->mac_index << 2) + 1))); 3215 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0); 3216 3217 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); 3218 3219 /* Indicate Configuration Complete */ 3220 ql_write_page0_reg(qdev, 3221 &port_regs->portControl, 3222 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC)); 3223 3224 do { 3225 value = ql_read_page0_reg(qdev, &port_regs->portStatus); 3226 if (value & PORT_STATUS_IC) 3227 break; 3228 spin_unlock_irq(&qdev->hw_lock); 3229 msleep(500); 3230 spin_lock_irq(&qdev->hw_lock); 3231 } while (--delay); 3232 3233 if (delay == 0) { 3234 netdev_err(qdev->ndev, "Hw Initialization timeout\n"); 3235 status = -1; 3236 goto out; 3237 } 3238 3239 /* Enable Ethernet Function */ 3240 if (qdev->device_id == QL3032_DEVICE_ID) { 3241 value = 3242 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE | 3243 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 | 3244 QL3032_PORT_CONTROL_ET); 3245 ql_write_page0_reg(qdev, &port_regs->functionControl, 3246 ((value << 16) | value)); 3247 } else { 3248 value = 3249 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI | 3250 PORT_CONTROL_HH); 3251 ql_write_page0_reg(qdev, &port_regs->portControl, 3252 ((value << 16) | value)); 3253 } 3254 3255 3256 out: 3257 return status; 3258 } 3259 3260 /* 3261 * Caller holds hw_lock. 3262 */ 3263 static int ql_adapter_reset(struct ql3_adapter *qdev) 3264 { 3265 struct ql3xxx_port_registers __iomem *port_regs = 3266 qdev->mem_map_registers; 3267 int status = 0; 3268 u16 value; 3269 int max_wait_time; 3270 3271 set_bit(QL_RESET_ACTIVE, &qdev->flags); 3272 clear_bit(QL_RESET_DONE, &qdev->flags); 3273 3274 /* 3275 * Issue soft reset to chip. 3276 */ 3277 netdev_printk(KERN_DEBUG, qdev->ndev, "Issue soft reset to chip\n"); 3278 ql_write_common_reg(qdev, 3279 &port_regs->CommonRegs.ispControlStatus, 3280 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR)); 3281 3282 /* Wait 3 seconds for reset to complete. */ 3283 netdev_printk(KERN_DEBUG, qdev->ndev, 3284 "Wait 10 milliseconds for reset to complete\n"); 3285 3286 /* Wait until the firmware tells us the Soft Reset is done */ 3287 max_wait_time = 5; 3288 do { 3289 value = 3290 ql_read_common_reg(qdev, 3291 &port_regs->CommonRegs.ispControlStatus); 3292 if ((value & ISP_CONTROL_SR) == 0) 3293 break; 3294 3295 ssleep(1); 3296 } while ((--max_wait_time)); 3297 3298 /* 3299 * Also, make sure that the Network Reset Interrupt bit has been 3300 * cleared after the soft reset has taken place. 3301 */ 3302 value = 3303 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus); 3304 if (value & ISP_CONTROL_RI) { 3305 netdev_printk(KERN_DEBUG, qdev->ndev, 3306 "clearing RI after reset\n"); 3307 ql_write_common_reg(qdev, 3308 &port_regs->CommonRegs. 3309 ispControlStatus, 3310 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI)); 3311 } 3312 3313 if (max_wait_time == 0) { 3314 /* Issue Force Soft Reset */ 3315 ql_write_common_reg(qdev, 3316 &port_regs->CommonRegs. 3317 ispControlStatus, 3318 ((ISP_CONTROL_FSR << 16) | 3319 ISP_CONTROL_FSR)); 3320 /* 3321 * Wait until the firmware tells us the Force Soft Reset is 3322 * done 3323 */ 3324 max_wait_time = 5; 3325 do { 3326 value = ql_read_common_reg(qdev, 3327 &port_regs->CommonRegs. 3328 ispControlStatus); 3329 if ((value & ISP_CONTROL_FSR) == 0) 3330 break; 3331 ssleep(1); 3332 } while ((--max_wait_time)); 3333 } 3334 if (max_wait_time == 0) 3335 status = 1; 3336 3337 clear_bit(QL_RESET_ACTIVE, &qdev->flags); 3338 set_bit(QL_RESET_DONE, &qdev->flags); 3339 return status; 3340 } 3341 3342 static void ql_set_mac_info(struct ql3_adapter *qdev) 3343 { 3344 struct ql3xxx_port_registers __iomem *port_regs = 3345 qdev->mem_map_registers; 3346 u32 value, port_status; 3347 u8 func_number; 3348 3349 /* Get the function number */ 3350 value = 3351 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus); 3352 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK); 3353 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus); 3354 switch (value & ISP_CONTROL_FN_MASK) { 3355 case ISP_CONTROL_FN0_NET: 3356 qdev->mac_index = 0; 3357 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number; 3358 qdev->mb_bit_mask = FN0_MA_BITS_MASK; 3359 qdev->PHYAddr = PORT0_PHY_ADDRESS; 3360 if (port_status & PORT_STATUS_SM0) 3361 set_bit(QL_LINK_OPTICAL, &qdev->flags); 3362 else 3363 clear_bit(QL_LINK_OPTICAL, &qdev->flags); 3364 break; 3365 3366 case ISP_CONTROL_FN1_NET: 3367 qdev->mac_index = 1; 3368 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number; 3369 qdev->mb_bit_mask = FN1_MA_BITS_MASK; 3370 qdev->PHYAddr = PORT1_PHY_ADDRESS; 3371 if (port_status & PORT_STATUS_SM1) 3372 set_bit(QL_LINK_OPTICAL, &qdev->flags); 3373 else 3374 clear_bit(QL_LINK_OPTICAL, &qdev->flags); 3375 break; 3376 3377 case ISP_CONTROL_FN0_SCSI: 3378 case ISP_CONTROL_FN1_SCSI: 3379 default: 3380 netdev_printk(KERN_DEBUG, qdev->ndev, 3381 "Invalid function number, ispControlStatus = 0x%x\n", 3382 value); 3383 break; 3384 } 3385 qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8; 3386 } 3387 3388 static void ql_display_dev_info(struct net_device *ndev) 3389 { 3390 struct ql3_adapter *qdev = netdev_priv(ndev); 3391 struct pci_dev *pdev = qdev->pdev; 3392 3393 netdev_info(ndev, 3394 "%s Adapter %d RevisionID %d found %s on PCI slot %d\n", 3395 DRV_NAME, qdev->index, qdev->chip_rev_id, 3396 qdev->device_id == QL3032_DEVICE_ID ? "QLA3032" : "QLA3022", 3397 qdev->pci_slot); 3398 netdev_info(ndev, "%s Interface\n", 3399 test_bit(QL_LINK_OPTICAL, &qdev->flags) ? "OPTICAL" : "COPPER"); 3400 3401 /* 3402 * Print PCI bus width/type. 3403 */ 3404 netdev_info(ndev, "Bus interface is %s %s\n", 3405 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"), 3406 ((qdev->pci_x) ? "PCI-X" : "PCI")); 3407 3408 netdev_info(ndev, "mem IO base address adjusted = 0x%p\n", 3409 qdev->mem_map_registers); 3410 netdev_info(ndev, "Interrupt number = %d\n", pdev->irq); 3411 3412 netif_info(qdev, probe, ndev, "MAC address %pM\n", ndev->dev_addr); 3413 } 3414 3415 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset) 3416 { 3417 struct net_device *ndev = qdev->ndev; 3418 int retval = 0; 3419 3420 netif_stop_queue(ndev); 3421 netif_carrier_off(ndev); 3422 3423 clear_bit(QL_ADAPTER_UP, &qdev->flags); 3424 clear_bit(QL_LINK_MASTER, &qdev->flags); 3425 3426 ql_disable_interrupts(qdev); 3427 3428 free_irq(qdev->pdev->irq, ndev); 3429 3430 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) { 3431 netdev_info(qdev->ndev, "calling pci_disable_msi()\n"); 3432 clear_bit(QL_MSI_ENABLED, &qdev->flags); 3433 pci_disable_msi(qdev->pdev); 3434 } 3435 3436 del_timer_sync(&qdev->adapter_timer); 3437 3438 napi_disable(&qdev->napi); 3439 3440 if (do_reset) { 3441 int soft_reset; 3442 unsigned long hw_flags; 3443 3444 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 3445 if (ql_wait_for_drvr_lock(qdev)) { 3446 soft_reset = ql_adapter_reset(qdev); 3447 if (soft_reset) { 3448 netdev_err(ndev, "ql_adapter_reset(%d) FAILED!\n", 3449 qdev->index); 3450 } 3451 netdev_err(ndev, 3452 "Releasing driver lock via chip reset\n"); 3453 } else { 3454 netdev_err(ndev, 3455 "Could not acquire driver lock to do reset!\n"); 3456 retval = -1; 3457 } 3458 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 3459 } 3460 ql_free_mem_resources(qdev); 3461 return retval; 3462 } 3463 3464 static int ql_adapter_up(struct ql3_adapter *qdev) 3465 { 3466 struct net_device *ndev = qdev->ndev; 3467 int err; 3468 unsigned long irq_flags = IRQF_SHARED; 3469 unsigned long hw_flags; 3470 3471 if (ql_alloc_mem_resources(qdev)) { 3472 netdev_err(ndev, "Unable to allocate buffers\n"); 3473 return -ENOMEM; 3474 } 3475 3476 if (qdev->msi) { 3477 if (pci_enable_msi(qdev->pdev)) { 3478 netdev_err(ndev, 3479 "User requested MSI, but MSI failed to initialize. Continuing without MSI.\n"); 3480 qdev->msi = 0; 3481 } else { 3482 netdev_info(ndev, "MSI Enabled...\n"); 3483 set_bit(QL_MSI_ENABLED, &qdev->flags); 3484 irq_flags &= ~IRQF_SHARED; 3485 } 3486 } 3487 3488 err = request_irq(qdev->pdev->irq, ql3xxx_isr, 3489 irq_flags, ndev->name, ndev); 3490 if (err) { 3491 netdev_err(ndev, 3492 "Failed to reserve interrupt %d - already in use\n", 3493 qdev->pdev->irq); 3494 goto err_irq; 3495 } 3496 3497 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 3498 3499 err = ql_wait_for_drvr_lock(qdev); 3500 if (err) { 3501 err = ql_adapter_initialize(qdev); 3502 if (err) { 3503 netdev_err(ndev, "Unable to initialize adapter\n"); 3504 goto err_init; 3505 } 3506 netdev_err(ndev, "Releasing driver lock\n"); 3507 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK); 3508 } else { 3509 netdev_err(ndev, "Could not acquire driver lock\n"); 3510 goto err_lock; 3511 } 3512 3513 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 3514 3515 set_bit(QL_ADAPTER_UP, &qdev->flags); 3516 3517 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1); 3518 3519 napi_enable(&qdev->napi); 3520 ql_enable_interrupts(qdev); 3521 return 0; 3522 3523 err_init: 3524 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK); 3525 err_lock: 3526 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 3527 free_irq(qdev->pdev->irq, ndev); 3528 err_irq: 3529 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) { 3530 netdev_info(ndev, "calling pci_disable_msi()\n"); 3531 clear_bit(QL_MSI_ENABLED, &qdev->flags); 3532 pci_disable_msi(qdev->pdev); 3533 } 3534 return err; 3535 } 3536 3537 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset) 3538 { 3539 if (ql_adapter_down(qdev, reset) || ql_adapter_up(qdev)) { 3540 netdev_err(qdev->ndev, 3541 "Driver up/down cycle failed, closing device\n"); 3542 rtnl_lock(); 3543 dev_close(qdev->ndev); 3544 rtnl_unlock(); 3545 return -1; 3546 } 3547 return 0; 3548 } 3549 3550 static int ql3xxx_close(struct net_device *ndev) 3551 { 3552 struct ql3_adapter *qdev = netdev_priv(ndev); 3553 3554 /* 3555 * Wait for device to recover from a reset. 3556 * (Rarely happens, but possible.) 3557 */ 3558 while (!test_bit(QL_ADAPTER_UP, &qdev->flags)) 3559 msleep(50); 3560 3561 ql_adapter_down(qdev, QL_DO_RESET); 3562 return 0; 3563 } 3564 3565 static int ql3xxx_open(struct net_device *ndev) 3566 { 3567 struct ql3_adapter *qdev = netdev_priv(ndev); 3568 return ql_adapter_up(qdev); 3569 } 3570 3571 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p) 3572 { 3573 struct ql3_adapter *qdev = netdev_priv(ndev); 3574 struct ql3xxx_port_registers __iomem *port_regs = 3575 qdev->mem_map_registers; 3576 struct sockaddr *addr = p; 3577 unsigned long hw_flags; 3578 3579 if (netif_running(ndev)) 3580 return -EBUSY; 3581 3582 if (!is_valid_ether_addr(addr->sa_data)) 3583 return -EADDRNOTAVAIL; 3584 3585 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3586 3587 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 3588 /* Program lower 32 bits of the MAC address */ 3589 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg, 3590 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16)); 3591 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg, 3592 ((ndev->dev_addr[2] << 24) | (ndev-> 3593 dev_addr[3] << 16) | 3594 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5])); 3595 3596 /* Program top 16 bits of the MAC address */ 3597 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg, 3598 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1)); 3599 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg, 3600 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1])); 3601 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 3602 3603 return 0; 3604 } 3605 3606 static void ql3xxx_tx_timeout(struct net_device *ndev) 3607 { 3608 struct ql3_adapter *qdev = netdev_priv(ndev); 3609 3610 netdev_err(ndev, "Resetting...\n"); 3611 /* 3612 * Stop the queues, we've got a problem. 3613 */ 3614 netif_stop_queue(ndev); 3615 3616 /* 3617 * Wake up the worker to process this event. 3618 */ 3619 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0); 3620 } 3621 3622 static void ql_reset_work(struct work_struct *work) 3623 { 3624 struct ql3_adapter *qdev = 3625 container_of(work, struct ql3_adapter, reset_work.work); 3626 struct net_device *ndev = qdev->ndev; 3627 u32 value; 3628 struct ql_tx_buf_cb *tx_cb; 3629 int max_wait_time, i; 3630 struct ql3xxx_port_registers __iomem *port_regs = 3631 qdev->mem_map_registers; 3632 unsigned long hw_flags; 3633 3634 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START), &qdev->flags)) { 3635 clear_bit(QL_LINK_MASTER, &qdev->flags); 3636 3637 /* 3638 * Loop through the active list and return the skb. 3639 */ 3640 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) { 3641 int j; 3642 tx_cb = &qdev->tx_buf[i]; 3643 if (tx_cb->skb) { 3644 netdev_printk(KERN_DEBUG, ndev, 3645 "Freeing lost SKB\n"); 3646 pci_unmap_single(qdev->pdev, 3647 dma_unmap_addr(&tx_cb->map[0], 3648 mapaddr), 3649 dma_unmap_len(&tx_cb->map[0], maplen), 3650 PCI_DMA_TODEVICE); 3651 for (j = 1; j < tx_cb->seg_count; j++) { 3652 pci_unmap_page(qdev->pdev, 3653 dma_unmap_addr(&tx_cb->map[j], 3654 mapaddr), 3655 dma_unmap_len(&tx_cb->map[j], 3656 maplen), 3657 PCI_DMA_TODEVICE); 3658 } 3659 dev_kfree_skb(tx_cb->skb); 3660 tx_cb->skb = NULL; 3661 } 3662 } 3663 3664 netdev_err(ndev, "Clearing NRI after reset\n"); 3665 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 3666 ql_write_common_reg(qdev, 3667 &port_regs->CommonRegs. 3668 ispControlStatus, 3669 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI)); 3670 /* 3671 * Wait the for Soft Reset to Complete. 3672 */ 3673 max_wait_time = 10; 3674 do { 3675 value = ql_read_common_reg(qdev, 3676 &port_regs->CommonRegs. 3677 3678 ispControlStatus); 3679 if ((value & ISP_CONTROL_SR) == 0) { 3680 netdev_printk(KERN_DEBUG, ndev, 3681 "reset completed\n"); 3682 break; 3683 } 3684 3685 if (value & ISP_CONTROL_RI) { 3686 netdev_printk(KERN_DEBUG, ndev, 3687 "clearing NRI after reset\n"); 3688 ql_write_common_reg(qdev, 3689 &port_regs-> 3690 CommonRegs. 3691 ispControlStatus, 3692 ((ISP_CONTROL_RI << 3693 16) | ISP_CONTROL_RI)); 3694 } 3695 3696 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 3697 ssleep(1); 3698 spin_lock_irqsave(&qdev->hw_lock, hw_flags); 3699 } while (--max_wait_time); 3700 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); 3701 3702 if (value & ISP_CONTROL_SR) { 3703 3704 /* 3705 * Set the reset flags and clear the board again. 3706 * Nothing else to do... 3707 */ 3708 netdev_err(ndev, 3709 "Timed out waiting for reset to complete\n"); 3710 netdev_err(ndev, "Do a reset\n"); 3711 clear_bit(QL_RESET_PER_SCSI, &qdev->flags); 3712 clear_bit(QL_RESET_START, &qdev->flags); 3713 ql_cycle_adapter(qdev, QL_DO_RESET); 3714 return; 3715 } 3716 3717 clear_bit(QL_RESET_ACTIVE, &qdev->flags); 3718 clear_bit(QL_RESET_PER_SCSI, &qdev->flags); 3719 clear_bit(QL_RESET_START, &qdev->flags); 3720 ql_cycle_adapter(qdev, QL_NO_RESET); 3721 } 3722 } 3723 3724 static void ql_tx_timeout_work(struct work_struct *work) 3725 { 3726 struct ql3_adapter *qdev = 3727 container_of(work, struct ql3_adapter, tx_timeout_work.work); 3728 3729 ql_cycle_adapter(qdev, QL_DO_RESET); 3730 } 3731 3732 static void ql_get_board_info(struct ql3_adapter *qdev) 3733 { 3734 struct ql3xxx_port_registers __iomem *port_regs = 3735 qdev->mem_map_registers; 3736 u32 value; 3737 3738 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus); 3739 3740 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12); 3741 if (value & PORT_STATUS_64) 3742 qdev->pci_width = 64; 3743 else 3744 qdev->pci_width = 32; 3745 if (value & PORT_STATUS_X) 3746 qdev->pci_x = 1; 3747 else 3748 qdev->pci_x = 0; 3749 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn); 3750 } 3751 3752 static void ql3xxx_timer(unsigned long ptr) 3753 { 3754 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr; 3755 queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0); 3756 } 3757 3758 static const struct net_device_ops ql3xxx_netdev_ops = { 3759 .ndo_open = ql3xxx_open, 3760 .ndo_start_xmit = ql3xxx_send, 3761 .ndo_stop = ql3xxx_close, 3762 .ndo_validate_addr = eth_validate_addr, 3763 .ndo_set_mac_address = ql3xxx_set_mac_address, 3764 .ndo_tx_timeout = ql3xxx_tx_timeout, 3765 }; 3766 3767 static int ql3xxx_probe(struct pci_dev *pdev, 3768 const struct pci_device_id *pci_entry) 3769 { 3770 struct net_device *ndev = NULL; 3771 struct ql3_adapter *qdev = NULL; 3772 static int cards_found; 3773 int uninitialized_var(pci_using_dac), err; 3774 3775 err = pci_enable_device(pdev); 3776 if (err) { 3777 pr_err("%s cannot enable PCI device\n", pci_name(pdev)); 3778 goto err_out; 3779 } 3780 3781 err = pci_request_regions(pdev, DRV_NAME); 3782 if (err) { 3783 pr_err("%s cannot obtain PCI resources\n", pci_name(pdev)); 3784 goto err_out_disable_pdev; 3785 } 3786 3787 pci_set_master(pdev); 3788 3789 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 3790 pci_using_dac = 1; 3791 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3792 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) { 3793 pci_using_dac = 0; 3794 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3795 } 3796 3797 if (err) { 3798 pr_err("%s no usable DMA configuration\n", pci_name(pdev)); 3799 goto err_out_free_regions; 3800 } 3801 3802 ndev = alloc_etherdev(sizeof(struct ql3_adapter)); 3803 if (!ndev) { 3804 err = -ENOMEM; 3805 goto err_out_free_regions; 3806 } 3807 3808 SET_NETDEV_DEV(ndev, &pdev->dev); 3809 3810 pci_set_drvdata(pdev, ndev); 3811 3812 qdev = netdev_priv(ndev); 3813 qdev->index = cards_found; 3814 qdev->ndev = ndev; 3815 qdev->pdev = pdev; 3816 qdev->device_id = pci_entry->device; 3817 qdev->port_link_state = LS_DOWN; 3818 if (msi) 3819 qdev->msi = 1; 3820 3821 qdev->msg_enable = netif_msg_init(debug, default_msg); 3822 3823 if (pci_using_dac) 3824 ndev->features |= NETIF_F_HIGHDMA; 3825 if (qdev->device_id == QL3032_DEVICE_ID) 3826 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 3827 3828 qdev->mem_map_registers = pci_ioremap_bar(pdev, 1); 3829 if (!qdev->mem_map_registers) { 3830 pr_err("%s: cannot map device registers\n", pci_name(pdev)); 3831 err = -EIO; 3832 goto err_out_free_ndev; 3833 } 3834 3835 spin_lock_init(&qdev->adapter_lock); 3836 spin_lock_init(&qdev->hw_lock); 3837 3838 /* Set driver entry points */ 3839 ndev->netdev_ops = &ql3xxx_netdev_ops; 3840 ndev->ethtool_ops = &ql3xxx_ethtool_ops; 3841 ndev->watchdog_timeo = 5 * HZ; 3842 3843 netif_napi_add(ndev, &qdev->napi, ql_poll, 64); 3844 3845 ndev->irq = pdev->irq; 3846 3847 /* make sure the EEPROM is good */ 3848 if (ql_get_nvram_params(qdev)) { 3849 pr_alert("%s: Adapter #%d, Invalid NVRAM parameters\n", 3850 __func__, qdev->index); 3851 err = -EIO; 3852 goto err_out_iounmap; 3853 } 3854 3855 ql_set_mac_info(qdev); 3856 3857 /* Validate and set parameters */ 3858 if (qdev->mac_index) { 3859 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ; 3860 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress); 3861 } else { 3862 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ; 3863 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress); 3864 } 3865 3866 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES; 3867 3868 /* Record PCI bus information. */ 3869 ql_get_board_info(qdev); 3870 3871 /* 3872 * Set the Maximum Memory Read Byte Count value. We do this to handle 3873 * jumbo frames. 3874 */ 3875 if (qdev->pci_x) 3876 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036); 3877 3878 err = register_netdev(ndev); 3879 if (err) { 3880 pr_err("%s: cannot register net device\n", pci_name(pdev)); 3881 goto err_out_iounmap; 3882 } 3883 3884 /* we're going to reset, so assume we have no link for now */ 3885 3886 netif_carrier_off(ndev); 3887 netif_stop_queue(ndev); 3888 3889 qdev->workqueue = create_singlethread_workqueue(ndev->name); 3890 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work); 3891 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work); 3892 INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work); 3893 3894 init_timer(&qdev->adapter_timer); 3895 qdev->adapter_timer.function = ql3xxx_timer; 3896 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */ 3897 qdev->adapter_timer.data = (unsigned long)qdev; 3898 3899 if (!cards_found) { 3900 pr_alert("%s\n", DRV_STRING); 3901 pr_alert("Driver name: %s, Version: %s\n", 3902 DRV_NAME, DRV_VERSION); 3903 } 3904 ql_display_dev_info(ndev); 3905 3906 cards_found++; 3907 return 0; 3908 3909 err_out_iounmap: 3910 iounmap(qdev->mem_map_registers); 3911 err_out_free_ndev: 3912 free_netdev(ndev); 3913 err_out_free_regions: 3914 pci_release_regions(pdev); 3915 err_out_disable_pdev: 3916 pci_disable_device(pdev); 3917 err_out: 3918 return err; 3919 } 3920 3921 static void ql3xxx_remove(struct pci_dev *pdev) 3922 { 3923 struct net_device *ndev = pci_get_drvdata(pdev); 3924 struct ql3_adapter *qdev = netdev_priv(ndev); 3925 3926 unregister_netdev(ndev); 3927 3928 ql_disable_interrupts(qdev); 3929 3930 if (qdev->workqueue) { 3931 cancel_delayed_work(&qdev->reset_work); 3932 cancel_delayed_work(&qdev->tx_timeout_work); 3933 destroy_workqueue(qdev->workqueue); 3934 qdev->workqueue = NULL; 3935 } 3936 3937 iounmap(qdev->mem_map_registers); 3938 pci_release_regions(pdev); 3939 free_netdev(ndev); 3940 } 3941 3942 static struct pci_driver ql3xxx_driver = { 3943 3944 .name = DRV_NAME, 3945 .id_table = ql3xxx_pci_tbl, 3946 .probe = ql3xxx_probe, 3947 .remove = ql3xxx_remove, 3948 }; 3949 3950 module_pci_driver(ql3xxx_driver); 3951