1 /* QLogic qede NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8 
9 #ifndef _QEDE_H_
10 #define _QEDE_H_
11 #include <linux/compiler.h>
12 #include <linux/version.h>
13 #include <linux/workqueue.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/bitmap.h>
17 #include <linux/kernel.h>
18 #include <linux/mutex.h>
19 #include <linux/io.h>
20 #include <linux/qed/common_hsi.h>
21 #include <linux/qed/eth_common.h>
22 #include <linux/qed/qed_if.h>
23 #include <linux/qed/qed_chain.h>
24 #include <linux/qed/qed_eth_if.h>
25 
26 #define QEDE_MAJOR_VERSION		8
27 #define QEDE_MINOR_VERSION		7
28 #define QEDE_REVISION_VERSION		1
29 #define QEDE_ENGINEERING_VERSION	20
30 #define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "."	\
31 		__stringify(QEDE_MINOR_VERSION) "."		\
32 		__stringify(QEDE_REVISION_VERSION) "."		\
33 		__stringify(QEDE_ENGINEERING_VERSION)
34 
35 #define DRV_MODULE_SYM		qede
36 
37 struct qede_stats {
38 	u64 no_buff_discards;
39 	u64 rx_ucast_bytes;
40 	u64 rx_mcast_bytes;
41 	u64 rx_bcast_bytes;
42 	u64 rx_ucast_pkts;
43 	u64 rx_mcast_pkts;
44 	u64 rx_bcast_pkts;
45 	u64 mftag_filter_discards;
46 	u64 mac_filter_discards;
47 	u64 tx_ucast_bytes;
48 	u64 tx_mcast_bytes;
49 	u64 tx_bcast_bytes;
50 	u64 tx_ucast_pkts;
51 	u64 tx_mcast_pkts;
52 	u64 tx_bcast_pkts;
53 	u64 tx_err_drop_pkts;
54 	u64 coalesced_pkts;
55 	u64 coalesced_events;
56 	u64 coalesced_aborts_num;
57 	u64 non_coalesced_pkts;
58 	u64 coalesced_bytes;
59 
60 	/* port */
61 	u64 rx_64_byte_packets;
62 	u64 rx_65_to_127_byte_packets;
63 	u64 rx_128_to_255_byte_packets;
64 	u64 rx_256_to_511_byte_packets;
65 	u64 rx_512_to_1023_byte_packets;
66 	u64 rx_1024_to_1518_byte_packets;
67 	u64 rx_1519_to_1522_byte_packets;
68 	u64 rx_1519_to_2047_byte_packets;
69 	u64 rx_2048_to_4095_byte_packets;
70 	u64 rx_4096_to_9216_byte_packets;
71 	u64 rx_9217_to_16383_byte_packets;
72 	u64 rx_crc_errors;
73 	u64 rx_mac_crtl_frames;
74 	u64 rx_pause_frames;
75 	u64 rx_pfc_frames;
76 	u64 rx_align_errors;
77 	u64 rx_carrier_errors;
78 	u64 rx_oversize_packets;
79 	u64 rx_jabbers;
80 	u64 rx_undersize_packets;
81 	u64 rx_fragments;
82 	u64 tx_64_byte_packets;
83 	u64 tx_65_to_127_byte_packets;
84 	u64 tx_128_to_255_byte_packets;
85 	u64 tx_256_to_511_byte_packets;
86 	u64 tx_512_to_1023_byte_packets;
87 	u64 tx_1024_to_1518_byte_packets;
88 	u64 tx_1519_to_2047_byte_packets;
89 	u64 tx_2048_to_4095_byte_packets;
90 	u64 tx_4096_to_9216_byte_packets;
91 	u64 tx_9217_to_16383_byte_packets;
92 	u64 tx_pause_frames;
93 	u64 tx_pfc_frames;
94 	u64 tx_lpi_entry_count;
95 	u64 tx_total_collisions;
96 	u64 brb_truncates;
97 	u64 brb_discards;
98 	u64 tx_mac_ctrl_frames;
99 };
100 
101 struct qede_vlan {
102 	struct list_head list;
103 	u16 vid;
104 	bool configured;
105 };
106 
107 struct qede_dev {
108 	struct qed_dev			*cdev;
109 	struct net_device		*ndev;
110 	struct pci_dev			*pdev;
111 
112 	u32				dp_module;
113 	u8				dp_level;
114 
115 	u32 flags;
116 #define QEDE_FLAG_IS_VF	BIT(0)
117 #define IS_VF(edev)	(!!((edev)->flags & QEDE_FLAG_IS_VF))
118 
119 	const struct qed_eth_ops	*ops;
120 
121 	struct qed_dev_eth_info	dev_info;
122 #define QEDE_MAX_RSS_CNT(edev)	((edev)->dev_info.num_queues)
123 #define QEDE_MAX_TSS_CNT(edev)	((edev)->dev_info.num_queues * \
124 				 (edev)->dev_info.num_tc)
125 
126 	struct qede_fastpath		*fp_array;
127 	u16				req_rss;
128 	u16				num_rss;
129 	u8				num_tc;
130 #define QEDE_RSS_CNT(edev)		((edev)->num_rss)
131 #define QEDE_TSS_CNT(edev)		((edev)->num_rss *	\
132 					 (edev)->num_tc)
133 #define QEDE_TSS_IDX(edev, txqidx)	((txqidx) % (edev)->num_rss)
134 #define QEDE_TC_IDX(edev, txqidx)	((txqidx) / (edev)->num_rss)
135 #define QEDE_TX_QUEUE(edev, txqidx)	\
136 	(&(edev)->fp_array[QEDE_TSS_IDX((edev), (txqidx))].txqs[QEDE_TC_IDX( \
137 							(edev), (txqidx))])
138 
139 	struct qed_int_info		int_info;
140 	unsigned char			primary_mac[ETH_ALEN];
141 
142 	/* Smaller private varaiant of the RTNL lock */
143 	struct mutex			qede_lock;
144 	u32				state; /* Protected by qede_lock */
145 	u16				rx_buf_size;
146 	/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
147 #define ETH_OVERHEAD			(ETH_HLEN + 8 + 8)
148 	/* Max supported alignment is 256 (8 shift)
149 	 * minimal alignment shift 6 is optimal for 57xxx HW performance
150 	 */
151 #define QEDE_RX_ALIGN_SHIFT		max(6, min(8, L1_CACHE_SHIFT))
152 	/* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
153 	 * at the end of skb->data, to avoid wasting a full cache line.
154 	 * This reduces memory use (skb->truesize).
155 	 */
156 #define QEDE_FW_RX_ALIGN_END					\
157 	max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT,			\
158 	      SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
159 
160 	struct qede_stats		stats;
161 #define QEDE_RSS_INDIR_INITED	BIT(0)
162 #define QEDE_RSS_KEY_INITED	BIT(1)
163 #define QEDE_RSS_CAPS_INITED	BIT(2)
164 	u32 rss_params_inited; /* bit-field to track initialized rss params */
165 	struct qed_update_vport_rss_params	rss_params;
166 	u16			q_num_rx_buffers; /* Must be a power of two */
167 	u16			q_num_tx_buffers; /* Must be a power of two */
168 
169 	bool gro_disable;
170 	struct list_head vlan_list;
171 	u16 configured_vlans;
172 	u16 non_configured_vlans;
173 	bool accept_any_vlan;
174 	struct delayed_work		sp_task;
175 	unsigned long			sp_flags;
176 	u16				vxlan_dst_port;
177 	u16				geneve_dst_port;
178 };
179 
180 enum QEDE_STATE {
181 	QEDE_STATE_CLOSED,
182 	QEDE_STATE_OPEN,
183 };
184 
185 #define HILO_U64(hi, lo)		((((u64)(hi)) << 32) + (lo))
186 
187 #define	MAX_NUM_TC	8
188 #define	MAX_NUM_PRI	8
189 
190 /* The driver supports the new build_skb() API:
191  * RX ring buffer contains pointer to kmalloc() data only,
192  * skb are built only after the frame was DMA-ed.
193  */
194 struct sw_rx_data {
195 	struct page *data;
196 	dma_addr_t mapping;
197 	unsigned int page_offset;
198 };
199 
200 enum qede_agg_state {
201 	QEDE_AGG_STATE_NONE  = 0,
202 	QEDE_AGG_STATE_START = 1,
203 	QEDE_AGG_STATE_ERROR = 2
204 };
205 
206 struct qede_agg_info {
207 	struct sw_rx_data replace_buf;
208 	dma_addr_t replace_buf_mapping;
209 	struct sw_rx_data start_buf;
210 	dma_addr_t start_buf_mapping;
211 	struct eth_fast_path_rx_tpa_start_cqe start_cqe;
212 	enum qede_agg_state agg_state;
213 	struct sk_buff *skb;
214 	int frag_id;
215 	u16 vlan_tag;
216 };
217 
218 struct qede_rx_queue {
219 	__le16			*hw_cons_ptr;
220 	struct sw_rx_data	*sw_rx_ring;
221 	u16			sw_rx_cons;
222 	u16			sw_rx_prod;
223 	struct qed_chain	rx_bd_ring;
224 	struct qed_chain	rx_comp_ring;
225 	void __iomem		*hw_rxq_prod_addr;
226 
227 	/* GRO */
228 	struct qede_agg_info	tpa_info[ETH_TPA_MAX_AGGS_NUM];
229 
230 	int			rx_buf_size;
231 	unsigned int		rx_buf_seg_size;
232 
233 	u16			num_rx_buffers;
234 	u16			rxq_id;
235 
236 	u64			rx_hw_errors;
237 	u64			rx_alloc_errors;
238 };
239 
240 union db_prod {
241 	struct eth_db_data data;
242 	u32		raw;
243 };
244 
245 struct sw_tx_bd {
246 	struct sk_buff *skb;
247 	u8 flags;
248 /* Set on the first BD descriptor when there is a split BD */
249 #define QEDE_TSO_SPLIT_BD		BIT(0)
250 };
251 
252 struct qede_tx_queue {
253 	int			index; /* Queue index */
254 	__le16			*hw_cons_ptr;
255 	struct sw_tx_bd		*sw_tx_ring;
256 	u16			sw_tx_cons;
257 	u16			sw_tx_prod;
258 	struct qed_chain	tx_pbl;
259 	void __iomem		*doorbell_addr;
260 	union db_prod		tx_db;
261 
262 	u16			num_tx_buffers;
263 };
264 
265 #define BD_UNMAP_ADDR(bd)		HILO_U64(le32_to_cpu((bd)->addr.hi), \
266 						 le32_to_cpu((bd)->addr.lo))
267 #define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len)				\
268 	do {								\
269 		(bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr));	\
270 		(bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr));	\
271 		(bd)->nbytes = cpu_to_le16(len);			\
272 	} while (0)
273 #define BD_UNMAP_LEN(bd)		(le16_to_cpu((bd)->nbytes))
274 
275 struct qede_fastpath {
276 	struct qede_dev	*edev;
277 	u8			rss_id;
278 	struct napi_struct	napi;
279 	struct qed_sb_info	*sb_info;
280 	struct qede_rx_queue	*rxq;
281 	struct qede_tx_queue	*txqs;
282 
283 #define VEC_NAME_SIZE	(sizeof(((struct net_device *)0)->name) + 8)
284 	char	name[VEC_NAME_SIZE];
285 };
286 
287 /* Debug print definitions */
288 #define DP_NAME(edev) ((edev)->ndev->name)
289 
290 #define XMIT_PLAIN		0
291 #define XMIT_L4_CSUM		BIT(0)
292 #define XMIT_LSO		BIT(1)
293 #define XMIT_ENC		BIT(2)
294 
295 #define QEDE_CSUM_ERROR			BIT(0)
296 #define QEDE_CSUM_UNNECESSARY		BIT(1)
297 #define QEDE_TUNN_CSUM_UNNECESSARY	BIT(2)
298 
299 #define QEDE_SP_RX_MODE			1
300 #define QEDE_SP_VXLAN_PORT_CONFIG	2
301 #define QEDE_SP_GENEVE_PORT_CONFIG	3
302 
303 union qede_reload_args {
304 	u16 mtu;
305 };
306 
307 void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level);
308 void qede_set_ethtool_ops(struct net_device *netdev);
309 void qede_reload(struct qede_dev *edev,
310 		 void (*func)(struct qede_dev *edev,
311 			      union qede_reload_args *args),
312 		 union qede_reload_args *args);
313 int qede_change_mtu(struct net_device *dev, int new_mtu);
314 void qede_fill_by_demand_stats(struct qede_dev *edev);
315 bool qede_has_rx_work(struct qede_rx_queue *rxq);
316 int qede_txq_has_work(struct qede_tx_queue *txq);
317 void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, struct qede_dev *edev,
318 			     u8 count);
319 
320 #define RX_RING_SIZE_POW	13
321 #define RX_RING_SIZE		((u16)BIT(RX_RING_SIZE_POW))
322 #define NUM_RX_BDS_MAX		(RX_RING_SIZE - 1)
323 #define NUM_RX_BDS_MIN		128
324 #define NUM_RX_BDS_DEF		NUM_RX_BDS_MAX
325 
326 #define TX_RING_SIZE_POW	13
327 #define TX_RING_SIZE		((u16)BIT(TX_RING_SIZE_POW))
328 #define NUM_TX_BDS_MAX		(TX_RING_SIZE - 1)
329 #define NUM_TX_BDS_MIN		128
330 #define NUM_TX_BDS_DEF		NUM_TX_BDS_MAX
331 
332 #define QEDE_RX_HDR_SIZE	256
333 #define	for_each_rss(i) for (i = 0; i < edev->num_rss; i++)
334 
335 #endif /* _QEDE_H_ */
336