1 /* QLogic qed NIC Driver
2  * Copyright (c) 2015-2017  QLogic Corporation
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and /or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include <linux/types.h>
34 #include <asm/byteorder.h>
35 #include <linux/bitops.h>
36 #include <linux/errno.h>
37 #include <linux/kernel.h>
38 #include <linux/string.h>
39 #include "qed.h"
40 #include <linux/qed/qed_chain.h>
41 #include "qed_cxt.h"
42 #include "qed_dcbx.h"
43 #include "qed_hsi.h"
44 #include "qed_hw.h"
45 #include "qed_int.h"
46 #include "qed_reg_addr.h"
47 #include "qed_sp.h"
48 #include "qed_sriov.h"
49 
50 int qed_sp_init_request(struct qed_hwfn *p_hwfn,
51 			struct qed_spq_entry **pp_ent,
52 			u8 cmd, u8 protocol, struct qed_sp_init_data *p_data)
53 {
54 	u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
55 	struct qed_spq_entry *p_ent = NULL;
56 	int rc;
57 
58 	if (!pp_ent)
59 		return -ENOMEM;
60 
61 	rc = qed_spq_get_entry(p_hwfn, pp_ent);
62 
63 	if (rc)
64 		return rc;
65 
66 	p_ent = *pp_ent;
67 
68 	p_ent->elem.hdr.cid		= cpu_to_le32(opaque_cid);
69 	p_ent->elem.hdr.cmd_id		= cmd;
70 	p_ent->elem.hdr.protocol_id	= protocol;
71 
72 	p_ent->priority		= QED_SPQ_PRIORITY_NORMAL;
73 	p_ent->comp_mode	= p_data->comp_mode;
74 	p_ent->comp_done.done	= 0;
75 
76 	switch (p_ent->comp_mode) {
77 	case QED_SPQ_MODE_EBLOCK:
78 		p_ent->comp_cb.cookie = &p_ent->comp_done;
79 		break;
80 
81 	case QED_SPQ_MODE_BLOCK:
82 		if (!p_data->p_comp_data)
83 			return -EINVAL;
84 
85 		p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
86 		break;
87 
88 	case QED_SPQ_MODE_CB:
89 		if (!p_data->p_comp_data)
90 			p_ent->comp_cb.function = NULL;
91 		else
92 			p_ent->comp_cb = *p_data->p_comp_data;
93 		break;
94 
95 	default:
96 		DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
97 			  p_ent->comp_mode);
98 		return -EINVAL;
99 	}
100 
101 	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
102 		   "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
103 		   opaque_cid, cmd, protocol,
104 		   (unsigned long)&p_ent->ramrod,
105 		   D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
106 			   QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
107 			   "MODE_CB"));
108 
109 	memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
110 
111 	return 0;
112 }
113 
114 static enum tunnel_clss qed_tunn_clss_to_fw_clss(u8 type)
115 {
116 	switch (type) {
117 	case QED_TUNN_CLSS_MAC_VLAN:
118 		return TUNNEL_CLSS_MAC_VLAN;
119 	case QED_TUNN_CLSS_MAC_VNI:
120 		return TUNNEL_CLSS_MAC_VNI;
121 	case QED_TUNN_CLSS_INNER_MAC_VLAN:
122 		return TUNNEL_CLSS_INNER_MAC_VLAN;
123 	case QED_TUNN_CLSS_INNER_MAC_VNI:
124 		return TUNNEL_CLSS_INNER_MAC_VNI;
125 	case QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE:
126 		return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE;
127 	default:
128 		return TUNNEL_CLSS_MAC_VLAN;
129 	}
130 }
131 
132 static void
133 qed_set_pf_update_tunn_mode(struct qed_tunnel_info *p_tun,
134 			    struct qed_tunnel_info *p_src, bool b_pf_start)
135 {
136 	if (p_src->vxlan.b_update_mode || b_pf_start)
137 		p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled;
138 
139 	if (p_src->l2_gre.b_update_mode || b_pf_start)
140 		p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled;
141 
142 	if (p_src->ip_gre.b_update_mode || b_pf_start)
143 		p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled;
144 
145 	if (p_src->l2_geneve.b_update_mode || b_pf_start)
146 		p_tun->l2_geneve.b_mode_enabled =
147 		    p_src->l2_geneve.b_mode_enabled;
148 
149 	if (p_src->ip_geneve.b_update_mode || b_pf_start)
150 		p_tun->ip_geneve.b_mode_enabled =
151 		    p_src->ip_geneve.b_mode_enabled;
152 }
153 
154 static void qed_set_tunn_cls_info(struct qed_tunnel_info *p_tun,
155 				  struct qed_tunnel_info *p_src)
156 {
157 	enum tunnel_clss type;
158 
159 	p_tun->b_update_rx_cls = p_src->b_update_rx_cls;
160 	p_tun->b_update_tx_cls = p_src->b_update_tx_cls;
161 
162 	type = qed_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls);
163 	p_tun->vxlan.tun_cls = type;
164 	type = qed_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls);
165 	p_tun->l2_gre.tun_cls = type;
166 	type = qed_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls);
167 	p_tun->ip_gre.tun_cls = type;
168 	type = qed_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls);
169 	p_tun->l2_geneve.tun_cls = type;
170 	type = qed_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls);
171 	p_tun->ip_geneve.tun_cls = type;
172 }
173 
174 static void qed_set_tunn_ports(struct qed_tunnel_info *p_tun,
175 			       struct qed_tunnel_info *p_src)
176 {
177 	p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port;
178 	p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port;
179 
180 	if (p_src->geneve_port.b_update_port)
181 		p_tun->geneve_port.port = p_src->geneve_port.port;
182 
183 	if (p_src->vxlan_port.b_update_port)
184 		p_tun->vxlan_port.port = p_src->vxlan_port.port;
185 }
186 
187 static void
188 __qed_set_ramrod_tunnel_param(u8 *p_tunn_cls,
189 			      struct qed_tunn_update_type *tun_type)
190 {
191 	*p_tunn_cls = tun_type->tun_cls;
192 }
193 
194 static void
195 qed_set_ramrod_tunnel_param(u8 *p_tunn_cls,
196 			    struct qed_tunn_update_type *tun_type,
197 			    u8 *p_update_port,
198 			    __le16 *p_port,
199 			    struct qed_tunn_update_udp_port *p_udp_port)
200 {
201 	__qed_set_ramrod_tunnel_param(p_tunn_cls, tun_type);
202 	if (p_udp_port->b_update_port) {
203 		*p_update_port = 1;
204 		*p_port = cpu_to_le16(p_udp_port->port);
205 	}
206 }
207 
208 static void
209 qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
210 			      struct qed_tunnel_info *p_src,
211 			      struct pf_update_tunnel_config *p_tunn_cfg)
212 {
213 	struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel;
214 
215 	qed_set_pf_update_tunn_mode(p_tun, p_src, false);
216 	qed_set_tunn_cls_info(p_tun, p_src);
217 	qed_set_tunn_ports(p_tun, p_src);
218 
219 	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
220 				    &p_tun->vxlan,
221 				    &p_tunn_cfg->set_vxlan_udp_port_flg,
222 				    &p_tunn_cfg->vxlan_udp_port,
223 				    &p_tun->vxlan_port);
224 
225 	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
226 				    &p_tun->l2_geneve,
227 				    &p_tunn_cfg->set_geneve_udp_port_flg,
228 				    &p_tunn_cfg->geneve_udp_port,
229 				    &p_tun->geneve_port);
230 
231 	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
232 				      &p_tun->ip_geneve);
233 
234 	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
235 				      &p_tun->l2_gre);
236 
237 	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
238 				      &p_tun->ip_gre);
239 
240 	p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls;
241 }
242 
243 static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
244 				 struct qed_ptt *p_ptt,
245 				 struct qed_tunnel_info *p_tun)
246 {
247 	qed_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled,
248 			   p_tun->ip_gre.b_mode_enabled);
249 	qed_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled);
250 
251 	qed_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled,
252 			      p_tun->ip_geneve.b_mode_enabled);
253 }
254 
255 static void qed_set_hw_tunn_mode_port(struct qed_hwfn *p_hwfn,
256 				      struct qed_ptt *p_ptt,
257 				      struct qed_tunnel_info *p_tunn)
258 {
259 	if (p_tunn->vxlan_port.b_update_port)
260 		qed_set_vxlan_dest_port(p_hwfn, p_ptt,
261 					p_tunn->vxlan_port.port);
262 
263 	if (p_tunn->geneve_port.b_update_port)
264 		qed_set_geneve_dest_port(p_hwfn, p_ptt,
265 					 p_tunn->geneve_port.port);
266 
267 	qed_set_hw_tunn_mode(p_hwfn, p_ptt, p_tunn);
268 }
269 
270 static void
271 qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
272 			     struct qed_tunnel_info *p_src,
273 			     struct pf_start_tunnel_config *p_tunn_cfg)
274 {
275 	struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel;
276 
277 	if (!p_src)
278 		return;
279 
280 	qed_set_pf_update_tunn_mode(p_tun, p_src, true);
281 	qed_set_tunn_cls_info(p_tun, p_src);
282 	qed_set_tunn_ports(p_tun, p_src);
283 
284 	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
285 				    &p_tun->vxlan,
286 				    &p_tunn_cfg->set_vxlan_udp_port_flg,
287 				    &p_tunn_cfg->vxlan_udp_port,
288 				    &p_tun->vxlan_port);
289 
290 	qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
291 				    &p_tun->l2_geneve,
292 				    &p_tunn_cfg->set_geneve_udp_port_flg,
293 				    &p_tunn_cfg->geneve_udp_port,
294 				    &p_tun->geneve_port);
295 
296 	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
297 				      &p_tun->ip_geneve);
298 
299 	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
300 				      &p_tun->l2_gre);
301 
302 	__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
303 				      &p_tun->ip_gre);
304 }
305 
306 int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
307 		    struct qed_ptt *p_ptt,
308 		    struct qed_tunnel_info *p_tunn,
309 		    enum qed_mf_mode mode, bool allow_npar_tx_switch)
310 {
311 	struct pf_start_ramrod_data *p_ramrod = NULL;
312 	u16 sb = qed_int_get_sp_sb_id(p_hwfn);
313 	u8 sb_index = p_hwfn->p_eq->eq_sb_index;
314 	struct qed_spq_entry *p_ent = NULL;
315 	struct qed_sp_init_data init_data;
316 	int rc = -EINVAL;
317 	u8 page_cnt;
318 
319 	/* update initial eq producer */
320 	qed_eq_prod_update(p_hwfn,
321 			   qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));
322 
323 	memset(&init_data, 0, sizeof(init_data));
324 	init_data.cid = qed_spq_get_cid(p_hwfn);
325 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
326 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
327 
328 	rc = qed_sp_init_request(p_hwfn, &p_ent,
329 				 COMMON_RAMROD_PF_START,
330 				 PROTOCOLID_COMMON, &init_data);
331 	if (rc)
332 		return rc;
333 
334 	p_ramrod = &p_ent->ramrod.pf_start;
335 
336 	p_ramrod->event_ring_sb_id	= cpu_to_le16(sb);
337 	p_ramrod->event_ring_sb_index	= sb_index;
338 	p_ramrod->path_id		= QED_PATH_ID(p_hwfn);
339 	p_ramrod->dont_log_ramrods	= 0;
340 	p_ramrod->log_type_mask		= cpu_to_le16(0xf);
341 
342 	switch (mode) {
343 	case QED_MF_DEFAULT:
344 	case QED_MF_NPAR:
345 		p_ramrod->mf_mode = MF_NPAR;
346 		break;
347 	case QED_MF_OVLAN:
348 		p_ramrod->mf_mode = MF_OVLAN;
349 		break;
350 	default:
351 		DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
352 		p_ramrod->mf_mode = MF_NPAR;
353 	}
354 	p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
355 
356 	/* Place EQ address in RAMROD */
357 	DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
358 		       p_hwfn->p_eq->chain.pbl_sp.p_phys_table);
359 	page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
360 	p_ramrod->event_ring_num_pages = page_cnt;
361 	DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
362 		       p_hwfn->p_consq->chain.pbl_sp.p_phys_table);
363 
364 	qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config);
365 
366 	if (IS_MF_SI(p_hwfn))
367 		p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
368 
369 	switch (p_hwfn->hw_info.personality) {
370 	case QED_PCI_ETH:
371 		p_ramrod->personality = PERSONALITY_ETH;
372 		break;
373 	case QED_PCI_FCOE:
374 		p_ramrod->personality = PERSONALITY_FCOE;
375 		break;
376 	case QED_PCI_ISCSI:
377 		p_ramrod->personality = PERSONALITY_ISCSI;
378 		break;
379 	case QED_PCI_ETH_ROCE:
380 		p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
381 		break;
382 	default:
383 		DP_NOTICE(p_hwfn, "Unknown personality %d\n",
384 			  p_hwfn->hw_info.personality);
385 		p_ramrod->personality = PERSONALITY_ETH;
386 	}
387 
388 	if (p_hwfn->cdev->p_iov_info) {
389 		struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
390 
391 		p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
392 		p_ramrod->num_vfs = (u8) p_iov->total_vfs;
393 	}
394 	p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
395 	p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
396 
397 	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
398 		   "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
399 		   sb, sb_index, p_ramrod->outer_tag);
400 
401 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
402 
403 	if (p_tunn)
404 		qed_set_hw_tunn_mode_port(p_hwfn, p_ptt,
405 					  &p_hwfn->cdev->tunnel);
406 
407 	return rc;
408 }
409 
410 int qed_sp_pf_update(struct qed_hwfn *p_hwfn)
411 {
412 	struct qed_spq_entry *p_ent = NULL;
413 	struct qed_sp_init_data init_data;
414 	int rc = -EINVAL;
415 
416 	/* Get SPQ entry */
417 	memset(&init_data, 0, sizeof(init_data));
418 	init_data.cid = qed_spq_get_cid(p_hwfn);
419 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
420 	init_data.comp_mode = QED_SPQ_MODE_CB;
421 
422 	rc = qed_sp_init_request(p_hwfn, &p_ent,
423 				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
424 				 &init_data);
425 	if (rc)
426 		return rc;
427 
428 	qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
429 				      &p_ent->ramrod.pf_update);
430 
431 	return qed_spq_post(p_hwfn, p_ent, NULL);
432 }
433 
434 /* Set pf update ramrod command params */
435 int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
436 			      struct qed_ptt *p_ptt,
437 			      struct qed_tunnel_info *p_tunn,
438 			      enum spq_mode comp_mode,
439 			      struct qed_spq_comp_cb *p_comp_data)
440 {
441 	struct qed_spq_entry *p_ent = NULL;
442 	struct qed_sp_init_data init_data;
443 	int rc = -EINVAL;
444 
445 	if (IS_VF(p_hwfn->cdev))
446 		return qed_vf_pf_tunnel_param_update(p_hwfn, p_tunn);
447 
448 	if (!p_tunn)
449 		return -EINVAL;
450 
451 	/* Get SPQ entry */
452 	memset(&init_data, 0, sizeof(init_data));
453 	init_data.cid = qed_spq_get_cid(p_hwfn);
454 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
455 	init_data.comp_mode = comp_mode;
456 	init_data.p_comp_data = p_comp_data;
457 
458 	rc = qed_sp_init_request(p_hwfn, &p_ent,
459 				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
460 				 &init_data);
461 	if (rc)
462 		return rc;
463 
464 	qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
465 				      &p_ent->ramrod.pf_update.tunnel_config);
466 
467 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
468 	if (rc)
469 		return rc;
470 
471 	qed_set_hw_tunn_mode_port(p_hwfn, p_ptt, &p_hwfn->cdev->tunnel);
472 
473 	return rc;
474 }
475 
476 int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
477 {
478 	struct qed_spq_entry *p_ent = NULL;
479 	struct qed_sp_init_data init_data;
480 	int rc = -EINVAL;
481 
482 	/* Get SPQ entry */
483 	memset(&init_data, 0, sizeof(init_data));
484 	init_data.cid = qed_spq_get_cid(p_hwfn);
485 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
486 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
487 
488 	rc = qed_sp_init_request(p_hwfn, &p_ent,
489 				 COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
490 				 &init_data);
491 	if (rc)
492 		return rc;
493 
494 	return qed_spq_post(p_hwfn, p_ent, NULL);
495 }
496 
497 int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
498 {
499 	struct qed_spq_entry *p_ent = NULL;
500 	struct qed_sp_init_data init_data;
501 	int rc;
502 
503 	/* Get SPQ entry */
504 	memset(&init_data, 0, sizeof(init_data));
505 	init_data.cid = qed_spq_get_cid(p_hwfn);
506 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
507 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
508 
509 	rc = qed_sp_init_request(p_hwfn, &p_ent,
510 				 COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
511 				 &init_data);
512 	if (rc)
513 		return rc;
514 
515 	return qed_spq_post(p_hwfn, p_ent, NULL);
516 }
517 
518 int qed_sp_pf_update_stag(struct qed_hwfn *p_hwfn)
519 {
520 	struct qed_spq_entry *p_ent = NULL;
521 	struct qed_sp_init_data init_data;
522 	int rc = -EINVAL;
523 
524 	/* Get SPQ entry */
525 	memset(&init_data, 0, sizeof(init_data));
526 	init_data.cid = qed_spq_get_cid(p_hwfn);
527 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
528 	init_data.comp_mode = QED_SPQ_MODE_CB;
529 
530 	rc = qed_sp_init_request(p_hwfn, &p_ent,
531 				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
532 				 &init_data);
533 	if (rc)
534 		return rc;
535 
536 	p_ent->ramrod.pf_update.update_mf_vlan_flag = true;
537 	p_ent->ramrod.pf_update.mf_vlan = cpu_to_le16(p_hwfn->hw_info.ovlan);
538 
539 	return qed_spq_post(p_hwfn, p_ent, NULL);
540 }
541