1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/bitops.h> 36fe56b9e6SYuval Mintz #include <linux/errno.h> 37fe56b9e6SYuval Mintz #include <linux/kernel.h> 38fe56b9e6SYuval Mintz #include <linux/string.h> 39fe56b9e6SYuval Mintz #include "qed.h" 40fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 41fe56b9e6SYuval Mintz #include "qed_cxt.h" 4239651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 43fe56b9e6SYuval Mintz #include "qed_hsi.h" 44fe56b9e6SYuval Mintz #include "qed_hw.h" 45fe56b9e6SYuval Mintz #include "qed_int.h" 46fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 47fe56b9e6SYuval Mintz #include "qed_sp.h" 481408cc1fSYuval Mintz #include "qed_sriov.h" 49fe56b9e6SYuval Mintz 50fe56b9e6SYuval Mintz int qed_sp_init_request(struct qed_hwfn *p_hwfn, 51fe56b9e6SYuval Mintz struct qed_spq_entry **pp_ent, 521a635e48SYuval Mintz u8 cmd, u8 protocol, struct qed_sp_init_data *p_data) 53fe56b9e6SYuval Mintz { 5406f56b81SYuval Mintz u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid; 55fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 5606f56b81SYuval Mintz int rc; 57fe56b9e6SYuval Mintz 58fe56b9e6SYuval Mintz if (!pp_ent) 59fe56b9e6SYuval Mintz return -ENOMEM; 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz rc = qed_spq_get_entry(p_hwfn, pp_ent); 62fe56b9e6SYuval Mintz 631a635e48SYuval Mintz if (rc) 64fe56b9e6SYuval Mintz return rc; 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz p_ent = *pp_ent; 67fe56b9e6SYuval Mintz 68fe56b9e6SYuval Mintz p_ent->elem.hdr.cid = cpu_to_le32(opaque_cid); 69fe56b9e6SYuval Mintz p_ent->elem.hdr.cmd_id = cmd; 70fe56b9e6SYuval Mintz p_ent->elem.hdr.protocol_id = protocol; 71fe56b9e6SYuval Mintz 72fe56b9e6SYuval Mintz p_ent->priority = QED_SPQ_PRIORITY_NORMAL; 7306f56b81SYuval Mintz p_ent->comp_mode = p_data->comp_mode; 74fe56b9e6SYuval Mintz p_ent->comp_done.done = 0; 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz switch (p_ent->comp_mode) { 77fe56b9e6SYuval Mintz case QED_SPQ_MODE_EBLOCK: 78fe56b9e6SYuval Mintz p_ent->comp_cb.cookie = &p_ent->comp_done; 79fe56b9e6SYuval Mintz break; 80fe56b9e6SYuval Mintz 81fe56b9e6SYuval Mintz case QED_SPQ_MODE_BLOCK: 8206f56b81SYuval Mintz if (!p_data->p_comp_data) 83fe56b9e6SYuval Mintz return -EINVAL; 84fe56b9e6SYuval Mintz 8506f56b81SYuval Mintz p_ent->comp_cb.cookie = p_data->p_comp_data->cookie; 86fe56b9e6SYuval Mintz break; 87fe56b9e6SYuval Mintz 88fe56b9e6SYuval Mintz case QED_SPQ_MODE_CB: 8906f56b81SYuval Mintz if (!p_data->p_comp_data) 90fe56b9e6SYuval Mintz p_ent->comp_cb.function = NULL; 91fe56b9e6SYuval Mintz else 9206f56b81SYuval Mintz p_ent->comp_cb = *p_data->p_comp_data; 93fe56b9e6SYuval Mintz break; 94fe56b9e6SYuval Mintz 95fe56b9e6SYuval Mintz default: 96fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n", 97fe56b9e6SYuval Mintz p_ent->comp_mode); 98fe56b9e6SYuval Mintz return -EINVAL; 99fe56b9e6SYuval Mintz } 100fe56b9e6SYuval Mintz 101fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 102fe56b9e6SYuval Mintz "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n", 103fe56b9e6SYuval Mintz opaque_cid, cmd, protocol, 104fe56b9e6SYuval Mintz (unsigned long)&p_ent->ramrod, 105fe56b9e6SYuval Mintz D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK, 106fe56b9e6SYuval Mintz QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK", 107fe56b9e6SYuval Mintz "MODE_CB")); 10806f56b81SYuval Mintz 10906f56b81SYuval Mintz memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod)); 110fe56b9e6SYuval Mintz 111fe56b9e6SYuval Mintz return 0; 112fe56b9e6SYuval Mintz } 113fe56b9e6SYuval Mintz 11419968430SChopra, Manish static enum tunnel_clss qed_tunn_clss_to_fw_clss(u8 type) 115464f6645SManish Chopra { 116464f6645SManish Chopra switch (type) { 117464f6645SManish Chopra case QED_TUNN_CLSS_MAC_VLAN: 118464f6645SManish Chopra return TUNNEL_CLSS_MAC_VLAN; 119464f6645SManish Chopra case QED_TUNN_CLSS_MAC_VNI: 120464f6645SManish Chopra return TUNNEL_CLSS_MAC_VNI; 121464f6645SManish Chopra case QED_TUNN_CLSS_INNER_MAC_VLAN: 122464f6645SManish Chopra return TUNNEL_CLSS_INNER_MAC_VLAN; 123464f6645SManish Chopra case QED_TUNN_CLSS_INNER_MAC_VNI: 124464f6645SManish Chopra return TUNNEL_CLSS_INNER_MAC_VNI; 12519968430SChopra, Manish case QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE: 12619968430SChopra, Manish return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE; 127464f6645SManish Chopra default: 128464f6645SManish Chopra return TUNNEL_CLSS_MAC_VLAN; 129464f6645SManish Chopra } 130464f6645SManish Chopra } 131464f6645SManish Chopra 132464f6645SManish Chopra static void 13319968430SChopra, Manish qed_set_pf_update_tunn_mode(struct qed_tunnel_info *p_tun, 13419968430SChopra, Manish struct qed_tunnel_info *p_src, bool b_pf_start) 135464f6645SManish Chopra { 13619968430SChopra, Manish if (p_src->vxlan.b_update_mode || b_pf_start) 13719968430SChopra, Manish p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled; 138464f6645SManish Chopra 13919968430SChopra, Manish if (p_src->l2_gre.b_update_mode || b_pf_start) 14019968430SChopra, Manish p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled; 14119968430SChopra, Manish 14219968430SChopra, Manish if (p_src->ip_gre.b_update_mode || b_pf_start) 14319968430SChopra, Manish p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled; 14419968430SChopra, Manish 14519968430SChopra, Manish if (p_src->l2_geneve.b_update_mode || b_pf_start) 14619968430SChopra, Manish p_tun->l2_geneve.b_mode_enabled = 14719968430SChopra, Manish p_src->l2_geneve.b_mode_enabled; 14819968430SChopra, Manish 14919968430SChopra, Manish if (p_src->ip_geneve.b_update_mode || b_pf_start) 15019968430SChopra, Manish p_tun->ip_geneve.b_mode_enabled = 15119968430SChopra, Manish p_src->ip_geneve.b_mode_enabled; 152464f6645SManish Chopra } 153464f6645SManish Chopra 15419968430SChopra, Manish static void qed_set_tunn_cls_info(struct qed_tunnel_info *p_tun, 15519968430SChopra, Manish struct qed_tunnel_info *p_src) 15619968430SChopra, Manish { 15719968430SChopra, Manish enum tunnel_clss type; 15819968430SChopra, Manish 15919968430SChopra, Manish p_tun->b_update_rx_cls = p_src->b_update_rx_cls; 16019968430SChopra, Manish p_tun->b_update_tx_cls = p_src->b_update_tx_cls; 16119968430SChopra, Manish 16219968430SChopra, Manish type = qed_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls); 16319968430SChopra, Manish p_tun->vxlan.tun_cls = type; 16419968430SChopra, Manish type = qed_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls); 16519968430SChopra, Manish p_tun->l2_gre.tun_cls = type; 16619968430SChopra, Manish type = qed_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls); 16719968430SChopra, Manish p_tun->ip_gre.tun_cls = type; 16819968430SChopra, Manish type = qed_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls); 16919968430SChopra, Manish p_tun->l2_geneve.tun_cls = type; 17019968430SChopra, Manish type = qed_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls); 17119968430SChopra, Manish p_tun->ip_geneve.tun_cls = type; 172464f6645SManish Chopra } 173464f6645SManish Chopra 17419968430SChopra, Manish static void qed_set_tunn_ports(struct qed_tunnel_info *p_tun, 17519968430SChopra, Manish struct qed_tunnel_info *p_src) 17619968430SChopra, Manish { 17719968430SChopra, Manish p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port; 17819968430SChopra, Manish p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port; 17919968430SChopra, Manish 18019968430SChopra, Manish if (p_src->geneve_port.b_update_port) 18119968430SChopra, Manish p_tun->geneve_port.port = p_src->geneve_port.port; 18219968430SChopra, Manish 18319968430SChopra, Manish if (p_src->vxlan_port.b_update_port) 18419968430SChopra, Manish p_tun->vxlan_port.port = p_src->vxlan_port.port; 185464f6645SManish Chopra } 186464f6645SManish Chopra 18719968430SChopra, Manish static void 1887b6859fbSMintz, Yuval __qed_set_ramrod_tunnel_param(u8 *p_tunn_cls, 18919968430SChopra, Manish struct qed_tunn_update_type *tun_type) 19019968430SChopra, Manish { 19119968430SChopra, Manish *p_tunn_cls = tun_type->tun_cls; 192464f6645SManish Chopra } 193464f6645SManish Chopra 19419968430SChopra, Manish static void 1957b6859fbSMintz, Yuval qed_set_ramrod_tunnel_param(u8 *p_tunn_cls, 19619968430SChopra, Manish struct qed_tunn_update_type *tun_type, 1977b6859fbSMintz, Yuval u8 *p_update_port, 1987b6859fbSMintz, Yuval __le16 *p_port, 19919968430SChopra, Manish struct qed_tunn_update_udp_port *p_udp_port) 20019968430SChopra, Manish { 2017b6859fbSMintz, Yuval __qed_set_ramrod_tunnel_param(p_tunn_cls, tun_type); 20219968430SChopra, Manish if (p_udp_port->b_update_port) { 20319968430SChopra, Manish *p_update_port = 1; 20419968430SChopra, Manish *p_port = cpu_to_le16(p_udp_port->port); 205464f6645SManish Chopra } 206464f6645SManish Chopra } 207464f6645SManish Chopra 208464f6645SManish Chopra static void 209464f6645SManish Chopra qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn, 21019968430SChopra, Manish struct qed_tunnel_info *p_src, 211464f6645SManish Chopra struct pf_update_tunnel_config *p_tunn_cfg) 212464f6645SManish Chopra { 21319968430SChopra, Manish struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel; 214464f6645SManish Chopra 21519968430SChopra, Manish qed_set_pf_update_tunn_mode(p_tun, p_src, false); 21619968430SChopra, Manish qed_set_tunn_cls_info(p_tun, p_src); 21719968430SChopra, Manish qed_set_tunn_ports(p_tun, p_src); 218464f6645SManish Chopra 21919968430SChopra, Manish qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan, 22019968430SChopra, Manish &p_tun->vxlan, 22119968430SChopra, Manish &p_tunn_cfg->set_vxlan_udp_port_flg, 22219968430SChopra, Manish &p_tunn_cfg->vxlan_udp_port, 22319968430SChopra, Manish &p_tun->vxlan_port); 224464f6645SManish Chopra 22519968430SChopra, Manish qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve, 22619968430SChopra, Manish &p_tun->l2_geneve, 22719968430SChopra, Manish &p_tunn_cfg->set_geneve_udp_port_flg, 22819968430SChopra, Manish &p_tunn_cfg->geneve_udp_port, 22919968430SChopra, Manish &p_tun->geneve_port); 230464f6645SManish Chopra 23119968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve, 23219968430SChopra, Manish &p_tun->ip_geneve); 233464f6645SManish Chopra 23419968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre, 23519968430SChopra, Manish &p_tun->l2_gre); 236464f6645SManish Chopra 23719968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre, 23819968430SChopra, Manish &p_tun->ip_gre); 239464f6645SManish Chopra 24019968430SChopra, Manish p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls; 241464f6645SManish Chopra } 242464f6645SManish Chopra 243464f6645SManish Chopra static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn, 244464f6645SManish Chopra struct qed_ptt *p_ptt, 24519968430SChopra, Manish struct qed_tunnel_info *p_tun) 246464f6645SManish Chopra { 24719968430SChopra, Manish qed_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled, 24819968430SChopra, Manish p_tun->ip_gre.b_mode_enabled); 24919968430SChopra, Manish qed_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled); 250464f6645SManish Chopra 25119968430SChopra, Manish qed_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled, 25219968430SChopra, Manish p_tun->ip_geneve.b_mode_enabled); 25319968430SChopra, Manish } 254464f6645SManish Chopra 25519968430SChopra, Manish static void qed_set_hw_tunn_mode_port(struct qed_hwfn *p_hwfn, 2564f64675fSManish Chopra struct qed_ptt *p_ptt, 25719968430SChopra, Manish struct qed_tunnel_info *p_tunn) 25819968430SChopra, Manish { 25919968430SChopra, Manish if (p_tunn->vxlan_port.b_update_port) 2604f64675fSManish Chopra qed_set_vxlan_dest_port(p_hwfn, p_ptt, 26119968430SChopra, Manish p_tunn->vxlan_port.port); 262464f6645SManish Chopra 26319968430SChopra, Manish if (p_tunn->geneve_port.b_update_port) 2644f64675fSManish Chopra qed_set_geneve_dest_port(p_hwfn, p_ptt, 26519968430SChopra, Manish p_tunn->geneve_port.port); 266464f6645SManish Chopra 2674f64675fSManish Chopra qed_set_hw_tunn_mode(p_hwfn, p_ptt, p_tunn); 268464f6645SManish Chopra } 269464f6645SManish Chopra 270464f6645SManish Chopra static void 271464f6645SManish Chopra qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn, 27219968430SChopra, Manish struct qed_tunnel_info *p_src, 273464f6645SManish Chopra struct pf_start_tunnel_config *p_tunn_cfg) 274464f6645SManish Chopra { 27519968430SChopra, Manish struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel; 276464f6645SManish Chopra 277464f6645SManish Chopra if (!p_src) 278464f6645SManish Chopra return; 279464f6645SManish Chopra 28019968430SChopra, Manish qed_set_pf_update_tunn_mode(p_tun, p_src, true); 28119968430SChopra, Manish qed_set_tunn_cls_info(p_tun, p_src); 28219968430SChopra, Manish qed_set_tunn_ports(p_tun, p_src); 283464f6645SManish Chopra 28419968430SChopra, Manish qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan, 28519968430SChopra, Manish &p_tun->vxlan, 28619968430SChopra, Manish &p_tunn_cfg->set_vxlan_udp_port_flg, 28719968430SChopra, Manish &p_tunn_cfg->vxlan_udp_port, 28819968430SChopra, Manish &p_tun->vxlan_port); 289464f6645SManish Chopra 29019968430SChopra, Manish qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve, 29119968430SChopra, Manish &p_tun->l2_geneve, 29219968430SChopra, Manish &p_tunn_cfg->set_geneve_udp_port_flg, 29319968430SChopra, Manish &p_tunn_cfg->geneve_udp_port, 29419968430SChopra, Manish &p_tun->geneve_port); 295464f6645SManish Chopra 29619968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve, 29719968430SChopra, Manish &p_tun->ip_geneve); 298464f6645SManish Chopra 29919968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre, 30019968430SChopra, Manish &p_tun->l2_gre); 301464f6645SManish Chopra 30219968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre, 30319968430SChopra, Manish &p_tun->ip_gre); 304464f6645SManish Chopra } 305464f6645SManish Chopra 306fe56b9e6SYuval Mintz int qed_sp_pf_start(struct qed_hwfn *p_hwfn, 3074f64675fSManish Chopra struct qed_ptt *p_ptt, 30819968430SChopra, Manish struct qed_tunnel_info *p_tunn, 309831bfb0eSYuval Mintz enum qed_mf_mode mode, bool allow_npar_tx_switch) 310fe56b9e6SYuval Mintz { 311fe56b9e6SYuval Mintz struct pf_start_ramrod_data *p_ramrod = NULL; 312fe56b9e6SYuval Mintz u16 sb = qed_int_get_sp_sb_id(p_hwfn); 313fe56b9e6SYuval Mintz u8 sb_index = p_hwfn->p_eq->eq_sb_index; 314fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 31506f56b81SYuval Mintz struct qed_sp_init_data init_data; 316fe56b9e6SYuval Mintz int rc = -EINVAL; 317a91eb52aSYuval Mintz u8 page_cnt; 318fe56b9e6SYuval Mintz 319fe56b9e6SYuval Mintz /* update initial eq producer */ 320fe56b9e6SYuval Mintz qed_eq_prod_update(p_hwfn, 321fe56b9e6SYuval Mintz qed_chain_get_prod_idx(&p_hwfn->p_eq->chain)); 322fe56b9e6SYuval Mintz 32306f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 32406f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 32506f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 32606f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 327fe56b9e6SYuval Mintz 32806f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 329fe56b9e6SYuval Mintz COMMON_RAMROD_PF_START, 3301a635e48SYuval Mintz PROTOCOLID_COMMON, &init_data); 331fe56b9e6SYuval Mintz if (rc) 332fe56b9e6SYuval Mintz return rc; 333fe56b9e6SYuval Mintz 334fe56b9e6SYuval Mintz p_ramrod = &p_ent->ramrod.pf_start; 335fe56b9e6SYuval Mintz 336fe56b9e6SYuval Mintz p_ramrod->event_ring_sb_id = cpu_to_le16(sb); 337fe56b9e6SYuval Mintz p_ramrod->event_ring_sb_index = sb_index; 338fe56b9e6SYuval Mintz p_ramrod->path_id = QED_PATH_ID(p_hwfn); 339fe56b9e6SYuval Mintz p_ramrod->dont_log_ramrods = 0; 340fe56b9e6SYuval Mintz p_ramrod->log_type_mask = cpu_to_le16(0xf); 341351a4dedSYuval Mintz 342fc48b7a6SYuval Mintz switch (mode) { 343fc48b7a6SYuval Mintz case QED_MF_DEFAULT: 344fc48b7a6SYuval Mintz case QED_MF_NPAR: 345fc48b7a6SYuval Mintz p_ramrod->mf_mode = MF_NPAR; 346fc48b7a6SYuval Mintz break; 347fc48b7a6SYuval Mintz case QED_MF_OVLAN: 348fc48b7a6SYuval Mintz p_ramrod->mf_mode = MF_OVLAN; 349fc48b7a6SYuval Mintz break; 350fc48b7a6SYuval Mintz default: 351fc48b7a6SYuval Mintz DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 352fc48b7a6SYuval Mintz p_ramrod->mf_mode = MF_NPAR; 353fc48b7a6SYuval Mintz } 354da090917STomer Tayar 355da090917STomer Tayar p_ramrod->outer_tag_config.outer_tag.tci = 356da090917STomer Tayar cpu_to_le16(p_hwfn->hw_info.ovlan); 357fe56b9e6SYuval Mintz 358fe56b9e6SYuval Mintz /* Place EQ address in RAMROD */ 35994494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr, 3606d937acfSMintz, Yuval p_hwfn->p_eq->chain.pbl_sp.p_phys_table); 361a91eb52aSYuval Mintz page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain); 362a91eb52aSYuval Mintz p_ramrod->event_ring_num_pages = page_cnt; 36394494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr, 3646d937acfSMintz, Yuval p_hwfn->p_consq->chain.pbl_sp.p_phys_table); 365fe56b9e6SYuval Mintz 3661a635e48SYuval Mintz qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config); 367fe56b9e6SYuval Mintz 368831bfb0eSYuval Mintz if (IS_MF_SI(p_hwfn)) 369831bfb0eSYuval Mintz p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch; 370831bfb0eSYuval Mintz 371c5ac9319SYuval Mintz switch (p_hwfn->hw_info.personality) { 372c5ac9319SYuval Mintz case QED_PCI_ETH: 373c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_ETH; 374c5ac9319SYuval Mintz break; 3751e128c81SArun Easi case QED_PCI_FCOE: 3761e128c81SArun Easi p_ramrod->personality = PERSONALITY_FCOE; 3771e128c81SArun Easi break; 378c5ac9319SYuval Mintz case QED_PCI_ISCSI: 379c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_ISCSI; 380c5ac9319SYuval Mintz break; 381c5ac9319SYuval Mintz case QED_PCI_ETH_ROCE: 382e0a8f9deSMichal Kalderon case QED_PCI_ETH_IWARP: 383c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_RDMA_AND_ETH; 384c5ac9319SYuval Mintz break; 385c5ac9319SYuval Mintz default: 3869165dabbSMasanari Iida DP_NOTICE(p_hwfn, "Unknown personality %d\n", 387c5ac9319SYuval Mintz p_hwfn->hw_info.personality); 388c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_ETH; 389c5ac9319SYuval Mintz } 390c5ac9319SYuval Mintz 3911408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 3921408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 3931408cc1fSYuval Mintz 3941408cc1fSYuval Mintz p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf; 3951408cc1fSYuval Mintz p_ramrod->num_vfs = (u8) p_iov->total_vfs; 3961408cc1fSYuval Mintz } 397351a4dedSYuval Mintz p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR; 398351a4dedSYuval Mintz p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR; 3991408cc1fSYuval Mintz 400fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 401da090917STomer Tayar "Setting event_ring_sb [id %04x index %02x], outer_tag.tci [%d]\n", 402da090917STomer Tayar sb, sb_index, p_ramrod->outer_tag_config.outer_tag.tci); 403fe56b9e6SYuval Mintz 404c0f31a05SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 405c0f31a05SManish Chopra 40619968430SChopra, Manish if (p_tunn) 4074f64675fSManish Chopra qed_set_hw_tunn_mode_port(p_hwfn, p_ptt, 4084f64675fSManish Chopra &p_hwfn->cdev->tunnel); 409c0f31a05SManish Chopra 410c0f31a05SManish Chopra return rc; 411fe56b9e6SYuval Mintz } 412fe56b9e6SYuval Mintz 41339651abdSSudarsana Reddy Kalluru int qed_sp_pf_update(struct qed_hwfn *p_hwfn) 41439651abdSSudarsana Reddy Kalluru { 41539651abdSSudarsana Reddy Kalluru struct qed_spq_entry *p_ent = NULL; 41639651abdSSudarsana Reddy Kalluru struct qed_sp_init_data init_data; 41739651abdSSudarsana Reddy Kalluru int rc = -EINVAL; 41839651abdSSudarsana Reddy Kalluru 41939651abdSSudarsana Reddy Kalluru /* Get SPQ entry */ 42039651abdSSudarsana Reddy Kalluru memset(&init_data, 0, sizeof(init_data)); 42139651abdSSudarsana Reddy Kalluru init_data.cid = qed_spq_get_cid(p_hwfn); 42239651abdSSudarsana Reddy Kalluru init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 42339651abdSSudarsana Reddy Kalluru init_data.comp_mode = QED_SPQ_MODE_CB; 42439651abdSSudarsana Reddy Kalluru 42539651abdSSudarsana Reddy Kalluru rc = qed_sp_init_request(p_hwfn, &p_ent, 42639651abdSSudarsana Reddy Kalluru COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 42739651abdSSudarsana Reddy Kalluru &init_data); 42839651abdSSudarsana Reddy Kalluru if (rc) 42939651abdSSudarsana Reddy Kalluru return rc; 43039651abdSSudarsana Reddy Kalluru 43139651abdSSudarsana Reddy Kalluru qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results, 43239651abdSSudarsana Reddy Kalluru &p_ent->ramrod.pf_update); 43339651abdSSudarsana Reddy Kalluru 43439651abdSSudarsana Reddy Kalluru return qed_spq_post(p_hwfn, p_ent, NULL); 43539651abdSSudarsana Reddy Kalluru } 43639651abdSSudarsana Reddy Kalluru 437464f6645SManish Chopra /* Set pf update ramrod command params */ 438464f6645SManish Chopra int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn, 4394f64675fSManish Chopra struct qed_ptt *p_ptt, 44019968430SChopra, Manish struct qed_tunnel_info *p_tunn, 441464f6645SManish Chopra enum spq_mode comp_mode, 442464f6645SManish Chopra struct qed_spq_comp_cb *p_comp_data) 443464f6645SManish Chopra { 444464f6645SManish Chopra struct qed_spq_entry *p_ent = NULL; 445464f6645SManish Chopra struct qed_sp_init_data init_data; 446464f6645SManish Chopra int rc = -EINVAL; 447464f6645SManish Chopra 448eaf3c0c6SChopra, Manish if (IS_VF(p_hwfn->cdev)) 449eaf3c0c6SChopra, Manish return qed_vf_pf_tunnel_param_update(p_hwfn, p_tunn); 450eaf3c0c6SChopra, Manish 45119968430SChopra, Manish if (!p_tunn) 45219968430SChopra, Manish return -EINVAL; 45319968430SChopra, Manish 454464f6645SManish Chopra /* Get SPQ entry */ 455464f6645SManish Chopra memset(&init_data, 0, sizeof(init_data)); 456464f6645SManish Chopra init_data.cid = qed_spq_get_cid(p_hwfn); 457464f6645SManish Chopra init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 458464f6645SManish Chopra init_data.comp_mode = comp_mode; 459464f6645SManish Chopra init_data.p_comp_data = p_comp_data; 460464f6645SManish Chopra 461464f6645SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 462464f6645SManish Chopra COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 463464f6645SManish Chopra &init_data); 464464f6645SManish Chopra if (rc) 465464f6645SManish Chopra return rc; 466464f6645SManish Chopra 467464f6645SManish Chopra qed_tunn_set_pf_update_params(p_hwfn, p_tunn, 468464f6645SManish Chopra &p_ent->ramrod.pf_update.tunnel_config); 469464f6645SManish Chopra 470464f6645SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 471464f6645SManish Chopra if (rc) 472464f6645SManish Chopra return rc; 473464f6645SManish Chopra 4744f64675fSManish Chopra qed_set_hw_tunn_mode_port(p_hwfn, p_ptt, &p_hwfn->cdev->tunnel); 475464f6645SManish Chopra 476464f6645SManish Chopra return rc; 477464f6645SManish Chopra } 478464f6645SManish Chopra 479fe56b9e6SYuval Mintz int qed_sp_pf_stop(struct qed_hwfn *p_hwfn) 480fe56b9e6SYuval Mintz { 481fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 48206f56b81SYuval Mintz struct qed_sp_init_data init_data; 483fe56b9e6SYuval Mintz int rc = -EINVAL; 484fe56b9e6SYuval Mintz 48506f56b81SYuval Mintz /* Get SPQ entry */ 48606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 48706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 48806f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 48906f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 490fe56b9e6SYuval Mintz 49106f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 492fe56b9e6SYuval Mintz COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON, 49306f56b81SYuval Mintz &init_data); 494fe56b9e6SYuval Mintz if (rc) 495fe56b9e6SYuval Mintz return rc; 496fe56b9e6SYuval Mintz 497fe56b9e6SYuval Mintz return qed_spq_post(p_hwfn, p_ent, NULL); 498fe56b9e6SYuval Mintz } 49903dc76caSSudarsana Reddy Kalluru 50003dc76caSSudarsana Reddy Kalluru int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn) 50103dc76caSSudarsana Reddy Kalluru { 50203dc76caSSudarsana Reddy Kalluru struct qed_spq_entry *p_ent = NULL; 50303dc76caSSudarsana Reddy Kalluru struct qed_sp_init_data init_data; 50403dc76caSSudarsana Reddy Kalluru int rc; 50503dc76caSSudarsana Reddy Kalluru 50603dc76caSSudarsana Reddy Kalluru /* Get SPQ entry */ 50703dc76caSSudarsana Reddy Kalluru memset(&init_data, 0, sizeof(init_data)); 50803dc76caSSudarsana Reddy Kalluru init_data.cid = qed_spq_get_cid(p_hwfn); 50903dc76caSSudarsana Reddy Kalluru init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 51003dc76caSSudarsana Reddy Kalluru init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 51103dc76caSSudarsana Reddy Kalluru 51203dc76caSSudarsana Reddy Kalluru rc = qed_sp_init_request(p_hwfn, &p_ent, 51303dc76caSSudarsana Reddy Kalluru COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON, 51403dc76caSSudarsana Reddy Kalluru &init_data); 51503dc76caSSudarsana Reddy Kalluru if (rc) 51603dc76caSSudarsana Reddy Kalluru return rc; 51703dc76caSSudarsana Reddy Kalluru 51803dc76caSSudarsana Reddy Kalluru return qed_spq_post(p_hwfn, p_ent, NULL); 51903dc76caSSudarsana Reddy Kalluru } 5202a351fd9SMintz, Yuval 5212a351fd9SMintz, Yuval int qed_sp_pf_update_stag(struct qed_hwfn *p_hwfn) 5222a351fd9SMintz, Yuval { 5232a351fd9SMintz, Yuval struct qed_spq_entry *p_ent = NULL; 5242a351fd9SMintz, Yuval struct qed_sp_init_data init_data; 5252a351fd9SMintz, Yuval int rc = -EINVAL; 5262a351fd9SMintz, Yuval 5272a351fd9SMintz, Yuval /* Get SPQ entry */ 5282a351fd9SMintz, Yuval memset(&init_data, 0, sizeof(init_data)); 5292a351fd9SMintz, Yuval init_data.cid = qed_spq_get_cid(p_hwfn); 5302a351fd9SMintz, Yuval init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 5312a351fd9SMintz, Yuval init_data.comp_mode = QED_SPQ_MODE_CB; 5322a351fd9SMintz, Yuval 5332a351fd9SMintz, Yuval rc = qed_sp_init_request(p_hwfn, &p_ent, 5342a351fd9SMintz, Yuval COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 5352a351fd9SMintz, Yuval &init_data); 5362a351fd9SMintz, Yuval if (rc) 5372a351fd9SMintz, Yuval return rc; 5382a351fd9SMintz, Yuval 5392a351fd9SMintz, Yuval p_ent->ramrod.pf_update.update_mf_vlan_flag = true; 5402a351fd9SMintz, Yuval p_ent->ramrod.pf_update.mf_vlan = cpu_to_le16(p_hwfn->hw_info.ovlan); 5412a351fd9SMintz, Yuval 5422a351fd9SMintz, Yuval return qed_spq_post(p_hwfn, p_ent, NULL); 5432a351fd9SMintz, Yuval } 544