1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver
2fe56b9e6SYuval Mintz  * Copyright (c) 2015 QLogic Corporation
3fe56b9e6SYuval Mintz  *
4fe56b9e6SYuval Mintz  * This software is available under the terms of the GNU General Public License
5fe56b9e6SYuval Mintz  * (GPL) Version 2, available from the file COPYING in the main directory of
6fe56b9e6SYuval Mintz  * this source tree.
7fe56b9e6SYuval Mintz  */
8fe56b9e6SYuval Mintz 
9fe56b9e6SYuval Mintz #include <linux/types.h>
10fe56b9e6SYuval Mintz #include <asm/byteorder.h>
11fe56b9e6SYuval Mintz #include <linux/bitops.h>
12fe56b9e6SYuval Mintz #include <linux/errno.h>
13fe56b9e6SYuval Mintz #include <linux/kernel.h>
14fe56b9e6SYuval Mintz #include <linux/string.h>
15fe56b9e6SYuval Mintz #include "qed.h"
16fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h>
17fe56b9e6SYuval Mintz #include "qed_cxt.h"
1839651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h"
19fe56b9e6SYuval Mintz #include "qed_hsi.h"
20fe56b9e6SYuval Mintz #include "qed_hw.h"
21fe56b9e6SYuval Mintz #include "qed_int.h"
22fe56b9e6SYuval Mintz #include "qed_reg_addr.h"
23fe56b9e6SYuval Mintz #include "qed_sp.h"
241408cc1fSYuval Mintz #include "qed_sriov.h"
25fe56b9e6SYuval Mintz 
26fe56b9e6SYuval Mintz int qed_sp_init_request(struct qed_hwfn *p_hwfn,
27fe56b9e6SYuval Mintz 			struct qed_spq_entry **pp_ent,
28fe56b9e6SYuval Mintz 			u8 cmd,
29fe56b9e6SYuval Mintz 			u8 protocol,
3006f56b81SYuval Mintz 			struct qed_sp_init_data *p_data)
31fe56b9e6SYuval Mintz {
3206f56b81SYuval Mintz 	u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
33fe56b9e6SYuval Mintz 	struct qed_spq_entry *p_ent = NULL;
3406f56b81SYuval Mintz 	int rc;
35fe56b9e6SYuval Mintz 
36fe56b9e6SYuval Mintz 	if (!pp_ent)
37fe56b9e6SYuval Mintz 		return -ENOMEM;
38fe56b9e6SYuval Mintz 
39fe56b9e6SYuval Mintz 	rc = qed_spq_get_entry(p_hwfn, pp_ent);
40fe56b9e6SYuval Mintz 
41fe56b9e6SYuval Mintz 	if (rc != 0)
42fe56b9e6SYuval Mintz 		return rc;
43fe56b9e6SYuval Mintz 
44fe56b9e6SYuval Mintz 	p_ent = *pp_ent;
45fe56b9e6SYuval Mintz 
46fe56b9e6SYuval Mintz 	p_ent->elem.hdr.cid		= cpu_to_le32(opaque_cid);
47fe56b9e6SYuval Mintz 	p_ent->elem.hdr.cmd_id		= cmd;
48fe56b9e6SYuval Mintz 	p_ent->elem.hdr.protocol_id	= protocol;
49fe56b9e6SYuval Mintz 
50fe56b9e6SYuval Mintz 	p_ent->priority		= QED_SPQ_PRIORITY_NORMAL;
5106f56b81SYuval Mintz 	p_ent->comp_mode	= p_data->comp_mode;
52fe56b9e6SYuval Mintz 	p_ent->comp_done.done	= 0;
53fe56b9e6SYuval Mintz 
54fe56b9e6SYuval Mintz 	switch (p_ent->comp_mode) {
55fe56b9e6SYuval Mintz 	case QED_SPQ_MODE_EBLOCK:
56fe56b9e6SYuval Mintz 		p_ent->comp_cb.cookie = &p_ent->comp_done;
57fe56b9e6SYuval Mintz 		break;
58fe56b9e6SYuval Mintz 
59fe56b9e6SYuval Mintz 	case QED_SPQ_MODE_BLOCK:
6006f56b81SYuval Mintz 		if (!p_data->p_comp_data)
61fe56b9e6SYuval Mintz 			return -EINVAL;
62fe56b9e6SYuval Mintz 
6306f56b81SYuval Mintz 		p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
64fe56b9e6SYuval Mintz 		break;
65fe56b9e6SYuval Mintz 
66fe56b9e6SYuval Mintz 	case QED_SPQ_MODE_CB:
6706f56b81SYuval Mintz 		if (!p_data->p_comp_data)
68fe56b9e6SYuval Mintz 			p_ent->comp_cb.function = NULL;
69fe56b9e6SYuval Mintz 		else
7006f56b81SYuval Mintz 			p_ent->comp_cb = *p_data->p_comp_data;
71fe56b9e6SYuval Mintz 		break;
72fe56b9e6SYuval Mintz 
73fe56b9e6SYuval Mintz 	default:
74fe56b9e6SYuval Mintz 		DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
75fe56b9e6SYuval Mintz 			  p_ent->comp_mode);
76fe56b9e6SYuval Mintz 		return -EINVAL;
77fe56b9e6SYuval Mintz 	}
78fe56b9e6SYuval Mintz 
79fe56b9e6SYuval Mintz 	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
80fe56b9e6SYuval Mintz 		   "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
81fe56b9e6SYuval Mintz 		   opaque_cid, cmd, protocol,
82fe56b9e6SYuval Mintz 		   (unsigned long)&p_ent->ramrod,
83fe56b9e6SYuval Mintz 		   D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
84fe56b9e6SYuval Mintz 			   QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
85fe56b9e6SYuval Mintz 			   "MODE_CB"));
8606f56b81SYuval Mintz 
8706f56b81SYuval Mintz 	memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
88fe56b9e6SYuval Mintz 
89fe56b9e6SYuval Mintz 	return 0;
90fe56b9e6SYuval Mintz }
91fe56b9e6SYuval Mintz 
92464f6645SManish Chopra static enum tunnel_clss qed_tunn_get_clss_type(u8 type)
93464f6645SManish Chopra {
94464f6645SManish Chopra 	switch (type) {
95464f6645SManish Chopra 	case QED_TUNN_CLSS_MAC_VLAN:
96464f6645SManish Chopra 		return TUNNEL_CLSS_MAC_VLAN;
97464f6645SManish Chopra 	case QED_TUNN_CLSS_MAC_VNI:
98464f6645SManish Chopra 		return TUNNEL_CLSS_MAC_VNI;
99464f6645SManish Chopra 	case QED_TUNN_CLSS_INNER_MAC_VLAN:
100464f6645SManish Chopra 		return TUNNEL_CLSS_INNER_MAC_VLAN;
101464f6645SManish Chopra 	case QED_TUNN_CLSS_INNER_MAC_VNI:
102464f6645SManish Chopra 		return TUNNEL_CLSS_INNER_MAC_VNI;
103464f6645SManish Chopra 	default:
104464f6645SManish Chopra 		return TUNNEL_CLSS_MAC_VLAN;
105464f6645SManish Chopra 	}
106464f6645SManish Chopra }
107464f6645SManish Chopra 
108464f6645SManish Chopra static void
109464f6645SManish Chopra qed_tunn_set_pf_fix_tunn_mode(struct qed_hwfn *p_hwfn,
110464f6645SManish Chopra 			      struct qed_tunn_update_params *p_src,
111464f6645SManish Chopra 			      struct pf_update_tunnel_config *p_tunn_cfg)
112464f6645SManish Chopra {
113464f6645SManish Chopra 	unsigned long cached_tunn_mode = p_hwfn->cdev->tunn_mode;
114464f6645SManish Chopra 	unsigned long update_mask = p_src->tunn_mode_update_mask;
115464f6645SManish Chopra 	unsigned long tunn_mode = p_src->tunn_mode;
116464f6645SManish Chopra 	unsigned long new_tunn_mode = 0;
117464f6645SManish Chopra 
118464f6645SManish Chopra 	if (test_bit(QED_MODE_L2GRE_TUNN, &update_mask)) {
119464f6645SManish Chopra 		if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
120464f6645SManish Chopra 			__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
121464f6645SManish Chopra 	} else {
122464f6645SManish Chopra 		if (test_bit(QED_MODE_L2GRE_TUNN, &cached_tunn_mode))
123464f6645SManish Chopra 			__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
124464f6645SManish Chopra 	}
125464f6645SManish Chopra 
126464f6645SManish Chopra 	if (test_bit(QED_MODE_IPGRE_TUNN, &update_mask)) {
127464f6645SManish Chopra 		if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
128464f6645SManish Chopra 			__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
129464f6645SManish Chopra 	} else {
130464f6645SManish Chopra 		if (test_bit(QED_MODE_IPGRE_TUNN, &cached_tunn_mode))
131464f6645SManish Chopra 			__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
132464f6645SManish Chopra 	}
133464f6645SManish Chopra 
134464f6645SManish Chopra 	if (test_bit(QED_MODE_VXLAN_TUNN, &update_mask)) {
135464f6645SManish Chopra 		if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
136464f6645SManish Chopra 			__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
137464f6645SManish Chopra 	} else {
138464f6645SManish Chopra 		if (test_bit(QED_MODE_VXLAN_TUNN, &cached_tunn_mode))
139464f6645SManish Chopra 			__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
140464f6645SManish Chopra 	}
141464f6645SManish Chopra 
142464f6645SManish Chopra 	if (p_src->update_geneve_udp_port) {
143464f6645SManish Chopra 		p_tunn_cfg->set_geneve_udp_port_flg = 1;
144464f6645SManish Chopra 		p_tunn_cfg->geneve_udp_port =
145464f6645SManish Chopra 				cpu_to_le16(p_src->geneve_udp_port);
146464f6645SManish Chopra 	}
147464f6645SManish Chopra 
148464f6645SManish Chopra 	if (test_bit(QED_MODE_L2GENEVE_TUNN, &update_mask)) {
149464f6645SManish Chopra 		if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
150464f6645SManish Chopra 			__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
151464f6645SManish Chopra 	} else {
152464f6645SManish Chopra 		if (test_bit(QED_MODE_L2GENEVE_TUNN, &cached_tunn_mode))
153464f6645SManish Chopra 			__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
154464f6645SManish Chopra 	}
155464f6645SManish Chopra 
156464f6645SManish Chopra 	if (test_bit(QED_MODE_IPGENEVE_TUNN, &update_mask)) {
157464f6645SManish Chopra 		if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
158464f6645SManish Chopra 			__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
159464f6645SManish Chopra 	} else {
160464f6645SManish Chopra 		if (test_bit(QED_MODE_IPGENEVE_TUNN, &cached_tunn_mode))
161464f6645SManish Chopra 			__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
162464f6645SManish Chopra 	}
163464f6645SManish Chopra 
164464f6645SManish Chopra 	p_src->tunn_mode = new_tunn_mode;
165464f6645SManish Chopra }
166464f6645SManish Chopra 
167464f6645SManish Chopra static void
168464f6645SManish Chopra qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
169464f6645SManish Chopra 			      struct qed_tunn_update_params *p_src,
170464f6645SManish Chopra 			      struct pf_update_tunnel_config *p_tunn_cfg)
171464f6645SManish Chopra {
172464f6645SManish Chopra 	unsigned long tunn_mode = p_src->tunn_mode;
173464f6645SManish Chopra 	enum tunnel_clss type;
174464f6645SManish Chopra 
175464f6645SManish Chopra 	qed_tunn_set_pf_fix_tunn_mode(p_hwfn, p_src, p_tunn_cfg);
176464f6645SManish Chopra 	p_tunn_cfg->update_rx_pf_clss = p_src->update_rx_pf_clss;
177464f6645SManish Chopra 	p_tunn_cfg->update_tx_pf_clss = p_src->update_tx_pf_clss;
178464f6645SManish Chopra 
179464f6645SManish Chopra 	type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
180464f6645SManish Chopra 	p_tunn_cfg->tunnel_clss_vxlan  = type;
181464f6645SManish Chopra 
182464f6645SManish Chopra 	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
183464f6645SManish Chopra 	p_tunn_cfg->tunnel_clss_l2gre = type;
184464f6645SManish Chopra 
185464f6645SManish Chopra 	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
186464f6645SManish Chopra 	p_tunn_cfg->tunnel_clss_ipgre = type;
187464f6645SManish Chopra 
188464f6645SManish Chopra 	if (p_src->update_vxlan_udp_port) {
189464f6645SManish Chopra 		p_tunn_cfg->set_vxlan_udp_port_flg = 1;
190464f6645SManish Chopra 		p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
191464f6645SManish Chopra 	}
192464f6645SManish Chopra 
193464f6645SManish Chopra 	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
194464f6645SManish Chopra 		p_tunn_cfg->tx_enable_l2gre = 1;
195464f6645SManish Chopra 
196464f6645SManish Chopra 	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
197464f6645SManish Chopra 		p_tunn_cfg->tx_enable_ipgre = 1;
198464f6645SManish Chopra 
199464f6645SManish Chopra 	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
200464f6645SManish Chopra 		p_tunn_cfg->tx_enable_vxlan = 1;
201464f6645SManish Chopra 
202464f6645SManish Chopra 	if (p_src->update_geneve_udp_port) {
203464f6645SManish Chopra 		p_tunn_cfg->set_geneve_udp_port_flg = 1;
204464f6645SManish Chopra 		p_tunn_cfg->geneve_udp_port =
205464f6645SManish Chopra 				cpu_to_le16(p_src->geneve_udp_port);
206464f6645SManish Chopra 	}
207464f6645SManish Chopra 
208464f6645SManish Chopra 	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
209464f6645SManish Chopra 		p_tunn_cfg->tx_enable_l2geneve = 1;
210464f6645SManish Chopra 
211464f6645SManish Chopra 	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
212464f6645SManish Chopra 		p_tunn_cfg->tx_enable_ipgeneve = 1;
213464f6645SManish Chopra 
214464f6645SManish Chopra 	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
215464f6645SManish Chopra 	p_tunn_cfg->tunnel_clss_l2geneve = type;
216464f6645SManish Chopra 
217464f6645SManish Chopra 	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
218464f6645SManish Chopra 	p_tunn_cfg->tunnel_clss_ipgeneve = type;
219464f6645SManish Chopra }
220464f6645SManish Chopra 
221464f6645SManish Chopra static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
222464f6645SManish Chopra 				 struct qed_ptt *p_ptt,
223464f6645SManish Chopra 				 unsigned long tunn_mode)
224464f6645SManish Chopra {
225464f6645SManish Chopra 	u8 l2gre_enable = 0, ipgre_enable = 0, vxlan_enable = 0;
226464f6645SManish Chopra 	u8 l2geneve_enable = 0, ipgeneve_enable = 0;
227464f6645SManish Chopra 
228464f6645SManish Chopra 	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
229464f6645SManish Chopra 		l2gre_enable = 1;
230464f6645SManish Chopra 
231464f6645SManish Chopra 	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
232464f6645SManish Chopra 		ipgre_enable = 1;
233464f6645SManish Chopra 
234464f6645SManish Chopra 	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
235464f6645SManish Chopra 		vxlan_enable = 1;
236464f6645SManish Chopra 
237464f6645SManish Chopra 	qed_set_gre_enable(p_hwfn, p_ptt, l2gre_enable, ipgre_enable);
238464f6645SManish Chopra 	qed_set_vxlan_enable(p_hwfn, p_ptt, vxlan_enable);
239464f6645SManish Chopra 
240464f6645SManish Chopra 	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
241464f6645SManish Chopra 		l2geneve_enable = 1;
242464f6645SManish Chopra 
243464f6645SManish Chopra 	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
244464f6645SManish Chopra 		ipgeneve_enable = 1;
245464f6645SManish Chopra 
246464f6645SManish Chopra 	qed_set_geneve_enable(p_hwfn, p_ptt, l2geneve_enable,
247464f6645SManish Chopra 			      ipgeneve_enable);
248464f6645SManish Chopra }
249464f6645SManish Chopra 
250464f6645SManish Chopra static void
251464f6645SManish Chopra qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
252464f6645SManish Chopra 			     struct qed_tunn_start_params *p_src,
253464f6645SManish Chopra 			     struct pf_start_tunnel_config *p_tunn_cfg)
254464f6645SManish Chopra {
255464f6645SManish Chopra 	unsigned long tunn_mode;
256464f6645SManish Chopra 	enum tunnel_clss type;
257464f6645SManish Chopra 
258464f6645SManish Chopra 	if (!p_src)
259464f6645SManish Chopra 		return;
260464f6645SManish Chopra 
261464f6645SManish Chopra 	tunn_mode = p_src->tunn_mode;
262464f6645SManish Chopra 	type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
263464f6645SManish Chopra 	p_tunn_cfg->tunnel_clss_vxlan = type;
264464f6645SManish Chopra 	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
265464f6645SManish Chopra 	p_tunn_cfg->tunnel_clss_l2gre = type;
266464f6645SManish Chopra 	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
267464f6645SManish Chopra 	p_tunn_cfg->tunnel_clss_ipgre = type;
268464f6645SManish Chopra 
269464f6645SManish Chopra 	if (p_src->update_vxlan_udp_port) {
270464f6645SManish Chopra 		p_tunn_cfg->set_vxlan_udp_port_flg = 1;
271464f6645SManish Chopra 		p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
272464f6645SManish Chopra 	}
273464f6645SManish Chopra 
274464f6645SManish Chopra 	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
275464f6645SManish Chopra 		p_tunn_cfg->tx_enable_l2gre = 1;
276464f6645SManish Chopra 
277464f6645SManish Chopra 	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
278464f6645SManish Chopra 		p_tunn_cfg->tx_enable_ipgre = 1;
279464f6645SManish Chopra 
280464f6645SManish Chopra 	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
281464f6645SManish Chopra 		p_tunn_cfg->tx_enable_vxlan = 1;
282464f6645SManish Chopra 
283464f6645SManish Chopra 	if (p_src->update_geneve_udp_port) {
284464f6645SManish Chopra 		p_tunn_cfg->set_geneve_udp_port_flg = 1;
285464f6645SManish Chopra 		p_tunn_cfg->geneve_udp_port =
286464f6645SManish Chopra 				cpu_to_le16(p_src->geneve_udp_port);
287464f6645SManish Chopra 	}
288464f6645SManish Chopra 
289464f6645SManish Chopra 	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
290464f6645SManish Chopra 		p_tunn_cfg->tx_enable_l2geneve = 1;
291464f6645SManish Chopra 
292464f6645SManish Chopra 	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
293464f6645SManish Chopra 		p_tunn_cfg->tx_enable_ipgeneve = 1;
294464f6645SManish Chopra 
295464f6645SManish Chopra 	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
296464f6645SManish Chopra 	p_tunn_cfg->tunnel_clss_l2geneve = type;
297464f6645SManish Chopra 	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
298464f6645SManish Chopra 	p_tunn_cfg->tunnel_clss_ipgeneve = type;
299464f6645SManish Chopra }
300464f6645SManish Chopra 
301fe56b9e6SYuval Mintz int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
302464f6645SManish Chopra 		    struct qed_tunn_start_params *p_tunn,
303831bfb0eSYuval Mintz 		    enum qed_mf_mode mode, bool allow_npar_tx_switch)
304fe56b9e6SYuval Mintz {
305fe56b9e6SYuval Mintz 	struct pf_start_ramrod_data *p_ramrod = NULL;
306fe56b9e6SYuval Mintz 	u16 sb = qed_int_get_sp_sb_id(p_hwfn);
307fe56b9e6SYuval Mintz 	u8 sb_index = p_hwfn->p_eq->eq_sb_index;
308fe56b9e6SYuval Mintz 	struct qed_spq_entry *p_ent = NULL;
30906f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
310fe56b9e6SYuval Mintz 	int rc = -EINVAL;
311a91eb52aSYuval Mintz 	u8 page_cnt;
312fe56b9e6SYuval Mintz 
313fe56b9e6SYuval Mintz 	/* update initial eq producer */
314fe56b9e6SYuval Mintz 	qed_eq_prod_update(p_hwfn,
315fe56b9e6SYuval Mintz 			   qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));
316fe56b9e6SYuval Mintz 
31706f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
31806f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
31906f56b81SYuval Mintz 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
32006f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
321fe56b9e6SYuval Mintz 
32206f56b81SYuval Mintz 	rc = qed_sp_init_request(p_hwfn, &p_ent,
323fe56b9e6SYuval Mintz 				 COMMON_RAMROD_PF_START,
324fe56b9e6SYuval Mintz 				 PROTOCOLID_COMMON,
32506f56b81SYuval Mintz 				 &init_data);
326fe56b9e6SYuval Mintz 	if (rc)
327fe56b9e6SYuval Mintz 		return rc;
328fe56b9e6SYuval Mintz 
329fe56b9e6SYuval Mintz 	p_ramrod = &p_ent->ramrod.pf_start;
330fe56b9e6SYuval Mintz 
331fe56b9e6SYuval Mintz 	p_ramrod->event_ring_sb_id	= cpu_to_le16(sb);
332fe56b9e6SYuval Mintz 	p_ramrod->event_ring_sb_index	= sb_index;
333fe56b9e6SYuval Mintz 	p_ramrod->path_id		= QED_PATH_ID(p_hwfn);
334fe56b9e6SYuval Mintz 	p_ramrod->dont_log_ramrods	= 0;
335fe56b9e6SYuval Mintz 	p_ramrod->log_type_mask		= cpu_to_le16(0xf);
336351a4dedSYuval Mintz 
337fc48b7a6SYuval Mintz 	switch (mode) {
338fc48b7a6SYuval Mintz 	case QED_MF_DEFAULT:
339fc48b7a6SYuval Mintz 	case QED_MF_NPAR:
340fc48b7a6SYuval Mintz 		p_ramrod->mf_mode = MF_NPAR;
341fc48b7a6SYuval Mintz 		break;
342fc48b7a6SYuval Mintz 	case QED_MF_OVLAN:
343fc48b7a6SYuval Mintz 		p_ramrod->mf_mode = MF_OVLAN;
344fc48b7a6SYuval Mintz 		break;
345fc48b7a6SYuval Mintz 	default:
346fc48b7a6SYuval Mintz 		DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
347fc48b7a6SYuval Mintz 		p_ramrod->mf_mode = MF_NPAR;
348fc48b7a6SYuval Mintz 	}
349fe56b9e6SYuval Mintz 	p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
350fe56b9e6SYuval Mintz 
351fe56b9e6SYuval Mintz 	/* Place EQ address in RAMROD */
35294494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
35394494598SYuval Mintz 		       p_hwfn->p_eq->chain.pbl.p_phys_table);
354a91eb52aSYuval Mintz 	page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
355a91eb52aSYuval Mintz 	p_ramrod->event_ring_num_pages = page_cnt;
35694494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
35794494598SYuval Mintz 		       p_hwfn->p_consq->chain.pbl.p_phys_table);
358fe56b9e6SYuval Mintz 
359b18e170cSManish Chopra 	qed_tunn_set_pf_start_params(p_hwfn, p_tunn,
360b18e170cSManish Chopra 				     &p_ramrod->tunnel_config);
361fe56b9e6SYuval Mintz 
362831bfb0eSYuval Mintz 	if (IS_MF_SI(p_hwfn))
363831bfb0eSYuval Mintz 		p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
364831bfb0eSYuval Mintz 
365c5ac9319SYuval Mintz 	switch (p_hwfn->hw_info.personality) {
366c5ac9319SYuval Mintz 	case QED_PCI_ETH:
367c5ac9319SYuval Mintz 		p_ramrod->personality = PERSONALITY_ETH;
368c5ac9319SYuval Mintz 		break;
369c5ac9319SYuval Mintz 	case QED_PCI_ISCSI:
370c5ac9319SYuval Mintz 		p_ramrod->personality = PERSONALITY_ISCSI;
371c5ac9319SYuval Mintz 		break;
372c5ac9319SYuval Mintz 	case QED_PCI_ETH_ROCE:
373c5ac9319SYuval Mintz 		p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
374c5ac9319SYuval Mintz 		break;
375c5ac9319SYuval Mintz 	default:
376c5ac9319SYuval Mintz 		DP_NOTICE(p_hwfn, "Unkown personality %d\n",
377c5ac9319SYuval Mintz 			  p_hwfn->hw_info.personality);
378c5ac9319SYuval Mintz 		p_ramrod->personality = PERSONALITY_ETH;
379c5ac9319SYuval Mintz 	}
380c5ac9319SYuval Mintz 
3811408cc1fSYuval Mintz 	if (p_hwfn->cdev->p_iov_info) {
3821408cc1fSYuval Mintz 		struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
3831408cc1fSYuval Mintz 
3841408cc1fSYuval Mintz 		p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
3851408cc1fSYuval Mintz 		p_ramrod->num_vfs = (u8) p_iov->total_vfs;
3861408cc1fSYuval Mintz 	}
387351a4dedSYuval Mintz 	p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
388351a4dedSYuval Mintz 	p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
3891408cc1fSYuval Mintz 
390fe56b9e6SYuval Mintz 	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
391fc48b7a6SYuval Mintz 		   "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
392fe56b9e6SYuval Mintz 		   sb, sb_index,
393fe56b9e6SYuval Mintz 		   p_ramrod->outer_tag);
394fe56b9e6SYuval Mintz 
395c0f31a05SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
396c0f31a05SManish Chopra 
397c0f31a05SManish Chopra 	if (p_tunn) {
398c0f31a05SManish Chopra 		qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt,
399c0f31a05SManish Chopra 				     p_tunn->tunn_mode);
400c0f31a05SManish Chopra 		p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
401c0f31a05SManish Chopra 	}
402c0f31a05SManish Chopra 
403c0f31a05SManish Chopra 	return rc;
404fe56b9e6SYuval Mintz }
405fe56b9e6SYuval Mintz 
40639651abdSSudarsana Reddy Kalluru int qed_sp_pf_update(struct qed_hwfn *p_hwfn)
40739651abdSSudarsana Reddy Kalluru {
40839651abdSSudarsana Reddy Kalluru 	struct qed_spq_entry *p_ent = NULL;
40939651abdSSudarsana Reddy Kalluru 	struct qed_sp_init_data init_data;
41039651abdSSudarsana Reddy Kalluru 	int rc = -EINVAL;
41139651abdSSudarsana Reddy Kalluru 
41239651abdSSudarsana Reddy Kalluru 	/* Get SPQ entry */
41339651abdSSudarsana Reddy Kalluru 	memset(&init_data, 0, sizeof(init_data));
41439651abdSSudarsana Reddy Kalluru 	init_data.cid = qed_spq_get_cid(p_hwfn);
41539651abdSSudarsana Reddy Kalluru 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
41639651abdSSudarsana Reddy Kalluru 	init_data.comp_mode = QED_SPQ_MODE_CB;
41739651abdSSudarsana Reddy Kalluru 
41839651abdSSudarsana Reddy Kalluru 	rc = qed_sp_init_request(p_hwfn, &p_ent,
41939651abdSSudarsana Reddy Kalluru 				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
42039651abdSSudarsana Reddy Kalluru 				 &init_data);
42139651abdSSudarsana Reddy Kalluru 	if (rc)
42239651abdSSudarsana Reddy Kalluru 		return rc;
42339651abdSSudarsana Reddy Kalluru 
42439651abdSSudarsana Reddy Kalluru 	qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
42539651abdSSudarsana Reddy Kalluru 				      &p_ent->ramrod.pf_update);
42639651abdSSudarsana Reddy Kalluru 
42739651abdSSudarsana Reddy Kalluru 	return qed_spq_post(p_hwfn, p_ent, NULL);
42839651abdSSudarsana Reddy Kalluru }
42939651abdSSudarsana Reddy Kalluru 
430464f6645SManish Chopra /* Set pf update ramrod command params */
431464f6645SManish Chopra int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
432464f6645SManish Chopra 			      struct qed_tunn_update_params *p_tunn,
433464f6645SManish Chopra 			      enum spq_mode comp_mode,
434464f6645SManish Chopra 			      struct qed_spq_comp_cb *p_comp_data)
435464f6645SManish Chopra {
436464f6645SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
437464f6645SManish Chopra 	struct qed_sp_init_data init_data;
438464f6645SManish Chopra 	int rc = -EINVAL;
439464f6645SManish Chopra 
440464f6645SManish Chopra 	/* Get SPQ entry */
441464f6645SManish Chopra 	memset(&init_data, 0, sizeof(init_data));
442464f6645SManish Chopra 	init_data.cid = qed_spq_get_cid(p_hwfn);
443464f6645SManish Chopra 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
444464f6645SManish Chopra 	init_data.comp_mode = comp_mode;
445464f6645SManish Chopra 	init_data.p_comp_data = p_comp_data;
446464f6645SManish Chopra 
447464f6645SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
448464f6645SManish Chopra 				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
449464f6645SManish Chopra 				 &init_data);
450464f6645SManish Chopra 	if (rc)
451464f6645SManish Chopra 		return rc;
452464f6645SManish Chopra 
453464f6645SManish Chopra 	qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
454464f6645SManish Chopra 				      &p_ent->ramrod.pf_update.tunnel_config);
455464f6645SManish Chopra 
456464f6645SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
457464f6645SManish Chopra 	if (rc)
458464f6645SManish Chopra 		return rc;
459464f6645SManish Chopra 
460464f6645SManish Chopra 	if (p_tunn->update_vxlan_udp_port)
461464f6645SManish Chopra 		qed_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
462464f6645SManish Chopra 					p_tunn->vxlan_udp_port);
463464f6645SManish Chopra 	if (p_tunn->update_geneve_udp_port)
464464f6645SManish Chopra 		qed_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
465464f6645SManish Chopra 					 p_tunn->geneve_udp_port);
466464f6645SManish Chopra 
467464f6645SManish Chopra 	qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode);
468464f6645SManish Chopra 	p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
469464f6645SManish Chopra 
470464f6645SManish Chopra 	return rc;
471464f6645SManish Chopra }
472464f6645SManish Chopra 
473fe56b9e6SYuval Mintz int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
474fe56b9e6SYuval Mintz {
475fe56b9e6SYuval Mintz 	struct qed_spq_entry *p_ent = NULL;
47606f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
477fe56b9e6SYuval Mintz 	int rc = -EINVAL;
478fe56b9e6SYuval Mintz 
47906f56b81SYuval Mintz 	/* Get SPQ entry */
48006f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
48106f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
48206f56b81SYuval Mintz 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
48306f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
484fe56b9e6SYuval Mintz 
48506f56b81SYuval Mintz 	rc = qed_sp_init_request(p_hwfn, &p_ent,
486fe56b9e6SYuval Mintz 				 COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
48706f56b81SYuval Mintz 				 &init_data);
488fe56b9e6SYuval Mintz 	if (rc)
489fe56b9e6SYuval Mintz 		return rc;
490fe56b9e6SYuval Mintz 
491fe56b9e6SYuval Mintz 	return qed_spq_post(p_hwfn, p_ent, NULL);
492fe56b9e6SYuval Mintz }
49303dc76caSSudarsana Reddy Kalluru 
49403dc76caSSudarsana Reddy Kalluru int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
49503dc76caSSudarsana Reddy Kalluru {
49603dc76caSSudarsana Reddy Kalluru 	struct qed_spq_entry *p_ent = NULL;
49703dc76caSSudarsana Reddy Kalluru 	struct qed_sp_init_data init_data;
49803dc76caSSudarsana Reddy Kalluru 	int rc;
49903dc76caSSudarsana Reddy Kalluru 
50003dc76caSSudarsana Reddy Kalluru 	/* Get SPQ entry */
50103dc76caSSudarsana Reddy Kalluru 	memset(&init_data, 0, sizeof(init_data));
50203dc76caSSudarsana Reddy Kalluru 	init_data.cid = qed_spq_get_cid(p_hwfn);
50303dc76caSSudarsana Reddy Kalluru 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
50403dc76caSSudarsana Reddy Kalluru 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
50503dc76caSSudarsana Reddy Kalluru 
50603dc76caSSudarsana Reddy Kalluru 	rc = qed_sp_init_request(p_hwfn, &p_ent,
50703dc76caSSudarsana Reddy Kalluru 				 COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
50803dc76caSSudarsana Reddy Kalluru 				 &init_data);
50903dc76caSSudarsana Reddy Kalluru 	if (rc)
51003dc76caSSudarsana Reddy Kalluru 		return rc;
51103dc76caSSudarsana Reddy Kalluru 
51203dc76caSSudarsana Reddy Kalluru 	return qed_spq_post(p_hwfn, p_ent, NULL);
51303dc76caSSudarsana Reddy Kalluru }
514