1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/types.h> 10fe56b9e6SYuval Mintz #include <asm/byteorder.h> 11fe56b9e6SYuval Mintz #include <linux/bitops.h> 12fe56b9e6SYuval Mintz #include <linux/errno.h> 13fe56b9e6SYuval Mintz #include <linux/kernel.h> 14fe56b9e6SYuval Mintz #include <linux/string.h> 15fe56b9e6SYuval Mintz #include "qed.h" 16fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 17fe56b9e6SYuval Mintz #include "qed_cxt.h" 1839651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 19fe56b9e6SYuval Mintz #include "qed_hsi.h" 20fe56b9e6SYuval Mintz #include "qed_hw.h" 21fe56b9e6SYuval Mintz #include "qed_int.h" 22fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 23fe56b9e6SYuval Mintz #include "qed_sp.h" 241408cc1fSYuval Mintz #include "qed_sriov.h" 25fe56b9e6SYuval Mintz 26fe56b9e6SYuval Mintz int qed_sp_init_request(struct qed_hwfn *p_hwfn, 27fe56b9e6SYuval Mintz struct qed_spq_entry **pp_ent, 281a635e48SYuval Mintz u8 cmd, u8 protocol, struct qed_sp_init_data *p_data) 29fe56b9e6SYuval Mintz { 3006f56b81SYuval Mintz u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid; 31fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 3206f56b81SYuval Mintz int rc; 33fe56b9e6SYuval Mintz 34fe56b9e6SYuval Mintz if (!pp_ent) 35fe56b9e6SYuval Mintz return -ENOMEM; 36fe56b9e6SYuval Mintz 37fe56b9e6SYuval Mintz rc = qed_spq_get_entry(p_hwfn, pp_ent); 38fe56b9e6SYuval Mintz 391a635e48SYuval Mintz if (rc) 40fe56b9e6SYuval Mintz return rc; 41fe56b9e6SYuval Mintz 42fe56b9e6SYuval Mintz p_ent = *pp_ent; 43fe56b9e6SYuval Mintz 44fe56b9e6SYuval Mintz p_ent->elem.hdr.cid = cpu_to_le32(opaque_cid); 45fe56b9e6SYuval Mintz p_ent->elem.hdr.cmd_id = cmd; 46fe56b9e6SYuval Mintz p_ent->elem.hdr.protocol_id = protocol; 47fe56b9e6SYuval Mintz 48fe56b9e6SYuval Mintz p_ent->priority = QED_SPQ_PRIORITY_NORMAL; 4906f56b81SYuval Mintz p_ent->comp_mode = p_data->comp_mode; 50fe56b9e6SYuval Mintz p_ent->comp_done.done = 0; 51fe56b9e6SYuval Mintz 52fe56b9e6SYuval Mintz switch (p_ent->comp_mode) { 53fe56b9e6SYuval Mintz case QED_SPQ_MODE_EBLOCK: 54fe56b9e6SYuval Mintz p_ent->comp_cb.cookie = &p_ent->comp_done; 55fe56b9e6SYuval Mintz break; 56fe56b9e6SYuval Mintz 57fe56b9e6SYuval Mintz case QED_SPQ_MODE_BLOCK: 5806f56b81SYuval Mintz if (!p_data->p_comp_data) 59fe56b9e6SYuval Mintz return -EINVAL; 60fe56b9e6SYuval Mintz 6106f56b81SYuval Mintz p_ent->comp_cb.cookie = p_data->p_comp_data->cookie; 62fe56b9e6SYuval Mintz break; 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz case QED_SPQ_MODE_CB: 6506f56b81SYuval Mintz if (!p_data->p_comp_data) 66fe56b9e6SYuval Mintz p_ent->comp_cb.function = NULL; 67fe56b9e6SYuval Mintz else 6806f56b81SYuval Mintz p_ent->comp_cb = *p_data->p_comp_data; 69fe56b9e6SYuval Mintz break; 70fe56b9e6SYuval Mintz 71fe56b9e6SYuval Mintz default: 72fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n", 73fe56b9e6SYuval Mintz p_ent->comp_mode); 74fe56b9e6SYuval Mintz return -EINVAL; 75fe56b9e6SYuval Mintz } 76fe56b9e6SYuval Mintz 77fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 78fe56b9e6SYuval Mintz "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n", 79fe56b9e6SYuval Mintz opaque_cid, cmd, protocol, 80fe56b9e6SYuval Mintz (unsigned long)&p_ent->ramrod, 81fe56b9e6SYuval Mintz D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK, 82fe56b9e6SYuval Mintz QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK", 83fe56b9e6SYuval Mintz "MODE_CB")); 8406f56b81SYuval Mintz 8506f56b81SYuval Mintz memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod)); 86fe56b9e6SYuval Mintz 87fe56b9e6SYuval Mintz return 0; 88fe56b9e6SYuval Mintz } 89fe56b9e6SYuval Mintz 90464f6645SManish Chopra static enum tunnel_clss qed_tunn_get_clss_type(u8 type) 91464f6645SManish Chopra { 92464f6645SManish Chopra switch (type) { 93464f6645SManish Chopra case QED_TUNN_CLSS_MAC_VLAN: 94464f6645SManish Chopra return TUNNEL_CLSS_MAC_VLAN; 95464f6645SManish Chopra case QED_TUNN_CLSS_MAC_VNI: 96464f6645SManish Chopra return TUNNEL_CLSS_MAC_VNI; 97464f6645SManish Chopra case QED_TUNN_CLSS_INNER_MAC_VLAN: 98464f6645SManish Chopra return TUNNEL_CLSS_INNER_MAC_VLAN; 99464f6645SManish Chopra case QED_TUNN_CLSS_INNER_MAC_VNI: 100464f6645SManish Chopra return TUNNEL_CLSS_INNER_MAC_VNI; 101464f6645SManish Chopra default: 102464f6645SManish Chopra return TUNNEL_CLSS_MAC_VLAN; 103464f6645SManish Chopra } 104464f6645SManish Chopra } 105464f6645SManish Chopra 106464f6645SManish Chopra static void 107464f6645SManish Chopra qed_tunn_set_pf_fix_tunn_mode(struct qed_hwfn *p_hwfn, 108464f6645SManish Chopra struct qed_tunn_update_params *p_src, 109464f6645SManish Chopra struct pf_update_tunnel_config *p_tunn_cfg) 110464f6645SManish Chopra { 111464f6645SManish Chopra unsigned long cached_tunn_mode = p_hwfn->cdev->tunn_mode; 112464f6645SManish Chopra unsigned long update_mask = p_src->tunn_mode_update_mask; 113464f6645SManish Chopra unsigned long tunn_mode = p_src->tunn_mode; 114464f6645SManish Chopra unsigned long new_tunn_mode = 0; 115464f6645SManish Chopra 116464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &update_mask)) { 117464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode)) 118464f6645SManish Chopra __set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode); 119464f6645SManish Chopra } else { 120464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &cached_tunn_mode)) 121464f6645SManish Chopra __set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode); 122464f6645SManish Chopra } 123464f6645SManish Chopra 124464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &update_mask)) { 125464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode)) 126464f6645SManish Chopra __set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode); 127464f6645SManish Chopra } else { 128464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &cached_tunn_mode)) 129464f6645SManish Chopra __set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode); 130464f6645SManish Chopra } 131464f6645SManish Chopra 132464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &update_mask)) { 133464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode)) 134464f6645SManish Chopra __set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode); 135464f6645SManish Chopra } else { 136464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &cached_tunn_mode)) 137464f6645SManish Chopra __set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode); 138464f6645SManish Chopra } 139464f6645SManish Chopra 140464f6645SManish Chopra if (p_src->update_geneve_udp_port) { 141464f6645SManish Chopra p_tunn_cfg->set_geneve_udp_port_flg = 1; 142464f6645SManish Chopra p_tunn_cfg->geneve_udp_port = 143464f6645SManish Chopra cpu_to_le16(p_src->geneve_udp_port); 144464f6645SManish Chopra } 145464f6645SManish Chopra 146464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &update_mask)) { 147464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode)) 148464f6645SManish Chopra __set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode); 149464f6645SManish Chopra } else { 150464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &cached_tunn_mode)) 151464f6645SManish Chopra __set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode); 152464f6645SManish Chopra } 153464f6645SManish Chopra 154464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &update_mask)) { 155464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode)) 156464f6645SManish Chopra __set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode); 157464f6645SManish Chopra } else { 158464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &cached_tunn_mode)) 159464f6645SManish Chopra __set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode); 160464f6645SManish Chopra } 161464f6645SManish Chopra 162464f6645SManish Chopra p_src->tunn_mode = new_tunn_mode; 163464f6645SManish Chopra } 164464f6645SManish Chopra 165464f6645SManish Chopra static void 166464f6645SManish Chopra qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn, 167464f6645SManish Chopra struct qed_tunn_update_params *p_src, 168464f6645SManish Chopra struct pf_update_tunnel_config *p_tunn_cfg) 169464f6645SManish Chopra { 170464f6645SManish Chopra unsigned long tunn_mode = p_src->tunn_mode; 171464f6645SManish Chopra enum tunnel_clss type; 172464f6645SManish Chopra 173464f6645SManish Chopra qed_tunn_set_pf_fix_tunn_mode(p_hwfn, p_src, p_tunn_cfg); 174464f6645SManish Chopra p_tunn_cfg->update_rx_pf_clss = p_src->update_rx_pf_clss; 175464f6645SManish Chopra p_tunn_cfg->update_tx_pf_clss = p_src->update_tx_pf_clss; 176464f6645SManish Chopra 177464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan); 178464f6645SManish Chopra p_tunn_cfg->tunnel_clss_vxlan = type; 179464f6645SManish Chopra 180464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre); 181464f6645SManish Chopra p_tunn_cfg->tunnel_clss_l2gre = type; 182464f6645SManish Chopra 183464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre); 184464f6645SManish Chopra p_tunn_cfg->tunnel_clss_ipgre = type; 185464f6645SManish Chopra 186464f6645SManish Chopra if (p_src->update_vxlan_udp_port) { 187464f6645SManish Chopra p_tunn_cfg->set_vxlan_udp_port_flg = 1; 188464f6645SManish Chopra p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port); 189464f6645SManish Chopra } 190464f6645SManish Chopra 191464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode)) 192464f6645SManish Chopra p_tunn_cfg->tx_enable_l2gre = 1; 193464f6645SManish Chopra 194464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode)) 195464f6645SManish Chopra p_tunn_cfg->tx_enable_ipgre = 1; 196464f6645SManish Chopra 197464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode)) 198464f6645SManish Chopra p_tunn_cfg->tx_enable_vxlan = 1; 199464f6645SManish Chopra 200464f6645SManish Chopra if (p_src->update_geneve_udp_port) { 201464f6645SManish Chopra p_tunn_cfg->set_geneve_udp_port_flg = 1; 202464f6645SManish Chopra p_tunn_cfg->geneve_udp_port = 203464f6645SManish Chopra cpu_to_le16(p_src->geneve_udp_port); 204464f6645SManish Chopra } 205464f6645SManish Chopra 206464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode)) 207464f6645SManish Chopra p_tunn_cfg->tx_enable_l2geneve = 1; 208464f6645SManish Chopra 209464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode)) 210464f6645SManish Chopra p_tunn_cfg->tx_enable_ipgeneve = 1; 211464f6645SManish Chopra 212464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve); 213464f6645SManish Chopra p_tunn_cfg->tunnel_clss_l2geneve = type; 214464f6645SManish Chopra 215464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve); 216464f6645SManish Chopra p_tunn_cfg->tunnel_clss_ipgeneve = type; 217464f6645SManish Chopra } 218464f6645SManish Chopra 219464f6645SManish Chopra static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn, 220464f6645SManish Chopra struct qed_ptt *p_ptt, 221464f6645SManish Chopra unsigned long tunn_mode) 222464f6645SManish Chopra { 223464f6645SManish Chopra u8 l2gre_enable = 0, ipgre_enable = 0, vxlan_enable = 0; 224464f6645SManish Chopra u8 l2geneve_enable = 0, ipgeneve_enable = 0; 225464f6645SManish Chopra 226464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode)) 227464f6645SManish Chopra l2gre_enable = 1; 228464f6645SManish Chopra 229464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode)) 230464f6645SManish Chopra ipgre_enable = 1; 231464f6645SManish Chopra 232464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode)) 233464f6645SManish Chopra vxlan_enable = 1; 234464f6645SManish Chopra 235464f6645SManish Chopra qed_set_gre_enable(p_hwfn, p_ptt, l2gre_enable, ipgre_enable); 236464f6645SManish Chopra qed_set_vxlan_enable(p_hwfn, p_ptt, vxlan_enable); 237464f6645SManish Chopra 238464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode)) 239464f6645SManish Chopra l2geneve_enable = 1; 240464f6645SManish Chopra 241464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode)) 242464f6645SManish Chopra ipgeneve_enable = 1; 243464f6645SManish Chopra 244464f6645SManish Chopra qed_set_geneve_enable(p_hwfn, p_ptt, l2geneve_enable, 245464f6645SManish Chopra ipgeneve_enable); 246464f6645SManish Chopra } 247464f6645SManish Chopra 248464f6645SManish Chopra static void 249464f6645SManish Chopra qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn, 250464f6645SManish Chopra struct qed_tunn_start_params *p_src, 251464f6645SManish Chopra struct pf_start_tunnel_config *p_tunn_cfg) 252464f6645SManish Chopra { 253464f6645SManish Chopra unsigned long tunn_mode; 254464f6645SManish Chopra enum tunnel_clss type; 255464f6645SManish Chopra 256464f6645SManish Chopra if (!p_src) 257464f6645SManish Chopra return; 258464f6645SManish Chopra 259464f6645SManish Chopra tunn_mode = p_src->tunn_mode; 260464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan); 261464f6645SManish Chopra p_tunn_cfg->tunnel_clss_vxlan = type; 262464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre); 263464f6645SManish Chopra p_tunn_cfg->tunnel_clss_l2gre = type; 264464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre); 265464f6645SManish Chopra p_tunn_cfg->tunnel_clss_ipgre = type; 266464f6645SManish Chopra 267464f6645SManish Chopra if (p_src->update_vxlan_udp_port) { 268464f6645SManish Chopra p_tunn_cfg->set_vxlan_udp_port_flg = 1; 269464f6645SManish Chopra p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port); 270464f6645SManish Chopra } 271464f6645SManish Chopra 272464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode)) 273464f6645SManish Chopra p_tunn_cfg->tx_enable_l2gre = 1; 274464f6645SManish Chopra 275464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode)) 276464f6645SManish Chopra p_tunn_cfg->tx_enable_ipgre = 1; 277464f6645SManish Chopra 278464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode)) 279464f6645SManish Chopra p_tunn_cfg->tx_enable_vxlan = 1; 280464f6645SManish Chopra 281464f6645SManish Chopra if (p_src->update_geneve_udp_port) { 282464f6645SManish Chopra p_tunn_cfg->set_geneve_udp_port_flg = 1; 283464f6645SManish Chopra p_tunn_cfg->geneve_udp_port = 284464f6645SManish Chopra cpu_to_le16(p_src->geneve_udp_port); 285464f6645SManish Chopra } 286464f6645SManish Chopra 287464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode)) 288464f6645SManish Chopra p_tunn_cfg->tx_enable_l2geneve = 1; 289464f6645SManish Chopra 290464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode)) 291464f6645SManish Chopra p_tunn_cfg->tx_enable_ipgeneve = 1; 292464f6645SManish Chopra 293464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve); 294464f6645SManish Chopra p_tunn_cfg->tunnel_clss_l2geneve = type; 295464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve); 296464f6645SManish Chopra p_tunn_cfg->tunnel_clss_ipgeneve = type; 297464f6645SManish Chopra } 298464f6645SManish Chopra 299fe56b9e6SYuval Mintz int qed_sp_pf_start(struct qed_hwfn *p_hwfn, 300464f6645SManish Chopra struct qed_tunn_start_params *p_tunn, 301831bfb0eSYuval Mintz enum qed_mf_mode mode, bool allow_npar_tx_switch) 302fe56b9e6SYuval Mintz { 303fe56b9e6SYuval Mintz struct pf_start_ramrod_data *p_ramrod = NULL; 304fe56b9e6SYuval Mintz u16 sb = qed_int_get_sp_sb_id(p_hwfn); 305fe56b9e6SYuval Mintz u8 sb_index = p_hwfn->p_eq->eq_sb_index; 306fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 30706f56b81SYuval Mintz struct qed_sp_init_data init_data; 308fe56b9e6SYuval Mintz int rc = -EINVAL; 309a91eb52aSYuval Mintz u8 page_cnt; 310fe56b9e6SYuval Mintz 311fe56b9e6SYuval Mintz /* update initial eq producer */ 312fe56b9e6SYuval Mintz qed_eq_prod_update(p_hwfn, 313fe56b9e6SYuval Mintz qed_chain_get_prod_idx(&p_hwfn->p_eq->chain)); 314fe56b9e6SYuval Mintz 31506f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 31606f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 31706f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 31806f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 319fe56b9e6SYuval Mintz 32006f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 321fe56b9e6SYuval Mintz COMMON_RAMROD_PF_START, 3221a635e48SYuval Mintz PROTOCOLID_COMMON, &init_data); 323fe56b9e6SYuval Mintz if (rc) 324fe56b9e6SYuval Mintz return rc; 325fe56b9e6SYuval Mintz 326fe56b9e6SYuval Mintz p_ramrod = &p_ent->ramrod.pf_start; 327fe56b9e6SYuval Mintz 328fe56b9e6SYuval Mintz p_ramrod->event_ring_sb_id = cpu_to_le16(sb); 329fe56b9e6SYuval Mintz p_ramrod->event_ring_sb_index = sb_index; 330fe56b9e6SYuval Mintz p_ramrod->path_id = QED_PATH_ID(p_hwfn); 331fe56b9e6SYuval Mintz p_ramrod->dont_log_ramrods = 0; 332fe56b9e6SYuval Mintz p_ramrod->log_type_mask = cpu_to_le16(0xf); 333351a4dedSYuval Mintz 334fc48b7a6SYuval Mintz switch (mode) { 335fc48b7a6SYuval Mintz case QED_MF_DEFAULT: 336fc48b7a6SYuval Mintz case QED_MF_NPAR: 337fc48b7a6SYuval Mintz p_ramrod->mf_mode = MF_NPAR; 338fc48b7a6SYuval Mintz break; 339fc48b7a6SYuval Mintz case QED_MF_OVLAN: 340fc48b7a6SYuval Mintz p_ramrod->mf_mode = MF_OVLAN; 341fc48b7a6SYuval Mintz break; 342fc48b7a6SYuval Mintz default: 343fc48b7a6SYuval Mintz DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 344fc48b7a6SYuval Mintz p_ramrod->mf_mode = MF_NPAR; 345fc48b7a6SYuval Mintz } 346fe56b9e6SYuval Mintz p_ramrod->outer_tag = p_hwfn->hw_info.ovlan; 347fe56b9e6SYuval Mintz 348fe56b9e6SYuval Mintz /* Place EQ address in RAMROD */ 34994494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr, 35094494598SYuval Mintz p_hwfn->p_eq->chain.pbl.p_phys_table); 351a91eb52aSYuval Mintz page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain); 352a91eb52aSYuval Mintz p_ramrod->event_ring_num_pages = page_cnt; 35394494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr, 35494494598SYuval Mintz p_hwfn->p_consq->chain.pbl.p_phys_table); 355fe56b9e6SYuval Mintz 3561a635e48SYuval Mintz qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config); 357fe56b9e6SYuval Mintz 358831bfb0eSYuval Mintz if (IS_MF_SI(p_hwfn)) 359831bfb0eSYuval Mintz p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch; 360831bfb0eSYuval Mintz 361c5ac9319SYuval Mintz switch (p_hwfn->hw_info.personality) { 362c5ac9319SYuval Mintz case QED_PCI_ETH: 363c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_ETH; 364c5ac9319SYuval Mintz break; 365c5ac9319SYuval Mintz case QED_PCI_ISCSI: 366c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_ISCSI; 367c5ac9319SYuval Mintz break; 368c5ac9319SYuval Mintz case QED_PCI_ETH_ROCE: 369c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_RDMA_AND_ETH; 370c5ac9319SYuval Mintz break; 371c5ac9319SYuval Mintz default: 3729165dabbSMasanari Iida DP_NOTICE(p_hwfn, "Unknown personality %d\n", 373c5ac9319SYuval Mintz p_hwfn->hw_info.personality); 374c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_ETH; 375c5ac9319SYuval Mintz } 376c5ac9319SYuval Mintz 3771408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 3781408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 3791408cc1fSYuval Mintz 3801408cc1fSYuval Mintz p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf; 3811408cc1fSYuval Mintz p_ramrod->num_vfs = (u8) p_iov->total_vfs; 3821408cc1fSYuval Mintz } 383351a4dedSYuval Mintz p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR; 384351a4dedSYuval Mintz p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR; 3851408cc1fSYuval Mintz 386fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 387fc48b7a6SYuval Mintz "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n", 3881a635e48SYuval Mintz sb, sb_index, p_ramrod->outer_tag); 389fe56b9e6SYuval Mintz 390c0f31a05SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 391c0f31a05SManish Chopra 392c0f31a05SManish Chopra if (p_tunn) { 393c0f31a05SManish Chopra qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, 394c0f31a05SManish Chopra p_tunn->tunn_mode); 395c0f31a05SManish Chopra p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode; 396c0f31a05SManish Chopra } 397c0f31a05SManish Chopra 398c0f31a05SManish Chopra return rc; 399fe56b9e6SYuval Mintz } 400fe56b9e6SYuval Mintz 40139651abdSSudarsana Reddy Kalluru int qed_sp_pf_update(struct qed_hwfn *p_hwfn) 40239651abdSSudarsana Reddy Kalluru { 40339651abdSSudarsana Reddy Kalluru struct qed_spq_entry *p_ent = NULL; 40439651abdSSudarsana Reddy Kalluru struct qed_sp_init_data init_data; 40539651abdSSudarsana Reddy Kalluru int rc = -EINVAL; 40639651abdSSudarsana Reddy Kalluru 40739651abdSSudarsana Reddy Kalluru /* Get SPQ entry */ 40839651abdSSudarsana Reddy Kalluru memset(&init_data, 0, sizeof(init_data)); 40939651abdSSudarsana Reddy Kalluru init_data.cid = qed_spq_get_cid(p_hwfn); 41039651abdSSudarsana Reddy Kalluru init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 41139651abdSSudarsana Reddy Kalluru init_data.comp_mode = QED_SPQ_MODE_CB; 41239651abdSSudarsana Reddy Kalluru 41339651abdSSudarsana Reddy Kalluru rc = qed_sp_init_request(p_hwfn, &p_ent, 41439651abdSSudarsana Reddy Kalluru COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 41539651abdSSudarsana Reddy Kalluru &init_data); 41639651abdSSudarsana Reddy Kalluru if (rc) 41739651abdSSudarsana Reddy Kalluru return rc; 41839651abdSSudarsana Reddy Kalluru 41939651abdSSudarsana Reddy Kalluru qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results, 42039651abdSSudarsana Reddy Kalluru &p_ent->ramrod.pf_update); 42139651abdSSudarsana Reddy Kalluru 42239651abdSSudarsana Reddy Kalluru return qed_spq_post(p_hwfn, p_ent, NULL); 42339651abdSSudarsana Reddy Kalluru } 42439651abdSSudarsana Reddy Kalluru 425464f6645SManish Chopra /* Set pf update ramrod command params */ 426464f6645SManish Chopra int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn, 427464f6645SManish Chopra struct qed_tunn_update_params *p_tunn, 428464f6645SManish Chopra enum spq_mode comp_mode, 429464f6645SManish Chopra struct qed_spq_comp_cb *p_comp_data) 430464f6645SManish Chopra { 431464f6645SManish Chopra struct qed_spq_entry *p_ent = NULL; 432464f6645SManish Chopra struct qed_sp_init_data init_data; 433464f6645SManish Chopra int rc = -EINVAL; 434464f6645SManish Chopra 435464f6645SManish Chopra /* Get SPQ entry */ 436464f6645SManish Chopra memset(&init_data, 0, sizeof(init_data)); 437464f6645SManish Chopra init_data.cid = qed_spq_get_cid(p_hwfn); 438464f6645SManish Chopra init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 439464f6645SManish Chopra init_data.comp_mode = comp_mode; 440464f6645SManish Chopra init_data.p_comp_data = p_comp_data; 441464f6645SManish Chopra 442464f6645SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 443464f6645SManish Chopra COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 444464f6645SManish Chopra &init_data); 445464f6645SManish Chopra if (rc) 446464f6645SManish Chopra return rc; 447464f6645SManish Chopra 448464f6645SManish Chopra qed_tunn_set_pf_update_params(p_hwfn, p_tunn, 449464f6645SManish Chopra &p_ent->ramrod.pf_update.tunnel_config); 450464f6645SManish Chopra 451464f6645SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 452464f6645SManish Chopra if (rc) 453464f6645SManish Chopra return rc; 454464f6645SManish Chopra 455464f6645SManish Chopra if (p_tunn->update_vxlan_udp_port) 456464f6645SManish Chopra qed_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt, 457464f6645SManish Chopra p_tunn->vxlan_udp_port); 458464f6645SManish Chopra if (p_tunn->update_geneve_udp_port) 459464f6645SManish Chopra qed_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt, 460464f6645SManish Chopra p_tunn->geneve_udp_port); 461464f6645SManish Chopra 462464f6645SManish Chopra qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode); 463464f6645SManish Chopra p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode; 464464f6645SManish Chopra 465464f6645SManish Chopra return rc; 466464f6645SManish Chopra } 467464f6645SManish Chopra 468fe56b9e6SYuval Mintz int qed_sp_pf_stop(struct qed_hwfn *p_hwfn) 469fe56b9e6SYuval Mintz { 470fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 47106f56b81SYuval Mintz struct qed_sp_init_data init_data; 472fe56b9e6SYuval Mintz int rc = -EINVAL; 473fe56b9e6SYuval Mintz 47406f56b81SYuval Mintz /* Get SPQ entry */ 47506f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 47606f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 47706f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 47806f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 479fe56b9e6SYuval Mintz 48006f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 481fe56b9e6SYuval Mintz COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON, 48206f56b81SYuval Mintz &init_data); 483fe56b9e6SYuval Mintz if (rc) 484fe56b9e6SYuval Mintz return rc; 485fe56b9e6SYuval Mintz 486fe56b9e6SYuval Mintz return qed_spq_post(p_hwfn, p_ent, NULL); 487fe56b9e6SYuval Mintz } 48803dc76caSSudarsana Reddy Kalluru 48903dc76caSSudarsana Reddy Kalluru int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn) 49003dc76caSSudarsana Reddy Kalluru { 49103dc76caSSudarsana Reddy Kalluru struct qed_spq_entry *p_ent = NULL; 49203dc76caSSudarsana Reddy Kalluru struct qed_sp_init_data init_data; 49303dc76caSSudarsana Reddy Kalluru int rc; 49403dc76caSSudarsana Reddy Kalluru 49503dc76caSSudarsana Reddy Kalluru /* Get SPQ entry */ 49603dc76caSSudarsana Reddy Kalluru memset(&init_data, 0, sizeof(init_data)); 49703dc76caSSudarsana Reddy Kalluru init_data.cid = qed_spq_get_cid(p_hwfn); 49803dc76caSSudarsana Reddy Kalluru init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 49903dc76caSSudarsana Reddy Kalluru init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 50003dc76caSSudarsana Reddy Kalluru 50103dc76caSSudarsana Reddy Kalluru rc = qed_sp_init_request(p_hwfn, &p_ent, 50203dc76caSSudarsana Reddy Kalluru COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON, 50303dc76caSSudarsana Reddy Kalluru &init_data); 50403dc76caSSudarsana Reddy Kalluru if (rc) 50503dc76caSSudarsana Reddy Kalluru return rc; 50603dc76caSSudarsana Reddy Kalluru 50703dc76caSSudarsana Reddy Kalluru return qed_spq_post(p_hwfn, p_ent, NULL); 50803dc76caSSudarsana Reddy Kalluru } 509