1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/types.h> 10fe56b9e6SYuval Mintz #include <asm/byteorder.h> 11fe56b9e6SYuval Mintz #include <linux/bitops.h> 12fe56b9e6SYuval Mintz #include <linux/errno.h> 13fe56b9e6SYuval Mintz #include <linux/kernel.h> 14fe56b9e6SYuval Mintz #include <linux/string.h> 15fe56b9e6SYuval Mintz #include "qed.h" 16fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 17fe56b9e6SYuval Mintz #include "qed_cxt.h" 18fe56b9e6SYuval Mintz #include "qed_hsi.h" 19fe56b9e6SYuval Mintz #include "qed_hw.h" 20fe56b9e6SYuval Mintz #include "qed_int.h" 21fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 22fe56b9e6SYuval Mintz #include "qed_sp.h" 231408cc1fSYuval Mintz #include "qed_sriov.h" 24fe56b9e6SYuval Mintz 25fe56b9e6SYuval Mintz int qed_sp_init_request(struct qed_hwfn *p_hwfn, 26fe56b9e6SYuval Mintz struct qed_spq_entry **pp_ent, 27fe56b9e6SYuval Mintz u8 cmd, 28fe56b9e6SYuval Mintz u8 protocol, 2906f56b81SYuval Mintz struct qed_sp_init_data *p_data) 30fe56b9e6SYuval Mintz { 3106f56b81SYuval Mintz u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid; 32fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 3306f56b81SYuval Mintz int rc; 34fe56b9e6SYuval Mintz 35fe56b9e6SYuval Mintz if (!pp_ent) 36fe56b9e6SYuval Mintz return -ENOMEM; 37fe56b9e6SYuval Mintz 38fe56b9e6SYuval Mintz rc = qed_spq_get_entry(p_hwfn, pp_ent); 39fe56b9e6SYuval Mintz 40fe56b9e6SYuval Mintz if (rc != 0) 41fe56b9e6SYuval Mintz return rc; 42fe56b9e6SYuval Mintz 43fe56b9e6SYuval Mintz p_ent = *pp_ent; 44fe56b9e6SYuval Mintz 45fe56b9e6SYuval Mintz p_ent->elem.hdr.cid = cpu_to_le32(opaque_cid); 46fe56b9e6SYuval Mintz p_ent->elem.hdr.cmd_id = cmd; 47fe56b9e6SYuval Mintz p_ent->elem.hdr.protocol_id = protocol; 48fe56b9e6SYuval Mintz 49fe56b9e6SYuval Mintz p_ent->priority = QED_SPQ_PRIORITY_NORMAL; 5006f56b81SYuval Mintz p_ent->comp_mode = p_data->comp_mode; 51fe56b9e6SYuval Mintz p_ent->comp_done.done = 0; 52fe56b9e6SYuval Mintz 53fe56b9e6SYuval Mintz switch (p_ent->comp_mode) { 54fe56b9e6SYuval Mintz case QED_SPQ_MODE_EBLOCK: 55fe56b9e6SYuval Mintz p_ent->comp_cb.cookie = &p_ent->comp_done; 56fe56b9e6SYuval Mintz break; 57fe56b9e6SYuval Mintz 58fe56b9e6SYuval Mintz case QED_SPQ_MODE_BLOCK: 5906f56b81SYuval Mintz if (!p_data->p_comp_data) 60fe56b9e6SYuval Mintz return -EINVAL; 61fe56b9e6SYuval Mintz 6206f56b81SYuval Mintz p_ent->comp_cb.cookie = p_data->p_comp_data->cookie; 63fe56b9e6SYuval Mintz break; 64fe56b9e6SYuval Mintz 65fe56b9e6SYuval Mintz case QED_SPQ_MODE_CB: 6606f56b81SYuval Mintz if (!p_data->p_comp_data) 67fe56b9e6SYuval Mintz p_ent->comp_cb.function = NULL; 68fe56b9e6SYuval Mintz else 6906f56b81SYuval Mintz p_ent->comp_cb = *p_data->p_comp_data; 70fe56b9e6SYuval Mintz break; 71fe56b9e6SYuval Mintz 72fe56b9e6SYuval Mintz default: 73fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n", 74fe56b9e6SYuval Mintz p_ent->comp_mode); 75fe56b9e6SYuval Mintz return -EINVAL; 76fe56b9e6SYuval Mintz } 77fe56b9e6SYuval Mintz 78fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 79fe56b9e6SYuval Mintz "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n", 80fe56b9e6SYuval Mintz opaque_cid, cmd, protocol, 81fe56b9e6SYuval Mintz (unsigned long)&p_ent->ramrod, 82fe56b9e6SYuval Mintz D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK, 83fe56b9e6SYuval Mintz QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK", 84fe56b9e6SYuval Mintz "MODE_CB")); 8506f56b81SYuval Mintz 8606f56b81SYuval Mintz memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod)); 87fe56b9e6SYuval Mintz 88fe56b9e6SYuval Mintz return 0; 89fe56b9e6SYuval Mintz } 90fe56b9e6SYuval Mintz 91464f6645SManish Chopra static enum tunnel_clss qed_tunn_get_clss_type(u8 type) 92464f6645SManish Chopra { 93464f6645SManish Chopra switch (type) { 94464f6645SManish Chopra case QED_TUNN_CLSS_MAC_VLAN: 95464f6645SManish Chopra return TUNNEL_CLSS_MAC_VLAN; 96464f6645SManish Chopra case QED_TUNN_CLSS_MAC_VNI: 97464f6645SManish Chopra return TUNNEL_CLSS_MAC_VNI; 98464f6645SManish Chopra case QED_TUNN_CLSS_INNER_MAC_VLAN: 99464f6645SManish Chopra return TUNNEL_CLSS_INNER_MAC_VLAN; 100464f6645SManish Chopra case QED_TUNN_CLSS_INNER_MAC_VNI: 101464f6645SManish Chopra return TUNNEL_CLSS_INNER_MAC_VNI; 102464f6645SManish Chopra default: 103464f6645SManish Chopra return TUNNEL_CLSS_MAC_VLAN; 104464f6645SManish Chopra } 105464f6645SManish Chopra } 106464f6645SManish Chopra 107464f6645SManish Chopra static void 108464f6645SManish Chopra qed_tunn_set_pf_fix_tunn_mode(struct qed_hwfn *p_hwfn, 109464f6645SManish Chopra struct qed_tunn_update_params *p_src, 110464f6645SManish Chopra struct pf_update_tunnel_config *p_tunn_cfg) 111464f6645SManish Chopra { 112464f6645SManish Chopra unsigned long cached_tunn_mode = p_hwfn->cdev->tunn_mode; 113464f6645SManish Chopra unsigned long update_mask = p_src->tunn_mode_update_mask; 114464f6645SManish Chopra unsigned long tunn_mode = p_src->tunn_mode; 115464f6645SManish Chopra unsigned long new_tunn_mode = 0; 116464f6645SManish Chopra 117464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &update_mask)) { 118464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode)) 119464f6645SManish Chopra __set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode); 120464f6645SManish Chopra } else { 121464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &cached_tunn_mode)) 122464f6645SManish Chopra __set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode); 123464f6645SManish Chopra } 124464f6645SManish Chopra 125464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &update_mask)) { 126464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode)) 127464f6645SManish Chopra __set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode); 128464f6645SManish Chopra } else { 129464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &cached_tunn_mode)) 130464f6645SManish Chopra __set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode); 131464f6645SManish Chopra } 132464f6645SManish Chopra 133464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &update_mask)) { 134464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode)) 135464f6645SManish Chopra __set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode); 136464f6645SManish Chopra } else { 137464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &cached_tunn_mode)) 138464f6645SManish Chopra __set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode); 139464f6645SManish Chopra } 140464f6645SManish Chopra 141464f6645SManish Chopra if (p_src->update_geneve_udp_port) { 142464f6645SManish Chopra p_tunn_cfg->set_geneve_udp_port_flg = 1; 143464f6645SManish Chopra p_tunn_cfg->geneve_udp_port = 144464f6645SManish Chopra cpu_to_le16(p_src->geneve_udp_port); 145464f6645SManish Chopra } 146464f6645SManish Chopra 147464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &update_mask)) { 148464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode)) 149464f6645SManish Chopra __set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode); 150464f6645SManish Chopra } else { 151464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &cached_tunn_mode)) 152464f6645SManish Chopra __set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode); 153464f6645SManish Chopra } 154464f6645SManish Chopra 155464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &update_mask)) { 156464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode)) 157464f6645SManish Chopra __set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode); 158464f6645SManish Chopra } else { 159464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &cached_tunn_mode)) 160464f6645SManish Chopra __set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode); 161464f6645SManish Chopra } 162464f6645SManish Chopra 163464f6645SManish Chopra p_src->tunn_mode = new_tunn_mode; 164464f6645SManish Chopra } 165464f6645SManish Chopra 166464f6645SManish Chopra static void 167464f6645SManish Chopra qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn, 168464f6645SManish Chopra struct qed_tunn_update_params *p_src, 169464f6645SManish Chopra struct pf_update_tunnel_config *p_tunn_cfg) 170464f6645SManish Chopra { 171464f6645SManish Chopra unsigned long tunn_mode = p_src->tunn_mode; 172464f6645SManish Chopra enum tunnel_clss type; 173464f6645SManish Chopra 174464f6645SManish Chopra qed_tunn_set_pf_fix_tunn_mode(p_hwfn, p_src, p_tunn_cfg); 175464f6645SManish Chopra p_tunn_cfg->update_rx_pf_clss = p_src->update_rx_pf_clss; 176464f6645SManish Chopra p_tunn_cfg->update_tx_pf_clss = p_src->update_tx_pf_clss; 177464f6645SManish Chopra 178464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan); 179464f6645SManish Chopra p_tunn_cfg->tunnel_clss_vxlan = type; 180464f6645SManish Chopra 181464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre); 182464f6645SManish Chopra p_tunn_cfg->tunnel_clss_l2gre = type; 183464f6645SManish Chopra 184464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre); 185464f6645SManish Chopra p_tunn_cfg->tunnel_clss_ipgre = type; 186464f6645SManish Chopra 187464f6645SManish Chopra if (p_src->update_vxlan_udp_port) { 188464f6645SManish Chopra p_tunn_cfg->set_vxlan_udp_port_flg = 1; 189464f6645SManish Chopra p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port); 190464f6645SManish Chopra } 191464f6645SManish Chopra 192464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode)) 193464f6645SManish Chopra p_tunn_cfg->tx_enable_l2gre = 1; 194464f6645SManish Chopra 195464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode)) 196464f6645SManish Chopra p_tunn_cfg->tx_enable_ipgre = 1; 197464f6645SManish Chopra 198464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode)) 199464f6645SManish Chopra p_tunn_cfg->tx_enable_vxlan = 1; 200464f6645SManish Chopra 201464f6645SManish Chopra if (p_src->update_geneve_udp_port) { 202464f6645SManish Chopra p_tunn_cfg->set_geneve_udp_port_flg = 1; 203464f6645SManish Chopra p_tunn_cfg->geneve_udp_port = 204464f6645SManish Chopra cpu_to_le16(p_src->geneve_udp_port); 205464f6645SManish Chopra } 206464f6645SManish Chopra 207464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode)) 208464f6645SManish Chopra p_tunn_cfg->tx_enable_l2geneve = 1; 209464f6645SManish Chopra 210464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode)) 211464f6645SManish Chopra p_tunn_cfg->tx_enable_ipgeneve = 1; 212464f6645SManish Chopra 213464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve); 214464f6645SManish Chopra p_tunn_cfg->tunnel_clss_l2geneve = type; 215464f6645SManish Chopra 216464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve); 217464f6645SManish Chopra p_tunn_cfg->tunnel_clss_ipgeneve = type; 218464f6645SManish Chopra } 219464f6645SManish Chopra 220464f6645SManish Chopra static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn, 221464f6645SManish Chopra struct qed_ptt *p_ptt, 222464f6645SManish Chopra unsigned long tunn_mode) 223464f6645SManish Chopra { 224464f6645SManish Chopra u8 l2gre_enable = 0, ipgre_enable = 0, vxlan_enable = 0; 225464f6645SManish Chopra u8 l2geneve_enable = 0, ipgeneve_enable = 0; 226464f6645SManish Chopra 227464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode)) 228464f6645SManish Chopra l2gre_enable = 1; 229464f6645SManish Chopra 230464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode)) 231464f6645SManish Chopra ipgre_enable = 1; 232464f6645SManish Chopra 233464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode)) 234464f6645SManish Chopra vxlan_enable = 1; 235464f6645SManish Chopra 236464f6645SManish Chopra qed_set_gre_enable(p_hwfn, p_ptt, l2gre_enable, ipgre_enable); 237464f6645SManish Chopra qed_set_vxlan_enable(p_hwfn, p_ptt, vxlan_enable); 238464f6645SManish Chopra 239464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode)) 240464f6645SManish Chopra l2geneve_enable = 1; 241464f6645SManish Chopra 242464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode)) 243464f6645SManish Chopra ipgeneve_enable = 1; 244464f6645SManish Chopra 245464f6645SManish Chopra qed_set_geneve_enable(p_hwfn, p_ptt, l2geneve_enable, 246464f6645SManish Chopra ipgeneve_enable); 247464f6645SManish Chopra } 248464f6645SManish Chopra 249464f6645SManish Chopra static void 250464f6645SManish Chopra qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn, 251464f6645SManish Chopra struct qed_tunn_start_params *p_src, 252464f6645SManish Chopra struct pf_start_tunnel_config *p_tunn_cfg) 253464f6645SManish Chopra { 254464f6645SManish Chopra unsigned long tunn_mode; 255464f6645SManish Chopra enum tunnel_clss type; 256464f6645SManish Chopra 257464f6645SManish Chopra if (!p_src) 258464f6645SManish Chopra return; 259464f6645SManish Chopra 260464f6645SManish Chopra tunn_mode = p_src->tunn_mode; 261464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan); 262464f6645SManish Chopra p_tunn_cfg->tunnel_clss_vxlan = type; 263464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre); 264464f6645SManish Chopra p_tunn_cfg->tunnel_clss_l2gre = type; 265464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre); 266464f6645SManish Chopra p_tunn_cfg->tunnel_clss_ipgre = type; 267464f6645SManish Chopra 268464f6645SManish Chopra if (p_src->update_vxlan_udp_port) { 269464f6645SManish Chopra p_tunn_cfg->set_vxlan_udp_port_flg = 1; 270464f6645SManish Chopra p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port); 271464f6645SManish Chopra } 272464f6645SManish Chopra 273464f6645SManish Chopra if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode)) 274464f6645SManish Chopra p_tunn_cfg->tx_enable_l2gre = 1; 275464f6645SManish Chopra 276464f6645SManish Chopra if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode)) 277464f6645SManish Chopra p_tunn_cfg->tx_enable_ipgre = 1; 278464f6645SManish Chopra 279464f6645SManish Chopra if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode)) 280464f6645SManish Chopra p_tunn_cfg->tx_enable_vxlan = 1; 281464f6645SManish Chopra 282464f6645SManish Chopra if (p_src->update_geneve_udp_port) { 283464f6645SManish Chopra p_tunn_cfg->set_geneve_udp_port_flg = 1; 284464f6645SManish Chopra p_tunn_cfg->geneve_udp_port = 285464f6645SManish Chopra cpu_to_le16(p_src->geneve_udp_port); 286464f6645SManish Chopra } 287464f6645SManish Chopra 288464f6645SManish Chopra if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode)) 289464f6645SManish Chopra p_tunn_cfg->tx_enable_l2geneve = 1; 290464f6645SManish Chopra 291464f6645SManish Chopra if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode)) 292464f6645SManish Chopra p_tunn_cfg->tx_enable_ipgeneve = 1; 293464f6645SManish Chopra 294464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve); 295464f6645SManish Chopra p_tunn_cfg->tunnel_clss_l2geneve = type; 296464f6645SManish Chopra type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve); 297464f6645SManish Chopra p_tunn_cfg->tunnel_clss_ipgeneve = type; 298464f6645SManish Chopra } 299464f6645SManish Chopra 300fe56b9e6SYuval Mintz int qed_sp_pf_start(struct qed_hwfn *p_hwfn, 301464f6645SManish Chopra struct qed_tunn_start_params *p_tunn, 302831bfb0eSYuval Mintz enum qed_mf_mode mode, bool allow_npar_tx_switch) 303fe56b9e6SYuval Mintz { 304fe56b9e6SYuval Mintz struct pf_start_ramrod_data *p_ramrod = NULL; 305fe56b9e6SYuval Mintz u16 sb = qed_int_get_sp_sb_id(p_hwfn); 306fe56b9e6SYuval Mintz u8 sb_index = p_hwfn->p_eq->eq_sb_index; 307fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 30806f56b81SYuval Mintz struct qed_sp_init_data init_data; 309fe56b9e6SYuval Mintz int rc = -EINVAL; 310fe56b9e6SYuval Mintz 311fe56b9e6SYuval Mintz /* update initial eq producer */ 312fe56b9e6SYuval Mintz qed_eq_prod_update(p_hwfn, 313fe56b9e6SYuval Mintz qed_chain_get_prod_idx(&p_hwfn->p_eq->chain)); 314fe56b9e6SYuval Mintz 31506f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 31606f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 31706f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 31806f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 319fe56b9e6SYuval Mintz 32006f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 321fe56b9e6SYuval Mintz COMMON_RAMROD_PF_START, 322fe56b9e6SYuval Mintz PROTOCOLID_COMMON, 32306f56b81SYuval Mintz &init_data); 324fe56b9e6SYuval Mintz if (rc) 325fe56b9e6SYuval Mintz return rc; 326fe56b9e6SYuval Mintz 327fe56b9e6SYuval Mintz p_ramrod = &p_ent->ramrod.pf_start; 328fe56b9e6SYuval Mintz 329fe56b9e6SYuval Mintz p_ramrod->event_ring_sb_id = cpu_to_le16(sb); 330fe56b9e6SYuval Mintz p_ramrod->event_ring_sb_index = sb_index; 331fe56b9e6SYuval Mintz p_ramrod->path_id = QED_PATH_ID(p_hwfn); 332fe56b9e6SYuval Mintz p_ramrod->dont_log_ramrods = 0; 333fe56b9e6SYuval Mintz p_ramrod->log_type_mask = cpu_to_le16(0xf); 334fe56b9e6SYuval Mintz p_ramrod->mf_mode = mode; 335fc48b7a6SYuval Mintz switch (mode) { 336fc48b7a6SYuval Mintz case QED_MF_DEFAULT: 337fc48b7a6SYuval Mintz case QED_MF_NPAR: 338fc48b7a6SYuval Mintz p_ramrod->mf_mode = MF_NPAR; 339fc48b7a6SYuval Mintz break; 340fc48b7a6SYuval Mintz case QED_MF_OVLAN: 341fc48b7a6SYuval Mintz p_ramrod->mf_mode = MF_OVLAN; 342fc48b7a6SYuval Mintz break; 343fc48b7a6SYuval Mintz default: 344fc48b7a6SYuval Mintz DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 345fc48b7a6SYuval Mintz p_ramrod->mf_mode = MF_NPAR; 346fc48b7a6SYuval Mintz } 347fe56b9e6SYuval Mintz p_ramrod->outer_tag = p_hwfn->hw_info.ovlan; 348fe56b9e6SYuval Mintz 349fe56b9e6SYuval Mintz /* Place EQ address in RAMROD */ 35094494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr, 35194494598SYuval Mintz p_hwfn->p_eq->chain.pbl.p_phys_table); 352fe56b9e6SYuval Mintz p_ramrod->event_ring_num_pages = (u8)p_hwfn->p_eq->chain.page_cnt; 353fe56b9e6SYuval Mintz 35494494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr, 35594494598SYuval Mintz p_hwfn->p_consq->chain.pbl.p_phys_table); 356fe56b9e6SYuval Mintz 357b18e170cSManish Chopra qed_tunn_set_pf_start_params(p_hwfn, p_tunn, 358b18e170cSManish Chopra &p_ramrod->tunnel_config); 359fe56b9e6SYuval Mintz p_hwfn->hw_info.personality = PERSONALITY_ETH; 360fe56b9e6SYuval Mintz 361831bfb0eSYuval Mintz if (IS_MF_SI(p_hwfn)) 362831bfb0eSYuval Mintz p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch; 363831bfb0eSYuval Mintz 3641408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 3651408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 3661408cc1fSYuval Mintz 3671408cc1fSYuval Mintz p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf; 3681408cc1fSYuval Mintz p_ramrod->num_vfs = (u8) p_iov->total_vfs; 3691408cc1fSYuval Mintz } 3701408cc1fSYuval Mintz 371fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 372fc48b7a6SYuval Mintz "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n", 373fe56b9e6SYuval Mintz sb, sb_index, 374fe56b9e6SYuval Mintz p_ramrod->outer_tag); 375fe56b9e6SYuval Mintz 376c0f31a05SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 377c0f31a05SManish Chopra 378c0f31a05SManish Chopra if (p_tunn) { 379c0f31a05SManish Chopra qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, 380c0f31a05SManish Chopra p_tunn->tunn_mode); 381c0f31a05SManish Chopra p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode; 382c0f31a05SManish Chopra } 383c0f31a05SManish Chopra 384c0f31a05SManish Chopra return rc; 385fe56b9e6SYuval Mintz } 386fe56b9e6SYuval Mintz 387464f6645SManish Chopra /* Set pf update ramrod command params */ 388464f6645SManish Chopra int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn, 389464f6645SManish Chopra struct qed_tunn_update_params *p_tunn, 390464f6645SManish Chopra enum spq_mode comp_mode, 391464f6645SManish Chopra struct qed_spq_comp_cb *p_comp_data) 392464f6645SManish Chopra { 393464f6645SManish Chopra struct qed_spq_entry *p_ent = NULL; 394464f6645SManish Chopra struct qed_sp_init_data init_data; 395464f6645SManish Chopra int rc = -EINVAL; 396464f6645SManish Chopra 397464f6645SManish Chopra /* Get SPQ entry */ 398464f6645SManish Chopra memset(&init_data, 0, sizeof(init_data)); 399464f6645SManish Chopra init_data.cid = qed_spq_get_cid(p_hwfn); 400464f6645SManish Chopra init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 401464f6645SManish Chopra init_data.comp_mode = comp_mode; 402464f6645SManish Chopra init_data.p_comp_data = p_comp_data; 403464f6645SManish Chopra 404464f6645SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 405464f6645SManish Chopra COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 406464f6645SManish Chopra &init_data); 407464f6645SManish Chopra if (rc) 408464f6645SManish Chopra return rc; 409464f6645SManish Chopra 410464f6645SManish Chopra qed_tunn_set_pf_update_params(p_hwfn, p_tunn, 411464f6645SManish Chopra &p_ent->ramrod.pf_update.tunnel_config); 412464f6645SManish Chopra 413464f6645SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 414464f6645SManish Chopra if (rc) 415464f6645SManish Chopra return rc; 416464f6645SManish Chopra 417464f6645SManish Chopra if (p_tunn->update_vxlan_udp_port) 418464f6645SManish Chopra qed_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt, 419464f6645SManish Chopra p_tunn->vxlan_udp_port); 420464f6645SManish Chopra if (p_tunn->update_geneve_udp_port) 421464f6645SManish Chopra qed_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt, 422464f6645SManish Chopra p_tunn->geneve_udp_port); 423464f6645SManish Chopra 424464f6645SManish Chopra qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode); 425464f6645SManish Chopra p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode; 426464f6645SManish Chopra 427464f6645SManish Chopra return rc; 428464f6645SManish Chopra } 429464f6645SManish Chopra 430fe56b9e6SYuval Mintz int qed_sp_pf_stop(struct qed_hwfn *p_hwfn) 431fe56b9e6SYuval Mintz { 432fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 43306f56b81SYuval Mintz struct qed_sp_init_data init_data; 434fe56b9e6SYuval Mintz int rc = -EINVAL; 435fe56b9e6SYuval Mintz 43606f56b81SYuval Mintz /* Get SPQ entry */ 43706f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 43806f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 43906f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 44006f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 441fe56b9e6SYuval Mintz 44206f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 443fe56b9e6SYuval Mintz COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON, 44406f56b81SYuval Mintz &init_data); 445fe56b9e6SYuval Mintz if (rc) 446fe56b9e6SYuval Mintz return rc; 447fe56b9e6SYuval Mintz 448fe56b9e6SYuval Mintz return qed_spq_post(p_hwfn, p_ent, NULL); 449fe56b9e6SYuval Mintz } 45003dc76caSSudarsana Reddy Kalluru 45103dc76caSSudarsana Reddy Kalluru int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn) 45203dc76caSSudarsana Reddy Kalluru { 45303dc76caSSudarsana Reddy Kalluru struct qed_spq_entry *p_ent = NULL; 45403dc76caSSudarsana Reddy Kalluru struct qed_sp_init_data init_data; 45503dc76caSSudarsana Reddy Kalluru int rc; 45603dc76caSSudarsana Reddy Kalluru 45703dc76caSSudarsana Reddy Kalluru /* Get SPQ entry */ 45803dc76caSSudarsana Reddy Kalluru memset(&init_data, 0, sizeof(init_data)); 45903dc76caSSudarsana Reddy Kalluru init_data.cid = qed_spq_get_cid(p_hwfn); 46003dc76caSSudarsana Reddy Kalluru init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 46103dc76caSSudarsana Reddy Kalluru init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 46203dc76caSSudarsana Reddy Kalluru 46303dc76caSSudarsana Reddy Kalluru rc = qed_sp_init_request(p_hwfn, &p_ent, 46403dc76caSSudarsana Reddy Kalluru COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON, 46503dc76caSSudarsana Reddy Kalluru &init_data); 46603dc76caSSudarsana Reddy Kalluru if (rc) 46703dc76caSSudarsana Reddy Kalluru return rc; 46803dc76caSSudarsana Reddy Kalluru 46903dc76caSSudarsana Reddy Kalluru return qed_spq_post(p_hwfn, p_ent, NULL); 47003dc76caSSudarsana Reddy Kalluru } 471