1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/bitops.h> 36fe56b9e6SYuval Mintz #include <linux/errno.h> 37fe56b9e6SYuval Mintz #include <linux/kernel.h> 38fe56b9e6SYuval Mintz #include <linux/string.h> 39fe56b9e6SYuval Mintz #include "qed.h" 40fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 41fe56b9e6SYuval Mintz #include "qed_cxt.h" 4239651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 43fe56b9e6SYuval Mintz #include "qed_hsi.h" 44fe56b9e6SYuval Mintz #include "qed_hw.h" 45fe56b9e6SYuval Mintz #include "qed_int.h" 46fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 47fe56b9e6SYuval Mintz #include "qed_sp.h" 481408cc1fSYuval Mintz #include "qed_sriov.h" 49fe56b9e6SYuval Mintz 50fe56b9e6SYuval Mintz int qed_sp_init_request(struct qed_hwfn *p_hwfn, 51fe56b9e6SYuval Mintz struct qed_spq_entry **pp_ent, 521a635e48SYuval Mintz u8 cmd, u8 protocol, struct qed_sp_init_data *p_data) 53fe56b9e6SYuval Mintz { 5406f56b81SYuval Mintz u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid; 55fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 5606f56b81SYuval Mintz int rc; 57fe56b9e6SYuval Mintz 58fe56b9e6SYuval Mintz if (!pp_ent) 59fe56b9e6SYuval Mintz return -ENOMEM; 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz rc = qed_spq_get_entry(p_hwfn, pp_ent); 62fe56b9e6SYuval Mintz 631a635e48SYuval Mintz if (rc) 64fe56b9e6SYuval Mintz return rc; 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz p_ent = *pp_ent; 67fe56b9e6SYuval Mintz 68fe56b9e6SYuval Mintz p_ent->elem.hdr.cid = cpu_to_le32(opaque_cid); 69fe56b9e6SYuval Mintz p_ent->elem.hdr.cmd_id = cmd; 70fe56b9e6SYuval Mintz p_ent->elem.hdr.protocol_id = protocol; 71fe56b9e6SYuval Mintz 72fe56b9e6SYuval Mintz p_ent->priority = QED_SPQ_PRIORITY_NORMAL; 7306f56b81SYuval Mintz p_ent->comp_mode = p_data->comp_mode; 74fe56b9e6SYuval Mintz p_ent->comp_done.done = 0; 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz switch (p_ent->comp_mode) { 77fe56b9e6SYuval Mintz case QED_SPQ_MODE_EBLOCK: 78fe56b9e6SYuval Mintz p_ent->comp_cb.cookie = &p_ent->comp_done; 79fe56b9e6SYuval Mintz break; 80fe56b9e6SYuval Mintz 81fe56b9e6SYuval Mintz case QED_SPQ_MODE_BLOCK: 8206f56b81SYuval Mintz if (!p_data->p_comp_data) 8339477551SDenis Bolotin goto err; 84fe56b9e6SYuval Mintz 8506f56b81SYuval Mintz p_ent->comp_cb.cookie = p_data->p_comp_data->cookie; 86fe56b9e6SYuval Mintz break; 87fe56b9e6SYuval Mintz 88fe56b9e6SYuval Mintz case QED_SPQ_MODE_CB: 8906f56b81SYuval Mintz if (!p_data->p_comp_data) 90fe56b9e6SYuval Mintz p_ent->comp_cb.function = NULL; 91fe56b9e6SYuval Mintz else 9206f56b81SYuval Mintz p_ent->comp_cb = *p_data->p_comp_data; 93fe56b9e6SYuval Mintz break; 94fe56b9e6SYuval Mintz 95fe56b9e6SYuval Mintz default: 96fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n", 97fe56b9e6SYuval Mintz p_ent->comp_mode); 9839477551SDenis Bolotin goto err; 99fe56b9e6SYuval Mintz } 100fe56b9e6SYuval Mintz 101fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 102fe56b9e6SYuval Mintz "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n", 103fe56b9e6SYuval Mintz opaque_cid, cmd, protocol, 104fe56b9e6SYuval Mintz (unsigned long)&p_ent->ramrod, 105fe56b9e6SYuval Mintz D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK, 106fe56b9e6SYuval Mintz QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK", 107fe56b9e6SYuval Mintz "MODE_CB")); 10806f56b81SYuval Mintz 10906f56b81SYuval Mintz memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod)); 110fe56b9e6SYuval Mintz 111fe56b9e6SYuval Mintz return 0; 11239477551SDenis Bolotin 11339477551SDenis Bolotin err: 11439477551SDenis Bolotin /* qed_spq_get_entry() can either get an entry from the free_pool, 11539477551SDenis Bolotin * or, if no entries are left, allocate a new entry and add it to 11639477551SDenis Bolotin * the unlimited_pending list. 11739477551SDenis Bolotin */ 11839477551SDenis Bolotin if (p_ent->queue == &p_hwfn->p_spq->unlimited_pending) 11939477551SDenis Bolotin kfree(p_ent); 12039477551SDenis Bolotin else 12139477551SDenis Bolotin qed_spq_return_entry(p_hwfn, p_ent); 12239477551SDenis Bolotin 12339477551SDenis Bolotin return -EINVAL; 124fe56b9e6SYuval Mintz } 125fe56b9e6SYuval Mintz 12619968430SChopra, Manish static enum tunnel_clss qed_tunn_clss_to_fw_clss(u8 type) 127464f6645SManish Chopra { 128464f6645SManish Chopra switch (type) { 129464f6645SManish Chopra case QED_TUNN_CLSS_MAC_VLAN: 130464f6645SManish Chopra return TUNNEL_CLSS_MAC_VLAN; 131464f6645SManish Chopra case QED_TUNN_CLSS_MAC_VNI: 132464f6645SManish Chopra return TUNNEL_CLSS_MAC_VNI; 133464f6645SManish Chopra case QED_TUNN_CLSS_INNER_MAC_VLAN: 134464f6645SManish Chopra return TUNNEL_CLSS_INNER_MAC_VLAN; 135464f6645SManish Chopra case QED_TUNN_CLSS_INNER_MAC_VNI: 136464f6645SManish Chopra return TUNNEL_CLSS_INNER_MAC_VNI; 13719968430SChopra, Manish case QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE: 13819968430SChopra, Manish return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE; 139464f6645SManish Chopra default: 140464f6645SManish Chopra return TUNNEL_CLSS_MAC_VLAN; 141464f6645SManish Chopra } 142464f6645SManish Chopra } 143464f6645SManish Chopra 144464f6645SManish Chopra static void 14519968430SChopra, Manish qed_set_pf_update_tunn_mode(struct qed_tunnel_info *p_tun, 14619968430SChopra, Manish struct qed_tunnel_info *p_src, bool b_pf_start) 147464f6645SManish Chopra { 14819968430SChopra, Manish if (p_src->vxlan.b_update_mode || b_pf_start) 14919968430SChopra, Manish p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled; 150464f6645SManish Chopra 15119968430SChopra, Manish if (p_src->l2_gre.b_update_mode || b_pf_start) 15219968430SChopra, Manish p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled; 15319968430SChopra, Manish 15419968430SChopra, Manish if (p_src->ip_gre.b_update_mode || b_pf_start) 15519968430SChopra, Manish p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled; 15619968430SChopra, Manish 15719968430SChopra, Manish if (p_src->l2_geneve.b_update_mode || b_pf_start) 15819968430SChopra, Manish p_tun->l2_geneve.b_mode_enabled = 15919968430SChopra, Manish p_src->l2_geneve.b_mode_enabled; 16019968430SChopra, Manish 16119968430SChopra, Manish if (p_src->ip_geneve.b_update_mode || b_pf_start) 16219968430SChopra, Manish p_tun->ip_geneve.b_mode_enabled = 16319968430SChopra, Manish p_src->ip_geneve.b_mode_enabled; 164464f6645SManish Chopra } 165464f6645SManish Chopra 16619968430SChopra, Manish static void qed_set_tunn_cls_info(struct qed_tunnel_info *p_tun, 16719968430SChopra, Manish struct qed_tunnel_info *p_src) 16819968430SChopra, Manish { 169a898fba3SNathan Chancellor int type; 17019968430SChopra, Manish 17119968430SChopra, Manish p_tun->b_update_rx_cls = p_src->b_update_rx_cls; 17219968430SChopra, Manish p_tun->b_update_tx_cls = p_src->b_update_tx_cls; 17319968430SChopra, Manish 17419968430SChopra, Manish type = qed_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls); 17519968430SChopra, Manish p_tun->vxlan.tun_cls = type; 17619968430SChopra, Manish type = qed_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls); 17719968430SChopra, Manish p_tun->l2_gre.tun_cls = type; 17819968430SChopra, Manish type = qed_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls); 17919968430SChopra, Manish p_tun->ip_gre.tun_cls = type; 18019968430SChopra, Manish type = qed_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls); 18119968430SChopra, Manish p_tun->l2_geneve.tun_cls = type; 18219968430SChopra, Manish type = qed_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls); 18319968430SChopra, Manish p_tun->ip_geneve.tun_cls = type; 184464f6645SManish Chopra } 185464f6645SManish Chopra 18619968430SChopra, Manish static void qed_set_tunn_ports(struct qed_tunnel_info *p_tun, 18719968430SChopra, Manish struct qed_tunnel_info *p_src) 18819968430SChopra, Manish { 18919968430SChopra, Manish p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port; 19019968430SChopra, Manish p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port; 19119968430SChopra, Manish 19219968430SChopra, Manish if (p_src->geneve_port.b_update_port) 19319968430SChopra, Manish p_tun->geneve_port.port = p_src->geneve_port.port; 19419968430SChopra, Manish 19519968430SChopra, Manish if (p_src->vxlan_port.b_update_port) 19619968430SChopra, Manish p_tun->vxlan_port.port = p_src->vxlan_port.port; 197464f6645SManish Chopra } 198464f6645SManish Chopra 19919968430SChopra, Manish static void 2007b6859fbSMintz, Yuval __qed_set_ramrod_tunnel_param(u8 *p_tunn_cls, 20119968430SChopra, Manish struct qed_tunn_update_type *tun_type) 20219968430SChopra, Manish { 20319968430SChopra, Manish *p_tunn_cls = tun_type->tun_cls; 204464f6645SManish Chopra } 205464f6645SManish Chopra 20619968430SChopra, Manish static void 2077b6859fbSMintz, Yuval qed_set_ramrod_tunnel_param(u8 *p_tunn_cls, 20819968430SChopra, Manish struct qed_tunn_update_type *tun_type, 2097b6859fbSMintz, Yuval u8 *p_update_port, 2107b6859fbSMintz, Yuval __le16 *p_port, 21119968430SChopra, Manish struct qed_tunn_update_udp_port *p_udp_port) 21219968430SChopra, Manish { 2137b6859fbSMintz, Yuval __qed_set_ramrod_tunnel_param(p_tunn_cls, tun_type); 21419968430SChopra, Manish if (p_udp_port->b_update_port) { 21519968430SChopra, Manish *p_update_port = 1; 21619968430SChopra, Manish *p_port = cpu_to_le16(p_udp_port->port); 217464f6645SManish Chopra } 218464f6645SManish Chopra } 219464f6645SManish Chopra 220464f6645SManish Chopra static void 221464f6645SManish Chopra qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn, 22219968430SChopra, Manish struct qed_tunnel_info *p_src, 223464f6645SManish Chopra struct pf_update_tunnel_config *p_tunn_cfg) 224464f6645SManish Chopra { 22519968430SChopra, Manish struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel; 226464f6645SManish Chopra 22719968430SChopra, Manish qed_set_pf_update_tunn_mode(p_tun, p_src, false); 22819968430SChopra, Manish qed_set_tunn_cls_info(p_tun, p_src); 22919968430SChopra, Manish qed_set_tunn_ports(p_tun, p_src); 230464f6645SManish Chopra 23119968430SChopra, Manish qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan, 23219968430SChopra, Manish &p_tun->vxlan, 23319968430SChopra, Manish &p_tunn_cfg->set_vxlan_udp_port_flg, 23419968430SChopra, Manish &p_tunn_cfg->vxlan_udp_port, 23519968430SChopra, Manish &p_tun->vxlan_port); 236464f6645SManish Chopra 23719968430SChopra, Manish qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve, 23819968430SChopra, Manish &p_tun->l2_geneve, 23919968430SChopra, Manish &p_tunn_cfg->set_geneve_udp_port_flg, 24019968430SChopra, Manish &p_tunn_cfg->geneve_udp_port, 24119968430SChopra, Manish &p_tun->geneve_port); 242464f6645SManish Chopra 24319968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve, 24419968430SChopra, Manish &p_tun->ip_geneve); 245464f6645SManish Chopra 24619968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre, 24719968430SChopra, Manish &p_tun->l2_gre); 248464f6645SManish Chopra 24919968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre, 25019968430SChopra, Manish &p_tun->ip_gre); 251464f6645SManish Chopra 25219968430SChopra, Manish p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls; 253464f6645SManish Chopra } 254464f6645SManish Chopra 255464f6645SManish Chopra static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn, 256464f6645SManish Chopra struct qed_ptt *p_ptt, 25719968430SChopra, Manish struct qed_tunnel_info *p_tun) 258464f6645SManish Chopra { 25919968430SChopra, Manish qed_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled, 26019968430SChopra, Manish p_tun->ip_gre.b_mode_enabled); 26119968430SChopra, Manish qed_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled); 262464f6645SManish Chopra 26319968430SChopra, Manish qed_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled, 26419968430SChopra, Manish p_tun->ip_geneve.b_mode_enabled); 26519968430SChopra, Manish } 266464f6645SManish Chopra 26719968430SChopra, Manish static void qed_set_hw_tunn_mode_port(struct qed_hwfn *p_hwfn, 2684f64675fSManish Chopra struct qed_ptt *p_ptt, 26919968430SChopra, Manish struct qed_tunnel_info *p_tunn) 27019968430SChopra, Manish { 27119968430SChopra, Manish if (p_tunn->vxlan_port.b_update_port) 2724f64675fSManish Chopra qed_set_vxlan_dest_port(p_hwfn, p_ptt, 27319968430SChopra, Manish p_tunn->vxlan_port.port); 274464f6645SManish Chopra 27519968430SChopra, Manish if (p_tunn->geneve_port.b_update_port) 2764f64675fSManish Chopra qed_set_geneve_dest_port(p_hwfn, p_ptt, 27719968430SChopra, Manish p_tunn->geneve_port.port); 278464f6645SManish Chopra 2794f64675fSManish Chopra qed_set_hw_tunn_mode(p_hwfn, p_ptt, p_tunn); 280464f6645SManish Chopra } 281464f6645SManish Chopra 282464f6645SManish Chopra static void 283464f6645SManish Chopra qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn, 28419968430SChopra, Manish struct qed_tunnel_info *p_src, 285464f6645SManish Chopra struct pf_start_tunnel_config *p_tunn_cfg) 286464f6645SManish Chopra { 28719968430SChopra, Manish struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel; 288464f6645SManish Chopra 289464f6645SManish Chopra if (!p_src) 290464f6645SManish Chopra return; 291464f6645SManish Chopra 29219968430SChopra, Manish qed_set_pf_update_tunn_mode(p_tun, p_src, true); 29319968430SChopra, Manish qed_set_tunn_cls_info(p_tun, p_src); 29419968430SChopra, Manish qed_set_tunn_ports(p_tun, p_src); 295464f6645SManish Chopra 29619968430SChopra, Manish qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan, 29719968430SChopra, Manish &p_tun->vxlan, 29819968430SChopra, Manish &p_tunn_cfg->set_vxlan_udp_port_flg, 29919968430SChopra, Manish &p_tunn_cfg->vxlan_udp_port, 30019968430SChopra, Manish &p_tun->vxlan_port); 301464f6645SManish Chopra 30219968430SChopra, Manish qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve, 30319968430SChopra, Manish &p_tun->l2_geneve, 30419968430SChopra, Manish &p_tunn_cfg->set_geneve_udp_port_flg, 30519968430SChopra, Manish &p_tunn_cfg->geneve_udp_port, 30619968430SChopra, Manish &p_tun->geneve_port); 307464f6645SManish Chopra 30819968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve, 30919968430SChopra, Manish &p_tun->ip_geneve); 310464f6645SManish Chopra 31119968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre, 31219968430SChopra, Manish &p_tun->l2_gre); 313464f6645SManish Chopra 31419968430SChopra, Manish __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre, 31519968430SChopra, Manish &p_tun->ip_gre); 316464f6645SManish Chopra } 317464f6645SManish Chopra 318fe56b9e6SYuval Mintz int qed_sp_pf_start(struct qed_hwfn *p_hwfn, 3194f64675fSManish Chopra struct qed_ptt *p_ptt, 32019968430SChopra, Manish struct qed_tunnel_info *p_tunn, 3210bc5fe85SSudarsana Reddy Kalluru bool allow_npar_tx_switch) 322fe56b9e6SYuval Mintz { 323fe56b9e6SYuval Mintz struct pf_start_ramrod_data *p_ramrod = NULL; 324fe56b9e6SYuval Mintz u16 sb = qed_int_get_sp_sb_id(p_hwfn); 325fe56b9e6SYuval Mintz u8 sb_index = p_hwfn->p_eq->eq_sb_index; 326fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 32706f56b81SYuval Mintz struct qed_sp_init_data init_data; 328fe56b9e6SYuval Mintz int rc = -EINVAL; 329cac6f691SSudarsana Reddy Kalluru u8 page_cnt, i; 330fe56b9e6SYuval Mintz 331fe56b9e6SYuval Mintz /* update initial eq producer */ 332fe56b9e6SYuval Mintz qed_eq_prod_update(p_hwfn, 333fe56b9e6SYuval Mintz qed_chain_get_prod_idx(&p_hwfn->p_eq->chain)); 334fe56b9e6SYuval Mintz 33506f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 33606f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 33706f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 33806f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 339fe56b9e6SYuval Mintz 34006f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 341fe56b9e6SYuval Mintz COMMON_RAMROD_PF_START, 3421a635e48SYuval Mintz PROTOCOLID_COMMON, &init_data); 343fe56b9e6SYuval Mintz if (rc) 344fe56b9e6SYuval Mintz return rc; 345fe56b9e6SYuval Mintz 346fe56b9e6SYuval Mintz p_ramrod = &p_ent->ramrod.pf_start; 347fe56b9e6SYuval Mintz 348fe56b9e6SYuval Mintz p_ramrod->event_ring_sb_id = cpu_to_le16(sb); 349fe56b9e6SYuval Mintz p_ramrod->event_ring_sb_index = sb_index; 350fe56b9e6SYuval Mintz p_ramrod->path_id = QED_PATH_ID(p_hwfn); 351fe56b9e6SYuval Mintz p_ramrod->dont_log_ramrods = 0; 352fe56b9e6SYuval Mintz p_ramrod->log_type_mask = cpu_to_le16(0xf); 353351a4dedSYuval Mintz 3540bc5fe85SSudarsana Reddy Kalluru if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) 355fc48b7a6SYuval Mintz p_ramrod->mf_mode = MF_OVLAN; 3560bc5fe85SSudarsana Reddy Kalluru else 357fc48b7a6SYuval Mintz p_ramrod->mf_mode = MF_NPAR; 358da090917STomer Tayar 359da090917STomer Tayar p_ramrod->outer_tag_config.outer_tag.tci = 360da090917STomer Tayar cpu_to_le16(p_hwfn->hw_info.ovlan); 361cac6f691SSudarsana Reddy Kalluru if (test_bit(QED_MF_8021Q_TAGGING, &p_hwfn->cdev->mf_bits)) { 362cac6f691SSudarsana Reddy Kalluru p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021Q; 363cac6f691SSudarsana Reddy Kalluru } else if (test_bit(QED_MF_8021AD_TAGGING, &p_hwfn->cdev->mf_bits)) { 364b51bdfb9SSudarsana Reddy Kalluru p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021AD; 365b51bdfb9SSudarsana Reddy Kalluru p_ramrod->outer_tag_config.enable_stag_pri_change = 1; 366b51bdfb9SSudarsana Reddy Kalluru } 367b51bdfb9SSudarsana Reddy Kalluru 368cac6f691SSudarsana Reddy Kalluru p_ramrod->outer_tag_config.pri_map_valid = 1; 369cac6f691SSudarsana Reddy Kalluru for (i = 0; i < QED_MAX_PFC_PRIORITIES; i++) 370cac6f691SSudarsana Reddy Kalluru p_ramrod->outer_tag_config.inner_to_outer_pri_map[i] = i; 371cac6f691SSudarsana Reddy Kalluru 372cac6f691SSudarsana Reddy Kalluru /* enable_stag_pri_change should be set if port is in BD mode or, 373cac6f691SSudarsana Reddy Kalluru * UFP with Host Control mode. 374cac6f691SSudarsana Reddy Kalluru */ 375cac6f691SSudarsana Reddy Kalluru if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) { 376cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_OS) 377cac6f691SSudarsana Reddy Kalluru p_ramrod->outer_tag_config.enable_stag_pri_change = 1; 378cac6f691SSudarsana Reddy Kalluru else 379cac6f691SSudarsana Reddy Kalluru p_ramrod->outer_tag_config.enable_stag_pri_change = 0; 380cac6f691SSudarsana Reddy Kalluru 381cac6f691SSudarsana Reddy Kalluru p_ramrod->outer_tag_config.outer_tag.tci |= 382cac6f691SSudarsana Reddy Kalluru cpu_to_le16(((u16)p_hwfn->ufp_info.tc << 13)); 383cac6f691SSudarsana Reddy Kalluru } 384fe56b9e6SYuval Mintz 385fe56b9e6SYuval Mintz /* Place EQ address in RAMROD */ 38694494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr, 3876d937acfSMintz, Yuval p_hwfn->p_eq->chain.pbl_sp.p_phys_table); 388a91eb52aSYuval Mintz page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain); 389a91eb52aSYuval Mintz p_ramrod->event_ring_num_pages = page_cnt; 39094494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr, 3916d937acfSMintz, Yuval p_hwfn->p_consq->chain.pbl_sp.p_phys_table); 392fe56b9e6SYuval Mintz 3931a635e48SYuval Mintz qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config); 394fe56b9e6SYuval Mintz 3950bc5fe85SSudarsana Reddy Kalluru if (test_bit(QED_MF_INTER_PF_SWITCH, &p_hwfn->cdev->mf_bits)) 396831bfb0eSYuval Mintz p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch; 397831bfb0eSYuval Mintz 398c5ac9319SYuval Mintz switch (p_hwfn->hw_info.personality) { 399c5ac9319SYuval Mintz case QED_PCI_ETH: 400c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_ETH; 401c5ac9319SYuval Mintz break; 4021e128c81SArun Easi case QED_PCI_FCOE: 4031e128c81SArun Easi p_ramrod->personality = PERSONALITY_FCOE; 4041e128c81SArun Easi break; 405c5ac9319SYuval Mintz case QED_PCI_ISCSI: 406c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_ISCSI; 407c5ac9319SYuval Mintz break; 408c5ac9319SYuval Mintz case QED_PCI_ETH_ROCE: 409e0a8f9deSMichal Kalderon case QED_PCI_ETH_IWARP: 410c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_RDMA_AND_ETH; 411c5ac9319SYuval Mintz break; 412c5ac9319SYuval Mintz default: 4139165dabbSMasanari Iida DP_NOTICE(p_hwfn, "Unknown personality %d\n", 414c5ac9319SYuval Mintz p_hwfn->hw_info.personality); 415c5ac9319SYuval Mintz p_ramrod->personality = PERSONALITY_ETH; 416c5ac9319SYuval Mintz } 417c5ac9319SYuval Mintz 4181408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 4191408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 4201408cc1fSYuval Mintz 4211408cc1fSYuval Mintz p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf; 4221408cc1fSYuval Mintz p_ramrod->num_vfs = (u8) p_iov->total_vfs; 4231408cc1fSYuval Mintz } 424351a4dedSYuval Mintz p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR; 425351a4dedSYuval Mintz p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR; 4261408cc1fSYuval Mintz 427fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 428da090917STomer Tayar "Setting event_ring_sb [id %04x index %02x], outer_tag.tci [%d]\n", 429da090917STomer Tayar sb, sb_index, p_ramrod->outer_tag_config.outer_tag.tci); 430fe56b9e6SYuval Mintz 431c0f31a05SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 432c0f31a05SManish Chopra 43319968430SChopra, Manish if (p_tunn) 4344f64675fSManish Chopra qed_set_hw_tunn_mode_port(p_hwfn, p_ptt, 4354f64675fSManish Chopra &p_hwfn->cdev->tunnel); 436c0f31a05SManish Chopra 437c0f31a05SManish Chopra return rc; 438fe56b9e6SYuval Mintz } 439fe56b9e6SYuval Mintz 44039651abdSSudarsana Reddy Kalluru int qed_sp_pf_update(struct qed_hwfn *p_hwfn) 44139651abdSSudarsana Reddy Kalluru { 44239651abdSSudarsana Reddy Kalluru struct qed_spq_entry *p_ent = NULL; 44339651abdSSudarsana Reddy Kalluru struct qed_sp_init_data init_data; 44439651abdSSudarsana Reddy Kalluru int rc = -EINVAL; 44539651abdSSudarsana Reddy Kalluru 44639651abdSSudarsana Reddy Kalluru /* Get SPQ entry */ 44739651abdSSudarsana Reddy Kalluru memset(&init_data, 0, sizeof(init_data)); 44839651abdSSudarsana Reddy Kalluru init_data.cid = qed_spq_get_cid(p_hwfn); 44939651abdSSudarsana Reddy Kalluru init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 45039651abdSSudarsana Reddy Kalluru init_data.comp_mode = QED_SPQ_MODE_CB; 45139651abdSSudarsana Reddy Kalluru 45239651abdSSudarsana Reddy Kalluru rc = qed_sp_init_request(p_hwfn, &p_ent, 45339651abdSSudarsana Reddy Kalluru COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 45439651abdSSudarsana Reddy Kalluru &init_data); 45539651abdSSudarsana Reddy Kalluru if (rc) 45639651abdSSudarsana Reddy Kalluru return rc; 45739651abdSSudarsana Reddy Kalluru 45839651abdSSudarsana Reddy Kalluru qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results, 45939651abdSSudarsana Reddy Kalluru &p_ent->ramrod.pf_update); 46039651abdSSudarsana Reddy Kalluru 46139651abdSSudarsana Reddy Kalluru return qed_spq_post(p_hwfn, p_ent, NULL); 46239651abdSSudarsana Reddy Kalluru } 46339651abdSSudarsana Reddy Kalluru 464cac6f691SSudarsana Reddy Kalluru int qed_sp_pf_update_ufp(struct qed_hwfn *p_hwfn) 465cac6f691SSudarsana Reddy Kalluru { 466cac6f691SSudarsana Reddy Kalluru struct qed_spq_entry *p_ent = NULL; 467cac6f691SSudarsana Reddy Kalluru struct qed_sp_init_data init_data; 468cac6f691SSudarsana Reddy Kalluru int rc = -EOPNOTSUPP; 469cac6f691SSudarsana Reddy Kalluru 470cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_UNKNOWN) { 471cac6f691SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "Invalid priority type %d\n", 472cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type); 473cac6f691SSudarsana Reddy Kalluru return -EINVAL; 474cac6f691SSudarsana Reddy Kalluru } 475cac6f691SSudarsana Reddy Kalluru 476cac6f691SSudarsana Reddy Kalluru /* Get SPQ entry */ 477cac6f691SSudarsana Reddy Kalluru memset(&init_data, 0, sizeof(init_data)); 478cac6f691SSudarsana Reddy Kalluru init_data.cid = qed_spq_get_cid(p_hwfn); 479cac6f691SSudarsana Reddy Kalluru init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 480cac6f691SSudarsana Reddy Kalluru init_data.comp_mode = QED_SPQ_MODE_CB; 481cac6f691SSudarsana Reddy Kalluru 482cac6f691SSudarsana Reddy Kalluru rc = qed_sp_init_request(p_hwfn, &p_ent, 483cac6f691SSudarsana Reddy Kalluru COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 484cac6f691SSudarsana Reddy Kalluru &init_data); 485cac6f691SSudarsana Reddy Kalluru if (rc) 486cac6f691SSudarsana Reddy Kalluru return rc; 487cac6f691SSudarsana Reddy Kalluru 488cac6f691SSudarsana Reddy Kalluru p_ent->ramrod.pf_update.update_enable_stag_pri_change = true; 489cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_OS) 490cac6f691SSudarsana Reddy Kalluru p_ent->ramrod.pf_update.enable_stag_pri_change = 1; 491cac6f691SSudarsana Reddy Kalluru else 492cac6f691SSudarsana Reddy Kalluru p_ent->ramrod.pf_update.enable_stag_pri_change = 0; 493cac6f691SSudarsana Reddy Kalluru 494cac6f691SSudarsana Reddy Kalluru return qed_spq_post(p_hwfn, p_ent, NULL); 495cac6f691SSudarsana Reddy Kalluru } 496cac6f691SSudarsana Reddy Kalluru 497464f6645SManish Chopra /* Set pf update ramrod command params */ 498464f6645SManish Chopra int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn, 4994f64675fSManish Chopra struct qed_ptt *p_ptt, 50019968430SChopra, Manish struct qed_tunnel_info *p_tunn, 501464f6645SManish Chopra enum spq_mode comp_mode, 502464f6645SManish Chopra struct qed_spq_comp_cb *p_comp_data) 503464f6645SManish Chopra { 504464f6645SManish Chopra struct qed_spq_entry *p_ent = NULL; 505464f6645SManish Chopra struct qed_sp_init_data init_data; 506464f6645SManish Chopra int rc = -EINVAL; 507464f6645SManish Chopra 508eaf3c0c6SChopra, Manish if (IS_VF(p_hwfn->cdev)) 509eaf3c0c6SChopra, Manish return qed_vf_pf_tunnel_param_update(p_hwfn, p_tunn); 510eaf3c0c6SChopra, Manish 51119968430SChopra, Manish if (!p_tunn) 51219968430SChopra, Manish return -EINVAL; 51319968430SChopra, Manish 514464f6645SManish Chopra /* Get SPQ entry */ 515464f6645SManish Chopra memset(&init_data, 0, sizeof(init_data)); 516464f6645SManish Chopra init_data.cid = qed_spq_get_cid(p_hwfn); 517464f6645SManish Chopra init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 518464f6645SManish Chopra init_data.comp_mode = comp_mode; 519464f6645SManish Chopra init_data.p_comp_data = p_comp_data; 520464f6645SManish Chopra 521464f6645SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 522464f6645SManish Chopra COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 523464f6645SManish Chopra &init_data); 524464f6645SManish Chopra if (rc) 525464f6645SManish Chopra return rc; 526464f6645SManish Chopra 527464f6645SManish Chopra qed_tunn_set_pf_update_params(p_hwfn, p_tunn, 528464f6645SManish Chopra &p_ent->ramrod.pf_update.tunnel_config); 529464f6645SManish Chopra 530464f6645SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 531464f6645SManish Chopra if (rc) 532464f6645SManish Chopra return rc; 533464f6645SManish Chopra 5344f64675fSManish Chopra qed_set_hw_tunn_mode_port(p_hwfn, p_ptt, &p_hwfn->cdev->tunnel); 535464f6645SManish Chopra 536464f6645SManish Chopra return rc; 537464f6645SManish Chopra } 538464f6645SManish Chopra 539fe56b9e6SYuval Mintz int qed_sp_pf_stop(struct qed_hwfn *p_hwfn) 540fe56b9e6SYuval Mintz { 541fe56b9e6SYuval Mintz struct qed_spq_entry *p_ent = NULL; 54206f56b81SYuval Mintz struct qed_sp_init_data init_data; 543fe56b9e6SYuval Mintz int rc = -EINVAL; 544fe56b9e6SYuval Mintz 54506f56b81SYuval Mintz /* Get SPQ entry */ 54606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 54706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 54806f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 54906f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 550fe56b9e6SYuval Mintz 55106f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 552fe56b9e6SYuval Mintz COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON, 55306f56b81SYuval Mintz &init_data); 554fe56b9e6SYuval Mintz if (rc) 555fe56b9e6SYuval Mintz return rc; 556fe56b9e6SYuval Mintz 557fe56b9e6SYuval Mintz return qed_spq_post(p_hwfn, p_ent, NULL); 558fe56b9e6SYuval Mintz } 55903dc76caSSudarsana Reddy Kalluru 56003dc76caSSudarsana Reddy Kalluru int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn) 56103dc76caSSudarsana Reddy Kalluru { 56203dc76caSSudarsana Reddy Kalluru struct qed_spq_entry *p_ent = NULL; 56303dc76caSSudarsana Reddy Kalluru struct qed_sp_init_data init_data; 56403dc76caSSudarsana Reddy Kalluru int rc; 56503dc76caSSudarsana Reddy Kalluru 56603dc76caSSudarsana Reddy Kalluru /* Get SPQ entry */ 56703dc76caSSudarsana Reddy Kalluru memset(&init_data, 0, sizeof(init_data)); 56803dc76caSSudarsana Reddy Kalluru init_data.cid = qed_spq_get_cid(p_hwfn); 56903dc76caSSudarsana Reddy Kalluru init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 57003dc76caSSudarsana Reddy Kalluru init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 57103dc76caSSudarsana Reddy Kalluru 57203dc76caSSudarsana Reddy Kalluru rc = qed_sp_init_request(p_hwfn, &p_ent, 57303dc76caSSudarsana Reddy Kalluru COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON, 57403dc76caSSudarsana Reddy Kalluru &init_data); 57503dc76caSSudarsana Reddy Kalluru if (rc) 57603dc76caSSudarsana Reddy Kalluru return rc; 57703dc76caSSudarsana Reddy Kalluru 57803dc76caSSudarsana Reddy Kalluru return qed_spq_post(p_hwfn, p_ent, NULL); 57903dc76caSSudarsana Reddy Kalluru } 5802a351fd9SMintz, Yuval 5812a351fd9SMintz, Yuval int qed_sp_pf_update_stag(struct qed_hwfn *p_hwfn) 5822a351fd9SMintz, Yuval { 5832a351fd9SMintz, Yuval struct qed_spq_entry *p_ent = NULL; 5842a351fd9SMintz, Yuval struct qed_sp_init_data init_data; 5852a351fd9SMintz, Yuval int rc = -EINVAL; 5862a351fd9SMintz, Yuval 5872a351fd9SMintz, Yuval /* Get SPQ entry */ 5882a351fd9SMintz, Yuval memset(&init_data, 0, sizeof(init_data)); 5892a351fd9SMintz, Yuval init_data.cid = qed_spq_get_cid(p_hwfn); 5902a351fd9SMintz, Yuval init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 5912a351fd9SMintz, Yuval init_data.comp_mode = QED_SPQ_MODE_CB; 5922a351fd9SMintz, Yuval 5932a351fd9SMintz, Yuval rc = qed_sp_init_request(p_hwfn, &p_ent, 5942a351fd9SMintz, Yuval COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 5952a351fd9SMintz, Yuval &init_data); 5962a351fd9SMintz, Yuval if (rc) 5972a351fd9SMintz, Yuval return rc; 5982a351fd9SMintz, Yuval 5992a351fd9SMintz, Yuval p_ent->ramrod.pf_update.update_mf_vlan_flag = true; 6002a351fd9SMintz, Yuval p_ent->ramrod.pf_update.mf_vlan = cpu_to_le16(p_hwfn->hw_info.ovlan); 6012a351fd9SMintz, Yuval 6022a351fd9SMintz, Yuval return qed_spq_post(p_hwfn, p_ent, NULL); 6032a351fd9SMintz, Yuval } 604