1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/types.h> 33 #include <asm/byteorder.h> 34 #include <linux/bitops.h> 35 #include <linux/delay.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/errno.h> 38 #include <linux/io.h> 39 #include <linux/kernel.h> 40 #include <linux/list.h> 41 #include <linux/module.h> 42 #include <linux/mutex.h> 43 #include <linux/pci.h> 44 #include <linux/slab.h> 45 #include <linux/spinlock.h> 46 #include <linux/string.h> 47 #include <linux/if_vlan.h> 48 #include "qed.h" 49 #include "qed_cxt.h" 50 #include "qed_dcbx.h" 51 #include "qed_hsi.h" 52 #include "qed_hw.h" 53 #include "qed_init_ops.h" 54 #include "qed_int.h" 55 #include "qed_ll2.h" 56 #include "qed_mcp.h" 57 #include "qed_reg_addr.h" 58 #include <linux/qed/qed_rdma_if.h> 59 #include "qed_rdma.h" 60 #include "qed_roce.h" 61 #include "qed_sp.h" 62 63 static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid); 64 65 static int 66 qed_roce_async_event(struct qed_hwfn *p_hwfn, 67 u8 fw_event_code, 68 u16 echo, union event_ring_data *data, u8 fw_return_code) 69 { 70 struct qed_rdma_events events = p_hwfn->p_rdma_info->events; 71 72 if (fw_event_code == ROCE_ASYNC_EVENT_DESTROY_QP_DONE) { 73 u16 icid = 74 (u16)le32_to_cpu(data->rdma_data.rdma_destroy_qp_data.cid); 75 76 /* icid release in this async event can occur only if the icid 77 * was offloaded to the FW. In case it wasn't offloaded this is 78 * handled in qed_roce_sp_destroy_qp. 79 */ 80 qed_roce_free_real_icid(p_hwfn, icid); 81 } else { 82 if (fw_event_code == ROCE_ASYNC_EVENT_SRQ_EMPTY || 83 fw_event_code == ROCE_ASYNC_EVENT_SRQ_LIMIT) { 84 u16 srq_id = (u16)data->rdma_data.async_handle.lo; 85 86 events.affiliated_event(events.context, fw_event_code, 87 &srq_id); 88 } else { 89 union rdma_eqe_data rdata = data->rdma_data; 90 91 events.affiliated_event(events.context, fw_event_code, 92 (void *)&rdata.async_handle); 93 } 94 } 95 96 return 0; 97 } 98 99 void qed_roce_stop(struct qed_hwfn *p_hwfn) 100 { 101 struct qed_bmap *rcid_map = &p_hwfn->p_rdma_info->real_cid_map; 102 int wait_count = 0; 103 104 /* when destroying a_RoCE QP the control is returned to the user after 105 * the synchronous part. The asynchronous part may take a little longer. 106 * We delay for a short while if an async destroy QP is still expected. 107 * Beyond the added delay we clear the bitmap anyway. 108 */ 109 while (bitmap_weight(rcid_map->bitmap, rcid_map->max_count)) { 110 msleep(100); 111 if (wait_count++ > 20) { 112 DP_NOTICE(p_hwfn, "cid bitmap wait timed out\n"); 113 break; 114 } 115 } 116 } 117 118 static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid, 119 __le32 *dst_gid) 120 { 121 u32 i; 122 123 if (qp->roce_mode == ROCE_V2_IPV4) { 124 /* The IPv4 addresses shall be aligned to the highest word. 125 * The lower words must be zero. 126 */ 127 memset(src_gid, 0, sizeof(union qed_gid)); 128 memset(dst_gid, 0, sizeof(union qed_gid)); 129 src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr); 130 dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr); 131 } else { 132 /* GIDs and IPv6 addresses coincide in location and size */ 133 for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) { 134 src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]); 135 dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]); 136 } 137 } 138 } 139 140 static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode) 141 { 142 switch (roce_mode) { 143 case ROCE_V1: 144 return PLAIN_ROCE; 145 case ROCE_V2_IPV4: 146 return RROCE_IPV4; 147 case ROCE_V2_IPV6: 148 return RROCE_IPV6; 149 default: 150 return MAX_ROCE_FLAVOR; 151 } 152 } 153 154 static void qed_roce_free_cid_pair(struct qed_hwfn *p_hwfn, u16 cid) 155 { 156 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 157 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid); 158 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid + 1); 159 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 160 } 161 162 int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid) 163 { 164 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 165 u32 responder_icid; 166 u32 requester_icid; 167 int rc; 168 169 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 170 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 171 &responder_icid); 172 if (rc) { 173 spin_unlock_bh(&p_rdma_info->lock); 174 return rc; 175 } 176 177 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 178 &requester_icid); 179 180 spin_unlock_bh(&p_rdma_info->lock); 181 if (rc) 182 goto err; 183 184 /* the two icid's should be adjacent */ 185 if ((requester_icid - responder_icid) != 1) { 186 DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n"); 187 rc = -EINVAL; 188 goto err; 189 } 190 191 responder_icid += qed_cxt_get_proto_cid_start(p_hwfn, 192 p_rdma_info->proto); 193 requester_icid += qed_cxt_get_proto_cid_start(p_hwfn, 194 p_rdma_info->proto); 195 196 /* If these icids require a new ILT line allocate DMA-able context for 197 * an ILT page 198 */ 199 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid); 200 if (rc) 201 goto err; 202 203 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid); 204 if (rc) 205 goto err; 206 207 *cid = (u16)responder_icid; 208 return rc; 209 210 err: 211 spin_lock_bh(&p_rdma_info->lock); 212 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid); 213 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid); 214 215 spin_unlock_bh(&p_rdma_info->lock); 216 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 217 "Allocate CID - failed, rc = %d\n", rc); 218 return rc; 219 } 220 221 static void qed_roce_set_real_cid(struct qed_hwfn *p_hwfn, u32 cid) 222 { 223 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 224 qed_bmap_set_id(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, cid); 225 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 226 } 227 228 static u8 qed_roce_get_qp_tc(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 229 { 230 u8 pri, tc = 0; 231 232 if (qp->vlan_id) { 233 pri = (qp->vlan_id & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 234 tc = qed_dcbx_get_priority_tc(p_hwfn, pri); 235 } 236 237 DP_VERBOSE(p_hwfn, QED_MSG_SP, 238 "qp icid %u tc: %u (vlan priority %s)\n", 239 qp->icid, tc, qp->vlan_id ? "enabled" : "disabled"); 240 241 return tc; 242 } 243 244 static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn, 245 struct qed_rdma_qp *qp) 246 { 247 struct roce_create_qp_resp_ramrod_data *p_ramrod; 248 u16 regular_latency_queue, low_latency_queue; 249 struct qed_sp_init_data init_data; 250 enum roce_flavor roce_flavor; 251 struct qed_spq_entry *p_ent; 252 enum protocol_type proto; 253 int rc; 254 u8 tc; 255 256 if (!qp->has_resp) 257 return 0; 258 259 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 260 261 /* Allocate DMA-able memory for IRQ */ 262 qp->irq_num_pages = 1; 263 qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 264 RDMA_RING_PAGE_SIZE, 265 &qp->irq_phys_addr, GFP_KERNEL); 266 if (!qp->irq) { 267 rc = -ENOMEM; 268 DP_NOTICE(p_hwfn, 269 "qed create responder failed: cannot allocate memory (irq). rc = %d\n", 270 rc); 271 return rc; 272 } 273 274 /* Get SPQ entry */ 275 memset(&init_data, 0, sizeof(init_data)); 276 init_data.cid = qp->icid; 277 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 278 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 279 280 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP, 281 PROTOCOLID_ROCE, &init_data); 282 if (rc) 283 goto err; 284 285 p_ramrod = &p_ent->ramrod.roce_create_qp_resp; 286 287 p_ramrod->flags = 0; 288 289 roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 290 SET_FIELD(p_ramrod->flags, 291 ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 292 293 SET_FIELD(p_ramrod->flags, 294 ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 295 qp->incoming_rdma_read_en); 296 297 SET_FIELD(p_ramrod->flags, 298 ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 299 qp->incoming_rdma_write_en); 300 301 SET_FIELD(p_ramrod->flags, 302 ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN, 303 qp->incoming_atomic_en); 304 305 SET_FIELD(p_ramrod->flags, 306 ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 307 qp->e2e_flow_control_en); 308 309 SET_FIELD(p_ramrod->flags, 310 ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq); 311 312 SET_FIELD(p_ramrod->flags, 313 ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN, 314 qp->fmr_and_reserved_lkey); 315 316 SET_FIELD(p_ramrod->flags, 317 ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 318 qp->min_rnr_nak_timer); 319 320 SET_FIELD(p_ramrod->flags, 321 ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG, 322 qed_rdma_is_xrc_qp(qp)); 323 324 p_ramrod->max_ird = qp->max_rd_atomic_resp; 325 p_ramrod->traffic_class = qp->traffic_class_tos; 326 p_ramrod->hop_limit = qp->hop_limit_ttl; 327 p_ramrod->irq_num_pages = qp->irq_num_pages; 328 p_ramrod->p_key = cpu_to_le16(qp->pkey); 329 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 330 p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 331 p_ramrod->mtu = cpu_to_le16(qp->mtu); 332 p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn); 333 p_ramrod->pd = cpu_to_le16(qp->pd); 334 p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages); 335 DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr); 336 DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr); 337 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 338 p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 339 p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 340 p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 341 p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 342 p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 343 qp->rq_cq_id); 344 p_ramrod->xrc_domain = cpu_to_le16(qp->xrcd_id); 345 346 tc = qed_roce_get_qp_tc(p_hwfn, qp); 347 regular_latency_queue = qed_get_cm_pq_idx_ofld_mtc(p_hwfn, tc); 348 low_latency_queue = qed_get_cm_pq_idx_llt_mtc(p_hwfn, tc); 349 DP_VERBOSE(p_hwfn, QED_MSG_SP, 350 "qp icid %u pqs: regular_latency %u low_latency %u\n", 351 qp->icid, regular_latency_queue - CM_TX_PQ_BASE, 352 low_latency_queue - CM_TX_PQ_BASE); 353 p_ramrod->regular_latency_phy_queue = 354 cpu_to_le16(regular_latency_queue); 355 p_ramrod->low_latency_phy_queue = 356 cpu_to_le16(low_latency_queue); 357 358 p_ramrod->dpi = cpu_to_le16(qp->dpi); 359 360 qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 361 qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 362 363 p_ramrod->udp_src_port = qp->udp_src_port; 364 p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 365 p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id); 366 p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid); 367 368 p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 369 qp->stats_queue; 370 371 rc = qed_spq_post(p_hwfn, p_ent, NULL); 372 if (rc) 373 goto err; 374 375 qp->resp_offloaded = true; 376 qp->cq_prod = 0; 377 378 proto = p_hwfn->p_rdma_info->proto; 379 qed_roce_set_real_cid(p_hwfn, qp->icid - 380 qed_cxt_get_proto_cid_start(p_hwfn, proto)); 381 382 return rc; 383 384 err: 385 DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc); 386 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 387 qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 388 qp->irq, qp->irq_phys_addr); 389 390 return rc; 391 } 392 393 static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn, 394 struct qed_rdma_qp *qp) 395 { 396 struct roce_create_qp_req_ramrod_data *p_ramrod; 397 u16 regular_latency_queue, low_latency_queue; 398 struct qed_sp_init_data init_data; 399 enum roce_flavor roce_flavor; 400 struct qed_spq_entry *p_ent; 401 enum protocol_type proto; 402 int rc; 403 u8 tc; 404 405 if (!qp->has_req) 406 return 0; 407 408 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 409 410 /* Allocate DMA-able memory for ORQ */ 411 qp->orq_num_pages = 1; 412 qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 413 RDMA_RING_PAGE_SIZE, 414 &qp->orq_phys_addr, GFP_KERNEL); 415 if (!qp->orq) { 416 rc = -ENOMEM; 417 DP_NOTICE(p_hwfn, 418 "qed create requester failed: cannot allocate memory (orq). rc = %d\n", 419 rc); 420 return rc; 421 } 422 423 /* Get SPQ entry */ 424 memset(&init_data, 0, sizeof(init_data)); 425 init_data.cid = qp->icid + 1; 426 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 427 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 428 429 rc = qed_sp_init_request(p_hwfn, &p_ent, 430 ROCE_RAMROD_CREATE_QP, 431 PROTOCOLID_ROCE, &init_data); 432 if (rc) 433 goto err; 434 435 p_ramrod = &p_ent->ramrod.roce_create_qp_req; 436 437 p_ramrod->flags = 0; 438 439 roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 440 SET_FIELD(p_ramrod->flags, 441 ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 442 443 SET_FIELD(p_ramrod->flags, 444 ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN, 445 qp->fmr_and_reserved_lkey); 446 447 SET_FIELD(p_ramrod->flags, 448 ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all); 449 450 SET_FIELD(p_ramrod->flags, 451 ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 452 453 SET_FIELD(p_ramrod->flags, 454 ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 455 qp->rnr_retry_cnt); 456 457 SET_FIELD(p_ramrod->flags, 458 ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG, 459 qed_rdma_is_xrc_qp(qp)); 460 461 SET_FIELD(p_ramrod->flags2, 462 ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE, qp->edpm_mode); 463 464 p_ramrod->max_ord = qp->max_rd_atomic_req; 465 p_ramrod->traffic_class = qp->traffic_class_tos; 466 p_ramrod->hop_limit = qp->hop_limit_ttl; 467 p_ramrod->orq_num_pages = qp->orq_num_pages; 468 p_ramrod->p_key = cpu_to_le16(qp->pkey); 469 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 470 p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 471 p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 472 p_ramrod->mtu = cpu_to_le16(qp->mtu); 473 p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn); 474 p_ramrod->pd = cpu_to_le16(qp->pd); 475 p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages); 476 DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr); 477 DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr); 478 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 479 p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 480 p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 481 p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 482 p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 483 p_ramrod->cq_cid = 484 cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | qp->sq_cq_id); 485 486 tc = qed_roce_get_qp_tc(p_hwfn, qp); 487 regular_latency_queue = qed_get_cm_pq_idx_ofld_mtc(p_hwfn, tc); 488 low_latency_queue = qed_get_cm_pq_idx_llt_mtc(p_hwfn, tc); 489 DP_VERBOSE(p_hwfn, QED_MSG_SP, 490 "qp icid %u pqs: regular_latency %u low_latency %u\n", 491 qp->icid, regular_latency_queue - CM_TX_PQ_BASE, 492 low_latency_queue - CM_TX_PQ_BASE); 493 p_ramrod->regular_latency_phy_queue = 494 cpu_to_le16(regular_latency_queue); 495 p_ramrod->low_latency_phy_queue = 496 cpu_to_le16(low_latency_queue); 497 498 p_ramrod->dpi = cpu_to_le16(qp->dpi); 499 500 qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 501 qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 502 503 p_ramrod->udp_src_port = qp->udp_src_port; 504 p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 505 p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 506 qp->stats_queue; 507 508 rc = qed_spq_post(p_hwfn, p_ent, NULL); 509 if (rc) 510 goto err; 511 512 qp->req_offloaded = true; 513 proto = p_hwfn->p_rdma_info->proto; 514 qed_roce_set_real_cid(p_hwfn, 515 qp->icid + 1 - 516 qed_cxt_get_proto_cid_start(p_hwfn, proto)); 517 518 return rc; 519 520 err: 521 DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc); 522 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 523 qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 524 qp->orq, qp->orq_phys_addr); 525 return rc; 526 } 527 528 static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn, 529 struct qed_rdma_qp *qp, 530 bool move_to_err, u32 modify_flags) 531 { 532 struct roce_modify_qp_resp_ramrod_data *p_ramrod; 533 struct qed_sp_init_data init_data; 534 struct qed_spq_entry *p_ent; 535 int rc; 536 537 if (!qp->has_resp) 538 return 0; 539 540 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 541 542 if (move_to_err && !qp->resp_offloaded) 543 return 0; 544 545 /* Get SPQ entry */ 546 memset(&init_data, 0, sizeof(init_data)); 547 init_data.cid = qp->icid; 548 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 549 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 550 551 rc = qed_sp_init_request(p_hwfn, &p_ent, 552 ROCE_EVENT_MODIFY_QP, 553 PROTOCOLID_ROCE, &init_data); 554 if (rc) { 555 DP_NOTICE(p_hwfn, "rc = %d\n", rc); 556 return rc; 557 } 558 559 p_ramrod = &p_ent->ramrod.roce_modify_qp_resp; 560 561 p_ramrod->flags = 0; 562 563 SET_FIELD(p_ramrod->flags, 564 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 565 566 SET_FIELD(p_ramrod->flags, 567 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 568 qp->incoming_rdma_read_en); 569 570 SET_FIELD(p_ramrod->flags, 571 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 572 qp->incoming_rdma_write_en); 573 574 SET_FIELD(p_ramrod->flags, 575 ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN, 576 qp->incoming_atomic_en); 577 578 SET_FIELD(p_ramrod->flags, 579 ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 580 qp->e2e_flow_control_en); 581 582 SET_FIELD(p_ramrod->flags, 583 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG, 584 GET_FIELD(modify_flags, 585 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)); 586 587 SET_FIELD(p_ramrod->flags, 588 ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG, 589 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 590 591 SET_FIELD(p_ramrod->flags, 592 ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG, 593 GET_FIELD(modify_flags, 594 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 595 596 SET_FIELD(p_ramrod->flags, 597 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG, 598 GET_FIELD(modify_flags, 599 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)); 600 601 SET_FIELD(p_ramrod->flags, 602 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG, 603 GET_FIELD(modify_flags, 604 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)); 605 606 p_ramrod->fields = 0; 607 SET_FIELD(p_ramrod->fields, 608 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 609 qp->min_rnr_nak_timer); 610 611 p_ramrod->max_ird = qp->max_rd_atomic_resp; 612 p_ramrod->traffic_class = qp->traffic_class_tos; 613 p_ramrod->hop_limit = qp->hop_limit_ttl; 614 p_ramrod->p_key = cpu_to_le16(qp->pkey); 615 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 616 p_ramrod->mtu = cpu_to_le16(qp->mtu); 617 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 618 rc = qed_spq_post(p_hwfn, p_ent, NULL); 619 620 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc); 621 return rc; 622 } 623 624 static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn, 625 struct qed_rdma_qp *qp, 626 bool move_to_sqd, 627 bool move_to_err, u32 modify_flags) 628 { 629 struct roce_modify_qp_req_ramrod_data *p_ramrod; 630 struct qed_sp_init_data init_data; 631 struct qed_spq_entry *p_ent; 632 int rc; 633 634 if (!qp->has_req) 635 return 0; 636 637 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 638 639 if (move_to_err && !(qp->req_offloaded)) 640 return 0; 641 642 /* Get SPQ entry */ 643 memset(&init_data, 0, sizeof(init_data)); 644 init_data.cid = qp->icid + 1; 645 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 646 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 647 648 rc = qed_sp_init_request(p_hwfn, &p_ent, 649 ROCE_EVENT_MODIFY_QP, 650 PROTOCOLID_ROCE, &init_data); 651 if (rc) { 652 DP_NOTICE(p_hwfn, "rc = %d\n", rc); 653 return rc; 654 } 655 656 p_ramrod = &p_ent->ramrod.roce_modify_qp_req; 657 658 p_ramrod->flags = 0; 659 660 SET_FIELD(p_ramrod->flags, 661 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 662 663 SET_FIELD(p_ramrod->flags, 664 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd); 665 666 SET_FIELD(p_ramrod->flags, 667 ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY, 668 qp->sqd_async); 669 670 SET_FIELD(p_ramrod->flags, 671 ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG, 672 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 673 674 SET_FIELD(p_ramrod->flags, 675 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG, 676 GET_FIELD(modify_flags, 677 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 678 679 SET_FIELD(p_ramrod->flags, 680 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG, 681 GET_FIELD(modify_flags, 682 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)); 683 684 SET_FIELD(p_ramrod->flags, 685 ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG, 686 GET_FIELD(modify_flags, 687 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)); 688 689 SET_FIELD(p_ramrod->flags, 690 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG, 691 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)); 692 693 SET_FIELD(p_ramrod->flags, 694 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG, 695 GET_FIELD(modify_flags, 696 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)); 697 698 p_ramrod->fields = 0; 699 SET_FIELD(p_ramrod->fields, 700 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 701 702 SET_FIELD(p_ramrod->fields, 703 ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 704 qp->rnr_retry_cnt); 705 706 p_ramrod->max_ord = qp->max_rd_atomic_req; 707 p_ramrod->traffic_class = qp->traffic_class_tos; 708 p_ramrod->hop_limit = qp->hop_limit_ttl; 709 p_ramrod->p_key = cpu_to_le16(qp->pkey); 710 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 711 p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 712 p_ramrod->mtu = cpu_to_le16(qp->mtu); 713 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 714 rc = qed_spq_post(p_hwfn, p_ent, NULL); 715 716 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc); 717 return rc; 718 } 719 720 static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn, 721 struct qed_rdma_qp *qp, 722 u32 *cq_prod) 723 { 724 struct roce_destroy_qp_resp_output_params *p_ramrod_res; 725 struct roce_destroy_qp_resp_ramrod_data *p_ramrod; 726 struct qed_sp_init_data init_data; 727 struct qed_spq_entry *p_ent; 728 dma_addr_t ramrod_res_phys; 729 int rc; 730 731 if (!qp->has_resp) { 732 *cq_prod = 0; 733 return 0; 734 } 735 736 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 737 *cq_prod = qp->cq_prod; 738 739 if (!qp->resp_offloaded) { 740 /* If a responder was never offload, we need to free the cids 741 * allocated in create_qp as a FW async event will never arrive 742 */ 743 u32 cid; 744 745 cid = qp->icid - 746 qed_cxt_get_proto_cid_start(p_hwfn, 747 p_hwfn->p_rdma_info->proto); 748 qed_roce_free_cid_pair(p_hwfn, (u16)cid); 749 750 return 0; 751 } 752 753 /* Get SPQ entry */ 754 memset(&init_data, 0, sizeof(init_data)); 755 init_data.cid = qp->icid; 756 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 757 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 758 759 rc = qed_sp_init_request(p_hwfn, &p_ent, 760 ROCE_RAMROD_DESTROY_QP, 761 PROTOCOLID_ROCE, &init_data); 762 if (rc) 763 return rc; 764 765 p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp; 766 767 p_ramrod_res = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 768 sizeof(*p_ramrod_res), 769 &ramrod_res_phys, GFP_KERNEL); 770 771 if (!p_ramrod_res) { 772 rc = -ENOMEM; 773 DP_NOTICE(p_hwfn, 774 "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n", 775 rc); 776 qed_sp_destroy_request(p_hwfn, p_ent); 777 return rc; 778 } 779 780 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 781 782 rc = qed_spq_post(p_hwfn, p_ent, NULL); 783 if (rc) 784 goto err; 785 786 *cq_prod = le32_to_cpu(p_ramrod_res->cq_prod); 787 qp->cq_prod = *cq_prod; 788 789 /* Free IRQ - only if ramrod succeeded, in case FW is still using it */ 790 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 791 qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 792 qp->irq, qp->irq_phys_addr); 793 794 qp->resp_offloaded = false; 795 796 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc); 797 798 err: 799 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 800 sizeof(struct roce_destroy_qp_resp_output_params), 801 p_ramrod_res, ramrod_res_phys); 802 803 return rc; 804 } 805 806 static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn, 807 struct qed_rdma_qp *qp) 808 { 809 struct roce_destroy_qp_req_output_params *p_ramrod_res; 810 struct roce_destroy_qp_req_ramrod_data *p_ramrod; 811 struct qed_sp_init_data init_data; 812 struct qed_spq_entry *p_ent; 813 dma_addr_t ramrod_res_phys; 814 int rc = -ENOMEM; 815 816 if (!qp->has_req) 817 return 0; 818 819 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 820 821 if (!qp->req_offloaded) 822 return 0; 823 824 p_ramrod_res = (struct roce_destroy_qp_req_output_params *) 825 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 826 sizeof(*p_ramrod_res), 827 &ramrod_res_phys, GFP_KERNEL); 828 if (!p_ramrod_res) { 829 DP_NOTICE(p_hwfn, 830 "qed destroy requester failed: cannot allocate memory (ramrod)\n"); 831 return rc; 832 } 833 834 /* Get SPQ entry */ 835 memset(&init_data, 0, sizeof(init_data)); 836 init_data.cid = qp->icid + 1; 837 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 838 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 839 840 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP, 841 PROTOCOLID_ROCE, &init_data); 842 if (rc) 843 goto err; 844 845 p_ramrod = &p_ent->ramrod.roce_destroy_qp_req; 846 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 847 848 rc = qed_spq_post(p_hwfn, p_ent, NULL); 849 if (rc) 850 goto err; 851 852 853 /* Free ORQ - only if ramrod succeeded, in case FW is still using it */ 854 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 855 qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 856 qp->orq, qp->orq_phys_addr); 857 858 qp->req_offloaded = false; 859 860 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc); 861 862 err: 863 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 864 p_ramrod_res, ramrod_res_phys); 865 866 return rc; 867 } 868 869 int qed_roce_query_qp(struct qed_hwfn *p_hwfn, 870 struct qed_rdma_qp *qp, 871 struct qed_rdma_query_qp_out_params *out_params) 872 { 873 struct roce_query_qp_resp_output_params *p_resp_ramrod_res; 874 struct roce_query_qp_req_output_params *p_req_ramrod_res; 875 struct roce_query_qp_resp_ramrod_data *p_resp_ramrod; 876 struct roce_query_qp_req_ramrod_data *p_req_ramrod; 877 struct qed_sp_init_data init_data; 878 dma_addr_t resp_ramrod_res_phys; 879 dma_addr_t req_ramrod_res_phys; 880 struct qed_spq_entry *p_ent; 881 bool rq_err_state; 882 bool sq_err_state; 883 bool sq_draining; 884 int rc = -ENOMEM; 885 886 if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) { 887 /* We can't send ramrod to the fw since this qp wasn't offloaded 888 * to the fw yet 889 */ 890 out_params->draining = false; 891 out_params->rq_psn = qp->rq_psn; 892 out_params->sq_psn = qp->sq_psn; 893 out_params->state = qp->cur_state; 894 895 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n"); 896 return 0; 897 } 898 899 if (!(qp->resp_offloaded)) { 900 DP_NOTICE(p_hwfn, 901 "The responder's qp should be offloaded before requester's\n"); 902 return -EINVAL; 903 } 904 905 /* Send a query responder ramrod to FW to get RQ-PSN and state */ 906 p_resp_ramrod_res = 907 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 908 sizeof(*p_resp_ramrod_res), 909 &resp_ramrod_res_phys, GFP_KERNEL); 910 if (!p_resp_ramrod_res) { 911 DP_NOTICE(p_hwfn, 912 "qed query qp failed: cannot allocate memory (ramrod)\n"); 913 return rc; 914 } 915 916 /* Get SPQ entry */ 917 memset(&init_data, 0, sizeof(init_data)); 918 init_data.cid = qp->icid; 919 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 920 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 921 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 922 PROTOCOLID_ROCE, &init_data); 923 if (rc) 924 goto err_resp; 925 926 p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp; 927 DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys); 928 929 rc = qed_spq_post(p_hwfn, p_ent, NULL); 930 if (rc) 931 goto err_resp; 932 933 out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn); 934 rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->flags), 935 ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG); 936 937 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 938 p_resp_ramrod_res, resp_ramrod_res_phys); 939 940 if (!(qp->req_offloaded)) { 941 /* Don't send query qp for the requester */ 942 out_params->sq_psn = qp->sq_psn; 943 out_params->draining = false; 944 945 if (rq_err_state) 946 qp->cur_state = QED_ROCE_QP_STATE_ERR; 947 948 out_params->state = qp->cur_state; 949 950 return 0; 951 } 952 953 /* Send a query requester ramrod to FW to get SQ-PSN and state */ 954 p_req_ramrod_res = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 955 sizeof(*p_req_ramrod_res), 956 &req_ramrod_res_phys, 957 GFP_KERNEL); 958 if (!p_req_ramrod_res) { 959 rc = -ENOMEM; 960 DP_NOTICE(p_hwfn, 961 "qed query qp failed: cannot allocate memory (ramrod)\n"); 962 return rc; 963 } 964 965 /* Get SPQ entry */ 966 init_data.cid = qp->icid + 1; 967 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 968 PROTOCOLID_ROCE, &init_data); 969 if (rc) 970 goto err_req; 971 972 p_req_ramrod = &p_ent->ramrod.roce_query_qp_req; 973 DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys); 974 975 rc = qed_spq_post(p_hwfn, p_ent, NULL); 976 if (rc) 977 goto err_req; 978 979 out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn); 980 sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 981 ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG); 982 sq_draining = 983 GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 984 ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG); 985 986 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 987 p_req_ramrod_res, req_ramrod_res_phys); 988 989 out_params->draining = false; 990 991 if (rq_err_state || sq_err_state) 992 qp->cur_state = QED_ROCE_QP_STATE_ERR; 993 else if (sq_draining) 994 out_params->draining = true; 995 out_params->state = qp->cur_state; 996 997 return 0; 998 999 err_req: 1000 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 1001 p_req_ramrod_res, req_ramrod_res_phys); 1002 return rc; 1003 err_resp: 1004 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 1005 p_resp_ramrod_res, resp_ramrod_res_phys); 1006 return rc; 1007 } 1008 1009 int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 1010 { 1011 u32 cq_prod; 1012 int rc; 1013 1014 /* Destroys the specified QP */ 1015 if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) && 1016 (qp->cur_state != QED_ROCE_QP_STATE_ERR) && 1017 (qp->cur_state != QED_ROCE_QP_STATE_INIT)) { 1018 DP_NOTICE(p_hwfn, 1019 "QP must be in error, reset or init state before destroying it\n"); 1020 return -EINVAL; 1021 } 1022 1023 if (qp->cur_state != QED_ROCE_QP_STATE_RESET) { 1024 rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, 1025 &cq_prod); 1026 if (rc) 1027 return rc; 1028 1029 /* Send destroy requester ramrod */ 1030 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp); 1031 if (rc) 1032 return rc; 1033 } 1034 1035 return 0; 1036 } 1037 1038 int qed_roce_modify_qp(struct qed_hwfn *p_hwfn, 1039 struct qed_rdma_qp *qp, 1040 enum qed_roce_qp_state prev_state, 1041 struct qed_rdma_modify_qp_in_params *params) 1042 { 1043 int rc = 0; 1044 1045 /* Perform additional operations according to the current state and the 1046 * next state 1047 */ 1048 if (((prev_state == QED_ROCE_QP_STATE_INIT) || 1049 (prev_state == QED_ROCE_QP_STATE_RESET)) && 1050 (qp->cur_state == QED_ROCE_QP_STATE_RTR)) { 1051 /* Init->RTR or Reset->RTR */ 1052 rc = qed_roce_sp_create_responder(p_hwfn, qp); 1053 return rc; 1054 } else if ((prev_state == QED_ROCE_QP_STATE_RTR) && 1055 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1056 /* RTR-> RTS */ 1057 rc = qed_roce_sp_create_requester(p_hwfn, qp); 1058 if (rc) 1059 return rc; 1060 1061 /* Send modify responder ramrod */ 1062 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1063 params->modify_flags); 1064 return rc; 1065 } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1066 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1067 /* RTS->RTS */ 1068 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1069 params->modify_flags); 1070 if (rc) 1071 return rc; 1072 1073 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1074 params->modify_flags); 1075 return rc; 1076 } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1077 (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1078 /* RTS->SQD */ 1079 rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false, 1080 params->modify_flags); 1081 return rc; 1082 } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1083 (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1084 /* SQD->SQD */ 1085 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1086 params->modify_flags); 1087 if (rc) 1088 return rc; 1089 1090 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1091 params->modify_flags); 1092 return rc; 1093 } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1094 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1095 /* SQD->RTS */ 1096 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1097 params->modify_flags); 1098 if (rc) 1099 return rc; 1100 1101 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1102 params->modify_flags); 1103 1104 return rc; 1105 } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR) { 1106 /* ->ERR */ 1107 rc = qed_roce_sp_modify_responder(p_hwfn, qp, true, 1108 params->modify_flags); 1109 if (rc) 1110 return rc; 1111 1112 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true, 1113 params->modify_flags); 1114 return rc; 1115 } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) { 1116 /* Any state -> RESET */ 1117 u32 cq_prod; 1118 1119 /* Send destroy responder ramrod */ 1120 rc = qed_roce_sp_destroy_qp_responder(p_hwfn, 1121 qp, 1122 &cq_prod); 1123 1124 if (rc) 1125 return rc; 1126 1127 qp->cq_prod = cq_prod; 1128 1129 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp); 1130 } else { 1131 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 1132 } 1133 1134 return rc; 1135 } 1136 1137 static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid) 1138 { 1139 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 1140 u32 start_cid, cid, xcid; 1141 1142 /* an even icid belongs to a responder while an odd icid belongs to a 1143 * requester. The 'cid' received as an input can be either. We calculate 1144 * the "partner" icid and call it xcid. Only if both are free then the 1145 * "cid" map can be cleared. 1146 */ 1147 start_cid = qed_cxt_get_proto_cid_start(p_hwfn, p_rdma_info->proto); 1148 cid = icid - start_cid; 1149 xcid = cid ^ 1; 1150 1151 spin_lock_bh(&p_rdma_info->lock); 1152 1153 qed_bmap_release_id(p_hwfn, &p_rdma_info->real_cid_map, cid); 1154 if (qed_bmap_test_id(p_hwfn, &p_rdma_info->real_cid_map, xcid) == 0) { 1155 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, cid); 1156 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, xcid); 1157 } 1158 1159 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1160 } 1161 1162 void qed_roce_dpm_dcbx(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1163 { 1164 u8 val; 1165 1166 /* if any QPs are already active, we want to disable DPM, since their 1167 * context information contains information from before the latest DCBx 1168 * update. Otherwise enable it. 1169 */ 1170 val = qed_rdma_allocated_qps(p_hwfn) ? true : false; 1171 p_hwfn->dcbx_no_edpm = (u8)val; 1172 1173 qed_rdma_dpm_conf(p_hwfn, p_ptt); 1174 } 1175 1176 int qed_roce_setup(struct qed_hwfn *p_hwfn) 1177 { 1178 return qed_spq_register_async_cb(p_hwfn, PROTOCOLID_ROCE, 1179 qed_roce_async_event); 1180 } 1181 1182 int qed_roce_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1183 { 1184 u32 ll2_ethertype_en; 1185 1186 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 1187 1188 p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE; 1189 1190 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 1191 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 1192 (ll2_ethertype_en | 0x01)); 1193 1194 if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) { 1195 DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n"); 1196 return -EINVAL; 1197 } 1198 1199 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n"); 1200 return 0; 1201 } 1202