1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/types.h> 33 #include <asm/byteorder.h> 34 #include <linux/bitops.h> 35 #include <linux/delay.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/errno.h> 38 #include <linux/etherdevice.h> 39 #include <linux/if_ether.h> 40 #include <linux/if_vlan.h> 41 #include <linux/io.h> 42 #include <linux/ip.h> 43 #include <linux/ipv6.h> 44 #include <linux/kernel.h> 45 #include <linux/list.h> 46 #include <linux/module.h> 47 #include <linux/mutex.h> 48 #include <linux/pci.h> 49 #include <linux/slab.h> 50 #include <linux/spinlock.h> 51 #include <linux/string.h> 52 #include <linux/tcp.h> 53 #include <linux/bitops.h> 54 #include <linux/qed/qed_roce_if.h> 55 #include <linux/qed/qed_roce_if.h> 56 #include "qed.h" 57 #include "qed_cxt.h" 58 #include "qed_hsi.h" 59 #include "qed_hw.h" 60 #include "qed_init_ops.h" 61 #include "qed_int.h" 62 #include "qed_ll2.h" 63 #include "qed_mcp.h" 64 #include "qed_reg_addr.h" 65 #include "qed_sp.h" 66 #include "qed_roce.h" 67 #include "qed_ll2.h" 68 69 static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid); 70 71 void qed_roce_async_event(struct qed_hwfn *p_hwfn, 72 u8 fw_event_code, union rdma_eqe_data *rdma_data) 73 { 74 if (fw_event_code == ROCE_ASYNC_EVENT_DESTROY_QP_DONE) { 75 u16 icid = 76 (u16)le32_to_cpu(rdma_data->rdma_destroy_qp_data.cid); 77 78 /* icid release in this async event can occur only if the icid 79 * was offloaded to the FW. In case it wasn't offloaded this is 80 * handled in qed_roce_sp_destroy_qp. 81 */ 82 qed_roce_free_real_icid(p_hwfn, icid); 83 } else { 84 struct qed_rdma_events *events = &p_hwfn->p_rdma_info->events; 85 86 events->affiliated_event(p_hwfn->p_rdma_info->events.context, 87 fw_event_code, 88 &rdma_data->async_handle); 89 } 90 } 91 92 static int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn, 93 struct qed_bmap *bmap, u32 max_count) 94 { 95 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count); 96 97 bmap->max_count = max_count; 98 99 bmap->bitmap = kzalloc(BITS_TO_LONGS(max_count) * sizeof(long), 100 GFP_KERNEL); 101 if (!bmap->bitmap) { 102 DP_NOTICE(p_hwfn, 103 "qed bmap alloc failed: cannot allocate memory (bitmap)\n"); 104 return -ENOMEM; 105 } 106 107 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocated bitmap %p\n", 108 bmap->bitmap); 109 return 0; 110 } 111 112 static int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn, 113 struct qed_bmap *bmap, u32 *id_num) 114 { 115 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "bmap = %p\n", bmap); 116 117 *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count); 118 119 if (*id_num >= bmap->max_count) { 120 DP_NOTICE(p_hwfn, "no id available max_count=%d\n", 121 bmap->max_count); 122 return -EINVAL; 123 } 124 125 __set_bit(*id_num, bmap->bitmap); 126 127 return 0; 128 } 129 130 static void qed_bmap_set_id(struct qed_hwfn *p_hwfn, 131 struct qed_bmap *bmap, u32 id_num) 132 { 133 if (id_num >= bmap->max_count) 134 return; 135 136 __set_bit(id_num, bmap->bitmap); 137 } 138 139 static void qed_bmap_release_id(struct qed_hwfn *p_hwfn, 140 struct qed_bmap *bmap, u32 id_num) 141 { 142 bool b_acquired; 143 144 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "id_num = %08x", id_num); 145 if (id_num >= bmap->max_count) 146 return; 147 148 b_acquired = test_and_clear_bit(id_num, bmap->bitmap); 149 if (!b_acquired) { 150 DP_NOTICE(p_hwfn, "ID %d already released\n", id_num); 151 return; 152 } 153 } 154 155 static int qed_bmap_test_id(struct qed_hwfn *p_hwfn, 156 struct qed_bmap *bmap, u32 id_num) 157 { 158 if (id_num >= bmap->max_count) 159 return -1; 160 161 return test_bit(id_num, bmap->bitmap); 162 } 163 164 static u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id) 165 { 166 /* First sb id for RoCE is after all the l2 sb */ 167 return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id; 168 } 169 170 static int qed_rdma_alloc(struct qed_hwfn *p_hwfn, 171 struct qed_ptt *p_ptt, 172 struct qed_rdma_start_in_params *params) 173 { 174 struct qed_rdma_info *p_rdma_info; 175 u32 num_cons, num_tasks; 176 int rc = -ENOMEM; 177 178 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n"); 179 180 /* Allocate a struct with current pf rdma info */ 181 p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL); 182 if (!p_rdma_info) { 183 DP_NOTICE(p_hwfn, 184 "qed rdma alloc failed: cannot allocate memory (rdma info). rc = %d\n", 185 rc); 186 return rc; 187 } 188 189 p_hwfn->p_rdma_info = p_rdma_info; 190 p_rdma_info->proto = PROTOCOLID_ROCE; 191 192 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto, 193 NULL); 194 195 p_rdma_info->num_qps = num_cons / 2; 196 197 num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE); 198 199 /* Each MR uses a single task */ 200 p_rdma_info->num_mrs = num_tasks; 201 202 /* Queue zone lines are shared between RoCE and L2 in such a way that 203 * they can be used by each without obstructing the other. 204 */ 205 p_rdma_info->queue_zone_base = (u16)RESC_START(p_hwfn, QED_L2_QUEUE); 206 p_rdma_info->max_queue_zones = (u16)RESC_NUM(p_hwfn, QED_L2_QUEUE); 207 208 /* Allocate a struct with device params and fill it */ 209 p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL); 210 if (!p_rdma_info->dev) { 211 DP_NOTICE(p_hwfn, 212 "qed rdma alloc failed: cannot allocate memory (rdma info dev). rc = %d\n", 213 rc); 214 goto free_rdma_info; 215 } 216 217 /* Allocate a struct with port params and fill it */ 218 p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL); 219 if (!p_rdma_info->port) { 220 DP_NOTICE(p_hwfn, 221 "qed rdma alloc failed: cannot allocate memory (rdma info port). rc = %d\n", 222 rc); 223 goto free_rdma_dev; 224 } 225 226 /* Allocate bit map for pd's */ 227 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS); 228 if (rc) { 229 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 230 "Failed to allocate pd_map, rc = %d\n", 231 rc); 232 goto free_rdma_port; 233 } 234 235 /* Allocate DPI bitmap */ 236 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map, 237 p_hwfn->dpi_count); 238 if (rc) { 239 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 240 "Failed to allocate DPI bitmap, rc = %d\n", rc); 241 goto free_pd_map; 242 } 243 244 /* Allocate bitmap for cq's. The maximum number of CQs is bounded to 245 * twice the number of QPs. 246 */ 247 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map, 248 p_rdma_info->num_qps * 2); 249 if (rc) { 250 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 251 "Failed to allocate cq bitmap, rc = %d\n", rc); 252 goto free_dpi_map; 253 } 254 255 /* Allocate bitmap for toggle bit for cq icids 256 * We toggle the bit every time we create or resize cq for a given icid. 257 * The maximum number of CQs is bounded to twice the number of QPs. 258 */ 259 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits, 260 p_rdma_info->num_qps * 2); 261 if (rc) { 262 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 263 "Failed to allocate toogle bits, rc = %d\n", rc); 264 goto free_cq_map; 265 } 266 267 /* Allocate bitmap for itids */ 268 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map, 269 p_rdma_info->num_mrs); 270 if (rc) { 271 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 272 "Failed to allocate itids bitmaps, rc = %d\n", rc); 273 goto free_toggle_map; 274 } 275 276 /* Allocate bitmap for cids used for qps. */ 277 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons); 278 if (rc) { 279 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 280 "Failed to allocate cid bitmap, rc = %d\n", rc); 281 goto free_tid_map; 282 } 283 284 /* Allocate bitmap for cids used for responders/requesters. */ 285 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->real_cid_map, num_cons); 286 if (rc) { 287 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 288 "Failed to allocate real cid bitmap, rc = %d\n", rc); 289 goto free_cid_map; 290 } 291 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n"); 292 return 0; 293 294 free_cid_map: 295 kfree(p_rdma_info->cid_map.bitmap); 296 free_tid_map: 297 kfree(p_rdma_info->tid_map.bitmap); 298 free_toggle_map: 299 kfree(p_rdma_info->toggle_bits.bitmap); 300 free_cq_map: 301 kfree(p_rdma_info->cq_map.bitmap); 302 free_dpi_map: 303 kfree(p_rdma_info->dpi_map.bitmap); 304 free_pd_map: 305 kfree(p_rdma_info->pd_map.bitmap); 306 free_rdma_port: 307 kfree(p_rdma_info->port); 308 free_rdma_dev: 309 kfree(p_rdma_info->dev); 310 free_rdma_info: 311 kfree(p_rdma_info); 312 313 return rc; 314 } 315 316 static void qed_rdma_resc_free(struct qed_hwfn *p_hwfn) 317 { 318 struct qed_bmap *rcid_map = &p_hwfn->p_rdma_info->real_cid_map; 319 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 320 int wait_count = 0; 321 322 /* when destroying a_RoCE QP the control is returned to the user after 323 * the synchronous part. The asynchronous part may take a little longer. 324 * We delay for a short while if an async destroy QP is still expected. 325 * Beyond the added delay we clear the bitmap anyway. 326 */ 327 while (bitmap_weight(rcid_map->bitmap, rcid_map->max_count)) { 328 msleep(100); 329 if (wait_count++ > 20) { 330 DP_NOTICE(p_hwfn, "cid bitmap wait timed out\n"); 331 break; 332 } 333 } 334 335 kfree(p_rdma_info->cid_map.bitmap); 336 kfree(p_rdma_info->tid_map.bitmap); 337 kfree(p_rdma_info->toggle_bits.bitmap); 338 kfree(p_rdma_info->cq_map.bitmap); 339 kfree(p_rdma_info->dpi_map.bitmap); 340 kfree(p_rdma_info->pd_map.bitmap); 341 342 kfree(p_rdma_info->port); 343 kfree(p_rdma_info->dev); 344 345 kfree(p_rdma_info); 346 } 347 348 static void qed_rdma_free(struct qed_hwfn *p_hwfn) 349 { 350 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n"); 351 352 qed_rdma_resc_free(p_hwfn); 353 } 354 355 static void qed_rdma_get_guid(struct qed_hwfn *p_hwfn, u8 *guid) 356 { 357 guid[0] = p_hwfn->hw_info.hw_mac_addr[0] ^ 2; 358 guid[1] = p_hwfn->hw_info.hw_mac_addr[1]; 359 guid[2] = p_hwfn->hw_info.hw_mac_addr[2]; 360 guid[3] = 0xff; 361 guid[4] = 0xfe; 362 guid[5] = p_hwfn->hw_info.hw_mac_addr[3]; 363 guid[6] = p_hwfn->hw_info.hw_mac_addr[4]; 364 guid[7] = p_hwfn->hw_info.hw_mac_addr[5]; 365 } 366 367 static void qed_rdma_init_events(struct qed_hwfn *p_hwfn, 368 struct qed_rdma_start_in_params *params) 369 { 370 struct qed_rdma_events *events; 371 372 events = &p_hwfn->p_rdma_info->events; 373 374 events->unaffiliated_event = params->events->unaffiliated_event; 375 events->affiliated_event = params->events->affiliated_event; 376 events->context = params->events->context; 377 } 378 379 static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn, 380 struct qed_rdma_start_in_params *params) 381 { 382 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 383 struct qed_dev *cdev = p_hwfn->cdev; 384 u32 pci_status_control; 385 u32 num_qps; 386 387 /* Vendor specific information */ 388 dev->vendor_id = cdev->vendor_id; 389 dev->vendor_part_id = cdev->device_id; 390 dev->hw_ver = 0; 391 dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | 392 (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION); 393 394 qed_rdma_get_guid(p_hwfn, (u8 *)&dev->sys_image_guid); 395 dev->node_guid = dev->sys_image_guid; 396 397 dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE, 398 RDMA_MAX_SGE_PER_RQ_WQE); 399 400 if (cdev->rdma_max_sge) 401 dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge); 402 403 dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE; 404 405 dev->max_inline = (cdev->rdma_max_inline) ? 406 min_t(u32, cdev->rdma_max_inline, dev->max_inline) : 407 dev->max_inline; 408 409 dev->max_wqe = QED_RDMA_MAX_WQE; 410 dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ); 411 412 /* The number of QPs may be higher than QED_ROCE_MAX_QPS, because 413 * it is up-aligned to 16 and then to ILT page size within qed cxt. 414 * This is OK in terms of ILT but we don't want to configure the FW 415 * above its abilities 416 */ 417 num_qps = ROCE_MAX_QPS; 418 num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps); 419 dev->max_qp = num_qps; 420 421 /* CQs uses the same icids that QPs use hence they are limited by the 422 * number of icids. There are two icids per QP. 423 */ 424 dev->max_cq = num_qps * 2; 425 426 /* The number of mrs is smaller by 1 since the first is reserved */ 427 dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1; 428 dev->max_mr_size = QED_RDMA_MAX_MR_SIZE; 429 430 /* The maximum CQE capacity per CQ supported. 431 * max number of cqes will be in two layer pbl, 432 * 8 is the pointer size in bytes 433 * 32 is the size of cq element in bytes 434 */ 435 if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS) 436 dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT; 437 else 438 dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT; 439 440 dev->max_mw = 0; 441 dev->max_fmr = QED_RDMA_MAX_FMR; 442 dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8); 443 dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE; 444 dev->max_pkey = QED_RDMA_MAX_P_KEY; 445 446 dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 447 (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2); 448 dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 449 RDMA_REQ_RD_ATOMIC_ELM_SIZE; 450 dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc * 451 p_hwfn->p_rdma_info->num_qps; 452 dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS; 453 dev->dev_ack_delay = QED_RDMA_ACK_DELAY; 454 dev->max_pd = RDMA_MAX_PDS; 455 dev->max_ah = p_hwfn->p_rdma_info->num_qps; 456 dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE); 457 458 /* Set capablities */ 459 dev->dev_caps = 0; 460 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1); 461 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1); 462 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1); 463 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1); 464 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1); 465 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1); 466 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1); 467 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1); 468 469 /* Check atomic operations support in PCI configuration space. */ 470 pci_read_config_dword(cdev->pdev, 471 cdev->pdev->pcie_cap + PCI_EXP_DEVCTL2, 472 &pci_status_control); 473 474 if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN) 475 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1); 476 } 477 478 static void qed_rdma_init_port(struct qed_hwfn *p_hwfn) 479 { 480 struct qed_rdma_port *port = p_hwfn->p_rdma_info->port; 481 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 482 483 port->port_state = p_hwfn->mcp_info->link_output.link_up ? 484 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN; 485 486 port->max_msg_size = min_t(u64, 487 (dev->max_mr_mw_fmr_size * 488 p_hwfn->cdev->rdma_max_sge), 489 BIT(31)); 490 491 port->pkey_bad_counter = 0; 492 } 493 494 static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 495 { 496 u32 ll2_ethertype_en; 497 498 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n"); 499 p_hwfn->b_rdma_enabled_in_prs = false; 500 501 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 502 503 p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE; 504 505 /* We delay writing to this reg until first cid is allocated. See 506 * qed_cxt_dynamic_ilt_alloc function for more details 507 */ 508 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 509 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 510 (ll2_ethertype_en | 0x01)); 511 512 if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) { 513 DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n"); 514 return -EINVAL; 515 } 516 517 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n"); 518 return 0; 519 } 520 521 static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn, 522 struct qed_rdma_start_in_params *params, 523 struct qed_ptt *p_ptt) 524 { 525 struct rdma_init_func_ramrod_data *p_ramrod; 526 struct qed_rdma_cnq_params *p_cnq_pbl_list; 527 struct rdma_init_func_hdr *p_params_header; 528 struct rdma_cnq_params *p_cnq_params; 529 struct qed_sp_init_data init_data; 530 struct qed_spq_entry *p_ent; 531 u32 cnq_id, sb_id; 532 int rc; 533 534 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n"); 535 536 /* Save the number of cnqs for the function close ramrod */ 537 p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq; 538 539 /* Get SPQ entry */ 540 memset(&init_data, 0, sizeof(init_data)); 541 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 542 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 543 544 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT, 545 p_hwfn->p_rdma_info->proto, &init_data); 546 if (rc) 547 return rc; 548 549 p_ramrod = &p_ent->ramrod.roce_init_func.rdma; 550 551 p_params_header = &p_ramrod->params_header; 552 p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn, 553 QED_RDMA_CNQ_RAM); 554 p_params_header->num_cnqs = params->desired_cnq; 555 556 if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS) 557 p_params_header->cq_ring_mode = 1; 558 else 559 p_params_header->cq_ring_mode = 0; 560 561 for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) { 562 sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id); 563 p_cnq_params = &p_ramrod->cnq_params[cnq_id]; 564 p_cnq_pbl_list = ¶ms->cnq_pbl_list[cnq_id]; 565 p_cnq_params->sb_num = 566 cpu_to_le16(p_hwfn->sbs_info[sb_id]->igu_sb_id); 567 568 p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi; 569 p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages; 570 571 DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr, 572 p_cnq_pbl_list->pbl_ptr); 573 574 /* we assume here that cnq_id and qz_offset are the same */ 575 p_cnq_params->queue_zone_num = 576 cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base + 577 cnq_id); 578 } 579 580 return qed_spq_post(p_hwfn, p_ent, NULL); 581 } 582 583 static int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid) 584 { 585 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 586 int rc; 587 588 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n"); 589 590 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 591 rc = qed_rdma_bmap_alloc_id(p_hwfn, 592 &p_hwfn->p_rdma_info->tid_map, itid); 593 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 594 if (rc) 595 goto out; 596 597 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid); 598 out: 599 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc); 600 return rc; 601 } 602 603 static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn) 604 { 605 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 606 607 /* The first DPI is reserved for the Kernel */ 608 __set_bit(0, p_hwfn->p_rdma_info->dpi_map.bitmap); 609 610 /* Tid 0 will be used as the key for "reserved MR". 611 * The driver should allocate memory for it so it can be loaded but no 612 * ramrod should be passed on it. 613 */ 614 qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey); 615 if (dev->reserved_lkey != RDMA_RESERVED_LKEY) { 616 DP_NOTICE(p_hwfn, 617 "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n"); 618 return -EINVAL; 619 } 620 621 return 0; 622 } 623 624 static int qed_rdma_setup(struct qed_hwfn *p_hwfn, 625 struct qed_ptt *p_ptt, 626 struct qed_rdma_start_in_params *params) 627 { 628 int rc; 629 630 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n"); 631 632 spin_lock_init(&p_hwfn->p_rdma_info->lock); 633 634 qed_rdma_init_devinfo(p_hwfn, params); 635 qed_rdma_init_port(p_hwfn); 636 qed_rdma_init_events(p_hwfn, params); 637 638 rc = qed_rdma_reserve_lkey(p_hwfn); 639 if (rc) 640 return rc; 641 642 rc = qed_rdma_init_hw(p_hwfn, p_ptt); 643 if (rc) 644 return rc; 645 646 return qed_rdma_start_fw(p_hwfn, params, p_ptt); 647 } 648 649 static int qed_rdma_stop(void *rdma_cxt) 650 { 651 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 652 struct rdma_close_func_ramrod_data *p_ramrod; 653 struct qed_sp_init_data init_data; 654 struct qed_spq_entry *p_ent; 655 struct qed_ptt *p_ptt; 656 u32 ll2_ethertype_en; 657 int rc = -EBUSY; 658 659 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n"); 660 661 p_ptt = qed_ptt_acquire(p_hwfn); 662 if (!p_ptt) { 663 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n"); 664 return rc; 665 } 666 667 /* Disable RoCE search */ 668 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0); 669 p_hwfn->b_rdma_enabled_in_prs = false; 670 671 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 672 673 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 674 675 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 676 (ll2_ethertype_en & 0xFFFE)); 677 678 qed_ptt_release(p_hwfn, p_ptt); 679 680 /* Get SPQ entry */ 681 memset(&init_data, 0, sizeof(init_data)); 682 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 683 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 684 685 /* Stop RoCE */ 686 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE, 687 p_hwfn->p_rdma_info->proto, &init_data); 688 if (rc) 689 goto out; 690 691 p_ramrod = &p_ent->ramrod.rdma_close_func; 692 693 p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs; 694 p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM); 695 696 rc = qed_spq_post(p_hwfn, p_ent, NULL); 697 698 out: 699 qed_rdma_free(p_hwfn); 700 701 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc); 702 return rc; 703 } 704 705 static int qed_rdma_add_user(void *rdma_cxt, 706 struct qed_rdma_add_user_out_params *out_params) 707 { 708 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 709 u32 dpi_start_offset; 710 u32 returned_id = 0; 711 int rc; 712 713 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n"); 714 715 /* Allocate DPI */ 716 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 717 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 718 &returned_id); 719 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 720 721 out_params->dpi = (u16)returned_id; 722 723 /* Calculate the corresponding DPI address */ 724 dpi_start_offset = p_hwfn->dpi_start_offset; 725 726 out_params->dpi_addr = (u64)((u8 __iomem *)p_hwfn->doorbells + 727 dpi_start_offset + 728 ((out_params->dpi) * p_hwfn->dpi_size)); 729 730 out_params->dpi_phys_addr = p_hwfn->cdev->db_phys_addr + 731 dpi_start_offset + 732 ((out_params->dpi) * p_hwfn->dpi_size); 733 734 out_params->dpi_size = p_hwfn->dpi_size; 735 736 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc); 737 return rc; 738 } 739 740 static struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt) 741 { 742 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 743 struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port; 744 745 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n"); 746 747 /* Link may have changed */ 748 p_port->port_state = p_hwfn->mcp_info->link_output.link_up ? 749 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN; 750 751 p_port->link_speed = p_hwfn->mcp_info->link_output.speed; 752 753 return p_port; 754 } 755 756 static struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt) 757 { 758 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 759 760 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n"); 761 762 /* Return struct with device parameters */ 763 return p_hwfn->p_rdma_info->dev; 764 } 765 766 static void qed_rdma_free_tid(void *rdma_cxt, u32 itid) 767 { 768 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 769 770 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 771 772 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 773 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->tid_map, itid); 774 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 775 } 776 777 static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod) 778 { 779 struct qed_hwfn *p_hwfn; 780 u16 qz_num; 781 u32 addr; 782 783 p_hwfn = (struct qed_hwfn *)rdma_cxt; 784 785 if (qz_offset > p_hwfn->p_rdma_info->max_queue_zones) { 786 DP_NOTICE(p_hwfn, 787 "queue zone offset %d is too large (max is %d)\n", 788 qz_offset, p_hwfn->p_rdma_info->max_queue_zones); 789 return; 790 } 791 792 qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset; 793 addr = GTT_BAR0_MAP_REG_USDM_RAM + 794 USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num); 795 796 REG_WR16(p_hwfn, addr, prod); 797 798 /* keep prod updates ordered */ 799 wmb(); 800 } 801 802 static int qed_fill_rdma_dev_info(struct qed_dev *cdev, 803 struct qed_dev_rdma_info *info) 804 { 805 memset(info, 0, sizeof(*info)); 806 807 info->rdma_type = QED_RDMA_TYPE_ROCE; 808 809 qed_fill_dev_info(cdev, &info->common); 810 811 return 0; 812 } 813 814 static int qed_rdma_get_sb_start(struct qed_dev *cdev) 815 { 816 int feat_num; 817 818 if (cdev->num_hwfns > 1) 819 feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE); 820 else 821 feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE) * 822 cdev->num_hwfns; 823 824 return feat_num; 825 } 826 827 static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev) 828 { 829 int n_cnq = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_RDMA_CNQ); 830 int n_msix = cdev->int_params.rdma_msix_cnt; 831 832 return min_t(int, n_cnq, n_msix); 833 } 834 835 static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt) 836 { 837 int limit = 0; 838 839 /* Mark the fastpath as free/used */ 840 cdev->int_params.fp_initialized = cnt ? true : false; 841 842 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) { 843 DP_ERR(cdev, 844 "qed roce supports only MSI-X interrupts (detected %d).\n", 845 cdev->int_params.out.int_mode); 846 return -EINVAL; 847 } else if (cdev->int_params.fp_msix_cnt) { 848 limit = cdev->int_params.rdma_msix_cnt; 849 } 850 851 if (!limit) 852 return -ENOMEM; 853 854 return min_t(int, cnt, limit); 855 } 856 857 static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info) 858 { 859 memset(info, 0, sizeof(*info)); 860 861 if (!cdev->int_params.fp_initialized) { 862 DP_INFO(cdev, 863 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 864 return -EINVAL; 865 } 866 867 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 868 int msix_base = cdev->int_params.rdma_msix_base; 869 870 info->msix_cnt = cdev->int_params.rdma_msix_cnt; 871 info->msix = &cdev->int_params.msix_table[msix_base]; 872 873 DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n", 874 info->msix_cnt, msix_base); 875 } 876 877 return 0; 878 } 879 880 static int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd) 881 { 882 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 883 u32 returned_id; 884 int rc; 885 886 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n"); 887 888 /* Allocates an unused protection domain */ 889 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 890 rc = qed_rdma_bmap_alloc_id(p_hwfn, 891 &p_hwfn->p_rdma_info->pd_map, &returned_id); 892 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 893 894 *pd = (u16)returned_id; 895 896 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc); 897 return rc; 898 } 899 900 static void qed_rdma_free_pd(void *rdma_cxt, u16 pd) 901 { 902 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 903 904 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd); 905 906 /* Returns a previously allocated protection domain for reuse */ 907 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 908 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd); 909 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 910 } 911 912 static enum qed_rdma_toggle_bit 913 qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid) 914 { 915 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 916 enum qed_rdma_toggle_bit toggle_bit; 917 u32 bmap_id; 918 919 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid); 920 921 /* the function toggle the bit that is related to a given icid 922 * and returns the new toggle bit's value 923 */ 924 bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto); 925 926 spin_lock_bh(&p_info->lock); 927 toggle_bit = !test_and_change_bit(bmap_id, 928 p_info->toggle_bits.bitmap); 929 spin_unlock_bh(&p_info->lock); 930 931 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n", 932 toggle_bit); 933 934 return toggle_bit; 935 } 936 937 static int qed_rdma_create_cq(void *rdma_cxt, 938 struct qed_rdma_create_cq_in_params *params, 939 u16 *icid) 940 { 941 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 942 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 943 struct rdma_create_cq_ramrod_data *p_ramrod; 944 enum qed_rdma_toggle_bit toggle_bit; 945 struct qed_sp_init_data init_data; 946 struct qed_spq_entry *p_ent; 947 u32 returned_id, start_cid; 948 int rc; 949 950 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n", 951 params->cq_handle_hi, params->cq_handle_lo); 952 953 /* Allocate icid */ 954 spin_lock_bh(&p_info->lock); 955 rc = qed_rdma_bmap_alloc_id(p_hwfn, 956 &p_info->cq_map, &returned_id); 957 spin_unlock_bh(&p_info->lock); 958 959 if (rc) { 960 DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc); 961 return rc; 962 } 963 964 start_cid = qed_cxt_get_proto_cid_start(p_hwfn, 965 p_info->proto); 966 *icid = returned_id + start_cid; 967 968 /* Check if icid requires a page allocation */ 969 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid); 970 if (rc) 971 goto err; 972 973 /* Get SPQ entry */ 974 memset(&init_data, 0, sizeof(init_data)); 975 init_data.cid = *icid; 976 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 977 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 978 979 /* Send create CQ ramrod */ 980 rc = qed_sp_init_request(p_hwfn, &p_ent, 981 RDMA_RAMROD_CREATE_CQ, 982 p_info->proto, &init_data); 983 if (rc) 984 goto err; 985 986 p_ramrod = &p_ent->ramrod.rdma_create_cq; 987 988 p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi); 989 p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo); 990 p_ramrod->dpi = cpu_to_le16(params->dpi); 991 p_ramrod->is_two_level_pbl = params->pbl_two_level; 992 p_ramrod->max_cqes = cpu_to_le32(params->cq_size); 993 DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr); 994 p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages); 995 p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) + 996 params->cnq_id; 997 p_ramrod->int_timeout = params->int_timeout; 998 999 /* toggle the bit for every resize or create cq for a given icid */ 1000 toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 1001 1002 p_ramrod->toggle_bit = toggle_bit; 1003 1004 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1005 if (rc) { 1006 /* restore toggle bit */ 1007 qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 1008 goto err; 1009 } 1010 1011 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc); 1012 return rc; 1013 1014 err: 1015 /* release allocated icid */ 1016 spin_lock_bh(&p_info->lock); 1017 qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id); 1018 spin_unlock_bh(&p_info->lock); 1019 DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc); 1020 1021 return rc; 1022 } 1023 1024 static int 1025 qed_rdma_destroy_cq(void *rdma_cxt, 1026 struct qed_rdma_destroy_cq_in_params *in_params, 1027 struct qed_rdma_destroy_cq_out_params *out_params) 1028 { 1029 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1030 struct rdma_destroy_cq_output_params *p_ramrod_res; 1031 struct rdma_destroy_cq_ramrod_data *p_ramrod; 1032 struct qed_sp_init_data init_data; 1033 struct qed_spq_entry *p_ent; 1034 dma_addr_t ramrod_res_phys; 1035 int rc = -ENOMEM; 1036 1037 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid); 1038 1039 p_ramrod_res = 1040 (struct rdma_destroy_cq_output_params *) 1041 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1042 sizeof(struct rdma_destroy_cq_output_params), 1043 &ramrod_res_phys, GFP_KERNEL); 1044 if (!p_ramrod_res) { 1045 DP_NOTICE(p_hwfn, 1046 "qed destroy cq failed: cannot allocate memory (ramrod)\n"); 1047 return rc; 1048 } 1049 1050 /* Get SPQ entry */ 1051 memset(&init_data, 0, sizeof(init_data)); 1052 init_data.cid = in_params->icid; 1053 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1054 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1055 1056 /* Send destroy CQ ramrod */ 1057 rc = qed_sp_init_request(p_hwfn, &p_ent, 1058 RDMA_RAMROD_DESTROY_CQ, 1059 p_hwfn->p_rdma_info->proto, &init_data); 1060 if (rc) 1061 goto err; 1062 1063 p_ramrod = &p_ent->ramrod.rdma_destroy_cq; 1064 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1065 1066 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1067 if (rc) 1068 goto err; 1069 1070 out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num); 1071 1072 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1073 sizeof(struct rdma_destroy_cq_output_params), 1074 p_ramrod_res, ramrod_res_phys); 1075 1076 /* Free icid */ 1077 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1078 1079 qed_bmap_release_id(p_hwfn, 1080 &p_hwfn->p_rdma_info->cq_map, 1081 (in_params->icid - 1082 qed_cxt_get_proto_cid_start(p_hwfn, 1083 p_hwfn-> 1084 p_rdma_info->proto))); 1085 1086 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1087 1088 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc); 1089 return rc; 1090 1091 err: dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1092 sizeof(struct rdma_destroy_cq_output_params), 1093 p_ramrod_res, ramrod_res_phys); 1094 1095 return rc; 1096 } 1097 1098 static void qed_rdma_set_fw_mac(u16 *p_fw_mac, u8 *p_qed_mac) 1099 { 1100 p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]); 1101 p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]); 1102 p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]); 1103 } 1104 1105 static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid, 1106 __le32 *dst_gid) 1107 { 1108 u32 i; 1109 1110 if (qp->roce_mode == ROCE_V2_IPV4) { 1111 /* The IPv4 addresses shall be aligned to the highest word. 1112 * The lower words must be zero. 1113 */ 1114 memset(src_gid, 0, sizeof(union qed_gid)); 1115 memset(dst_gid, 0, sizeof(union qed_gid)); 1116 src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr); 1117 dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr); 1118 } else { 1119 /* GIDs and IPv6 addresses coincide in location and size */ 1120 for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) { 1121 src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]); 1122 dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]); 1123 } 1124 } 1125 } 1126 1127 static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode) 1128 { 1129 enum roce_flavor flavor; 1130 1131 switch (roce_mode) { 1132 case ROCE_V1: 1133 flavor = PLAIN_ROCE; 1134 break; 1135 case ROCE_V2_IPV4: 1136 flavor = RROCE_IPV4; 1137 break; 1138 case ROCE_V2_IPV6: 1139 flavor = ROCE_V2_IPV6; 1140 break; 1141 default: 1142 flavor = MAX_ROCE_MODE; 1143 break; 1144 } 1145 return flavor; 1146 } 1147 1148 void qed_roce_free_cid_pair(struct qed_hwfn *p_hwfn, u16 cid) 1149 { 1150 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1151 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid); 1152 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid + 1); 1153 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1154 } 1155 1156 static int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid) 1157 { 1158 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 1159 u32 responder_icid; 1160 u32 requester_icid; 1161 int rc; 1162 1163 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1164 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 1165 &responder_icid); 1166 if (rc) { 1167 spin_unlock_bh(&p_rdma_info->lock); 1168 return rc; 1169 } 1170 1171 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 1172 &requester_icid); 1173 1174 spin_unlock_bh(&p_rdma_info->lock); 1175 if (rc) 1176 goto err; 1177 1178 /* the two icid's should be adjacent */ 1179 if ((requester_icid - responder_icid) != 1) { 1180 DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n"); 1181 rc = -EINVAL; 1182 goto err; 1183 } 1184 1185 responder_icid += qed_cxt_get_proto_cid_start(p_hwfn, 1186 p_rdma_info->proto); 1187 requester_icid += qed_cxt_get_proto_cid_start(p_hwfn, 1188 p_rdma_info->proto); 1189 1190 /* If these icids require a new ILT line allocate DMA-able context for 1191 * an ILT page 1192 */ 1193 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid); 1194 if (rc) 1195 goto err; 1196 1197 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid); 1198 if (rc) 1199 goto err; 1200 1201 *cid = (u16)responder_icid; 1202 return rc; 1203 1204 err: 1205 spin_lock_bh(&p_rdma_info->lock); 1206 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid); 1207 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid); 1208 1209 spin_unlock_bh(&p_rdma_info->lock); 1210 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1211 "Allocate CID - failed, rc = %d\n", rc); 1212 return rc; 1213 } 1214 1215 static void qed_roce_set_real_cid(struct qed_hwfn *p_hwfn, u32 cid) 1216 { 1217 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1218 qed_bmap_set_id(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, cid); 1219 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1220 } 1221 1222 static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn, 1223 struct qed_rdma_qp *qp) 1224 { 1225 struct roce_create_qp_resp_ramrod_data *p_ramrod; 1226 struct qed_sp_init_data init_data; 1227 enum roce_flavor roce_flavor; 1228 struct qed_spq_entry *p_ent; 1229 u16 regular_latency_queue; 1230 enum protocol_type proto; 1231 int rc; 1232 1233 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1234 1235 /* Allocate DMA-able memory for IRQ */ 1236 qp->irq_num_pages = 1; 1237 qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1238 RDMA_RING_PAGE_SIZE, 1239 &qp->irq_phys_addr, GFP_KERNEL); 1240 if (!qp->irq) { 1241 rc = -ENOMEM; 1242 DP_NOTICE(p_hwfn, 1243 "qed create responder failed: cannot allocate memory (irq). rc = %d\n", 1244 rc); 1245 return rc; 1246 } 1247 1248 /* Get SPQ entry */ 1249 memset(&init_data, 0, sizeof(init_data)); 1250 init_data.cid = qp->icid; 1251 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1252 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1253 1254 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP, 1255 PROTOCOLID_ROCE, &init_data); 1256 if (rc) 1257 goto err; 1258 1259 p_ramrod = &p_ent->ramrod.roce_create_qp_resp; 1260 1261 p_ramrod->flags = 0; 1262 1263 roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 1264 SET_FIELD(p_ramrod->flags, 1265 ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 1266 1267 SET_FIELD(p_ramrod->flags, 1268 ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 1269 qp->incoming_rdma_read_en); 1270 1271 SET_FIELD(p_ramrod->flags, 1272 ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 1273 qp->incoming_rdma_write_en); 1274 1275 SET_FIELD(p_ramrod->flags, 1276 ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN, 1277 qp->incoming_atomic_en); 1278 1279 SET_FIELD(p_ramrod->flags, 1280 ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 1281 qp->e2e_flow_control_en); 1282 1283 SET_FIELD(p_ramrod->flags, 1284 ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq); 1285 1286 SET_FIELD(p_ramrod->flags, 1287 ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN, 1288 qp->fmr_and_reserved_lkey); 1289 1290 SET_FIELD(p_ramrod->flags, 1291 ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 1292 qp->min_rnr_nak_timer); 1293 1294 p_ramrod->max_ird = qp->max_rd_atomic_resp; 1295 p_ramrod->traffic_class = qp->traffic_class_tos; 1296 p_ramrod->hop_limit = qp->hop_limit_ttl; 1297 p_ramrod->irq_num_pages = qp->irq_num_pages; 1298 p_ramrod->p_key = cpu_to_le16(qp->pkey); 1299 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1300 p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 1301 p_ramrod->mtu = cpu_to_le16(qp->mtu); 1302 p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn); 1303 p_ramrod->pd = cpu_to_le16(qp->pd); 1304 p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages); 1305 DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr); 1306 DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr); 1307 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1308 p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 1309 p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 1310 p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 1311 p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 1312 p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 1313 qp->rq_cq_id); 1314 1315 regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 1316 1317 p_ramrod->regular_latency_phy_queue = 1318 cpu_to_le16(regular_latency_queue); 1319 p_ramrod->low_latency_phy_queue = 1320 cpu_to_le16(regular_latency_queue); 1321 1322 p_ramrod->dpi = cpu_to_le16(qp->dpi); 1323 1324 qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 1325 qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 1326 1327 p_ramrod->udp_src_port = qp->udp_src_port; 1328 p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 1329 p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id); 1330 p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid); 1331 1332 p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 1333 qp->stats_queue; 1334 1335 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1336 1337 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1338 "rc = %d regular physical queue = 0x%x\n", rc, 1339 regular_latency_queue); 1340 1341 if (rc) 1342 goto err; 1343 1344 qp->resp_offloaded = true; 1345 qp->cq_prod = 0; 1346 1347 proto = p_hwfn->p_rdma_info->proto; 1348 qed_roce_set_real_cid(p_hwfn, qp->icid - 1349 qed_cxt_get_proto_cid_start(p_hwfn, proto)); 1350 1351 return rc; 1352 1353 err: 1354 DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc); 1355 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1356 qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 1357 qp->irq, qp->irq_phys_addr); 1358 1359 return rc; 1360 } 1361 1362 static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn, 1363 struct qed_rdma_qp *qp) 1364 { 1365 struct roce_create_qp_req_ramrod_data *p_ramrod; 1366 struct qed_sp_init_data init_data; 1367 enum roce_flavor roce_flavor; 1368 struct qed_spq_entry *p_ent; 1369 u16 regular_latency_queue; 1370 enum protocol_type proto; 1371 int rc; 1372 1373 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1374 1375 /* Allocate DMA-able memory for ORQ */ 1376 qp->orq_num_pages = 1; 1377 qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1378 RDMA_RING_PAGE_SIZE, 1379 &qp->orq_phys_addr, GFP_KERNEL); 1380 if (!qp->orq) { 1381 rc = -ENOMEM; 1382 DP_NOTICE(p_hwfn, 1383 "qed create requester failed: cannot allocate memory (orq). rc = %d\n", 1384 rc); 1385 return rc; 1386 } 1387 1388 /* Get SPQ entry */ 1389 memset(&init_data, 0, sizeof(init_data)); 1390 init_data.cid = qp->icid + 1; 1391 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1392 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1393 1394 rc = qed_sp_init_request(p_hwfn, &p_ent, 1395 ROCE_RAMROD_CREATE_QP, 1396 PROTOCOLID_ROCE, &init_data); 1397 if (rc) 1398 goto err; 1399 1400 p_ramrod = &p_ent->ramrod.roce_create_qp_req; 1401 1402 p_ramrod->flags = 0; 1403 1404 roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 1405 SET_FIELD(p_ramrod->flags, 1406 ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 1407 1408 SET_FIELD(p_ramrod->flags, 1409 ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN, 1410 qp->fmr_and_reserved_lkey); 1411 1412 SET_FIELD(p_ramrod->flags, 1413 ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all); 1414 1415 SET_FIELD(p_ramrod->flags, 1416 ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 1417 1418 SET_FIELD(p_ramrod->flags, 1419 ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 1420 qp->rnr_retry_cnt); 1421 1422 p_ramrod->max_ord = qp->max_rd_atomic_req; 1423 p_ramrod->traffic_class = qp->traffic_class_tos; 1424 p_ramrod->hop_limit = qp->hop_limit_ttl; 1425 p_ramrod->orq_num_pages = qp->orq_num_pages; 1426 p_ramrod->p_key = cpu_to_le16(qp->pkey); 1427 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1428 p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 1429 p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 1430 p_ramrod->mtu = cpu_to_le16(qp->mtu); 1431 p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn); 1432 p_ramrod->pd = cpu_to_le16(qp->pd); 1433 p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages); 1434 DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr); 1435 DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr); 1436 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1437 p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 1438 p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 1439 p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 1440 p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 1441 p_ramrod->cq_cid = 1442 cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | qp->sq_cq_id); 1443 1444 regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 1445 1446 p_ramrod->regular_latency_phy_queue = 1447 cpu_to_le16(regular_latency_queue); 1448 p_ramrod->low_latency_phy_queue = 1449 cpu_to_le16(regular_latency_queue); 1450 1451 p_ramrod->dpi = cpu_to_le16(qp->dpi); 1452 1453 qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 1454 qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 1455 1456 p_ramrod->udp_src_port = qp->udp_src_port; 1457 p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 1458 p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 1459 qp->stats_queue; 1460 1461 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1462 1463 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1464 1465 if (rc) 1466 goto err; 1467 1468 qp->req_offloaded = true; 1469 proto = p_hwfn->p_rdma_info->proto; 1470 qed_roce_set_real_cid(p_hwfn, 1471 qp->icid + 1 - 1472 qed_cxt_get_proto_cid_start(p_hwfn, proto)); 1473 1474 return rc; 1475 1476 err: 1477 DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc); 1478 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1479 qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 1480 qp->orq, qp->orq_phys_addr); 1481 return rc; 1482 } 1483 1484 static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn, 1485 struct qed_rdma_qp *qp, 1486 bool move_to_err, u32 modify_flags) 1487 { 1488 struct roce_modify_qp_resp_ramrod_data *p_ramrod; 1489 struct qed_sp_init_data init_data; 1490 struct qed_spq_entry *p_ent; 1491 int rc; 1492 1493 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1494 1495 if (move_to_err && !qp->resp_offloaded) 1496 return 0; 1497 1498 /* Get SPQ entry */ 1499 memset(&init_data, 0, sizeof(init_data)); 1500 init_data.cid = qp->icid; 1501 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1502 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1503 1504 rc = qed_sp_init_request(p_hwfn, &p_ent, 1505 ROCE_EVENT_MODIFY_QP, 1506 PROTOCOLID_ROCE, &init_data); 1507 if (rc) { 1508 DP_NOTICE(p_hwfn, "rc = %d\n", rc); 1509 return rc; 1510 } 1511 1512 p_ramrod = &p_ent->ramrod.roce_modify_qp_resp; 1513 1514 p_ramrod->flags = 0; 1515 1516 SET_FIELD(p_ramrod->flags, 1517 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 1518 1519 SET_FIELD(p_ramrod->flags, 1520 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 1521 qp->incoming_rdma_read_en); 1522 1523 SET_FIELD(p_ramrod->flags, 1524 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 1525 qp->incoming_rdma_write_en); 1526 1527 SET_FIELD(p_ramrod->flags, 1528 ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN, 1529 qp->incoming_atomic_en); 1530 1531 SET_FIELD(p_ramrod->flags, 1532 ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 1533 qp->e2e_flow_control_en); 1534 1535 SET_FIELD(p_ramrod->flags, 1536 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG, 1537 GET_FIELD(modify_flags, 1538 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)); 1539 1540 SET_FIELD(p_ramrod->flags, 1541 ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG, 1542 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 1543 1544 SET_FIELD(p_ramrod->flags, 1545 ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG, 1546 GET_FIELD(modify_flags, 1547 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 1548 1549 SET_FIELD(p_ramrod->flags, 1550 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG, 1551 GET_FIELD(modify_flags, 1552 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)); 1553 1554 SET_FIELD(p_ramrod->flags, 1555 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG, 1556 GET_FIELD(modify_flags, 1557 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)); 1558 1559 p_ramrod->fields = 0; 1560 SET_FIELD(p_ramrod->fields, 1561 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 1562 qp->min_rnr_nak_timer); 1563 1564 p_ramrod->max_ird = qp->max_rd_atomic_resp; 1565 p_ramrod->traffic_class = qp->traffic_class_tos; 1566 p_ramrod->hop_limit = qp->hop_limit_ttl; 1567 p_ramrod->p_key = cpu_to_le16(qp->pkey); 1568 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1569 p_ramrod->mtu = cpu_to_le16(qp->mtu); 1570 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1571 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1572 1573 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc); 1574 return rc; 1575 } 1576 1577 static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn, 1578 struct qed_rdma_qp *qp, 1579 bool move_to_sqd, 1580 bool move_to_err, u32 modify_flags) 1581 { 1582 struct roce_modify_qp_req_ramrod_data *p_ramrod; 1583 struct qed_sp_init_data init_data; 1584 struct qed_spq_entry *p_ent; 1585 int rc; 1586 1587 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1588 1589 if (move_to_err && !(qp->req_offloaded)) 1590 return 0; 1591 1592 /* Get SPQ entry */ 1593 memset(&init_data, 0, sizeof(init_data)); 1594 init_data.cid = qp->icid + 1; 1595 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1596 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1597 1598 rc = qed_sp_init_request(p_hwfn, &p_ent, 1599 ROCE_EVENT_MODIFY_QP, 1600 PROTOCOLID_ROCE, &init_data); 1601 if (rc) { 1602 DP_NOTICE(p_hwfn, "rc = %d\n", rc); 1603 return rc; 1604 } 1605 1606 p_ramrod = &p_ent->ramrod.roce_modify_qp_req; 1607 1608 p_ramrod->flags = 0; 1609 1610 SET_FIELD(p_ramrod->flags, 1611 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 1612 1613 SET_FIELD(p_ramrod->flags, 1614 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd); 1615 1616 SET_FIELD(p_ramrod->flags, 1617 ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY, 1618 qp->sqd_async); 1619 1620 SET_FIELD(p_ramrod->flags, 1621 ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG, 1622 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 1623 1624 SET_FIELD(p_ramrod->flags, 1625 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG, 1626 GET_FIELD(modify_flags, 1627 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 1628 1629 SET_FIELD(p_ramrod->flags, 1630 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG, 1631 GET_FIELD(modify_flags, 1632 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)); 1633 1634 SET_FIELD(p_ramrod->flags, 1635 ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG, 1636 GET_FIELD(modify_flags, 1637 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)); 1638 1639 SET_FIELD(p_ramrod->flags, 1640 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG, 1641 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)); 1642 1643 SET_FIELD(p_ramrod->flags, 1644 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG, 1645 GET_FIELD(modify_flags, 1646 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)); 1647 1648 p_ramrod->fields = 0; 1649 SET_FIELD(p_ramrod->fields, 1650 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 1651 1652 SET_FIELD(p_ramrod->fields, 1653 ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 1654 qp->rnr_retry_cnt); 1655 1656 p_ramrod->max_ord = qp->max_rd_atomic_req; 1657 p_ramrod->traffic_class = qp->traffic_class_tos; 1658 p_ramrod->hop_limit = qp->hop_limit_ttl; 1659 p_ramrod->p_key = cpu_to_le16(qp->pkey); 1660 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1661 p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 1662 p_ramrod->mtu = cpu_to_le16(qp->mtu); 1663 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1664 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1665 1666 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc); 1667 return rc; 1668 } 1669 1670 static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn, 1671 struct qed_rdma_qp *qp, 1672 u32 *num_invalidated_mw, 1673 u32 *cq_prod) 1674 { 1675 struct roce_destroy_qp_resp_output_params *p_ramrod_res; 1676 struct roce_destroy_qp_resp_ramrod_data *p_ramrod; 1677 struct qed_sp_init_data init_data; 1678 struct qed_spq_entry *p_ent; 1679 dma_addr_t ramrod_res_phys; 1680 int rc; 1681 1682 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1683 1684 *num_invalidated_mw = 0; 1685 *cq_prod = qp->cq_prod; 1686 1687 if (!qp->resp_offloaded) { 1688 /* If a responder was never offload, we need to free the cids 1689 * allocated in create_qp as a FW async event will never arrive 1690 */ 1691 u32 cid; 1692 1693 cid = qp->icid - 1694 qed_cxt_get_proto_cid_start(p_hwfn, 1695 p_hwfn->p_rdma_info->proto); 1696 qed_roce_free_cid_pair(p_hwfn, (u16)cid); 1697 1698 return 0; 1699 } 1700 1701 /* Get SPQ entry */ 1702 memset(&init_data, 0, sizeof(init_data)); 1703 init_data.cid = qp->icid; 1704 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1705 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1706 1707 rc = qed_sp_init_request(p_hwfn, &p_ent, 1708 ROCE_RAMROD_DESTROY_QP, 1709 PROTOCOLID_ROCE, &init_data); 1710 if (rc) 1711 return rc; 1712 1713 p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp; 1714 1715 p_ramrod_res = (struct roce_destroy_qp_resp_output_params *) 1716 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 1717 &ramrod_res_phys, GFP_KERNEL); 1718 1719 if (!p_ramrod_res) { 1720 rc = -ENOMEM; 1721 DP_NOTICE(p_hwfn, 1722 "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n", 1723 rc); 1724 return rc; 1725 } 1726 1727 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1728 1729 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1730 if (rc) 1731 goto err; 1732 1733 *num_invalidated_mw = le32_to_cpu(p_ramrod_res->num_invalidated_mw); 1734 *cq_prod = le32_to_cpu(p_ramrod_res->cq_prod); 1735 qp->cq_prod = *cq_prod; 1736 1737 /* Free IRQ - only if ramrod succeeded, in case FW is still using it */ 1738 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1739 qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 1740 qp->irq, qp->irq_phys_addr); 1741 1742 qp->resp_offloaded = false; 1743 1744 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc); 1745 1746 err: 1747 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1748 sizeof(struct roce_destroy_qp_resp_output_params), 1749 p_ramrod_res, ramrod_res_phys); 1750 1751 return rc; 1752 } 1753 1754 static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn, 1755 struct qed_rdma_qp *qp, 1756 u32 *num_bound_mw) 1757 { 1758 struct roce_destroy_qp_req_output_params *p_ramrod_res; 1759 struct roce_destroy_qp_req_ramrod_data *p_ramrod; 1760 struct qed_sp_init_data init_data; 1761 struct qed_spq_entry *p_ent; 1762 dma_addr_t ramrod_res_phys; 1763 int rc = -ENOMEM; 1764 1765 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1766 1767 if (!qp->req_offloaded) 1768 return 0; 1769 1770 p_ramrod_res = (struct roce_destroy_qp_req_output_params *) 1771 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1772 sizeof(*p_ramrod_res), 1773 &ramrod_res_phys, GFP_KERNEL); 1774 if (!p_ramrod_res) { 1775 DP_NOTICE(p_hwfn, 1776 "qed destroy requester failed: cannot allocate memory (ramrod)\n"); 1777 return rc; 1778 } 1779 1780 /* Get SPQ entry */ 1781 memset(&init_data, 0, sizeof(init_data)); 1782 init_data.cid = qp->icid + 1; 1783 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1784 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1785 1786 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP, 1787 PROTOCOLID_ROCE, &init_data); 1788 if (rc) 1789 goto err; 1790 1791 p_ramrod = &p_ent->ramrod.roce_destroy_qp_req; 1792 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1793 1794 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1795 if (rc) 1796 goto err; 1797 1798 *num_bound_mw = le32_to_cpu(p_ramrod_res->num_bound_mw); 1799 1800 /* Free ORQ - only if ramrod succeeded, in case FW is still using it */ 1801 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1802 qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 1803 qp->orq, qp->orq_phys_addr); 1804 1805 qp->req_offloaded = false; 1806 1807 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc); 1808 1809 err: 1810 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 1811 p_ramrod_res, ramrod_res_phys); 1812 1813 return rc; 1814 } 1815 1816 static int qed_roce_query_qp(struct qed_hwfn *p_hwfn, 1817 struct qed_rdma_qp *qp, 1818 struct qed_rdma_query_qp_out_params *out_params) 1819 { 1820 struct roce_query_qp_resp_output_params *p_resp_ramrod_res; 1821 struct roce_query_qp_req_output_params *p_req_ramrod_res; 1822 struct roce_query_qp_resp_ramrod_data *p_resp_ramrod; 1823 struct roce_query_qp_req_ramrod_data *p_req_ramrod; 1824 struct qed_sp_init_data init_data; 1825 dma_addr_t resp_ramrod_res_phys; 1826 dma_addr_t req_ramrod_res_phys; 1827 struct qed_spq_entry *p_ent; 1828 bool rq_err_state; 1829 bool sq_err_state; 1830 bool sq_draining; 1831 int rc = -ENOMEM; 1832 1833 if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) { 1834 /* We can't send ramrod to the fw since this qp wasn't offloaded 1835 * to the fw yet 1836 */ 1837 out_params->draining = false; 1838 out_params->rq_psn = qp->rq_psn; 1839 out_params->sq_psn = qp->sq_psn; 1840 out_params->state = qp->cur_state; 1841 1842 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n"); 1843 return 0; 1844 } 1845 1846 if (!(qp->resp_offloaded)) { 1847 DP_NOTICE(p_hwfn, 1848 "The responder's qp should be offloded before requester's\n"); 1849 return -EINVAL; 1850 } 1851 1852 /* Send a query responder ramrod to FW to get RQ-PSN and state */ 1853 p_resp_ramrod_res = (struct roce_query_qp_resp_output_params *) 1854 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1855 sizeof(*p_resp_ramrod_res), 1856 &resp_ramrod_res_phys, GFP_KERNEL); 1857 if (!p_resp_ramrod_res) { 1858 DP_NOTICE(p_hwfn, 1859 "qed query qp failed: cannot allocate memory (ramrod)\n"); 1860 return rc; 1861 } 1862 1863 /* Get SPQ entry */ 1864 memset(&init_data, 0, sizeof(init_data)); 1865 init_data.cid = qp->icid; 1866 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1867 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1868 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 1869 PROTOCOLID_ROCE, &init_data); 1870 if (rc) 1871 goto err_resp; 1872 1873 p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp; 1874 DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys); 1875 1876 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1877 if (rc) 1878 goto err_resp; 1879 1880 out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn); 1881 rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->err_flag), 1882 ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG); 1883 1884 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 1885 p_resp_ramrod_res, resp_ramrod_res_phys); 1886 1887 if (!(qp->req_offloaded)) { 1888 /* Don't send query qp for the requester */ 1889 out_params->sq_psn = qp->sq_psn; 1890 out_params->draining = false; 1891 1892 if (rq_err_state) 1893 qp->cur_state = QED_ROCE_QP_STATE_ERR; 1894 1895 out_params->state = qp->cur_state; 1896 1897 return 0; 1898 } 1899 1900 /* Send a query requester ramrod to FW to get SQ-PSN and state */ 1901 p_req_ramrod_res = (struct roce_query_qp_req_output_params *) 1902 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1903 sizeof(*p_req_ramrod_res), 1904 &req_ramrod_res_phys, 1905 GFP_KERNEL); 1906 if (!p_req_ramrod_res) { 1907 rc = -ENOMEM; 1908 DP_NOTICE(p_hwfn, 1909 "qed query qp failed: cannot allocate memory (ramrod)\n"); 1910 return rc; 1911 } 1912 1913 /* Get SPQ entry */ 1914 init_data.cid = qp->icid + 1; 1915 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 1916 PROTOCOLID_ROCE, &init_data); 1917 if (rc) 1918 goto err_req; 1919 1920 p_req_ramrod = &p_ent->ramrod.roce_query_qp_req; 1921 DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys); 1922 1923 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1924 if (rc) 1925 goto err_req; 1926 1927 out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn); 1928 sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 1929 ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG); 1930 sq_draining = 1931 GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 1932 ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG); 1933 1934 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 1935 p_req_ramrod_res, req_ramrod_res_phys); 1936 1937 out_params->draining = false; 1938 1939 if (rq_err_state || sq_err_state) 1940 qp->cur_state = QED_ROCE_QP_STATE_ERR; 1941 else if (sq_draining) 1942 out_params->draining = true; 1943 out_params->state = qp->cur_state; 1944 1945 return 0; 1946 1947 err_req: 1948 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 1949 p_req_ramrod_res, req_ramrod_res_phys); 1950 return rc; 1951 err_resp: 1952 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 1953 p_resp_ramrod_res, resp_ramrod_res_phys); 1954 return rc; 1955 } 1956 1957 static int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 1958 { 1959 u32 num_invalidated_mw = 0; 1960 u32 num_bound_mw = 0; 1961 u32 cq_prod; 1962 int rc; 1963 1964 /* Destroys the specified QP */ 1965 if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) && 1966 (qp->cur_state != QED_ROCE_QP_STATE_ERR) && 1967 (qp->cur_state != QED_ROCE_QP_STATE_INIT)) { 1968 DP_NOTICE(p_hwfn, 1969 "QP must be in error, reset or init state before destroying it\n"); 1970 return -EINVAL; 1971 } 1972 1973 if (qp->cur_state != QED_ROCE_QP_STATE_RESET) { 1974 rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, 1975 &num_invalidated_mw, 1976 &cq_prod); 1977 if (rc) 1978 return rc; 1979 1980 /* Send destroy requester ramrod */ 1981 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, 1982 &num_bound_mw); 1983 if (rc) 1984 return rc; 1985 1986 if (num_invalidated_mw != num_bound_mw) { 1987 DP_NOTICE(p_hwfn, 1988 "number of invalidate memory windows is different from bounded ones\n"); 1989 return -EINVAL; 1990 } 1991 } 1992 1993 return 0; 1994 } 1995 1996 static int qed_rdma_query_qp(void *rdma_cxt, 1997 struct qed_rdma_qp *qp, 1998 struct qed_rdma_query_qp_out_params *out_params) 1999 { 2000 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2001 int rc; 2002 2003 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 2004 2005 /* The following fields are filled in from qp and not FW as they can't 2006 * be modified by FW 2007 */ 2008 out_params->mtu = qp->mtu; 2009 out_params->dest_qp = qp->dest_qp; 2010 out_params->incoming_atomic_en = qp->incoming_atomic_en; 2011 out_params->e2e_flow_control_en = qp->e2e_flow_control_en; 2012 out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en; 2013 out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en; 2014 out_params->dgid = qp->dgid; 2015 out_params->flow_label = qp->flow_label; 2016 out_params->hop_limit_ttl = qp->hop_limit_ttl; 2017 out_params->traffic_class_tos = qp->traffic_class_tos; 2018 out_params->timeout = qp->ack_timeout; 2019 out_params->rnr_retry = qp->rnr_retry_cnt; 2020 out_params->retry_cnt = qp->retry_cnt; 2021 out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer; 2022 out_params->pkey_index = 0; 2023 out_params->max_rd_atomic = qp->max_rd_atomic_req; 2024 out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp; 2025 out_params->sqd_async = qp->sqd_async; 2026 2027 rc = qed_roce_query_qp(p_hwfn, qp, out_params); 2028 2029 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc); 2030 return rc; 2031 } 2032 2033 static int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp) 2034 { 2035 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2036 int rc = 0; 2037 2038 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 2039 2040 rc = qed_roce_destroy_qp(p_hwfn, qp); 2041 2042 /* free qp params struct */ 2043 kfree(qp); 2044 2045 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n"); 2046 return rc; 2047 } 2048 2049 static struct qed_rdma_qp * 2050 qed_rdma_create_qp(void *rdma_cxt, 2051 struct qed_rdma_create_qp_in_params *in_params, 2052 struct qed_rdma_create_qp_out_params *out_params) 2053 { 2054 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2055 struct qed_rdma_qp *qp; 2056 u8 max_stats_queues; 2057 int rc; 2058 2059 if (!rdma_cxt || !in_params || !out_params || !p_hwfn->p_rdma_info) { 2060 DP_ERR(p_hwfn->cdev, 2061 "qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n", 2062 rdma_cxt, in_params, out_params); 2063 return NULL; 2064 } 2065 2066 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2067 "qed rdma create qp called with qp_handle = %08x%08x\n", 2068 in_params->qp_handle_hi, in_params->qp_handle_lo); 2069 2070 /* Some sanity checks... */ 2071 max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues; 2072 if (in_params->stats_queue >= max_stats_queues) { 2073 DP_ERR(p_hwfn->cdev, 2074 "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n", 2075 in_params->stats_queue, max_stats_queues); 2076 return NULL; 2077 } 2078 2079 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2080 if (!qp) { 2081 DP_NOTICE(p_hwfn, "Failed to allocate qed_rdma_qp\n"); 2082 return NULL; 2083 } 2084 2085 rc = qed_roce_alloc_cid(p_hwfn, &qp->icid); 2086 qp->qpid = ((0xFF << 16) | qp->icid); 2087 2088 DP_INFO(p_hwfn, "ROCE qpid=%x\n", qp->qpid); 2089 2090 if (rc) { 2091 kfree(qp); 2092 return NULL; 2093 } 2094 2095 qp->cur_state = QED_ROCE_QP_STATE_RESET; 2096 qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi); 2097 qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo); 2098 qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi); 2099 qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo); 2100 qp->use_srq = in_params->use_srq; 2101 qp->signal_all = in_params->signal_all; 2102 qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey; 2103 qp->pd = in_params->pd; 2104 qp->dpi = in_params->dpi; 2105 qp->sq_cq_id = in_params->sq_cq_id; 2106 qp->sq_num_pages = in_params->sq_num_pages; 2107 qp->sq_pbl_ptr = in_params->sq_pbl_ptr; 2108 qp->rq_cq_id = in_params->rq_cq_id; 2109 qp->rq_num_pages = in_params->rq_num_pages; 2110 qp->rq_pbl_ptr = in_params->rq_pbl_ptr; 2111 qp->srq_id = in_params->srq_id; 2112 qp->req_offloaded = false; 2113 qp->resp_offloaded = false; 2114 qp->e2e_flow_control_en = qp->use_srq ? false : true; 2115 qp->stats_queue = in_params->stats_queue; 2116 2117 out_params->icid = qp->icid; 2118 out_params->qp_id = qp->qpid; 2119 2120 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc); 2121 return qp; 2122 } 2123 2124 static int qed_roce_modify_qp(struct qed_hwfn *p_hwfn, 2125 struct qed_rdma_qp *qp, 2126 enum qed_roce_qp_state prev_state, 2127 struct qed_rdma_modify_qp_in_params *params) 2128 { 2129 u32 num_invalidated_mw = 0, num_bound_mw = 0; 2130 int rc = 0; 2131 2132 /* Perform additional operations according to the current state and the 2133 * next state 2134 */ 2135 if (((prev_state == QED_ROCE_QP_STATE_INIT) || 2136 (prev_state == QED_ROCE_QP_STATE_RESET)) && 2137 (qp->cur_state == QED_ROCE_QP_STATE_RTR)) { 2138 /* Init->RTR or Reset->RTR */ 2139 rc = qed_roce_sp_create_responder(p_hwfn, qp); 2140 return rc; 2141 } else if ((prev_state == QED_ROCE_QP_STATE_RTR) && 2142 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 2143 /* RTR-> RTS */ 2144 rc = qed_roce_sp_create_requester(p_hwfn, qp); 2145 if (rc) 2146 return rc; 2147 2148 /* Send modify responder ramrod */ 2149 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2150 params->modify_flags); 2151 return rc; 2152 } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 2153 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 2154 /* RTS->RTS */ 2155 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2156 params->modify_flags); 2157 if (rc) 2158 return rc; 2159 2160 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 2161 params->modify_flags); 2162 return rc; 2163 } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 2164 (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 2165 /* RTS->SQD */ 2166 rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false, 2167 params->modify_flags); 2168 return rc; 2169 } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 2170 (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 2171 /* SQD->SQD */ 2172 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2173 params->modify_flags); 2174 if (rc) 2175 return rc; 2176 2177 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 2178 params->modify_flags); 2179 return rc; 2180 } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 2181 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 2182 /* SQD->RTS */ 2183 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2184 params->modify_flags); 2185 if (rc) 2186 return rc; 2187 2188 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 2189 params->modify_flags); 2190 2191 return rc; 2192 } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR || 2193 qp->cur_state == QED_ROCE_QP_STATE_SQE) { 2194 /* ->ERR */ 2195 rc = qed_roce_sp_modify_responder(p_hwfn, qp, true, 2196 params->modify_flags); 2197 if (rc) 2198 return rc; 2199 2200 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true, 2201 params->modify_flags); 2202 return rc; 2203 } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) { 2204 /* Any state -> RESET */ 2205 u32 cq_prod; 2206 2207 /* Send destroy responder ramrod */ 2208 rc = qed_roce_sp_destroy_qp_responder(p_hwfn, 2209 qp, 2210 &num_invalidated_mw, 2211 &cq_prod); 2212 2213 if (rc) 2214 return rc; 2215 2216 qp->cq_prod = cq_prod; 2217 2218 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, 2219 &num_bound_mw); 2220 2221 if (num_invalidated_mw != num_bound_mw) { 2222 DP_NOTICE(p_hwfn, 2223 "number of invalidate memory windows is different from bounded ones\n"); 2224 return -EINVAL; 2225 } 2226 } else { 2227 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 2228 } 2229 2230 return rc; 2231 } 2232 2233 static int qed_rdma_modify_qp(void *rdma_cxt, 2234 struct qed_rdma_qp *qp, 2235 struct qed_rdma_modify_qp_in_params *params) 2236 { 2237 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2238 enum qed_roce_qp_state prev_state; 2239 int rc = 0; 2240 2241 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n", 2242 qp->icid, params->new_state); 2243 2244 if (rc) { 2245 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2246 return rc; 2247 } 2248 2249 if (GET_FIELD(params->modify_flags, 2250 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) { 2251 qp->incoming_rdma_read_en = params->incoming_rdma_read_en; 2252 qp->incoming_rdma_write_en = params->incoming_rdma_write_en; 2253 qp->incoming_atomic_en = params->incoming_atomic_en; 2254 } 2255 2256 /* Update QP structure with the updated values */ 2257 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE)) 2258 qp->roce_mode = params->roce_mode; 2259 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)) 2260 qp->pkey = params->pkey; 2261 if (GET_FIELD(params->modify_flags, 2262 QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN)) 2263 qp->e2e_flow_control_en = params->e2e_flow_control_en; 2264 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP)) 2265 qp->dest_qp = params->dest_qp; 2266 if (GET_FIELD(params->modify_flags, 2267 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) { 2268 /* Indicates that the following parameters have changed: 2269 * Traffic class, flow label, hop limit, source GID, 2270 * destination GID, loopback indicator 2271 */ 2272 qp->traffic_class_tos = params->traffic_class_tos; 2273 qp->flow_label = params->flow_label; 2274 qp->hop_limit_ttl = params->hop_limit_ttl; 2275 2276 qp->sgid = params->sgid; 2277 qp->dgid = params->dgid; 2278 qp->udp_src_port = 0; 2279 qp->vlan_id = params->vlan_id; 2280 qp->mtu = params->mtu; 2281 qp->lb_indication = params->lb_indication; 2282 memcpy((u8 *)&qp->remote_mac_addr[0], 2283 (u8 *)¶ms->remote_mac_addr[0], ETH_ALEN); 2284 if (params->use_local_mac) { 2285 memcpy((u8 *)&qp->local_mac_addr[0], 2286 (u8 *)¶ms->local_mac_addr[0], ETH_ALEN); 2287 } else { 2288 memcpy((u8 *)&qp->local_mac_addr[0], 2289 (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN); 2290 } 2291 } 2292 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN)) 2293 qp->rq_psn = params->rq_psn; 2294 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN)) 2295 qp->sq_psn = params->sq_psn; 2296 if (GET_FIELD(params->modify_flags, 2297 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)) 2298 qp->max_rd_atomic_req = params->max_rd_atomic_req; 2299 if (GET_FIELD(params->modify_flags, 2300 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)) 2301 qp->max_rd_atomic_resp = params->max_rd_atomic_resp; 2302 if (GET_FIELD(params->modify_flags, 2303 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)) 2304 qp->ack_timeout = params->ack_timeout; 2305 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)) 2306 qp->retry_cnt = params->retry_cnt; 2307 if (GET_FIELD(params->modify_flags, 2308 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)) 2309 qp->rnr_retry_cnt = params->rnr_retry_cnt; 2310 if (GET_FIELD(params->modify_flags, 2311 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)) 2312 qp->min_rnr_nak_timer = params->min_rnr_nak_timer; 2313 2314 qp->sqd_async = params->sqd_async; 2315 2316 prev_state = qp->cur_state; 2317 if (GET_FIELD(params->modify_flags, 2318 QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) { 2319 qp->cur_state = params->new_state; 2320 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n", 2321 qp->cur_state); 2322 } 2323 2324 rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params); 2325 2326 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc); 2327 return rc; 2328 } 2329 2330 static int 2331 qed_rdma_register_tid(void *rdma_cxt, 2332 struct qed_rdma_register_tid_in_params *params) 2333 { 2334 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2335 struct rdma_register_tid_ramrod_data *p_ramrod; 2336 struct qed_sp_init_data init_data; 2337 struct qed_spq_entry *p_ent; 2338 enum rdma_tid_type tid_type; 2339 u8 fw_return_code; 2340 int rc; 2341 2342 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", params->itid); 2343 2344 /* Get SPQ entry */ 2345 memset(&init_data, 0, sizeof(init_data)); 2346 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 2347 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 2348 2349 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_REGISTER_MR, 2350 p_hwfn->p_rdma_info->proto, &init_data); 2351 if (rc) { 2352 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2353 return rc; 2354 } 2355 2356 if (p_hwfn->p_rdma_info->last_tid < params->itid) 2357 p_hwfn->p_rdma_info->last_tid = params->itid; 2358 2359 p_ramrod = &p_ent->ramrod.rdma_register_tid; 2360 2361 p_ramrod->flags = 0; 2362 SET_FIELD(p_ramrod->flags, 2363 RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL, 2364 params->pbl_two_level); 2365 2366 SET_FIELD(p_ramrod->flags, 2367 RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED, params->zbva); 2368 2369 SET_FIELD(p_ramrod->flags, 2370 RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR, params->phy_mr); 2371 2372 /* Don't initialize D/C field, as it may override other bits. */ 2373 if (!(params->tid_type == QED_RDMA_TID_FMR) && !(params->dma_mr)) 2374 SET_FIELD(p_ramrod->flags, 2375 RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG, 2376 params->page_size_log - 12); 2377 2378 SET_FIELD(p_ramrod->flags, 2379 RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID, 2380 p_hwfn->p_rdma_info->last_tid); 2381 2382 SET_FIELD(p_ramrod->flags, 2383 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ, 2384 params->remote_read); 2385 2386 SET_FIELD(p_ramrod->flags, 2387 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE, 2388 params->remote_write); 2389 2390 SET_FIELD(p_ramrod->flags, 2391 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC, 2392 params->remote_atomic); 2393 2394 SET_FIELD(p_ramrod->flags, 2395 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE, 2396 params->local_write); 2397 2398 SET_FIELD(p_ramrod->flags, 2399 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ, params->local_read); 2400 2401 SET_FIELD(p_ramrod->flags, 2402 RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND, 2403 params->mw_bind); 2404 2405 SET_FIELD(p_ramrod->flags1, 2406 RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG, 2407 params->pbl_page_size_log - 12); 2408 2409 SET_FIELD(p_ramrod->flags2, 2410 RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR, params->dma_mr); 2411 2412 switch (params->tid_type) { 2413 case QED_RDMA_TID_REGISTERED_MR: 2414 tid_type = RDMA_TID_REGISTERED_MR; 2415 break; 2416 case QED_RDMA_TID_FMR: 2417 tid_type = RDMA_TID_FMR; 2418 break; 2419 case QED_RDMA_TID_MW_TYPE1: 2420 tid_type = RDMA_TID_MW_TYPE1; 2421 break; 2422 case QED_RDMA_TID_MW_TYPE2A: 2423 tid_type = RDMA_TID_MW_TYPE2A; 2424 break; 2425 default: 2426 rc = -EINVAL; 2427 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2428 return rc; 2429 } 2430 SET_FIELD(p_ramrod->flags1, 2431 RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE, tid_type); 2432 2433 p_ramrod->itid = cpu_to_le32(params->itid); 2434 p_ramrod->key = params->key; 2435 p_ramrod->pd = cpu_to_le16(params->pd); 2436 p_ramrod->length_hi = (u8)(params->length >> 32); 2437 p_ramrod->length_lo = DMA_LO_LE(params->length); 2438 if (params->zbva) { 2439 /* Lower 32 bits of the registered MR address. 2440 * In case of zero based MR, will hold FBO 2441 */ 2442 p_ramrod->va.hi = 0; 2443 p_ramrod->va.lo = cpu_to_le32(params->fbo); 2444 } else { 2445 DMA_REGPAIR_LE(p_ramrod->va, params->vaddr); 2446 } 2447 DMA_REGPAIR_LE(p_ramrod->pbl_base, params->pbl_ptr); 2448 2449 /* DIF */ 2450 if (params->dif_enabled) { 2451 SET_FIELD(p_ramrod->flags2, 2452 RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG, 1); 2453 DMA_REGPAIR_LE(p_ramrod->dif_error_addr, 2454 params->dif_error_addr); 2455 DMA_REGPAIR_LE(p_ramrod->dif_runt_addr, params->dif_runt_addr); 2456 } 2457 2458 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 2459 2460 if (fw_return_code != RDMA_RETURN_OK) { 2461 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 2462 return -EINVAL; 2463 } 2464 2465 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Register TID, rc = %d\n", rc); 2466 return rc; 2467 } 2468 2469 static int qed_rdma_deregister_tid(void *rdma_cxt, u32 itid) 2470 { 2471 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2472 struct rdma_deregister_tid_ramrod_data *p_ramrod; 2473 struct qed_sp_init_data init_data; 2474 struct qed_spq_entry *p_ent; 2475 struct qed_ptt *p_ptt; 2476 u8 fw_return_code; 2477 int rc; 2478 2479 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 2480 2481 /* Get SPQ entry */ 2482 memset(&init_data, 0, sizeof(init_data)); 2483 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 2484 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 2485 2486 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_DEREGISTER_MR, 2487 p_hwfn->p_rdma_info->proto, &init_data); 2488 if (rc) { 2489 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2490 return rc; 2491 } 2492 2493 p_ramrod = &p_ent->ramrod.rdma_deregister_tid; 2494 p_ramrod->itid = cpu_to_le32(itid); 2495 2496 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 2497 if (rc) { 2498 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2499 return rc; 2500 } 2501 2502 if (fw_return_code == RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR) { 2503 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 2504 return -EINVAL; 2505 } else if (fw_return_code == RDMA_RETURN_NIG_DRAIN_REQ) { 2506 /* Bit indicating that the TID is in use and a nig drain is 2507 * required before sending the ramrod again 2508 */ 2509 p_ptt = qed_ptt_acquire(p_hwfn); 2510 if (!p_ptt) { 2511 rc = -EBUSY; 2512 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2513 "Failed to acquire PTT\n"); 2514 return rc; 2515 } 2516 2517 rc = qed_mcp_drain(p_hwfn, p_ptt); 2518 if (rc) { 2519 qed_ptt_release(p_hwfn, p_ptt); 2520 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2521 "Drain failed\n"); 2522 return rc; 2523 } 2524 2525 qed_ptt_release(p_hwfn, p_ptt); 2526 2527 /* Resend the ramrod */ 2528 rc = qed_sp_init_request(p_hwfn, &p_ent, 2529 RDMA_RAMROD_DEREGISTER_MR, 2530 p_hwfn->p_rdma_info->proto, 2531 &init_data); 2532 if (rc) { 2533 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2534 "Failed to init sp-element\n"); 2535 return rc; 2536 } 2537 2538 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 2539 if (rc) { 2540 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2541 "Ramrod failed\n"); 2542 return rc; 2543 } 2544 2545 if (fw_return_code != RDMA_RETURN_OK) { 2546 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", 2547 fw_return_code); 2548 return rc; 2549 } 2550 } 2551 2552 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "De-registered TID, rc = %d\n", rc); 2553 return rc; 2554 } 2555 2556 static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid) 2557 { 2558 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 2559 u32 start_cid, cid, xcid; 2560 2561 /* an even icid belongs to a responder while an odd icid belongs to a 2562 * requester. The 'cid' received as an input can be either. We calculate 2563 * the "partner" icid and call it xcid. Only if both are free then the 2564 * "cid" map can be cleared. 2565 */ 2566 start_cid = qed_cxt_get_proto_cid_start(p_hwfn, p_rdma_info->proto); 2567 cid = icid - start_cid; 2568 xcid = cid ^ 1; 2569 2570 spin_lock_bh(&p_rdma_info->lock); 2571 2572 qed_bmap_release_id(p_hwfn, &p_rdma_info->real_cid_map, cid); 2573 if (qed_bmap_test_id(p_hwfn, &p_rdma_info->real_cid_map, xcid) == 0) { 2574 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, cid); 2575 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, xcid); 2576 } 2577 2578 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 2579 } 2580 2581 static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev) 2582 { 2583 return QED_LEADING_HWFN(cdev); 2584 } 2585 2586 static void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2587 { 2588 u32 val; 2589 2590 val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1; 2591 2592 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val); 2593 DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA), 2594 "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n", 2595 val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm); 2596 } 2597 2598 void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2599 { 2600 p_hwfn->db_bar_no_edpm = true; 2601 2602 qed_rdma_dpm_conf(p_hwfn, p_ptt); 2603 } 2604 2605 static int qed_rdma_start(void *rdma_cxt, 2606 struct qed_rdma_start_in_params *params) 2607 { 2608 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2609 struct qed_ptt *p_ptt; 2610 int rc = -EBUSY; 2611 2612 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2613 "desired_cnq = %08x\n", params->desired_cnq); 2614 2615 p_ptt = qed_ptt_acquire(p_hwfn); 2616 if (!p_ptt) 2617 goto err; 2618 2619 rc = qed_rdma_alloc(p_hwfn, p_ptt, params); 2620 if (rc) 2621 goto err1; 2622 2623 rc = qed_rdma_setup(p_hwfn, p_ptt, params); 2624 if (rc) 2625 goto err2; 2626 2627 qed_ptt_release(p_hwfn, p_ptt); 2628 2629 return rc; 2630 2631 err2: 2632 qed_rdma_free(p_hwfn); 2633 err1: 2634 qed_ptt_release(p_hwfn, p_ptt); 2635 err: 2636 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc); 2637 return rc; 2638 } 2639 2640 static int qed_rdma_init(struct qed_dev *cdev, 2641 struct qed_rdma_start_in_params *params) 2642 { 2643 return qed_rdma_start(QED_LEADING_HWFN(cdev), params); 2644 } 2645 2646 static void qed_rdma_remove_user(void *rdma_cxt, u16 dpi) 2647 { 2648 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2649 2650 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi); 2651 2652 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 2653 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi); 2654 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 2655 } 2656 2657 void qed_ll2b_complete_tx_gsi_packet(struct qed_hwfn *p_hwfn, 2658 u8 connection_handle, 2659 void *cookie, 2660 dma_addr_t first_frag_addr, 2661 bool b_last_fragment, bool b_last_packet) 2662 { 2663 struct qed_roce_ll2_packet *packet = cookie; 2664 struct qed_roce_ll2_info *roce_ll2 = p_hwfn->ll2; 2665 2666 roce_ll2->cbs.tx_cb(roce_ll2->cb_cookie, packet); 2667 } 2668 2669 void qed_ll2b_release_tx_gsi_packet(struct qed_hwfn *p_hwfn, 2670 u8 connection_handle, 2671 void *cookie, 2672 dma_addr_t first_frag_addr, 2673 bool b_last_fragment, bool b_last_packet) 2674 { 2675 qed_ll2b_complete_tx_gsi_packet(p_hwfn, connection_handle, 2676 cookie, first_frag_addr, 2677 b_last_fragment, b_last_packet); 2678 } 2679 2680 void qed_ll2b_complete_rx_gsi_packet(struct qed_hwfn *p_hwfn, 2681 u8 connection_handle, 2682 void *cookie, 2683 dma_addr_t rx_buf_addr, 2684 u16 data_length, 2685 u8 data_length_error, 2686 u16 parse_flags, 2687 u16 vlan, 2688 u32 src_mac_addr_hi, 2689 u16 src_mac_addr_lo, bool b_last_packet) 2690 { 2691 struct qed_roce_ll2_info *roce_ll2 = p_hwfn->ll2; 2692 struct qed_roce_ll2_rx_params params; 2693 struct qed_dev *cdev = p_hwfn->cdev; 2694 struct qed_roce_ll2_packet pkt; 2695 2696 DP_VERBOSE(cdev, 2697 QED_MSG_LL2, 2698 "roce ll2 rx complete: bus_addr=%p, len=%d, data_len_err=%d\n", 2699 (void *)(uintptr_t)rx_buf_addr, 2700 data_length, data_length_error); 2701 2702 memset(&pkt, 0, sizeof(pkt)); 2703 pkt.n_seg = 1; 2704 pkt.payload[0].baddr = rx_buf_addr; 2705 pkt.payload[0].len = data_length; 2706 2707 memset(¶ms, 0, sizeof(params)); 2708 params.vlan_id = vlan; 2709 *((u32 *)¶ms.smac[0]) = ntohl(src_mac_addr_hi); 2710 *((u16 *)¶ms.smac[4]) = ntohs(src_mac_addr_lo); 2711 2712 if (data_length_error) { 2713 DP_ERR(cdev, 2714 "roce ll2 rx complete: data length error %d, length=%d\n", 2715 data_length_error, data_length); 2716 params.rc = -EINVAL; 2717 } 2718 2719 roce_ll2->cbs.rx_cb(roce_ll2->cb_cookie, &pkt, ¶ms); 2720 } 2721 2722 static int qed_roce_ll2_set_mac_filter(struct qed_dev *cdev, 2723 u8 *old_mac_address, 2724 u8 *new_mac_address) 2725 { 2726 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2727 struct qed_ptt *p_ptt; 2728 int rc = 0; 2729 2730 if (!hwfn->ll2 || hwfn->ll2->handle == QED_LL2_UNUSED_HANDLE) { 2731 DP_ERR(cdev, 2732 "qed roce mac filter failed - roce_info/ll2 NULL\n"); 2733 return -EINVAL; 2734 } 2735 2736 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 2737 if (!p_ptt) { 2738 DP_ERR(cdev, 2739 "qed roce ll2 mac filter set: failed to acquire PTT\n"); 2740 return -EINVAL; 2741 } 2742 2743 mutex_lock(&hwfn->ll2->lock); 2744 if (old_mac_address) 2745 qed_llh_remove_mac_filter(QED_LEADING_HWFN(cdev), p_ptt, 2746 old_mac_address); 2747 if (new_mac_address) 2748 rc = qed_llh_add_mac_filter(QED_LEADING_HWFN(cdev), p_ptt, 2749 new_mac_address); 2750 mutex_unlock(&hwfn->ll2->lock); 2751 2752 qed_ptt_release(QED_LEADING_HWFN(cdev), p_ptt); 2753 2754 if (rc) 2755 DP_ERR(cdev, 2756 "qed roce ll2 mac filter set: failed to add mac filter\n"); 2757 2758 return rc; 2759 } 2760 2761 static int qed_roce_ll2_start(struct qed_dev *cdev, 2762 struct qed_roce_ll2_params *params) 2763 { 2764 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2765 struct qed_roce_ll2_info *roce_ll2; 2766 struct qed_ll2_conn ll2_params; 2767 int rc; 2768 2769 if (!params) { 2770 DP_ERR(cdev, "qed roce ll2 start: failed due to NULL params\n"); 2771 return -EINVAL; 2772 } 2773 if (!params->cbs.tx_cb || !params->cbs.rx_cb) { 2774 DP_ERR(cdev, 2775 "qed roce ll2 start: failed due to NULL tx/rx. tx_cb=%p, rx_cb=%p\n", 2776 params->cbs.tx_cb, params->cbs.rx_cb); 2777 return -EINVAL; 2778 } 2779 if (!is_valid_ether_addr(params->mac_address)) { 2780 DP_ERR(cdev, 2781 "qed roce ll2 start: failed due to invalid Ethernet address %pM\n", 2782 params->mac_address); 2783 return -EINVAL; 2784 } 2785 2786 /* Initialize */ 2787 roce_ll2 = kzalloc(sizeof(*roce_ll2), GFP_ATOMIC); 2788 if (!roce_ll2) { 2789 DP_ERR(cdev, "qed roce ll2 start: failed memory allocation\n"); 2790 return -ENOMEM; 2791 } 2792 roce_ll2->handle = QED_LL2_UNUSED_HANDLE; 2793 roce_ll2->cbs = params->cbs; 2794 roce_ll2->cb_cookie = params->cb_cookie; 2795 mutex_init(&roce_ll2->lock); 2796 2797 memset(&ll2_params, 0, sizeof(ll2_params)); 2798 ll2_params.conn_type = QED_LL2_TYPE_ROCE; 2799 ll2_params.mtu = params->mtu; 2800 ll2_params.rx_drop_ttl0_flg = true; 2801 ll2_params.rx_vlan_removal_en = false; 2802 ll2_params.tx_dest = CORE_TX_DEST_NW; 2803 ll2_params.ai_err_packet_too_big = LL2_DROP_PACKET; 2804 ll2_params.ai_err_no_buf = LL2_DROP_PACKET; 2805 ll2_params.gsi_enable = true; 2806 2807 rc = qed_ll2_acquire_connection(QED_LEADING_HWFN(cdev), &ll2_params, 2808 params->max_rx_buffers, 2809 params->max_tx_buffers, 2810 &roce_ll2->handle); 2811 if (rc) { 2812 DP_ERR(cdev, 2813 "qed roce ll2 start: failed to acquire LL2 connection (rc=%d)\n", 2814 rc); 2815 goto err; 2816 } 2817 2818 rc = qed_ll2_establish_connection(QED_LEADING_HWFN(cdev), 2819 roce_ll2->handle); 2820 if (rc) { 2821 DP_ERR(cdev, 2822 "qed roce ll2 start: failed to establish LL2 connection (rc=%d)\n", 2823 rc); 2824 goto err1; 2825 } 2826 2827 hwfn->ll2 = roce_ll2; 2828 2829 rc = qed_roce_ll2_set_mac_filter(cdev, NULL, params->mac_address); 2830 if (rc) { 2831 hwfn->ll2 = NULL; 2832 goto err2; 2833 } 2834 ether_addr_copy(roce_ll2->mac_address, params->mac_address); 2835 2836 return 0; 2837 2838 err2: 2839 qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle); 2840 err1: 2841 qed_ll2_release_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle); 2842 err: 2843 kfree(roce_ll2); 2844 return rc; 2845 } 2846 2847 static int qed_roce_ll2_stop(struct qed_dev *cdev) 2848 { 2849 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2850 struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2; 2851 int rc; 2852 2853 if (roce_ll2->handle == QED_LL2_UNUSED_HANDLE) { 2854 DP_ERR(cdev, "qed roce ll2 stop: cannot stop an unused LL2\n"); 2855 return -EINVAL; 2856 } 2857 2858 /* remove LL2 MAC address filter */ 2859 rc = qed_roce_ll2_set_mac_filter(cdev, roce_ll2->mac_address, NULL); 2860 eth_zero_addr(roce_ll2->mac_address); 2861 2862 rc = qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev), 2863 roce_ll2->handle); 2864 if (rc) 2865 DP_ERR(cdev, 2866 "qed roce ll2 stop: failed to terminate LL2 connection (rc=%d)\n", 2867 rc); 2868 2869 qed_ll2_release_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle); 2870 2871 roce_ll2->handle = QED_LL2_UNUSED_HANDLE; 2872 2873 kfree(roce_ll2); 2874 2875 return rc; 2876 } 2877 2878 static int qed_roce_ll2_tx(struct qed_dev *cdev, 2879 struct qed_roce_ll2_packet *pkt, 2880 struct qed_roce_ll2_tx_params *params) 2881 { 2882 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2883 struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2; 2884 enum qed_ll2_roce_flavor_type qed_roce_flavor; 2885 u8 flags = 0; 2886 int rc; 2887 int i; 2888 2889 if (!pkt || !params) { 2890 DP_ERR(cdev, 2891 "roce ll2 tx: failed tx because one of the following is NULL - drv=%p, pkt=%p, params=%p\n", 2892 cdev, pkt, params); 2893 return -EINVAL; 2894 } 2895 2896 qed_roce_flavor = (pkt->roce_mode == ROCE_V1) ? QED_LL2_ROCE 2897 : QED_LL2_RROCE; 2898 2899 if (pkt->roce_mode == ROCE_V2_IPV4) 2900 flags |= BIT(CORE_TX_BD_DATA_IP_CSUM_SHIFT); 2901 2902 /* Tx header */ 2903 rc = qed_ll2_prepare_tx_packet(QED_LEADING_HWFN(cdev), roce_ll2->handle, 2904 1 + pkt->n_seg, 0, flags, 0, 2905 QED_LL2_TX_DEST_NW, 2906 qed_roce_flavor, pkt->header.baddr, 2907 pkt->header.len, pkt, 1); 2908 if (rc) { 2909 DP_ERR(cdev, "roce ll2 tx: header failed (rc=%d)\n", rc); 2910 return QED_ROCE_TX_HEAD_FAILURE; 2911 } 2912 2913 /* Tx payload */ 2914 for (i = 0; i < pkt->n_seg; i++) { 2915 rc = qed_ll2_set_fragment_of_tx_packet(QED_LEADING_HWFN(cdev), 2916 roce_ll2->handle, 2917 pkt->payload[i].baddr, 2918 pkt->payload[i].len); 2919 if (rc) { 2920 /* If failed not much to do here, partial packet has 2921 * been posted * we can't free memory, will need to wait 2922 * for completion 2923 */ 2924 DP_ERR(cdev, 2925 "roce ll2 tx: payload failed (rc=%d)\n", rc); 2926 return QED_ROCE_TX_FRAG_FAILURE; 2927 } 2928 } 2929 2930 return 0; 2931 } 2932 2933 static int qed_roce_ll2_post_rx_buffer(struct qed_dev *cdev, 2934 struct qed_roce_ll2_buffer *buf, 2935 u64 cookie, u8 notify_fw) 2936 { 2937 return qed_ll2_post_rx_buffer(QED_LEADING_HWFN(cdev), 2938 QED_LEADING_HWFN(cdev)->ll2->handle, 2939 buf->baddr, buf->len, 2940 (void *)(uintptr_t)cookie, notify_fw); 2941 } 2942 2943 static int qed_roce_ll2_stats(struct qed_dev *cdev, struct qed_ll2_stats *stats) 2944 { 2945 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2946 struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2; 2947 2948 return qed_ll2_get_stats(QED_LEADING_HWFN(cdev), 2949 roce_ll2->handle, stats); 2950 } 2951 2952 static const struct qed_rdma_ops qed_rdma_ops_pass = { 2953 .common = &qed_common_ops_pass, 2954 .fill_dev_info = &qed_fill_rdma_dev_info, 2955 .rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx, 2956 .rdma_init = &qed_rdma_init, 2957 .rdma_add_user = &qed_rdma_add_user, 2958 .rdma_remove_user = &qed_rdma_remove_user, 2959 .rdma_stop = &qed_rdma_stop, 2960 .rdma_query_port = &qed_rdma_query_port, 2961 .rdma_query_device = &qed_rdma_query_device, 2962 .rdma_get_start_sb = &qed_rdma_get_sb_start, 2963 .rdma_get_rdma_int = &qed_rdma_get_int, 2964 .rdma_set_rdma_int = &qed_rdma_set_int, 2965 .rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix, 2966 .rdma_cnq_prod_update = &qed_rdma_cnq_prod_update, 2967 .rdma_alloc_pd = &qed_rdma_alloc_pd, 2968 .rdma_dealloc_pd = &qed_rdma_free_pd, 2969 .rdma_create_cq = &qed_rdma_create_cq, 2970 .rdma_destroy_cq = &qed_rdma_destroy_cq, 2971 .rdma_create_qp = &qed_rdma_create_qp, 2972 .rdma_modify_qp = &qed_rdma_modify_qp, 2973 .rdma_query_qp = &qed_rdma_query_qp, 2974 .rdma_destroy_qp = &qed_rdma_destroy_qp, 2975 .rdma_alloc_tid = &qed_rdma_alloc_tid, 2976 .rdma_free_tid = &qed_rdma_free_tid, 2977 .rdma_register_tid = &qed_rdma_register_tid, 2978 .rdma_deregister_tid = &qed_rdma_deregister_tid, 2979 .roce_ll2_start = &qed_roce_ll2_start, 2980 .roce_ll2_stop = &qed_roce_ll2_stop, 2981 .roce_ll2_tx = &qed_roce_ll2_tx, 2982 .roce_ll2_post_rx_buffer = &qed_roce_ll2_post_rx_buffer, 2983 .roce_ll2_set_mac_filter = &qed_roce_ll2_set_mac_filter, 2984 .roce_ll2_stats = &qed_roce_ll2_stats, 2985 }; 2986 2987 const struct qed_rdma_ops *qed_get_rdma_ops(void) 2988 { 2989 return &qed_rdma_ops_pass; 2990 } 2991 EXPORT_SYMBOL(qed_get_rdma_ops); 2992