1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/types.h> 33 #include <asm/byteorder.h> 34 #include <linux/bitops.h> 35 #include <linux/delay.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/errno.h> 38 #include <linux/io.h> 39 #include <linux/kernel.h> 40 #include <linux/list.h> 41 #include <linux/module.h> 42 #include <linux/mutex.h> 43 #include <linux/pci.h> 44 #include <linux/slab.h> 45 #include <linux/spinlock.h> 46 #include <linux/string.h> 47 #include "qed.h" 48 #include "qed_cxt.h" 49 #include "qed_hsi.h" 50 #include "qed_hw.h" 51 #include "qed_init_ops.h" 52 #include "qed_int.h" 53 #include "qed_ll2.h" 54 #include "qed_mcp.h" 55 #include "qed_reg_addr.h" 56 #include <linux/qed/qed_rdma_if.h> 57 #include "qed_rdma.h" 58 #include "qed_roce.h" 59 #include "qed_sp.h" 60 61 static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid); 62 63 static int 64 qed_roce_async_event(struct qed_hwfn *p_hwfn, 65 u8 fw_event_code, 66 u16 echo, union event_ring_data *data, u8 fw_return_code) 67 { 68 struct qed_rdma_events events = p_hwfn->p_rdma_info->events; 69 70 if (fw_event_code == ROCE_ASYNC_EVENT_DESTROY_QP_DONE) { 71 u16 icid = 72 (u16)le32_to_cpu(data->rdma_data.rdma_destroy_qp_data.cid); 73 74 /* icid release in this async event can occur only if the icid 75 * was offloaded to the FW. In case it wasn't offloaded this is 76 * handled in qed_roce_sp_destroy_qp. 77 */ 78 qed_roce_free_real_icid(p_hwfn, icid); 79 } else { 80 if (fw_event_code == ROCE_ASYNC_EVENT_SRQ_EMPTY || 81 fw_event_code == ROCE_ASYNC_EVENT_SRQ_LIMIT) { 82 u16 srq_id = (u16)data->rdma_data.async_handle.lo; 83 84 events.affiliated_event(events.context, fw_event_code, 85 &srq_id); 86 } else { 87 union rdma_eqe_data rdata = data->rdma_data; 88 89 events.affiliated_event(events.context, fw_event_code, 90 (void *)&rdata.async_handle); 91 } 92 } 93 94 return 0; 95 } 96 97 void qed_roce_stop(struct qed_hwfn *p_hwfn) 98 { 99 struct qed_bmap *rcid_map = &p_hwfn->p_rdma_info->real_cid_map; 100 int wait_count = 0; 101 102 /* when destroying a_RoCE QP the control is returned to the user after 103 * the synchronous part. The asynchronous part may take a little longer. 104 * We delay for a short while if an async destroy QP is still expected. 105 * Beyond the added delay we clear the bitmap anyway. 106 */ 107 while (bitmap_weight(rcid_map->bitmap, rcid_map->max_count)) { 108 msleep(100); 109 if (wait_count++ > 20) { 110 DP_NOTICE(p_hwfn, "cid bitmap wait timed out\n"); 111 break; 112 } 113 } 114 qed_spq_unregister_async_cb(p_hwfn, PROTOCOLID_ROCE); 115 } 116 117 static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid, 118 __le32 *dst_gid) 119 { 120 u32 i; 121 122 if (qp->roce_mode == ROCE_V2_IPV4) { 123 /* The IPv4 addresses shall be aligned to the highest word. 124 * The lower words must be zero. 125 */ 126 memset(src_gid, 0, sizeof(union qed_gid)); 127 memset(dst_gid, 0, sizeof(union qed_gid)); 128 src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr); 129 dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr); 130 } else { 131 /* GIDs and IPv6 addresses coincide in location and size */ 132 for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) { 133 src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]); 134 dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]); 135 } 136 } 137 } 138 139 static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode) 140 { 141 enum roce_flavor flavor; 142 143 switch (roce_mode) { 144 case ROCE_V1: 145 flavor = PLAIN_ROCE; 146 break; 147 case ROCE_V2_IPV4: 148 flavor = RROCE_IPV4; 149 break; 150 case ROCE_V2_IPV6: 151 flavor = ROCE_V2_IPV6; 152 break; 153 default: 154 flavor = MAX_ROCE_MODE; 155 break; 156 } 157 return flavor; 158 } 159 160 void qed_roce_free_cid_pair(struct qed_hwfn *p_hwfn, u16 cid) 161 { 162 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 163 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid); 164 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid + 1); 165 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 166 } 167 168 int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid) 169 { 170 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 171 u32 responder_icid; 172 u32 requester_icid; 173 int rc; 174 175 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 176 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 177 &responder_icid); 178 if (rc) { 179 spin_unlock_bh(&p_rdma_info->lock); 180 return rc; 181 } 182 183 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 184 &requester_icid); 185 186 spin_unlock_bh(&p_rdma_info->lock); 187 if (rc) 188 goto err; 189 190 /* the two icid's should be adjacent */ 191 if ((requester_icid - responder_icid) != 1) { 192 DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n"); 193 rc = -EINVAL; 194 goto err; 195 } 196 197 responder_icid += qed_cxt_get_proto_cid_start(p_hwfn, 198 p_rdma_info->proto); 199 requester_icid += qed_cxt_get_proto_cid_start(p_hwfn, 200 p_rdma_info->proto); 201 202 /* If these icids require a new ILT line allocate DMA-able context for 203 * an ILT page 204 */ 205 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid); 206 if (rc) 207 goto err; 208 209 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid); 210 if (rc) 211 goto err; 212 213 *cid = (u16)responder_icid; 214 return rc; 215 216 err: 217 spin_lock_bh(&p_rdma_info->lock); 218 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid); 219 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid); 220 221 spin_unlock_bh(&p_rdma_info->lock); 222 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 223 "Allocate CID - failed, rc = %d\n", rc); 224 return rc; 225 } 226 227 static void qed_roce_set_real_cid(struct qed_hwfn *p_hwfn, u32 cid) 228 { 229 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 230 qed_bmap_set_id(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, cid); 231 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 232 } 233 234 static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn, 235 struct qed_rdma_qp *qp) 236 { 237 struct roce_create_qp_resp_ramrod_data *p_ramrod; 238 struct qed_sp_init_data init_data; 239 enum roce_flavor roce_flavor; 240 struct qed_spq_entry *p_ent; 241 u16 regular_latency_queue; 242 enum protocol_type proto; 243 int rc; 244 245 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 246 247 /* Allocate DMA-able memory for IRQ */ 248 qp->irq_num_pages = 1; 249 qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 250 RDMA_RING_PAGE_SIZE, 251 &qp->irq_phys_addr, GFP_KERNEL); 252 if (!qp->irq) { 253 rc = -ENOMEM; 254 DP_NOTICE(p_hwfn, 255 "qed create responder failed: cannot allocate memory (irq). rc = %d\n", 256 rc); 257 return rc; 258 } 259 260 /* Get SPQ entry */ 261 memset(&init_data, 0, sizeof(init_data)); 262 init_data.cid = qp->icid; 263 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 264 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 265 266 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP, 267 PROTOCOLID_ROCE, &init_data); 268 if (rc) 269 goto err; 270 271 p_ramrod = &p_ent->ramrod.roce_create_qp_resp; 272 273 p_ramrod->flags = 0; 274 275 roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 276 SET_FIELD(p_ramrod->flags, 277 ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 278 279 SET_FIELD(p_ramrod->flags, 280 ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 281 qp->incoming_rdma_read_en); 282 283 SET_FIELD(p_ramrod->flags, 284 ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 285 qp->incoming_rdma_write_en); 286 287 SET_FIELD(p_ramrod->flags, 288 ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN, 289 qp->incoming_atomic_en); 290 291 SET_FIELD(p_ramrod->flags, 292 ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 293 qp->e2e_flow_control_en); 294 295 SET_FIELD(p_ramrod->flags, 296 ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq); 297 298 SET_FIELD(p_ramrod->flags, 299 ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN, 300 qp->fmr_and_reserved_lkey); 301 302 SET_FIELD(p_ramrod->flags, 303 ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 304 qp->min_rnr_nak_timer); 305 306 p_ramrod->max_ird = qp->max_rd_atomic_resp; 307 p_ramrod->traffic_class = qp->traffic_class_tos; 308 p_ramrod->hop_limit = qp->hop_limit_ttl; 309 p_ramrod->irq_num_pages = qp->irq_num_pages; 310 p_ramrod->p_key = cpu_to_le16(qp->pkey); 311 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 312 p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 313 p_ramrod->mtu = cpu_to_le16(qp->mtu); 314 p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn); 315 p_ramrod->pd = cpu_to_le16(qp->pd); 316 p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages); 317 DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr); 318 DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr); 319 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 320 p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 321 p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 322 p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 323 p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 324 p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 325 qp->rq_cq_id); 326 327 regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 328 329 p_ramrod->regular_latency_phy_queue = 330 cpu_to_le16(regular_latency_queue); 331 p_ramrod->low_latency_phy_queue = 332 cpu_to_le16(regular_latency_queue); 333 334 p_ramrod->dpi = cpu_to_le16(qp->dpi); 335 336 qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 337 qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 338 339 p_ramrod->udp_src_port = qp->udp_src_port; 340 p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 341 p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id); 342 p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid); 343 344 p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 345 qp->stats_queue; 346 347 rc = qed_spq_post(p_hwfn, p_ent, NULL); 348 349 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 350 "rc = %d regular physical queue = 0x%x\n", rc, 351 regular_latency_queue); 352 353 if (rc) 354 goto err; 355 356 qp->resp_offloaded = true; 357 qp->cq_prod = 0; 358 359 proto = p_hwfn->p_rdma_info->proto; 360 qed_roce_set_real_cid(p_hwfn, qp->icid - 361 qed_cxt_get_proto_cid_start(p_hwfn, proto)); 362 363 return rc; 364 365 err: 366 DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc); 367 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 368 qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 369 qp->irq, qp->irq_phys_addr); 370 371 return rc; 372 } 373 374 static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn, 375 struct qed_rdma_qp *qp) 376 { 377 struct roce_create_qp_req_ramrod_data *p_ramrod; 378 struct qed_sp_init_data init_data; 379 enum roce_flavor roce_flavor; 380 struct qed_spq_entry *p_ent; 381 u16 regular_latency_queue; 382 enum protocol_type proto; 383 int rc; 384 385 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 386 387 /* Allocate DMA-able memory for ORQ */ 388 qp->orq_num_pages = 1; 389 qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 390 RDMA_RING_PAGE_SIZE, 391 &qp->orq_phys_addr, GFP_KERNEL); 392 if (!qp->orq) { 393 rc = -ENOMEM; 394 DP_NOTICE(p_hwfn, 395 "qed create requester failed: cannot allocate memory (orq). rc = %d\n", 396 rc); 397 return rc; 398 } 399 400 /* Get SPQ entry */ 401 memset(&init_data, 0, sizeof(init_data)); 402 init_data.cid = qp->icid + 1; 403 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 404 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 405 406 rc = qed_sp_init_request(p_hwfn, &p_ent, 407 ROCE_RAMROD_CREATE_QP, 408 PROTOCOLID_ROCE, &init_data); 409 if (rc) 410 goto err; 411 412 p_ramrod = &p_ent->ramrod.roce_create_qp_req; 413 414 p_ramrod->flags = 0; 415 416 roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 417 SET_FIELD(p_ramrod->flags, 418 ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 419 420 SET_FIELD(p_ramrod->flags, 421 ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN, 422 qp->fmr_and_reserved_lkey); 423 424 SET_FIELD(p_ramrod->flags, 425 ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all); 426 427 SET_FIELD(p_ramrod->flags, 428 ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 429 430 SET_FIELD(p_ramrod->flags, 431 ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 432 qp->rnr_retry_cnt); 433 434 p_ramrod->max_ord = qp->max_rd_atomic_req; 435 p_ramrod->traffic_class = qp->traffic_class_tos; 436 p_ramrod->hop_limit = qp->hop_limit_ttl; 437 p_ramrod->orq_num_pages = qp->orq_num_pages; 438 p_ramrod->p_key = cpu_to_le16(qp->pkey); 439 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 440 p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 441 p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 442 p_ramrod->mtu = cpu_to_le16(qp->mtu); 443 p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn); 444 p_ramrod->pd = cpu_to_le16(qp->pd); 445 p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages); 446 DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr); 447 DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr); 448 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 449 p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 450 p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 451 p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 452 p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 453 p_ramrod->cq_cid = 454 cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | qp->sq_cq_id); 455 456 regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 457 458 p_ramrod->regular_latency_phy_queue = 459 cpu_to_le16(regular_latency_queue); 460 p_ramrod->low_latency_phy_queue = 461 cpu_to_le16(regular_latency_queue); 462 463 p_ramrod->dpi = cpu_to_le16(qp->dpi); 464 465 qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 466 qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 467 468 p_ramrod->udp_src_port = qp->udp_src_port; 469 p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 470 p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 471 qp->stats_queue; 472 473 rc = qed_spq_post(p_hwfn, p_ent, NULL); 474 475 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 476 477 if (rc) 478 goto err; 479 480 qp->req_offloaded = true; 481 proto = p_hwfn->p_rdma_info->proto; 482 qed_roce_set_real_cid(p_hwfn, 483 qp->icid + 1 - 484 qed_cxt_get_proto_cid_start(p_hwfn, proto)); 485 486 return rc; 487 488 err: 489 DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc); 490 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 491 qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 492 qp->orq, qp->orq_phys_addr); 493 return rc; 494 } 495 496 static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn, 497 struct qed_rdma_qp *qp, 498 bool move_to_err, u32 modify_flags) 499 { 500 struct roce_modify_qp_resp_ramrod_data *p_ramrod; 501 struct qed_sp_init_data init_data; 502 struct qed_spq_entry *p_ent; 503 int rc; 504 505 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 506 507 if (move_to_err && !qp->resp_offloaded) 508 return 0; 509 510 /* Get SPQ entry */ 511 memset(&init_data, 0, sizeof(init_data)); 512 init_data.cid = qp->icid; 513 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 514 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 515 516 rc = qed_sp_init_request(p_hwfn, &p_ent, 517 ROCE_EVENT_MODIFY_QP, 518 PROTOCOLID_ROCE, &init_data); 519 if (rc) { 520 DP_NOTICE(p_hwfn, "rc = %d\n", rc); 521 return rc; 522 } 523 524 p_ramrod = &p_ent->ramrod.roce_modify_qp_resp; 525 526 p_ramrod->flags = 0; 527 528 SET_FIELD(p_ramrod->flags, 529 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 530 531 SET_FIELD(p_ramrod->flags, 532 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 533 qp->incoming_rdma_read_en); 534 535 SET_FIELD(p_ramrod->flags, 536 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 537 qp->incoming_rdma_write_en); 538 539 SET_FIELD(p_ramrod->flags, 540 ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN, 541 qp->incoming_atomic_en); 542 543 SET_FIELD(p_ramrod->flags, 544 ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 545 qp->e2e_flow_control_en); 546 547 SET_FIELD(p_ramrod->flags, 548 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG, 549 GET_FIELD(modify_flags, 550 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)); 551 552 SET_FIELD(p_ramrod->flags, 553 ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG, 554 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 555 556 SET_FIELD(p_ramrod->flags, 557 ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG, 558 GET_FIELD(modify_flags, 559 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 560 561 SET_FIELD(p_ramrod->flags, 562 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG, 563 GET_FIELD(modify_flags, 564 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)); 565 566 SET_FIELD(p_ramrod->flags, 567 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG, 568 GET_FIELD(modify_flags, 569 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)); 570 571 p_ramrod->fields = 0; 572 SET_FIELD(p_ramrod->fields, 573 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 574 qp->min_rnr_nak_timer); 575 576 p_ramrod->max_ird = qp->max_rd_atomic_resp; 577 p_ramrod->traffic_class = qp->traffic_class_tos; 578 p_ramrod->hop_limit = qp->hop_limit_ttl; 579 p_ramrod->p_key = cpu_to_le16(qp->pkey); 580 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 581 p_ramrod->mtu = cpu_to_le16(qp->mtu); 582 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 583 rc = qed_spq_post(p_hwfn, p_ent, NULL); 584 585 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc); 586 return rc; 587 } 588 589 static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn, 590 struct qed_rdma_qp *qp, 591 bool move_to_sqd, 592 bool move_to_err, u32 modify_flags) 593 { 594 struct roce_modify_qp_req_ramrod_data *p_ramrod; 595 struct qed_sp_init_data init_data; 596 struct qed_spq_entry *p_ent; 597 int rc; 598 599 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 600 601 if (move_to_err && !(qp->req_offloaded)) 602 return 0; 603 604 /* Get SPQ entry */ 605 memset(&init_data, 0, sizeof(init_data)); 606 init_data.cid = qp->icid + 1; 607 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 608 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 609 610 rc = qed_sp_init_request(p_hwfn, &p_ent, 611 ROCE_EVENT_MODIFY_QP, 612 PROTOCOLID_ROCE, &init_data); 613 if (rc) { 614 DP_NOTICE(p_hwfn, "rc = %d\n", rc); 615 return rc; 616 } 617 618 p_ramrod = &p_ent->ramrod.roce_modify_qp_req; 619 620 p_ramrod->flags = 0; 621 622 SET_FIELD(p_ramrod->flags, 623 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 624 625 SET_FIELD(p_ramrod->flags, 626 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd); 627 628 SET_FIELD(p_ramrod->flags, 629 ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY, 630 qp->sqd_async); 631 632 SET_FIELD(p_ramrod->flags, 633 ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG, 634 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 635 636 SET_FIELD(p_ramrod->flags, 637 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG, 638 GET_FIELD(modify_flags, 639 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 640 641 SET_FIELD(p_ramrod->flags, 642 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG, 643 GET_FIELD(modify_flags, 644 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)); 645 646 SET_FIELD(p_ramrod->flags, 647 ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG, 648 GET_FIELD(modify_flags, 649 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)); 650 651 SET_FIELD(p_ramrod->flags, 652 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG, 653 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)); 654 655 SET_FIELD(p_ramrod->flags, 656 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG, 657 GET_FIELD(modify_flags, 658 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)); 659 660 p_ramrod->fields = 0; 661 SET_FIELD(p_ramrod->fields, 662 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 663 664 SET_FIELD(p_ramrod->fields, 665 ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 666 qp->rnr_retry_cnt); 667 668 p_ramrod->max_ord = qp->max_rd_atomic_req; 669 p_ramrod->traffic_class = qp->traffic_class_tos; 670 p_ramrod->hop_limit = qp->hop_limit_ttl; 671 p_ramrod->p_key = cpu_to_le16(qp->pkey); 672 p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 673 p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 674 p_ramrod->mtu = cpu_to_le16(qp->mtu); 675 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 676 rc = qed_spq_post(p_hwfn, p_ent, NULL); 677 678 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc); 679 return rc; 680 } 681 682 static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn, 683 struct qed_rdma_qp *qp, 684 u32 *num_invalidated_mw, 685 u32 *cq_prod) 686 { 687 struct roce_destroy_qp_resp_output_params *p_ramrod_res; 688 struct roce_destroy_qp_resp_ramrod_data *p_ramrod; 689 struct qed_sp_init_data init_data; 690 struct qed_spq_entry *p_ent; 691 dma_addr_t ramrod_res_phys; 692 int rc; 693 694 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 695 696 *num_invalidated_mw = 0; 697 *cq_prod = qp->cq_prod; 698 699 if (!qp->resp_offloaded) { 700 /* If a responder was never offload, we need to free the cids 701 * allocated in create_qp as a FW async event will never arrive 702 */ 703 u32 cid; 704 705 cid = qp->icid - 706 qed_cxt_get_proto_cid_start(p_hwfn, 707 p_hwfn->p_rdma_info->proto); 708 qed_roce_free_cid_pair(p_hwfn, (u16)cid); 709 710 return 0; 711 } 712 713 /* Get SPQ entry */ 714 memset(&init_data, 0, sizeof(init_data)); 715 init_data.cid = qp->icid; 716 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 717 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 718 719 rc = qed_sp_init_request(p_hwfn, &p_ent, 720 ROCE_RAMROD_DESTROY_QP, 721 PROTOCOLID_ROCE, &init_data); 722 if (rc) 723 return rc; 724 725 p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp; 726 727 p_ramrod_res = (struct roce_destroy_qp_resp_output_params *) 728 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 729 &ramrod_res_phys, GFP_KERNEL); 730 731 if (!p_ramrod_res) { 732 rc = -ENOMEM; 733 DP_NOTICE(p_hwfn, 734 "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n", 735 rc); 736 return rc; 737 } 738 739 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 740 741 rc = qed_spq_post(p_hwfn, p_ent, NULL); 742 if (rc) 743 goto err; 744 745 *num_invalidated_mw = le32_to_cpu(p_ramrod_res->num_invalidated_mw); 746 *cq_prod = le32_to_cpu(p_ramrod_res->cq_prod); 747 qp->cq_prod = *cq_prod; 748 749 /* Free IRQ - only if ramrod succeeded, in case FW is still using it */ 750 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 751 qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 752 qp->irq, qp->irq_phys_addr); 753 754 qp->resp_offloaded = false; 755 756 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc); 757 758 err: 759 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 760 sizeof(struct roce_destroy_qp_resp_output_params), 761 p_ramrod_res, ramrod_res_phys); 762 763 return rc; 764 } 765 766 static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn, 767 struct qed_rdma_qp *qp, 768 u32 *num_bound_mw) 769 { 770 struct roce_destroy_qp_req_output_params *p_ramrod_res; 771 struct roce_destroy_qp_req_ramrod_data *p_ramrod; 772 struct qed_sp_init_data init_data; 773 struct qed_spq_entry *p_ent; 774 dma_addr_t ramrod_res_phys; 775 int rc = -ENOMEM; 776 777 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 778 779 if (!qp->req_offloaded) 780 return 0; 781 782 p_ramrod_res = (struct roce_destroy_qp_req_output_params *) 783 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 784 sizeof(*p_ramrod_res), 785 &ramrod_res_phys, GFP_KERNEL); 786 if (!p_ramrod_res) { 787 DP_NOTICE(p_hwfn, 788 "qed destroy requester failed: cannot allocate memory (ramrod)\n"); 789 return rc; 790 } 791 792 /* Get SPQ entry */ 793 memset(&init_data, 0, sizeof(init_data)); 794 init_data.cid = qp->icid + 1; 795 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 796 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 797 798 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP, 799 PROTOCOLID_ROCE, &init_data); 800 if (rc) 801 goto err; 802 803 p_ramrod = &p_ent->ramrod.roce_destroy_qp_req; 804 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 805 806 rc = qed_spq_post(p_hwfn, p_ent, NULL); 807 if (rc) 808 goto err; 809 810 *num_bound_mw = le32_to_cpu(p_ramrod_res->num_bound_mw); 811 812 /* Free ORQ - only if ramrod succeeded, in case FW is still using it */ 813 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 814 qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 815 qp->orq, qp->orq_phys_addr); 816 817 qp->req_offloaded = false; 818 819 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc); 820 821 err: 822 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 823 p_ramrod_res, ramrod_res_phys); 824 825 return rc; 826 } 827 828 int qed_roce_query_qp(struct qed_hwfn *p_hwfn, 829 struct qed_rdma_qp *qp, 830 struct qed_rdma_query_qp_out_params *out_params) 831 { 832 struct roce_query_qp_resp_output_params *p_resp_ramrod_res; 833 struct roce_query_qp_req_output_params *p_req_ramrod_res; 834 struct roce_query_qp_resp_ramrod_data *p_resp_ramrod; 835 struct roce_query_qp_req_ramrod_data *p_req_ramrod; 836 struct qed_sp_init_data init_data; 837 dma_addr_t resp_ramrod_res_phys; 838 dma_addr_t req_ramrod_res_phys; 839 struct qed_spq_entry *p_ent; 840 bool rq_err_state; 841 bool sq_err_state; 842 bool sq_draining; 843 int rc = -ENOMEM; 844 845 if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) { 846 /* We can't send ramrod to the fw since this qp wasn't offloaded 847 * to the fw yet 848 */ 849 out_params->draining = false; 850 out_params->rq_psn = qp->rq_psn; 851 out_params->sq_psn = qp->sq_psn; 852 out_params->state = qp->cur_state; 853 854 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n"); 855 return 0; 856 } 857 858 if (!(qp->resp_offloaded)) { 859 DP_NOTICE(p_hwfn, 860 "The responder's qp should be offloaded before requester's\n"); 861 return -EINVAL; 862 } 863 864 /* Send a query responder ramrod to FW to get RQ-PSN and state */ 865 p_resp_ramrod_res = (struct roce_query_qp_resp_output_params *) 866 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 867 sizeof(*p_resp_ramrod_res), 868 &resp_ramrod_res_phys, GFP_KERNEL); 869 if (!p_resp_ramrod_res) { 870 DP_NOTICE(p_hwfn, 871 "qed query qp failed: cannot allocate memory (ramrod)\n"); 872 return rc; 873 } 874 875 /* Get SPQ entry */ 876 memset(&init_data, 0, sizeof(init_data)); 877 init_data.cid = qp->icid; 878 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 879 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 880 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 881 PROTOCOLID_ROCE, &init_data); 882 if (rc) 883 goto err_resp; 884 885 p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp; 886 DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys); 887 888 rc = qed_spq_post(p_hwfn, p_ent, NULL); 889 if (rc) 890 goto err_resp; 891 892 out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn); 893 rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->err_flag), 894 ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG); 895 896 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 897 p_resp_ramrod_res, resp_ramrod_res_phys); 898 899 if (!(qp->req_offloaded)) { 900 /* Don't send query qp for the requester */ 901 out_params->sq_psn = qp->sq_psn; 902 out_params->draining = false; 903 904 if (rq_err_state) 905 qp->cur_state = QED_ROCE_QP_STATE_ERR; 906 907 out_params->state = qp->cur_state; 908 909 return 0; 910 } 911 912 /* Send a query requester ramrod to FW to get SQ-PSN and state */ 913 p_req_ramrod_res = (struct roce_query_qp_req_output_params *) 914 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 915 sizeof(*p_req_ramrod_res), 916 &req_ramrod_res_phys, 917 GFP_KERNEL); 918 if (!p_req_ramrod_res) { 919 rc = -ENOMEM; 920 DP_NOTICE(p_hwfn, 921 "qed query qp failed: cannot allocate memory (ramrod)\n"); 922 return rc; 923 } 924 925 /* Get SPQ entry */ 926 init_data.cid = qp->icid + 1; 927 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 928 PROTOCOLID_ROCE, &init_data); 929 if (rc) 930 goto err_req; 931 932 p_req_ramrod = &p_ent->ramrod.roce_query_qp_req; 933 DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys); 934 935 rc = qed_spq_post(p_hwfn, p_ent, NULL); 936 if (rc) 937 goto err_req; 938 939 out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn); 940 sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 941 ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG); 942 sq_draining = 943 GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 944 ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG); 945 946 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 947 p_req_ramrod_res, req_ramrod_res_phys); 948 949 out_params->draining = false; 950 951 if (rq_err_state || sq_err_state) 952 qp->cur_state = QED_ROCE_QP_STATE_ERR; 953 else if (sq_draining) 954 out_params->draining = true; 955 out_params->state = qp->cur_state; 956 957 return 0; 958 959 err_req: 960 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 961 p_req_ramrod_res, req_ramrod_res_phys); 962 return rc; 963 err_resp: 964 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 965 p_resp_ramrod_res, resp_ramrod_res_phys); 966 return rc; 967 } 968 969 int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 970 { 971 u32 num_invalidated_mw = 0; 972 u32 num_bound_mw = 0; 973 u32 cq_prod; 974 int rc; 975 976 /* Destroys the specified QP */ 977 if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) && 978 (qp->cur_state != QED_ROCE_QP_STATE_ERR) && 979 (qp->cur_state != QED_ROCE_QP_STATE_INIT)) { 980 DP_NOTICE(p_hwfn, 981 "QP must be in error, reset or init state before destroying it\n"); 982 return -EINVAL; 983 } 984 985 if (qp->cur_state != QED_ROCE_QP_STATE_RESET) { 986 rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, 987 &num_invalidated_mw, 988 &cq_prod); 989 if (rc) 990 return rc; 991 992 /* Send destroy requester ramrod */ 993 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, 994 &num_bound_mw); 995 if (rc) 996 return rc; 997 998 if (num_invalidated_mw != num_bound_mw) { 999 DP_NOTICE(p_hwfn, 1000 "number of invalidate memory windows is different from bounded ones\n"); 1001 return -EINVAL; 1002 } 1003 } 1004 1005 return 0; 1006 } 1007 1008 int qed_roce_modify_qp(struct qed_hwfn *p_hwfn, 1009 struct qed_rdma_qp *qp, 1010 enum qed_roce_qp_state prev_state, 1011 struct qed_rdma_modify_qp_in_params *params) 1012 { 1013 u32 num_invalidated_mw = 0, num_bound_mw = 0; 1014 int rc = 0; 1015 1016 /* Perform additional operations according to the current state and the 1017 * next state 1018 */ 1019 if (((prev_state == QED_ROCE_QP_STATE_INIT) || 1020 (prev_state == QED_ROCE_QP_STATE_RESET)) && 1021 (qp->cur_state == QED_ROCE_QP_STATE_RTR)) { 1022 /* Init->RTR or Reset->RTR */ 1023 rc = qed_roce_sp_create_responder(p_hwfn, qp); 1024 return rc; 1025 } else if ((prev_state == QED_ROCE_QP_STATE_RTR) && 1026 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1027 /* RTR-> RTS */ 1028 rc = qed_roce_sp_create_requester(p_hwfn, qp); 1029 if (rc) 1030 return rc; 1031 1032 /* Send modify responder ramrod */ 1033 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1034 params->modify_flags); 1035 return rc; 1036 } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1037 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1038 /* RTS->RTS */ 1039 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1040 params->modify_flags); 1041 if (rc) 1042 return rc; 1043 1044 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1045 params->modify_flags); 1046 return rc; 1047 } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1048 (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1049 /* RTS->SQD */ 1050 rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false, 1051 params->modify_flags); 1052 return rc; 1053 } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1054 (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1055 /* SQD->SQD */ 1056 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1057 params->modify_flags); 1058 if (rc) 1059 return rc; 1060 1061 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1062 params->modify_flags); 1063 return rc; 1064 } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1065 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1066 /* SQD->RTS */ 1067 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1068 params->modify_flags); 1069 if (rc) 1070 return rc; 1071 1072 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1073 params->modify_flags); 1074 1075 return rc; 1076 } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR) { 1077 /* ->ERR */ 1078 rc = qed_roce_sp_modify_responder(p_hwfn, qp, true, 1079 params->modify_flags); 1080 if (rc) 1081 return rc; 1082 1083 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true, 1084 params->modify_flags); 1085 return rc; 1086 } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) { 1087 /* Any state -> RESET */ 1088 u32 cq_prod; 1089 1090 /* Send destroy responder ramrod */ 1091 rc = qed_roce_sp_destroy_qp_responder(p_hwfn, 1092 qp, 1093 &num_invalidated_mw, 1094 &cq_prod); 1095 1096 if (rc) 1097 return rc; 1098 1099 qp->cq_prod = cq_prod; 1100 1101 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, 1102 &num_bound_mw); 1103 1104 if (num_invalidated_mw != num_bound_mw) { 1105 DP_NOTICE(p_hwfn, 1106 "number of invalidate memory windows is different from bounded ones\n"); 1107 return -EINVAL; 1108 } 1109 } else { 1110 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 1111 } 1112 1113 return rc; 1114 } 1115 1116 static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid) 1117 { 1118 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 1119 u32 start_cid, cid, xcid; 1120 1121 /* an even icid belongs to a responder while an odd icid belongs to a 1122 * requester. The 'cid' received as an input can be either. We calculate 1123 * the "partner" icid and call it xcid. Only if both are free then the 1124 * "cid" map can be cleared. 1125 */ 1126 start_cid = qed_cxt_get_proto_cid_start(p_hwfn, p_rdma_info->proto); 1127 cid = icid - start_cid; 1128 xcid = cid ^ 1; 1129 1130 spin_lock_bh(&p_rdma_info->lock); 1131 1132 qed_bmap_release_id(p_hwfn, &p_rdma_info->real_cid_map, cid); 1133 if (qed_bmap_test_id(p_hwfn, &p_rdma_info->real_cid_map, xcid) == 0) { 1134 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, cid); 1135 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, xcid); 1136 } 1137 1138 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1139 } 1140 1141 void qed_roce_dpm_dcbx(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1142 { 1143 u8 val; 1144 1145 /* if any QPs are already active, we want to disable DPM, since their 1146 * context information contains information from before the latest DCBx 1147 * update. Otherwise enable it. 1148 */ 1149 val = qed_rdma_allocated_qps(p_hwfn) ? true : false; 1150 p_hwfn->dcbx_no_edpm = (u8)val; 1151 1152 qed_rdma_dpm_conf(p_hwfn, p_ptt); 1153 } 1154 1155 int qed_roce_setup(struct qed_hwfn *p_hwfn) 1156 { 1157 return qed_spq_register_async_cb(p_hwfn, PROTOCOLID_ROCE, 1158 qed_roce_async_event); 1159 } 1160 1161 int qed_roce_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1162 { 1163 u32 ll2_ethertype_en; 1164 1165 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 1166 1167 p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE; 1168 1169 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 1170 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 1171 (ll2_ethertype_en | 0x01)); 1172 1173 if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) { 1174 DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n"); 1175 return -EINVAL; 1176 } 1177 1178 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n"); 1179 return 0; 1180 } 1181