151ff1725SRam Amrani /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 351ff1725SRam Amrani * 451ff1725SRam Amrani * This software is available to you under a choice of one of two 551ff1725SRam Amrani * licenses. You may choose to be licensed under the terms of the GNU 651ff1725SRam Amrani * General Public License (GPL) Version 2, available from the file 751ff1725SRam Amrani * COPYING in the main directory of this source tree, or the 851ff1725SRam Amrani * OpenIB.org BSD license below: 951ff1725SRam Amrani * 1051ff1725SRam Amrani * Redistribution and use in source and binary forms, with or 1151ff1725SRam Amrani * without modification, are permitted provided that the following 1251ff1725SRam Amrani * conditions are met: 1351ff1725SRam Amrani * 1451ff1725SRam Amrani * - Redistributions of source code must retain the above 1551ff1725SRam Amrani * copyright notice, this list of conditions and the following 1651ff1725SRam Amrani * disclaimer. 1751ff1725SRam Amrani * 1851ff1725SRam Amrani * - Redistributions in binary form must reproduce the above 1951ff1725SRam Amrani * copyright notice, this list of conditions and the following 2051ff1725SRam Amrani * disclaimer in the documentation and /or other materials 2151ff1725SRam Amrani * provided with the distribution. 2251ff1725SRam Amrani * 2351ff1725SRam Amrani * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 2451ff1725SRam Amrani * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 2551ff1725SRam Amrani * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 2651ff1725SRam Amrani * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 2751ff1725SRam Amrani * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 2851ff1725SRam Amrani * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 2951ff1725SRam Amrani * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 3051ff1725SRam Amrani * SOFTWARE. 3151ff1725SRam Amrani */ 3251ff1725SRam Amrani #include <linux/types.h> 3351ff1725SRam Amrani #include <asm/byteorder.h> 3451ff1725SRam Amrani #include <linux/bitops.h> 3551ff1725SRam Amrani #include <linux/delay.h> 3651ff1725SRam Amrani #include <linux/dma-mapping.h> 3751ff1725SRam Amrani #include <linux/errno.h> 3851ff1725SRam Amrani #include <linux/etherdevice.h> 3951ff1725SRam Amrani #include <linux/if_ether.h> 4051ff1725SRam Amrani #include <linux/if_vlan.h> 4151ff1725SRam Amrani #include <linux/io.h> 4251ff1725SRam Amrani #include <linux/ip.h> 4351ff1725SRam Amrani #include <linux/ipv6.h> 4451ff1725SRam Amrani #include <linux/kernel.h> 4551ff1725SRam Amrani #include <linux/list.h> 4651ff1725SRam Amrani #include <linux/module.h> 4751ff1725SRam Amrani #include <linux/mutex.h> 4851ff1725SRam Amrani #include <linux/pci.h> 4951ff1725SRam Amrani #include <linux/slab.h> 5051ff1725SRam Amrani #include <linux/spinlock.h> 5151ff1725SRam Amrani #include <linux/string.h> 5251ff1725SRam Amrani #include <linux/tcp.h> 5351ff1725SRam Amrani #include <linux/bitops.h> 5451ff1725SRam Amrani #include <linux/qed/qed_roce_if.h> 5551ff1725SRam Amrani #include <linux/qed/qed_roce_if.h> 5651ff1725SRam Amrani #include "qed.h" 5751ff1725SRam Amrani #include "qed_cxt.h" 5851ff1725SRam Amrani #include "qed_hsi.h" 5951ff1725SRam Amrani #include "qed_hw.h" 6051ff1725SRam Amrani #include "qed_init_ops.h" 6151ff1725SRam Amrani #include "qed_int.h" 6251ff1725SRam Amrani #include "qed_ll2.h" 6351ff1725SRam Amrani #include "qed_mcp.h" 6451ff1725SRam Amrani #include "qed_reg_addr.h" 6551ff1725SRam Amrani #include "qed_sp.h" 6651ff1725SRam Amrani #include "qed_roce.h" 67abd49676SRam Amrani #include "qed_ll2.h" 6851ff1725SRam Amrani 6951ff1725SRam Amrani void qed_async_roce_event(struct qed_hwfn *p_hwfn, 7051ff1725SRam Amrani struct event_ring_entry *p_eqe) 7151ff1725SRam Amrani { 7251ff1725SRam Amrani struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 7351ff1725SRam Amrani 7451ff1725SRam Amrani p_rdma_info->events.affiliated_event(p_rdma_info->events.context, 7551ff1725SRam Amrani p_eqe->opcode, &p_eqe->data); 7651ff1725SRam Amrani } 7751ff1725SRam Amrani 7851ff1725SRam Amrani static int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn, 7951ff1725SRam Amrani struct qed_bmap *bmap, u32 max_count) 8051ff1725SRam Amrani { 8151ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count); 8251ff1725SRam Amrani 8351ff1725SRam Amrani bmap->max_count = max_count; 8451ff1725SRam Amrani 8551ff1725SRam Amrani bmap->bitmap = kzalloc(BITS_TO_LONGS(max_count) * sizeof(long), 8651ff1725SRam Amrani GFP_KERNEL); 8751ff1725SRam Amrani if (!bmap->bitmap) { 8851ff1725SRam Amrani DP_NOTICE(p_hwfn, 8951ff1725SRam Amrani "qed bmap alloc failed: cannot allocate memory (bitmap)\n"); 9051ff1725SRam Amrani return -ENOMEM; 9151ff1725SRam Amrani } 9251ff1725SRam Amrani 9351ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocated bitmap %p\n", 9451ff1725SRam Amrani bmap->bitmap); 9551ff1725SRam Amrani return 0; 9651ff1725SRam Amrani } 9751ff1725SRam Amrani 9851ff1725SRam Amrani static int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn, 9951ff1725SRam Amrani struct qed_bmap *bmap, u32 *id_num) 10051ff1725SRam Amrani { 10151ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "bmap = %p\n", bmap); 10251ff1725SRam Amrani 10351ff1725SRam Amrani *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count); 10451ff1725SRam Amrani 10551ff1725SRam Amrani if (*id_num >= bmap->max_count) { 10651ff1725SRam Amrani DP_NOTICE(p_hwfn, "no id available max_count=%d\n", 10751ff1725SRam Amrani bmap->max_count); 10851ff1725SRam Amrani return -EINVAL; 10951ff1725SRam Amrani } 11051ff1725SRam Amrani 11151ff1725SRam Amrani __set_bit(*id_num, bmap->bitmap); 11251ff1725SRam Amrani 11351ff1725SRam Amrani return 0; 11451ff1725SRam Amrani } 11551ff1725SRam Amrani 11651ff1725SRam Amrani static void qed_bmap_release_id(struct qed_hwfn *p_hwfn, 11751ff1725SRam Amrani struct qed_bmap *bmap, u32 id_num) 11851ff1725SRam Amrani { 11951ff1725SRam Amrani bool b_acquired; 12051ff1725SRam Amrani 12151ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "id_num = %08x", id_num); 12251ff1725SRam Amrani if (id_num >= bmap->max_count) 12351ff1725SRam Amrani return; 12451ff1725SRam Amrani 12551ff1725SRam Amrani b_acquired = test_and_clear_bit(id_num, bmap->bitmap); 12651ff1725SRam Amrani if (!b_acquired) { 12751ff1725SRam Amrani DP_NOTICE(p_hwfn, "ID %d already released\n", id_num); 12851ff1725SRam Amrani return; 12951ff1725SRam Amrani } 13051ff1725SRam Amrani } 13151ff1725SRam Amrani 1320189efb8SYuval Mintz static u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id) 13351ff1725SRam Amrani { 13451ff1725SRam Amrani /* First sb id for RoCE is after all the l2 sb */ 13551ff1725SRam Amrani return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id; 13651ff1725SRam Amrani } 13751ff1725SRam Amrani 13851ff1725SRam Amrani static int qed_rdma_alloc(struct qed_hwfn *p_hwfn, 13951ff1725SRam Amrani struct qed_ptt *p_ptt, 14051ff1725SRam Amrani struct qed_rdma_start_in_params *params) 14151ff1725SRam Amrani { 14251ff1725SRam Amrani struct qed_rdma_info *p_rdma_info; 14351ff1725SRam Amrani u32 num_cons, num_tasks; 14451ff1725SRam Amrani int rc = -ENOMEM; 14551ff1725SRam Amrani 14651ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n"); 14751ff1725SRam Amrani 14851ff1725SRam Amrani /* Allocate a struct with current pf rdma info */ 14951ff1725SRam Amrani p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL); 15051ff1725SRam Amrani if (!p_rdma_info) { 15151ff1725SRam Amrani DP_NOTICE(p_hwfn, 15251ff1725SRam Amrani "qed rdma alloc failed: cannot allocate memory (rdma info). rc = %d\n", 15351ff1725SRam Amrani rc); 15451ff1725SRam Amrani return rc; 15551ff1725SRam Amrani } 15651ff1725SRam Amrani 15751ff1725SRam Amrani p_hwfn->p_rdma_info = p_rdma_info; 15851ff1725SRam Amrani p_rdma_info->proto = PROTOCOLID_ROCE; 15951ff1725SRam Amrani 1608c93beafSYuval Mintz num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto, 1618c93beafSYuval Mintz NULL); 16251ff1725SRam Amrani 16351ff1725SRam Amrani p_rdma_info->num_qps = num_cons / 2; 16451ff1725SRam Amrani 16551ff1725SRam Amrani num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE); 16651ff1725SRam Amrani 16751ff1725SRam Amrani /* Each MR uses a single task */ 16851ff1725SRam Amrani p_rdma_info->num_mrs = num_tasks; 16951ff1725SRam Amrani 17051ff1725SRam Amrani /* Queue zone lines are shared between RoCE and L2 in such a way that 17151ff1725SRam Amrani * they can be used by each without obstructing the other. 17251ff1725SRam Amrani */ 17351ff1725SRam Amrani p_rdma_info->queue_zone_base = (u16)FEAT_NUM(p_hwfn, QED_L2_QUEUE); 17451ff1725SRam Amrani 17551ff1725SRam Amrani /* Allocate a struct with device params and fill it */ 17651ff1725SRam Amrani p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL); 17751ff1725SRam Amrani if (!p_rdma_info->dev) { 17851ff1725SRam Amrani DP_NOTICE(p_hwfn, 17951ff1725SRam Amrani "qed rdma alloc failed: cannot allocate memory (rdma info dev). rc = %d\n", 18051ff1725SRam Amrani rc); 18151ff1725SRam Amrani goto free_rdma_info; 18251ff1725SRam Amrani } 18351ff1725SRam Amrani 18451ff1725SRam Amrani /* Allocate a struct with port params and fill it */ 18551ff1725SRam Amrani p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL); 18651ff1725SRam Amrani if (!p_rdma_info->port) { 18751ff1725SRam Amrani DP_NOTICE(p_hwfn, 18851ff1725SRam Amrani "qed rdma alloc failed: cannot allocate memory (rdma info port). rc = %d\n", 18951ff1725SRam Amrani rc); 19051ff1725SRam Amrani goto free_rdma_dev; 19151ff1725SRam Amrani } 19251ff1725SRam Amrani 19351ff1725SRam Amrani /* Allocate bit map for pd's */ 19451ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS); 19551ff1725SRam Amrani if (rc) { 19651ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 19751ff1725SRam Amrani "Failed to allocate pd_map, rc = %d\n", 19851ff1725SRam Amrani rc); 19951ff1725SRam Amrani goto free_rdma_port; 20051ff1725SRam Amrani } 20151ff1725SRam Amrani 20251ff1725SRam Amrani /* Allocate DPI bitmap */ 20351ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map, 20451ff1725SRam Amrani p_hwfn->dpi_count); 20551ff1725SRam Amrani if (rc) { 20651ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 20751ff1725SRam Amrani "Failed to allocate DPI bitmap, rc = %d\n", rc); 20851ff1725SRam Amrani goto free_pd_map; 20951ff1725SRam Amrani } 21051ff1725SRam Amrani 21151ff1725SRam Amrani /* Allocate bitmap for cq's. The maximum number of CQs is bounded to 21251ff1725SRam Amrani * twice the number of QPs. 21351ff1725SRam Amrani */ 21451ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map, 21551ff1725SRam Amrani p_rdma_info->num_qps * 2); 21651ff1725SRam Amrani if (rc) { 21751ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 21851ff1725SRam Amrani "Failed to allocate cq bitmap, rc = %d\n", rc); 21951ff1725SRam Amrani goto free_dpi_map; 22051ff1725SRam Amrani } 22151ff1725SRam Amrani 22251ff1725SRam Amrani /* Allocate bitmap for toggle bit for cq icids 22351ff1725SRam Amrani * We toggle the bit every time we create or resize cq for a given icid. 22451ff1725SRam Amrani * The maximum number of CQs is bounded to twice the number of QPs. 22551ff1725SRam Amrani */ 22651ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits, 22751ff1725SRam Amrani p_rdma_info->num_qps * 2); 22851ff1725SRam Amrani if (rc) { 22951ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 23051ff1725SRam Amrani "Failed to allocate toogle bits, rc = %d\n", rc); 23151ff1725SRam Amrani goto free_cq_map; 23251ff1725SRam Amrani } 23351ff1725SRam Amrani 23451ff1725SRam Amrani /* Allocate bitmap for itids */ 23551ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map, 23651ff1725SRam Amrani p_rdma_info->num_mrs); 23751ff1725SRam Amrani if (rc) { 23851ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 23951ff1725SRam Amrani "Failed to allocate itids bitmaps, rc = %d\n", rc); 24051ff1725SRam Amrani goto free_toggle_map; 24151ff1725SRam Amrani } 24251ff1725SRam Amrani 24351ff1725SRam Amrani /* Allocate bitmap for cids used for qps. */ 24451ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons); 24551ff1725SRam Amrani if (rc) { 24651ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 24751ff1725SRam Amrani "Failed to allocate cid bitmap, rc = %d\n", rc); 24851ff1725SRam Amrani goto free_tid_map; 24951ff1725SRam Amrani } 25051ff1725SRam Amrani 25151ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n"); 25251ff1725SRam Amrani return 0; 25351ff1725SRam Amrani 25451ff1725SRam Amrani free_tid_map: 25551ff1725SRam Amrani kfree(p_rdma_info->tid_map.bitmap); 25651ff1725SRam Amrani free_toggle_map: 25751ff1725SRam Amrani kfree(p_rdma_info->toggle_bits.bitmap); 25851ff1725SRam Amrani free_cq_map: 25951ff1725SRam Amrani kfree(p_rdma_info->cq_map.bitmap); 26051ff1725SRam Amrani free_dpi_map: 26151ff1725SRam Amrani kfree(p_rdma_info->dpi_map.bitmap); 26251ff1725SRam Amrani free_pd_map: 26351ff1725SRam Amrani kfree(p_rdma_info->pd_map.bitmap); 26451ff1725SRam Amrani free_rdma_port: 26551ff1725SRam Amrani kfree(p_rdma_info->port); 26651ff1725SRam Amrani free_rdma_dev: 26751ff1725SRam Amrani kfree(p_rdma_info->dev); 26851ff1725SRam Amrani free_rdma_info: 26951ff1725SRam Amrani kfree(p_rdma_info); 27051ff1725SRam Amrani 27151ff1725SRam Amrani return rc; 27251ff1725SRam Amrani } 27351ff1725SRam Amrani 2740189efb8SYuval Mintz static void qed_rdma_resc_free(struct qed_hwfn *p_hwfn) 27551ff1725SRam Amrani { 27651ff1725SRam Amrani struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 27751ff1725SRam Amrani 27851ff1725SRam Amrani kfree(p_rdma_info->cid_map.bitmap); 27951ff1725SRam Amrani kfree(p_rdma_info->tid_map.bitmap); 28051ff1725SRam Amrani kfree(p_rdma_info->toggle_bits.bitmap); 28151ff1725SRam Amrani kfree(p_rdma_info->cq_map.bitmap); 28251ff1725SRam Amrani kfree(p_rdma_info->dpi_map.bitmap); 28351ff1725SRam Amrani kfree(p_rdma_info->pd_map.bitmap); 28451ff1725SRam Amrani 28551ff1725SRam Amrani kfree(p_rdma_info->port); 28651ff1725SRam Amrani kfree(p_rdma_info->dev); 28751ff1725SRam Amrani 28851ff1725SRam Amrani kfree(p_rdma_info); 28951ff1725SRam Amrani } 29051ff1725SRam Amrani 29151ff1725SRam Amrani static void qed_rdma_free(struct qed_hwfn *p_hwfn) 29251ff1725SRam Amrani { 29351ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n"); 29451ff1725SRam Amrani 29551ff1725SRam Amrani qed_rdma_resc_free(p_hwfn); 29651ff1725SRam Amrani } 29751ff1725SRam Amrani 29851ff1725SRam Amrani static void qed_rdma_get_guid(struct qed_hwfn *p_hwfn, u8 *guid) 29951ff1725SRam Amrani { 30051ff1725SRam Amrani guid[0] = p_hwfn->hw_info.hw_mac_addr[0] ^ 2; 30151ff1725SRam Amrani guid[1] = p_hwfn->hw_info.hw_mac_addr[1]; 30251ff1725SRam Amrani guid[2] = p_hwfn->hw_info.hw_mac_addr[2]; 30351ff1725SRam Amrani guid[3] = 0xff; 30451ff1725SRam Amrani guid[4] = 0xfe; 30551ff1725SRam Amrani guid[5] = p_hwfn->hw_info.hw_mac_addr[3]; 30651ff1725SRam Amrani guid[6] = p_hwfn->hw_info.hw_mac_addr[4]; 30751ff1725SRam Amrani guid[7] = p_hwfn->hw_info.hw_mac_addr[5]; 30851ff1725SRam Amrani } 30951ff1725SRam Amrani 31051ff1725SRam Amrani static void qed_rdma_init_events(struct qed_hwfn *p_hwfn, 31151ff1725SRam Amrani struct qed_rdma_start_in_params *params) 31251ff1725SRam Amrani { 31351ff1725SRam Amrani struct qed_rdma_events *events; 31451ff1725SRam Amrani 31551ff1725SRam Amrani events = &p_hwfn->p_rdma_info->events; 31651ff1725SRam Amrani 31751ff1725SRam Amrani events->unaffiliated_event = params->events->unaffiliated_event; 31851ff1725SRam Amrani events->affiliated_event = params->events->affiliated_event; 31951ff1725SRam Amrani events->context = params->events->context; 32051ff1725SRam Amrani } 32151ff1725SRam Amrani 32251ff1725SRam Amrani static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn, 32351ff1725SRam Amrani struct qed_rdma_start_in_params *params) 32451ff1725SRam Amrani { 32551ff1725SRam Amrani struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 32651ff1725SRam Amrani struct qed_dev *cdev = p_hwfn->cdev; 32751ff1725SRam Amrani u32 pci_status_control; 32851ff1725SRam Amrani u32 num_qps; 32951ff1725SRam Amrani 33051ff1725SRam Amrani /* Vendor specific information */ 33151ff1725SRam Amrani dev->vendor_id = cdev->vendor_id; 33251ff1725SRam Amrani dev->vendor_part_id = cdev->device_id; 33351ff1725SRam Amrani dev->hw_ver = 0; 33451ff1725SRam Amrani dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | 33551ff1725SRam Amrani (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION); 33651ff1725SRam Amrani 33751ff1725SRam Amrani qed_rdma_get_guid(p_hwfn, (u8 *)&dev->sys_image_guid); 33851ff1725SRam Amrani dev->node_guid = dev->sys_image_guid; 33951ff1725SRam Amrani 34051ff1725SRam Amrani dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE, 34151ff1725SRam Amrani RDMA_MAX_SGE_PER_RQ_WQE); 34251ff1725SRam Amrani 34351ff1725SRam Amrani if (cdev->rdma_max_sge) 34451ff1725SRam Amrani dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge); 34551ff1725SRam Amrani 34651ff1725SRam Amrani dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE; 34751ff1725SRam Amrani 34851ff1725SRam Amrani dev->max_inline = (cdev->rdma_max_inline) ? 34951ff1725SRam Amrani min_t(u32, cdev->rdma_max_inline, dev->max_inline) : 35051ff1725SRam Amrani dev->max_inline; 35151ff1725SRam Amrani 35251ff1725SRam Amrani dev->max_wqe = QED_RDMA_MAX_WQE; 35351ff1725SRam Amrani dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ); 35451ff1725SRam Amrani 35551ff1725SRam Amrani /* The number of QPs may be higher than QED_ROCE_MAX_QPS, because 35651ff1725SRam Amrani * it is up-aligned to 16 and then to ILT page size within qed cxt. 35751ff1725SRam Amrani * This is OK in terms of ILT but we don't want to configure the FW 35851ff1725SRam Amrani * above its abilities 35951ff1725SRam Amrani */ 36051ff1725SRam Amrani num_qps = ROCE_MAX_QPS; 36151ff1725SRam Amrani num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps); 36251ff1725SRam Amrani dev->max_qp = num_qps; 36351ff1725SRam Amrani 36451ff1725SRam Amrani /* CQs uses the same icids that QPs use hence they are limited by the 36551ff1725SRam Amrani * number of icids. There are two icids per QP. 36651ff1725SRam Amrani */ 36751ff1725SRam Amrani dev->max_cq = num_qps * 2; 36851ff1725SRam Amrani 36951ff1725SRam Amrani /* The number of mrs is smaller by 1 since the first is reserved */ 37051ff1725SRam Amrani dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1; 37151ff1725SRam Amrani dev->max_mr_size = QED_RDMA_MAX_MR_SIZE; 37251ff1725SRam Amrani 37351ff1725SRam Amrani /* The maximum CQE capacity per CQ supported. 37451ff1725SRam Amrani * max number of cqes will be in two layer pbl, 37551ff1725SRam Amrani * 8 is the pointer size in bytes 37651ff1725SRam Amrani * 32 is the size of cq element in bytes 37751ff1725SRam Amrani */ 37851ff1725SRam Amrani if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS) 37951ff1725SRam Amrani dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT; 38051ff1725SRam Amrani else 38151ff1725SRam Amrani dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT; 38251ff1725SRam Amrani 38351ff1725SRam Amrani dev->max_mw = 0; 38451ff1725SRam Amrani dev->max_fmr = QED_RDMA_MAX_FMR; 38551ff1725SRam Amrani dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8); 38651ff1725SRam Amrani dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE; 38751ff1725SRam Amrani dev->max_pkey = QED_RDMA_MAX_P_KEY; 38851ff1725SRam Amrani 38951ff1725SRam Amrani dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 39051ff1725SRam Amrani (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2); 39151ff1725SRam Amrani dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 39251ff1725SRam Amrani RDMA_REQ_RD_ATOMIC_ELM_SIZE; 39351ff1725SRam Amrani dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc * 39451ff1725SRam Amrani p_hwfn->p_rdma_info->num_qps; 39551ff1725SRam Amrani dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS; 39651ff1725SRam Amrani dev->dev_ack_delay = QED_RDMA_ACK_DELAY; 39751ff1725SRam Amrani dev->max_pd = RDMA_MAX_PDS; 39851ff1725SRam Amrani dev->max_ah = p_hwfn->p_rdma_info->num_qps; 39951ff1725SRam Amrani dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE); 40051ff1725SRam Amrani 40151ff1725SRam Amrani /* Set capablities */ 40251ff1725SRam Amrani dev->dev_caps = 0; 40351ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1); 40451ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1); 40551ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1); 40651ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1); 40751ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1); 40851ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1); 40951ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1); 41051ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1); 41151ff1725SRam Amrani 41251ff1725SRam Amrani /* Check atomic operations support in PCI configuration space. */ 41351ff1725SRam Amrani pci_read_config_dword(cdev->pdev, 41451ff1725SRam Amrani cdev->pdev->pcie_cap + PCI_EXP_DEVCTL2, 41551ff1725SRam Amrani &pci_status_control); 41651ff1725SRam Amrani 41751ff1725SRam Amrani if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN) 41851ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1); 41951ff1725SRam Amrani } 42051ff1725SRam Amrani 42151ff1725SRam Amrani static void qed_rdma_init_port(struct qed_hwfn *p_hwfn) 42251ff1725SRam Amrani { 42351ff1725SRam Amrani struct qed_rdma_port *port = p_hwfn->p_rdma_info->port; 42451ff1725SRam Amrani struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 42551ff1725SRam Amrani 42651ff1725SRam Amrani port->port_state = p_hwfn->mcp_info->link_output.link_up ? 42751ff1725SRam Amrani QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN; 42851ff1725SRam Amrani 42951ff1725SRam Amrani port->max_msg_size = min_t(u64, 43051ff1725SRam Amrani (dev->max_mr_mw_fmr_size * 43151ff1725SRam Amrani p_hwfn->cdev->rdma_max_sge), 43251ff1725SRam Amrani BIT(31)); 43351ff1725SRam Amrani 43451ff1725SRam Amrani port->pkey_bad_counter = 0; 43551ff1725SRam Amrani } 43651ff1725SRam Amrani 43751ff1725SRam Amrani static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 43851ff1725SRam Amrani { 43951ff1725SRam Amrani u32 ll2_ethertype_en; 44051ff1725SRam Amrani 44151ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n"); 44251ff1725SRam Amrani p_hwfn->b_rdma_enabled_in_prs = false; 44351ff1725SRam Amrani 44451ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 44551ff1725SRam Amrani 44651ff1725SRam Amrani p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE; 44751ff1725SRam Amrani 44851ff1725SRam Amrani /* We delay writing to this reg until first cid is allocated. See 44951ff1725SRam Amrani * qed_cxt_dynamic_ilt_alloc function for more details 45051ff1725SRam Amrani */ 45151ff1725SRam Amrani ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 45251ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 45351ff1725SRam Amrani (ll2_ethertype_en | 0x01)); 45451ff1725SRam Amrani 45551ff1725SRam Amrani if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) { 45651ff1725SRam Amrani DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n"); 45751ff1725SRam Amrani return -EINVAL; 45851ff1725SRam Amrani } 45951ff1725SRam Amrani 46051ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n"); 46151ff1725SRam Amrani return 0; 46251ff1725SRam Amrani } 46351ff1725SRam Amrani 46451ff1725SRam Amrani static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn, 46551ff1725SRam Amrani struct qed_rdma_start_in_params *params, 46651ff1725SRam Amrani struct qed_ptt *p_ptt) 46751ff1725SRam Amrani { 46851ff1725SRam Amrani struct rdma_init_func_ramrod_data *p_ramrod; 46951ff1725SRam Amrani struct qed_rdma_cnq_params *p_cnq_pbl_list; 47051ff1725SRam Amrani struct rdma_init_func_hdr *p_params_header; 47151ff1725SRam Amrani struct rdma_cnq_params *p_cnq_params; 47251ff1725SRam Amrani struct qed_sp_init_data init_data; 47351ff1725SRam Amrani struct qed_spq_entry *p_ent; 47451ff1725SRam Amrani u32 cnq_id, sb_id; 47551ff1725SRam Amrani int rc; 47651ff1725SRam Amrani 47751ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n"); 47851ff1725SRam Amrani 47951ff1725SRam Amrani /* Save the number of cnqs for the function close ramrod */ 48051ff1725SRam Amrani p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq; 48151ff1725SRam Amrani 48251ff1725SRam Amrani /* Get SPQ entry */ 48351ff1725SRam Amrani memset(&init_data, 0, sizeof(init_data)); 48451ff1725SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 48551ff1725SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 48651ff1725SRam Amrani 48751ff1725SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT, 48851ff1725SRam Amrani p_hwfn->p_rdma_info->proto, &init_data); 48951ff1725SRam Amrani if (rc) 49051ff1725SRam Amrani return rc; 49151ff1725SRam Amrani 49251ff1725SRam Amrani p_ramrod = &p_ent->ramrod.roce_init_func.rdma; 49351ff1725SRam Amrani 49451ff1725SRam Amrani p_params_header = &p_ramrod->params_header; 49551ff1725SRam Amrani p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn, 49651ff1725SRam Amrani QED_RDMA_CNQ_RAM); 49751ff1725SRam Amrani p_params_header->num_cnqs = params->desired_cnq; 49851ff1725SRam Amrani 49951ff1725SRam Amrani if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS) 50051ff1725SRam Amrani p_params_header->cq_ring_mode = 1; 50151ff1725SRam Amrani else 50251ff1725SRam Amrani p_params_header->cq_ring_mode = 0; 50351ff1725SRam Amrani 50451ff1725SRam Amrani for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) { 50551ff1725SRam Amrani sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id); 50651ff1725SRam Amrani p_cnq_params = &p_ramrod->cnq_params[cnq_id]; 50751ff1725SRam Amrani p_cnq_pbl_list = ¶ms->cnq_pbl_list[cnq_id]; 50851ff1725SRam Amrani p_cnq_params->sb_num = 50951ff1725SRam Amrani cpu_to_le16(p_hwfn->sbs_info[sb_id]->igu_sb_id); 51051ff1725SRam Amrani 51151ff1725SRam Amrani p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi; 51251ff1725SRam Amrani p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages; 51351ff1725SRam Amrani 51451ff1725SRam Amrani DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr, 51551ff1725SRam Amrani p_cnq_pbl_list->pbl_ptr); 51651ff1725SRam Amrani 51751ff1725SRam Amrani /* we assume here that cnq_id and qz_offset are the same */ 51851ff1725SRam Amrani p_cnq_params->queue_zone_num = 51951ff1725SRam Amrani cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base + 52051ff1725SRam Amrani cnq_id); 52151ff1725SRam Amrani } 52251ff1725SRam Amrani 52351ff1725SRam Amrani return qed_spq_post(p_hwfn, p_ent, NULL); 52451ff1725SRam Amrani } 52551ff1725SRam Amrani 5260189efb8SYuval Mintz static int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid) 5270189efb8SYuval Mintz { 5280189efb8SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 5290189efb8SYuval Mintz int rc; 5300189efb8SYuval Mintz 5310189efb8SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n"); 5320189efb8SYuval Mintz 5330189efb8SYuval Mintz spin_lock_bh(&p_hwfn->p_rdma_info->lock); 5340189efb8SYuval Mintz rc = qed_rdma_bmap_alloc_id(p_hwfn, 5350189efb8SYuval Mintz &p_hwfn->p_rdma_info->tid_map, itid); 5360189efb8SYuval Mintz spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 5370189efb8SYuval Mintz if (rc) 5380189efb8SYuval Mintz goto out; 5390189efb8SYuval Mintz 5400189efb8SYuval Mintz rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid); 5410189efb8SYuval Mintz out: 5420189efb8SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc); 5430189efb8SYuval Mintz return rc; 5440189efb8SYuval Mintz } 5450189efb8SYuval Mintz 54651ff1725SRam Amrani static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn) 54751ff1725SRam Amrani { 54851ff1725SRam Amrani struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 54951ff1725SRam Amrani 55051ff1725SRam Amrani /* The first DPI is reserved for the Kernel */ 55151ff1725SRam Amrani __set_bit(0, p_hwfn->p_rdma_info->dpi_map.bitmap); 55251ff1725SRam Amrani 55351ff1725SRam Amrani /* Tid 0 will be used as the key for "reserved MR". 55451ff1725SRam Amrani * The driver should allocate memory for it so it can be loaded but no 55551ff1725SRam Amrani * ramrod should be passed on it. 55651ff1725SRam Amrani */ 55751ff1725SRam Amrani qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey); 55851ff1725SRam Amrani if (dev->reserved_lkey != RDMA_RESERVED_LKEY) { 55951ff1725SRam Amrani DP_NOTICE(p_hwfn, 56051ff1725SRam Amrani "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n"); 56151ff1725SRam Amrani return -EINVAL; 56251ff1725SRam Amrani } 56351ff1725SRam Amrani 56451ff1725SRam Amrani return 0; 56551ff1725SRam Amrani } 56651ff1725SRam Amrani 56751ff1725SRam Amrani static int qed_rdma_setup(struct qed_hwfn *p_hwfn, 56851ff1725SRam Amrani struct qed_ptt *p_ptt, 56951ff1725SRam Amrani struct qed_rdma_start_in_params *params) 57051ff1725SRam Amrani { 57151ff1725SRam Amrani int rc; 57251ff1725SRam Amrani 57351ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n"); 57451ff1725SRam Amrani 57551ff1725SRam Amrani spin_lock_init(&p_hwfn->p_rdma_info->lock); 57651ff1725SRam Amrani 57751ff1725SRam Amrani qed_rdma_init_devinfo(p_hwfn, params); 57851ff1725SRam Amrani qed_rdma_init_port(p_hwfn); 57951ff1725SRam Amrani qed_rdma_init_events(p_hwfn, params); 58051ff1725SRam Amrani 58151ff1725SRam Amrani rc = qed_rdma_reserve_lkey(p_hwfn); 58251ff1725SRam Amrani if (rc) 58351ff1725SRam Amrani return rc; 58451ff1725SRam Amrani 58551ff1725SRam Amrani rc = qed_rdma_init_hw(p_hwfn, p_ptt); 58651ff1725SRam Amrani if (rc) 58751ff1725SRam Amrani return rc; 58851ff1725SRam Amrani 58951ff1725SRam Amrani return qed_rdma_start_fw(p_hwfn, params, p_ptt); 59051ff1725SRam Amrani } 59151ff1725SRam Amrani 5920189efb8SYuval Mintz static int qed_rdma_stop(void *rdma_cxt) 59351ff1725SRam Amrani { 59451ff1725SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 59551ff1725SRam Amrani struct rdma_close_func_ramrod_data *p_ramrod; 59651ff1725SRam Amrani struct qed_sp_init_data init_data; 59751ff1725SRam Amrani struct qed_spq_entry *p_ent; 59851ff1725SRam Amrani struct qed_ptt *p_ptt; 59951ff1725SRam Amrani u32 ll2_ethertype_en; 60051ff1725SRam Amrani int rc = -EBUSY; 60151ff1725SRam Amrani 60251ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n"); 60351ff1725SRam Amrani 60451ff1725SRam Amrani p_ptt = qed_ptt_acquire(p_hwfn); 60551ff1725SRam Amrani if (!p_ptt) { 60651ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n"); 60751ff1725SRam Amrani return rc; 60851ff1725SRam Amrani } 60951ff1725SRam Amrani 61051ff1725SRam Amrani /* Disable RoCE search */ 61151ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0); 61251ff1725SRam Amrani p_hwfn->b_rdma_enabled_in_prs = false; 61351ff1725SRam Amrani 61451ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 61551ff1725SRam Amrani 61651ff1725SRam Amrani ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 61751ff1725SRam Amrani 61851ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 61951ff1725SRam Amrani (ll2_ethertype_en & 0xFFFE)); 62051ff1725SRam Amrani 62151ff1725SRam Amrani qed_ptt_release(p_hwfn, p_ptt); 62251ff1725SRam Amrani 62351ff1725SRam Amrani /* Get SPQ entry */ 62451ff1725SRam Amrani memset(&init_data, 0, sizeof(init_data)); 62551ff1725SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 62651ff1725SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 62751ff1725SRam Amrani 62851ff1725SRam Amrani /* Stop RoCE */ 62951ff1725SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE, 63051ff1725SRam Amrani p_hwfn->p_rdma_info->proto, &init_data); 63151ff1725SRam Amrani if (rc) 63251ff1725SRam Amrani goto out; 63351ff1725SRam Amrani 63451ff1725SRam Amrani p_ramrod = &p_ent->ramrod.rdma_close_func; 63551ff1725SRam Amrani 63651ff1725SRam Amrani p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs; 63751ff1725SRam Amrani p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM); 63851ff1725SRam Amrani 63951ff1725SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 64051ff1725SRam Amrani 64151ff1725SRam Amrani out: 64251ff1725SRam Amrani qed_rdma_free(p_hwfn); 64351ff1725SRam Amrani 64451ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc); 64551ff1725SRam Amrani return rc; 64651ff1725SRam Amrani } 64751ff1725SRam Amrani 6480189efb8SYuval Mintz static int qed_rdma_add_user(void *rdma_cxt, 64951ff1725SRam Amrani struct qed_rdma_add_user_out_params *out_params) 65051ff1725SRam Amrani { 65151ff1725SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 65251ff1725SRam Amrani u32 dpi_start_offset; 65351ff1725SRam Amrani u32 returned_id = 0; 65451ff1725SRam Amrani int rc; 65551ff1725SRam Amrani 65651ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n"); 65751ff1725SRam Amrani 65851ff1725SRam Amrani /* Allocate DPI */ 65951ff1725SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 66051ff1725SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 66151ff1725SRam Amrani &returned_id); 66251ff1725SRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 66351ff1725SRam Amrani 66451ff1725SRam Amrani out_params->dpi = (u16)returned_id; 66551ff1725SRam Amrani 66651ff1725SRam Amrani /* Calculate the corresponding DPI address */ 66751ff1725SRam Amrani dpi_start_offset = p_hwfn->dpi_start_offset; 66851ff1725SRam Amrani 66951ff1725SRam Amrani out_params->dpi_addr = (u64)((u8 __iomem *)p_hwfn->doorbells + 67051ff1725SRam Amrani dpi_start_offset + 67151ff1725SRam Amrani ((out_params->dpi) * p_hwfn->dpi_size)); 67251ff1725SRam Amrani 67351ff1725SRam Amrani out_params->dpi_phys_addr = p_hwfn->cdev->db_phys_addr + 67451ff1725SRam Amrani dpi_start_offset + 67551ff1725SRam Amrani ((out_params->dpi) * p_hwfn->dpi_size); 67651ff1725SRam Amrani 67751ff1725SRam Amrani out_params->dpi_size = p_hwfn->dpi_size; 67851ff1725SRam Amrani 67951ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc); 68051ff1725SRam Amrani return rc; 68151ff1725SRam Amrani } 68251ff1725SRam Amrani 6830189efb8SYuval Mintz static struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt) 684c295f86eSRam Amrani { 685c295f86eSRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 686c295f86eSRam Amrani struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port; 687c295f86eSRam Amrani 688c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n"); 689c295f86eSRam Amrani 690c295f86eSRam Amrani /* Link may have changed */ 691c295f86eSRam Amrani p_port->port_state = p_hwfn->mcp_info->link_output.link_up ? 692c295f86eSRam Amrani QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN; 693c295f86eSRam Amrani 694c295f86eSRam Amrani p_port->link_speed = p_hwfn->mcp_info->link_output.speed; 695c295f86eSRam Amrani 696c295f86eSRam Amrani return p_port; 697c295f86eSRam Amrani } 698c295f86eSRam Amrani 6990189efb8SYuval Mintz static struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt) 70051ff1725SRam Amrani { 70151ff1725SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 70251ff1725SRam Amrani 70351ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n"); 70451ff1725SRam Amrani 70551ff1725SRam Amrani /* Return struct with device parameters */ 70651ff1725SRam Amrani return p_hwfn->p_rdma_info->dev; 70751ff1725SRam Amrani } 70851ff1725SRam Amrani 7090189efb8SYuval Mintz static void qed_rdma_free_tid(void *rdma_cxt, u32 itid) 710ee8eaea3SRam Amrani { 711ee8eaea3SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 712ee8eaea3SRam Amrani 713ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 714ee8eaea3SRam Amrani 715ee8eaea3SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 716ee8eaea3SRam Amrani qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->tid_map, itid); 717ee8eaea3SRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 718ee8eaea3SRam Amrani } 719ee8eaea3SRam Amrani 7200189efb8SYuval Mintz static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod) 72151ff1725SRam Amrani { 72251ff1725SRam Amrani struct qed_hwfn *p_hwfn; 72351ff1725SRam Amrani u16 qz_num; 72451ff1725SRam Amrani u32 addr; 72551ff1725SRam Amrani 72651ff1725SRam Amrani p_hwfn = (struct qed_hwfn *)rdma_cxt; 72751ff1725SRam Amrani qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset; 72851ff1725SRam Amrani addr = GTT_BAR0_MAP_REG_USDM_RAM + 72951ff1725SRam Amrani USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num); 73051ff1725SRam Amrani 73151ff1725SRam Amrani REG_WR16(p_hwfn, addr, prod); 73251ff1725SRam Amrani 73351ff1725SRam Amrani /* keep prod updates ordered */ 73451ff1725SRam Amrani wmb(); 73551ff1725SRam Amrani } 73651ff1725SRam Amrani 73751ff1725SRam Amrani static int qed_fill_rdma_dev_info(struct qed_dev *cdev, 73851ff1725SRam Amrani struct qed_dev_rdma_info *info) 73951ff1725SRam Amrani { 74051ff1725SRam Amrani memset(info, 0, sizeof(*info)); 74151ff1725SRam Amrani 74251ff1725SRam Amrani info->rdma_type = QED_RDMA_TYPE_ROCE; 74351ff1725SRam Amrani 74451ff1725SRam Amrani qed_fill_dev_info(cdev, &info->common); 74551ff1725SRam Amrani 74651ff1725SRam Amrani return 0; 74751ff1725SRam Amrani } 74851ff1725SRam Amrani 74951ff1725SRam Amrani static int qed_rdma_get_sb_start(struct qed_dev *cdev) 75051ff1725SRam Amrani { 75151ff1725SRam Amrani int feat_num; 75251ff1725SRam Amrani 75351ff1725SRam Amrani if (cdev->num_hwfns > 1) 75451ff1725SRam Amrani feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE); 75551ff1725SRam Amrani else 75651ff1725SRam Amrani feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE) * 75751ff1725SRam Amrani cdev->num_hwfns; 75851ff1725SRam Amrani 75951ff1725SRam Amrani return feat_num; 76051ff1725SRam Amrani } 76151ff1725SRam Amrani 76251ff1725SRam Amrani static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev) 76351ff1725SRam Amrani { 76451ff1725SRam Amrani int n_cnq = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_RDMA_CNQ); 76551ff1725SRam Amrani int n_msix = cdev->int_params.rdma_msix_cnt; 76651ff1725SRam Amrani 76751ff1725SRam Amrani return min_t(int, n_cnq, n_msix); 76851ff1725SRam Amrani } 76951ff1725SRam Amrani 77051ff1725SRam Amrani static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt) 77151ff1725SRam Amrani { 77251ff1725SRam Amrani int limit = 0; 77351ff1725SRam Amrani 77451ff1725SRam Amrani /* Mark the fastpath as free/used */ 77551ff1725SRam Amrani cdev->int_params.fp_initialized = cnt ? true : false; 77651ff1725SRam Amrani 77751ff1725SRam Amrani if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) { 77851ff1725SRam Amrani DP_ERR(cdev, 77951ff1725SRam Amrani "qed roce supports only MSI-X interrupts (detected %d).\n", 78051ff1725SRam Amrani cdev->int_params.out.int_mode); 78151ff1725SRam Amrani return -EINVAL; 78251ff1725SRam Amrani } else if (cdev->int_params.fp_msix_cnt) { 78351ff1725SRam Amrani limit = cdev->int_params.rdma_msix_cnt; 78451ff1725SRam Amrani } 78551ff1725SRam Amrani 78651ff1725SRam Amrani if (!limit) 78751ff1725SRam Amrani return -ENOMEM; 78851ff1725SRam Amrani 78951ff1725SRam Amrani return min_t(int, cnt, limit); 79051ff1725SRam Amrani } 79151ff1725SRam Amrani 79251ff1725SRam Amrani static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info) 79351ff1725SRam Amrani { 79451ff1725SRam Amrani memset(info, 0, sizeof(*info)); 79551ff1725SRam Amrani 79651ff1725SRam Amrani if (!cdev->int_params.fp_initialized) { 79751ff1725SRam Amrani DP_INFO(cdev, 79851ff1725SRam Amrani "Protocol driver requested interrupt information, but its support is not yet configured\n"); 79951ff1725SRam Amrani return -EINVAL; 80051ff1725SRam Amrani } 80151ff1725SRam Amrani 80251ff1725SRam Amrani if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 80351ff1725SRam Amrani int msix_base = cdev->int_params.rdma_msix_base; 80451ff1725SRam Amrani 80551ff1725SRam Amrani info->msix_cnt = cdev->int_params.rdma_msix_cnt; 80651ff1725SRam Amrani info->msix = &cdev->int_params.msix_table[msix_base]; 80751ff1725SRam Amrani 80851ff1725SRam Amrani DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n", 80951ff1725SRam Amrani info->msix_cnt, msix_base); 81051ff1725SRam Amrani } 81151ff1725SRam Amrani 81251ff1725SRam Amrani return 0; 81351ff1725SRam Amrani } 81451ff1725SRam Amrani 8150189efb8SYuval Mintz static int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd) 816c295f86eSRam Amrani { 817c295f86eSRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 818c295f86eSRam Amrani u32 returned_id; 819c295f86eSRam Amrani int rc; 820c295f86eSRam Amrani 821c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n"); 822c295f86eSRam Amrani 823c295f86eSRam Amrani /* Allocates an unused protection domain */ 824c295f86eSRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 825c295f86eSRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, 826c295f86eSRam Amrani &p_hwfn->p_rdma_info->pd_map, &returned_id); 827c295f86eSRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 828c295f86eSRam Amrani 829c295f86eSRam Amrani *pd = (u16)returned_id; 830c295f86eSRam Amrani 831c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc); 832c295f86eSRam Amrani return rc; 833c295f86eSRam Amrani } 834c295f86eSRam Amrani 8358c93beafSYuval Mintz static void qed_rdma_free_pd(void *rdma_cxt, u16 pd) 836c295f86eSRam Amrani { 837c295f86eSRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 838c295f86eSRam Amrani 839c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd); 840c295f86eSRam Amrani 841c295f86eSRam Amrani /* Returns a previously allocated protection domain for reuse */ 842c295f86eSRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 843c295f86eSRam Amrani qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd); 844c295f86eSRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 845c295f86eSRam Amrani } 846c295f86eSRam Amrani 847c295f86eSRam Amrani static enum qed_rdma_toggle_bit 848c295f86eSRam Amrani qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid) 849c295f86eSRam Amrani { 850c295f86eSRam Amrani struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 851c295f86eSRam Amrani enum qed_rdma_toggle_bit toggle_bit; 852c295f86eSRam Amrani u32 bmap_id; 853c295f86eSRam Amrani 854c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid); 855c295f86eSRam Amrani 856c295f86eSRam Amrani /* the function toggle the bit that is related to a given icid 857c295f86eSRam Amrani * and returns the new toggle bit's value 858c295f86eSRam Amrani */ 859c295f86eSRam Amrani bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto); 860c295f86eSRam Amrani 861c295f86eSRam Amrani spin_lock_bh(&p_info->lock); 862c295f86eSRam Amrani toggle_bit = !test_and_change_bit(bmap_id, 863c295f86eSRam Amrani p_info->toggle_bits.bitmap); 864c295f86eSRam Amrani spin_unlock_bh(&p_info->lock); 865c295f86eSRam Amrani 866c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n", 867c295f86eSRam Amrani toggle_bit); 868c295f86eSRam Amrani 869c295f86eSRam Amrani return toggle_bit; 870c295f86eSRam Amrani } 871c295f86eSRam Amrani 8728c93beafSYuval Mintz static int qed_rdma_create_cq(void *rdma_cxt, 8738c93beafSYuval Mintz struct qed_rdma_create_cq_in_params *params, 8748c93beafSYuval Mintz u16 *icid) 875c295f86eSRam Amrani { 876c295f86eSRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 877c295f86eSRam Amrani struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 878c295f86eSRam Amrani struct rdma_create_cq_ramrod_data *p_ramrod; 879c295f86eSRam Amrani enum qed_rdma_toggle_bit toggle_bit; 880c295f86eSRam Amrani struct qed_sp_init_data init_data; 881c295f86eSRam Amrani struct qed_spq_entry *p_ent; 882c295f86eSRam Amrani u32 returned_id, start_cid; 883c295f86eSRam Amrani int rc; 884c295f86eSRam Amrani 885c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n", 886c295f86eSRam Amrani params->cq_handle_hi, params->cq_handle_lo); 887c295f86eSRam Amrani 888c295f86eSRam Amrani /* Allocate icid */ 889c295f86eSRam Amrani spin_lock_bh(&p_info->lock); 890c295f86eSRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, 891c295f86eSRam Amrani &p_info->cq_map, &returned_id); 892c295f86eSRam Amrani spin_unlock_bh(&p_info->lock); 893c295f86eSRam Amrani 894c295f86eSRam Amrani if (rc) { 895c295f86eSRam Amrani DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc); 896c295f86eSRam Amrani return rc; 897c295f86eSRam Amrani } 898c295f86eSRam Amrani 899c295f86eSRam Amrani start_cid = qed_cxt_get_proto_cid_start(p_hwfn, 900c295f86eSRam Amrani p_info->proto); 901c295f86eSRam Amrani *icid = returned_id + start_cid; 902c295f86eSRam Amrani 903c295f86eSRam Amrani /* Check if icid requires a page allocation */ 904c295f86eSRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid); 905c295f86eSRam Amrani if (rc) 906c295f86eSRam Amrani goto err; 907c295f86eSRam Amrani 908c295f86eSRam Amrani /* Get SPQ entry */ 909c295f86eSRam Amrani memset(&init_data, 0, sizeof(init_data)); 910c295f86eSRam Amrani init_data.cid = *icid; 911c295f86eSRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 912c295f86eSRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 913c295f86eSRam Amrani 914c295f86eSRam Amrani /* Send create CQ ramrod */ 915c295f86eSRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 916c295f86eSRam Amrani RDMA_RAMROD_CREATE_CQ, 917c295f86eSRam Amrani p_info->proto, &init_data); 918c295f86eSRam Amrani if (rc) 919c295f86eSRam Amrani goto err; 920c295f86eSRam Amrani 921c295f86eSRam Amrani p_ramrod = &p_ent->ramrod.rdma_create_cq; 922c295f86eSRam Amrani 923c295f86eSRam Amrani p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi); 924c295f86eSRam Amrani p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo); 925c295f86eSRam Amrani p_ramrod->dpi = cpu_to_le16(params->dpi); 926c295f86eSRam Amrani p_ramrod->is_two_level_pbl = params->pbl_two_level; 927c295f86eSRam Amrani p_ramrod->max_cqes = cpu_to_le32(params->cq_size); 928c295f86eSRam Amrani DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr); 929c295f86eSRam Amrani p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages); 930c295f86eSRam Amrani p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) + 931c295f86eSRam Amrani params->cnq_id; 932c295f86eSRam Amrani p_ramrod->int_timeout = params->int_timeout; 933c295f86eSRam Amrani 934c295f86eSRam Amrani /* toggle the bit for every resize or create cq for a given icid */ 935c295f86eSRam Amrani toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 936c295f86eSRam Amrani 937c295f86eSRam Amrani p_ramrod->toggle_bit = toggle_bit; 938c295f86eSRam Amrani 939c295f86eSRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 940c295f86eSRam Amrani if (rc) { 941c295f86eSRam Amrani /* restore toggle bit */ 942c295f86eSRam Amrani qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 943c295f86eSRam Amrani goto err; 944c295f86eSRam Amrani } 945c295f86eSRam Amrani 946c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc); 947c295f86eSRam Amrani return rc; 948c295f86eSRam Amrani 949c295f86eSRam Amrani err: 950c295f86eSRam Amrani /* release allocated icid */ 951670dde55SRam Amrani spin_lock_bh(&p_info->lock); 952c295f86eSRam Amrani qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id); 953670dde55SRam Amrani spin_unlock_bh(&p_info->lock); 954c295f86eSRam Amrani DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc); 955c295f86eSRam Amrani 956c295f86eSRam Amrani return rc; 957c295f86eSRam Amrani } 958c295f86eSRam Amrani 9598c93beafSYuval Mintz static int 9608c93beafSYuval Mintz qed_rdma_destroy_cq(void *rdma_cxt, 961c295f86eSRam Amrani struct qed_rdma_destroy_cq_in_params *in_params, 962c295f86eSRam Amrani struct qed_rdma_destroy_cq_out_params *out_params) 963c295f86eSRam Amrani { 964c295f86eSRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 965c295f86eSRam Amrani struct rdma_destroy_cq_output_params *p_ramrod_res; 966c295f86eSRam Amrani struct rdma_destroy_cq_ramrod_data *p_ramrod; 967c295f86eSRam Amrani struct qed_sp_init_data init_data; 968c295f86eSRam Amrani struct qed_spq_entry *p_ent; 969c295f86eSRam Amrani dma_addr_t ramrod_res_phys; 970c295f86eSRam Amrani int rc = -ENOMEM; 971c295f86eSRam Amrani 972c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid); 973c295f86eSRam Amrani 974c295f86eSRam Amrani p_ramrod_res = 975c295f86eSRam Amrani (struct rdma_destroy_cq_output_params *) 976c295f86eSRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 977c295f86eSRam Amrani sizeof(struct rdma_destroy_cq_output_params), 978c295f86eSRam Amrani &ramrod_res_phys, GFP_KERNEL); 979c295f86eSRam Amrani if (!p_ramrod_res) { 980c295f86eSRam Amrani DP_NOTICE(p_hwfn, 981c295f86eSRam Amrani "qed destroy cq failed: cannot allocate memory (ramrod)\n"); 982c295f86eSRam Amrani return rc; 983c295f86eSRam Amrani } 984c295f86eSRam Amrani 985c295f86eSRam Amrani /* Get SPQ entry */ 986c295f86eSRam Amrani memset(&init_data, 0, sizeof(init_data)); 987c295f86eSRam Amrani init_data.cid = in_params->icid; 988c295f86eSRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 989c295f86eSRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 990c295f86eSRam Amrani 991c295f86eSRam Amrani /* Send destroy CQ ramrod */ 992c295f86eSRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 993c295f86eSRam Amrani RDMA_RAMROD_DESTROY_CQ, 994c295f86eSRam Amrani p_hwfn->p_rdma_info->proto, &init_data); 995c295f86eSRam Amrani if (rc) 996c295f86eSRam Amrani goto err; 997c295f86eSRam Amrani 998c295f86eSRam Amrani p_ramrod = &p_ent->ramrod.rdma_destroy_cq; 999c295f86eSRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1000c295f86eSRam Amrani 1001c295f86eSRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1002c295f86eSRam Amrani if (rc) 1003c295f86eSRam Amrani goto err; 1004c295f86eSRam Amrani 1005c295f86eSRam Amrani out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num); 1006c295f86eSRam Amrani 1007c295f86eSRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1008c295f86eSRam Amrani sizeof(struct rdma_destroy_cq_output_params), 1009c295f86eSRam Amrani p_ramrod_res, ramrod_res_phys); 1010c295f86eSRam Amrani 1011c295f86eSRam Amrani /* Free icid */ 1012c295f86eSRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1013c295f86eSRam Amrani 1014c295f86eSRam Amrani qed_bmap_release_id(p_hwfn, 1015c295f86eSRam Amrani &p_hwfn->p_rdma_info->cq_map, 1016c295f86eSRam Amrani (in_params->icid - 1017c295f86eSRam Amrani qed_cxt_get_proto_cid_start(p_hwfn, 1018c295f86eSRam Amrani p_hwfn-> 1019c295f86eSRam Amrani p_rdma_info->proto))); 1020c295f86eSRam Amrani 1021c295f86eSRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1022c295f86eSRam Amrani 1023c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc); 1024c295f86eSRam Amrani return rc; 1025c295f86eSRam Amrani 1026c295f86eSRam Amrani err: dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1027c295f86eSRam Amrani sizeof(struct rdma_destroy_cq_output_params), 1028c295f86eSRam Amrani p_ramrod_res, ramrod_res_phys); 1029c295f86eSRam Amrani 1030c295f86eSRam Amrani return rc; 1031c295f86eSRam Amrani } 1032c295f86eSRam Amrani 1033f1093940SRam Amrani static void qed_rdma_set_fw_mac(u16 *p_fw_mac, u8 *p_qed_mac) 1034f1093940SRam Amrani { 1035f1093940SRam Amrani p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]); 1036f1093940SRam Amrani p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]); 1037f1093940SRam Amrani p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]); 1038f1093940SRam Amrani } 1039f1093940SRam Amrani 1040f1093940SRam Amrani static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid, 1041f1093940SRam Amrani __le32 *dst_gid) 1042f1093940SRam Amrani { 1043f1093940SRam Amrani u32 i; 1044f1093940SRam Amrani 1045f1093940SRam Amrani if (qp->roce_mode == ROCE_V2_IPV4) { 1046f1093940SRam Amrani /* The IPv4 addresses shall be aligned to the highest word. 1047f1093940SRam Amrani * The lower words must be zero. 1048f1093940SRam Amrani */ 1049f1093940SRam Amrani memset(src_gid, 0, sizeof(union qed_gid)); 1050f1093940SRam Amrani memset(dst_gid, 0, sizeof(union qed_gid)); 1051f1093940SRam Amrani src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr); 1052f1093940SRam Amrani dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr); 1053f1093940SRam Amrani } else { 1054f1093940SRam Amrani /* GIDs and IPv6 addresses coincide in location and size */ 1055f1093940SRam Amrani for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) { 1056f1093940SRam Amrani src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]); 1057f1093940SRam Amrani dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]); 1058f1093940SRam Amrani } 1059f1093940SRam Amrani } 1060f1093940SRam Amrani } 1061f1093940SRam Amrani 1062f1093940SRam Amrani static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode) 1063f1093940SRam Amrani { 1064f1093940SRam Amrani enum roce_flavor flavor; 1065f1093940SRam Amrani 1066f1093940SRam Amrani switch (roce_mode) { 1067f1093940SRam Amrani case ROCE_V1: 1068f1093940SRam Amrani flavor = PLAIN_ROCE; 1069f1093940SRam Amrani break; 1070f1093940SRam Amrani case ROCE_V2_IPV4: 1071f1093940SRam Amrani flavor = RROCE_IPV4; 1072f1093940SRam Amrani break; 1073f1093940SRam Amrani case ROCE_V2_IPV6: 1074f1093940SRam Amrani flavor = ROCE_V2_IPV6; 1075f1093940SRam Amrani break; 1076f1093940SRam Amrani default: 1077f1093940SRam Amrani flavor = MAX_ROCE_MODE; 1078f1093940SRam Amrani break; 1079f1093940SRam Amrani } 1080f1093940SRam Amrani return flavor; 1081f1093940SRam Amrani } 1082f1093940SRam Amrani 10838c93beafSYuval Mintz static int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid) 1084f1093940SRam Amrani { 1085f1093940SRam Amrani struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 1086f1093940SRam Amrani u32 responder_icid; 1087f1093940SRam Amrani u32 requester_icid; 1088f1093940SRam Amrani int rc; 1089f1093940SRam Amrani 1090f1093940SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1091f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 1092f1093940SRam Amrani &responder_icid); 1093f1093940SRam Amrani if (rc) { 1094f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 1095f1093940SRam Amrani return rc; 1096f1093940SRam Amrani } 1097f1093940SRam Amrani 1098f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 1099f1093940SRam Amrani &requester_icid); 1100f1093940SRam Amrani 1101f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 1102f1093940SRam Amrani if (rc) 1103f1093940SRam Amrani goto err; 1104f1093940SRam Amrani 1105f1093940SRam Amrani /* the two icid's should be adjacent */ 1106f1093940SRam Amrani if ((requester_icid - responder_icid) != 1) { 1107f1093940SRam Amrani DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n"); 1108f1093940SRam Amrani rc = -EINVAL; 1109f1093940SRam Amrani goto err; 1110f1093940SRam Amrani } 1111f1093940SRam Amrani 1112f1093940SRam Amrani responder_icid += qed_cxt_get_proto_cid_start(p_hwfn, 1113f1093940SRam Amrani p_rdma_info->proto); 1114f1093940SRam Amrani requester_icid += qed_cxt_get_proto_cid_start(p_hwfn, 1115f1093940SRam Amrani p_rdma_info->proto); 1116f1093940SRam Amrani 1117f1093940SRam Amrani /* If these icids require a new ILT line allocate DMA-able context for 1118f1093940SRam Amrani * an ILT page 1119f1093940SRam Amrani */ 1120f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid); 1121f1093940SRam Amrani if (rc) 1122f1093940SRam Amrani goto err; 1123f1093940SRam Amrani 1124f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid); 1125f1093940SRam Amrani if (rc) 1126f1093940SRam Amrani goto err; 1127f1093940SRam Amrani 1128f1093940SRam Amrani *cid = (u16)responder_icid; 1129f1093940SRam Amrani return rc; 1130f1093940SRam Amrani 1131f1093940SRam Amrani err: 1132f1093940SRam Amrani spin_lock_bh(&p_rdma_info->lock); 1133f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid); 1134f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid); 1135f1093940SRam Amrani 1136f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 1137f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1138f1093940SRam Amrani "Allocate CID - failed, rc = %d\n", rc); 1139f1093940SRam Amrani return rc; 1140f1093940SRam Amrani } 1141f1093940SRam Amrani 1142f1093940SRam Amrani static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn, 1143f1093940SRam Amrani struct qed_rdma_qp *qp) 1144f1093940SRam Amrani { 1145f1093940SRam Amrani struct roce_create_qp_resp_ramrod_data *p_ramrod; 1146f1093940SRam Amrani struct qed_sp_init_data init_data; 1147f1093940SRam Amrani union qed_qm_pq_params qm_params; 1148f1093940SRam Amrani enum roce_flavor roce_flavor; 1149f1093940SRam Amrani struct qed_spq_entry *p_ent; 1150f1093940SRam Amrani u16 physical_queue0 = 0; 1151f1093940SRam Amrani int rc; 1152f1093940SRam Amrani 1153f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1154f1093940SRam Amrani 1155f1093940SRam Amrani /* Allocate DMA-able memory for IRQ */ 1156f1093940SRam Amrani qp->irq_num_pages = 1; 1157f1093940SRam Amrani qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1158f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 1159f1093940SRam Amrani &qp->irq_phys_addr, GFP_KERNEL); 1160f1093940SRam Amrani if (!qp->irq) { 1161f1093940SRam Amrani rc = -ENOMEM; 1162f1093940SRam Amrani DP_NOTICE(p_hwfn, 1163f1093940SRam Amrani "qed create responder failed: cannot allocate memory (irq). rc = %d\n", 1164f1093940SRam Amrani rc); 1165f1093940SRam Amrani return rc; 1166f1093940SRam Amrani } 1167f1093940SRam Amrani 1168f1093940SRam Amrani /* Get SPQ entry */ 1169f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1170f1093940SRam Amrani init_data.cid = qp->icid; 1171f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1172f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1173f1093940SRam Amrani 1174f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP, 1175f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1176f1093940SRam Amrani if (rc) 1177f1093940SRam Amrani goto err; 1178f1093940SRam Amrani 1179f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_resp; 1180f1093940SRam Amrani 1181f1093940SRam Amrani p_ramrod->flags = 0; 1182f1093940SRam Amrani 1183f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 1184f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1185f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 1186f1093940SRam Amrani 1187f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1188f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 1189f1093940SRam Amrani qp->incoming_rdma_read_en); 1190f1093940SRam Amrani 1191f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1192f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 1193f1093940SRam Amrani qp->incoming_rdma_write_en); 1194f1093940SRam Amrani 1195f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1196f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN, 1197f1093940SRam Amrani qp->incoming_atomic_en); 1198f1093940SRam Amrani 1199f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1200f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 1201f1093940SRam Amrani qp->e2e_flow_control_en); 1202f1093940SRam Amrani 1203f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1204f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq); 1205f1093940SRam Amrani 1206f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1207f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN, 1208f1093940SRam Amrani qp->fmr_and_reserved_lkey); 1209f1093940SRam Amrani 1210f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1211f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 1212f1093940SRam Amrani qp->min_rnr_nak_timer); 1213f1093940SRam Amrani 1214f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 1215f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 1216f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 1217f1093940SRam Amrani p_ramrod->irq_num_pages = qp->irq_num_pages; 1218f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 1219f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1220f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 1221f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 1222f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn); 1223f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 1224f1093940SRam Amrani p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages); 1225f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr); 1226f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr); 1227f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1228f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 1229f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 1230f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 1231f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 1232f1093940SRam Amrani p_ramrod->stats_counter_id = p_hwfn->rel_pf_id; 1233f1093940SRam Amrani p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 1234f1093940SRam Amrani qp->rq_cq_id); 1235f1093940SRam Amrani 1236f1093940SRam Amrani memset(&qm_params, 0, sizeof(qm_params)); 1237f1093940SRam Amrani qm_params.roce.qpid = qp->icid >> 1; 1238f1093940SRam Amrani physical_queue0 = qed_get_qm_pq(p_hwfn, PROTOCOLID_ROCE, &qm_params); 1239f1093940SRam Amrani 1240f1093940SRam Amrani p_ramrod->physical_queue0 = cpu_to_le16(physical_queue0); 1241f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 1242f1093940SRam Amrani 1243f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 1244f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 1245f1093940SRam Amrani 1246f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 1247f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 1248f1093940SRam Amrani p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id); 1249f1093940SRam Amrani p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid); 1250f1093940SRam Amrani 1251f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 1252f1093940SRam Amrani qp->stats_queue; 1253f1093940SRam Amrani 1254f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1255f1093940SRam Amrani 1256f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d physical_queue0 = 0x%x\n", 1257f1093940SRam Amrani rc, physical_queue0); 1258f1093940SRam Amrani 1259f1093940SRam Amrani if (rc) 1260f1093940SRam Amrani goto err; 1261f1093940SRam Amrani 1262f1093940SRam Amrani qp->resp_offloaded = true; 1263f1093940SRam Amrani 1264f1093940SRam Amrani return rc; 1265f1093940SRam Amrani 1266f1093940SRam Amrani err: 1267f1093940SRam Amrani DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc); 1268f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1269f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 1270f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 1271f1093940SRam Amrani 1272f1093940SRam Amrani return rc; 1273f1093940SRam Amrani } 1274f1093940SRam Amrani 1275f1093940SRam Amrani static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn, 1276f1093940SRam Amrani struct qed_rdma_qp *qp) 1277f1093940SRam Amrani { 1278f1093940SRam Amrani struct roce_create_qp_req_ramrod_data *p_ramrod; 1279f1093940SRam Amrani struct qed_sp_init_data init_data; 1280f1093940SRam Amrani union qed_qm_pq_params qm_params; 1281f1093940SRam Amrani enum roce_flavor roce_flavor; 1282f1093940SRam Amrani struct qed_spq_entry *p_ent; 1283f1093940SRam Amrani u16 physical_queue0 = 0; 1284f1093940SRam Amrani int rc; 1285f1093940SRam Amrani 1286f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1287f1093940SRam Amrani 1288f1093940SRam Amrani /* Allocate DMA-able memory for ORQ */ 1289f1093940SRam Amrani qp->orq_num_pages = 1; 1290f1093940SRam Amrani qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1291f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 1292f1093940SRam Amrani &qp->orq_phys_addr, GFP_KERNEL); 1293f1093940SRam Amrani if (!qp->orq) { 1294f1093940SRam Amrani rc = -ENOMEM; 1295f1093940SRam Amrani DP_NOTICE(p_hwfn, 1296f1093940SRam Amrani "qed create requester failed: cannot allocate memory (orq). rc = %d\n", 1297f1093940SRam Amrani rc); 1298f1093940SRam Amrani return rc; 1299f1093940SRam Amrani } 1300f1093940SRam Amrani 1301f1093940SRam Amrani /* Get SPQ entry */ 1302f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1303f1093940SRam Amrani init_data.cid = qp->icid + 1; 1304f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1305f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1306f1093940SRam Amrani 1307f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 1308f1093940SRam Amrani ROCE_RAMROD_CREATE_QP, 1309f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1310f1093940SRam Amrani if (rc) 1311f1093940SRam Amrani goto err; 1312f1093940SRam Amrani 1313f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_req; 1314f1093940SRam Amrani 1315f1093940SRam Amrani p_ramrod->flags = 0; 1316f1093940SRam Amrani 1317f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 1318f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1319f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 1320f1093940SRam Amrani 1321f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1322f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN, 1323f1093940SRam Amrani qp->fmr_and_reserved_lkey); 1324f1093940SRam Amrani 1325f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1326f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all); 1327f1093940SRam Amrani 1328f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1329f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 1330f1093940SRam Amrani 1331f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1332f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 1333f1093940SRam Amrani qp->rnr_retry_cnt); 1334f1093940SRam Amrani 1335f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 1336f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 1337f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 1338f1093940SRam Amrani p_ramrod->orq_num_pages = qp->orq_num_pages; 1339f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 1340f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1341f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 1342f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 1343f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 1344f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn); 1345f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 1346f1093940SRam Amrani p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages); 1347f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr); 1348f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr); 1349f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1350f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 1351f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 1352f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 1353f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 1354f1093940SRam Amrani p_ramrod->stats_counter_id = p_hwfn->rel_pf_id; 1355f1093940SRam Amrani p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 1356f1093940SRam Amrani qp->sq_cq_id); 1357f1093940SRam Amrani 1358f1093940SRam Amrani memset(&qm_params, 0, sizeof(qm_params)); 1359f1093940SRam Amrani qm_params.roce.qpid = qp->icid >> 1; 1360f1093940SRam Amrani physical_queue0 = qed_get_qm_pq(p_hwfn, PROTOCOLID_ROCE, &qm_params); 1361f1093940SRam Amrani 1362f1093940SRam Amrani p_ramrod->physical_queue0 = cpu_to_le16(physical_queue0); 1363f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 1364f1093940SRam Amrani 1365f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 1366f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 1367f1093940SRam Amrani 1368f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 1369f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 1370f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 1371f1093940SRam Amrani qp->stats_queue; 1372f1093940SRam Amrani 1373f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1374f1093940SRam Amrani 1375f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1376f1093940SRam Amrani 1377f1093940SRam Amrani if (rc) 1378f1093940SRam Amrani goto err; 1379f1093940SRam Amrani 1380f1093940SRam Amrani qp->req_offloaded = true; 1381f1093940SRam Amrani 1382f1093940SRam Amrani return rc; 1383f1093940SRam Amrani 1384f1093940SRam Amrani err: 1385f1093940SRam Amrani DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc); 1386f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1387f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 1388f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 1389f1093940SRam Amrani return rc; 1390f1093940SRam Amrani } 1391f1093940SRam Amrani 1392f1093940SRam Amrani static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn, 1393f1093940SRam Amrani struct qed_rdma_qp *qp, 1394f1093940SRam Amrani bool move_to_err, u32 modify_flags) 1395f1093940SRam Amrani { 1396f1093940SRam Amrani struct roce_modify_qp_resp_ramrod_data *p_ramrod; 1397f1093940SRam Amrani struct qed_sp_init_data init_data; 1398f1093940SRam Amrani struct qed_spq_entry *p_ent; 1399f1093940SRam Amrani int rc; 1400f1093940SRam Amrani 1401f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1402f1093940SRam Amrani 1403f1093940SRam Amrani if (move_to_err && !qp->resp_offloaded) 1404f1093940SRam Amrani return 0; 1405f1093940SRam Amrani 1406f1093940SRam Amrani /* Get SPQ entry */ 1407f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1408f1093940SRam Amrani init_data.cid = qp->icid; 1409f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1410f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1411f1093940SRam Amrani 1412f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 1413f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 1414f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1415f1093940SRam Amrani if (rc) { 1416f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 1417f1093940SRam Amrani return rc; 1418f1093940SRam Amrani } 1419f1093940SRam Amrani 1420f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_resp; 1421f1093940SRam Amrani 1422f1093940SRam Amrani p_ramrod->flags = 0; 1423f1093940SRam Amrani 1424f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1425f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 1426f1093940SRam Amrani 1427f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1428f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 1429f1093940SRam Amrani qp->incoming_rdma_read_en); 1430f1093940SRam Amrani 1431f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1432f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 1433f1093940SRam Amrani qp->incoming_rdma_write_en); 1434f1093940SRam Amrani 1435f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1436f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN, 1437f1093940SRam Amrani qp->incoming_atomic_en); 1438f1093940SRam Amrani 1439f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1440f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 1441f1093940SRam Amrani qp->e2e_flow_control_en); 1442f1093940SRam Amrani 1443f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1444f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG, 1445f1093940SRam Amrani GET_FIELD(modify_flags, 1446f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)); 1447f1093940SRam Amrani 1448f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1449f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG, 1450f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 1451f1093940SRam Amrani 1452f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1453f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG, 1454f1093940SRam Amrani GET_FIELD(modify_flags, 1455f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 1456f1093940SRam Amrani 1457f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1458f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG, 1459f1093940SRam Amrani GET_FIELD(modify_flags, 1460f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)); 1461f1093940SRam Amrani 1462f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1463f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG, 1464f1093940SRam Amrani GET_FIELD(modify_flags, 1465f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)); 1466f1093940SRam Amrani 1467f1093940SRam Amrani p_ramrod->fields = 0; 1468f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 1469f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 1470f1093940SRam Amrani qp->min_rnr_nak_timer); 1471f1093940SRam Amrani 1472f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 1473f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 1474f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 1475f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 1476f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1477f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 1478f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1479f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1480f1093940SRam Amrani 1481f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc); 1482f1093940SRam Amrani return rc; 1483f1093940SRam Amrani } 1484f1093940SRam Amrani 1485f1093940SRam Amrani static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn, 1486f1093940SRam Amrani struct qed_rdma_qp *qp, 1487f1093940SRam Amrani bool move_to_sqd, 1488f1093940SRam Amrani bool move_to_err, u32 modify_flags) 1489f1093940SRam Amrani { 1490f1093940SRam Amrani struct roce_modify_qp_req_ramrod_data *p_ramrod; 1491f1093940SRam Amrani struct qed_sp_init_data init_data; 1492f1093940SRam Amrani struct qed_spq_entry *p_ent; 1493f1093940SRam Amrani int rc; 1494f1093940SRam Amrani 1495f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1496f1093940SRam Amrani 1497f1093940SRam Amrani if (move_to_err && !(qp->req_offloaded)) 1498f1093940SRam Amrani return 0; 1499f1093940SRam Amrani 1500f1093940SRam Amrani /* Get SPQ entry */ 1501f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1502f1093940SRam Amrani init_data.cid = qp->icid + 1; 1503f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1504f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1505f1093940SRam Amrani 1506f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 1507f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 1508f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1509f1093940SRam Amrani if (rc) { 1510f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 1511f1093940SRam Amrani return rc; 1512f1093940SRam Amrani } 1513f1093940SRam Amrani 1514f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_req; 1515f1093940SRam Amrani 1516f1093940SRam Amrani p_ramrod->flags = 0; 1517f1093940SRam Amrani 1518f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1519f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 1520f1093940SRam Amrani 1521f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1522f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd); 1523f1093940SRam Amrani 1524f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1525f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY, 1526f1093940SRam Amrani qp->sqd_async); 1527f1093940SRam Amrani 1528f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1529f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG, 1530f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 1531f1093940SRam Amrani 1532f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1533f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG, 1534f1093940SRam Amrani GET_FIELD(modify_flags, 1535f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 1536f1093940SRam Amrani 1537f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1538f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG, 1539f1093940SRam Amrani GET_FIELD(modify_flags, 1540f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)); 1541f1093940SRam Amrani 1542f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1543f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG, 1544f1093940SRam Amrani GET_FIELD(modify_flags, 1545f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)); 1546f1093940SRam Amrani 1547f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1548f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG, 1549f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)); 1550f1093940SRam Amrani 1551f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1552f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG, 1553f1093940SRam Amrani GET_FIELD(modify_flags, 1554f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)); 1555f1093940SRam Amrani 1556f1093940SRam Amrani p_ramrod->fields = 0; 1557f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 1558f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 1559f1093940SRam Amrani 1560f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 1561f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 1562f1093940SRam Amrani qp->rnr_retry_cnt); 1563f1093940SRam Amrani 1564f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 1565f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 1566f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 1567f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 1568f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1569f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 1570f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 1571f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1572f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1573f1093940SRam Amrani 1574f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc); 1575f1093940SRam Amrani return rc; 1576f1093940SRam Amrani } 1577f1093940SRam Amrani 1578f1093940SRam Amrani static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn, 1579f1093940SRam Amrani struct qed_rdma_qp *qp, 1580f1093940SRam Amrani u32 *num_invalidated_mw) 1581f1093940SRam Amrani { 1582f1093940SRam Amrani struct roce_destroy_qp_resp_output_params *p_ramrod_res; 1583f1093940SRam Amrani struct roce_destroy_qp_resp_ramrod_data *p_ramrod; 1584f1093940SRam Amrani struct qed_sp_init_data init_data; 1585f1093940SRam Amrani struct qed_spq_entry *p_ent; 1586f1093940SRam Amrani dma_addr_t ramrod_res_phys; 1587f1093940SRam Amrani int rc; 1588f1093940SRam Amrani 1589f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1590f1093940SRam Amrani 1591f1093940SRam Amrani if (!qp->resp_offloaded) 1592f1093940SRam Amrani return 0; 1593f1093940SRam Amrani 1594f1093940SRam Amrani /* Get SPQ entry */ 1595f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1596f1093940SRam Amrani init_data.cid = qp->icid; 1597f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1598f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1599f1093940SRam Amrani 1600f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 1601f1093940SRam Amrani ROCE_RAMROD_DESTROY_QP, 1602f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1603f1093940SRam Amrani if (rc) 1604f1093940SRam Amrani return rc; 1605f1093940SRam Amrani 1606f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp; 1607f1093940SRam Amrani 1608f1093940SRam Amrani p_ramrod_res = (struct roce_destroy_qp_resp_output_params *) 1609f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 1610f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 1611f1093940SRam Amrani 1612f1093940SRam Amrani if (!p_ramrod_res) { 1613f1093940SRam Amrani rc = -ENOMEM; 1614f1093940SRam Amrani DP_NOTICE(p_hwfn, 1615f1093940SRam Amrani "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n", 1616f1093940SRam Amrani rc); 1617f1093940SRam Amrani return rc; 1618f1093940SRam Amrani } 1619f1093940SRam Amrani 1620f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1621f1093940SRam Amrani 1622f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1623f1093940SRam Amrani if (rc) 1624f1093940SRam Amrani goto err; 1625f1093940SRam Amrani 1626f1093940SRam Amrani *num_invalidated_mw = le32_to_cpu(p_ramrod_res->num_invalidated_mw); 1627f1093940SRam Amrani 1628f1093940SRam Amrani /* Free IRQ - only if ramrod succeeded, in case FW is still using it */ 1629f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1630f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 1631f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 1632f1093940SRam Amrani 1633f1093940SRam Amrani qp->resp_offloaded = false; 1634f1093940SRam Amrani 1635f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc); 1636f1093940SRam Amrani 1637f1093940SRam Amrani err: 1638f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1639f1093940SRam Amrani sizeof(struct roce_destroy_qp_resp_output_params), 1640f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 1641f1093940SRam Amrani 1642f1093940SRam Amrani return rc; 1643f1093940SRam Amrani } 1644f1093940SRam Amrani 1645f1093940SRam Amrani static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn, 1646f1093940SRam Amrani struct qed_rdma_qp *qp, 1647f1093940SRam Amrani u32 *num_bound_mw) 1648f1093940SRam Amrani { 1649f1093940SRam Amrani struct roce_destroy_qp_req_output_params *p_ramrod_res; 1650f1093940SRam Amrani struct roce_destroy_qp_req_ramrod_data *p_ramrod; 1651f1093940SRam Amrani struct qed_sp_init_data init_data; 1652f1093940SRam Amrani struct qed_spq_entry *p_ent; 1653f1093940SRam Amrani dma_addr_t ramrod_res_phys; 1654f1093940SRam Amrani int rc = -ENOMEM; 1655f1093940SRam Amrani 1656f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1657f1093940SRam Amrani 1658f1093940SRam Amrani if (!qp->req_offloaded) 1659f1093940SRam Amrani return 0; 1660f1093940SRam Amrani 1661f1093940SRam Amrani p_ramrod_res = (struct roce_destroy_qp_req_output_params *) 1662f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1663f1093940SRam Amrani sizeof(*p_ramrod_res), 1664f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 1665f1093940SRam Amrani if (!p_ramrod_res) { 1666f1093940SRam Amrani DP_NOTICE(p_hwfn, 1667f1093940SRam Amrani "qed destroy requester failed: cannot allocate memory (ramrod)\n"); 1668f1093940SRam Amrani return rc; 1669f1093940SRam Amrani } 1670f1093940SRam Amrani 1671f1093940SRam Amrani /* Get SPQ entry */ 1672f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1673f1093940SRam Amrani init_data.cid = qp->icid + 1; 1674f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1675f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1676f1093940SRam Amrani 1677f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP, 1678f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1679f1093940SRam Amrani if (rc) 1680f1093940SRam Amrani goto err; 1681f1093940SRam Amrani 1682f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_req; 1683f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1684f1093940SRam Amrani 1685f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1686f1093940SRam Amrani if (rc) 1687f1093940SRam Amrani goto err; 1688f1093940SRam Amrani 1689f1093940SRam Amrani *num_bound_mw = le32_to_cpu(p_ramrod_res->num_bound_mw); 1690f1093940SRam Amrani 1691f1093940SRam Amrani /* Free ORQ - only if ramrod succeeded, in case FW is still using it */ 1692f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1693f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 1694f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 1695f1093940SRam Amrani 1696f1093940SRam Amrani qp->req_offloaded = false; 1697f1093940SRam Amrani 1698f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc); 1699f1093940SRam Amrani 1700f1093940SRam Amrani err: 1701f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 1702f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 1703f1093940SRam Amrani 1704f1093940SRam Amrani return rc; 1705f1093940SRam Amrani } 1706f1093940SRam Amrani 17078c93beafSYuval Mintz static int qed_roce_query_qp(struct qed_hwfn *p_hwfn, 1708f1093940SRam Amrani struct qed_rdma_qp *qp, 1709f1093940SRam Amrani struct qed_rdma_query_qp_out_params *out_params) 1710f1093940SRam Amrani { 1711f1093940SRam Amrani struct roce_query_qp_resp_output_params *p_resp_ramrod_res; 1712f1093940SRam Amrani struct roce_query_qp_req_output_params *p_req_ramrod_res; 1713f1093940SRam Amrani struct roce_query_qp_resp_ramrod_data *p_resp_ramrod; 1714f1093940SRam Amrani struct roce_query_qp_req_ramrod_data *p_req_ramrod; 1715f1093940SRam Amrani struct qed_sp_init_data init_data; 1716f1093940SRam Amrani dma_addr_t resp_ramrod_res_phys; 1717f1093940SRam Amrani dma_addr_t req_ramrod_res_phys; 1718f1093940SRam Amrani struct qed_spq_entry *p_ent; 1719f1093940SRam Amrani bool rq_err_state; 1720f1093940SRam Amrani bool sq_err_state; 1721f1093940SRam Amrani bool sq_draining; 1722f1093940SRam Amrani int rc = -ENOMEM; 1723f1093940SRam Amrani 1724f1093940SRam Amrani if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) { 1725f1093940SRam Amrani /* We can't send ramrod to the fw since this qp wasn't offloaded 1726f1093940SRam Amrani * to the fw yet 1727f1093940SRam Amrani */ 1728f1093940SRam Amrani out_params->draining = false; 1729f1093940SRam Amrani out_params->rq_psn = qp->rq_psn; 1730f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 1731f1093940SRam Amrani out_params->state = qp->cur_state; 1732f1093940SRam Amrani 1733f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n"); 1734f1093940SRam Amrani return 0; 1735f1093940SRam Amrani } 1736f1093940SRam Amrani 1737f1093940SRam Amrani if (!(qp->resp_offloaded)) { 1738f1093940SRam Amrani DP_NOTICE(p_hwfn, 1739f1093940SRam Amrani "The responder's qp should be offloded before requester's\n"); 1740f1093940SRam Amrani return -EINVAL; 1741f1093940SRam Amrani } 1742f1093940SRam Amrani 1743f1093940SRam Amrani /* Send a query responder ramrod to FW to get RQ-PSN and state */ 1744f1093940SRam Amrani p_resp_ramrod_res = (struct roce_query_qp_resp_output_params *) 1745f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1746f1093940SRam Amrani sizeof(*p_resp_ramrod_res), 1747f1093940SRam Amrani &resp_ramrod_res_phys, GFP_KERNEL); 1748f1093940SRam Amrani if (!p_resp_ramrod_res) { 1749f1093940SRam Amrani DP_NOTICE(p_hwfn, 1750f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 1751f1093940SRam Amrani return rc; 1752f1093940SRam Amrani } 1753f1093940SRam Amrani 1754f1093940SRam Amrani /* Get SPQ entry */ 1755f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1756f1093940SRam Amrani init_data.cid = qp->icid; 1757f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1758f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1759f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 1760f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1761f1093940SRam Amrani if (rc) 1762f1093940SRam Amrani goto err_resp; 1763f1093940SRam Amrani 1764f1093940SRam Amrani p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp; 1765f1093940SRam Amrani DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys); 1766f1093940SRam Amrani 1767f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1768f1093940SRam Amrani if (rc) 1769f1093940SRam Amrani goto err_resp; 1770f1093940SRam Amrani 1771f1093940SRam Amrani out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn); 1772f1093940SRam Amrani rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->err_flag), 1773f1093940SRam Amrani ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG); 1774f1093940SRam Amrani 1775c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 1776c5212b94SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 1777c5212b94SRam Amrani 1778f1093940SRam Amrani if (!(qp->req_offloaded)) { 1779f1093940SRam Amrani /* Don't send query qp for the requester */ 1780f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 1781f1093940SRam Amrani out_params->draining = false; 1782f1093940SRam Amrani 1783f1093940SRam Amrani if (rq_err_state) 1784f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 1785f1093940SRam Amrani 1786f1093940SRam Amrani out_params->state = qp->cur_state; 1787f1093940SRam Amrani 1788f1093940SRam Amrani return 0; 1789f1093940SRam Amrani } 1790f1093940SRam Amrani 1791f1093940SRam Amrani /* Send a query requester ramrod to FW to get SQ-PSN and state */ 1792f1093940SRam Amrani p_req_ramrod_res = (struct roce_query_qp_req_output_params *) 1793f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1794f1093940SRam Amrani sizeof(*p_req_ramrod_res), 1795f1093940SRam Amrani &req_ramrod_res_phys, 1796f1093940SRam Amrani GFP_KERNEL); 1797f1093940SRam Amrani if (!p_req_ramrod_res) { 1798f1093940SRam Amrani rc = -ENOMEM; 1799f1093940SRam Amrani DP_NOTICE(p_hwfn, 1800f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 1801f1093940SRam Amrani return rc; 1802f1093940SRam Amrani } 1803f1093940SRam Amrani 1804f1093940SRam Amrani /* Get SPQ entry */ 1805f1093940SRam Amrani init_data.cid = qp->icid + 1; 1806f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 1807f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1808f1093940SRam Amrani if (rc) 1809f1093940SRam Amrani goto err_req; 1810f1093940SRam Amrani 1811f1093940SRam Amrani p_req_ramrod = &p_ent->ramrod.roce_query_qp_req; 1812f1093940SRam Amrani DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys); 1813f1093940SRam Amrani 1814f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1815f1093940SRam Amrani if (rc) 1816f1093940SRam Amrani goto err_req; 1817f1093940SRam Amrani 1818f1093940SRam Amrani out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn); 1819f1093940SRam Amrani sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 1820f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG); 1821f1093940SRam Amrani sq_draining = 1822f1093940SRam Amrani GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 1823f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG); 1824f1093940SRam Amrani 1825c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 1826c5212b94SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 1827c5212b94SRam Amrani 1828f1093940SRam Amrani out_params->draining = false; 1829f1093940SRam Amrani 1830f1093940SRam Amrani if (rq_err_state) 1831f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 1832f1093940SRam Amrani else if (sq_err_state) 1833f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_SQE; 1834f1093940SRam Amrani else if (sq_draining) 1835f1093940SRam Amrani out_params->draining = true; 1836f1093940SRam Amrani out_params->state = qp->cur_state; 1837f1093940SRam Amrani 1838f1093940SRam Amrani return 0; 1839f1093940SRam Amrani 1840f1093940SRam Amrani err_req: 1841f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 1842f1093940SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 1843f1093940SRam Amrani return rc; 1844f1093940SRam Amrani err_resp: 1845f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 1846f1093940SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 1847f1093940SRam Amrani return rc; 1848f1093940SRam Amrani } 1849f1093940SRam Amrani 18508c93beafSYuval Mintz static int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 1851f1093940SRam Amrani { 1852f1093940SRam Amrani u32 num_invalidated_mw = 0; 1853f1093940SRam Amrani u32 num_bound_mw = 0; 1854f1093940SRam Amrani u32 start_cid; 1855f1093940SRam Amrani int rc; 1856f1093940SRam Amrani 1857f1093940SRam Amrani /* Destroys the specified QP */ 1858f1093940SRam Amrani if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) && 1859f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_ERR) && 1860f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_INIT)) { 1861f1093940SRam Amrani DP_NOTICE(p_hwfn, 1862f1093940SRam Amrani "QP must be in error, reset or init state before destroying it\n"); 1863f1093940SRam Amrani return -EINVAL; 1864f1093940SRam Amrani } 1865f1093940SRam Amrani 1866f1093940SRam Amrani rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, &num_invalidated_mw); 1867f1093940SRam Amrani if (rc) 1868f1093940SRam Amrani return rc; 1869f1093940SRam Amrani 1870f1093940SRam Amrani /* Send destroy requester ramrod */ 1871f1093940SRam Amrani rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, &num_bound_mw); 1872f1093940SRam Amrani if (rc) 1873f1093940SRam Amrani return rc; 1874f1093940SRam Amrani 1875f1093940SRam Amrani if (num_invalidated_mw != num_bound_mw) { 1876f1093940SRam Amrani DP_NOTICE(p_hwfn, 1877f1093940SRam Amrani "number of invalidate memory windows is different from bounded ones\n"); 1878f1093940SRam Amrani return -EINVAL; 1879f1093940SRam Amrani } 1880f1093940SRam Amrani 1881f1093940SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1882f1093940SRam Amrani 1883f1093940SRam Amrani start_cid = qed_cxt_get_proto_cid_start(p_hwfn, 1884f1093940SRam Amrani p_hwfn->p_rdma_info->proto); 1885f1093940SRam Amrani 1886f1093940SRam Amrani /* Release responder's icid */ 1887f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, 1888f1093940SRam Amrani qp->icid - start_cid); 1889f1093940SRam Amrani 1890f1093940SRam Amrani /* Release requester's icid */ 1891f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, 1892f1093940SRam Amrani qp->icid + 1 - start_cid); 1893f1093940SRam Amrani 1894f1093940SRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1895f1093940SRam Amrani 1896f1093940SRam Amrani return 0; 1897f1093940SRam Amrani } 1898f1093940SRam Amrani 18990189efb8SYuval Mintz static int qed_rdma_query_qp(void *rdma_cxt, 1900f1093940SRam Amrani struct qed_rdma_qp *qp, 1901f1093940SRam Amrani struct qed_rdma_query_qp_out_params *out_params) 1902f1093940SRam Amrani { 1903f1093940SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1904f1093940SRam Amrani int rc; 1905f1093940SRam Amrani 1906f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1907f1093940SRam Amrani 1908f1093940SRam Amrani /* The following fields are filled in from qp and not FW as they can't 1909f1093940SRam Amrani * be modified by FW 1910f1093940SRam Amrani */ 1911f1093940SRam Amrani out_params->mtu = qp->mtu; 1912f1093940SRam Amrani out_params->dest_qp = qp->dest_qp; 1913f1093940SRam Amrani out_params->incoming_atomic_en = qp->incoming_atomic_en; 1914f1093940SRam Amrani out_params->e2e_flow_control_en = qp->e2e_flow_control_en; 1915f1093940SRam Amrani out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en; 1916f1093940SRam Amrani out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en; 1917f1093940SRam Amrani out_params->dgid = qp->dgid; 1918f1093940SRam Amrani out_params->flow_label = qp->flow_label; 1919f1093940SRam Amrani out_params->hop_limit_ttl = qp->hop_limit_ttl; 1920f1093940SRam Amrani out_params->traffic_class_tos = qp->traffic_class_tos; 1921f1093940SRam Amrani out_params->timeout = qp->ack_timeout; 1922f1093940SRam Amrani out_params->rnr_retry = qp->rnr_retry_cnt; 1923f1093940SRam Amrani out_params->retry_cnt = qp->retry_cnt; 1924f1093940SRam Amrani out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer; 1925f1093940SRam Amrani out_params->pkey_index = 0; 1926f1093940SRam Amrani out_params->max_rd_atomic = qp->max_rd_atomic_req; 1927f1093940SRam Amrani out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp; 1928f1093940SRam Amrani out_params->sqd_async = qp->sqd_async; 1929f1093940SRam Amrani 1930f1093940SRam Amrani rc = qed_roce_query_qp(p_hwfn, qp, out_params); 1931f1093940SRam Amrani 1932f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc); 1933f1093940SRam Amrani return rc; 1934f1093940SRam Amrani } 1935f1093940SRam Amrani 19360189efb8SYuval Mintz static int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp) 1937f1093940SRam Amrani { 1938f1093940SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1939f1093940SRam Amrani int rc = 0; 1940f1093940SRam Amrani 1941f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1942f1093940SRam Amrani 1943f1093940SRam Amrani rc = qed_roce_destroy_qp(p_hwfn, qp); 1944f1093940SRam Amrani 1945f1093940SRam Amrani /* free qp params struct */ 1946f1093940SRam Amrani kfree(qp); 1947f1093940SRam Amrani 1948f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n"); 1949f1093940SRam Amrani return rc; 1950f1093940SRam Amrani } 1951f1093940SRam Amrani 19528c93beafSYuval Mintz static struct qed_rdma_qp * 1953f1093940SRam Amrani qed_rdma_create_qp(void *rdma_cxt, 1954f1093940SRam Amrani struct qed_rdma_create_qp_in_params *in_params, 1955f1093940SRam Amrani struct qed_rdma_create_qp_out_params *out_params) 1956f1093940SRam Amrani { 1957f1093940SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1958f1093940SRam Amrani struct qed_rdma_qp *qp; 1959f1093940SRam Amrani u8 max_stats_queues; 1960f1093940SRam Amrani int rc; 1961f1093940SRam Amrani 1962f1093940SRam Amrani if (!rdma_cxt || !in_params || !out_params || !p_hwfn->p_rdma_info) { 1963f1093940SRam Amrani DP_ERR(p_hwfn->cdev, 1964f1093940SRam Amrani "qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n", 1965f1093940SRam Amrani rdma_cxt, in_params, out_params); 1966f1093940SRam Amrani return NULL; 1967f1093940SRam Amrani } 1968f1093940SRam Amrani 1969f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1970f1093940SRam Amrani "qed rdma create qp called with qp_handle = %08x%08x\n", 1971f1093940SRam Amrani in_params->qp_handle_hi, in_params->qp_handle_lo); 1972f1093940SRam Amrani 1973f1093940SRam Amrani /* Some sanity checks... */ 1974f1093940SRam Amrani max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues; 1975f1093940SRam Amrani if (in_params->stats_queue >= max_stats_queues) { 1976f1093940SRam Amrani DP_ERR(p_hwfn->cdev, 1977f1093940SRam Amrani "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n", 1978f1093940SRam Amrani in_params->stats_queue, max_stats_queues); 1979f1093940SRam Amrani return NULL; 1980f1093940SRam Amrani } 1981f1093940SRam Amrani 1982f1093940SRam Amrani qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1983f1093940SRam Amrani if (!qp) { 1984f1093940SRam Amrani DP_NOTICE(p_hwfn, "Failed to allocate qed_rdma_qp\n"); 1985f1093940SRam Amrani return NULL; 1986f1093940SRam Amrani } 1987f1093940SRam Amrani 1988f1093940SRam Amrani rc = qed_roce_alloc_cid(p_hwfn, &qp->icid); 1989f1093940SRam Amrani qp->qpid = ((0xFF << 16) | qp->icid); 1990f1093940SRam Amrani 1991f1093940SRam Amrani DP_INFO(p_hwfn, "ROCE qpid=%x\n", qp->qpid); 1992f1093940SRam Amrani 1993f1093940SRam Amrani if (rc) { 1994f1093940SRam Amrani kfree(qp); 1995f1093940SRam Amrani return NULL; 1996f1093940SRam Amrani } 1997f1093940SRam Amrani 1998f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_RESET; 1999f1093940SRam Amrani qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi); 2000f1093940SRam Amrani qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo); 2001f1093940SRam Amrani qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi); 2002f1093940SRam Amrani qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo); 2003f1093940SRam Amrani qp->use_srq = in_params->use_srq; 2004f1093940SRam Amrani qp->signal_all = in_params->signal_all; 2005f1093940SRam Amrani qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey; 2006f1093940SRam Amrani qp->pd = in_params->pd; 2007f1093940SRam Amrani qp->dpi = in_params->dpi; 2008f1093940SRam Amrani qp->sq_cq_id = in_params->sq_cq_id; 2009f1093940SRam Amrani qp->sq_num_pages = in_params->sq_num_pages; 2010f1093940SRam Amrani qp->sq_pbl_ptr = in_params->sq_pbl_ptr; 2011f1093940SRam Amrani qp->rq_cq_id = in_params->rq_cq_id; 2012f1093940SRam Amrani qp->rq_num_pages = in_params->rq_num_pages; 2013f1093940SRam Amrani qp->rq_pbl_ptr = in_params->rq_pbl_ptr; 2014f1093940SRam Amrani qp->srq_id = in_params->srq_id; 2015f1093940SRam Amrani qp->req_offloaded = false; 2016f1093940SRam Amrani qp->resp_offloaded = false; 2017f1093940SRam Amrani qp->e2e_flow_control_en = qp->use_srq ? false : true; 2018f1093940SRam Amrani qp->stats_queue = in_params->stats_queue; 2019f1093940SRam Amrani 2020f1093940SRam Amrani out_params->icid = qp->icid; 2021f1093940SRam Amrani out_params->qp_id = qp->qpid; 2022f1093940SRam Amrani 2023f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc); 2024f1093940SRam Amrani return qp; 2025f1093940SRam Amrani } 2026f1093940SRam Amrani 2027f1093940SRam Amrani static int qed_roce_modify_qp(struct qed_hwfn *p_hwfn, 2028f1093940SRam Amrani struct qed_rdma_qp *qp, 2029f1093940SRam Amrani enum qed_roce_qp_state prev_state, 2030f1093940SRam Amrani struct qed_rdma_modify_qp_in_params *params) 2031f1093940SRam Amrani { 2032f1093940SRam Amrani u32 num_invalidated_mw = 0, num_bound_mw = 0; 2033f1093940SRam Amrani int rc = 0; 2034f1093940SRam Amrani 2035f1093940SRam Amrani /* Perform additional operations according to the current state and the 2036f1093940SRam Amrani * next state 2037f1093940SRam Amrani */ 2038f1093940SRam Amrani if (((prev_state == QED_ROCE_QP_STATE_INIT) || 2039f1093940SRam Amrani (prev_state == QED_ROCE_QP_STATE_RESET)) && 2040f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTR)) { 2041f1093940SRam Amrani /* Init->RTR or Reset->RTR */ 2042f1093940SRam Amrani rc = qed_roce_sp_create_responder(p_hwfn, qp); 2043f1093940SRam Amrani return rc; 2044f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTR) && 2045f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 2046f1093940SRam Amrani /* RTR-> RTS */ 2047f1093940SRam Amrani rc = qed_roce_sp_create_requester(p_hwfn, qp); 2048f1093940SRam Amrani if (rc) 2049f1093940SRam Amrani return rc; 2050f1093940SRam Amrani 2051f1093940SRam Amrani /* Send modify responder ramrod */ 2052f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2053f1093940SRam Amrani params->modify_flags); 2054f1093940SRam Amrani return rc; 2055f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 2056f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 2057f1093940SRam Amrani /* RTS->RTS */ 2058f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2059f1093940SRam Amrani params->modify_flags); 2060f1093940SRam Amrani if (rc) 2061f1093940SRam Amrani return rc; 2062f1093940SRam Amrani 2063f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 2064f1093940SRam Amrani params->modify_flags); 2065f1093940SRam Amrani return rc; 2066f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 2067f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 2068f1093940SRam Amrani /* RTS->SQD */ 2069f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false, 2070f1093940SRam Amrani params->modify_flags); 2071f1093940SRam Amrani return rc; 2072f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 2073f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 2074f1093940SRam Amrani /* SQD->SQD */ 2075f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2076f1093940SRam Amrani params->modify_flags); 2077f1093940SRam Amrani if (rc) 2078f1093940SRam Amrani return rc; 2079f1093940SRam Amrani 2080f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 2081f1093940SRam Amrani params->modify_flags); 2082f1093940SRam Amrani return rc; 2083f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 2084f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 2085f1093940SRam Amrani /* SQD->RTS */ 2086f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2087f1093940SRam Amrani params->modify_flags); 2088f1093940SRam Amrani if (rc) 2089f1093940SRam Amrani return rc; 2090f1093940SRam Amrani 2091f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 2092f1093940SRam Amrani params->modify_flags); 2093f1093940SRam Amrani 2094f1093940SRam Amrani return rc; 2095f1093940SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR || 2096f1093940SRam Amrani qp->cur_state == QED_ROCE_QP_STATE_SQE) { 2097f1093940SRam Amrani /* ->ERR */ 2098f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, true, 2099f1093940SRam Amrani params->modify_flags); 2100f1093940SRam Amrani if (rc) 2101f1093940SRam Amrani return rc; 2102f1093940SRam Amrani 2103f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true, 2104f1093940SRam Amrani params->modify_flags); 2105f1093940SRam Amrani return rc; 2106f1093940SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) { 2107f1093940SRam Amrani /* Any state -> RESET */ 2108f1093940SRam Amrani 2109f1093940SRam Amrani rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, 2110f1093940SRam Amrani &num_invalidated_mw); 2111f1093940SRam Amrani if (rc) 2112f1093940SRam Amrani return rc; 2113f1093940SRam Amrani 2114f1093940SRam Amrani rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, 2115f1093940SRam Amrani &num_bound_mw); 2116f1093940SRam Amrani 2117f1093940SRam Amrani if (num_invalidated_mw != num_bound_mw) { 2118f1093940SRam Amrani DP_NOTICE(p_hwfn, 2119f1093940SRam Amrani "number of invalidate memory windows is different from bounded ones\n"); 2120f1093940SRam Amrani return -EINVAL; 2121f1093940SRam Amrani } 2122f1093940SRam Amrani } else { 2123f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 2124f1093940SRam Amrani } 2125f1093940SRam Amrani 2126f1093940SRam Amrani return rc; 2127f1093940SRam Amrani } 2128f1093940SRam Amrani 21290189efb8SYuval Mintz static int qed_rdma_modify_qp(void *rdma_cxt, 2130f1093940SRam Amrani struct qed_rdma_qp *qp, 2131f1093940SRam Amrani struct qed_rdma_modify_qp_in_params *params) 2132f1093940SRam Amrani { 2133f1093940SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2134f1093940SRam Amrani enum qed_roce_qp_state prev_state; 2135f1093940SRam Amrani int rc = 0; 2136f1093940SRam Amrani 2137f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n", 2138f1093940SRam Amrani qp->icid, params->new_state); 2139f1093940SRam Amrani 2140f1093940SRam Amrani if (rc) { 2141f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2142f1093940SRam Amrani return rc; 2143f1093940SRam Amrani } 2144f1093940SRam Amrani 2145f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2146f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) { 2147f1093940SRam Amrani qp->incoming_rdma_read_en = params->incoming_rdma_read_en; 2148f1093940SRam Amrani qp->incoming_rdma_write_en = params->incoming_rdma_write_en; 2149f1093940SRam Amrani qp->incoming_atomic_en = params->incoming_atomic_en; 2150f1093940SRam Amrani } 2151f1093940SRam Amrani 2152f1093940SRam Amrani /* Update QP structure with the updated values */ 2153f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE)) 2154f1093940SRam Amrani qp->roce_mode = params->roce_mode; 2155f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)) 2156f1093940SRam Amrani qp->pkey = params->pkey; 2157f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2158f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN)) 2159f1093940SRam Amrani qp->e2e_flow_control_en = params->e2e_flow_control_en; 2160f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP)) 2161f1093940SRam Amrani qp->dest_qp = params->dest_qp; 2162f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2163f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) { 2164f1093940SRam Amrani /* Indicates that the following parameters have changed: 2165f1093940SRam Amrani * Traffic class, flow label, hop limit, source GID, 2166f1093940SRam Amrani * destination GID, loopback indicator 2167f1093940SRam Amrani */ 2168f1093940SRam Amrani qp->traffic_class_tos = params->traffic_class_tos; 2169f1093940SRam Amrani qp->flow_label = params->flow_label; 2170f1093940SRam Amrani qp->hop_limit_ttl = params->hop_limit_ttl; 2171f1093940SRam Amrani 2172f1093940SRam Amrani qp->sgid = params->sgid; 2173f1093940SRam Amrani qp->dgid = params->dgid; 2174f1093940SRam Amrani qp->udp_src_port = 0; 2175f1093940SRam Amrani qp->vlan_id = params->vlan_id; 2176f1093940SRam Amrani qp->mtu = params->mtu; 2177f1093940SRam Amrani qp->lb_indication = params->lb_indication; 2178f1093940SRam Amrani memcpy((u8 *)&qp->remote_mac_addr[0], 2179f1093940SRam Amrani (u8 *)¶ms->remote_mac_addr[0], ETH_ALEN); 2180f1093940SRam Amrani if (params->use_local_mac) { 2181f1093940SRam Amrani memcpy((u8 *)&qp->local_mac_addr[0], 2182f1093940SRam Amrani (u8 *)¶ms->local_mac_addr[0], ETH_ALEN); 2183f1093940SRam Amrani } else { 2184f1093940SRam Amrani memcpy((u8 *)&qp->local_mac_addr[0], 2185f1093940SRam Amrani (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN); 2186f1093940SRam Amrani } 2187f1093940SRam Amrani } 2188f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN)) 2189f1093940SRam Amrani qp->rq_psn = params->rq_psn; 2190f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN)) 2191f1093940SRam Amrani qp->sq_psn = params->sq_psn; 2192f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2193f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)) 2194f1093940SRam Amrani qp->max_rd_atomic_req = params->max_rd_atomic_req; 2195f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2196f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)) 2197f1093940SRam Amrani qp->max_rd_atomic_resp = params->max_rd_atomic_resp; 2198f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2199f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)) 2200f1093940SRam Amrani qp->ack_timeout = params->ack_timeout; 2201f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)) 2202f1093940SRam Amrani qp->retry_cnt = params->retry_cnt; 2203f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2204f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)) 2205f1093940SRam Amrani qp->rnr_retry_cnt = params->rnr_retry_cnt; 2206f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2207f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)) 2208f1093940SRam Amrani qp->min_rnr_nak_timer = params->min_rnr_nak_timer; 2209f1093940SRam Amrani 2210f1093940SRam Amrani qp->sqd_async = params->sqd_async; 2211f1093940SRam Amrani 2212f1093940SRam Amrani prev_state = qp->cur_state; 2213f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2214f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) { 2215f1093940SRam Amrani qp->cur_state = params->new_state; 2216f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n", 2217f1093940SRam Amrani qp->cur_state); 2218f1093940SRam Amrani } 2219f1093940SRam Amrani 2220f1093940SRam Amrani rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params); 2221f1093940SRam Amrani 2222f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc); 2223f1093940SRam Amrani return rc; 2224f1093940SRam Amrani } 2225f1093940SRam Amrani 22260189efb8SYuval Mintz static int 22270189efb8SYuval Mintz qed_rdma_register_tid(void *rdma_cxt, 2228ee8eaea3SRam Amrani struct qed_rdma_register_tid_in_params *params) 2229ee8eaea3SRam Amrani { 2230ee8eaea3SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2231ee8eaea3SRam Amrani struct rdma_register_tid_ramrod_data *p_ramrod; 2232ee8eaea3SRam Amrani struct qed_sp_init_data init_data; 2233ee8eaea3SRam Amrani struct qed_spq_entry *p_ent; 2234ee8eaea3SRam Amrani enum rdma_tid_type tid_type; 2235ee8eaea3SRam Amrani u8 fw_return_code; 2236ee8eaea3SRam Amrani int rc; 2237ee8eaea3SRam Amrani 2238ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", params->itid); 2239ee8eaea3SRam Amrani 2240ee8eaea3SRam Amrani /* Get SPQ entry */ 2241ee8eaea3SRam Amrani memset(&init_data, 0, sizeof(init_data)); 2242ee8eaea3SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 2243ee8eaea3SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 2244ee8eaea3SRam Amrani 2245ee8eaea3SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_REGISTER_MR, 2246ee8eaea3SRam Amrani p_hwfn->p_rdma_info->proto, &init_data); 2247ee8eaea3SRam Amrani if (rc) { 2248ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2249ee8eaea3SRam Amrani return rc; 2250ee8eaea3SRam Amrani } 2251ee8eaea3SRam Amrani 2252ee8eaea3SRam Amrani if (p_hwfn->p_rdma_info->last_tid < params->itid) 2253ee8eaea3SRam Amrani p_hwfn->p_rdma_info->last_tid = params->itid; 2254ee8eaea3SRam Amrani 2255ee8eaea3SRam Amrani p_ramrod = &p_ent->ramrod.rdma_register_tid; 2256ee8eaea3SRam Amrani 2257ee8eaea3SRam Amrani p_ramrod->flags = 0; 2258ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2259ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL, 2260ee8eaea3SRam Amrani params->pbl_two_level); 2261ee8eaea3SRam Amrani 2262ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2263ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED, params->zbva); 2264ee8eaea3SRam Amrani 2265ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2266ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR, params->phy_mr); 2267ee8eaea3SRam Amrani 2268ee8eaea3SRam Amrani /* Don't initialize D/C field, as it may override other bits. */ 2269ee8eaea3SRam Amrani if (!(params->tid_type == QED_RDMA_TID_FMR) && !(params->dma_mr)) 2270ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2271ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG, 2272ee8eaea3SRam Amrani params->page_size_log - 12); 2273ee8eaea3SRam Amrani 2274ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2275ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID, 2276ee8eaea3SRam Amrani p_hwfn->p_rdma_info->last_tid); 2277ee8eaea3SRam Amrani 2278ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2279ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ, 2280ee8eaea3SRam Amrani params->remote_read); 2281ee8eaea3SRam Amrani 2282ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2283ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE, 2284ee8eaea3SRam Amrani params->remote_write); 2285ee8eaea3SRam Amrani 2286ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2287ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC, 2288ee8eaea3SRam Amrani params->remote_atomic); 2289ee8eaea3SRam Amrani 2290ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2291ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE, 2292ee8eaea3SRam Amrani params->local_write); 2293ee8eaea3SRam Amrani 2294ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2295ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ, params->local_read); 2296ee8eaea3SRam Amrani 2297ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2298ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND, 2299ee8eaea3SRam Amrani params->mw_bind); 2300ee8eaea3SRam Amrani 2301ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags1, 2302ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG, 2303ee8eaea3SRam Amrani params->pbl_page_size_log - 12); 2304ee8eaea3SRam Amrani 2305ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags2, 2306ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR, params->dma_mr); 2307ee8eaea3SRam Amrani 2308ee8eaea3SRam Amrani switch (params->tid_type) { 2309ee8eaea3SRam Amrani case QED_RDMA_TID_REGISTERED_MR: 2310ee8eaea3SRam Amrani tid_type = RDMA_TID_REGISTERED_MR; 2311ee8eaea3SRam Amrani break; 2312ee8eaea3SRam Amrani case QED_RDMA_TID_FMR: 2313ee8eaea3SRam Amrani tid_type = RDMA_TID_FMR; 2314ee8eaea3SRam Amrani break; 2315ee8eaea3SRam Amrani case QED_RDMA_TID_MW_TYPE1: 2316ee8eaea3SRam Amrani tid_type = RDMA_TID_MW_TYPE1; 2317ee8eaea3SRam Amrani break; 2318ee8eaea3SRam Amrani case QED_RDMA_TID_MW_TYPE2A: 2319ee8eaea3SRam Amrani tid_type = RDMA_TID_MW_TYPE2A; 2320ee8eaea3SRam Amrani break; 2321ee8eaea3SRam Amrani default: 2322ee8eaea3SRam Amrani rc = -EINVAL; 2323ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2324ee8eaea3SRam Amrani return rc; 2325ee8eaea3SRam Amrani } 2326ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags1, 2327ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE, tid_type); 2328ee8eaea3SRam Amrani 2329ee8eaea3SRam Amrani p_ramrod->itid = cpu_to_le32(params->itid); 2330ee8eaea3SRam Amrani p_ramrod->key = params->key; 2331ee8eaea3SRam Amrani p_ramrod->pd = cpu_to_le16(params->pd); 2332ee8eaea3SRam Amrani p_ramrod->length_hi = (u8)(params->length >> 32); 2333ee8eaea3SRam Amrani p_ramrod->length_lo = DMA_LO_LE(params->length); 2334ee8eaea3SRam Amrani if (params->zbva) { 2335ee8eaea3SRam Amrani /* Lower 32 bits of the registered MR address. 2336ee8eaea3SRam Amrani * In case of zero based MR, will hold FBO 2337ee8eaea3SRam Amrani */ 2338ee8eaea3SRam Amrani p_ramrod->va.hi = 0; 2339ee8eaea3SRam Amrani p_ramrod->va.lo = cpu_to_le32(params->fbo); 2340ee8eaea3SRam Amrani } else { 2341ee8eaea3SRam Amrani DMA_REGPAIR_LE(p_ramrod->va, params->vaddr); 2342ee8eaea3SRam Amrani } 2343ee8eaea3SRam Amrani DMA_REGPAIR_LE(p_ramrod->pbl_base, params->pbl_ptr); 2344ee8eaea3SRam Amrani 2345ee8eaea3SRam Amrani /* DIF */ 2346ee8eaea3SRam Amrani if (params->dif_enabled) { 2347ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags2, 2348ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG, 1); 2349ee8eaea3SRam Amrani DMA_REGPAIR_LE(p_ramrod->dif_error_addr, 2350ee8eaea3SRam Amrani params->dif_error_addr); 2351ee8eaea3SRam Amrani DMA_REGPAIR_LE(p_ramrod->dif_runt_addr, params->dif_runt_addr); 2352ee8eaea3SRam Amrani } 2353ee8eaea3SRam Amrani 2354ee8eaea3SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 2355ee8eaea3SRam Amrani 2356ee8eaea3SRam Amrani if (fw_return_code != RDMA_RETURN_OK) { 2357ee8eaea3SRam Amrani DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 2358ee8eaea3SRam Amrani return -EINVAL; 2359ee8eaea3SRam Amrani } 2360ee8eaea3SRam Amrani 2361ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Register TID, rc = %d\n", rc); 2362ee8eaea3SRam Amrani return rc; 2363ee8eaea3SRam Amrani } 2364ee8eaea3SRam Amrani 23650189efb8SYuval Mintz static int qed_rdma_deregister_tid(void *rdma_cxt, u32 itid) 2366ee8eaea3SRam Amrani { 2367ee8eaea3SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2368ee8eaea3SRam Amrani struct rdma_deregister_tid_ramrod_data *p_ramrod; 2369ee8eaea3SRam Amrani struct qed_sp_init_data init_data; 2370ee8eaea3SRam Amrani struct qed_spq_entry *p_ent; 2371ee8eaea3SRam Amrani struct qed_ptt *p_ptt; 2372ee8eaea3SRam Amrani u8 fw_return_code; 2373ee8eaea3SRam Amrani int rc; 2374ee8eaea3SRam Amrani 2375ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 2376ee8eaea3SRam Amrani 2377ee8eaea3SRam Amrani /* Get SPQ entry */ 2378ee8eaea3SRam Amrani memset(&init_data, 0, sizeof(init_data)); 2379ee8eaea3SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 2380ee8eaea3SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 2381ee8eaea3SRam Amrani 2382ee8eaea3SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_DEREGISTER_MR, 2383ee8eaea3SRam Amrani p_hwfn->p_rdma_info->proto, &init_data); 2384ee8eaea3SRam Amrani if (rc) { 2385ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2386ee8eaea3SRam Amrani return rc; 2387ee8eaea3SRam Amrani } 2388ee8eaea3SRam Amrani 2389ee8eaea3SRam Amrani p_ramrod = &p_ent->ramrod.rdma_deregister_tid; 2390ee8eaea3SRam Amrani p_ramrod->itid = cpu_to_le32(itid); 2391ee8eaea3SRam Amrani 2392ee8eaea3SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 2393ee8eaea3SRam Amrani if (rc) { 2394ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2395ee8eaea3SRam Amrani return rc; 2396ee8eaea3SRam Amrani } 2397ee8eaea3SRam Amrani 2398ee8eaea3SRam Amrani if (fw_return_code == RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR) { 2399ee8eaea3SRam Amrani DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 2400ee8eaea3SRam Amrani return -EINVAL; 2401ee8eaea3SRam Amrani } else if (fw_return_code == RDMA_RETURN_NIG_DRAIN_REQ) { 2402ee8eaea3SRam Amrani /* Bit indicating that the TID is in use and a nig drain is 2403ee8eaea3SRam Amrani * required before sending the ramrod again 2404ee8eaea3SRam Amrani */ 2405ee8eaea3SRam Amrani p_ptt = qed_ptt_acquire(p_hwfn); 2406ee8eaea3SRam Amrani if (!p_ptt) { 2407ee8eaea3SRam Amrani rc = -EBUSY; 2408ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2409ee8eaea3SRam Amrani "Failed to acquire PTT\n"); 2410ee8eaea3SRam Amrani return rc; 2411ee8eaea3SRam Amrani } 2412ee8eaea3SRam Amrani 2413ee8eaea3SRam Amrani rc = qed_mcp_drain(p_hwfn, p_ptt); 2414ee8eaea3SRam Amrani if (rc) { 2415ee8eaea3SRam Amrani qed_ptt_release(p_hwfn, p_ptt); 2416ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2417ee8eaea3SRam Amrani "Drain failed\n"); 2418ee8eaea3SRam Amrani return rc; 2419ee8eaea3SRam Amrani } 2420ee8eaea3SRam Amrani 2421ee8eaea3SRam Amrani qed_ptt_release(p_hwfn, p_ptt); 2422ee8eaea3SRam Amrani 2423ee8eaea3SRam Amrani /* Resend the ramrod */ 2424ee8eaea3SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 2425ee8eaea3SRam Amrani RDMA_RAMROD_DEREGISTER_MR, 2426ee8eaea3SRam Amrani p_hwfn->p_rdma_info->proto, 2427ee8eaea3SRam Amrani &init_data); 2428ee8eaea3SRam Amrani if (rc) { 2429ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2430ee8eaea3SRam Amrani "Failed to init sp-element\n"); 2431ee8eaea3SRam Amrani return rc; 2432ee8eaea3SRam Amrani } 2433ee8eaea3SRam Amrani 2434ee8eaea3SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 2435ee8eaea3SRam Amrani if (rc) { 2436ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2437ee8eaea3SRam Amrani "Ramrod failed\n"); 2438ee8eaea3SRam Amrani return rc; 2439ee8eaea3SRam Amrani } 2440ee8eaea3SRam Amrani 2441ee8eaea3SRam Amrani if (fw_return_code != RDMA_RETURN_OK) { 2442ee8eaea3SRam Amrani DP_NOTICE(p_hwfn, "fw_return_code = %d\n", 2443ee8eaea3SRam Amrani fw_return_code); 2444ee8eaea3SRam Amrani return rc; 2445ee8eaea3SRam Amrani } 2446ee8eaea3SRam Amrani } 2447ee8eaea3SRam Amrani 2448ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "De-registered TID, rc = %d\n", rc); 2449ee8eaea3SRam Amrani return rc; 2450ee8eaea3SRam Amrani } 2451ee8eaea3SRam Amrani 245251ff1725SRam Amrani static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev) 245351ff1725SRam Amrani { 245451ff1725SRam Amrani return QED_LEADING_HWFN(cdev); 245551ff1725SRam Amrani } 245651ff1725SRam Amrani 245751ff1725SRam Amrani static void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 245851ff1725SRam Amrani { 245951ff1725SRam Amrani u32 val; 246051ff1725SRam Amrani 246151ff1725SRam Amrani val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1; 246251ff1725SRam Amrani 246351ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val); 246451ff1725SRam Amrani DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA), 246551ff1725SRam Amrani "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n", 246651ff1725SRam Amrani val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm); 246751ff1725SRam Amrani } 246851ff1725SRam Amrani 246951ff1725SRam Amrani void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 247051ff1725SRam Amrani { 247151ff1725SRam Amrani p_hwfn->db_bar_no_edpm = true; 247251ff1725SRam Amrani 247351ff1725SRam Amrani qed_rdma_dpm_conf(p_hwfn, p_ptt); 247451ff1725SRam Amrani } 247551ff1725SRam Amrani 24760189efb8SYuval Mintz static int qed_rdma_start(void *rdma_cxt, 24770189efb8SYuval Mintz struct qed_rdma_start_in_params *params) 247851ff1725SRam Amrani { 247951ff1725SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 248051ff1725SRam Amrani struct qed_ptt *p_ptt; 248151ff1725SRam Amrani int rc = -EBUSY; 248251ff1725SRam Amrani 248351ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 248451ff1725SRam Amrani "desired_cnq = %08x\n", params->desired_cnq); 248551ff1725SRam Amrani 248651ff1725SRam Amrani p_ptt = qed_ptt_acquire(p_hwfn); 248751ff1725SRam Amrani if (!p_ptt) 248851ff1725SRam Amrani goto err; 248951ff1725SRam Amrani 249051ff1725SRam Amrani rc = qed_rdma_alloc(p_hwfn, p_ptt, params); 249151ff1725SRam Amrani if (rc) 249251ff1725SRam Amrani goto err1; 249351ff1725SRam Amrani 249451ff1725SRam Amrani rc = qed_rdma_setup(p_hwfn, p_ptt, params); 249551ff1725SRam Amrani if (rc) 249651ff1725SRam Amrani goto err2; 249751ff1725SRam Amrani 249851ff1725SRam Amrani qed_ptt_release(p_hwfn, p_ptt); 249951ff1725SRam Amrani 250051ff1725SRam Amrani return rc; 250151ff1725SRam Amrani 250251ff1725SRam Amrani err2: 250351ff1725SRam Amrani qed_rdma_free(p_hwfn); 250451ff1725SRam Amrani err1: 250551ff1725SRam Amrani qed_ptt_release(p_hwfn, p_ptt); 250651ff1725SRam Amrani err: 250751ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc); 250851ff1725SRam Amrani return rc; 250951ff1725SRam Amrani } 251051ff1725SRam Amrani 251151ff1725SRam Amrani static int qed_rdma_init(struct qed_dev *cdev, 251251ff1725SRam Amrani struct qed_rdma_start_in_params *params) 251351ff1725SRam Amrani { 251451ff1725SRam Amrani return qed_rdma_start(QED_LEADING_HWFN(cdev), params); 251551ff1725SRam Amrani } 251651ff1725SRam Amrani 25170189efb8SYuval Mintz static void qed_rdma_remove_user(void *rdma_cxt, u16 dpi) 251851ff1725SRam Amrani { 251951ff1725SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 252051ff1725SRam Amrani 252151ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi); 252251ff1725SRam Amrani 252351ff1725SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 252451ff1725SRam Amrani qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi); 252551ff1725SRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 252651ff1725SRam Amrani } 252751ff1725SRam Amrani 2528abd49676SRam Amrani void qed_ll2b_complete_tx_gsi_packet(struct qed_hwfn *p_hwfn, 2529abd49676SRam Amrani u8 connection_handle, 2530abd49676SRam Amrani void *cookie, 2531abd49676SRam Amrani dma_addr_t first_frag_addr, 2532abd49676SRam Amrani bool b_last_fragment, bool b_last_packet) 2533abd49676SRam Amrani { 2534abd49676SRam Amrani struct qed_roce_ll2_packet *packet = cookie; 2535abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2 = p_hwfn->ll2; 2536abd49676SRam Amrani 2537abd49676SRam Amrani roce_ll2->cbs.tx_cb(roce_ll2->cb_cookie, packet); 2538abd49676SRam Amrani } 2539abd49676SRam Amrani 2540abd49676SRam Amrani void qed_ll2b_release_tx_gsi_packet(struct qed_hwfn *p_hwfn, 2541abd49676SRam Amrani u8 connection_handle, 2542abd49676SRam Amrani void *cookie, 2543abd49676SRam Amrani dma_addr_t first_frag_addr, 2544abd49676SRam Amrani bool b_last_fragment, bool b_last_packet) 2545abd49676SRam Amrani { 2546abd49676SRam Amrani qed_ll2b_complete_tx_gsi_packet(p_hwfn, connection_handle, 2547abd49676SRam Amrani cookie, first_frag_addr, 2548abd49676SRam Amrani b_last_fragment, b_last_packet); 2549abd49676SRam Amrani } 2550abd49676SRam Amrani 2551abd49676SRam Amrani void qed_ll2b_complete_rx_gsi_packet(struct qed_hwfn *p_hwfn, 2552abd49676SRam Amrani u8 connection_handle, 2553abd49676SRam Amrani void *cookie, 2554abd49676SRam Amrani dma_addr_t rx_buf_addr, 2555abd49676SRam Amrani u16 data_length, 2556abd49676SRam Amrani u8 data_length_error, 2557abd49676SRam Amrani u16 parse_flags, 2558abd49676SRam Amrani u16 vlan, 2559abd49676SRam Amrani u32 src_mac_addr_hi, 2560abd49676SRam Amrani u16 src_mac_addr_lo, bool b_last_packet) 2561abd49676SRam Amrani { 2562abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2 = p_hwfn->ll2; 2563abd49676SRam Amrani struct qed_roce_ll2_rx_params params; 2564abd49676SRam Amrani struct qed_dev *cdev = p_hwfn->cdev; 2565abd49676SRam Amrani struct qed_roce_ll2_packet pkt; 2566abd49676SRam Amrani 2567abd49676SRam Amrani DP_VERBOSE(cdev, 2568abd49676SRam Amrani QED_MSG_LL2, 2569abd49676SRam Amrani "roce ll2 rx complete: bus_addr=%p, len=%d, data_len_err=%d\n", 2570abd49676SRam Amrani (void *)(uintptr_t)rx_buf_addr, 2571abd49676SRam Amrani data_length, data_length_error); 2572abd49676SRam Amrani 2573abd49676SRam Amrani memset(&pkt, 0, sizeof(pkt)); 2574abd49676SRam Amrani pkt.n_seg = 1; 2575abd49676SRam Amrani pkt.payload[0].baddr = rx_buf_addr; 2576abd49676SRam Amrani pkt.payload[0].len = data_length; 2577abd49676SRam Amrani 2578abd49676SRam Amrani memset(¶ms, 0, sizeof(params)); 2579abd49676SRam Amrani params.vlan_id = vlan; 2580abd49676SRam Amrani *((u32 *)¶ms.smac[0]) = ntohl(src_mac_addr_hi); 2581abd49676SRam Amrani *((u16 *)¶ms.smac[4]) = ntohs(src_mac_addr_lo); 2582abd49676SRam Amrani 2583abd49676SRam Amrani if (data_length_error) { 2584abd49676SRam Amrani DP_ERR(cdev, 2585abd49676SRam Amrani "roce ll2 rx complete: data length error %d, length=%d\n", 2586abd49676SRam Amrani data_length_error, data_length); 2587abd49676SRam Amrani params.rc = -EINVAL; 2588abd49676SRam Amrani } 2589abd49676SRam Amrani 2590abd49676SRam Amrani roce_ll2->cbs.rx_cb(roce_ll2->cb_cookie, &pkt, ¶ms); 2591abd49676SRam Amrani } 2592abd49676SRam Amrani 2593abd49676SRam Amrani static int qed_roce_ll2_set_mac_filter(struct qed_dev *cdev, 2594abd49676SRam Amrani u8 *old_mac_address, 2595abd49676SRam Amrani u8 *new_mac_address) 2596abd49676SRam Amrani { 2597abd49676SRam Amrani struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2598abd49676SRam Amrani struct qed_ptt *p_ptt; 2599abd49676SRam Amrani int rc = 0; 2600abd49676SRam Amrani 2601abd49676SRam Amrani if (!hwfn->ll2 || hwfn->ll2->handle == QED_LL2_UNUSED_HANDLE) { 2602abd49676SRam Amrani DP_ERR(cdev, 2603abd49676SRam Amrani "qed roce mac filter failed - roce_info/ll2 NULL\n"); 2604abd49676SRam Amrani return -EINVAL; 2605abd49676SRam Amrani } 2606abd49676SRam Amrani 2607abd49676SRam Amrani p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 2608abd49676SRam Amrani if (!p_ptt) { 2609abd49676SRam Amrani DP_ERR(cdev, 2610abd49676SRam Amrani "qed roce ll2 mac filter set: failed to acquire PTT\n"); 2611abd49676SRam Amrani return -EINVAL; 2612abd49676SRam Amrani } 2613abd49676SRam Amrani 2614abd49676SRam Amrani mutex_lock(&hwfn->ll2->lock); 2615abd49676SRam Amrani if (old_mac_address) 2616abd49676SRam Amrani qed_llh_remove_mac_filter(QED_LEADING_HWFN(cdev), p_ptt, 2617abd49676SRam Amrani old_mac_address); 2618abd49676SRam Amrani if (new_mac_address) 2619abd49676SRam Amrani rc = qed_llh_add_mac_filter(QED_LEADING_HWFN(cdev), p_ptt, 2620abd49676SRam Amrani new_mac_address); 2621abd49676SRam Amrani mutex_unlock(&hwfn->ll2->lock); 2622abd49676SRam Amrani 2623abd49676SRam Amrani qed_ptt_release(QED_LEADING_HWFN(cdev), p_ptt); 2624abd49676SRam Amrani 2625abd49676SRam Amrani if (rc) 2626abd49676SRam Amrani DP_ERR(cdev, 2627abd49676SRam Amrani "qed roce ll2 mac filter set: failed to add mac filter\n"); 2628abd49676SRam Amrani 2629abd49676SRam Amrani return rc; 2630abd49676SRam Amrani } 2631abd49676SRam Amrani 2632abd49676SRam Amrani static int qed_roce_ll2_start(struct qed_dev *cdev, 2633abd49676SRam Amrani struct qed_roce_ll2_params *params) 2634abd49676SRam Amrani { 2635abd49676SRam Amrani struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2636abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2; 26370629a330SArnd Bergmann struct qed_ll2_conn ll2_params; 2638abd49676SRam Amrani int rc; 2639abd49676SRam Amrani 2640abd49676SRam Amrani if (!params) { 2641abd49676SRam Amrani DP_ERR(cdev, "qed roce ll2 start: failed due to NULL params\n"); 2642abd49676SRam Amrani return -EINVAL; 2643abd49676SRam Amrani } 2644abd49676SRam Amrani if (!params->cbs.tx_cb || !params->cbs.rx_cb) { 2645abd49676SRam Amrani DP_ERR(cdev, 2646abd49676SRam Amrani "qed roce ll2 start: failed due to NULL tx/rx. tx_cb=%p, rx_cb=%p\n", 2647abd49676SRam Amrani params->cbs.tx_cb, params->cbs.rx_cb); 2648abd49676SRam Amrani return -EINVAL; 2649abd49676SRam Amrani } 2650abd49676SRam Amrani if (!is_valid_ether_addr(params->mac_address)) { 2651abd49676SRam Amrani DP_ERR(cdev, 2652abd49676SRam Amrani "qed roce ll2 start: failed due to invalid Ethernet address %pM\n", 2653abd49676SRam Amrani params->mac_address); 2654abd49676SRam Amrani return -EINVAL; 2655abd49676SRam Amrani } 2656abd49676SRam Amrani 2657abd49676SRam Amrani /* Initialize */ 2658abd49676SRam Amrani roce_ll2 = kzalloc(sizeof(*roce_ll2), GFP_ATOMIC); 2659abd49676SRam Amrani if (!roce_ll2) { 2660abd49676SRam Amrani DP_ERR(cdev, "qed roce ll2 start: failed memory allocation\n"); 2661abd49676SRam Amrani return -ENOMEM; 2662abd49676SRam Amrani } 2663abd49676SRam Amrani roce_ll2->handle = QED_LL2_UNUSED_HANDLE; 2664abd49676SRam Amrani roce_ll2->cbs = params->cbs; 2665abd49676SRam Amrani roce_ll2->cb_cookie = params->cb_cookie; 2666abd49676SRam Amrani mutex_init(&roce_ll2->lock); 2667abd49676SRam Amrani 2668abd49676SRam Amrani memset(&ll2_params, 0, sizeof(ll2_params)); 2669abd49676SRam Amrani ll2_params.conn_type = QED_LL2_TYPE_ROCE; 2670abd49676SRam Amrani ll2_params.mtu = params->mtu; 2671abd49676SRam Amrani ll2_params.rx_drop_ttl0_flg = true; 2672abd49676SRam Amrani ll2_params.rx_vlan_removal_en = false; 2673abd49676SRam Amrani ll2_params.tx_dest = CORE_TX_DEST_NW; 2674abd49676SRam Amrani ll2_params.ai_err_packet_too_big = LL2_DROP_PACKET; 2675abd49676SRam Amrani ll2_params.ai_err_no_buf = LL2_DROP_PACKET; 2676abd49676SRam Amrani ll2_params.gsi_enable = true; 2677abd49676SRam Amrani 2678abd49676SRam Amrani rc = qed_ll2_acquire_connection(QED_LEADING_HWFN(cdev), &ll2_params, 2679abd49676SRam Amrani params->max_rx_buffers, 2680abd49676SRam Amrani params->max_tx_buffers, 2681abd49676SRam Amrani &roce_ll2->handle); 2682abd49676SRam Amrani if (rc) { 2683abd49676SRam Amrani DP_ERR(cdev, 2684abd49676SRam Amrani "qed roce ll2 start: failed to acquire LL2 connection (rc=%d)\n", 2685abd49676SRam Amrani rc); 2686abd49676SRam Amrani goto err; 2687abd49676SRam Amrani } 2688abd49676SRam Amrani 2689abd49676SRam Amrani rc = qed_ll2_establish_connection(QED_LEADING_HWFN(cdev), 2690abd49676SRam Amrani roce_ll2->handle); 2691abd49676SRam Amrani if (rc) { 2692abd49676SRam Amrani DP_ERR(cdev, 2693abd49676SRam Amrani "qed roce ll2 start: failed to establish LL2 connection (rc=%d)\n", 2694abd49676SRam Amrani rc); 2695abd49676SRam Amrani goto err1; 2696abd49676SRam Amrani } 2697abd49676SRam Amrani 2698abd49676SRam Amrani hwfn->ll2 = roce_ll2; 2699abd49676SRam Amrani 2700abd49676SRam Amrani rc = qed_roce_ll2_set_mac_filter(cdev, NULL, params->mac_address); 2701abd49676SRam Amrani if (rc) { 2702abd49676SRam Amrani hwfn->ll2 = NULL; 2703abd49676SRam Amrani goto err2; 2704abd49676SRam Amrani } 2705abd49676SRam Amrani ether_addr_copy(roce_ll2->mac_address, params->mac_address); 2706abd49676SRam Amrani 2707abd49676SRam Amrani return 0; 2708abd49676SRam Amrani 2709abd49676SRam Amrani err2: 2710abd49676SRam Amrani qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle); 2711abd49676SRam Amrani err1: 2712abd49676SRam Amrani qed_ll2_release_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle); 2713abd49676SRam Amrani err: 2714abd49676SRam Amrani kfree(roce_ll2); 2715abd49676SRam Amrani return rc; 2716abd49676SRam Amrani } 2717abd49676SRam Amrani 2718abd49676SRam Amrani static int qed_roce_ll2_stop(struct qed_dev *cdev) 2719abd49676SRam Amrani { 2720abd49676SRam Amrani struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2721abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2; 2722abd49676SRam Amrani int rc; 2723abd49676SRam Amrani 2724abd49676SRam Amrani if (roce_ll2->handle == QED_LL2_UNUSED_HANDLE) { 2725abd49676SRam Amrani DP_ERR(cdev, "qed roce ll2 stop: cannot stop an unused LL2\n"); 2726abd49676SRam Amrani return -EINVAL; 2727abd49676SRam Amrani } 2728abd49676SRam Amrani 2729abd49676SRam Amrani /* remove LL2 MAC address filter */ 2730abd49676SRam Amrani rc = qed_roce_ll2_set_mac_filter(cdev, roce_ll2->mac_address, NULL); 2731abd49676SRam Amrani eth_zero_addr(roce_ll2->mac_address); 2732abd49676SRam Amrani 2733abd49676SRam Amrani rc = qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev), 2734abd49676SRam Amrani roce_ll2->handle); 2735abd49676SRam Amrani if (rc) 2736abd49676SRam Amrani DP_ERR(cdev, 2737abd49676SRam Amrani "qed roce ll2 stop: failed to terminate LL2 connection (rc=%d)\n", 2738abd49676SRam Amrani rc); 2739abd49676SRam Amrani 2740abd49676SRam Amrani qed_ll2_release_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle); 2741abd49676SRam Amrani 2742abd49676SRam Amrani roce_ll2->handle = QED_LL2_UNUSED_HANDLE; 2743abd49676SRam Amrani 2744abd49676SRam Amrani kfree(roce_ll2); 2745abd49676SRam Amrani 2746abd49676SRam Amrani return rc; 2747abd49676SRam Amrani } 2748abd49676SRam Amrani 2749abd49676SRam Amrani static int qed_roce_ll2_tx(struct qed_dev *cdev, 2750abd49676SRam Amrani struct qed_roce_ll2_packet *pkt, 2751abd49676SRam Amrani struct qed_roce_ll2_tx_params *params) 2752abd49676SRam Amrani { 2753abd49676SRam Amrani struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2754abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2; 2755abd49676SRam Amrani enum qed_ll2_roce_flavor_type qed_roce_flavor; 2756abd49676SRam Amrani u8 flags = 0; 2757abd49676SRam Amrani int rc; 2758abd49676SRam Amrani int i; 2759abd49676SRam Amrani 2760ce6b04eeSYuval Mintz if (!pkt || !params) { 2761abd49676SRam Amrani DP_ERR(cdev, 2762abd49676SRam Amrani "roce ll2 tx: failed tx because one of the following is NULL - drv=%p, pkt=%p, params=%p\n", 2763abd49676SRam Amrani cdev, pkt, params); 2764abd49676SRam Amrani return -EINVAL; 2765abd49676SRam Amrani } 2766abd49676SRam Amrani 2767abd49676SRam Amrani qed_roce_flavor = (pkt->roce_mode == ROCE_V1) ? QED_LL2_ROCE 2768abd49676SRam Amrani : QED_LL2_RROCE; 2769abd49676SRam Amrani 2770abd49676SRam Amrani if (pkt->roce_mode == ROCE_V2_IPV4) 2771abd49676SRam Amrani flags |= BIT(CORE_TX_BD_FLAGS_IP_CSUM_SHIFT); 2772abd49676SRam Amrani 2773abd49676SRam Amrani /* Tx header */ 2774abd49676SRam Amrani rc = qed_ll2_prepare_tx_packet(QED_LEADING_HWFN(cdev), roce_ll2->handle, 2775abd49676SRam Amrani 1 + pkt->n_seg, 0, flags, 0, 27761d6cff4fSYuval Mintz QED_LL2_TX_DEST_NW, 2777abd49676SRam Amrani qed_roce_flavor, pkt->header.baddr, 2778abd49676SRam Amrani pkt->header.len, pkt, 1); 2779abd49676SRam Amrani if (rc) { 2780abd49676SRam Amrani DP_ERR(cdev, "roce ll2 tx: header failed (rc=%d)\n", rc); 2781abd49676SRam Amrani return QED_ROCE_TX_HEAD_FAILURE; 2782abd49676SRam Amrani } 2783abd49676SRam Amrani 2784abd49676SRam Amrani /* Tx payload */ 2785abd49676SRam Amrani for (i = 0; i < pkt->n_seg; i++) { 2786abd49676SRam Amrani rc = qed_ll2_set_fragment_of_tx_packet(QED_LEADING_HWFN(cdev), 2787abd49676SRam Amrani roce_ll2->handle, 2788abd49676SRam Amrani pkt->payload[i].baddr, 2789abd49676SRam Amrani pkt->payload[i].len); 2790abd49676SRam Amrani if (rc) { 2791abd49676SRam Amrani /* If failed not much to do here, partial packet has 2792abd49676SRam Amrani * been posted * we can't free memory, will need to wait 2793abd49676SRam Amrani * for completion 2794abd49676SRam Amrani */ 2795abd49676SRam Amrani DP_ERR(cdev, 2796abd49676SRam Amrani "roce ll2 tx: payload failed (rc=%d)\n", rc); 2797abd49676SRam Amrani return QED_ROCE_TX_FRAG_FAILURE; 2798abd49676SRam Amrani } 2799abd49676SRam Amrani } 2800abd49676SRam Amrani 2801abd49676SRam Amrani return 0; 2802abd49676SRam Amrani } 2803abd49676SRam Amrani 2804abd49676SRam Amrani static int qed_roce_ll2_post_rx_buffer(struct qed_dev *cdev, 2805abd49676SRam Amrani struct qed_roce_ll2_buffer *buf, 2806abd49676SRam Amrani u64 cookie, u8 notify_fw) 2807abd49676SRam Amrani { 2808abd49676SRam Amrani return qed_ll2_post_rx_buffer(QED_LEADING_HWFN(cdev), 2809abd49676SRam Amrani QED_LEADING_HWFN(cdev)->ll2->handle, 2810abd49676SRam Amrani buf->baddr, buf->len, 2811abd49676SRam Amrani (void *)(uintptr_t)cookie, notify_fw); 2812abd49676SRam Amrani } 2813abd49676SRam Amrani 2814abd49676SRam Amrani static int qed_roce_ll2_stats(struct qed_dev *cdev, struct qed_ll2_stats *stats) 2815abd49676SRam Amrani { 2816abd49676SRam Amrani struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2817abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2; 2818abd49676SRam Amrani 2819abd49676SRam Amrani return qed_ll2_get_stats(QED_LEADING_HWFN(cdev), 2820abd49676SRam Amrani roce_ll2->handle, stats); 2821abd49676SRam Amrani } 2822abd49676SRam Amrani 282351ff1725SRam Amrani static const struct qed_rdma_ops qed_rdma_ops_pass = { 282451ff1725SRam Amrani .common = &qed_common_ops_pass, 282551ff1725SRam Amrani .fill_dev_info = &qed_fill_rdma_dev_info, 282651ff1725SRam Amrani .rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx, 282751ff1725SRam Amrani .rdma_init = &qed_rdma_init, 282851ff1725SRam Amrani .rdma_add_user = &qed_rdma_add_user, 282951ff1725SRam Amrani .rdma_remove_user = &qed_rdma_remove_user, 283051ff1725SRam Amrani .rdma_stop = &qed_rdma_stop, 2831c295f86eSRam Amrani .rdma_query_port = &qed_rdma_query_port, 283251ff1725SRam Amrani .rdma_query_device = &qed_rdma_query_device, 283351ff1725SRam Amrani .rdma_get_start_sb = &qed_rdma_get_sb_start, 283451ff1725SRam Amrani .rdma_get_rdma_int = &qed_rdma_get_int, 283551ff1725SRam Amrani .rdma_set_rdma_int = &qed_rdma_set_int, 283651ff1725SRam Amrani .rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix, 283751ff1725SRam Amrani .rdma_cnq_prod_update = &qed_rdma_cnq_prod_update, 2838c295f86eSRam Amrani .rdma_alloc_pd = &qed_rdma_alloc_pd, 2839c295f86eSRam Amrani .rdma_dealloc_pd = &qed_rdma_free_pd, 2840c295f86eSRam Amrani .rdma_create_cq = &qed_rdma_create_cq, 2841c295f86eSRam Amrani .rdma_destroy_cq = &qed_rdma_destroy_cq, 2842f1093940SRam Amrani .rdma_create_qp = &qed_rdma_create_qp, 2843f1093940SRam Amrani .rdma_modify_qp = &qed_rdma_modify_qp, 2844f1093940SRam Amrani .rdma_query_qp = &qed_rdma_query_qp, 2845f1093940SRam Amrani .rdma_destroy_qp = &qed_rdma_destroy_qp, 2846ee8eaea3SRam Amrani .rdma_alloc_tid = &qed_rdma_alloc_tid, 2847ee8eaea3SRam Amrani .rdma_free_tid = &qed_rdma_free_tid, 2848ee8eaea3SRam Amrani .rdma_register_tid = &qed_rdma_register_tid, 2849ee8eaea3SRam Amrani .rdma_deregister_tid = &qed_rdma_deregister_tid, 2850abd49676SRam Amrani .roce_ll2_start = &qed_roce_ll2_start, 2851abd49676SRam Amrani .roce_ll2_stop = &qed_roce_ll2_stop, 2852abd49676SRam Amrani .roce_ll2_tx = &qed_roce_ll2_tx, 2853abd49676SRam Amrani .roce_ll2_post_rx_buffer = &qed_roce_ll2_post_rx_buffer, 2854abd49676SRam Amrani .roce_ll2_set_mac_filter = &qed_roce_ll2_set_mac_filter, 2855abd49676SRam Amrani .roce_ll2_stats = &qed_roce_ll2_stats, 285651ff1725SRam Amrani }; 285751ff1725SRam Amrani 2858d4e99131SArnd Bergmann const struct qed_rdma_ops *qed_get_rdma_ops(void) 285951ff1725SRam Amrani { 286051ff1725SRam Amrani return &qed_rdma_ops_pass; 286151ff1725SRam Amrani } 286251ff1725SRam Amrani EXPORT_SYMBOL(qed_get_rdma_ops); 2863