151ff1725SRam Amrani /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 351ff1725SRam Amrani * 451ff1725SRam Amrani * This software is available to you under a choice of one of two 551ff1725SRam Amrani * licenses. You may choose to be licensed under the terms of the GNU 651ff1725SRam Amrani * General Public License (GPL) Version 2, available from the file 751ff1725SRam Amrani * COPYING in the main directory of this source tree, or the 851ff1725SRam Amrani * OpenIB.org BSD license below: 951ff1725SRam Amrani * 1051ff1725SRam Amrani * Redistribution and use in source and binary forms, with or 1151ff1725SRam Amrani * without modification, are permitted provided that the following 1251ff1725SRam Amrani * conditions are met: 1351ff1725SRam Amrani * 1451ff1725SRam Amrani * - Redistributions of source code must retain the above 1551ff1725SRam Amrani * copyright notice, this list of conditions and the following 1651ff1725SRam Amrani * disclaimer. 1751ff1725SRam Amrani * 1851ff1725SRam Amrani * - Redistributions in binary form must reproduce the above 1951ff1725SRam Amrani * copyright notice, this list of conditions and the following 2051ff1725SRam Amrani * disclaimer in the documentation and /or other materials 2151ff1725SRam Amrani * provided with the distribution. 2251ff1725SRam Amrani * 2351ff1725SRam Amrani * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 2451ff1725SRam Amrani * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 2551ff1725SRam Amrani * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 2651ff1725SRam Amrani * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 2751ff1725SRam Amrani * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 2851ff1725SRam Amrani * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 2951ff1725SRam Amrani * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 3051ff1725SRam Amrani * SOFTWARE. 3151ff1725SRam Amrani */ 3251ff1725SRam Amrani #include <linux/types.h> 3351ff1725SRam Amrani #include <asm/byteorder.h> 3451ff1725SRam Amrani #include <linux/bitops.h> 3551ff1725SRam Amrani #include <linux/delay.h> 3651ff1725SRam Amrani #include <linux/dma-mapping.h> 3751ff1725SRam Amrani #include <linux/errno.h> 3851ff1725SRam Amrani #include <linux/etherdevice.h> 3951ff1725SRam Amrani #include <linux/if_ether.h> 4051ff1725SRam Amrani #include <linux/if_vlan.h> 4151ff1725SRam Amrani #include <linux/io.h> 4251ff1725SRam Amrani #include <linux/ip.h> 4351ff1725SRam Amrani #include <linux/ipv6.h> 4451ff1725SRam Amrani #include <linux/kernel.h> 4551ff1725SRam Amrani #include <linux/list.h> 4651ff1725SRam Amrani #include <linux/module.h> 4751ff1725SRam Amrani #include <linux/mutex.h> 4851ff1725SRam Amrani #include <linux/pci.h> 4951ff1725SRam Amrani #include <linux/slab.h> 5051ff1725SRam Amrani #include <linux/spinlock.h> 5151ff1725SRam Amrani #include <linux/string.h> 5251ff1725SRam Amrani #include <linux/tcp.h> 5351ff1725SRam Amrani #include <linux/bitops.h> 5451ff1725SRam Amrani #include <linux/qed/qed_roce_if.h> 5551ff1725SRam Amrani #include <linux/qed/qed_roce_if.h> 5651ff1725SRam Amrani #include "qed.h" 5751ff1725SRam Amrani #include "qed_cxt.h" 5851ff1725SRam Amrani #include "qed_hsi.h" 5951ff1725SRam Amrani #include "qed_hw.h" 6051ff1725SRam Amrani #include "qed_init_ops.h" 6151ff1725SRam Amrani #include "qed_int.h" 6251ff1725SRam Amrani #include "qed_ll2.h" 6351ff1725SRam Amrani #include "qed_mcp.h" 6451ff1725SRam Amrani #include "qed_reg_addr.h" 6551ff1725SRam Amrani #include "qed_sp.h" 6651ff1725SRam Amrani #include "qed_roce.h" 67abd49676SRam Amrani #include "qed_ll2.h" 6851ff1725SRam Amrani 69be086e7cSMintz, Yuval static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid); 7051ff1725SRam Amrani 71be086e7cSMintz, Yuval void qed_roce_async_event(struct qed_hwfn *p_hwfn, 72be086e7cSMintz, Yuval u8 fw_event_code, union rdma_eqe_data *rdma_data) 73be086e7cSMintz, Yuval { 74be086e7cSMintz, Yuval if (fw_event_code == ROCE_ASYNC_EVENT_DESTROY_QP_DONE) { 75be086e7cSMintz, Yuval u16 icid = 76be086e7cSMintz, Yuval (u16)le32_to_cpu(rdma_data->rdma_destroy_qp_data.cid); 77be086e7cSMintz, Yuval 78be086e7cSMintz, Yuval /* icid release in this async event can occur only if the icid 79be086e7cSMintz, Yuval * was offloaded to the FW. In case it wasn't offloaded this is 80be086e7cSMintz, Yuval * handled in qed_roce_sp_destroy_qp. 81be086e7cSMintz, Yuval */ 82be086e7cSMintz, Yuval qed_roce_free_real_icid(p_hwfn, icid); 83be086e7cSMintz, Yuval } else { 84be086e7cSMintz, Yuval struct qed_rdma_events *events = &p_hwfn->p_rdma_info->events; 85be086e7cSMintz, Yuval 86be086e7cSMintz, Yuval events->affiliated_event(p_hwfn->p_rdma_info->events.context, 87be086e7cSMintz, Yuval fw_event_code, 88be086e7cSMintz, Yuval &rdma_data->async_handle); 89be086e7cSMintz, Yuval } 9051ff1725SRam Amrani } 9151ff1725SRam Amrani 9251ff1725SRam Amrani static int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn, 9351ff1725SRam Amrani struct qed_bmap *bmap, u32 max_count) 9451ff1725SRam Amrani { 9551ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count); 9651ff1725SRam Amrani 9751ff1725SRam Amrani bmap->max_count = max_count; 9851ff1725SRam Amrani 9951ff1725SRam Amrani bmap->bitmap = kzalloc(BITS_TO_LONGS(max_count) * sizeof(long), 10051ff1725SRam Amrani GFP_KERNEL); 10151ff1725SRam Amrani if (!bmap->bitmap) { 10251ff1725SRam Amrani DP_NOTICE(p_hwfn, 10351ff1725SRam Amrani "qed bmap alloc failed: cannot allocate memory (bitmap)\n"); 10451ff1725SRam Amrani return -ENOMEM; 10551ff1725SRam Amrani } 10651ff1725SRam Amrani 10751ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocated bitmap %p\n", 10851ff1725SRam Amrani bmap->bitmap); 10951ff1725SRam Amrani return 0; 11051ff1725SRam Amrani } 11151ff1725SRam Amrani 11251ff1725SRam Amrani static int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn, 11351ff1725SRam Amrani struct qed_bmap *bmap, u32 *id_num) 11451ff1725SRam Amrani { 11551ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "bmap = %p\n", bmap); 11651ff1725SRam Amrani 11751ff1725SRam Amrani *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count); 11851ff1725SRam Amrani 11951ff1725SRam Amrani if (*id_num >= bmap->max_count) { 12051ff1725SRam Amrani DP_NOTICE(p_hwfn, "no id available max_count=%d\n", 12151ff1725SRam Amrani bmap->max_count); 12251ff1725SRam Amrani return -EINVAL; 12351ff1725SRam Amrani } 12451ff1725SRam Amrani 12551ff1725SRam Amrani __set_bit(*id_num, bmap->bitmap); 12651ff1725SRam Amrani 12751ff1725SRam Amrani return 0; 12851ff1725SRam Amrani } 12951ff1725SRam Amrani 130be086e7cSMintz, Yuval static void qed_bmap_set_id(struct qed_hwfn *p_hwfn, 131be086e7cSMintz, Yuval struct qed_bmap *bmap, u32 id_num) 132be086e7cSMintz, Yuval { 133be086e7cSMintz, Yuval if (id_num >= bmap->max_count) 134be086e7cSMintz, Yuval return; 135be086e7cSMintz, Yuval 136be086e7cSMintz, Yuval __set_bit(id_num, bmap->bitmap); 137be086e7cSMintz, Yuval } 138be086e7cSMintz, Yuval 13951ff1725SRam Amrani static void qed_bmap_release_id(struct qed_hwfn *p_hwfn, 14051ff1725SRam Amrani struct qed_bmap *bmap, u32 id_num) 14151ff1725SRam Amrani { 14251ff1725SRam Amrani bool b_acquired; 14351ff1725SRam Amrani 14451ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "id_num = %08x", id_num); 14551ff1725SRam Amrani if (id_num >= bmap->max_count) 14651ff1725SRam Amrani return; 14751ff1725SRam Amrani 14851ff1725SRam Amrani b_acquired = test_and_clear_bit(id_num, bmap->bitmap); 14951ff1725SRam Amrani if (!b_acquired) { 15051ff1725SRam Amrani DP_NOTICE(p_hwfn, "ID %d already released\n", id_num); 15151ff1725SRam Amrani return; 15251ff1725SRam Amrani } 15351ff1725SRam Amrani } 15451ff1725SRam Amrani 155be086e7cSMintz, Yuval static int qed_bmap_test_id(struct qed_hwfn *p_hwfn, 156be086e7cSMintz, Yuval struct qed_bmap *bmap, u32 id_num) 157be086e7cSMintz, Yuval { 158be086e7cSMintz, Yuval if (id_num >= bmap->max_count) 159be086e7cSMintz, Yuval return -1; 160be086e7cSMintz, Yuval 161be086e7cSMintz, Yuval return test_bit(id_num, bmap->bitmap); 162be086e7cSMintz, Yuval } 163be086e7cSMintz, Yuval 1640189efb8SYuval Mintz static u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id) 16551ff1725SRam Amrani { 16651ff1725SRam Amrani /* First sb id for RoCE is after all the l2 sb */ 16751ff1725SRam Amrani return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id; 16851ff1725SRam Amrani } 16951ff1725SRam Amrani 17051ff1725SRam Amrani static int qed_rdma_alloc(struct qed_hwfn *p_hwfn, 17151ff1725SRam Amrani struct qed_ptt *p_ptt, 17251ff1725SRam Amrani struct qed_rdma_start_in_params *params) 17351ff1725SRam Amrani { 17451ff1725SRam Amrani struct qed_rdma_info *p_rdma_info; 17551ff1725SRam Amrani u32 num_cons, num_tasks; 17651ff1725SRam Amrani int rc = -ENOMEM; 17751ff1725SRam Amrani 17851ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n"); 17951ff1725SRam Amrani 18051ff1725SRam Amrani /* Allocate a struct with current pf rdma info */ 18151ff1725SRam Amrani p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL); 18251ff1725SRam Amrani if (!p_rdma_info) { 18351ff1725SRam Amrani DP_NOTICE(p_hwfn, 18451ff1725SRam Amrani "qed rdma alloc failed: cannot allocate memory (rdma info). rc = %d\n", 18551ff1725SRam Amrani rc); 18651ff1725SRam Amrani return rc; 18751ff1725SRam Amrani } 18851ff1725SRam Amrani 18951ff1725SRam Amrani p_hwfn->p_rdma_info = p_rdma_info; 19051ff1725SRam Amrani p_rdma_info->proto = PROTOCOLID_ROCE; 19151ff1725SRam Amrani 1928c93beafSYuval Mintz num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto, 1938c93beafSYuval Mintz NULL); 19451ff1725SRam Amrani 19551ff1725SRam Amrani p_rdma_info->num_qps = num_cons / 2; 19651ff1725SRam Amrani 19751ff1725SRam Amrani num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE); 19851ff1725SRam Amrani 19951ff1725SRam Amrani /* Each MR uses a single task */ 20051ff1725SRam Amrani p_rdma_info->num_mrs = num_tasks; 20151ff1725SRam Amrani 20251ff1725SRam Amrani /* Queue zone lines are shared between RoCE and L2 in such a way that 20351ff1725SRam Amrani * they can be used by each without obstructing the other. 20451ff1725SRam Amrani */ 205be086e7cSMintz, Yuval p_rdma_info->queue_zone_base = (u16)RESC_START(p_hwfn, QED_L2_QUEUE); 206be086e7cSMintz, Yuval p_rdma_info->max_queue_zones = (u16)RESC_NUM(p_hwfn, QED_L2_QUEUE); 20751ff1725SRam Amrani 20851ff1725SRam Amrani /* Allocate a struct with device params and fill it */ 20951ff1725SRam Amrani p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL); 21051ff1725SRam Amrani if (!p_rdma_info->dev) { 21151ff1725SRam Amrani DP_NOTICE(p_hwfn, 21251ff1725SRam Amrani "qed rdma alloc failed: cannot allocate memory (rdma info dev). rc = %d\n", 21351ff1725SRam Amrani rc); 21451ff1725SRam Amrani goto free_rdma_info; 21551ff1725SRam Amrani } 21651ff1725SRam Amrani 21751ff1725SRam Amrani /* Allocate a struct with port params and fill it */ 21851ff1725SRam Amrani p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL); 21951ff1725SRam Amrani if (!p_rdma_info->port) { 22051ff1725SRam Amrani DP_NOTICE(p_hwfn, 22151ff1725SRam Amrani "qed rdma alloc failed: cannot allocate memory (rdma info port). rc = %d\n", 22251ff1725SRam Amrani rc); 22351ff1725SRam Amrani goto free_rdma_dev; 22451ff1725SRam Amrani } 22551ff1725SRam Amrani 22651ff1725SRam Amrani /* Allocate bit map for pd's */ 22751ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS); 22851ff1725SRam Amrani if (rc) { 22951ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 23051ff1725SRam Amrani "Failed to allocate pd_map, rc = %d\n", 23151ff1725SRam Amrani rc); 23251ff1725SRam Amrani goto free_rdma_port; 23351ff1725SRam Amrani } 23451ff1725SRam Amrani 23551ff1725SRam Amrani /* Allocate DPI bitmap */ 23651ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map, 23751ff1725SRam Amrani p_hwfn->dpi_count); 23851ff1725SRam Amrani if (rc) { 23951ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 24051ff1725SRam Amrani "Failed to allocate DPI bitmap, rc = %d\n", rc); 24151ff1725SRam Amrani goto free_pd_map; 24251ff1725SRam Amrani } 24351ff1725SRam Amrani 24451ff1725SRam Amrani /* Allocate bitmap for cq's. The maximum number of CQs is bounded to 24551ff1725SRam Amrani * twice the number of QPs. 24651ff1725SRam Amrani */ 24751ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map, 24851ff1725SRam Amrani p_rdma_info->num_qps * 2); 24951ff1725SRam Amrani if (rc) { 25051ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 25151ff1725SRam Amrani "Failed to allocate cq bitmap, rc = %d\n", rc); 25251ff1725SRam Amrani goto free_dpi_map; 25351ff1725SRam Amrani } 25451ff1725SRam Amrani 25551ff1725SRam Amrani /* Allocate bitmap for toggle bit for cq icids 25651ff1725SRam Amrani * We toggle the bit every time we create or resize cq for a given icid. 25751ff1725SRam Amrani * The maximum number of CQs is bounded to twice the number of QPs. 25851ff1725SRam Amrani */ 25951ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits, 26051ff1725SRam Amrani p_rdma_info->num_qps * 2); 26151ff1725SRam Amrani if (rc) { 26251ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 26351ff1725SRam Amrani "Failed to allocate toogle bits, rc = %d\n", rc); 26451ff1725SRam Amrani goto free_cq_map; 26551ff1725SRam Amrani } 26651ff1725SRam Amrani 26751ff1725SRam Amrani /* Allocate bitmap for itids */ 26851ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map, 26951ff1725SRam Amrani p_rdma_info->num_mrs); 27051ff1725SRam Amrani if (rc) { 27151ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 27251ff1725SRam Amrani "Failed to allocate itids bitmaps, rc = %d\n", rc); 27351ff1725SRam Amrani goto free_toggle_map; 27451ff1725SRam Amrani } 27551ff1725SRam Amrani 27651ff1725SRam Amrani /* Allocate bitmap for cids used for qps. */ 27751ff1725SRam Amrani rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons); 27851ff1725SRam Amrani if (rc) { 27951ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 28051ff1725SRam Amrani "Failed to allocate cid bitmap, rc = %d\n", rc); 28151ff1725SRam Amrani goto free_tid_map; 28251ff1725SRam Amrani } 28351ff1725SRam Amrani 284be086e7cSMintz, Yuval /* Allocate bitmap for cids used for responders/requesters. */ 285be086e7cSMintz, Yuval rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->real_cid_map, num_cons); 286be086e7cSMintz, Yuval if (rc) { 287be086e7cSMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 288be086e7cSMintz, Yuval "Failed to allocate real cid bitmap, rc = %d\n", rc); 289be086e7cSMintz, Yuval goto free_cid_map; 290be086e7cSMintz, Yuval } 29151ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n"); 29251ff1725SRam Amrani return 0; 29351ff1725SRam Amrani 294be086e7cSMintz, Yuval free_cid_map: 295be086e7cSMintz, Yuval kfree(p_rdma_info->cid_map.bitmap); 29651ff1725SRam Amrani free_tid_map: 29751ff1725SRam Amrani kfree(p_rdma_info->tid_map.bitmap); 29851ff1725SRam Amrani free_toggle_map: 29951ff1725SRam Amrani kfree(p_rdma_info->toggle_bits.bitmap); 30051ff1725SRam Amrani free_cq_map: 30151ff1725SRam Amrani kfree(p_rdma_info->cq_map.bitmap); 30251ff1725SRam Amrani free_dpi_map: 30351ff1725SRam Amrani kfree(p_rdma_info->dpi_map.bitmap); 30451ff1725SRam Amrani free_pd_map: 30551ff1725SRam Amrani kfree(p_rdma_info->pd_map.bitmap); 30651ff1725SRam Amrani free_rdma_port: 30751ff1725SRam Amrani kfree(p_rdma_info->port); 30851ff1725SRam Amrani free_rdma_dev: 30951ff1725SRam Amrani kfree(p_rdma_info->dev); 31051ff1725SRam Amrani free_rdma_info: 31151ff1725SRam Amrani kfree(p_rdma_info); 31251ff1725SRam Amrani 31351ff1725SRam Amrani return rc; 31451ff1725SRam Amrani } 31551ff1725SRam Amrani 3160189efb8SYuval Mintz static void qed_rdma_resc_free(struct qed_hwfn *p_hwfn) 31751ff1725SRam Amrani { 318be086e7cSMintz, Yuval struct qed_bmap *rcid_map = &p_hwfn->p_rdma_info->real_cid_map; 31951ff1725SRam Amrani struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 320be086e7cSMintz, Yuval int wait_count = 0; 321be086e7cSMintz, Yuval 322be086e7cSMintz, Yuval /* when destroying a_RoCE QP the control is returned to the user after 323be086e7cSMintz, Yuval * the synchronous part. The asynchronous part may take a little longer. 324be086e7cSMintz, Yuval * We delay for a short while if an async destroy QP is still expected. 325be086e7cSMintz, Yuval * Beyond the added delay we clear the bitmap anyway. 326be086e7cSMintz, Yuval */ 327be086e7cSMintz, Yuval while (bitmap_weight(rcid_map->bitmap, rcid_map->max_count)) { 328be086e7cSMintz, Yuval msleep(100); 329be086e7cSMintz, Yuval if (wait_count++ > 20) { 330be086e7cSMintz, Yuval DP_NOTICE(p_hwfn, "cid bitmap wait timed out\n"); 331be086e7cSMintz, Yuval break; 332be086e7cSMintz, Yuval } 333be086e7cSMintz, Yuval } 33451ff1725SRam Amrani 33551ff1725SRam Amrani kfree(p_rdma_info->cid_map.bitmap); 33651ff1725SRam Amrani kfree(p_rdma_info->tid_map.bitmap); 33751ff1725SRam Amrani kfree(p_rdma_info->toggle_bits.bitmap); 33851ff1725SRam Amrani kfree(p_rdma_info->cq_map.bitmap); 33951ff1725SRam Amrani kfree(p_rdma_info->dpi_map.bitmap); 34051ff1725SRam Amrani kfree(p_rdma_info->pd_map.bitmap); 34151ff1725SRam Amrani 34251ff1725SRam Amrani kfree(p_rdma_info->port); 34351ff1725SRam Amrani kfree(p_rdma_info->dev); 34451ff1725SRam Amrani 34551ff1725SRam Amrani kfree(p_rdma_info); 34651ff1725SRam Amrani } 34751ff1725SRam Amrani 34851ff1725SRam Amrani static void qed_rdma_free(struct qed_hwfn *p_hwfn) 34951ff1725SRam Amrani { 35051ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n"); 35151ff1725SRam Amrani 35251ff1725SRam Amrani qed_rdma_resc_free(p_hwfn); 35351ff1725SRam Amrani } 35451ff1725SRam Amrani 35551ff1725SRam Amrani static void qed_rdma_get_guid(struct qed_hwfn *p_hwfn, u8 *guid) 35651ff1725SRam Amrani { 35751ff1725SRam Amrani guid[0] = p_hwfn->hw_info.hw_mac_addr[0] ^ 2; 35851ff1725SRam Amrani guid[1] = p_hwfn->hw_info.hw_mac_addr[1]; 35951ff1725SRam Amrani guid[2] = p_hwfn->hw_info.hw_mac_addr[2]; 36051ff1725SRam Amrani guid[3] = 0xff; 36151ff1725SRam Amrani guid[4] = 0xfe; 36251ff1725SRam Amrani guid[5] = p_hwfn->hw_info.hw_mac_addr[3]; 36351ff1725SRam Amrani guid[6] = p_hwfn->hw_info.hw_mac_addr[4]; 36451ff1725SRam Amrani guid[7] = p_hwfn->hw_info.hw_mac_addr[5]; 36551ff1725SRam Amrani } 36651ff1725SRam Amrani 36751ff1725SRam Amrani static void qed_rdma_init_events(struct qed_hwfn *p_hwfn, 36851ff1725SRam Amrani struct qed_rdma_start_in_params *params) 36951ff1725SRam Amrani { 37051ff1725SRam Amrani struct qed_rdma_events *events; 37151ff1725SRam Amrani 37251ff1725SRam Amrani events = &p_hwfn->p_rdma_info->events; 37351ff1725SRam Amrani 37451ff1725SRam Amrani events->unaffiliated_event = params->events->unaffiliated_event; 37551ff1725SRam Amrani events->affiliated_event = params->events->affiliated_event; 37651ff1725SRam Amrani events->context = params->events->context; 37751ff1725SRam Amrani } 37851ff1725SRam Amrani 37951ff1725SRam Amrani static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn, 38051ff1725SRam Amrani struct qed_rdma_start_in_params *params) 38151ff1725SRam Amrani { 38251ff1725SRam Amrani struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 38351ff1725SRam Amrani struct qed_dev *cdev = p_hwfn->cdev; 38451ff1725SRam Amrani u32 pci_status_control; 38551ff1725SRam Amrani u32 num_qps; 38651ff1725SRam Amrani 38751ff1725SRam Amrani /* Vendor specific information */ 38851ff1725SRam Amrani dev->vendor_id = cdev->vendor_id; 38951ff1725SRam Amrani dev->vendor_part_id = cdev->device_id; 39051ff1725SRam Amrani dev->hw_ver = 0; 39151ff1725SRam Amrani dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | 39251ff1725SRam Amrani (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION); 39351ff1725SRam Amrani 39451ff1725SRam Amrani qed_rdma_get_guid(p_hwfn, (u8 *)&dev->sys_image_guid); 39551ff1725SRam Amrani dev->node_guid = dev->sys_image_guid; 39651ff1725SRam Amrani 39751ff1725SRam Amrani dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE, 39851ff1725SRam Amrani RDMA_MAX_SGE_PER_RQ_WQE); 39951ff1725SRam Amrani 40051ff1725SRam Amrani if (cdev->rdma_max_sge) 40151ff1725SRam Amrani dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge); 40251ff1725SRam Amrani 40351ff1725SRam Amrani dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE; 40451ff1725SRam Amrani 40551ff1725SRam Amrani dev->max_inline = (cdev->rdma_max_inline) ? 40651ff1725SRam Amrani min_t(u32, cdev->rdma_max_inline, dev->max_inline) : 40751ff1725SRam Amrani dev->max_inline; 40851ff1725SRam Amrani 40951ff1725SRam Amrani dev->max_wqe = QED_RDMA_MAX_WQE; 41051ff1725SRam Amrani dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ); 41151ff1725SRam Amrani 41251ff1725SRam Amrani /* The number of QPs may be higher than QED_ROCE_MAX_QPS, because 41351ff1725SRam Amrani * it is up-aligned to 16 and then to ILT page size within qed cxt. 41451ff1725SRam Amrani * This is OK in terms of ILT but we don't want to configure the FW 41551ff1725SRam Amrani * above its abilities 41651ff1725SRam Amrani */ 41751ff1725SRam Amrani num_qps = ROCE_MAX_QPS; 41851ff1725SRam Amrani num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps); 41951ff1725SRam Amrani dev->max_qp = num_qps; 42051ff1725SRam Amrani 42151ff1725SRam Amrani /* CQs uses the same icids that QPs use hence they are limited by the 42251ff1725SRam Amrani * number of icids. There are two icids per QP. 42351ff1725SRam Amrani */ 42451ff1725SRam Amrani dev->max_cq = num_qps * 2; 42551ff1725SRam Amrani 42651ff1725SRam Amrani /* The number of mrs is smaller by 1 since the first is reserved */ 42751ff1725SRam Amrani dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1; 42851ff1725SRam Amrani dev->max_mr_size = QED_RDMA_MAX_MR_SIZE; 42951ff1725SRam Amrani 43051ff1725SRam Amrani /* The maximum CQE capacity per CQ supported. 43151ff1725SRam Amrani * max number of cqes will be in two layer pbl, 43251ff1725SRam Amrani * 8 is the pointer size in bytes 43351ff1725SRam Amrani * 32 is the size of cq element in bytes 43451ff1725SRam Amrani */ 43551ff1725SRam Amrani if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS) 43651ff1725SRam Amrani dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT; 43751ff1725SRam Amrani else 43851ff1725SRam Amrani dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT; 43951ff1725SRam Amrani 44051ff1725SRam Amrani dev->max_mw = 0; 44151ff1725SRam Amrani dev->max_fmr = QED_RDMA_MAX_FMR; 44251ff1725SRam Amrani dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8); 44351ff1725SRam Amrani dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE; 44451ff1725SRam Amrani dev->max_pkey = QED_RDMA_MAX_P_KEY; 44551ff1725SRam Amrani 44651ff1725SRam Amrani dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 44751ff1725SRam Amrani (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2); 44851ff1725SRam Amrani dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 44951ff1725SRam Amrani RDMA_REQ_RD_ATOMIC_ELM_SIZE; 45051ff1725SRam Amrani dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc * 45151ff1725SRam Amrani p_hwfn->p_rdma_info->num_qps; 45251ff1725SRam Amrani dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS; 45351ff1725SRam Amrani dev->dev_ack_delay = QED_RDMA_ACK_DELAY; 45451ff1725SRam Amrani dev->max_pd = RDMA_MAX_PDS; 45551ff1725SRam Amrani dev->max_ah = p_hwfn->p_rdma_info->num_qps; 45651ff1725SRam Amrani dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE); 45751ff1725SRam Amrani 45851ff1725SRam Amrani /* Set capablities */ 45951ff1725SRam Amrani dev->dev_caps = 0; 46051ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1); 46151ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1); 46251ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1); 46351ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1); 46451ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1); 46551ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1); 46651ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1); 46751ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1); 46851ff1725SRam Amrani 46951ff1725SRam Amrani /* Check atomic operations support in PCI configuration space. */ 47051ff1725SRam Amrani pci_read_config_dword(cdev->pdev, 47151ff1725SRam Amrani cdev->pdev->pcie_cap + PCI_EXP_DEVCTL2, 47251ff1725SRam Amrani &pci_status_control); 47351ff1725SRam Amrani 47451ff1725SRam Amrani if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN) 47551ff1725SRam Amrani SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1); 47651ff1725SRam Amrani } 47751ff1725SRam Amrani 47851ff1725SRam Amrani static void qed_rdma_init_port(struct qed_hwfn *p_hwfn) 47951ff1725SRam Amrani { 48051ff1725SRam Amrani struct qed_rdma_port *port = p_hwfn->p_rdma_info->port; 48151ff1725SRam Amrani struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 48251ff1725SRam Amrani 48351ff1725SRam Amrani port->port_state = p_hwfn->mcp_info->link_output.link_up ? 48451ff1725SRam Amrani QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN; 48551ff1725SRam Amrani 48651ff1725SRam Amrani port->max_msg_size = min_t(u64, 48751ff1725SRam Amrani (dev->max_mr_mw_fmr_size * 48851ff1725SRam Amrani p_hwfn->cdev->rdma_max_sge), 48951ff1725SRam Amrani BIT(31)); 49051ff1725SRam Amrani 49151ff1725SRam Amrani port->pkey_bad_counter = 0; 49251ff1725SRam Amrani } 49351ff1725SRam Amrani 49451ff1725SRam Amrani static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 49551ff1725SRam Amrani { 49651ff1725SRam Amrani u32 ll2_ethertype_en; 49751ff1725SRam Amrani 49851ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n"); 49951ff1725SRam Amrani p_hwfn->b_rdma_enabled_in_prs = false; 50051ff1725SRam Amrani 50151ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 50251ff1725SRam Amrani 50351ff1725SRam Amrani p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE; 50451ff1725SRam Amrani 50551ff1725SRam Amrani /* We delay writing to this reg until first cid is allocated. See 50651ff1725SRam Amrani * qed_cxt_dynamic_ilt_alloc function for more details 50751ff1725SRam Amrani */ 50851ff1725SRam Amrani ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 50951ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 51051ff1725SRam Amrani (ll2_ethertype_en | 0x01)); 51151ff1725SRam Amrani 51251ff1725SRam Amrani if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) { 51351ff1725SRam Amrani DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n"); 51451ff1725SRam Amrani return -EINVAL; 51551ff1725SRam Amrani } 51651ff1725SRam Amrani 51751ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n"); 51851ff1725SRam Amrani return 0; 51951ff1725SRam Amrani } 52051ff1725SRam Amrani 52151ff1725SRam Amrani static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn, 52251ff1725SRam Amrani struct qed_rdma_start_in_params *params, 52351ff1725SRam Amrani struct qed_ptt *p_ptt) 52451ff1725SRam Amrani { 52551ff1725SRam Amrani struct rdma_init_func_ramrod_data *p_ramrod; 52651ff1725SRam Amrani struct qed_rdma_cnq_params *p_cnq_pbl_list; 52751ff1725SRam Amrani struct rdma_init_func_hdr *p_params_header; 52851ff1725SRam Amrani struct rdma_cnq_params *p_cnq_params; 52951ff1725SRam Amrani struct qed_sp_init_data init_data; 53051ff1725SRam Amrani struct qed_spq_entry *p_ent; 53151ff1725SRam Amrani u32 cnq_id, sb_id; 53251ff1725SRam Amrani int rc; 53351ff1725SRam Amrani 53451ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n"); 53551ff1725SRam Amrani 53651ff1725SRam Amrani /* Save the number of cnqs for the function close ramrod */ 53751ff1725SRam Amrani p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq; 53851ff1725SRam Amrani 53951ff1725SRam Amrani /* Get SPQ entry */ 54051ff1725SRam Amrani memset(&init_data, 0, sizeof(init_data)); 54151ff1725SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 54251ff1725SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 54351ff1725SRam Amrani 54451ff1725SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT, 54551ff1725SRam Amrani p_hwfn->p_rdma_info->proto, &init_data); 54651ff1725SRam Amrani if (rc) 54751ff1725SRam Amrani return rc; 54851ff1725SRam Amrani 54951ff1725SRam Amrani p_ramrod = &p_ent->ramrod.roce_init_func.rdma; 55051ff1725SRam Amrani 55151ff1725SRam Amrani p_params_header = &p_ramrod->params_header; 55251ff1725SRam Amrani p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn, 55351ff1725SRam Amrani QED_RDMA_CNQ_RAM); 55451ff1725SRam Amrani p_params_header->num_cnqs = params->desired_cnq; 55551ff1725SRam Amrani 55651ff1725SRam Amrani if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS) 55751ff1725SRam Amrani p_params_header->cq_ring_mode = 1; 55851ff1725SRam Amrani else 55951ff1725SRam Amrani p_params_header->cq_ring_mode = 0; 56051ff1725SRam Amrani 56151ff1725SRam Amrani for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) { 56251ff1725SRam Amrani sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id); 56351ff1725SRam Amrani p_cnq_params = &p_ramrod->cnq_params[cnq_id]; 56451ff1725SRam Amrani p_cnq_pbl_list = ¶ms->cnq_pbl_list[cnq_id]; 56551ff1725SRam Amrani p_cnq_params->sb_num = 56651ff1725SRam Amrani cpu_to_le16(p_hwfn->sbs_info[sb_id]->igu_sb_id); 56751ff1725SRam Amrani 56851ff1725SRam Amrani p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi; 56951ff1725SRam Amrani p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages; 57051ff1725SRam Amrani 57151ff1725SRam Amrani DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr, 57251ff1725SRam Amrani p_cnq_pbl_list->pbl_ptr); 57351ff1725SRam Amrani 57451ff1725SRam Amrani /* we assume here that cnq_id and qz_offset are the same */ 57551ff1725SRam Amrani p_cnq_params->queue_zone_num = 57651ff1725SRam Amrani cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base + 57751ff1725SRam Amrani cnq_id); 57851ff1725SRam Amrani } 57951ff1725SRam Amrani 58051ff1725SRam Amrani return qed_spq_post(p_hwfn, p_ent, NULL); 58151ff1725SRam Amrani } 58251ff1725SRam Amrani 5830189efb8SYuval Mintz static int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid) 5840189efb8SYuval Mintz { 5850189efb8SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 5860189efb8SYuval Mintz int rc; 5870189efb8SYuval Mintz 5880189efb8SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n"); 5890189efb8SYuval Mintz 5900189efb8SYuval Mintz spin_lock_bh(&p_hwfn->p_rdma_info->lock); 5910189efb8SYuval Mintz rc = qed_rdma_bmap_alloc_id(p_hwfn, 5920189efb8SYuval Mintz &p_hwfn->p_rdma_info->tid_map, itid); 5930189efb8SYuval Mintz spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 5940189efb8SYuval Mintz if (rc) 5950189efb8SYuval Mintz goto out; 5960189efb8SYuval Mintz 5970189efb8SYuval Mintz rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid); 5980189efb8SYuval Mintz out: 5990189efb8SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc); 6000189efb8SYuval Mintz return rc; 6010189efb8SYuval Mintz } 6020189efb8SYuval Mintz 60351ff1725SRam Amrani static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn) 60451ff1725SRam Amrani { 60551ff1725SRam Amrani struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 60651ff1725SRam Amrani 60751ff1725SRam Amrani /* The first DPI is reserved for the Kernel */ 60851ff1725SRam Amrani __set_bit(0, p_hwfn->p_rdma_info->dpi_map.bitmap); 60951ff1725SRam Amrani 61051ff1725SRam Amrani /* Tid 0 will be used as the key for "reserved MR". 61151ff1725SRam Amrani * The driver should allocate memory for it so it can be loaded but no 61251ff1725SRam Amrani * ramrod should be passed on it. 61351ff1725SRam Amrani */ 61451ff1725SRam Amrani qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey); 61551ff1725SRam Amrani if (dev->reserved_lkey != RDMA_RESERVED_LKEY) { 61651ff1725SRam Amrani DP_NOTICE(p_hwfn, 61751ff1725SRam Amrani "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n"); 61851ff1725SRam Amrani return -EINVAL; 61951ff1725SRam Amrani } 62051ff1725SRam Amrani 62151ff1725SRam Amrani return 0; 62251ff1725SRam Amrani } 62351ff1725SRam Amrani 62451ff1725SRam Amrani static int qed_rdma_setup(struct qed_hwfn *p_hwfn, 62551ff1725SRam Amrani struct qed_ptt *p_ptt, 62651ff1725SRam Amrani struct qed_rdma_start_in_params *params) 62751ff1725SRam Amrani { 62851ff1725SRam Amrani int rc; 62951ff1725SRam Amrani 63051ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n"); 63151ff1725SRam Amrani 63251ff1725SRam Amrani spin_lock_init(&p_hwfn->p_rdma_info->lock); 63351ff1725SRam Amrani 63451ff1725SRam Amrani qed_rdma_init_devinfo(p_hwfn, params); 63551ff1725SRam Amrani qed_rdma_init_port(p_hwfn); 63651ff1725SRam Amrani qed_rdma_init_events(p_hwfn, params); 63751ff1725SRam Amrani 63851ff1725SRam Amrani rc = qed_rdma_reserve_lkey(p_hwfn); 63951ff1725SRam Amrani if (rc) 64051ff1725SRam Amrani return rc; 64151ff1725SRam Amrani 64251ff1725SRam Amrani rc = qed_rdma_init_hw(p_hwfn, p_ptt); 64351ff1725SRam Amrani if (rc) 64451ff1725SRam Amrani return rc; 64551ff1725SRam Amrani 64651ff1725SRam Amrani return qed_rdma_start_fw(p_hwfn, params, p_ptt); 64751ff1725SRam Amrani } 64851ff1725SRam Amrani 6490189efb8SYuval Mintz static int qed_rdma_stop(void *rdma_cxt) 65051ff1725SRam Amrani { 65151ff1725SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 65251ff1725SRam Amrani struct rdma_close_func_ramrod_data *p_ramrod; 65351ff1725SRam Amrani struct qed_sp_init_data init_data; 65451ff1725SRam Amrani struct qed_spq_entry *p_ent; 65551ff1725SRam Amrani struct qed_ptt *p_ptt; 65651ff1725SRam Amrani u32 ll2_ethertype_en; 65751ff1725SRam Amrani int rc = -EBUSY; 65851ff1725SRam Amrani 65951ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n"); 66051ff1725SRam Amrani 66151ff1725SRam Amrani p_ptt = qed_ptt_acquire(p_hwfn); 66251ff1725SRam Amrani if (!p_ptt) { 66351ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n"); 66451ff1725SRam Amrani return rc; 66551ff1725SRam Amrani } 66651ff1725SRam Amrani 66751ff1725SRam Amrani /* Disable RoCE search */ 66851ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0); 66951ff1725SRam Amrani p_hwfn->b_rdma_enabled_in_prs = false; 67051ff1725SRam Amrani 67151ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 67251ff1725SRam Amrani 67351ff1725SRam Amrani ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 67451ff1725SRam Amrani 67551ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 67651ff1725SRam Amrani (ll2_ethertype_en & 0xFFFE)); 67751ff1725SRam Amrani 67851ff1725SRam Amrani qed_ptt_release(p_hwfn, p_ptt); 67951ff1725SRam Amrani 68051ff1725SRam Amrani /* Get SPQ entry */ 68151ff1725SRam Amrani memset(&init_data, 0, sizeof(init_data)); 68251ff1725SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 68351ff1725SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 68451ff1725SRam Amrani 68551ff1725SRam Amrani /* Stop RoCE */ 68651ff1725SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE, 68751ff1725SRam Amrani p_hwfn->p_rdma_info->proto, &init_data); 68851ff1725SRam Amrani if (rc) 68951ff1725SRam Amrani goto out; 69051ff1725SRam Amrani 69151ff1725SRam Amrani p_ramrod = &p_ent->ramrod.rdma_close_func; 69251ff1725SRam Amrani 69351ff1725SRam Amrani p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs; 69451ff1725SRam Amrani p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM); 69551ff1725SRam Amrani 69651ff1725SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 69751ff1725SRam Amrani 69851ff1725SRam Amrani out: 69951ff1725SRam Amrani qed_rdma_free(p_hwfn); 70051ff1725SRam Amrani 70151ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc); 70251ff1725SRam Amrani return rc; 70351ff1725SRam Amrani } 70451ff1725SRam Amrani 7050189efb8SYuval Mintz static int qed_rdma_add_user(void *rdma_cxt, 70651ff1725SRam Amrani struct qed_rdma_add_user_out_params *out_params) 70751ff1725SRam Amrani { 70851ff1725SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 70951ff1725SRam Amrani u32 dpi_start_offset; 71051ff1725SRam Amrani u32 returned_id = 0; 71151ff1725SRam Amrani int rc; 71251ff1725SRam Amrani 71351ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n"); 71451ff1725SRam Amrani 71551ff1725SRam Amrani /* Allocate DPI */ 71651ff1725SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 71751ff1725SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 71851ff1725SRam Amrani &returned_id); 71951ff1725SRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 72051ff1725SRam Amrani 72151ff1725SRam Amrani out_params->dpi = (u16)returned_id; 72251ff1725SRam Amrani 72351ff1725SRam Amrani /* Calculate the corresponding DPI address */ 72451ff1725SRam Amrani dpi_start_offset = p_hwfn->dpi_start_offset; 72551ff1725SRam Amrani 72651ff1725SRam Amrani out_params->dpi_addr = (u64)((u8 __iomem *)p_hwfn->doorbells + 72751ff1725SRam Amrani dpi_start_offset + 72851ff1725SRam Amrani ((out_params->dpi) * p_hwfn->dpi_size)); 72951ff1725SRam Amrani 73051ff1725SRam Amrani out_params->dpi_phys_addr = p_hwfn->cdev->db_phys_addr + 73151ff1725SRam Amrani dpi_start_offset + 73251ff1725SRam Amrani ((out_params->dpi) * p_hwfn->dpi_size); 73351ff1725SRam Amrani 73451ff1725SRam Amrani out_params->dpi_size = p_hwfn->dpi_size; 73551ff1725SRam Amrani 73651ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc); 73751ff1725SRam Amrani return rc; 73851ff1725SRam Amrani } 73951ff1725SRam Amrani 7400189efb8SYuval Mintz static struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt) 741c295f86eSRam Amrani { 742c295f86eSRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 743c295f86eSRam Amrani struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port; 744c295f86eSRam Amrani 745c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n"); 746c295f86eSRam Amrani 747c295f86eSRam Amrani /* Link may have changed */ 748c295f86eSRam Amrani p_port->port_state = p_hwfn->mcp_info->link_output.link_up ? 749c295f86eSRam Amrani QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN; 750c295f86eSRam Amrani 751c295f86eSRam Amrani p_port->link_speed = p_hwfn->mcp_info->link_output.speed; 752c295f86eSRam Amrani 753793ea8a9SRam Amrani p_port->max_msg_size = RDMA_MAX_DATA_SIZE_IN_WQE; 754793ea8a9SRam Amrani 755c295f86eSRam Amrani return p_port; 756c295f86eSRam Amrani } 757c295f86eSRam Amrani 7580189efb8SYuval Mintz static struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt) 75951ff1725SRam Amrani { 76051ff1725SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 76151ff1725SRam Amrani 76251ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n"); 76351ff1725SRam Amrani 76451ff1725SRam Amrani /* Return struct with device parameters */ 76551ff1725SRam Amrani return p_hwfn->p_rdma_info->dev; 76651ff1725SRam Amrani } 76751ff1725SRam Amrani 7680189efb8SYuval Mintz static void qed_rdma_free_tid(void *rdma_cxt, u32 itid) 769ee8eaea3SRam Amrani { 770ee8eaea3SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 771ee8eaea3SRam Amrani 772ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 773ee8eaea3SRam Amrani 774ee8eaea3SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 775ee8eaea3SRam Amrani qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->tid_map, itid); 776ee8eaea3SRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 777ee8eaea3SRam Amrani } 778ee8eaea3SRam Amrani 7790189efb8SYuval Mintz static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod) 78051ff1725SRam Amrani { 78151ff1725SRam Amrani struct qed_hwfn *p_hwfn; 78251ff1725SRam Amrani u16 qz_num; 78351ff1725SRam Amrani u32 addr; 78451ff1725SRam Amrani 78551ff1725SRam Amrani p_hwfn = (struct qed_hwfn *)rdma_cxt; 786be086e7cSMintz, Yuval 787be086e7cSMintz, Yuval if (qz_offset > p_hwfn->p_rdma_info->max_queue_zones) { 788be086e7cSMintz, Yuval DP_NOTICE(p_hwfn, 789be086e7cSMintz, Yuval "queue zone offset %d is too large (max is %d)\n", 790be086e7cSMintz, Yuval qz_offset, p_hwfn->p_rdma_info->max_queue_zones); 791be086e7cSMintz, Yuval return; 792be086e7cSMintz, Yuval } 793be086e7cSMintz, Yuval 79451ff1725SRam Amrani qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset; 79551ff1725SRam Amrani addr = GTT_BAR0_MAP_REG_USDM_RAM + 79651ff1725SRam Amrani USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num); 79751ff1725SRam Amrani 79851ff1725SRam Amrani REG_WR16(p_hwfn, addr, prod); 79951ff1725SRam Amrani 80051ff1725SRam Amrani /* keep prod updates ordered */ 80151ff1725SRam Amrani wmb(); 80251ff1725SRam Amrani } 80351ff1725SRam Amrani 80451ff1725SRam Amrani static int qed_fill_rdma_dev_info(struct qed_dev *cdev, 80551ff1725SRam Amrani struct qed_dev_rdma_info *info) 80651ff1725SRam Amrani { 80751ff1725SRam Amrani memset(info, 0, sizeof(*info)); 80851ff1725SRam Amrani 80951ff1725SRam Amrani info->rdma_type = QED_RDMA_TYPE_ROCE; 81051ff1725SRam Amrani 81151ff1725SRam Amrani qed_fill_dev_info(cdev, &info->common); 81251ff1725SRam Amrani 81351ff1725SRam Amrani return 0; 81451ff1725SRam Amrani } 81551ff1725SRam Amrani 81651ff1725SRam Amrani static int qed_rdma_get_sb_start(struct qed_dev *cdev) 81751ff1725SRam Amrani { 81851ff1725SRam Amrani int feat_num; 81951ff1725SRam Amrani 82051ff1725SRam Amrani if (cdev->num_hwfns > 1) 82151ff1725SRam Amrani feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE); 82251ff1725SRam Amrani else 82351ff1725SRam Amrani feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE) * 82451ff1725SRam Amrani cdev->num_hwfns; 82551ff1725SRam Amrani 82651ff1725SRam Amrani return feat_num; 82751ff1725SRam Amrani } 82851ff1725SRam Amrani 82951ff1725SRam Amrani static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev) 83051ff1725SRam Amrani { 83151ff1725SRam Amrani int n_cnq = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_RDMA_CNQ); 83251ff1725SRam Amrani int n_msix = cdev->int_params.rdma_msix_cnt; 83351ff1725SRam Amrani 83451ff1725SRam Amrani return min_t(int, n_cnq, n_msix); 83551ff1725SRam Amrani } 83651ff1725SRam Amrani 83751ff1725SRam Amrani static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt) 83851ff1725SRam Amrani { 83951ff1725SRam Amrani int limit = 0; 84051ff1725SRam Amrani 84151ff1725SRam Amrani /* Mark the fastpath as free/used */ 84251ff1725SRam Amrani cdev->int_params.fp_initialized = cnt ? true : false; 84351ff1725SRam Amrani 84451ff1725SRam Amrani if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) { 84551ff1725SRam Amrani DP_ERR(cdev, 84651ff1725SRam Amrani "qed roce supports only MSI-X interrupts (detected %d).\n", 84751ff1725SRam Amrani cdev->int_params.out.int_mode); 84851ff1725SRam Amrani return -EINVAL; 84951ff1725SRam Amrani } else if (cdev->int_params.fp_msix_cnt) { 85051ff1725SRam Amrani limit = cdev->int_params.rdma_msix_cnt; 85151ff1725SRam Amrani } 85251ff1725SRam Amrani 85351ff1725SRam Amrani if (!limit) 85451ff1725SRam Amrani return -ENOMEM; 85551ff1725SRam Amrani 85651ff1725SRam Amrani return min_t(int, cnt, limit); 85751ff1725SRam Amrani } 85851ff1725SRam Amrani 85951ff1725SRam Amrani static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info) 86051ff1725SRam Amrani { 86151ff1725SRam Amrani memset(info, 0, sizeof(*info)); 86251ff1725SRam Amrani 86351ff1725SRam Amrani if (!cdev->int_params.fp_initialized) { 86451ff1725SRam Amrani DP_INFO(cdev, 86551ff1725SRam Amrani "Protocol driver requested interrupt information, but its support is not yet configured\n"); 86651ff1725SRam Amrani return -EINVAL; 86751ff1725SRam Amrani } 86851ff1725SRam Amrani 86951ff1725SRam Amrani if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 87051ff1725SRam Amrani int msix_base = cdev->int_params.rdma_msix_base; 87151ff1725SRam Amrani 87251ff1725SRam Amrani info->msix_cnt = cdev->int_params.rdma_msix_cnt; 87351ff1725SRam Amrani info->msix = &cdev->int_params.msix_table[msix_base]; 87451ff1725SRam Amrani 87551ff1725SRam Amrani DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n", 87651ff1725SRam Amrani info->msix_cnt, msix_base); 87751ff1725SRam Amrani } 87851ff1725SRam Amrani 87951ff1725SRam Amrani return 0; 88051ff1725SRam Amrani } 88151ff1725SRam Amrani 8820189efb8SYuval Mintz static int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd) 883c295f86eSRam Amrani { 884c295f86eSRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 885c295f86eSRam Amrani u32 returned_id; 886c295f86eSRam Amrani int rc; 887c295f86eSRam Amrani 888c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n"); 889c295f86eSRam Amrani 890c295f86eSRam Amrani /* Allocates an unused protection domain */ 891c295f86eSRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 892c295f86eSRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, 893c295f86eSRam Amrani &p_hwfn->p_rdma_info->pd_map, &returned_id); 894c295f86eSRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 895c295f86eSRam Amrani 896c295f86eSRam Amrani *pd = (u16)returned_id; 897c295f86eSRam Amrani 898c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc); 899c295f86eSRam Amrani return rc; 900c295f86eSRam Amrani } 901c295f86eSRam Amrani 9028c93beafSYuval Mintz static void qed_rdma_free_pd(void *rdma_cxt, u16 pd) 903c295f86eSRam Amrani { 904c295f86eSRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 905c295f86eSRam Amrani 906c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd); 907c295f86eSRam Amrani 908c295f86eSRam Amrani /* Returns a previously allocated protection domain for reuse */ 909c295f86eSRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 910c295f86eSRam Amrani qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd); 911c295f86eSRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 912c295f86eSRam Amrani } 913c295f86eSRam Amrani 914c295f86eSRam Amrani static enum qed_rdma_toggle_bit 915c295f86eSRam Amrani qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid) 916c295f86eSRam Amrani { 917c295f86eSRam Amrani struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 918c295f86eSRam Amrani enum qed_rdma_toggle_bit toggle_bit; 919c295f86eSRam Amrani u32 bmap_id; 920c295f86eSRam Amrani 921c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid); 922c295f86eSRam Amrani 923c295f86eSRam Amrani /* the function toggle the bit that is related to a given icid 924c295f86eSRam Amrani * and returns the new toggle bit's value 925c295f86eSRam Amrani */ 926c295f86eSRam Amrani bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto); 927c295f86eSRam Amrani 928c295f86eSRam Amrani spin_lock_bh(&p_info->lock); 929c295f86eSRam Amrani toggle_bit = !test_and_change_bit(bmap_id, 930c295f86eSRam Amrani p_info->toggle_bits.bitmap); 931c295f86eSRam Amrani spin_unlock_bh(&p_info->lock); 932c295f86eSRam Amrani 933c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n", 934c295f86eSRam Amrani toggle_bit); 935c295f86eSRam Amrani 936c295f86eSRam Amrani return toggle_bit; 937c295f86eSRam Amrani } 938c295f86eSRam Amrani 9398c93beafSYuval Mintz static int qed_rdma_create_cq(void *rdma_cxt, 9408c93beafSYuval Mintz struct qed_rdma_create_cq_in_params *params, 9418c93beafSYuval Mintz u16 *icid) 942c295f86eSRam Amrani { 943c295f86eSRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 944c295f86eSRam Amrani struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 945c295f86eSRam Amrani struct rdma_create_cq_ramrod_data *p_ramrod; 946c295f86eSRam Amrani enum qed_rdma_toggle_bit toggle_bit; 947c295f86eSRam Amrani struct qed_sp_init_data init_data; 948c295f86eSRam Amrani struct qed_spq_entry *p_ent; 949c295f86eSRam Amrani u32 returned_id, start_cid; 950c295f86eSRam Amrani int rc; 951c295f86eSRam Amrani 952c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n", 953c295f86eSRam Amrani params->cq_handle_hi, params->cq_handle_lo); 954c295f86eSRam Amrani 955c295f86eSRam Amrani /* Allocate icid */ 956c295f86eSRam Amrani spin_lock_bh(&p_info->lock); 957c295f86eSRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, 958c295f86eSRam Amrani &p_info->cq_map, &returned_id); 959c295f86eSRam Amrani spin_unlock_bh(&p_info->lock); 960c295f86eSRam Amrani 961c295f86eSRam Amrani if (rc) { 962c295f86eSRam Amrani DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc); 963c295f86eSRam Amrani return rc; 964c295f86eSRam Amrani } 965c295f86eSRam Amrani 966c295f86eSRam Amrani start_cid = qed_cxt_get_proto_cid_start(p_hwfn, 967c295f86eSRam Amrani p_info->proto); 968c295f86eSRam Amrani *icid = returned_id + start_cid; 969c295f86eSRam Amrani 970c295f86eSRam Amrani /* Check if icid requires a page allocation */ 971c295f86eSRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid); 972c295f86eSRam Amrani if (rc) 973c295f86eSRam Amrani goto err; 974c295f86eSRam Amrani 975c295f86eSRam Amrani /* Get SPQ entry */ 976c295f86eSRam Amrani memset(&init_data, 0, sizeof(init_data)); 977c295f86eSRam Amrani init_data.cid = *icid; 978c295f86eSRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 979c295f86eSRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 980c295f86eSRam Amrani 981c295f86eSRam Amrani /* Send create CQ ramrod */ 982c295f86eSRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 983c295f86eSRam Amrani RDMA_RAMROD_CREATE_CQ, 984c295f86eSRam Amrani p_info->proto, &init_data); 985c295f86eSRam Amrani if (rc) 986c295f86eSRam Amrani goto err; 987c295f86eSRam Amrani 988c295f86eSRam Amrani p_ramrod = &p_ent->ramrod.rdma_create_cq; 989c295f86eSRam Amrani 990c295f86eSRam Amrani p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi); 991c295f86eSRam Amrani p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo); 992c295f86eSRam Amrani p_ramrod->dpi = cpu_to_le16(params->dpi); 993c295f86eSRam Amrani p_ramrod->is_two_level_pbl = params->pbl_two_level; 994c295f86eSRam Amrani p_ramrod->max_cqes = cpu_to_le32(params->cq_size); 995c295f86eSRam Amrani DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr); 996c295f86eSRam Amrani p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages); 997c295f86eSRam Amrani p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) + 998c295f86eSRam Amrani params->cnq_id; 999c295f86eSRam Amrani p_ramrod->int_timeout = params->int_timeout; 1000c295f86eSRam Amrani 1001c295f86eSRam Amrani /* toggle the bit for every resize or create cq for a given icid */ 1002c295f86eSRam Amrani toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 1003c295f86eSRam Amrani 1004c295f86eSRam Amrani p_ramrod->toggle_bit = toggle_bit; 1005c295f86eSRam Amrani 1006c295f86eSRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1007c295f86eSRam Amrani if (rc) { 1008c295f86eSRam Amrani /* restore toggle bit */ 1009c295f86eSRam Amrani qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 1010c295f86eSRam Amrani goto err; 1011c295f86eSRam Amrani } 1012c295f86eSRam Amrani 1013c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc); 1014c295f86eSRam Amrani return rc; 1015c295f86eSRam Amrani 1016c295f86eSRam Amrani err: 1017c295f86eSRam Amrani /* release allocated icid */ 1018670dde55SRam Amrani spin_lock_bh(&p_info->lock); 1019c295f86eSRam Amrani qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id); 1020670dde55SRam Amrani spin_unlock_bh(&p_info->lock); 1021c295f86eSRam Amrani DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc); 1022c295f86eSRam Amrani 1023c295f86eSRam Amrani return rc; 1024c295f86eSRam Amrani } 1025c295f86eSRam Amrani 10268c93beafSYuval Mintz static int 10278c93beafSYuval Mintz qed_rdma_destroy_cq(void *rdma_cxt, 1028c295f86eSRam Amrani struct qed_rdma_destroy_cq_in_params *in_params, 1029c295f86eSRam Amrani struct qed_rdma_destroy_cq_out_params *out_params) 1030c295f86eSRam Amrani { 1031c295f86eSRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1032c295f86eSRam Amrani struct rdma_destroy_cq_output_params *p_ramrod_res; 1033c295f86eSRam Amrani struct rdma_destroy_cq_ramrod_data *p_ramrod; 1034c295f86eSRam Amrani struct qed_sp_init_data init_data; 1035c295f86eSRam Amrani struct qed_spq_entry *p_ent; 1036c295f86eSRam Amrani dma_addr_t ramrod_res_phys; 1037c295f86eSRam Amrani int rc = -ENOMEM; 1038c295f86eSRam Amrani 1039c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid); 1040c295f86eSRam Amrani 1041c295f86eSRam Amrani p_ramrod_res = 1042c295f86eSRam Amrani (struct rdma_destroy_cq_output_params *) 1043c295f86eSRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1044c295f86eSRam Amrani sizeof(struct rdma_destroy_cq_output_params), 1045c295f86eSRam Amrani &ramrod_res_phys, GFP_KERNEL); 1046c295f86eSRam Amrani if (!p_ramrod_res) { 1047c295f86eSRam Amrani DP_NOTICE(p_hwfn, 1048c295f86eSRam Amrani "qed destroy cq failed: cannot allocate memory (ramrod)\n"); 1049c295f86eSRam Amrani return rc; 1050c295f86eSRam Amrani } 1051c295f86eSRam Amrani 1052c295f86eSRam Amrani /* Get SPQ entry */ 1053c295f86eSRam Amrani memset(&init_data, 0, sizeof(init_data)); 1054c295f86eSRam Amrani init_data.cid = in_params->icid; 1055c295f86eSRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1056c295f86eSRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1057c295f86eSRam Amrani 1058c295f86eSRam Amrani /* Send destroy CQ ramrod */ 1059c295f86eSRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 1060c295f86eSRam Amrani RDMA_RAMROD_DESTROY_CQ, 1061c295f86eSRam Amrani p_hwfn->p_rdma_info->proto, &init_data); 1062c295f86eSRam Amrani if (rc) 1063c295f86eSRam Amrani goto err; 1064c295f86eSRam Amrani 1065c295f86eSRam Amrani p_ramrod = &p_ent->ramrod.rdma_destroy_cq; 1066c295f86eSRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1067c295f86eSRam Amrani 1068c295f86eSRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1069c295f86eSRam Amrani if (rc) 1070c295f86eSRam Amrani goto err; 1071c295f86eSRam Amrani 1072c295f86eSRam Amrani out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num); 1073c295f86eSRam Amrani 1074c295f86eSRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1075c295f86eSRam Amrani sizeof(struct rdma_destroy_cq_output_params), 1076c295f86eSRam Amrani p_ramrod_res, ramrod_res_phys); 1077c295f86eSRam Amrani 1078c295f86eSRam Amrani /* Free icid */ 1079c295f86eSRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1080c295f86eSRam Amrani 1081c295f86eSRam Amrani qed_bmap_release_id(p_hwfn, 1082c295f86eSRam Amrani &p_hwfn->p_rdma_info->cq_map, 1083c295f86eSRam Amrani (in_params->icid - 1084c295f86eSRam Amrani qed_cxt_get_proto_cid_start(p_hwfn, 1085c295f86eSRam Amrani p_hwfn-> 1086c295f86eSRam Amrani p_rdma_info->proto))); 1087c295f86eSRam Amrani 1088c295f86eSRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1089c295f86eSRam Amrani 1090c295f86eSRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc); 1091c295f86eSRam Amrani return rc; 1092c295f86eSRam Amrani 1093c295f86eSRam Amrani err: dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1094c295f86eSRam Amrani sizeof(struct rdma_destroy_cq_output_params), 1095c295f86eSRam Amrani p_ramrod_res, ramrod_res_phys); 1096c295f86eSRam Amrani 1097c295f86eSRam Amrani return rc; 1098c295f86eSRam Amrani } 1099c295f86eSRam Amrani 1100f1093940SRam Amrani static void qed_rdma_set_fw_mac(u16 *p_fw_mac, u8 *p_qed_mac) 1101f1093940SRam Amrani { 1102f1093940SRam Amrani p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]); 1103f1093940SRam Amrani p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]); 1104f1093940SRam Amrani p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]); 1105f1093940SRam Amrani } 1106f1093940SRam Amrani 1107f1093940SRam Amrani static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid, 1108f1093940SRam Amrani __le32 *dst_gid) 1109f1093940SRam Amrani { 1110f1093940SRam Amrani u32 i; 1111f1093940SRam Amrani 1112f1093940SRam Amrani if (qp->roce_mode == ROCE_V2_IPV4) { 1113f1093940SRam Amrani /* The IPv4 addresses shall be aligned to the highest word. 1114f1093940SRam Amrani * The lower words must be zero. 1115f1093940SRam Amrani */ 1116f1093940SRam Amrani memset(src_gid, 0, sizeof(union qed_gid)); 1117f1093940SRam Amrani memset(dst_gid, 0, sizeof(union qed_gid)); 1118f1093940SRam Amrani src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr); 1119f1093940SRam Amrani dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr); 1120f1093940SRam Amrani } else { 1121f1093940SRam Amrani /* GIDs and IPv6 addresses coincide in location and size */ 1122f1093940SRam Amrani for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) { 1123f1093940SRam Amrani src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]); 1124f1093940SRam Amrani dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]); 1125f1093940SRam Amrani } 1126f1093940SRam Amrani } 1127f1093940SRam Amrani } 1128f1093940SRam Amrani 1129f1093940SRam Amrani static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode) 1130f1093940SRam Amrani { 1131f1093940SRam Amrani enum roce_flavor flavor; 1132f1093940SRam Amrani 1133f1093940SRam Amrani switch (roce_mode) { 1134f1093940SRam Amrani case ROCE_V1: 1135f1093940SRam Amrani flavor = PLAIN_ROCE; 1136f1093940SRam Amrani break; 1137f1093940SRam Amrani case ROCE_V2_IPV4: 1138f1093940SRam Amrani flavor = RROCE_IPV4; 1139f1093940SRam Amrani break; 1140f1093940SRam Amrani case ROCE_V2_IPV6: 1141f1093940SRam Amrani flavor = ROCE_V2_IPV6; 1142f1093940SRam Amrani break; 1143f1093940SRam Amrani default: 1144f1093940SRam Amrani flavor = MAX_ROCE_MODE; 1145f1093940SRam Amrani break; 1146f1093940SRam Amrani } 1147f1093940SRam Amrani return flavor; 1148f1093940SRam Amrani } 1149f1093940SRam Amrani 1150be086e7cSMintz, Yuval void qed_roce_free_cid_pair(struct qed_hwfn *p_hwfn, u16 cid) 1151be086e7cSMintz, Yuval { 1152be086e7cSMintz, Yuval spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1153be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid); 1154be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid + 1); 1155be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1156be086e7cSMintz, Yuval } 1157be086e7cSMintz, Yuval 11588c93beafSYuval Mintz static int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid) 1159f1093940SRam Amrani { 1160f1093940SRam Amrani struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 1161f1093940SRam Amrani u32 responder_icid; 1162f1093940SRam Amrani u32 requester_icid; 1163f1093940SRam Amrani int rc; 1164f1093940SRam Amrani 1165f1093940SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1166f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 1167f1093940SRam Amrani &responder_icid); 1168f1093940SRam Amrani if (rc) { 1169f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 1170f1093940SRam Amrani return rc; 1171f1093940SRam Amrani } 1172f1093940SRam Amrani 1173f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 1174f1093940SRam Amrani &requester_icid); 1175f1093940SRam Amrani 1176f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 1177f1093940SRam Amrani if (rc) 1178f1093940SRam Amrani goto err; 1179f1093940SRam Amrani 1180f1093940SRam Amrani /* the two icid's should be adjacent */ 1181f1093940SRam Amrani if ((requester_icid - responder_icid) != 1) { 1182f1093940SRam Amrani DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n"); 1183f1093940SRam Amrani rc = -EINVAL; 1184f1093940SRam Amrani goto err; 1185f1093940SRam Amrani } 1186f1093940SRam Amrani 1187f1093940SRam Amrani responder_icid += qed_cxt_get_proto_cid_start(p_hwfn, 1188f1093940SRam Amrani p_rdma_info->proto); 1189f1093940SRam Amrani requester_icid += qed_cxt_get_proto_cid_start(p_hwfn, 1190f1093940SRam Amrani p_rdma_info->proto); 1191f1093940SRam Amrani 1192f1093940SRam Amrani /* If these icids require a new ILT line allocate DMA-able context for 1193f1093940SRam Amrani * an ILT page 1194f1093940SRam Amrani */ 1195f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid); 1196f1093940SRam Amrani if (rc) 1197f1093940SRam Amrani goto err; 1198f1093940SRam Amrani 1199f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid); 1200f1093940SRam Amrani if (rc) 1201f1093940SRam Amrani goto err; 1202f1093940SRam Amrani 1203f1093940SRam Amrani *cid = (u16)responder_icid; 1204f1093940SRam Amrani return rc; 1205f1093940SRam Amrani 1206f1093940SRam Amrani err: 1207f1093940SRam Amrani spin_lock_bh(&p_rdma_info->lock); 1208f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid); 1209f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid); 1210f1093940SRam Amrani 1211f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 1212f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1213f1093940SRam Amrani "Allocate CID - failed, rc = %d\n", rc); 1214f1093940SRam Amrani return rc; 1215f1093940SRam Amrani } 1216f1093940SRam Amrani 1217be086e7cSMintz, Yuval static void qed_roce_set_real_cid(struct qed_hwfn *p_hwfn, u32 cid) 1218be086e7cSMintz, Yuval { 1219be086e7cSMintz, Yuval spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1220be086e7cSMintz, Yuval qed_bmap_set_id(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, cid); 1221be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1222be086e7cSMintz, Yuval } 1223be086e7cSMintz, Yuval 1224f1093940SRam Amrani static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn, 1225f1093940SRam Amrani struct qed_rdma_qp *qp) 1226f1093940SRam Amrani { 1227f1093940SRam Amrani struct roce_create_qp_resp_ramrod_data *p_ramrod; 1228f1093940SRam Amrani struct qed_sp_init_data init_data; 1229f1093940SRam Amrani enum roce_flavor roce_flavor; 1230f1093940SRam Amrani struct qed_spq_entry *p_ent; 1231be086e7cSMintz, Yuval u16 regular_latency_queue; 1232be086e7cSMintz, Yuval enum protocol_type proto; 1233f1093940SRam Amrani int rc; 1234f1093940SRam Amrani 1235f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1236f1093940SRam Amrani 1237f1093940SRam Amrani /* Allocate DMA-able memory for IRQ */ 1238f1093940SRam Amrani qp->irq_num_pages = 1; 1239f1093940SRam Amrani qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1240f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 1241f1093940SRam Amrani &qp->irq_phys_addr, GFP_KERNEL); 1242f1093940SRam Amrani if (!qp->irq) { 1243f1093940SRam Amrani rc = -ENOMEM; 1244f1093940SRam Amrani DP_NOTICE(p_hwfn, 1245f1093940SRam Amrani "qed create responder failed: cannot allocate memory (irq). rc = %d\n", 1246f1093940SRam Amrani rc); 1247f1093940SRam Amrani return rc; 1248f1093940SRam Amrani } 1249f1093940SRam Amrani 1250f1093940SRam Amrani /* Get SPQ entry */ 1251f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1252f1093940SRam Amrani init_data.cid = qp->icid; 1253f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1254f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1255f1093940SRam Amrani 1256f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP, 1257f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1258f1093940SRam Amrani if (rc) 1259f1093940SRam Amrani goto err; 1260f1093940SRam Amrani 1261f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_resp; 1262f1093940SRam Amrani 1263f1093940SRam Amrani p_ramrod->flags = 0; 1264f1093940SRam Amrani 1265f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 1266f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1267f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 1268f1093940SRam Amrani 1269f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1270f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 1271f1093940SRam Amrani qp->incoming_rdma_read_en); 1272f1093940SRam Amrani 1273f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1274f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 1275f1093940SRam Amrani qp->incoming_rdma_write_en); 1276f1093940SRam Amrani 1277f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1278f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN, 1279f1093940SRam Amrani qp->incoming_atomic_en); 1280f1093940SRam Amrani 1281f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1282f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 1283f1093940SRam Amrani qp->e2e_flow_control_en); 1284f1093940SRam Amrani 1285f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1286f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq); 1287f1093940SRam Amrani 1288f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1289f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN, 1290f1093940SRam Amrani qp->fmr_and_reserved_lkey); 1291f1093940SRam Amrani 1292f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1293f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 1294f1093940SRam Amrani qp->min_rnr_nak_timer); 1295f1093940SRam Amrani 1296f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 1297f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 1298f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 1299f1093940SRam Amrani p_ramrod->irq_num_pages = qp->irq_num_pages; 1300f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 1301f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1302f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 1303f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 1304f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn); 1305f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 1306f1093940SRam Amrani p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages); 1307f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr); 1308f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr); 1309f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1310f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 1311f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 1312f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 1313f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 1314f1093940SRam Amrani p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 1315f1093940SRam Amrani qp->rq_cq_id); 1316f1093940SRam Amrani 1317b5a9ee7cSAriel Elior regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 1318f1093940SRam Amrani 1319be086e7cSMintz, Yuval p_ramrod->regular_latency_phy_queue = 1320be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 1321be086e7cSMintz, Yuval p_ramrod->low_latency_phy_queue = 1322be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 1323be086e7cSMintz, Yuval 1324f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 1325f1093940SRam Amrani 1326f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 1327f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 1328f1093940SRam Amrani 1329f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 1330f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 1331f1093940SRam Amrani p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id); 1332f1093940SRam Amrani p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid); 1333f1093940SRam Amrani 1334f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 1335f1093940SRam Amrani qp->stats_queue; 1336f1093940SRam Amrani 1337f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1338f1093940SRam Amrani 1339be086e7cSMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1340be086e7cSMintz, Yuval "rc = %d regular physical queue = 0x%x\n", rc, 1341be086e7cSMintz, Yuval regular_latency_queue); 1342f1093940SRam Amrani 1343f1093940SRam Amrani if (rc) 1344f1093940SRam Amrani goto err; 1345f1093940SRam Amrani 1346f1093940SRam Amrani qp->resp_offloaded = true; 1347be086e7cSMintz, Yuval qp->cq_prod = 0; 1348be086e7cSMintz, Yuval 1349be086e7cSMintz, Yuval proto = p_hwfn->p_rdma_info->proto; 1350be086e7cSMintz, Yuval qed_roce_set_real_cid(p_hwfn, qp->icid - 1351be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, proto)); 1352f1093940SRam Amrani 1353f1093940SRam Amrani return rc; 1354f1093940SRam Amrani 1355f1093940SRam Amrani err: 1356f1093940SRam Amrani DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc); 1357f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1358f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 1359f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 1360f1093940SRam Amrani 1361f1093940SRam Amrani return rc; 1362f1093940SRam Amrani } 1363f1093940SRam Amrani 1364f1093940SRam Amrani static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn, 1365f1093940SRam Amrani struct qed_rdma_qp *qp) 1366f1093940SRam Amrani { 1367f1093940SRam Amrani struct roce_create_qp_req_ramrod_data *p_ramrod; 1368f1093940SRam Amrani struct qed_sp_init_data init_data; 1369f1093940SRam Amrani enum roce_flavor roce_flavor; 1370f1093940SRam Amrani struct qed_spq_entry *p_ent; 1371be086e7cSMintz, Yuval u16 regular_latency_queue; 1372be086e7cSMintz, Yuval enum protocol_type proto; 1373f1093940SRam Amrani int rc; 1374f1093940SRam Amrani 1375f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1376f1093940SRam Amrani 1377f1093940SRam Amrani /* Allocate DMA-able memory for ORQ */ 1378f1093940SRam Amrani qp->orq_num_pages = 1; 1379f1093940SRam Amrani qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1380f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 1381f1093940SRam Amrani &qp->orq_phys_addr, GFP_KERNEL); 1382f1093940SRam Amrani if (!qp->orq) { 1383f1093940SRam Amrani rc = -ENOMEM; 1384f1093940SRam Amrani DP_NOTICE(p_hwfn, 1385f1093940SRam Amrani "qed create requester failed: cannot allocate memory (orq). rc = %d\n", 1386f1093940SRam Amrani rc); 1387f1093940SRam Amrani return rc; 1388f1093940SRam Amrani } 1389f1093940SRam Amrani 1390f1093940SRam Amrani /* Get SPQ entry */ 1391f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1392f1093940SRam Amrani init_data.cid = qp->icid + 1; 1393f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1394f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1395f1093940SRam Amrani 1396f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 1397f1093940SRam Amrani ROCE_RAMROD_CREATE_QP, 1398f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1399f1093940SRam Amrani if (rc) 1400f1093940SRam Amrani goto err; 1401f1093940SRam Amrani 1402f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_req; 1403f1093940SRam Amrani 1404f1093940SRam Amrani p_ramrod->flags = 0; 1405f1093940SRam Amrani 1406f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 1407f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1408f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 1409f1093940SRam Amrani 1410f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1411f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN, 1412f1093940SRam Amrani qp->fmr_and_reserved_lkey); 1413f1093940SRam Amrani 1414f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1415f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all); 1416f1093940SRam Amrani 1417f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1418f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 1419f1093940SRam Amrani 1420f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1421f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 1422f1093940SRam Amrani qp->rnr_retry_cnt); 1423f1093940SRam Amrani 1424f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 1425f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 1426f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 1427f1093940SRam Amrani p_ramrod->orq_num_pages = qp->orq_num_pages; 1428f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 1429f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1430f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 1431f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 1432f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 1433f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn); 1434f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 1435f1093940SRam Amrani p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages); 1436f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr); 1437f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr); 1438f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1439f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 1440f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 1441f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 1442f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 1443be086e7cSMintz, Yuval p_ramrod->cq_cid = 1444be086e7cSMintz, Yuval cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | qp->sq_cq_id); 1445f1093940SRam Amrani 1446b5a9ee7cSAriel Elior regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 1447f1093940SRam Amrani 1448be086e7cSMintz, Yuval p_ramrod->regular_latency_phy_queue = 1449be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 1450be086e7cSMintz, Yuval p_ramrod->low_latency_phy_queue = 1451be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 1452be086e7cSMintz, Yuval 1453f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 1454f1093940SRam Amrani 1455f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 1456f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 1457f1093940SRam Amrani 1458f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 1459f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 1460f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 1461f1093940SRam Amrani qp->stats_queue; 1462f1093940SRam Amrani 1463f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1464f1093940SRam Amrani 1465f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1466f1093940SRam Amrani 1467f1093940SRam Amrani if (rc) 1468f1093940SRam Amrani goto err; 1469f1093940SRam Amrani 1470f1093940SRam Amrani qp->req_offloaded = true; 1471be086e7cSMintz, Yuval proto = p_hwfn->p_rdma_info->proto; 1472be086e7cSMintz, Yuval qed_roce_set_real_cid(p_hwfn, 1473be086e7cSMintz, Yuval qp->icid + 1 - 1474be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, proto)); 1475f1093940SRam Amrani 1476f1093940SRam Amrani return rc; 1477f1093940SRam Amrani 1478f1093940SRam Amrani err: 1479f1093940SRam Amrani DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc); 1480f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1481f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 1482f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 1483f1093940SRam Amrani return rc; 1484f1093940SRam Amrani } 1485f1093940SRam Amrani 1486f1093940SRam Amrani static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn, 1487f1093940SRam Amrani struct qed_rdma_qp *qp, 1488f1093940SRam Amrani bool move_to_err, u32 modify_flags) 1489f1093940SRam Amrani { 1490f1093940SRam Amrani struct roce_modify_qp_resp_ramrod_data *p_ramrod; 1491f1093940SRam Amrani struct qed_sp_init_data init_data; 1492f1093940SRam Amrani struct qed_spq_entry *p_ent; 1493f1093940SRam Amrani int rc; 1494f1093940SRam Amrani 1495f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1496f1093940SRam Amrani 1497f1093940SRam Amrani if (move_to_err && !qp->resp_offloaded) 1498f1093940SRam Amrani return 0; 1499f1093940SRam Amrani 1500f1093940SRam Amrani /* Get SPQ entry */ 1501f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1502f1093940SRam Amrani init_data.cid = qp->icid; 1503f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1504f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1505f1093940SRam Amrani 1506f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 1507f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 1508f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1509f1093940SRam Amrani if (rc) { 1510f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 1511f1093940SRam Amrani return rc; 1512f1093940SRam Amrani } 1513f1093940SRam Amrani 1514f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_resp; 1515f1093940SRam Amrani 1516f1093940SRam Amrani p_ramrod->flags = 0; 1517f1093940SRam Amrani 1518f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1519f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 1520f1093940SRam Amrani 1521f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1522f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 1523f1093940SRam Amrani qp->incoming_rdma_read_en); 1524f1093940SRam Amrani 1525f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1526f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 1527f1093940SRam Amrani qp->incoming_rdma_write_en); 1528f1093940SRam Amrani 1529f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1530f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN, 1531f1093940SRam Amrani qp->incoming_atomic_en); 1532f1093940SRam Amrani 1533f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1534f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 1535f1093940SRam Amrani qp->e2e_flow_control_en); 1536f1093940SRam Amrani 1537f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1538f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG, 1539f1093940SRam Amrani GET_FIELD(modify_flags, 1540f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)); 1541f1093940SRam Amrani 1542f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1543f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG, 1544f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 1545f1093940SRam Amrani 1546f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1547f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG, 1548f1093940SRam Amrani GET_FIELD(modify_flags, 1549f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 1550f1093940SRam Amrani 1551f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1552f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG, 1553f1093940SRam Amrani GET_FIELD(modify_flags, 1554f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)); 1555f1093940SRam Amrani 1556f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1557f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG, 1558f1093940SRam Amrani GET_FIELD(modify_flags, 1559f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)); 1560f1093940SRam Amrani 1561f1093940SRam Amrani p_ramrod->fields = 0; 1562f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 1563f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 1564f1093940SRam Amrani qp->min_rnr_nak_timer); 1565f1093940SRam Amrani 1566f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 1567f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 1568f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 1569f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 1570f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1571f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 1572f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1573f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1574f1093940SRam Amrani 1575f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc); 1576f1093940SRam Amrani return rc; 1577f1093940SRam Amrani } 1578f1093940SRam Amrani 1579f1093940SRam Amrani static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn, 1580f1093940SRam Amrani struct qed_rdma_qp *qp, 1581f1093940SRam Amrani bool move_to_sqd, 1582f1093940SRam Amrani bool move_to_err, u32 modify_flags) 1583f1093940SRam Amrani { 1584f1093940SRam Amrani struct roce_modify_qp_req_ramrod_data *p_ramrod; 1585f1093940SRam Amrani struct qed_sp_init_data init_data; 1586f1093940SRam Amrani struct qed_spq_entry *p_ent; 1587f1093940SRam Amrani int rc; 1588f1093940SRam Amrani 1589f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1590f1093940SRam Amrani 1591f1093940SRam Amrani if (move_to_err && !(qp->req_offloaded)) 1592f1093940SRam Amrani return 0; 1593f1093940SRam Amrani 1594f1093940SRam Amrani /* Get SPQ entry */ 1595f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1596f1093940SRam Amrani init_data.cid = qp->icid + 1; 1597f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1598f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1599f1093940SRam Amrani 1600f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 1601f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 1602f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1603f1093940SRam Amrani if (rc) { 1604f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 1605f1093940SRam Amrani return rc; 1606f1093940SRam Amrani } 1607f1093940SRam Amrani 1608f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_req; 1609f1093940SRam Amrani 1610f1093940SRam Amrani p_ramrod->flags = 0; 1611f1093940SRam Amrani 1612f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1613f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 1614f1093940SRam Amrani 1615f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1616f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd); 1617f1093940SRam Amrani 1618f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1619f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY, 1620f1093940SRam Amrani qp->sqd_async); 1621f1093940SRam Amrani 1622f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1623f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG, 1624f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 1625f1093940SRam Amrani 1626f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1627f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG, 1628f1093940SRam Amrani GET_FIELD(modify_flags, 1629f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 1630f1093940SRam Amrani 1631f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1632f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG, 1633f1093940SRam Amrani GET_FIELD(modify_flags, 1634f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)); 1635f1093940SRam Amrani 1636f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1637f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG, 1638f1093940SRam Amrani GET_FIELD(modify_flags, 1639f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)); 1640f1093940SRam Amrani 1641f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1642f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG, 1643f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)); 1644f1093940SRam Amrani 1645f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 1646f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG, 1647f1093940SRam Amrani GET_FIELD(modify_flags, 1648f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)); 1649f1093940SRam Amrani 1650f1093940SRam Amrani p_ramrod->fields = 0; 1651f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 1652f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 1653f1093940SRam Amrani 1654f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 1655f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 1656f1093940SRam Amrani qp->rnr_retry_cnt); 1657f1093940SRam Amrani 1658f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 1659f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 1660f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 1661f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 1662f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 1663f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 1664f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 1665f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 1666f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1667f1093940SRam Amrani 1668f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc); 1669f1093940SRam Amrani return rc; 1670f1093940SRam Amrani } 1671f1093940SRam Amrani 1672f1093940SRam Amrani static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn, 1673f1093940SRam Amrani struct qed_rdma_qp *qp, 1674be086e7cSMintz, Yuval u32 *num_invalidated_mw, 1675be086e7cSMintz, Yuval u32 *cq_prod) 1676f1093940SRam Amrani { 1677f1093940SRam Amrani struct roce_destroy_qp_resp_output_params *p_ramrod_res; 1678f1093940SRam Amrani struct roce_destroy_qp_resp_ramrod_data *p_ramrod; 1679f1093940SRam Amrani struct qed_sp_init_data init_data; 1680f1093940SRam Amrani struct qed_spq_entry *p_ent; 1681f1093940SRam Amrani dma_addr_t ramrod_res_phys; 1682f1093940SRam Amrani int rc; 1683f1093940SRam Amrani 1684f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1685f1093940SRam Amrani 1686be086e7cSMintz, Yuval *num_invalidated_mw = 0; 1687be086e7cSMintz, Yuval *cq_prod = qp->cq_prod; 1688be086e7cSMintz, Yuval 1689be086e7cSMintz, Yuval if (!qp->resp_offloaded) { 1690be086e7cSMintz, Yuval /* If a responder was never offload, we need to free the cids 1691be086e7cSMintz, Yuval * allocated in create_qp as a FW async event will never arrive 1692be086e7cSMintz, Yuval */ 1693be086e7cSMintz, Yuval u32 cid; 1694be086e7cSMintz, Yuval 1695be086e7cSMintz, Yuval cid = qp->icid - 1696be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, 1697be086e7cSMintz, Yuval p_hwfn->p_rdma_info->proto); 1698be086e7cSMintz, Yuval qed_roce_free_cid_pair(p_hwfn, (u16)cid); 1699be086e7cSMintz, Yuval 1700f1093940SRam Amrani return 0; 1701be086e7cSMintz, Yuval } 1702f1093940SRam Amrani 1703f1093940SRam Amrani /* Get SPQ entry */ 1704f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1705f1093940SRam Amrani init_data.cid = qp->icid; 1706f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1707f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1708f1093940SRam Amrani 1709f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 1710f1093940SRam Amrani ROCE_RAMROD_DESTROY_QP, 1711f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1712f1093940SRam Amrani if (rc) 1713f1093940SRam Amrani return rc; 1714f1093940SRam Amrani 1715f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp; 1716f1093940SRam Amrani 1717f1093940SRam Amrani p_ramrod_res = (struct roce_destroy_qp_resp_output_params *) 1718f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 1719f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 1720f1093940SRam Amrani 1721f1093940SRam Amrani if (!p_ramrod_res) { 1722f1093940SRam Amrani rc = -ENOMEM; 1723f1093940SRam Amrani DP_NOTICE(p_hwfn, 1724f1093940SRam Amrani "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n", 1725f1093940SRam Amrani rc); 1726f1093940SRam Amrani return rc; 1727f1093940SRam Amrani } 1728f1093940SRam Amrani 1729f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1730f1093940SRam Amrani 1731f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1732f1093940SRam Amrani if (rc) 1733f1093940SRam Amrani goto err; 1734f1093940SRam Amrani 1735f1093940SRam Amrani *num_invalidated_mw = le32_to_cpu(p_ramrod_res->num_invalidated_mw); 1736be086e7cSMintz, Yuval *cq_prod = le32_to_cpu(p_ramrod_res->cq_prod); 1737be086e7cSMintz, Yuval qp->cq_prod = *cq_prod; 1738f1093940SRam Amrani 1739f1093940SRam Amrani /* Free IRQ - only if ramrod succeeded, in case FW is still using it */ 1740f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1741f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 1742f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 1743f1093940SRam Amrani 1744f1093940SRam Amrani qp->resp_offloaded = false; 1745f1093940SRam Amrani 1746f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc); 1747f1093940SRam Amrani 1748f1093940SRam Amrani err: 1749f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1750f1093940SRam Amrani sizeof(struct roce_destroy_qp_resp_output_params), 1751f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 1752f1093940SRam Amrani 1753f1093940SRam Amrani return rc; 1754f1093940SRam Amrani } 1755f1093940SRam Amrani 1756f1093940SRam Amrani static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn, 1757f1093940SRam Amrani struct qed_rdma_qp *qp, 1758f1093940SRam Amrani u32 *num_bound_mw) 1759f1093940SRam Amrani { 1760f1093940SRam Amrani struct roce_destroy_qp_req_output_params *p_ramrod_res; 1761f1093940SRam Amrani struct roce_destroy_qp_req_ramrod_data *p_ramrod; 1762f1093940SRam Amrani struct qed_sp_init_data init_data; 1763f1093940SRam Amrani struct qed_spq_entry *p_ent; 1764f1093940SRam Amrani dma_addr_t ramrod_res_phys; 1765f1093940SRam Amrani int rc = -ENOMEM; 1766f1093940SRam Amrani 1767f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1768f1093940SRam Amrani 1769f1093940SRam Amrani if (!qp->req_offloaded) 1770f1093940SRam Amrani return 0; 1771f1093940SRam Amrani 1772f1093940SRam Amrani p_ramrod_res = (struct roce_destroy_qp_req_output_params *) 1773f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1774f1093940SRam Amrani sizeof(*p_ramrod_res), 1775f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 1776f1093940SRam Amrani if (!p_ramrod_res) { 1777f1093940SRam Amrani DP_NOTICE(p_hwfn, 1778f1093940SRam Amrani "qed destroy requester failed: cannot allocate memory (ramrod)\n"); 1779f1093940SRam Amrani return rc; 1780f1093940SRam Amrani } 1781f1093940SRam Amrani 1782f1093940SRam Amrani /* Get SPQ entry */ 1783f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1784f1093940SRam Amrani init_data.cid = qp->icid + 1; 1785f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1786f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1787f1093940SRam Amrani 1788f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP, 1789f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1790f1093940SRam Amrani if (rc) 1791f1093940SRam Amrani goto err; 1792f1093940SRam Amrani 1793f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_req; 1794f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1795f1093940SRam Amrani 1796f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1797f1093940SRam Amrani if (rc) 1798f1093940SRam Amrani goto err; 1799f1093940SRam Amrani 1800f1093940SRam Amrani *num_bound_mw = le32_to_cpu(p_ramrod_res->num_bound_mw); 1801f1093940SRam Amrani 1802f1093940SRam Amrani /* Free ORQ - only if ramrod succeeded, in case FW is still using it */ 1803f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1804f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 1805f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 1806f1093940SRam Amrani 1807f1093940SRam Amrani qp->req_offloaded = false; 1808f1093940SRam Amrani 1809f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc); 1810f1093940SRam Amrani 1811f1093940SRam Amrani err: 1812f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 1813f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 1814f1093940SRam Amrani 1815f1093940SRam Amrani return rc; 1816f1093940SRam Amrani } 1817f1093940SRam Amrani 18188c93beafSYuval Mintz static int qed_roce_query_qp(struct qed_hwfn *p_hwfn, 1819f1093940SRam Amrani struct qed_rdma_qp *qp, 1820f1093940SRam Amrani struct qed_rdma_query_qp_out_params *out_params) 1821f1093940SRam Amrani { 1822f1093940SRam Amrani struct roce_query_qp_resp_output_params *p_resp_ramrod_res; 1823f1093940SRam Amrani struct roce_query_qp_req_output_params *p_req_ramrod_res; 1824f1093940SRam Amrani struct roce_query_qp_resp_ramrod_data *p_resp_ramrod; 1825f1093940SRam Amrani struct roce_query_qp_req_ramrod_data *p_req_ramrod; 1826f1093940SRam Amrani struct qed_sp_init_data init_data; 1827f1093940SRam Amrani dma_addr_t resp_ramrod_res_phys; 1828f1093940SRam Amrani dma_addr_t req_ramrod_res_phys; 1829f1093940SRam Amrani struct qed_spq_entry *p_ent; 1830f1093940SRam Amrani bool rq_err_state; 1831f1093940SRam Amrani bool sq_err_state; 1832f1093940SRam Amrani bool sq_draining; 1833f1093940SRam Amrani int rc = -ENOMEM; 1834f1093940SRam Amrani 1835f1093940SRam Amrani if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) { 1836f1093940SRam Amrani /* We can't send ramrod to the fw since this qp wasn't offloaded 1837f1093940SRam Amrani * to the fw yet 1838f1093940SRam Amrani */ 1839f1093940SRam Amrani out_params->draining = false; 1840f1093940SRam Amrani out_params->rq_psn = qp->rq_psn; 1841f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 1842f1093940SRam Amrani out_params->state = qp->cur_state; 1843f1093940SRam Amrani 1844f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n"); 1845f1093940SRam Amrani return 0; 1846f1093940SRam Amrani } 1847f1093940SRam Amrani 1848f1093940SRam Amrani if (!(qp->resp_offloaded)) { 1849f1093940SRam Amrani DP_NOTICE(p_hwfn, 1850f1093940SRam Amrani "The responder's qp should be offloded before requester's\n"); 1851f1093940SRam Amrani return -EINVAL; 1852f1093940SRam Amrani } 1853f1093940SRam Amrani 1854f1093940SRam Amrani /* Send a query responder ramrod to FW to get RQ-PSN and state */ 1855f1093940SRam Amrani p_resp_ramrod_res = (struct roce_query_qp_resp_output_params *) 1856f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1857f1093940SRam Amrani sizeof(*p_resp_ramrod_res), 1858f1093940SRam Amrani &resp_ramrod_res_phys, GFP_KERNEL); 1859f1093940SRam Amrani if (!p_resp_ramrod_res) { 1860f1093940SRam Amrani DP_NOTICE(p_hwfn, 1861f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 1862f1093940SRam Amrani return rc; 1863f1093940SRam Amrani } 1864f1093940SRam Amrani 1865f1093940SRam Amrani /* Get SPQ entry */ 1866f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 1867f1093940SRam Amrani init_data.cid = qp->icid; 1868f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1869f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1870f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 1871f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1872f1093940SRam Amrani if (rc) 1873f1093940SRam Amrani goto err_resp; 1874f1093940SRam Amrani 1875f1093940SRam Amrani p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp; 1876f1093940SRam Amrani DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys); 1877f1093940SRam Amrani 1878f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1879f1093940SRam Amrani if (rc) 1880f1093940SRam Amrani goto err_resp; 1881f1093940SRam Amrani 1882f1093940SRam Amrani out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn); 1883f1093940SRam Amrani rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->err_flag), 1884f1093940SRam Amrani ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG); 1885f1093940SRam Amrani 1886c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 1887c5212b94SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 1888c5212b94SRam Amrani 1889f1093940SRam Amrani if (!(qp->req_offloaded)) { 1890f1093940SRam Amrani /* Don't send query qp for the requester */ 1891f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 1892f1093940SRam Amrani out_params->draining = false; 1893f1093940SRam Amrani 1894f1093940SRam Amrani if (rq_err_state) 1895f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 1896f1093940SRam Amrani 1897f1093940SRam Amrani out_params->state = qp->cur_state; 1898f1093940SRam Amrani 1899f1093940SRam Amrani return 0; 1900f1093940SRam Amrani } 1901f1093940SRam Amrani 1902f1093940SRam Amrani /* Send a query requester ramrod to FW to get SQ-PSN and state */ 1903f1093940SRam Amrani p_req_ramrod_res = (struct roce_query_qp_req_output_params *) 1904f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1905f1093940SRam Amrani sizeof(*p_req_ramrod_res), 1906f1093940SRam Amrani &req_ramrod_res_phys, 1907f1093940SRam Amrani GFP_KERNEL); 1908f1093940SRam Amrani if (!p_req_ramrod_res) { 1909f1093940SRam Amrani rc = -ENOMEM; 1910f1093940SRam Amrani DP_NOTICE(p_hwfn, 1911f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 1912f1093940SRam Amrani return rc; 1913f1093940SRam Amrani } 1914f1093940SRam Amrani 1915f1093940SRam Amrani /* Get SPQ entry */ 1916f1093940SRam Amrani init_data.cid = qp->icid + 1; 1917f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 1918f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 1919f1093940SRam Amrani if (rc) 1920f1093940SRam Amrani goto err_req; 1921f1093940SRam Amrani 1922f1093940SRam Amrani p_req_ramrod = &p_ent->ramrod.roce_query_qp_req; 1923f1093940SRam Amrani DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys); 1924f1093940SRam Amrani 1925f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 1926f1093940SRam Amrani if (rc) 1927f1093940SRam Amrani goto err_req; 1928f1093940SRam Amrani 1929f1093940SRam Amrani out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn); 1930f1093940SRam Amrani sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 1931f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG); 1932f1093940SRam Amrani sq_draining = 1933f1093940SRam Amrani GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 1934f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG); 1935f1093940SRam Amrani 1936c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 1937c5212b94SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 1938c5212b94SRam Amrani 1939f1093940SRam Amrani out_params->draining = false; 1940f1093940SRam Amrani 1941be086e7cSMintz, Yuval if (rq_err_state || sq_err_state) 1942f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 1943f1093940SRam Amrani else if (sq_draining) 1944f1093940SRam Amrani out_params->draining = true; 1945f1093940SRam Amrani out_params->state = qp->cur_state; 1946f1093940SRam Amrani 1947f1093940SRam Amrani return 0; 1948f1093940SRam Amrani 1949f1093940SRam Amrani err_req: 1950f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 1951f1093940SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 1952f1093940SRam Amrani return rc; 1953f1093940SRam Amrani err_resp: 1954f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 1955f1093940SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 1956f1093940SRam Amrani return rc; 1957f1093940SRam Amrani } 1958f1093940SRam Amrani 19598c93beafSYuval Mintz static int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 1960f1093940SRam Amrani { 1961f1093940SRam Amrani u32 num_invalidated_mw = 0; 1962f1093940SRam Amrani u32 num_bound_mw = 0; 1963be086e7cSMintz, Yuval u32 cq_prod; 1964f1093940SRam Amrani int rc; 1965f1093940SRam Amrani 1966f1093940SRam Amrani /* Destroys the specified QP */ 1967f1093940SRam Amrani if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) && 1968f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_ERR) && 1969f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_INIT)) { 1970f1093940SRam Amrani DP_NOTICE(p_hwfn, 1971f1093940SRam Amrani "QP must be in error, reset or init state before destroying it\n"); 1972f1093940SRam Amrani return -EINVAL; 1973f1093940SRam Amrani } 1974f1093940SRam Amrani 1975300c0d7cSRam Amrani if (qp->cur_state != QED_ROCE_QP_STATE_RESET) { 1976300c0d7cSRam Amrani rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, 1977be086e7cSMintz, Yuval &num_invalidated_mw, 1978be086e7cSMintz, Yuval &cq_prod); 1979f1093940SRam Amrani if (rc) 1980f1093940SRam Amrani return rc; 1981f1093940SRam Amrani 1982f1093940SRam Amrani /* Send destroy requester ramrod */ 1983300c0d7cSRam Amrani rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, 1984300c0d7cSRam Amrani &num_bound_mw); 1985f1093940SRam Amrani if (rc) 1986f1093940SRam Amrani return rc; 1987f1093940SRam Amrani 1988f1093940SRam Amrani if (num_invalidated_mw != num_bound_mw) { 1989f1093940SRam Amrani DP_NOTICE(p_hwfn, 1990f1093940SRam Amrani "number of invalidate memory windows is different from bounded ones\n"); 1991f1093940SRam Amrani return -EINVAL; 1992f1093940SRam Amrani } 1993300c0d7cSRam Amrani } 1994f1093940SRam Amrani 1995f1093940SRam Amrani return 0; 1996f1093940SRam Amrani } 1997f1093940SRam Amrani 19980189efb8SYuval Mintz static int qed_rdma_query_qp(void *rdma_cxt, 1999f1093940SRam Amrani struct qed_rdma_qp *qp, 2000f1093940SRam Amrani struct qed_rdma_query_qp_out_params *out_params) 2001f1093940SRam Amrani { 2002f1093940SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2003f1093940SRam Amrani int rc; 2004f1093940SRam Amrani 2005f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 2006f1093940SRam Amrani 2007f1093940SRam Amrani /* The following fields are filled in from qp and not FW as they can't 2008f1093940SRam Amrani * be modified by FW 2009f1093940SRam Amrani */ 2010f1093940SRam Amrani out_params->mtu = qp->mtu; 2011f1093940SRam Amrani out_params->dest_qp = qp->dest_qp; 2012f1093940SRam Amrani out_params->incoming_atomic_en = qp->incoming_atomic_en; 2013f1093940SRam Amrani out_params->e2e_flow_control_en = qp->e2e_flow_control_en; 2014f1093940SRam Amrani out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en; 2015f1093940SRam Amrani out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en; 2016f1093940SRam Amrani out_params->dgid = qp->dgid; 2017f1093940SRam Amrani out_params->flow_label = qp->flow_label; 2018f1093940SRam Amrani out_params->hop_limit_ttl = qp->hop_limit_ttl; 2019f1093940SRam Amrani out_params->traffic_class_tos = qp->traffic_class_tos; 2020f1093940SRam Amrani out_params->timeout = qp->ack_timeout; 2021f1093940SRam Amrani out_params->rnr_retry = qp->rnr_retry_cnt; 2022f1093940SRam Amrani out_params->retry_cnt = qp->retry_cnt; 2023f1093940SRam Amrani out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer; 2024f1093940SRam Amrani out_params->pkey_index = 0; 2025f1093940SRam Amrani out_params->max_rd_atomic = qp->max_rd_atomic_req; 2026f1093940SRam Amrani out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp; 2027f1093940SRam Amrani out_params->sqd_async = qp->sqd_async; 2028f1093940SRam Amrani 2029f1093940SRam Amrani rc = qed_roce_query_qp(p_hwfn, qp, out_params); 2030f1093940SRam Amrani 2031f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc); 2032f1093940SRam Amrani return rc; 2033f1093940SRam Amrani } 2034f1093940SRam Amrani 20350189efb8SYuval Mintz static int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp) 2036f1093940SRam Amrani { 2037f1093940SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2038f1093940SRam Amrani int rc = 0; 2039f1093940SRam Amrani 2040f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 2041f1093940SRam Amrani 2042f1093940SRam Amrani rc = qed_roce_destroy_qp(p_hwfn, qp); 2043f1093940SRam Amrani 2044f1093940SRam Amrani /* free qp params struct */ 2045f1093940SRam Amrani kfree(qp); 2046f1093940SRam Amrani 2047f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n"); 2048f1093940SRam Amrani return rc; 2049f1093940SRam Amrani } 2050f1093940SRam Amrani 20518c93beafSYuval Mintz static struct qed_rdma_qp * 2052f1093940SRam Amrani qed_rdma_create_qp(void *rdma_cxt, 2053f1093940SRam Amrani struct qed_rdma_create_qp_in_params *in_params, 2054f1093940SRam Amrani struct qed_rdma_create_qp_out_params *out_params) 2055f1093940SRam Amrani { 2056f1093940SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2057f1093940SRam Amrani struct qed_rdma_qp *qp; 2058f1093940SRam Amrani u8 max_stats_queues; 2059f1093940SRam Amrani int rc; 2060f1093940SRam Amrani 2061f1093940SRam Amrani if (!rdma_cxt || !in_params || !out_params || !p_hwfn->p_rdma_info) { 2062f1093940SRam Amrani DP_ERR(p_hwfn->cdev, 2063f1093940SRam Amrani "qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n", 2064f1093940SRam Amrani rdma_cxt, in_params, out_params); 2065f1093940SRam Amrani return NULL; 2066f1093940SRam Amrani } 2067f1093940SRam Amrani 2068f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2069f1093940SRam Amrani "qed rdma create qp called with qp_handle = %08x%08x\n", 2070f1093940SRam Amrani in_params->qp_handle_hi, in_params->qp_handle_lo); 2071f1093940SRam Amrani 2072f1093940SRam Amrani /* Some sanity checks... */ 2073f1093940SRam Amrani max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues; 2074f1093940SRam Amrani if (in_params->stats_queue >= max_stats_queues) { 2075f1093940SRam Amrani DP_ERR(p_hwfn->cdev, 2076f1093940SRam Amrani "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n", 2077f1093940SRam Amrani in_params->stats_queue, max_stats_queues); 2078f1093940SRam Amrani return NULL; 2079f1093940SRam Amrani } 2080f1093940SRam Amrani 2081f1093940SRam Amrani qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2082f1093940SRam Amrani if (!qp) { 2083f1093940SRam Amrani DP_NOTICE(p_hwfn, "Failed to allocate qed_rdma_qp\n"); 2084f1093940SRam Amrani return NULL; 2085f1093940SRam Amrani } 2086f1093940SRam Amrani 2087f1093940SRam Amrani rc = qed_roce_alloc_cid(p_hwfn, &qp->icid); 2088f1093940SRam Amrani qp->qpid = ((0xFF << 16) | qp->icid); 2089f1093940SRam Amrani 2090f1093940SRam Amrani DP_INFO(p_hwfn, "ROCE qpid=%x\n", qp->qpid); 2091f1093940SRam Amrani 2092f1093940SRam Amrani if (rc) { 2093f1093940SRam Amrani kfree(qp); 2094f1093940SRam Amrani return NULL; 2095f1093940SRam Amrani } 2096f1093940SRam Amrani 2097f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_RESET; 2098f1093940SRam Amrani qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi); 2099f1093940SRam Amrani qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo); 2100f1093940SRam Amrani qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi); 2101f1093940SRam Amrani qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo); 2102f1093940SRam Amrani qp->use_srq = in_params->use_srq; 2103f1093940SRam Amrani qp->signal_all = in_params->signal_all; 2104f1093940SRam Amrani qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey; 2105f1093940SRam Amrani qp->pd = in_params->pd; 2106f1093940SRam Amrani qp->dpi = in_params->dpi; 2107f1093940SRam Amrani qp->sq_cq_id = in_params->sq_cq_id; 2108f1093940SRam Amrani qp->sq_num_pages = in_params->sq_num_pages; 2109f1093940SRam Amrani qp->sq_pbl_ptr = in_params->sq_pbl_ptr; 2110f1093940SRam Amrani qp->rq_cq_id = in_params->rq_cq_id; 2111f1093940SRam Amrani qp->rq_num_pages = in_params->rq_num_pages; 2112f1093940SRam Amrani qp->rq_pbl_ptr = in_params->rq_pbl_ptr; 2113f1093940SRam Amrani qp->srq_id = in_params->srq_id; 2114f1093940SRam Amrani qp->req_offloaded = false; 2115f1093940SRam Amrani qp->resp_offloaded = false; 2116f1093940SRam Amrani qp->e2e_flow_control_en = qp->use_srq ? false : true; 2117f1093940SRam Amrani qp->stats_queue = in_params->stats_queue; 2118f1093940SRam Amrani 2119f1093940SRam Amrani out_params->icid = qp->icid; 2120f1093940SRam Amrani out_params->qp_id = qp->qpid; 2121f1093940SRam Amrani 2122f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc); 2123f1093940SRam Amrani return qp; 2124f1093940SRam Amrani } 2125f1093940SRam Amrani 2126f1093940SRam Amrani static int qed_roce_modify_qp(struct qed_hwfn *p_hwfn, 2127f1093940SRam Amrani struct qed_rdma_qp *qp, 2128f1093940SRam Amrani enum qed_roce_qp_state prev_state, 2129f1093940SRam Amrani struct qed_rdma_modify_qp_in_params *params) 2130f1093940SRam Amrani { 2131f1093940SRam Amrani u32 num_invalidated_mw = 0, num_bound_mw = 0; 2132f1093940SRam Amrani int rc = 0; 2133f1093940SRam Amrani 2134f1093940SRam Amrani /* Perform additional operations according to the current state and the 2135f1093940SRam Amrani * next state 2136f1093940SRam Amrani */ 2137f1093940SRam Amrani if (((prev_state == QED_ROCE_QP_STATE_INIT) || 2138f1093940SRam Amrani (prev_state == QED_ROCE_QP_STATE_RESET)) && 2139f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTR)) { 2140f1093940SRam Amrani /* Init->RTR or Reset->RTR */ 2141f1093940SRam Amrani rc = qed_roce_sp_create_responder(p_hwfn, qp); 2142f1093940SRam Amrani return rc; 2143f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTR) && 2144f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 2145f1093940SRam Amrani /* RTR-> RTS */ 2146f1093940SRam Amrani rc = qed_roce_sp_create_requester(p_hwfn, qp); 2147f1093940SRam Amrani if (rc) 2148f1093940SRam Amrani return rc; 2149f1093940SRam Amrani 2150f1093940SRam Amrani /* Send modify responder ramrod */ 2151f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2152f1093940SRam Amrani params->modify_flags); 2153f1093940SRam Amrani return rc; 2154f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 2155f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 2156f1093940SRam Amrani /* RTS->RTS */ 2157f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2158f1093940SRam Amrani params->modify_flags); 2159f1093940SRam Amrani if (rc) 2160f1093940SRam Amrani return rc; 2161f1093940SRam Amrani 2162f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 2163f1093940SRam Amrani params->modify_flags); 2164f1093940SRam Amrani return rc; 2165f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 2166f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 2167f1093940SRam Amrani /* RTS->SQD */ 2168f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false, 2169f1093940SRam Amrani params->modify_flags); 2170f1093940SRam Amrani return rc; 2171f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 2172f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 2173f1093940SRam Amrani /* SQD->SQD */ 2174f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2175f1093940SRam Amrani params->modify_flags); 2176f1093940SRam Amrani if (rc) 2177f1093940SRam Amrani return rc; 2178f1093940SRam Amrani 2179f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 2180f1093940SRam Amrani params->modify_flags); 2181f1093940SRam Amrani return rc; 2182f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 2183f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 2184f1093940SRam Amrani /* SQD->RTS */ 2185f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 2186f1093940SRam Amrani params->modify_flags); 2187f1093940SRam Amrani if (rc) 2188f1093940SRam Amrani return rc; 2189f1093940SRam Amrani 2190f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 2191f1093940SRam Amrani params->modify_flags); 2192f1093940SRam Amrani 2193f1093940SRam Amrani return rc; 2194ba0154e9SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR) { 2195f1093940SRam Amrani /* ->ERR */ 2196f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, true, 2197f1093940SRam Amrani params->modify_flags); 2198f1093940SRam Amrani if (rc) 2199f1093940SRam Amrani return rc; 2200f1093940SRam Amrani 2201f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true, 2202f1093940SRam Amrani params->modify_flags); 2203f1093940SRam Amrani return rc; 2204f1093940SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) { 2205f1093940SRam Amrani /* Any state -> RESET */ 2206be086e7cSMintz, Yuval u32 cq_prod; 2207f1093940SRam Amrani 2208be086e7cSMintz, Yuval /* Send destroy responder ramrod */ 2209be086e7cSMintz, Yuval rc = qed_roce_sp_destroy_qp_responder(p_hwfn, 2210be086e7cSMintz, Yuval qp, 2211be086e7cSMintz, Yuval &num_invalidated_mw, 2212be086e7cSMintz, Yuval &cq_prod); 2213be086e7cSMintz, Yuval 2214f1093940SRam Amrani if (rc) 2215f1093940SRam Amrani return rc; 2216f1093940SRam Amrani 2217be086e7cSMintz, Yuval qp->cq_prod = cq_prod; 2218be086e7cSMintz, Yuval 2219f1093940SRam Amrani rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, 2220f1093940SRam Amrani &num_bound_mw); 2221f1093940SRam Amrani 2222f1093940SRam Amrani if (num_invalidated_mw != num_bound_mw) { 2223f1093940SRam Amrani DP_NOTICE(p_hwfn, 2224f1093940SRam Amrani "number of invalidate memory windows is different from bounded ones\n"); 2225f1093940SRam Amrani return -EINVAL; 2226f1093940SRam Amrani } 2227f1093940SRam Amrani } else { 2228f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 2229f1093940SRam Amrani } 2230f1093940SRam Amrani 2231f1093940SRam Amrani return rc; 2232f1093940SRam Amrani } 2233f1093940SRam Amrani 22340189efb8SYuval Mintz static int qed_rdma_modify_qp(void *rdma_cxt, 2235f1093940SRam Amrani struct qed_rdma_qp *qp, 2236f1093940SRam Amrani struct qed_rdma_modify_qp_in_params *params) 2237f1093940SRam Amrani { 2238f1093940SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2239f1093940SRam Amrani enum qed_roce_qp_state prev_state; 2240f1093940SRam Amrani int rc = 0; 2241f1093940SRam Amrani 2242f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n", 2243f1093940SRam Amrani qp->icid, params->new_state); 2244f1093940SRam Amrani 2245f1093940SRam Amrani if (rc) { 2246f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2247f1093940SRam Amrani return rc; 2248f1093940SRam Amrani } 2249f1093940SRam Amrani 2250f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2251f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) { 2252f1093940SRam Amrani qp->incoming_rdma_read_en = params->incoming_rdma_read_en; 2253f1093940SRam Amrani qp->incoming_rdma_write_en = params->incoming_rdma_write_en; 2254f1093940SRam Amrani qp->incoming_atomic_en = params->incoming_atomic_en; 2255f1093940SRam Amrani } 2256f1093940SRam Amrani 2257f1093940SRam Amrani /* Update QP structure with the updated values */ 2258f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE)) 2259f1093940SRam Amrani qp->roce_mode = params->roce_mode; 2260f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)) 2261f1093940SRam Amrani qp->pkey = params->pkey; 2262f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2263f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN)) 2264f1093940SRam Amrani qp->e2e_flow_control_en = params->e2e_flow_control_en; 2265f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP)) 2266f1093940SRam Amrani qp->dest_qp = params->dest_qp; 2267f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2268f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) { 2269f1093940SRam Amrani /* Indicates that the following parameters have changed: 2270f1093940SRam Amrani * Traffic class, flow label, hop limit, source GID, 2271f1093940SRam Amrani * destination GID, loopback indicator 2272f1093940SRam Amrani */ 2273f1093940SRam Amrani qp->traffic_class_tos = params->traffic_class_tos; 2274f1093940SRam Amrani qp->flow_label = params->flow_label; 2275f1093940SRam Amrani qp->hop_limit_ttl = params->hop_limit_ttl; 2276f1093940SRam Amrani 2277f1093940SRam Amrani qp->sgid = params->sgid; 2278f1093940SRam Amrani qp->dgid = params->dgid; 2279f1093940SRam Amrani qp->udp_src_port = 0; 2280f1093940SRam Amrani qp->vlan_id = params->vlan_id; 2281f1093940SRam Amrani qp->mtu = params->mtu; 2282f1093940SRam Amrani qp->lb_indication = params->lb_indication; 2283f1093940SRam Amrani memcpy((u8 *)&qp->remote_mac_addr[0], 2284f1093940SRam Amrani (u8 *)¶ms->remote_mac_addr[0], ETH_ALEN); 2285f1093940SRam Amrani if (params->use_local_mac) { 2286f1093940SRam Amrani memcpy((u8 *)&qp->local_mac_addr[0], 2287f1093940SRam Amrani (u8 *)¶ms->local_mac_addr[0], ETH_ALEN); 2288f1093940SRam Amrani } else { 2289f1093940SRam Amrani memcpy((u8 *)&qp->local_mac_addr[0], 2290f1093940SRam Amrani (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN); 2291f1093940SRam Amrani } 2292f1093940SRam Amrani } 2293f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN)) 2294f1093940SRam Amrani qp->rq_psn = params->rq_psn; 2295f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN)) 2296f1093940SRam Amrani qp->sq_psn = params->sq_psn; 2297f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2298f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)) 2299f1093940SRam Amrani qp->max_rd_atomic_req = params->max_rd_atomic_req; 2300f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2301f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)) 2302f1093940SRam Amrani qp->max_rd_atomic_resp = params->max_rd_atomic_resp; 2303f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2304f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)) 2305f1093940SRam Amrani qp->ack_timeout = params->ack_timeout; 2306f1093940SRam Amrani if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)) 2307f1093940SRam Amrani qp->retry_cnt = params->retry_cnt; 2308f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2309f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)) 2310f1093940SRam Amrani qp->rnr_retry_cnt = params->rnr_retry_cnt; 2311f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2312f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)) 2313f1093940SRam Amrani qp->min_rnr_nak_timer = params->min_rnr_nak_timer; 2314f1093940SRam Amrani 2315f1093940SRam Amrani qp->sqd_async = params->sqd_async; 2316f1093940SRam Amrani 2317f1093940SRam Amrani prev_state = qp->cur_state; 2318f1093940SRam Amrani if (GET_FIELD(params->modify_flags, 2319f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) { 2320f1093940SRam Amrani qp->cur_state = params->new_state; 2321f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n", 2322f1093940SRam Amrani qp->cur_state); 2323f1093940SRam Amrani } 2324f1093940SRam Amrani 2325f1093940SRam Amrani rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params); 2326f1093940SRam Amrani 2327f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc); 2328f1093940SRam Amrani return rc; 2329f1093940SRam Amrani } 2330f1093940SRam Amrani 23310189efb8SYuval Mintz static int 23320189efb8SYuval Mintz qed_rdma_register_tid(void *rdma_cxt, 2333ee8eaea3SRam Amrani struct qed_rdma_register_tid_in_params *params) 2334ee8eaea3SRam Amrani { 2335ee8eaea3SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2336ee8eaea3SRam Amrani struct rdma_register_tid_ramrod_data *p_ramrod; 2337ee8eaea3SRam Amrani struct qed_sp_init_data init_data; 2338ee8eaea3SRam Amrani struct qed_spq_entry *p_ent; 2339ee8eaea3SRam Amrani enum rdma_tid_type tid_type; 2340ee8eaea3SRam Amrani u8 fw_return_code; 2341ee8eaea3SRam Amrani int rc; 2342ee8eaea3SRam Amrani 2343ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", params->itid); 2344ee8eaea3SRam Amrani 2345ee8eaea3SRam Amrani /* Get SPQ entry */ 2346ee8eaea3SRam Amrani memset(&init_data, 0, sizeof(init_data)); 2347ee8eaea3SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 2348ee8eaea3SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 2349ee8eaea3SRam Amrani 2350ee8eaea3SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_REGISTER_MR, 2351ee8eaea3SRam Amrani p_hwfn->p_rdma_info->proto, &init_data); 2352ee8eaea3SRam Amrani if (rc) { 2353ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2354ee8eaea3SRam Amrani return rc; 2355ee8eaea3SRam Amrani } 2356ee8eaea3SRam Amrani 2357ee8eaea3SRam Amrani if (p_hwfn->p_rdma_info->last_tid < params->itid) 2358ee8eaea3SRam Amrani p_hwfn->p_rdma_info->last_tid = params->itid; 2359ee8eaea3SRam Amrani 2360ee8eaea3SRam Amrani p_ramrod = &p_ent->ramrod.rdma_register_tid; 2361ee8eaea3SRam Amrani 2362ee8eaea3SRam Amrani p_ramrod->flags = 0; 2363ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2364ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL, 2365ee8eaea3SRam Amrani params->pbl_two_level); 2366ee8eaea3SRam Amrani 2367ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2368ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED, params->zbva); 2369ee8eaea3SRam Amrani 2370ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2371ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR, params->phy_mr); 2372ee8eaea3SRam Amrani 2373ee8eaea3SRam Amrani /* Don't initialize D/C field, as it may override other bits. */ 2374ee8eaea3SRam Amrani if (!(params->tid_type == QED_RDMA_TID_FMR) && !(params->dma_mr)) 2375ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2376ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG, 2377ee8eaea3SRam Amrani params->page_size_log - 12); 2378ee8eaea3SRam Amrani 2379ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2380ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID, 2381ee8eaea3SRam Amrani p_hwfn->p_rdma_info->last_tid); 2382ee8eaea3SRam Amrani 2383ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2384ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ, 2385ee8eaea3SRam Amrani params->remote_read); 2386ee8eaea3SRam Amrani 2387ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2388ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE, 2389ee8eaea3SRam Amrani params->remote_write); 2390ee8eaea3SRam Amrani 2391ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2392ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC, 2393ee8eaea3SRam Amrani params->remote_atomic); 2394ee8eaea3SRam Amrani 2395ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2396ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE, 2397ee8eaea3SRam Amrani params->local_write); 2398ee8eaea3SRam Amrani 2399ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2400ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ, params->local_read); 2401ee8eaea3SRam Amrani 2402ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags, 2403ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND, 2404ee8eaea3SRam Amrani params->mw_bind); 2405ee8eaea3SRam Amrani 2406ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags1, 2407ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG, 2408ee8eaea3SRam Amrani params->pbl_page_size_log - 12); 2409ee8eaea3SRam Amrani 2410ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags2, 2411ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR, params->dma_mr); 2412ee8eaea3SRam Amrani 2413ee8eaea3SRam Amrani switch (params->tid_type) { 2414ee8eaea3SRam Amrani case QED_RDMA_TID_REGISTERED_MR: 2415ee8eaea3SRam Amrani tid_type = RDMA_TID_REGISTERED_MR; 2416ee8eaea3SRam Amrani break; 2417ee8eaea3SRam Amrani case QED_RDMA_TID_FMR: 2418ee8eaea3SRam Amrani tid_type = RDMA_TID_FMR; 2419ee8eaea3SRam Amrani break; 2420ee8eaea3SRam Amrani case QED_RDMA_TID_MW_TYPE1: 2421ee8eaea3SRam Amrani tid_type = RDMA_TID_MW_TYPE1; 2422ee8eaea3SRam Amrani break; 2423ee8eaea3SRam Amrani case QED_RDMA_TID_MW_TYPE2A: 2424ee8eaea3SRam Amrani tid_type = RDMA_TID_MW_TYPE2A; 2425ee8eaea3SRam Amrani break; 2426ee8eaea3SRam Amrani default: 2427ee8eaea3SRam Amrani rc = -EINVAL; 2428ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2429ee8eaea3SRam Amrani return rc; 2430ee8eaea3SRam Amrani } 2431ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags1, 2432ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE, tid_type); 2433ee8eaea3SRam Amrani 2434ee8eaea3SRam Amrani p_ramrod->itid = cpu_to_le32(params->itid); 2435ee8eaea3SRam Amrani p_ramrod->key = params->key; 2436ee8eaea3SRam Amrani p_ramrod->pd = cpu_to_le16(params->pd); 2437ee8eaea3SRam Amrani p_ramrod->length_hi = (u8)(params->length >> 32); 2438ee8eaea3SRam Amrani p_ramrod->length_lo = DMA_LO_LE(params->length); 2439ee8eaea3SRam Amrani if (params->zbva) { 2440ee8eaea3SRam Amrani /* Lower 32 bits of the registered MR address. 2441ee8eaea3SRam Amrani * In case of zero based MR, will hold FBO 2442ee8eaea3SRam Amrani */ 2443ee8eaea3SRam Amrani p_ramrod->va.hi = 0; 2444ee8eaea3SRam Amrani p_ramrod->va.lo = cpu_to_le32(params->fbo); 2445ee8eaea3SRam Amrani } else { 2446ee8eaea3SRam Amrani DMA_REGPAIR_LE(p_ramrod->va, params->vaddr); 2447ee8eaea3SRam Amrani } 2448ee8eaea3SRam Amrani DMA_REGPAIR_LE(p_ramrod->pbl_base, params->pbl_ptr); 2449ee8eaea3SRam Amrani 2450ee8eaea3SRam Amrani /* DIF */ 2451ee8eaea3SRam Amrani if (params->dif_enabled) { 2452ee8eaea3SRam Amrani SET_FIELD(p_ramrod->flags2, 2453ee8eaea3SRam Amrani RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG, 1); 2454ee8eaea3SRam Amrani DMA_REGPAIR_LE(p_ramrod->dif_error_addr, 2455ee8eaea3SRam Amrani params->dif_error_addr); 2456ee8eaea3SRam Amrani DMA_REGPAIR_LE(p_ramrod->dif_runt_addr, params->dif_runt_addr); 2457ee8eaea3SRam Amrani } 2458ee8eaea3SRam Amrani 2459ee8eaea3SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 2460ee8eaea3SRam Amrani 2461ee8eaea3SRam Amrani if (fw_return_code != RDMA_RETURN_OK) { 2462ee8eaea3SRam Amrani DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 2463ee8eaea3SRam Amrani return -EINVAL; 2464ee8eaea3SRam Amrani } 2465ee8eaea3SRam Amrani 2466ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Register TID, rc = %d\n", rc); 2467ee8eaea3SRam Amrani return rc; 2468ee8eaea3SRam Amrani } 2469ee8eaea3SRam Amrani 24700189efb8SYuval Mintz static int qed_rdma_deregister_tid(void *rdma_cxt, u32 itid) 2471ee8eaea3SRam Amrani { 2472ee8eaea3SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 2473ee8eaea3SRam Amrani struct rdma_deregister_tid_ramrod_data *p_ramrod; 2474ee8eaea3SRam Amrani struct qed_sp_init_data init_data; 2475ee8eaea3SRam Amrani struct qed_spq_entry *p_ent; 2476ee8eaea3SRam Amrani struct qed_ptt *p_ptt; 2477ee8eaea3SRam Amrani u8 fw_return_code; 2478ee8eaea3SRam Amrani int rc; 2479ee8eaea3SRam Amrani 2480ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 2481ee8eaea3SRam Amrani 2482ee8eaea3SRam Amrani /* Get SPQ entry */ 2483ee8eaea3SRam Amrani memset(&init_data, 0, sizeof(init_data)); 2484ee8eaea3SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 2485ee8eaea3SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 2486ee8eaea3SRam Amrani 2487ee8eaea3SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_DEREGISTER_MR, 2488ee8eaea3SRam Amrani p_hwfn->p_rdma_info->proto, &init_data); 2489ee8eaea3SRam Amrani if (rc) { 2490ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2491ee8eaea3SRam Amrani return rc; 2492ee8eaea3SRam Amrani } 2493ee8eaea3SRam Amrani 2494ee8eaea3SRam Amrani p_ramrod = &p_ent->ramrod.rdma_deregister_tid; 2495ee8eaea3SRam Amrani p_ramrod->itid = cpu_to_le32(itid); 2496ee8eaea3SRam Amrani 2497ee8eaea3SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 2498ee8eaea3SRam Amrani if (rc) { 2499ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 2500ee8eaea3SRam Amrani return rc; 2501ee8eaea3SRam Amrani } 2502ee8eaea3SRam Amrani 2503ee8eaea3SRam Amrani if (fw_return_code == RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR) { 2504ee8eaea3SRam Amrani DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 2505ee8eaea3SRam Amrani return -EINVAL; 2506ee8eaea3SRam Amrani } else if (fw_return_code == RDMA_RETURN_NIG_DRAIN_REQ) { 2507ee8eaea3SRam Amrani /* Bit indicating that the TID is in use and a nig drain is 2508ee8eaea3SRam Amrani * required before sending the ramrod again 2509ee8eaea3SRam Amrani */ 2510ee8eaea3SRam Amrani p_ptt = qed_ptt_acquire(p_hwfn); 2511ee8eaea3SRam Amrani if (!p_ptt) { 2512ee8eaea3SRam Amrani rc = -EBUSY; 2513ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2514ee8eaea3SRam Amrani "Failed to acquire PTT\n"); 2515ee8eaea3SRam Amrani return rc; 2516ee8eaea3SRam Amrani } 2517ee8eaea3SRam Amrani 2518ee8eaea3SRam Amrani rc = qed_mcp_drain(p_hwfn, p_ptt); 2519ee8eaea3SRam Amrani if (rc) { 2520ee8eaea3SRam Amrani qed_ptt_release(p_hwfn, p_ptt); 2521ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2522ee8eaea3SRam Amrani "Drain failed\n"); 2523ee8eaea3SRam Amrani return rc; 2524ee8eaea3SRam Amrani } 2525ee8eaea3SRam Amrani 2526ee8eaea3SRam Amrani qed_ptt_release(p_hwfn, p_ptt); 2527ee8eaea3SRam Amrani 2528ee8eaea3SRam Amrani /* Resend the ramrod */ 2529ee8eaea3SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 2530ee8eaea3SRam Amrani RDMA_RAMROD_DEREGISTER_MR, 2531ee8eaea3SRam Amrani p_hwfn->p_rdma_info->proto, 2532ee8eaea3SRam Amrani &init_data); 2533ee8eaea3SRam Amrani if (rc) { 2534ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2535ee8eaea3SRam Amrani "Failed to init sp-element\n"); 2536ee8eaea3SRam Amrani return rc; 2537ee8eaea3SRam Amrani } 2538ee8eaea3SRam Amrani 2539ee8eaea3SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 2540ee8eaea3SRam Amrani if (rc) { 2541ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 2542ee8eaea3SRam Amrani "Ramrod failed\n"); 2543ee8eaea3SRam Amrani return rc; 2544ee8eaea3SRam Amrani } 2545ee8eaea3SRam Amrani 2546ee8eaea3SRam Amrani if (fw_return_code != RDMA_RETURN_OK) { 2547ee8eaea3SRam Amrani DP_NOTICE(p_hwfn, "fw_return_code = %d\n", 2548ee8eaea3SRam Amrani fw_return_code); 2549ee8eaea3SRam Amrani return rc; 2550ee8eaea3SRam Amrani } 2551ee8eaea3SRam Amrani } 2552ee8eaea3SRam Amrani 2553ee8eaea3SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "De-registered TID, rc = %d\n", rc); 2554ee8eaea3SRam Amrani return rc; 2555ee8eaea3SRam Amrani } 2556ee8eaea3SRam Amrani 2557be086e7cSMintz, Yuval static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid) 2558be086e7cSMintz, Yuval { 2559be086e7cSMintz, Yuval struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 2560be086e7cSMintz, Yuval u32 start_cid, cid, xcid; 2561be086e7cSMintz, Yuval 2562be086e7cSMintz, Yuval /* an even icid belongs to a responder while an odd icid belongs to a 2563be086e7cSMintz, Yuval * requester. The 'cid' received as an input can be either. We calculate 2564be086e7cSMintz, Yuval * the "partner" icid and call it xcid. Only if both are free then the 2565be086e7cSMintz, Yuval * "cid" map can be cleared. 2566be086e7cSMintz, Yuval */ 2567be086e7cSMintz, Yuval start_cid = qed_cxt_get_proto_cid_start(p_hwfn, p_rdma_info->proto); 2568be086e7cSMintz, Yuval cid = icid - start_cid; 2569be086e7cSMintz, Yuval xcid = cid ^ 1; 2570be086e7cSMintz, Yuval 2571be086e7cSMintz, Yuval spin_lock_bh(&p_rdma_info->lock); 2572be086e7cSMintz, Yuval 2573be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->real_cid_map, cid); 2574be086e7cSMintz, Yuval if (qed_bmap_test_id(p_hwfn, &p_rdma_info->real_cid_map, xcid) == 0) { 2575be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, cid); 2576be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, xcid); 2577be086e7cSMintz, Yuval } 2578be086e7cSMintz, Yuval 2579be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 2580be086e7cSMintz, Yuval } 2581be086e7cSMintz, Yuval 258251ff1725SRam Amrani static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev) 258351ff1725SRam Amrani { 258451ff1725SRam Amrani return QED_LEADING_HWFN(cdev); 258551ff1725SRam Amrani } 258651ff1725SRam Amrani 258751ff1725SRam Amrani static void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 258851ff1725SRam Amrani { 258951ff1725SRam Amrani u32 val; 259051ff1725SRam Amrani 259151ff1725SRam Amrani val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1; 259251ff1725SRam Amrani 259351ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val); 259451ff1725SRam Amrani DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA), 259551ff1725SRam Amrani "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n", 259651ff1725SRam Amrani val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm); 259751ff1725SRam Amrani } 259851ff1725SRam Amrani 259951ff1725SRam Amrani void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 260051ff1725SRam Amrani { 260151ff1725SRam Amrani p_hwfn->db_bar_no_edpm = true; 260251ff1725SRam Amrani 260351ff1725SRam Amrani qed_rdma_dpm_conf(p_hwfn, p_ptt); 260451ff1725SRam Amrani } 260551ff1725SRam Amrani 26060189efb8SYuval Mintz static int qed_rdma_start(void *rdma_cxt, 26070189efb8SYuval Mintz struct qed_rdma_start_in_params *params) 260851ff1725SRam Amrani { 260951ff1725SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 261051ff1725SRam Amrani struct qed_ptt *p_ptt; 261151ff1725SRam Amrani int rc = -EBUSY; 261251ff1725SRam Amrani 261351ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 261451ff1725SRam Amrani "desired_cnq = %08x\n", params->desired_cnq); 261551ff1725SRam Amrani 261651ff1725SRam Amrani p_ptt = qed_ptt_acquire(p_hwfn); 261751ff1725SRam Amrani if (!p_ptt) 261851ff1725SRam Amrani goto err; 261951ff1725SRam Amrani 262051ff1725SRam Amrani rc = qed_rdma_alloc(p_hwfn, p_ptt, params); 262151ff1725SRam Amrani if (rc) 262251ff1725SRam Amrani goto err1; 262351ff1725SRam Amrani 262451ff1725SRam Amrani rc = qed_rdma_setup(p_hwfn, p_ptt, params); 262551ff1725SRam Amrani if (rc) 262651ff1725SRam Amrani goto err2; 262751ff1725SRam Amrani 262851ff1725SRam Amrani qed_ptt_release(p_hwfn, p_ptt); 262951ff1725SRam Amrani 263051ff1725SRam Amrani return rc; 263151ff1725SRam Amrani 263251ff1725SRam Amrani err2: 263351ff1725SRam Amrani qed_rdma_free(p_hwfn); 263451ff1725SRam Amrani err1: 263551ff1725SRam Amrani qed_ptt_release(p_hwfn, p_ptt); 263651ff1725SRam Amrani err: 263751ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc); 263851ff1725SRam Amrani return rc; 263951ff1725SRam Amrani } 264051ff1725SRam Amrani 264151ff1725SRam Amrani static int qed_rdma_init(struct qed_dev *cdev, 264251ff1725SRam Amrani struct qed_rdma_start_in_params *params) 264351ff1725SRam Amrani { 264451ff1725SRam Amrani return qed_rdma_start(QED_LEADING_HWFN(cdev), params); 264551ff1725SRam Amrani } 264651ff1725SRam Amrani 26470189efb8SYuval Mintz static void qed_rdma_remove_user(void *rdma_cxt, u16 dpi) 264851ff1725SRam Amrani { 264951ff1725SRam Amrani struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 265051ff1725SRam Amrani 265151ff1725SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi); 265251ff1725SRam Amrani 265351ff1725SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 265451ff1725SRam Amrani qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi); 265551ff1725SRam Amrani spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 265651ff1725SRam Amrani } 265751ff1725SRam Amrani 2658abd49676SRam Amrani void qed_ll2b_complete_tx_gsi_packet(struct qed_hwfn *p_hwfn, 2659abd49676SRam Amrani u8 connection_handle, 2660abd49676SRam Amrani void *cookie, 2661abd49676SRam Amrani dma_addr_t first_frag_addr, 2662abd49676SRam Amrani bool b_last_fragment, bool b_last_packet) 2663abd49676SRam Amrani { 2664abd49676SRam Amrani struct qed_roce_ll2_packet *packet = cookie; 2665abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2 = p_hwfn->ll2; 2666abd49676SRam Amrani 2667abd49676SRam Amrani roce_ll2->cbs.tx_cb(roce_ll2->cb_cookie, packet); 2668abd49676SRam Amrani } 2669abd49676SRam Amrani 2670abd49676SRam Amrani void qed_ll2b_release_tx_gsi_packet(struct qed_hwfn *p_hwfn, 2671abd49676SRam Amrani u8 connection_handle, 2672abd49676SRam Amrani void *cookie, 2673abd49676SRam Amrani dma_addr_t first_frag_addr, 2674abd49676SRam Amrani bool b_last_fragment, bool b_last_packet) 2675abd49676SRam Amrani { 2676abd49676SRam Amrani qed_ll2b_complete_tx_gsi_packet(p_hwfn, connection_handle, 2677abd49676SRam Amrani cookie, first_frag_addr, 2678abd49676SRam Amrani b_last_fragment, b_last_packet); 2679abd49676SRam Amrani } 2680abd49676SRam Amrani 2681abd49676SRam Amrani void qed_ll2b_complete_rx_gsi_packet(struct qed_hwfn *p_hwfn, 2682abd49676SRam Amrani u8 connection_handle, 2683abd49676SRam Amrani void *cookie, 2684abd49676SRam Amrani dma_addr_t rx_buf_addr, 2685abd49676SRam Amrani u16 data_length, 2686abd49676SRam Amrani u8 data_length_error, 2687abd49676SRam Amrani u16 parse_flags, 2688abd49676SRam Amrani u16 vlan, 2689abd49676SRam Amrani u32 src_mac_addr_hi, 2690abd49676SRam Amrani u16 src_mac_addr_lo, bool b_last_packet) 2691abd49676SRam Amrani { 2692abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2 = p_hwfn->ll2; 2693abd49676SRam Amrani struct qed_roce_ll2_rx_params params; 2694abd49676SRam Amrani struct qed_dev *cdev = p_hwfn->cdev; 2695abd49676SRam Amrani struct qed_roce_ll2_packet pkt; 2696abd49676SRam Amrani 2697abd49676SRam Amrani DP_VERBOSE(cdev, 2698abd49676SRam Amrani QED_MSG_LL2, 2699abd49676SRam Amrani "roce ll2 rx complete: bus_addr=%p, len=%d, data_len_err=%d\n", 2700abd49676SRam Amrani (void *)(uintptr_t)rx_buf_addr, 2701abd49676SRam Amrani data_length, data_length_error); 2702abd49676SRam Amrani 2703abd49676SRam Amrani memset(&pkt, 0, sizeof(pkt)); 2704abd49676SRam Amrani pkt.n_seg = 1; 2705abd49676SRam Amrani pkt.payload[0].baddr = rx_buf_addr; 2706abd49676SRam Amrani pkt.payload[0].len = data_length; 2707abd49676SRam Amrani 2708abd49676SRam Amrani memset(¶ms, 0, sizeof(params)); 2709abd49676SRam Amrani params.vlan_id = vlan; 2710abd49676SRam Amrani *((u32 *)¶ms.smac[0]) = ntohl(src_mac_addr_hi); 2711abd49676SRam Amrani *((u16 *)¶ms.smac[4]) = ntohs(src_mac_addr_lo); 2712abd49676SRam Amrani 2713abd49676SRam Amrani if (data_length_error) { 2714abd49676SRam Amrani DP_ERR(cdev, 2715abd49676SRam Amrani "roce ll2 rx complete: data length error %d, length=%d\n", 2716abd49676SRam Amrani data_length_error, data_length); 2717abd49676SRam Amrani params.rc = -EINVAL; 2718abd49676SRam Amrani } 2719abd49676SRam Amrani 2720abd49676SRam Amrani roce_ll2->cbs.rx_cb(roce_ll2->cb_cookie, &pkt, ¶ms); 2721abd49676SRam Amrani } 2722abd49676SRam Amrani 2723abd49676SRam Amrani static int qed_roce_ll2_set_mac_filter(struct qed_dev *cdev, 2724abd49676SRam Amrani u8 *old_mac_address, 2725abd49676SRam Amrani u8 *new_mac_address) 2726abd49676SRam Amrani { 2727abd49676SRam Amrani struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2728abd49676SRam Amrani struct qed_ptt *p_ptt; 2729abd49676SRam Amrani int rc = 0; 2730abd49676SRam Amrani 2731abd49676SRam Amrani if (!hwfn->ll2 || hwfn->ll2->handle == QED_LL2_UNUSED_HANDLE) { 2732abd49676SRam Amrani DP_ERR(cdev, 2733abd49676SRam Amrani "qed roce mac filter failed - roce_info/ll2 NULL\n"); 2734abd49676SRam Amrani return -EINVAL; 2735abd49676SRam Amrani } 2736abd49676SRam Amrani 2737abd49676SRam Amrani p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 2738abd49676SRam Amrani if (!p_ptt) { 2739abd49676SRam Amrani DP_ERR(cdev, 2740abd49676SRam Amrani "qed roce ll2 mac filter set: failed to acquire PTT\n"); 2741abd49676SRam Amrani return -EINVAL; 2742abd49676SRam Amrani } 2743abd49676SRam Amrani 2744abd49676SRam Amrani mutex_lock(&hwfn->ll2->lock); 2745abd49676SRam Amrani if (old_mac_address) 2746abd49676SRam Amrani qed_llh_remove_mac_filter(QED_LEADING_HWFN(cdev), p_ptt, 2747abd49676SRam Amrani old_mac_address); 2748abd49676SRam Amrani if (new_mac_address) 2749abd49676SRam Amrani rc = qed_llh_add_mac_filter(QED_LEADING_HWFN(cdev), p_ptt, 2750abd49676SRam Amrani new_mac_address); 2751abd49676SRam Amrani mutex_unlock(&hwfn->ll2->lock); 2752abd49676SRam Amrani 2753abd49676SRam Amrani qed_ptt_release(QED_LEADING_HWFN(cdev), p_ptt); 2754abd49676SRam Amrani 2755abd49676SRam Amrani if (rc) 2756abd49676SRam Amrani DP_ERR(cdev, 2757abd49676SRam Amrani "qed roce ll2 mac filter set: failed to add mac filter\n"); 2758abd49676SRam Amrani 2759abd49676SRam Amrani return rc; 2760abd49676SRam Amrani } 2761abd49676SRam Amrani 2762abd49676SRam Amrani static int qed_roce_ll2_start(struct qed_dev *cdev, 2763abd49676SRam Amrani struct qed_roce_ll2_params *params) 2764abd49676SRam Amrani { 2765abd49676SRam Amrani struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2766abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2; 27670629a330SArnd Bergmann struct qed_ll2_conn ll2_params; 2768abd49676SRam Amrani int rc; 2769abd49676SRam Amrani 2770abd49676SRam Amrani if (!params) { 2771abd49676SRam Amrani DP_ERR(cdev, "qed roce ll2 start: failed due to NULL params\n"); 2772abd49676SRam Amrani return -EINVAL; 2773abd49676SRam Amrani } 2774abd49676SRam Amrani if (!params->cbs.tx_cb || !params->cbs.rx_cb) { 2775abd49676SRam Amrani DP_ERR(cdev, 2776abd49676SRam Amrani "qed roce ll2 start: failed due to NULL tx/rx. tx_cb=%p, rx_cb=%p\n", 2777abd49676SRam Amrani params->cbs.tx_cb, params->cbs.rx_cb); 2778abd49676SRam Amrani return -EINVAL; 2779abd49676SRam Amrani } 2780abd49676SRam Amrani if (!is_valid_ether_addr(params->mac_address)) { 2781abd49676SRam Amrani DP_ERR(cdev, 2782abd49676SRam Amrani "qed roce ll2 start: failed due to invalid Ethernet address %pM\n", 2783abd49676SRam Amrani params->mac_address); 2784abd49676SRam Amrani return -EINVAL; 2785abd49676SRam Amrani } 2786abd49676SRam Amrani 2787abd49676SRam Amrani /* Initialize */ 2788abd49676SRam Amrani roce_ll2 = kzalloc(sizeof(*roce_ll2), GFP_ATOMIC); 2789abd49676SRam Amrani if (!roce_ll2) { 2790abd49676SRam Amrani DP_ERR(cdev, "qed roce ll2 start: failed memory allocation\n"); 2791abd49676SRam Amrani return -ENOMEM; 2792abd49676SRam Amrani } 2793abd49676SRam Amrani roce_ll2->handle = QED_LL2_UNUSED_HANDLE; 2794abd49676SRam Amrani roce_ll2->cbs = params->cbs; 2795abd49676SRam Amrani roce_ll2->cb_cookie = params->cb_cookie; 2796abd49676SRam Amrani mutex_init(&roce_ll2->lock); 2797abd49676SRam Amrani 2798abd49676SRam Amrani memset(&ll2_params, 0, sizeof(ll2_params)); 2799abd49676SRam Amrani ll2_params.conn_type = QED_LL2_TYPE_ROCE; 2800abd49676SRam Amrani ll2_params.mtu = params->mtu; 2801abd49676SRam Amrani ll2_params.rx_drop_ttl0_flg = true; 2802abd49676SRam Amrani ll2_params.rx_vlan_removal_en = false; 2803abd49676SRam Amrani ll2_params.tx_dest = CORE_TX_DEST_NW; 2804abd49676SRam Amrani ll2_params.ai_err_packet_too_big = LL2_DROP_PACKET; 2805abd49676SRam Amrani ll2_params.ai_err_no_buf = LL2_DROP_PACKET; 2806abd49676SRam Amrani ll2_params.gsi_enable = true; 2807abd49676SRam Amrani 2808abd49676SRam Amrani rc = qed_ll2_acquire_connection(QED_LEADING_HWFN(cdev), &ll2_params, 2809abd49676SRam Amrani params->max_rx_buffers, 2810abd49676SRam Amrani params->max_tx_buffers, 2811abd49676SRam Amrani &roce_ll2->handle); 2812abd49676SRam Amrani if (rc) { 2813abd49676SRam Amrani DP_ERR(cdev, 2814abd49676SRam Amrani "qed roce ll2 start: failed to acquire LL2 connection (rc=%d)\n", 2815abd49676SRam Amrani rc); 2816abd49676SRam Amrani goto err; 2817abd49676SRam Amrani } 2818abd49676SRam Amrani 2819abd49676SRam Amrani rc = qed_ll2_establish_connection(QED_LEADING_HWFN(cdev), 2820abd49676SRam Amrani roce_ll2->handle); 2821abd49676SRam Amrani if (rc) { 2822abd49676SRam Amrani DP_ERR(cdev, 2823abd49676SRam Amrani "qed roce ll2 start: failed to establish LL2 connection (rc=%d)\n", 2824abd49676SRam Amrani rc); 2825abd49676SRam Amrani goto err1; 2826abd49676SRam Amrani } 2827abd49676SRam Amrani 2828abd49676SRam Amrani hwfn->ll2 = roce_ll2; 2829abd49676SRam Amrani 2830abd49676SRam Amrani rc = qed_roce_ll2_set_mac_filter(cdev, NULL, params->mac_address); 2831abd49676SRam Amrani if (rc) { 2832abd49676SRam Amrani hwfn->ll2 = NULL; 2833abd49676SRam Amrani goto err2; 2834abd49676SRam Amrani } 2835abd49676SRam Amrani ether_addr_copy(roce_ll2->mac_address, params->mac_address); 2836abd49676SRam Amrani 2837abd49676SRam Amrani return 0; 2838abd49676SRam Amrani 2839abd49676SRam Amrani err2: 2840abd49676SRam Amrani qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle); 2841abd49676SRam Amrani err1: 2842abd49676SRam Amrani qed_ll2_release_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle); 2843abd49676SRam Amrani err: 2844abd49676SRam Amrani kfree(roce_ll2); 2845abd49676SRam Amrani return rc; 2846abd49676SRam Amrani } 2847abd49676SRam Amrani 2848abd49676SRam Amrani static int qed_roce_ll2_stop(struct qed_dev *cdev) 2849abd49676SRam Amrani { 2850abd49676SRam Amrani struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2851abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2; 2852abd49676SRam Amrani int rc; 2853abd49676SRam Amrani 2854abd49676SRam Amrani if (roce_ll2->handle == QED_LL2_UNUSED_HANDLE) { 2855abd49676SRam Amrani DP_ERR(cdev, "qed roce ll2 stop: cannot stop an unused LL2\n"); 2856abd49676SRam Amrani return -EINVAL; 2857abd49676SRam Amrani } 2858abd49676SRam Amrani 2859abd49676SRam Amrani /* remove LL2 MAC address filter */ 2860abd49676SRam Amrani rc = qed_roce_ll2_set_mac_filter(cdev, roce_ll2->mac_address, NULL); 2861abd49676SRam Amrani eth_zero_addr(roce_ll2->mac_address); 2862abd49676SRam Amrani 2863abd49676SRam Amrani rc = qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev), 2864abd49676SRam Amrani roce_ll2->handle); 2865abd49676SRam Amrani if (rc) 2866abd49676SRam Amrani DP_ERR(cdev, 2867abd49676SRam Amrani "qed roce ll2 stop: failed to terminate LL2 connection (rc=%d)\n", 2868abd49676SRam Amrani rc); 2869abd49676SRam Amrani 2870abd49676SRam Amrani qed_ll2_release_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle); 2871abd49676SRam Amrani 2872abd49676SRam Amrani roce_ll2->handle = QED_LL2_UNUSED_HANDLE; 2873abd49676SRam Amrani 2874abd49676SRam Amrani kfree(roce_ll2); 2875abd49676SRam Amrani 2876abd49676SRam Amrani return rc; 2877abd49676SRam Amrani } 2878abd49676SRam Amrani 2879abd49676SRam Amrani static int qed_roce_ll2_tx(struct qed_dev *cdev, 2880abd49676SRam Amrani struct qed_roce_ll2_packet *pkt, 2881abd49676SRam Amrani struct qed_roce_ll2_tx_params *params) 2882abd49676SRam Amrani { 2883abd49676SRam Amrani struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2884abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2; 2885abd49676SRam Amrani enum qed_ll2_roce_flavor_type qed_roce_flavor; 2886abd49676SRam Amrani u8 flags = 0; 2887abd49676SRam Amrani int rc; 2888abd49676SRam Amrani int i; 2889abd49676SRam Amrani 2890ce6b04eeSYuval Mintz if (!pkt || !params) { 2891abd49676SRam Amrani DP_ERR(cdev, 2892abd49676SRam Amrani "roce ll2 tx: failed tx because one of the following is NULL - drv=%p, pkt=%p, params=%p\n", 2893abd49676SRam Amrani cdev, pkt, params); 2894abd49676SRam Amrani return -EINVAL; 2895abd49676SRam Amrani } 2896abd49676SRam Amrani 2897abd49676SRam Amrani qed_roce_flavor = (pkt->roce_mode == ROCE_V1) ? QED_LL2_ROCE 2898abd49676SRam Amrani : QED_LL2_RROCE; 2899abd49676SRam Amrani 2900abd49676SRam Amrani if (pkt->roce_mode == ROCE_V2_IPV4) 2901be086e7cSMintz, Yuval flags |= BIT(CORE_TX_BD_DATA_IP_CSUM_SHIFT); 2902abd49676SRam Amrani 2903abd49676SRam Amrani /* Tx header */ 2904abd49676SRam Amrani rc = qed_ll2_prepare_tx_packet(QED_LEADING_HWFN(cdev), roce_ll2->handle, 2905abd49676SRam Amrani 1 + pkt->n_seg, 0, flags, 0, 29061d6cff4fSYuval Mintz QED_LL2_TX_DEST_NW, 2907abd49676SRam Amrani qed_roce_flavor, pkt->header.baddr, 2908abd49676SRam Amrani pkt->header.len, pkt, 1); 2909abd49676SRam Amrani if (rc) { 2910abd49676SRam Amrani DP_ERR(cdev, "roce ll2 tx: header failed (rc=%d)\n", rc); 2911abd49676SRam Amrani return QED_ROCE_TX_HEAD_FAILURE; 2912abd49676SRam Amrani } 2913abd49676SRam Amrani 2914abd49676SRam Amrani /* Tx payload */ 2915abd49676SRam Amrani for (i = 0; i < pkt->n_seg; i++) { 2916abd49676SRam Amrani rc = qed_ll2_set_fragment_of_tx_packet(QED_LEADING_HWFN(cdev), 2917abd49676SRam Amrani roce_ll2->handle, 2918abd49676SRam Amrani pkt->payload[i].baddr, 2919abd49676SRam Amrani pkt->payload[i].len); 2920abd49676SRam Amrani if (rc) { 2921abd49676SRam Amrani /* If failed not much to do here, partial packet has 2922abd49676SRam Amrani * been posted * we can't free memory, will need to wait 2923abd49676SRam Amrani * for completion 2924abd49676SRam Amrani */ 2925abd49676SRam Amrani DP_ERR(cdev, 2926abd49676SRam Amrani "roce ll2 tx: payload failed (rc=%d)\n", rc); 2927abd49676SRam Amrani return QED_ROCE_TX_FRAG_FAILURE; 2928abd49676SRam Amrani } 2929abd49676SRam Amrani } 2930abd49676SRam Amrani 2931abd49676SRam Amrani return 0; 2932abd49676SRam Amrani } 2933abd49676SRam Amrani 2934abd49676SRam Amrani static int qed_roce_ll2_post_rx_buffer(struct qed_dev *cdev, 2935abd49676SRam Amrani struct qed_roce_ll2_buffer *buf, 2936abd49676SRam Amrani u64 cookie, u8 notify_fw) 2937abd49676SRam Amrani { 2938abd49676SRam Amrani return qed_ll2_post_rx_buffer(QED_LEADING_HWFN(cdev), 2939abd49676SRam Amrani QED_LEADING_HWFN(cdev)->ll2->handle, 2940abd49676SRam Amrani buf->baddr, buf->len, 2941abd49676SRam Amrani (void *)(uintptr_t)cookie, notify_fw); 2942abd49676SRam Amrani } 2943abd49676SRam Amrani 2944abd49676SRam Amrani static int qed_roce_ll2_stats(struct qed_dev *cdev, struct qed_ll2_stats *stats) 2945abd49676SRam Amrani { 2946abd49676SRam Amrani struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2947abd49676SRam Amrani struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2; 2948abd49676SRam Amrani 2949abd49676SRam Amrani return qed_ll2_get_stats(QED_LEADING_HWFN(cdev), 2950abd49676SRam Amrani roce_ll2->handle, stats); 2951abd49676SRam Amrani } 2952abd49676SRam Amrani 295351ff1725SRam Amrani static const struct qed_rdma_ops qed_rdma_ops_pass = { 295451ff1725SRam Amrani .common = &qed_common_ops_pass, 295551ff1725SRam Amrani .fill_dev_info = &qed_fill_rdma_dev_info, 295651ff1725SRam Amrani .rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx, 295751ff1725SRam Amrani .rdma_init = &qed_rdma_init, 295851ff1725SRam Amrani .rdma_add_user = &qed_rdma_add_user, 295951ff1725SRam Amrani .rdma_remove_user = &qed_rdma_remove_user, 296051ff1725SRam Amrani .rdma_stop = &qed_rdma_stop, 2961c295f86eSRam Amrani .rdma_query_port = &qed_rdma_query_port, 296251ff1725SRam Amrani .rdma_query_device = &qed_rdma_query_device, 296351ff1725SRam Amrani .rdma_get_start_sb = &qed_rdma_get_sb_start, 296451ff1725SRam Amrani .rdma_get_rdma_int = &qed_rdma_get_int, 296551ff1725SRam Amrani .rdma_set_rdma_int = &qed_rdma_set_int, 296651ff1725SRam Amrani .rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix, 296751ff1725SRam Amrani .rdma_cnq_prod_update = &qed_rdma_cnq_prod_update, 2968c295f86eSRam Amrani .rdma_alloc_pd = &qed_rdma_alloc_pd, 2969c295f86eSRam Amrani .rdma_dealloc_pd = &qed_rdma_free_pd, 2970c295f86eSRam Amrani .rdma_create_cq = &qed_rdma_create_cq, 2971c295f86eSRam Amrani .rdma_destroy_cq = &qed_rdma_destroy_cq, 2972f1093940SRam Amrani .rdma_create_qp = &qed_rdma_create_qp, 2973f1093940SRam Amrani .rdma_modify_qp = &qed_rdma_modify_qp, 2974f1093940SRam Amrani .rdma_query_qp = &qed_rdma_query_qp, 2975f1093940SRam Amrani .rdma_destroy_qp = &qed_rdma_destroy_qp, 2976ee8eaea3SRam Amrani .rdma_alloc_tid = &qed_rdma_alloc_tid, 2977ee8eaea3SRam Amrani .rdma_free_tid = &qed_rdma_free_tid, 2978ee8eaea3SRam Amrani .rdma_register_tid = &qed_rdma_register_tid, 2979ee8eaea3SRam Amrani .rdma_deregister_tid = &qed_rdma_deregister_tid, 2980abd49676SRam Amrani .roce_ll2_start = &qed_roce_ll2_start, 2981abd49676SRam Amrani .roce_ll2_stop = &qed_roce_ll2_stop, 2982abd49676SRam Amrani .roce_ll2_tx = &qed_roce_ll2_tx, 2983abd49676SRam Amrani .roce_ll2_post_rx_buffer = &qed_roce_ll2_post_rx_buffer, 2984abd49676SRam Amrani .roce_ll2_set_mac_filter = &qed_roce_ll2_set_mac_filter, 2985abd49676SRam Amrani .roce_ll2_stats = &qed_roce_ll2_stats, 298651ff1725SRam Amrani }; 298751ff1725SRam Amrani 2988d4e99131SArnd Bergmann const struct qed_rdma_ops *qed_get_rdma_ops(void) 298951ff1725SRam Amrani { 299051ff1725SRam Amrani return &qed_rdma_ops_pass; 299151ff1725SRam Amrani } 299251ff1725SRam Amrani EXPORT_SYMBOL(qed_get_rdma_ops); 2993