151ff1725SRam Amrani /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 351ff1725SRam Amrani * 451ff1725SRam Amrani * This software is available to you under a choice of one of two 551ff1725SRam Amrani * licenses. You may choose to be licensed under the terms of the GNU 651ff1725SRam Amrani * General Public License (GPL) Version 2, available from the file 751ff1725SRam Amrani * COPYING in the main directory of this source tree, or the 851ff1725SRam Amrani * OpenIB.org BSD license below: 951ff1725SRam Amrani * 1051ff1725SRam Amrani * Redistribution and use in source and binary forms, with or 1151ff1725SRam Amrani * without modification, are permitted provided that the following 1251ff1725SRam Amrani * conditions are met: 1351ff1725SRam Amrani * 1451ff1725SRam Amrani * - Redistributions of source code must retain the above 1551ff1725SRam Amrani * copyright notice, this list of conditions and the following 1651ff1725SRam Amrani * disclaimer. 1751ff1725SRam Amrani * 1851ff1725SRam Amrani * - Redistributions in binary form must reproduce the above 1951ff1725SRam Amrani * copyright notice, this list of conditions and the following 2051ff1725SRam Amrani * disclaimer in the documentation and /or other materials 2151ff1725SRam Amrani * provided with the distribution. 2251ff1725SRam Amrani * 2351ff1725SRam Amrani * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 2451ff1725SRam Amrani * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 2551ff1725SRam Amrani * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 2651ff1725SRam Amrani * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 2751ff1725SRam Amrani * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 2851ff1725SRam Amrani * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 2951ff1725SRam Amrani * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 3051ff1725SRam Amrani * SOFTWARE. 3151ff1725SRam Amrani */ 3251ff1725SRam Amrani #include <linux/types.h> 3351ff1725SRam Amrani #include <asm/byteorder.h> 3451ff1725SRam Amrani #include <linux/bitops.h> 3551ff1725SRam Amrani #include <linux/delay.h> 3651ff1725SRam Amrani #include <linux/dma-mapping.h> 3751ff1725SRam Amrani #include <linux/errno.h> 3851ff1725SRam Amrani #include <linux/io.h> 3951ff1725SRam Amrani #include <linux/kernel.h> 4051ff1725SRam Amrani #include <linux/list.h> 4151ff1725SRam Amrani #include <linux/module.h> 4251ff1725SRam Amrani #include <linux/mutex.h> 4351ff1725SRam Amrani #include <linux/pci.h> 4451ff1725SRam Amrani #include <linux/slab.h> 4551ff1725SRam Amrani #include <linux/spinlock.h> 4651ff1725SRam Amrani #include <linux/string.h> 4751ff1725SRam Amrani #include "qed.h" 4851ff1725SRam Amrani #include "qed_cxt.h" 4951ff1725SRam Amrani #include "qed_hsi.h" 5051ff1725SRam Amrani #include "qed_hw.h" 5151ff1725SRam Amrani #include "qed_init_ops.h" 5251ff1725SRam Amrani #include "qed_int.h" 5351ff1725SRam Amrani #include "qed_ll2.h" 5451ff1725SRam Amrani #include "qed_mcp.h" 5551ff1725SRam Amrani #include "qed_reg_addr.h" 567003cdd6SKalderon, Michal #include <linux/qed/qed_rdma_if.h> 57b71b9afdSKalderon, Michal #include "qed_rdma.h" 58b71b9afdSKalderon, Michal #include "qed_roce.h" 598e8dddbaSKalderon, Michal #include "qed_sp.h" 6051ff1725SRam Amrani 61be086e7cSMintz, Yuval static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid); 6251ff1725SRam Amrani 636c9e80eaSMichal Kalderon static int 646c9e80eaSMichal Kalderon qed_roce_async_event(struct qed_hwfn *p_hwfn, 656c9e80eaSMichal Kalderon u8 fw_event_code, 666c9e80eaSMichal Kalderon u16 echo, union event_ring_data *data, u8 fw_return_code) 67be086e7cSMintz, Yuval { 68be086e7cSMintz, Yuval if (fw_event_code == ROCE_ASYNC_EVENT_DESTROY_QP_DONE) { 69be086e7cSMintz, Yuval u16 icid = 706c9e80eaSMichal Kalderon (u16)le32_to_cpu(data->rdma_data.rdma_destroy_qp_data.cid); 71be086e7cSMintz, Yuval 72be086e7cSMintz, Yuval /* icid release in this async event can occur only if the icid 73be086e7cSMintz, Yuval * was offloaded to the FW. In case it wasn't offloaded this is 74be086e7cSMintz, Yuval * handled in qed_roce_sp_destroy_qp. 75be086e7cSMintz, Yuval */ 76be086e7cSMintz, Yuval qed_roce_free_real_icid(p_hwfn, icid); 77be086e7cSMintz, Yuval } else { 78be086e7cSMintz, Yuval struct qed_rdma_events *events = &p_hwfn->p_rdma_info->events; 79be086e7cSMintz, Yuval 80be086e7cSMintz, Yuval events->affiliated_event(p_hwfn->p_rdma_info->events.context, 81be086e7cSMintz, Yuval fw_event_code, 826c9e80eaSMichal Kalderon (void *)&data->rdma_data.async_handle); 83be086e7cSMintz, Yuval } 846c9e80eaSMichal Kalderon 856c9e80eaSMichal Kalderon return 0; 8651ff1725SRam Amrani } 8751ff1725SRam Amrani 88898fff12SMichal Kalderon void qed_roce_stop(struct qed_hwfn *p_hwfn) 89898fff12SMichal Kalderon { 90898fff12SMichal Kalderon struct qed_bmap *rcid_map = &p_hwfn->p_rdma_info->real_cid_map; 91898fff12SMichal Kalderon int wait_count = 0; 92898fff12SMichal Kalderon 93898fff12SMichal Kalderon /* when destroying a_RoCE QP the control is returned to the user after 94898fff12SMichal Kalderon * the synchronous part. The asynchronous part may take a little longer. 95898fff12SMichal Kalderon * We delay for a short while if an async destroy QP is still expected. 96898fff12SMichal Kalderon * Beyond the added delay we clear the bitmap anyway. 97898fff12SMichal Kalderon */ 98898fff12SMichal Kalderon while (bitmap_weight(rcid_map->bitmap, rcid_map->max_count)) { 99898fff12SMichal Kalderon msleep(100); 100898fff12SMichal Kalderon if (wait_count++ > 20) { 101898fff12SMichal Kalderon DP_NOTICE(p_hwfn, "cid bitmap wait timed out\n"); 102898fff12SMichal Kalderon break; 103898fff12SMichal Kalderon } 104898fff12SMichal Kalderon } 1056c9e80eaSMichal Kalderon qed_spq_unregister_async_cb(p_hwfn, PROTOCOLID_ROCE); 106898fff12SMichal Kalderon } 107898fff12SMichal Kalderon 108f1093940SRam Amrani static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid, 109f1093940SRam Amrani __le32 *dst_gid) 110f1093940SRam Amrani { 111f1093940SRam Amrani u32 i; 112f1093940SRam Amrani 113f1093940SRam Amrani if (qp->roce_mode == ROCE_V2_IPV4) { 114f1093940SRam Amrani /* The IPv4 addresses shall be aligned to the highest word. 115f1093940SRam Amrani * The lower words must be zero. 116f1093940SRam Amrani */ 117f1093940SRam Amrani memset(src_gid, 0, sizeof(union qed_gid)); 118f1093940SRam Amrani memset(dst_gid, 0, sizeof(union qed_gid)); 119f1093940SRam Amrani src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr); 120f1093940SRam Amrani dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr); 121f1093940SRam Amrani } else { 122f1093940SRam Amrani /* GIDs and IPv6 addresses coincide in location and size */ 123f1093940SRam Amrani for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) { 124f1093940SRam Amrani src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]); 125f1093940SRam Amrani dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]); 126f1093940SRam Amrani } 127f1093940SRam Amrani } 128f1093940SRam Amrani } 129f1093940SRam Amrani 130f1093940SRam Amrani static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode) 131f1093940SRam Amrani { 132f1093940SRam Amrani enum roce_flavor flavor; 133f1093940SRam Amrani 134f1093940SRam Amrani switch (roce_mode) { 135f1093940SRam Amrani case ROCE_V1: 136f1093940SRam Amrani flavor = PLAIN_ROCE; 137f1093940SRam Amrani break; 138f1093940SRam Amrani case ROCE_V2_IPV4: 139f1093940SRam Amrani flavor = RROCE_IPV4; 140f1093940SRam Amrani break; 141f1093940SRam Amrani case ROCE_V2_IPV6: 142f1093940SRam Amrani flavor = ROCE_V2_IPV6; 143f1093940SRam Amrani break; 144f1093940SRam Amrani default: 145f1093940SRam Amrani flavor = MAX_ROCE_MODE; 146f1093940SRam Amrani break; 147f1093940SRam Amrani } 148f1093940SRam Amrani return flavor; 149f1093940SRam Amrani } 150f1093940SRam Amrani 151be086e7cSMintz, Yuval void qed_roce_free_cid_pair(struct qed_hwfn *p_hwfn, u16 cid) 152be086e7cSMintz, Yuval { 153be086e7cSMintz, Yuval spin_lock_bh(&p_hwfn->p_rdma_info->lock); 154be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid); 155be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid + 1); 156be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 157be086e7cSMintz, Yuval } 158be086e7cSMintz, Yuval 159b71b9afdSKalderon, Michal int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid) 160f1093940SRam Amrani { 161f1093940SRam Amrani struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 162f1093940SRam Amrani u32 responder_icid; 163f1093940SRam Amrani u32 requester_icid; 164f1093940SRam Amrani int rc; 165f1093940SRam Amrani 166f1093940SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 167f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 168f1093940SRam Amrani &responder_icid); 169f1093940SRam Amrani if (rc) { 170f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 171f1093940SRam Amrani return rc; 172f1093940SRam Amrani } 173f1093940SRam Amrani 174f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 175f1093940SRam Amrani &requester_icid); 176f1093940SRam Amrani 177f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 178f1093940SRam Amrani if (rc) 179f1093940SRam Amrani goto err; 180f1093940SRam Amrani 181f1093940SRam Amrani /* the two icid's should be adjacent */ 182f1093940SRam Amrani if ((requester_icid - responder_icid) != 1) { 183f1093940SRam Amrani DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n"); 184f1093940SRam Amrani rc = -EINVAL; 185f1093940SRam Amrani goto err; 186f1093940SRam Amrani } 187f1093940SRam Amrani 188f1093940SRam Amrani responder_icid += qed_cxt_get_proto_cid_start(p_hwfn, 189f1093940SRam Amrani p_rdma_info->proto); 190f1093940SRam Amrani requester_icid += qed_cxt_get_proto_cid_start(p_hwfn, 191f1093940SRam Amrani p_rdma_info->proto); 192f1093940SRam Amrani 193f1093940SRam Amrani /* If these icids require a new ILT line allocate DMA-able context for 194f1093940SRam Amrani * an ILT page 195f1093940SRam Amrani */ 196f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid); 197f1093940SRam Amrani if (rc) 198f1093940SRam Amrani goto err; 199f1093940SRam Amrani 200f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid); 201f1093940SRam Amrani if (rc) 202f1093940SRam Amrani goto err; 203f1093940SRam Amrani 204f1093940SRam Amrani *cid = (u16)responder_icid; 205f1093940SRam Amrani return rc; 206f1093940SRam Amrani 207f1093940SRam Amrani err: 208f1093940SRam Amrani spin_lock_bh(&p_rdma_info->lock); 209f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid); 210f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid); 211f1093940SRam Amrani 212f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 213f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 214f1093940SRam Amrani "Allocate CID - failed, rc = %d\n", rc); 215f1093940SRam Amrani return rc; 216f1093940SRam Amrani } 217f1093940SRam Amrani 218be086e7cSMintz, Yuval static void qed_roce_set_real_cid(struct qed_hwfn *p_hwfn, u32 cid) 219be086e7cSMintz, Yuval { 220be086e7cSMintz, Yuval spin_lock_bh(&p_hwfn->p_rdma_info->lock); 221be086e7cSMintz, Yuval qed_bmap_set_id(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, cid); 222be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 223be086e7cSMintz, Yuval } 224be086e7cSMintz, Yuval 225f1093940SRam Amrani static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn, 226f1093940SRam Amrani struct qed_rdma_qp *qp) 227f1093940SRam Amrani { 228f1093940SRam Amrani struct roce_create_qp_resp_ramrod_data *p_ramrod; 229f1093940SRam Amrani struct qed_sp_init_data init_data; 230f1093940SRam Amrani enum roce_flavor roce_flavor; 231f1093940SRam Amrani struct qed_spq_entry *p_ent; 232be086e7cSMintz, Yuval u16 regular_latency_queue; 233be086e7cSMintz, Yuval enum protocol_type proto; 234f1093940SRam Amrani int rc; 235f1093940SRam Amrani 236f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 237f1093940SRam Amrani 238f1093940SRam Amrani /* Allocate DMA-able memory for IRQ */ 239f1093940SRam Amrani qp->irq_num_pages = 1; 240f1093940SRam Amrani qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 241f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 242f1093940SRam Amrani &qp->irq_phys_addr, GFP_KERNEL); 243f1093940SRam Amrani if (!qp->irq) { 244f1093940SRam Amrani rc = -ENOMEM; 245f1093940SRam Amrani DP_NOTICE(p_hwfn, 246f1093940SRam Amrani "qed create responder failed: cannot allocate memory (irq). rc = %d\n", 247f1093940SRam Amrani rc); 248f1093940SRam Amrani return rc; 249f1093940SRam Amrani } 250f1093940SRam Amrani 251f1093940SRam Amrani /* Get SPQ entry */ 252f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 253f1093940SRam Amrani init_data.cid = qp->icid; 254f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 255f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 256f1093940SRam Amrani 257f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP, 258f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 259f1093940SRam Amrani if (rc) 260f1093940SRam Amrani goto err; 261f1093940SRam Amrani 262f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_resp; 263f1093940SRam Amrani 264f1093940SRam Amrani p_ramrod->flags = 0; 265f1093940SRam Amrani 266f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 267f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 268f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 269f1093940SRam Amrani 270f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 271f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 272f1093940SRam Amrani qp->incoming_rdma_read_en); 273f1093940SRam Amrani 274f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 275f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 276f1093940SRam Amrani qp->incoming_rdma_write_en); 277f1093940SRam Amrani 278f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 279f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN, 280f1093940SRam Amrani qp->incoming_atomic_en); 281f1093940SRam Amrani 282f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 283f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 284f1093940SRam Amrani qp->e2e_flow_control_en); 285f1093940SRam Amrani 286f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 287f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq); 288f1093940SRam Amrani 289f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 290f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN, 291f1093940SRam Amrani qp->fmr_and_reserved_lkey); 292f1093940SRam Amrani 293f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 294f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 295f1093940SRam Amrani qp->min_rnr_nak_timer); 296f1093940SRam Amrani 297f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 298f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 299f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 300f1093940SRam Amrani p_ramrod->irq_num_pages = qp->irq_num_pages; 301f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 302f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 303f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 304f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 305f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn); 306f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 307f1093940SRam Amrani p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages); 308f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr); 309f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr); 310f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 311f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 312f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 313f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 314f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 315f1093940SRam Amrani p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 316f1093940SRam Amrani qp->rq_cq_id); 317f1093940SRam Amrani 318b5a9ee7cSAriel Elior regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 319f1093940SRam Amrani 320be086e7cSMintz, Yuval p_ramrod->regular_latency_phy_queue = 321be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 322be086e7cSMintz, Yuval p_ramrod->low_latency_phy_queue = 323be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 324be086e7cSMintz, Yuval 325f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 326f1093940SRam Amrani 327f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 328f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 329f1093940SRam Amrani 330f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 331f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 332f1093940SRam Amrani p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id); 333f1093940SRam Amrani p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid); 334f1093940SRam Amrani 335f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 336f1093940SRam Amrani qp->stats_queue; 337f1093940SRam Amrani 338f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 339f1093940SRam Amrani 340be086e7cSMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 341be086e7cSMintz, Yuval "rc = %d regular physical queue = 0x%x\n", rc, 342be086e7cSMintz, Yuval regular_latency_queue); 343f1093940SRam Amrani 344f1093940SRam Amrani if (rc) 345f1093940SRam Amrani goto err; 346f1093940SRam Amrani 347f1093940SRam Amrani qp->resp_offloaded = true; 348be086e7cSMintz, Yuval qp->cq_prod = 0; 349be086e7cSMintz, Yuval 350be086e7cSMintz, Yuval proto = p_hwfn->p_rdma_info->proto; 351be086e7cSMintz, Yuval qed_roce_set_real_cid(p_hwfn, qp->icid - 352be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, proto)); 353f1093940SRam Amrani 354f1093940SRam Amrani return rc; 355f1093940SRam Amrani 356f1093940SRam Amrani err: 357f1093940SRam Amrani DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc); 358f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 359f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 360f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 361f1093940SRam Amrani 362f1093940SRam Amrani return rc; 363f1093940SRam Amrani } 364f1093940SRam Amrani 365f1093940SRam Amrani static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn, 366f1093940SRam Amrani struct qed_rdma_qp *qp) 367f1093940SRam Amrani { 368f1093940SRam Amrani struct roce_create_qp_req_ramrod_data *p_ramrod; 369f1093940SRam Amrani struct qed_sp_init_data init_data; 370f1093940SRam Amrani enum roce_flavor roce_flavor; 371f1093940SRam Amrani struct qed_spq_entry *p_ent; 372be086e7cSMintz, Yuval u16 regular_latency_queue; 373be086e7cSMintz, Yuval enum protocol_type proto; 374f1093940SRam Amrani int rc; 375f1093940SRam Amrani 376f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 377f1093940SRam Amrani 378f1093940SRam Amrani /* Allocate DMA-able memory for ORQ */ 379f1093940SRam Amrani qp->orq_num_pages = 1; 380f1093940SRam Amrani qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 381f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 382f1093940SRam Amrani &qp->orq_phys_addr, GFP_KERNEL); 383f1093940SRam Amrani if (!qp->orq) { 384f1093940SRam Amrani rc = -ENOMEM; 385f1093940SRam Amrani DP_NOTICE(p_hwfn, 386f1093940SRam Amrani "qed create requester failed: cannot allocate memory (orq). rc = %d\n", 387f1093940SRam Amrani rc); 388f1093940SRam Amrani return rc; 389f1093940SRam Amrani } 390f1093940SRam Amrani 391f1093940SRam Amrani /* Get SPQ entry */ 392f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 393f1093940SRam Amrani init_data.cid = qp->icid + 1; 394f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 395f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 396f1093940SRam Amrani 397f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 398f1093940SRam Amrani ROCE_RAMROD_CREATE_QP, 399f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 400f1093940SRam Amrani if (rc) 401f1093940SRam Amrani goto err; 402f1093940SRam Amrani 403f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_req; 404f1093940SRam Amrani 405f1093940SRam Amrani p_ramrod->flags = 0; 406f1093940SRam Amrani 407f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 408f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 409f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 410f1093940SRam Amrani 411f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 412f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN, 413f1093940SRam Amrani qp->fmr_and_reserved_lkey); 414f1093940SRam Amrani 415f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 416f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all); 417f1093940SRam Amrani 418f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 419f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 420f1093940SRam Amrani 421f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 422f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 423f1093940SRam Amrani qp->rnr_retry_cnt); 424f1093940SRam Amrani 425f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 426f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 427f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 428f1093940SRam Amrani p_ramrod->orq_num_pages = qp->orq_num_pages; 429f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 430f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 431f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 432f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 433f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 434f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn); 435f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 436f1093940SRam Amrani p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages); 437f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr); 438f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr); 439f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 440f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 441f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 442f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 443f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 444be086e7cSMintz, Yuval p_ramrod->cq_cid = 445be086e7cSMintz, Yuval cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | qp->sq_cq_id); 446f1093940SRam Amrani 447b5a9ee7cSAriel Elior regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 448f1093940SRam Amrani 449be086e7cSMintz, Yuval p_ramrod->regular_latency_phy_queue = 450be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 451be086e7cSMintz, Yuval p_ramrod->low_latency_phy_queue = 452be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 453be086e7cSMintz, Yuval 454f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 455f1093940SRam Amrani 456f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 457f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 458f1093940SRam Amrani 459f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 460f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 461f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 462f1093940SRam Amrani qp->stats_queue; 463f1093940SRam Amrani 464f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 465f1093940SRam Amrani 466f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 467f1093940SRam Amrani 468f1093940SRam Amrani if (rc) 469f1093940SRam Amrani goto err; 470f1093940SRam Amrani 471f1093940SRam Amrani qp->req_offloaded = true; 472be086e7cSMintz, Yuval proto = p_hwfn->p_rdma_info->proto; 473be086e7cSMintz, Yuval qed_roce_set_real_cid(p_hwfn, 474be086e7cSMintz, Yuval qp->icid + 1 - 475be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, proto)); 476f1093940SRam Amrani 477f1093940SRam Amrani return rc; 478f1093940SRam Amrani 479f1093940SRam Amrani err: 480f1093940SRam Amrani DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc); 481f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 482f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 483f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 484f1093940SRam Amrani return rc; 485f1093940SRam Amrani } 486f1093940SRam Amrani 487f1093940SRam Amrani static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn, 488f1093940SRam Amrani struct qed_rdma_qp *qp, 489f1093940SRam Amrani bool move_to_err, u32 modify_flags) 490f1093940SRam Amrani { 491f1093940SRam Amrani struct roce_modify_qp_resp_ramrod_data *p_ramrod; 492f1093940SRam Amrani struct qed_sp_init_data init_data; 493f1093940SRam Amrani struct qed_spq_entry *p_ent; 494f1093940SRam Amrani int rc; 495f1093940SRam Amrani 496f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 497f1093940SRam Amrani 498f1093940SRam Amrani if (move_to_err && !qp->resp_offloaded) 499f1093940SRam Amrani return 0; 500f1093940SRam Amrani 501f1093940SRam Amrani /* Get SPQ entry */ 502f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 503f1093940SRam Amrani init_data.cid = qp->icid; 504f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 505f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 506f1093940SRam Amrani 507f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 508f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 509f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 510f1093940SRam Amrani if (rc) { 511f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 512f1093940SRam Amrani return rc; 513f1093940SRam Amrani } 514f1093940SRam Amrani 515f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_resp; 516f1093940SRam Amrani 517f1093940SRam Amrani p_ramrod->flags = 0; 518f1093940SRam Amrani 519f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 520f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 521f1093940SRam Amrani 522f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 523f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 524f1093940SRam Amrani qp->incoming_rdma_read_en); 525f1093940SRam Amrani 526f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 527f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 528f1093940SRam Amrani qp->incoming_rdma_write_en); 529f1093940SRam Amrani 530f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 531f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN, 532f1093940SRam Amrani qp->incoming_atomic_en); 533f1093940SRam Amrani 534f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 535f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 536f1093940SRam Amrani qp->e2e_flow_control_en); 537f1093940SRam Amrani 538f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 539f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG, 540f1093940SRam Amrani GET_FIELD(modify_flags, 541f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)); 542f1093940SRam Amrani 543f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 544f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG, 545f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 546f1093940SRam Amrani 547f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 548f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG, 549f1093940SRam Amrani GET_FIELD(modify_flags, 550f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 551f1093940SRam Amrani 552f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 553f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG, 554f1093940SRam Amrani GET_FIELD(modify_flags, 555f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)); 556f1093940SRam Amrani 557f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 558f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG, 559f1093940SRam Amrani GET_FIELD(modify_flags, 560f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)); 561f1093940SRam Amrani 562f1093940SRam Amrani p_ramrod->fields = 0; 563f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 564f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 565f1093940SRam Amrani qp->min_rnr_nak_timer); 566f1093940SRam Amrani 567f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 568f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 569f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 570f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 571f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 572f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 573f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 574f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 575f1093940SRam Amrani 576f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc); 577f1093940SRam Amrani return rc; 578f1093940SRam Amrani } 579f1093940SRam Amrani 580f1093940SRam Amrani static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn, 581f1093940SRam Amrani struct qed_rdma_qp *qp, 582f1093940SRam Amrani bool move_to_sqd, 583f1093940SRam Amrani bool move_to_err, u32 modify_flags) 584f1093940SRam Amrani { 585f1093940SRam Amrani struct roce_modify_qp_req_ramrod_data *p_ramrod; 586f1093940SRam Amrani struct qed_sp_init_data init_data; 587f1093940SRam Amrani struct qed_spq_entry *p_ent; 588f1093940SRam Amrani int rc; 589f1093940SRam Amrani 590f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 591f1093940SRam Amrani 592f1093940SRam Amrani if (move_to_err && !(qp->req_offloaded)) 593f1093940SRam Amrani return 0; 594f1093940SRam Amrani 595f1093940SRam Amrani /* Get SPQ entry */ 596f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 597f1093940SRam Amrani init_data.cid = qp->icid + 1; 598f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 599f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 600f1093940SRam Amrani 601f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 602f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 603f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 604f1093940SRam Amrani if (rc) { 605f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 606f1093940SRam Amrani return rc; 607f1093940SRam Amrani } 608f1093940SRam Amrani 609f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_req; 610f1093940SRam Amrani 611f1093940SRam Amrani p_ramrod->flags = 0; 612f1093940SRam Amrani 613f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 614f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 615f1093940SRam Amrani 616f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 617f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd); 618f1093940SRam Amrani 619f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 620f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY, 621f1093940SRam Amrani qp->sqd_async); 622f1093940SRam Amrani 623f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 624f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG, 625f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 626f1093940SRam Amrani 627f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 628f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG, 629f1093940SRam Amrani GET_FIELD(modify_flags, 630f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 631f1093940SRam Amrani 632f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 633f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG, 634f1093940SRam Amrani GET_FIELD(modify_flags, 635f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)); 636f1093940SRam Amrani 637f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 638f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG, 639f1093940SRam Amrani GET_FIELD(modify_flags, 640f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)); 641f1093940SRam Amrani 642f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 643f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG, 644f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)); 645f1093940SRam Amrani 646f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 647f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG, 648f1093940SRam Amrani GET_FIELD(modify_flags, 649f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)); 650f1093940SRam Amrani 651f1093940SRam Amrani p_ramrod->fields = 0; 652f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 653f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 654f1093940SRam Amrani 655f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 656f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 657f1093940SRam Amrani qp->rnr_retry_cnt); 658f1093940SRam Amrani 659f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 660f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 661f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 662f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 663f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 664f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 665f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 666f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 667f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 668f1093940SRam Amrani 669f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc); 670f1093940SRam Amrani return rc; 671f1093940SRam Amrani } 672f1093940SRam Amrani 673f1093940SRam Amrani static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn, 674f1093940SRam Amrani struct qed_rdma_qp *qp, 675be086e7cSMintz, Yuval u32 *num_invalidated_mw, 676be086e7cSMintz, Yuval u32 *cq_prod) 677f1093940SRam Amrani { 678f1093940SRam Amrani struct roce_destroy_qp_resp_output_params *p_ramrod_res; 679f1093940SRam Amrani struct roce_destroy_qp_resp_ramrod_data *p_ramrod; 680f1093940SRam Amrani struct qed_sp_init_data init_data; 681f1093940SRam Amrani struct qed_spq_entry *p_ent; 682f1093940SRam Amrani dma_addr_t ramrod_res_phys; 683f1093940SRam Amrani int rc; 684f1093940SRam Amrani 685f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 686f1093940SRam Amrani 687be086e7cSMintz, Yuval *num_invalidated_mw = 0; 688be086e7cSMintz, Yuval *cq_prod = qp->cq_prod; 689be086e7cSMintz, Yuval 690be086e7cSMintz, Yuval if (!qp->resp_offloaded) { 691be086e7cSMintz, Yuval /* If a responder was never offload, we need to free the cids 692be086e7cSMintz, Yuval * allocated in create_qp as a FW async event will never arrive 693be086e7cSMintz, Yuval */ 694be086e7cSMintz, Yuval u32 cid; 695be086e7cSMintz, Yuval 696be086e7cSMintz, Yuval cid = qp->icid - 697be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, 698be086e7cSMintz, Yuval p_hwfn->p_rdma_info->proto); 699be086e7cSMintz, Yuval qed_roce_free_cid_pair(p_hwfn, (u16)cid); 700be086e7cSMintz, Yuval 701f1093940SRam Amrani return 0; 702be086e7cSMintz, Yuval } 703f1093940SRam Amrani 704f1093940SRam Amrani /* Get SPQ entry */ 705f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 706f1093940SRam Amrani init_data.cid = qp->icid; 707f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 708f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 709f1093940SRam Amrani 710f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 711f1093940SRam Amrani ROCE_RAMROD_DESTROY_QP, 712f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 713f1093940SRam Amrani if (rc) 714f1093940SRam Amrani return rc; 715f1093940SRam Amrani 716f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp; 717f1093940SRam Amrani 718f1093940SRam Amrani p_ramrod_res = (struct roce_destroy_qp_resp_output_params *) 719f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 720f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 721f1093940SRam Amrani 722f1093940SRam Amrani if (!p_ramrod_res) { 723f1093940SRam Amrani rc = -ENOMEM; 724f1093940SRam Amrani DP_NOTICE(p_hwfn, 725f1093940SRam Amrani "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n", 726f1093940SRam Amrani rc); 727f1093940SRam Amrani return rc; 728f1093940SRam Amrani } 729f1093940SRam Amrani 730f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 731f1093940SRam Amrani 732f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 733f1093940SRam Amrani if (rc) 734f1093940SRam Amrani goto err; 735f1093940SRam Amrani 736f1093940SRam Amrani *num_invalidated_mw = le32_to_cpu(p_ramrod_res->num_invalidated_mw); 737be086e7cSMintz, Yuval *cq_prod = le32_to_cpu(p_ramrod_res->cq_prod); 738be086e7cSMintz, Yuval qp->cq_prod = *cq_prod; 739f1093940SRam Amrani 740f1093940SRam Amrani /* Free IRQ - only if ramrod succeeded, in case FW is still using it */ 741f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 742f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 743f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 744f1093940SRam Amrani 745f1093940SRam Amrani qp->resp_offloaded = false; 746f1093940SRam Amrani 747f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc); 748f1093940SRam Amrani 749f1093940SRam Amrani err: 750f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 751f1093940SRam Amrani sizeof(struct roce_destroy_qp_resp_output_params), 752f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 753f1093940SRam Amrani 754f1093940SRam Amrani return rc; 755f1093940SRam Amrani } 756f1093940SRam Amrani 757f1093940SRam Amrani static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn, 758f1093940SRam Amrani struct qed_rdma_qp *qp, 759f1093940SRam Amrani u32 *num_bound_mw) 760f1093940SRam Amrani { 761f1093940SRam Amrani struct roce_destroy_qp_req_output_params *p_ramrod_res; 762f1093940SRam Amrani struct roce_destroy_qp_req_ramrod_data *p_ramrod; 763f1093940SRam Amrani struct qed_sp_init_data init_data; 764f1093940SRam Amrani struct qed_spq_entry *p_ent; 765f1093940SRam Amrani dma_addr_t ramrod_res_phys; 766f1093940SRam Amrani int rc = -ENOMEM; 767f1093940SRam Amrani 768f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 769f1093940SRam Amrani 770f1093940SRam Amrani if (!qp->req_offloaded) 771f1093940SRam Amrani return 0; 772f1093940SRam Amrani 773f1093940SRam Amrani p_ramrod_res = (struct roce_destroy_qp_req_output_params *) 774f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 775f1093940SRam Amrani sizeof(*p_ramrod_res), 776f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 777f1093940SRam Amrani if (!p_ramrod_res) { 778f1093940SRam Amrani DP_NOTICE(p_hwfn, 779f1093940SRam Amrani "qed destroy requester failed: cannot allocate memory (ramrod)\n"); 780f1093940SRam Amrani return rc; 781f1093940SRam Amrani } 782f1093940SRam Amrani 783f1093940SRam Amrani /* Get SPQ entry */ 784f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 785f1093940SRam Amrani init_data.cid = qp->icid + 1; 786f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 787f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 788f1093940SRam Amrani 789f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP, 790f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 791f1093940SRam Amrani if (rc) 792f1093940SRam Amrani goto err; 793f1093940SRam Amrani 794f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_req; 795f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 796f1093940SRam Amrani 797f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 798f1093940SRam Amrani if (rc) 799f1093940SRam Amrani goto err; 800f1093940SRam Amrani 801f1093940SRam Amrani *num_bound_mw = le32_to_cpu(p_ramrod_res->num_bound_mw); 802f1093940SRam Amrani 803f1093940SRam Amrani /* Free ORQ - only if ramrod succeeded, in case FW is still using it */ 804f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 805f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 806f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 807f1093940SRam Amrani 808f1093940SRam Amrani qp->req_offloaded = false; 809f1093940SRam Amrani 810f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc); 811f1093940SRam Amrani 812f1093940SRam Amrani err: 813f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 814f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 815f1093940SRam Amrani 816f1093940SRam Amrani return rc; 817f1093940SRam Amrani } 818f1093940SRam Amrani 819b71b9afdSKalderon, Michal int qed_roce_query_qp(struct qed_hwfn *p_hwfn, 820f1093940SRam Amrani struct qed_rdma_qp *qp, 821f1093940SRam Amrani struct qed_rdma_query_qp_out_params *out_params) 822f1093940SRam Amrani { 823f1093940SRam Amrani struct roce_query_qp_resp_output_params *p_resp_ramrod_res; 824f1093940SRam Amrani struct roce_query_qp_req_output_params *p_req_ramrod_res; 825f1093940SRam Amrani struct roce_query_qp_resp_ramrod_data *p_resp_ramrod; 826f1093940SRam Amrani struct roce_query_qp_req_ramrod_data *p_req_ramrod; 827f1093940SRam Amrani struct qed_sp_init_data init_data; 828f1093940SRam Amrani dma_addr_t resp_ramrod_res_phys; 829f1093940SRam Amrani dma_addr_t req_ramrod_res_phys; 830f1093940SRam Amrani struct qed_spq_entry *p_ent; 831f1093940SRam Amrani bool rq_err_state; 832f1093940SRam Amrani bool sq_err_state; 833f1093940SRam Amrani bool sq_draining; 834f1093940SRam Amrani int rc = -ENOMEM; 835f1093940SRam Amrani 836f1093940SRam Amrani if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) { 837f1093940SRam Amrani /* We can't send ramrod to the fw since this qp wasn't offloaded 838f1093940SRam Amrani * to the fw yet 839f1093940SRam Amrani */ 840f1093940SRam Amrani out_params->draining = false; 841f1093940SRam Amrani out_params->rq_psn = qp->rq_psn; 842f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 843f1093940SRam Amrani out_params->state = qp->cur_state; 844f1093940SRam Amrani 845f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n"); 846f1093940SRam Amrani return 0; 847f1093940SRam Amrani } 848f1093940SRam Amrani 849f1093940SRam Amrani if (!(qp->resp_offloaded)) { 850f1093940SRam Amrani DP_NOTICE(p_hwfn, 851f1093940SRam Amrani "The responder's qp should be offloded before requester's\n"); 852f1093940SRam Amrani return -EINVAL; 853f1093940SRam Amrani } 854f1093940SRam Amrani 855f1093940SRam Amrani /* Send a query responder ramrod to FW to get RQ-PSN and state */ 856f1093940SRam Amrani p_resp_ramrod_res = (struct roce_query_qp_resp_output_params *) 857f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 858f1093940SRam Amrani sizeof(*p_resp_ramrod_res), 859f1093940SRam Amrani &resp_ramrod_res_phys, GFP_KERNEL); 860f1093940SRam Amrani if (!p_resp_ramrod_res) { 861f1093940SRam Amrani DP_NOTICE(p_hwfn, 862f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 863f1093940SRam Amrani return rc; 864f1093940SRam Amrani } 865f1093940SRam Amrani 866f1093940SRam Amrani /* Get SPQ entry */ 867f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 868f1093940SRam Amrani init_data.cid = qp->icid; 869f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 870f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 871f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 872f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 873f1093940SRam Amrani if (rc) 874f1093940SRam Amrani goto err_resp; 875f1093940SRam Amrani 876f1093940SRam Amrani p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp; 877f1093940SRam Amrani DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys); 878f1093940SRam Amrani 879f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 880f1093940SRam Amrani if (rc) 881f1093940SRam Amrani goto err_resp; 882f1093940SRam Amrani 883f1093940SRam Amrani out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn); 884f1093940SRam Amrani rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->err_flag), 885f1093940SRam Amrani ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG); 886f1093940SRam Amrani 887c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 888c5212b94SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 889c5212b94SRam Amrani 890f1093940SRam Amrani if (!(qp->req_offloaded)) { 891f1093940SRam Amrani /* Don't send query qp for the requester */ 892f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 893f1093940SRam Amrani out_params->draining = false; 894f1093940SRam Amrani 895f1093940SRam Amrani if (rq_err_state) 896f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 897f1093940SRam Amrani 898f1093940SRam Amrani out_params->state = qp->cur_state; 899f1093940SRam Amrani 900f1093940SRam Amrani return 0; 901f1093940SRam Amrani } 902f1093940SRam Amrani 903f1093940SRam Amrani /* Send a query requester ramrod to FW to get SQ-PSN and state */ 904f1093940SRam Amrani p_req_ramrod_res = (struct roce_query_qp_req_output_params *) 905f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 906f1093940SRam Amrani sizeof(*p_req_ramrod_res), 907f1093940SRam Amrani &req_ramrod_res_phys, 908f1093940SRam Amrani GFP_KERNEL); 909f1093940SRam Amrani if (!p_req_ramrod_res) { 910f1093940SRam Amrani rc = -ENOMEM; 911f1093940SRam Amrani DP_NOTICE(p_hwfn, 912f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 913f1093940SRam Amrani return rc; 914f1093940SRam Amrani } 915f1093940SRam Amrani 916f1093940SRam Amrani /* Get SPQ entry */ 917f1093940SRam Amrani init_data.cid = qp->icid + 1; 918f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 919f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 920f1093940SRam Amrani if (rc) 921f1093940SRam Amrani goto err_req; 922f1093940SRam Amrani 923f1093940SRam Amrani p_req_ramrod = &p_ent->ramrod.roce_query_qp_req; 924f1093940SRam Amrani DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys); 925f1093940SRam Amrani 926f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 927f1093940SRam Amrani if (rc) 928f1093940SRam Amrani goto err_req; 929f1093940SRam Amrani 930f1093940SRam Amrani out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn); 931f1093940SRam Amrani sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 932f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG); 933f1093940SRam Amrani sq_draining = 934f1093940SRam Amrani GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 935f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG); 936f1093940SRam Amrani 937c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 938c5212b94SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 939c5212b94SRam Amrani 940f1093940SRam Amrani out_params->draining = false; 941f1093940SRam Amrani 942be086e7cSMintz, Yuval if (rq_err_state || sq_err_state) 943f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 944f1093940SRam Amrani else if (sq_draining) 945f1093940SRam Amrani out_params->draining = true; 946f1093940SRam Amrani out_params->state = qp->cur_state; 947f1093940SRam Amrani 948f1093940SRam Amrani return 0; 949f1093940SRam Amrani 950f1093940SRam Amrani err_req: 951f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 952f1093940SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 953f1093940SRam Amrani return rc; 954f1093940SRam Amrani err_resp: 955f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 956f1093940SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 957f1093940SRam Amrani return rc; 958f1093940SRam Amrani } 959f1093940SRam Amrani 960b71b9afdSKalderon, Michal int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 961f1093940SRam Amrani { 962f1093940SRam Amrani u32 num_invalidated_mw = 0; 963f1093940SRam Amrani u32 num_bound_mw = 0; 964be086e7cSMintz, Yuval u32 cq_prod; 965f1093940SRam Amrani int rc; 966f1093940SRam Amrani 967f1093940SRam Amrani /* Destroys the specified QP */ 968f1093940SRam Amrani if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) && 969f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_ERR) && 970f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_INIT)) { 971f1093940SRam Amrani DP_NOTICE(p_hwfn, 972f1093940SRam Amrani "QP must be in error, reset or init state before destroying it\n"); 973f1093940SRam Amrani return -EINVAL; 974f1093940SRam Amrani } 975f1093940SRam Amrani 976300c0d7cSRam Amrani if (qp->cur_state != QED_ROCE_QP_STATE_RESET) { 977300c0d7cSRam Amrani rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, 978be086e7cSMintz, Yuval &num_invalidated_mw, 979be086e7cSMintz, Yuval &cq_prod); 980f1093940SRam Amrani if (rc) 981f1093940SRam Amrani return rc; 982f1093940SRam Amrani 983f1093940SRam Amrani /* Send destroy requester ramrod */ 984300c0d7cSRam Amrani rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, 985300c0d7cSRam Amrani &num_bound_mw); 986f1093940SRam Amrani if (rc) 987f1093940SRam Amrani return rc; 988f1093940SRam Amrani 989f1093940SRam Amrani if (num_invalidated_mw != num_bound_mw) { 990f1093940SRam Amrani DP_NOTICE(p_hwfn, 991f1093940SRam Amrani "number of invalidate memory windows is different from bounded ones\n"); 992f1093940SRam Amrani return -EINVAL; 993f1093940SRam Amrani } 994300c0d7cSRam Amrani } 995f1093940SRam Amrani 996f1093940SRam Amrani return 0; 997f1093940SRam Amrani } 998f1093940SRam Amrani 999b71b9afdSKalderon, Michal int qed_roce_modify_qp(struct qed_hwfn *p_hwfn, 1000f1093940SRam Amrani struct qed_rdma_qp *qp, 1001f1093940SRam Amrani enum qed_roce_qp_state prev_state, 1002f1093940SRam Amrani struct qed_rdma_modify_qp_in_params *params) 1003f1093940SRam Amrani { 1004f1093940SRam Amrani u32 num_invalidated_mw = 0, num_bound_mw = 0; 1005f1093940SRam Amrani int rc = 0; 1006f1093940SRam Amrani 1007f1093940SRam Amrani /* Perform additional operations according to the current state and the 1008f1093940SRam Amrani * next state 1009f1093940SRam Amrani */ 1010f1093940SRam Amrani if (((prev_state == QED_ROCE_QP_STATE_INIT) || 1011f1093940SRam Amrani (prev_state == QED_ROCE_QP_STATE_RESET)) && 1012f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTR)) { 1013f1093940SRam Amrani /* Init->RTR or Reset->RTR */ 1014f1093940SRam Amrani rc = qed_roce_sp_create_responder(p_hwfn, qp); 1015f1093940SRam Amrani return rc; 1016f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTR) && 1017f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1018f1093940SRam Amrani /* RTR-> RTS */ 1019f1093940SRam Amrani rc = qed_roce_sp_create_requester(p_hwfn, qp); 1020f1093940SRam Amrani if (rc) 1021f1093940SRam Amrani return rc; 1022f1093940SRam Amrani 1023f1093940SRam Amrani /* Send modify responder ramrod */ 1024f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1025f1093940SRam Amrani params->modify_flags); 1026f1093940SRam Amrani return rc; 1027f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1028f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1029f1093940SRam Amrani /* RTS->RTS */ 1030f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1031f1093940SRam Amrani params->modify_flags); 1032f1093940SRam Amrani if (rc) 1033f1093940SRam Amrani return rc; 1034f1093940SRam Amrani 1035f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1036f1093940SRam Amrani params->modify_flags); 1037f1093940SRam Amrani return rc; 1038f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1039f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1040f1093940SRam Amrani /* RTS->SQD */ 1041f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false, 1042f1093940SRam Amrani params->modify_flags); 1043f1093940SRam Amrani return rc; 1044f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1045f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1046f1093940SRam Amrani /* SQD->SQD */ 1047f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1048f1093940SRam Amrani params->modify_flags); 1049f1093940SRam Amrani if (rc) 1050f1093940SRam Amrani return rc; 1051f1093940SRam Amrani 1052f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1053f1093940SRam Amrani params->modify_flags); 1054f1093940SRam Amrani return rc; 1055f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1056f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1057f1093940SRam Amrani /* SQD->RTS */ 1058f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1059f1093940SRam Amrani params->modify_flags); 1060f1093940SRam Amrani if (rc) 1061f1093940SRam Amrani return rc; 1062f1093940SRam Amrani 1063f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1064f1093940SRam Amrani params->modify_flags); 1065f1093940SRam Amrani 1066f1093940SRam Amrani return rc; 1067ba0154e9SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR) { 1068f1093940SRam Amrani /* ->ERR */ 1069f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, true, 1070f1093940SRam Amrani params->modify_flags); 1071f1093940SRam Amrani if (rc) 1072f1093940SRam Amrani return rc; 1073f1093940SRam Amrani 1074f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true, 1075f1093940SRam Amrani params->modify_flags); 1076f1093940SRam Amrani return rc; 1077f1093940SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) { 1078f1093940SRam Amrani /* Any state -> RESET */ 1079be086e7cSMintz, Yuval u32 cq_prod; 1080f1093940SRam Amrani 1081be086e7cSMintz, Yuval /* Send destroy responder ramrod */ 1082be086e7cSMintz, Yuval rc = qed_roce_sp_destroy_qp_responder(p_hwfn, 1083be086e7cSMintz, Yuval qp, 1084be086e7cSMintz, Yuval &num_invalidated_mw, 1085be086e7cSMintz, Yuval &cq_prod); 1086be086e7cSMintz, Yuval 1087f1093940SRam Amrani if (rc) 1088f1093940SRam Amrani return rc; 1089f1093940SRam Amrani 1090be086e7cSMintz, Yuval qp->cq_prod = cq_prod; 1091be086e7cSMintz, Yuval 1092f1093940SRam Amrani rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, 1093f1093940SRam Amrani &num_bound_mw); 1094f1093940SRam Amrani 1095f1093940SRam Amrani if (num_invalidated_mw != num_bound_mw) { 1096f1093940SRam Amrani DP_NOTICE(p_hwfn, 1097f1093940SRam Amrani "number of invalidate memory windows is different from bounded ones\n"); 1098f1093940SRam Amrani return -EINVAL; 1099f1093940SRam Amrani } 1100f1093940SRam Amrani } else { 1101f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 1102f1093940SRam Amrani } 1103f1093940SRam Amrani 1104f1093940SRam Amrani return rc; 1105f1093940SRam Amrani } 1106f1093940SRam Amrani 1107be086e7cSMintz, Yuval static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid) 1108be086e7cSMintz, Yuval { 1109be086e7cSMintz, Yuval struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 1110be086e7cSMintz, Yuval u32 start_cid, cid, xcid; 1111be086e7cSMintz, Yuval 1112be086e7cSMintz, Yuval /* an even icid belongs to a responder while an odd icid belongs to a 1113be086e7cSMintz, Yuval * requester. The 'cid' received as an input can be either. We calculate 1114be086e7cSMintz, Yuval * the "partner" icid and call it xcid. Only if both are free then the 1115be086e7cSMintz, Yuval * "cid" map can be cleared. 1116be086e7cSMintz, Yuval */ 1117be086e7cSMintz, Yuval start_cid = qed_cxt_get_proto_cid_start(p_hwfn, p_rdma_info->proto); 1118be086e7cSMintz, Yuval cid = icid - start_cid; 1119be086e7cSMintz, Yuval xcid = cid ^ 1; 1120be086e7cSMintz, Yuval 1121be086e7cSMintz, Yuval spin_lock_bh(&p_rdma_info->lock); 1122be086e7cSMintz, Yuval 1123be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->real_cid_map, cid); 1124be086e7cSMintz, Yuval if (qed_bmap_test_id(p_hwfn, &p_rdma_info->real_cid_map, xcid) == 0) { 1125be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, cid); 1126be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, xcid); 1127be086e7cSMintz, Yuval } 1128be086e7cSMintz, Yuval 1129be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1130be086e7cSMintz, Yuval } 1131be086e7cSMintz, Yuval 11329331dad1SMintz, Yuval void qed_roce_dpm_dcbx(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11339331dad1SMintz, Yuval { 11349331dad1SMintz, Yuval u8 val; 11359331dad1SMintz, Yuval 11369331dad1SMintz, Yuval /* if any QPs are already active, we want to disable DPM, since their 11379331dad1SMintz, Yuval * context information contains information from before the latest DCBx 11389331dad1SMintz, Yuval * update. Otherwise enable it. 11399331dad1SMintz, Yuval */ 11409331dad1SMintz, Yuval val = qed_rdma_allocated_qps(p_hwfn) ? true : false; 11419331dad1SMintz, Yuval p_hwfn->dcbx_no_edpm = (u8)val; 11429331dad1SMintz, Yuval 11439331dad1SMintz, Yuval qed_rdma_dpm_conf(p_hwfn, p_ptt); 11449331dad1SMintz, Yuval } 11459331dad1SMintz, Yuval 1146b71b9afdSKalderon, Michal int qed_roce_setup(struct qed_hwfn *p_hwfn) 114751ff1725SRam Amrani { 1148b71b9afdSKalderon, Michal return qed_spq_register_async_cb(p_hwfn, PROTOCOLID_ROCE, 1149b71b9afdSKalderon, Michal qed_roce_async_event); 115051ff1725SRam Amrani } 115151ff1725SRam Amrani 1152