151ff1725SRam Amrani /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 351ff1725SRam Amrani * 451ff1725SRam Amrani * This software is available to you under a choice of one of two 551ff1725SRam Amrani * licenses. You may choose to be licensed under the terms of the GNU 651ff1725SRam Amrani * General Public License (GPL) Version 2, available from the file 751ff1725SRam Amrani * COPYING in the main directory of this source tree, or the 851ff1725SRam Amrani * OpenIB.org BSD license below: 951ff1725SRam Amrani * 1051ff1725SRam Amrani * Redistribution and use in source and binary forms, with or 1151ff1725SRam Amrani * without modification, are permitted provided that the following 1251ff1725SRam Amrani * conditions are met: 1351ff1725SRam Amrani * 1451ff1725SRam Amrani * - Redistributions of source code must retain the above 1551ff1725SRam Amrani * copyright notice, this list of conditions and the following 1651ff1725SRam Amrani * disclaimer. 1751ff1725SRam Amrani * 1851ff1725SRam Amrani * - Redistributions in binary form must reproduce the above 1951ff1725SRam Amrani * copyright notice, this list of conditions and the following 2051ff1725SRam Amrani * disclaimer in the documentation and /or other materials 2151ff1725SRam Amrani * provided with the distribution. 2251ff1725SRam Amrani * 2351ff1725SRam Amrani * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 2451ff1725SRam Amrani * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 2551ff1725SRam Amrani * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 2651ff1725SRam Amrani * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 2751ff1725SRam Amrani * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 2851ff1725SRam Amrani * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 2951ff1725SRam Amrani * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 3051ff1725SRam Amrani * SOFTWARE. 3151ff1725SRam Amrani */ 3251ff1725SRam Amrani #include <linux/types.h> 3351ff1725SRam Amrani #include <asm/byteorder.h> 3451ff1725SRam Amrani #include <linux/bitops.h> 3551ff1725SRam Amrani #include <linux/delay.h> 3651ff1725SRam Amrani #include <linux/dma-mapping.h> 3751ff1725SRam Amrani #include <linux/errno.h> 3851ff1725SRam Amrani #include <linux/io.h> 3951ff1725SRam Amrani #include <linux/kernel.h> 4051ff1725SRam Amrani #include <linux/list.h> 4151ff1725SRam Amrani #include <linux/module.h> 4251ff1725SRam Amrani #include <linux/mutex.h> 4351ff1725SRam Amrani #include <linux/pci.h> 4451ff1725SRam Amrani #include <linux/slab.h> 4551ff1725SRam Amrani #include <linux/spinlock.h> 4651ff1725SRam Amrani #include <linux/string.h> 4751ff1725SRam Amrani #include "qed.h" 4851ff1725SRam Amrani #include "qed_cxt.h" 4951ff1725SRam Amrani #include "qed_hsi.h" 5051ff1725SRam Amrani #include "qed_hw.h" 5151ff1725SRam Amrani #include "qed_init_ops.h" 5251ff1725SRam Amrani #include "qed_int.h" 5351ff1725SRam Amrani #include "qed_ll2.h" 5451ff1725SRam Amrani #include "qed_mcp.h" 5551ff1725SRam Amrani #include "qed_reg_addr.h" 567003cdd6SKalderon, Michal #include <linux/qed/qed_rdma_if.h> 57b71b9afdSKalderon, Michal #include "qed_rdma.h" 58b71b9afdSKalderon, Michal #include "qed_roce.h" 598e8dddbaSKalderon, Michal #include "qed_sp.h" 6051ff1725SRam Amrani 61be086e7cSMintz, Yuval static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid); 6251ff1725SRam Amrani 636c9e80eaSMichal Kalderon static int 646c9e80eaSMichal Kalderon qed_roce_async_event(struct qed_hwfn *p_hwfn, 656c9e80eaSMichal Kalderon u8 fw_event_code, 666c9e80eaSMichal Kalderon u16 echo, union event_ring_data *data, u8 fw_return_code) 67be086e7cSMintz, Yuval { 6839dbc646SYuval Bason struct qed_rdma_events events = p_hwfn->p_rdma_info->events; 6939dbc646SYuval Bason 70be086e7cSMintz, Yuval if (fw_event_code == ROCE_ASYNC_EVENT_DESTROY_QP_DONE) { 71be086e7cSMintz, Yuval u16 icid = 726c9e80eaSMichal Kalderon (u16)le32_to_cpu(data->rdma_data.rdma_destroy_qp_data.cid); 73be086e7cSMintz, Yuval 74be086e7cSMintz, Yuval /* icid release in this async event can occur only if the icid 75be086e7cSMintz, Yuval * was offloaded to the FW. In case it wasn't offloaded this is 76be086e7cSMintz, Yuval * handled in qed_roce_sp_destroy_qp. 77be086e7cSMintz, Yuval */ 78be086e7cSMintz, Yuval qed_roce_free_real_icid(p_hwfn, icid); 79be086e7cSMintz, Yuval } else { 8039dbc646SYuval Bason if (fw_event_code == ROCE_ASYNC_EVENT_SRQ_EMPTY || 8139dbc646SYuval Bason fw_event_code == ROCE_ASYNC_EVENT_SRQ_LIMIT) { 8239dbc646SYuval Bason u16 srq_id = (u16)data->rdma_data.async_handle.lo; 83be086e7cSMintz, Yuval 8439dbc646SYuval Bason events.affiliated_event(events.context, fw_event_code, 8539dbc646SYuval Bason &srq_id); 8639dbc646SYuval Bason } else { 8739dbc646SYuval Bason union rdma_eqe_data rdata = data->rdma_data; 8839dbc646SYuval Bason 8939dbc646SYuval Bason events.affiliated_event(events.context, fw_event_code, 9039dbc646SYuval Bason (void *)&rdata.async_handle); 9139dbc646SYuval Bason } 92be086e7cSMintz, Yuval } 936c9e80eaSMichal Kalderon 946c9e80eaSMichal Kalderon return 0; 9551ff1725SRam Amrani } 9651ff1725SRam Amrani 97898fff12SMichal Kalderon void qed_roce_stop(struct qed_hwfn *p_hwfn) 98898fff12SMichal Kalderon { 99898fff12SMichal Kalderon struct qed_bmap *rcid_map = &p_hwfn->p_rdma_info->real_cid_map; 100898fff12SMichal Kalderon int wait_count = 0; 101898fff12SMichal Kalderon 102898fff12SMichal Kalderon /* when destroying a_RoCE QP the control is returned to the user after 103898fff12SMichal Kalderon * the synchronous part. The asynchronous part may take a little longer. 104898fff12SMichal Kalderon * We delay for a short while if an async destroy QP is still expected. 105898fff12SMichal Kalderon * Beyond the added delay we clear the bitmap anyway. 106898fff12SMichal Kalderon */ 107898fff12SMichal Kalderon while (bitmap_weight(rcid_map->bitmap, rcid_map->max_count)) { 108898fff12SMichal Kalderon msleep(100); 109898fff12SMichal Kalderon if (wait_count++ > 20) { 110898fff12SMichal Kalderon DP_NOTICE(p_hwfn, "cid bitmap wait timed out\n"); 111898fff12SMichal Kalderon break; 112898fff12SMichal Kalderon } 113898fff12SMichal Kalderon } 1146c9e80eaSMichal Kalderon qed_spq_unregister_async_cb(p_hwfn, PROTOCOLID_ROCE); 115898fff12SMichal Kalderon } 116898fff12SMichal Kalderon 117f1093940SRam Amrani static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid, 118f1093940SRam Amrani __le32 *dst_gid) 119f1093940SRam Amrani { 120f1093940SRam Amrani u32 i; 121f1093940SRam Amrani 122f1093940SRam Amrani if (qp->roce_mode == ROCE_V2_IPV4) { 123f1093940SRam Amrani /* The IPv4 addresses shall be aligned to the highest word. 124f1093940SRam Amrani * The lower words must be zero. 125f1093940SRam Amrani */ 126f1093940SRam Amrani memset(src_gid, 0, sizeof(union qed_gid)); 127f1093940SRam Amrani memset(dst_gid, 0, sizeof(union qed_gid)); 128f1093940SRam Amrani src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr); 129f1093940SRam Amrani dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr); 130f1093940SRam Amrani } else { 131f1093940SRam Amrani /* GIDs and IPv6 addresses coincide in location and size */ 132f1093940SRam Amrani for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) { 133f1093940SRam Amrani src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]); 134f1093940SRam Amrani dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]); 135f1093940SRam Amrani } 136f1093940SRam Amrani } 137f1093940SRam Amrani } 138f1093940SRam Amrani 139f1093940SRam Amrani static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode) 140f1093940SRam Amrani { 141f1093940SRam Amrani enum roce_flavor flavor; 142f1093940SRam Amrani 143f1093940SRam Amrani switch (roce_mode) { 144f1093940SRam Amrani case ROCE_V1: 145f1093940SRam Amrani flavor = PLAIN_ROCE; 146f1093940SRam Amrani break; 147f1093940SRam Amrani case ROCE_V2_IPV4: 148f1093940SRam Amrani flavor = RROCE_IPV4; 149f1093940SRam Amrani break; 150f1093940SRam Amrani case ROCE_V2_IPV6: 151f1093940SRam Amrani flavor = ROCE_V2_IPV6; 152f1093940SRam Amrani break; 153f1093940SRam Amrani default: 154f1093940SRam Amrani flavor = MAX_ROCE_MODE; 155f1093940SRam Amrani break; 156f1093940SRam Amrani } 157f1093940SRam Amrani return flavor; 158f1093940SRam Amrani } 159f1093940SRam Amrani 160be086e7cSMintz, Yuval void qed_roce_free_cid_pair(struct qed_hwfn *p_hwfn, u16 cid) 161be086e7cSMintz, Yuval { 162be086e7cSMintz, Yuval spin_lock_bh(&p_hwfn->p_rdma_info->lock); 163be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid); 164be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid + 1); 165be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 166be086e7cSMintz, Yuval } 167be086e7cSMintz, Yuval 168b71b9afdSKalderon, Michal int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid) 169f1093940SRam Amrani { 170f1093940SRam Amrani struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 171f1093940SRam Amrani u32 responder_icid; 172f1093940SRam Amrani u32 requester_icid; 173f1093940SRam Amrani int rc; 174f1093940SRam Amrani 175f1093940SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 176f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 177f1093940SRam Amrani &responder_icid); 178f1093940SRam Amrani if (rc) { 179f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 180f1093940SRam Amrani return rc; 181f1093940SRam Amrani } 182f1093940SRam Amrani 183f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 184f1093940SRam Amrani &requester_icid); 185f1093940SRam Amrani 186f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 187f1093940SRam Amrani if (rc) 188f1093940SRam Amrani goto err; 189f1093940SRam Amrani 190f1093940SRam Amrani /* the two icid's should be adjacent */ 191f1093940SRam Amrani if ((requester_icid - responder_icid) != 1) { 192f1093940SRam Amrani DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n"); 193f1093940SRam Amrani rc = -EINVAL; 194f1093940SRam Amrani goto err; 195f1093940SRam Amrani } 196f1093940SRam Amrani 197f1093940SRam Amrani responder_icid += qed_cxt_get_proto_cid_start(p_hwfn, 198f1093940SRam Amrani p_rdma_info->proto); 199f1093940SRam Amrani requester_icid += qed_cxt_get_proto_cid_start(p_hwfn, 200f1093940SRam Amrani p_rdma_info->proto); 201f1093940SRam Amrani 202f1093940SRam Amrani /* If these icids require a new ILT line allocate DMA-able context for 203f1093940SRam Amrani * an ILT page 204f1093940SRam Amrani */ 205f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid); 206f1093940SRam Amrani if (rc) 207f1093940SRam Amrani goto err; 208f1093940SRam Amrani 209f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid); 210f1093940SRam Amrani if (rc) 211f1093940SRam Amrani goto err; 212f1093940SRam Amrani 213f1093940SRam Amrani *cid = (u16)responder_icid; 214f1093940SRam Amrani return rc; 215f1093940SRam Amrani 216f1093940SRam Amrani err: 217f1093940SRam Amrani spin_lock_bh(&p_rdma_info->lock); 218f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid); 219f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid); 220f1093940SRam Amrani 221f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 222f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 223f1093940SRam Amrani "Allocate CID - failed, rc = %d\n", rc); 224f1093940SRam Amrani return rc; 225f1093940SRam Amrani } 226f1093940SRam Amrani 227be086e7cSMintz, Yuval static void qed_roce_set_real_cid(struct qed_hwfn *p_hwfn, u32 cid) 228be086e7cSMintz, Yuval { 229be086e7cSMintz, Yuval spin_lock_bh(&p_hwfn->p_rdma_info->lock); 230be086e7cSMintz, Yuval qed_bmap_set_id(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, cid); 231be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 232be086e7cSMintz, Yuval } 233be086e7cSMintz, Yuval 234f1093940SRam Amrani static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn, 235f1093940SRam Amrani struct qed_rdma_qp *qp) 236f1093940SRam Amrani { 237f1093940SRam Amrani struct roce_create_qp_resp_ramrod_data *p_ramrod; 238f1093940SRam Amrani struct qed_sp_init_data init_data; 239f1093940SRam Amrani enum roce_flavor roce_flavor; 240f1093940SRam Amrani struct qed_spq_entry *p_ent; 241be086e7cSMintz, Yuval u16 regular_latency_queue; 242be086e7cSMintz, Yuval enum protocol_type proto; 243f1093940SRam Amrani int rc; 244f1093940SRam Amrani 245f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 246f1093940SRam Amrani 247f1093940SRam Amrani /* Allocate DMA-able memory for IRQ */ 248f1093940SRam Amrani qp->irq_num_pages = 1; 249f1093940SRam Amrani qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 250f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 251f1093940SRam Amrani &qp->irq_phys_addr, GFP_KERNEL); 252f1093940SRam Amrani if (!qp->irq) { 253f1093940SRam Amrani rc = -ENOMEM; 254f1093940SRam Amrani DP_NOTICE(p_hwfn, 255f1093940SRam Amrani "qed create responder failed: cannot allocate memory (irq). rc = %d\n", 256f1093940SRam Amrani rc); 257f1093940SRam Amrani return rc; 258f1093940SRam Amrani } 259f1093940SRam Amrani 260f1093940SRam Amrani /* Get SPQ entry */ 261f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 262f1093940SRam Amrani init_data.cid = qp->icid; 263f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 264f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 265f1093940SRam Amrani 266f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP, 267f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 268f1093940SRam Amrani if (rc) 269f1093940SRam Amrani goto err; 270f1093940SRam Amrani 271f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_resp; 272f1093940SRam Amrani 273f1093940SRam Amrani p_ramrod->flags = 0; 274f1093940SRam Amrani 275f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 276f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 277f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 278f1093940SRam Amrani 279f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 280f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 281f1093940SRam Amrani qp->incoming_rdma_read_en); 282f1093940SRam Amrani 283f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 284f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 285f1093940SRam Amrani qp->incoming_rdma_write_en); 286f1093940SRam Amrani 287f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 288f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN, 289f1093940SRam Amrani qp->incoming_atomic_en); 290f1093940SRam Amrani 291f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 292f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 293f1093940SRam Amrani qp->e2e_flow_control_en); 294f1093940SRam Amrani 295f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 296f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq); 297f1093940SRam Amrani 298f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 299f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN, 300f1093940SRam Amrani qp->fmr_and_reserved_lkey); 301f1093940SRam Amrani 302f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 303f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 304f1093940SRam Amrani qp->min_rnr_nak_timer); 305f1093940SRam Amrani 306f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 307f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 308f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 309f1093940SRam Amrani p_ramrod->irq_num_pages = qp->irq_num_pages; 310f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 311f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 312f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 313f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 314f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn); 315f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 316f1093940SRam Amrani p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages); 317f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr); 318f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr); 319f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 320f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 321f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 322f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 323f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 324f1093940SRam Amrani p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 325f1093940SRam Amrani qp->rq_cq_id); 326f1093940SRam Amrani 327b5a9ee7cSAriel Elior regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 328f1093940SRam Amrani 329be086e7cSMintz, Yuval p_ramrod->regular_latency_phy_queue = 330be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 331be086e7cSMintz, Yuval p_ramrod->low_latency_phy_queue = 332be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 333be086e7cSMintz, Yuval 334f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 335f1093940SRam Amrani 336f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 337f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 338f1093940SRam Amrani 339f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 340f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 341f1093940SRam Amrani p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id); 342f1093940SRam Amrani p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid); 343f1093940SRam Amrani 344f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 345f1093940SRam Amrani qp->stats_queue; 346f1093940SRam Amrani 347f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 348f1093940SRam Amrani 349be086e7cSMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 350be086e7cSMintz, Yuval "rc = %d regular physical queue = 0x%x\n", rc, 351be086e7cSMintz, Yuval regular_latency_queue); 352f1093940SRam Amrani 353f1093940SRam Amrani if (rc) 354f1093940SRam Amrani goto err; 355f1093940SRam Amrani 356f1093940SRam Amrani qp->resp_offloaded = true; 357be086e7cSMintz, Yuval qp->cq_prod = 0; 358be086e7cSMintz, Yuval 359be086e7cSMintz, Yuval proto = p_hwfn->p_rdma_info->proto; 360be086e7cSMintz, Yuval qed_roce_set_real_cid(p_hwfn, qp->icid - 361be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, proto)); 362f1093940SRam Amrani 363f1093940SRam Amrani return rc; 364f1093940SRam Amrani 365f1093940SRam Amrani err: 366f1093940SRam Amrani DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc); 367f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 368f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 369f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 370f1093940SRam Amrani 371f1093940SRam Amrani return rc; 372f1093940SRam Amrani } 373f1093940SRam Amrani 374f1093940SRam Amrani static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn, 375f1093940SRam Amrani struct qed_rdma_qp *qp) 376f1093940SRam Amrani { 377f1093940SRam Amrani struct roce_create_qp_req_ramrod_data *p_ramrod; 378f1093940SRam Amrani struct qed_sp_init_data init_data; 379f1093940SRam Amrani enum roce_flavor roce_flavor; 380f1093940SRam Amrani struct qed_spq_entry *p_ent; 381be086e7cSMintz, Yuval u16 regular_latency_queue; 382be086e7cSMintz, Yuval enum protocol_type proto; 383f1093940SRam Amrani int rc; 384f1093940SRam Amrani 385f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 386f1093940SRam Amrani 387f1093940SRam Amrani /* Allocate DMA-able memory for ORQ */ 388f1093940SRam Amrani qp->orq_num_pages = 1; 389f1093940SRam Amrani qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 390f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 391f1093940SRam Amrani &qp->orq_phys_addr, GFP_KERNEL); 392f1093940SRam Amrani if (!qp->orq) { 393f1093940SRam Amrani rc = -ENOMEM; 394f1093940SRam Amrani DP_NOTICE(p_hwfn, 395f1093940SRam Amrani "qed create requester failed: cannot allocate memory (orq). rc = %d\n", 396f1093940SRam Amrani rc); 397f1093940SRam Amrani return rc; 398f1093940SRam Amrani } 399f1093940SRam Amrani 400f1093940SRam Amrani /* Get SPQ entry */ 401f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 402f1093940SRam Amrani init_data.cid = qp->icid + 1; 403f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 404f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 405f1093940SRam Amrani 406f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 407f1093940SRam Amrani ROCE_RAMROD_CREATE_QP, 408f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 409f1093940SRam Amrani if (rc) 410f1093940SRam Amrani goto err; 411f1093940SRam Amrani 412f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_req; 413f1093940SRam Amrani 414f1093940SRam Amrani p_ramrod->flags = 0; 415f1093940SRam Amrani 416f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 417f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 418f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 419f1093940SRam Amrani 420f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 421f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN, 422f1093940SRam Amrani qp->fmr_and_reserved_lkey); 423f1093940SRam Amrani 424f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 425f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all); 426f1093940SRam Amrani 427f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 428f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 429f1093940SRam Amrani 430f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 431f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 432f1093940SRam Amrani qp->rnr_retry_cnt); 433f1093940SRam Amrani 434f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 435f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 436f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 437f1093940SRam Amrani p_ramrod->orq_num_pages = qp->orq_num_pages; 438f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 439f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 440f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 441f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 442f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 443f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn); 444f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 445f1093940SRam Amrani p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages); 446f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr); 447f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr); 448f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 449f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 450f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 451f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 452f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 453be086e7cSMintz, Yuval p_ramrod->cq_cid = 454be086e7cSMintz, Yuval cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | qp->sq_cq_id); 455f1093940SRam Amrani 456b5a9ee7cSAriel Elior regular_latency_queue = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 457f1093940SRam Amrani 458be086e7cSMintz, Yuval p_ramrod->regular_latency_phy_queue = 459be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 460be086e7cSMintz, Yuval p_ramrod->low_latency_phy_queue = 461be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 462be086e7cSMintz, Yuval 463f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 464f1093940SRam Amrani 465f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 466f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 467f1093940SRam Amrani 468f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 469f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 470f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 471f1093940SRam Amrani qp->stats_queue; 472f1093940SRam Amrani 473f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 474f1093940SRam Amrani 475f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 476f1093940SRam Amrani 477f1093940SRam Amrani if (rc) 478f1093940SRam Amrani goto err; 479f1093940SRam Amrani 480f1093940SRam Amrani qp->req_offloaded = true; 481be086e7cSMintz, Yuval proto = p_hwfn->p_rdma_info->proto; 482be086e7cSMintz, Yuval qed_roce_set_real_cid(p_hwfn, 483be086e7cSMintz, Yuval qp->icid + 1 - 484be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, proto)); 485f1093940SRam Amrani 486f1093940SRam Amrani return rc; 487f1093940SRam Amrani 488f1093940SRam Amrani err: 489f1093940SRam Amrani DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc); 490f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 491f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 492f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 493f1093940SRam Amrani return rc; 494f1093940SRam Amrani } 495f1093940SRam Amrani 496f1093940SRam Amrani static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn, 497f1093940SRam Amrani struct qed_rdma_qp *qp, 498f1093940SRam Amrani bool move_to_err, u32 modify_flags) 499f1093940SRam Amrani { 500f1093940SRam Amrani struct roce_modify_qp_resp_ramrod_data *p_ramrod; 501f1093940SRam Amrani struct qed_sp_init_data init_data; 502f1093940SRam Amrani struct qed_spq_entry *p_ent; 503f1093940SRam Amrani int rc; 504f1093940SRam Amrani 505f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 506f1093940SRam Amrani 507f1093940SRam Amrani if (move_to_err && !qp->resp_offloaded) 508f1093940SRam Amrani return 0; 509f1093940SRam Amrani 510f1093940SRam Amrani /* Get SPQ entry */ 511f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 512f1093940SRam Amrani init_data.cid = qp->icid; 513f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 514f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 515f1093940SRam Amrani 516f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 517f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 518f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 519f1093940SRam Amrani if (rc) { 520f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 521f1093940SRam Amrani return rc; 522f1093940SRam Amrani } 523f1093940SRam Amrani 524f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_resp; 525f1093940SRam Amrani 526f1093940SRam Amrani p_ramrod->flags = 0; 527f1093940SRam Amrani 528f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 529f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 530f1093940SRam Amrani 531f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 532f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 533f1093940SRam Amrani qp->incoming_rdma_read_en); 534f1093940SRam Amrani 535f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 536f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 537f1093940SRam Amrani qp->incoming_rdma_write_en); 538f1093940SRam Amrani 539f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 540f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN, 541f1093940SRam Amrani qp->incoming_atomic_en); 542f1093940SRam Amrani 543f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 544f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 545f1093940SRam Amrani qp->e2e_flow_control_en); 546f1093940SRam Amrani 547f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 548f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG, 549f1093940SRam Amrani GET_FIELD(modify_flags, 550f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)); 551f1093940SRam Amrani 552f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 553f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG, 554f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 555f1093940SRam Amrani 556f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 557f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG, 558f1093940SRam Amrani GET_FIELD(modify_flags, 559f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 560f1093940SRam Amrani 561f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 562f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG, 563f1093940SRam Amrani GET_FIELD(modify_flags, 564f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)); 565f1093940SRam Amrani 566f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 567f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG, 568f1093940SRam Amrani GET_FIELD(modify_flags, 569f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)); 570f1093940SRam Amrani 571f1093940SRam Amrani p_ramrod->fields = 0; 572f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 573f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 574f1093940SRam Amrani qp->min_rnr_nak_timer); 575f1093940SRam Amrani 576f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 577f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 578f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 579f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 580f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 581f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 582f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 583f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 584f1093940SRam Amrani 585f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc); 586f1093940SRam Amrani return rc; 587f1093940SRam Amrani } 588f1093940SRam Amrani 589f1093940SRam Amrani static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn, 590f1093940SRam Amrani struct qed_rdma_qp *qp, 591f1093940SRam Amrani bool move_to_sqd, 592f1093940SRam Amrani bool move_to_err, u32 modify_flags) 593f1093940SRam Amrani { 594f1093940SRam Amrani struct roce_modify_qp_req_ramrod_data *p_ramrod; 595f1093940SRam Amrani struct qed_sp_init_data init_data; 596f1093940SRam Amrani struct qed_spq_entry *p_ent; 597f1093940SRam Amrani int rc; 598f1093940SRam Amrani 599f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 600f1093940SRam Amrani 601f1093940SRam Amrani if (move_to_err && !(qp->req_offloaded)) 602f1093940SRam Amrani return 0; 603f1093940SRam Amrani 604f1093940SRam Amrani /* Get SPQ entry */ 605f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 606f1093940SRam Amrani init_data.cid = qp->icid + 1; 607f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 608f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 609f1093940SRam Amrani 610f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 611f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 612f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 613f1093940SRam Amrani if (rc) { 614f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 615f1093940SRam Amrani return rc; 616f1093940SRam Amrani } 617f1093940SRam Amrani 618f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_req; 619f1093940SRam Amrani 620f1093940SRam Amrani p_ramrod->flags = 0; 621f1093940SRam Amrani 622f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 623f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 624f1093940SRam Amrani 625f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 626f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd); 627f1093940SRam Amrani 628f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 629f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY, 630f1093940SRam Amrani qp->sqd_async); 631f1093940SRam Amrani 632f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 633f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG, 634f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 635f1093940SRam Amrani 636f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 637f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG, 638f1093940SRam Amrani GET_FIELD(modify_flags, 639f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 640f1093940SRam Amrani 641f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 642f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG, 643f1093940SRam Amrani GET_FIELD(modify_flags, 644f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)); 645f1093940SRam Amrani 646f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 647f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG, 648f1093940SRam Amrani GET_FIELD(modify_flags, 649f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)); 650f1093940SRam Amrani 651f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 652f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG, 653f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)); 654f1093940SRam Amrani 655f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 656f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG, 657f1093940SRam Amrani GET_FIELD(modify_flags, 658f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)); 659f1093940SRam Amrani 660f1093940SRam Amrani p_ramrod->fields = 0; 661f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 662f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 663f1093940SRam Amrani 664f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 665f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 666f1093940SRam Amrani qp->rnr_retry_cnt); 667f1093940SRam Amrani 668f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 669f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 670f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 671f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 672f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 673f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 674f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 675f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 676f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 677f1093940SRam Amrani 678f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc); 679f1093940SRam Amrani return rc; 680f1093940SRam Amrani } 681f1093940SRam Amrani 682f1093940SRam Amrani static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn, 683f1093940SRam Amrani struct qed_rdma_qp *qp, 684be086e7cSMintz, Yuval u32 *num_invalidated_mw, 685be086e7cSMintz, Yuval u32 *cq_prod) 686f1093940SRam Amrani { 687f1093940SRam Amrani struct roce_destroy_qp_resp_output_params *p_ramrod_res; 688f1093940SRam Amrani struct roce_destroy_qp_resp_ramrod_data *p_ramrod; 689f1093940SRam Amrani struct qed_sp_init_data init_data; 690f1093940SRam Amrani struct qed_spq_entry *p_ent; 691f1093940SRam Amrani dma_addr_t ramrod_res_phys; 692f1093940SRam Amrani int rc; 693f1093940SRam Amrani 694f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 695f1093940SRam Amrani 696be086e7cSMintz, Yuval *num_invalidated_mw = 0; 697be086e7cSMintz, Yuval *cq_prod = qp->cq_prod; 698be086e7cSMintz, Yuval 699be086e7cSMintz, Yuval if (!qp->resp_offloaded) { 700be086e7cSMintz, Yuval /* If a responder was never offload, we need to free the cids 701be086e7cSMintz, Yuval * allocated in create_qp as a FW async event will never arrive 702be086e7cSMintz, Yuval */ 703be086e7cSMintz, Yuval u32 cid; 704be086e7cSMintz, Yuval 705be086e7cSMintz, Yuval cid = qp->icid - 706be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, 707be086e7cSMintz, Yuval p_hwfn->p_rdma_info->proto); 708be086e7cSMintz, Yuval qed_roce_free_cid_pair(p_hwfn, (u16)cid); 709be086e7cSMintz, Yuval 710f1093940SRam Amrani return 0; 711be086e7cSMintz, Yuval } 712f1093940SRam Amrani 713f1093940SRam Amrani /* Get SPQ entry */ 714f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 715f1093940SRam Amrani init_data.cid = qp->icid; 716f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 717f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 718f1093940SRam Amrani 719f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 720f1093940SRam Amrani ROCE_RAMROD_DESTROY_QP, 721f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 722f1093940SRam Amrani if (rc) 723f1093940SRam Amrani return rc; 724f1093940SRam Amrani 725f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp; 726f1093940SRam Amrani 727f1093940SRam Amrani p_ramrod_res = (struct roce_destroy_qp_resp_output_params *) 728f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 729f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 730f1093940SRam Amrani 731f1093940SRam Amrani if (!p_ramrod_res) { 732f1093940SRam Amrani rc = -ENOMEM; 733f1093940SRam Amrani DP_NOTICE(p_hwfn, 734f1093940SRam Amrani "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n", 735f1093940SRam Amrani rc); 736f1093940SRam Amrani return rc; 737f1093940SRam Amrani } 738f1093940SRam Amrani 739f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 740f1093940SRam Amrani 741f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 742f1093940SRam Amrani if (rc) 743f1093940SRam Amrani goto err; 744f1093940SRam Amrani 745f1093940SRam Amrani *num_invalidated_mw = le32_to_cpu(p_ramrod_res->num_invalidated_mw); 746be086e7cSMintz, Yuval *cq_prod = le32_to_cpu(p_ramrod_res->cq_prod); 747be086e7cSMintz, Yuval qp->cq_prod = *cq_prod; 748f1093940SRam Amrani 749f1093940SRam Amrani /* Free IRQ - only if ramrod succeeded, in case FW is still using it */ 750f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 751f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 752f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 753f1093940SRam Amrani 754f1093940SRam Amrani qp->resp_offloaded = false; 755f1093940SRam Amrani 756f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc); 757f1093940SRam Amrani 758f1093940SRam Amrani err: 759f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 760f1093940SRam Amrani sizeof(struct roce_destroy_qp_resp_output_params), 761f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 762f1093940SRam Amrani 763f1093940SRam Amrani return rc; 764f1093940SRam Amrani } 765f1093940SRam Amrani 766f1093940SRam Amrani static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn, 767f1093940SRam Amrani struct qed_rdma_qp *qp, 768f1093940SRam Amrani u32 *num_bound_mw) 769f1093940SRam Amrani { 770f1093940SRam Amrani struct roce_destroy_qp_req_output_params *p_ramrod_res; 771f1093940SRam Amrani struct roce_destroy_qp_req_ramrod_data *p_ramrod; 772f1093940SRam Amrani struct qed_sp_init_data init_data; 773f1093940SRam Amrani struct qed_spq_entry *p_ent; 774f1093940SRam Amrani dma_addr_t ramrod_res_phys; 775f1093940SRam Amrani int rc = -ENOMEM; 776f1093940SRam Amrani 777f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 778f1093940SRam Amrani 779f1093940SRam Amrani if (!qp->req_offloaded) 780f1093940SRam Amrani return 0; 781f1093940SRam Amrani 782f1093940SRam Amrani p_ramrod_res = (struct roce_destroy_qp_req_output_params *) 783f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 784f1093940SRam Amrani sizeof(*p_ramrod_res), 785f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 786f1093940SRam Amrani if (!p_ramrod_res) { 787f1093940SRam Amrani DP_NOTICE(p_hwfn, 788f1093940SRam Amrani "qed destroy requester failed: cannot allocate memory (ramrod)\n"); 789f1093940SRam Amrani return rc; 790f1093940SRam Amrani } 791f1093940SRam Amrani 792f1093940SRam Amrani /* Get SPQ entry */ 793f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 794f1093940SRam Amrani init_data.cid = qp->icid + 1; 795f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 796f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 797f1093940SRam Amrani 798f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP, 799f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 800f1093940SRam Amrani if (rc) 801f1093940SRam Amrani goto err; 802f1093940SRam Amrani 803f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_req; 804f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 805f1093940SRam Amrani 806f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 807f1093940SRam Amrani if (rc) 808f1093940SRam Amrani goto err; 809f1093940SRam Amrani 810f1093940SRam Amrani *num_bound_mw = le32_to_cpu(p_ramrod_res->num_bound_mw); 811f1093940SRam Amrani 812f1093940SRam Amrani /* Free ORQ - only if ramrod succeeded, in case FW is still using it */ 813f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 814f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 815f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 816f1093940SRam Amrani 817f1093940SRam Amrani qp->req_offloaded = false; 818f1093940SRam Amrani 819f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc); 820f1093940SRam Amrani 821f1093940SRam Amrani err: 822f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 823f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 824f1093940SRam Amrani 825f1093940SRam Amrani return rc; 826f1093940SRam Amrani } 827f1093940SRam Amrani 828b71b9afdSKalderon, Michal int qed_roce_query_qp(struct qed_hwfn *p_hwfn, 829f1093940SRam Amrani struct qed_rdma_qp *qp, 830f1093940SRam Amrani struct qed_rdma_query_qp_out_params *out_params) 831f1093940SRam Amrani { 832f1093940SRam Amrani struct roce_query_qp_resp_output_params *p_resp_ramrod_res; 833f1093940SRam Amrani struct roce_query_qp_req_output_params *p_req_ramrod_res; 834f1093940SRam Amrani struct roce_query_qp_resp_ramrod_data *p_resp_ramrod; 835f1093940SRam Amrani struct roce_query_qp_req_ramrod_data *p_req_ramrod; 836f1093940SRam Amrani struct qed_sp_init_data init_data; 837f1093940SRam Amrani dma_addr_t resp_ramrod_res_phys; 838f1093940SRam Amrani dma_addr_t req_ramrod_res_phys; 839f1093940SRam Amrani struct qed_spq_entry *p_ent; 840f1093940SRam Amrani bool rq_err_state; 841f1093940SRam Amrani bool sq_err_state; 842f1093940SRam Amrani bool sq_draining; 843f1093940SRam Amrani int rc = -ENOMEM; 844f1093940SRam Amrani 845f1093940SRam Amrani if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) { 846f1093940SRam Amrani /* We can't send ramrod to the fw since this qp wasn't offloaded 847f1093940SRam Amrani * to the fw yet 848f1093940SRam Amrani */ 849f1093940SRam Amrani out_params->draining = false; 850f1093940SRam Amrani out_params->rq_psn = qp->rq_psn; 851f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 852f1093940SRam Amrani out_params->state = qp->cur_state; 853f1093940SRam Amrani 854f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n"); 855f1093940SRam Amrani return 0; 856f1093940SRam Amrani } 857f1093940SRam Amrani 858f1093940SRam Amrani if (!(qp->resp_offloaded)) { 859f1093940SRam Amrani DP_NOTICE(p_hwfn, 860df80b8fbSColin Ian King "The responder's qp should be offloaded before requester's\n"); 861f1093940SRam Amrani return -EINVAL; 862f1093940SRam Amrani } 863f1093940SRam Amrani 864f1093940SRam Amrani /* Send a query responder ramrod to FW to get RQ-PSN and state */ 865f1093940SRam Amrani p_resp_ramrod_res = (struct roce_query_qp_resp_output_params *) 866f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 867f1093940SRam Amrani sizeof(*p_resp_ramrod_res), 868f1093940SRam Amrani &resp_ramrod_res_phys, GFP_KERNEL); 869f1093940SRam Amrani if (!p_resp_ramrod_res) { 870f1093940SRam Amrani DP_NOTICE(p_hwfn, 871f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 872f1093940SRam Amrani return rc; 873f1093940SRam Amrani } 874f1093940SRam Amrani 875f1093940SRam Amrani /* Get SPQ entry */ 876f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 877f1093940SRam Amrani init_data.cid = qp->icid; 878f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 879f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 880f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 881f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 882f1093940SRam Amrani if (rc) 883f1093940SRam Amrani goto err_resp; 884f1093940SRam Amrani 885f1093940SRam Amrani p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp; 886f1093940SRam Amrani DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys); 887f1093940SRam Amrani 888f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 889f1093940SRam Amrani if (rc) 890f1093940SRam Amrani goto err_resp; 891f1093940SRam Amrani 892f1093940SRam Amrani out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn); 893f1093940SRam Amrani rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->err_flag), 894f1093940SRam Amrani ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG); 895f1093940SRam Amrani 896c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 897c5212b94SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 898c5212b94SRam Amrani 899f1093940SRam Amrani if (!(qp->req_offloaded)) { 900f1093940SRam Amrani /* Don't send query qp for the requester */ 901f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 902f1093940SRam Amrani out_params->draining = false; 903f1093940SRam Amrani 904f1093940SRam Amrani if (rq_err_state) 905f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 906f1093940SRam Amrani 907f1093940SRam Amrani out_params->state = qp->cur_state; 908f1093940SRam Amrani 909f1093940SRam Amrani return 0; 910f1093940SRam Amrani } 911f1093940SRam Amrani 912f1093940SRam Amrani /* Send a query requester ramrod to FW to get SQ-PSN and state */ 913f1093940SRam Amrani p_req_ramrod_res = (struct roce_query_qp_req_output_params *) 914f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 915f1093940SRam Amrani sizeof(*p_req_ramrod_res), 916f1093940SRam Amrani &req_ramrod_res_phys, 917f1093940SRam Amrani GFP_KERNEL); 918f1093940SRam Amrani if (!p_req_ramrod_res) { 919f1093940SRam Amrani rc = -ENOMEM; 920f1093940SRam Amrani DP_NOTICE(p_hwfn, 921f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 922f1093940SRam Amrani return rc; 923f1093940SRam Amrani } 924f1093940SRam Amrani 925f1093940SRam Amrani /* Get SPQ entry */ 926f1093940SRam Amrani init_data.cid = qp->icid + 1; 927f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 928f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 929f1093940SRam Amrani if (rc) 930f1093940SRam Amrani goto err_req; 931f1093940SRam Amrani 932f1093940SRam Amrani p_req_ramrod = &p_ent->ramrod.roce_query_qp_req; 933f1093940SRam Amrani DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys); 934f1093940SRam Amrani 935f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 936f1093940SRam Amrani if (rc) 937f1093940SRam Amrani goto err_req; 938f1093940SRam Amrani 939f1093940SRam Amrani out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn); 940f1093940SRam Amrani sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 941f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG); 942f1093940SRam Amrani sq_draining = 943f1093940SRam Amrani GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 944f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG); 945f1093940SRam Amrani 946c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 947c5212b94SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 948c5212b94SRam Amrani 949f1093940SRam Amrani out_params->draining = false; 950f1093940SRam Amrani 951be086e7cSMintz, Yuval if (rq_err_state || sq_err_state) 952f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 953f1093940SRam Amrani else if (sq_draining) 954f1093940SRam Amrani out_params->draining = true; 955f1093940SRam Amrani out_params->state = qp->cur_state; 956f1093940SRam Amrani 957f1093940SRam Amrani return 0; 958f1093940SRam Amrani 959f1093940SRam Amrani err_req: 960f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 961f1093940SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 962f1093940SRam Amrani return rc; 963f1093940SRam Amrani err_resp: 964f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 965f1093940SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 966f1093940SRam Amrani return rc; 967f1093940SRam Amrani } 968f1093940SRam Amrani 969b71b9afdSKalderon, Michal int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 970f1093940SRam Amrani { 971f1093940SRam Amrani u32 num_invalidated_mw = 0; 972f1093940SRam Amrani u32 num_bound_mw = 0; 973be086e7cSMintz, Yuval u32 cq_prod; 974f1093940SRam Amrani int rc; 975f1093940SRam Amrani 976f1093940SRam Amrani /* Destroys the specified QP */ 977f1093940SRam Amrani if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) && 978f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_ERR) && 979f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_INIT)) { 980f1093940SRam Amrani DP_NOTICE(p_hwfn, 981f1093940SRam Amrani "QP must be in error, reset or init state before destroying it\n"); 982f1093940SRam Amrani return -EINVAL; 983f1093940SRam Amrani } 984f1093940SRam Amrani 985300c0d7cSRam Amrani if (qp->cur_state != QED_ROCE_QP_STATE_RESET) { 986300c0d7cSRam Amrani rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, 987be086e7cSMintz, Yuval &num_invalidated_mw, 988be086e7cSMintz, Yuval &cq_prod); 989f1093940SRam Amrani if (rc) 990f1093940SRam Amrani return rc; 991f1093940SRam Amrani 992f1093940SRam Amrani /* Send destroy requester ramrod */ 993300c0d7cSRam Amrani rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, 994300c0d7cSRam Amrani &num_bound_mw); 995f1093940SRam Amrani if (rc) 996f1093940SRam Amrani return rc; 997f1093940SRam Amrani 998f1093940SRam Amrani if (num_invalidated_mw != num_bound_mw) { 999f1093940SRam Amrani DP_NOTICE(p_hwfn, 1000f1093940SRam Amrani "number of invalidate memory windows is different from bounded ones\n"); 1001f1093940SRam Amrani return -EINVAL; 1002f1093940SRam Amrani } 1003300c0d7cSRam Amrani } 1004f1093940SRam Amrani 1005f1093940SRam Amrani return 0; 1006f1093940SRam Amrani } 1007f1093940SRam Amrani 1008b71b9afdSKalderon, Michal int qed_roce_modify_qp(struct qed_hwfn *p_hwfn, 1009f1093940SRam Amrani struct qed_rdma_qp *qp, 1010f1093940SRam Amrani enum qed_roce_qp_state prev_state, 1011f1093940SRam Amrani struct qed_rdma_modify_qp_in_params *params) 1012f1093940SRam Amrani { 1013f1093940SRam Amrani u32 num_invalidated_mw = 0, num_bound_mw = 0; 1014f1093940SRam Amrani int rc = 0; 1015f1093940SRam Amrani 1016f1093940SRam Amrani /* Perform additional operations according to the current state and the 1017f1093940SRam Amrani * next state 1018f1093940SRam Amrani */ 1019f1093940SRam Amrani if (((prev_state == QED_ROCE_QP_STATE_INIT) || 1020f1093940SRam Amrani (prev_state == QED_ROCE_QP_STATE_RESET)) && 1021f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTR)) { 1022f1093940SRam Amrani /* Init->RTR or Reset->RTR */ 1023f1093940SRam Amrani rc = qed_roce_sp_create_responder(p_hwfn, qp); 1024f1093940SRam Amrani return rc; 1025f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTR) && 1026f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1027f1093940SRam Amrani /* RTR-> RTS */ 1028f1093940SRam Amrani rc = qed_roce_sp_create_requester(p_hwfn, qp); 1029f1093940SRam Amrani if (rc) 1030f1093940SRam Amrani return rc; 1031f1093940SRam Amrani 1032f1093940SRam Amrani /* Send modify responder ramrod */ 1033f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1034f1093940SRam Amrani params->modify_flags); 1035f1093940SRam Amrani return rc; 1036f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1037f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1038f1093940SRam Amrani /* RTS->RTS */ 1039f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1040f1093940SRam Amrani params->modify_flags); 1041f1093940SRam Amrani if (rc) 1042f1093940SRam Amrani return rc; 1043f1093940SRam Amrani 1044f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1045f1093940SRam Amrani params->modify_flags); 1046f1093940SRam Amrani return rc; 1047f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1048f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1049f1093940SRam Amrani /* RTS->SQD */ 1050f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false, 1051f1093940SRam Amrani params->modify_flags); 1052f1093940SRam Amrani return rc; 1053f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1054f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1055f1093940SRam Amrani /* SQD->SQD */ 1056f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1057f1093940SRam Amrani params->modify_flags); 1058f1093940SRam Amrani if (rc) 1059f1093940SRam Amrani return rc; 1060f1093940SRam Amrani 1061f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1062f1093940SRam Amrani params->modify_flags); 1063f1093940SRam Amrani return rc; 1064f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1065f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1066f1093940SRam Amrani /* SQD->RTS */ 1067f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1068f1093940SRam Amrani params->modify_flags); 1069f1093940SRam Amrani if (rc) 1070f1093940SRam Amrani return rc; 1071f1093940SRam Amrani 1072f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1073f1093940SRam Amrani params->modify_flags); 1074f1093940SRam Amrani 1075f1093940SRam Amrani return rc; 1076ba0154e9SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR) { 1077f1093940SRam Amrani /* ->ERR */ 1078f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, true, 1079f1093940SRam Amrani params->modify_flags); 1080f1093940SRam Amrani if (rc) 1081f1093940SRam Amrani return rc; 1082f1093940SRam Amrani 1083f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true, 1084f1093940SRam Amrani params->modify_flags); 1085f1093940SRam Amrani return rc; 1086f1093940SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) { 1087f1093940SRam Amrani /* Any state -> RESET */ 1088be086e7cSMintz, Yuval u32 cq_prod; 1089f1093940SRam Amrani 1090be086e7cSMintz, Yuval /* Send destroy responder ramrod */ 1091be086e7cSMintz, Yuval rc = qed_roce_sp_destroy_qp_responder(p_hwfn, 1092be086e7cSMintz, Yuval qp, 1093be086e7cSMintz, Yuval &num_invalidated_mw, 1094be086e7cSMintz, Yuval &cq_prod); 1095be086e7cSMintz, Yuval 1096f1093940SRam Amrani if (rc) 1097f1093940SRam Amrani return rc; 1098f1093940SRam Amrani 1099be086e7cSMintz, Yuval qp->cq_prod = cq_prod; 1100be086e7cSMintz, Yuval 1101f1093940SRam Amrani rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, 1102f1093940SRam Amrani &num_bound_mw); 1103f1093940SRam Amrani 1104f1093940SRam Amrani if (num_invalidated_mw != num_bound_mw) { 1105f1093940SRam Amrani DP_NOTICE(p_hwfn, 1106f1093940SRam Amrani "number of invalidate memory windows is different from bounded ones\n"); 1107f1093940SRam Amrani return -EINVAL; 1108f1093940SRam Amrani } 1109f1093940SRam Amrani } else { 1110f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 1111f1093940SRam Amrani } 1112f1093940SRam Amrani 1113f1093940SRam Amrani return rc; 1114f1093940SRam Amrani } 1115f1093940SRam Amrani 1116be086e7cSMintz, Yuval static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid) 1117be086e7cSMintz, Yuval { 1118be086e7cSMintz, Yuval struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 1119be086e7cSMintz, Yuval u32 start_cid, cid, xcid; 1120be086e7cSMintz, Yuval 1121be086e7cSMintz, Yuval /* an even icid belongs to a responder while an odd icid belongs to a 1122be086e7cSMintz, Yuval * requester. The 'cid' received as an input can be either. We calculate 1123be086e7cSMintz, Yuval * the "partner" icid and call it xcid. Only if both are free then the 1124be086e7cSMintz, Yuval * "cid" map can be cleared. 1125be086e7cSMintz, Yuval */ 1126be086e7cSMintz, Yuval start_cid = qed_cxt_get_proto_cid_start(p_hwfn, p_rdma_info->proto); 1127be086e7cSMintz, Yuval cid = icid - start_cid; 1128be086e7cSMintz, Yuval xcid = cid ^ 1; 1129be086e7cSMintz, Yuval 1130be086e7cSMintz, Yuval spin_lock_bh(&p_rdma_info->lock); 1131be086e7cSMintz, Yuval 1132be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->real_cid_map, cid); 1133be086e7cSMintz, Yuval if (qed_bmap_test_id(p_hwfn, &p_rdma_info->real_cid_map, xcid) == 0) { 1134be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, cid); 1135be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, xcid); 1136be086e7cSMintz, Yuval } 1137be086e7cSMintz, Yuval 1138be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1139be086e7cSMintz, Yuval } 1140be086e7cSMintz, Yuval 11419331dad1SMintz, Yuval void qed_roce_dpm_dcbx(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11429331dad1SMintz, Yuval { 11439331dad1SMintz, Yuval u8 val; 11449331dad1SMintz, Yuval 11459331dad1SMintz, Yuval /* if any QPs are already active, we want to disable DPM, since their 11469331dad1SMintz, Yuval * context information contains information from before the latest DCBx 11479331dad1SMintz, Yuval * update. Otherwise enable it. 11489331dad1SMintz, Yuval */ 11499331dad1SMintz, Yuval val = qed_rdma_allocated_qps(p_hwfn) ? true : false; 11509331dad1SMintz, Yuval p_hwfn->dcbx_no_edpm = (u8)val; 11519331dad1SMintz, Yuval 11529331dad1SMintz, Yuval qed_rdma_dpm_conf(p_hwfn, p_ptt); 11539331dad1SMintz, Yuval } 11549331dad1SMintz, Yuval 1155b71b9afdSKalderon, Michal int qed_roce_setup(struct qed_hwfn *p_hwfn) 115651ff1725SRam Amrani { 1157b71b9afdSKalderon, Michal return qed_spq_register_async_cb(p_hwfn, PROTOCOLID_ROCE, 1158b71b9afdSKalderon, Michal qed_roce_async_event); 115951ff1725SRam Amrani } 116051ff1725SRam Amrani 116167b40dccSKalderon, Michal int qed_roce_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 116267b40dccSKalderon, Michal { 116367b40dccSKalderon, Michal u32 ll2_ethertype_en; 116467b40dccSKalderon, Michal 116567b40dccSKalderon, Michal qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 116667b40dccSKalderon, Michal 116767b40dccSKalderon, Michal p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE; 116867b40dccSKalderon, Michal 116967b40dccSKalderon, Michal ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 117067b40dccSKalderon, Michal qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 117167b40dccSKalderon, Michal (ll2_ethertype_en | 0x01)); 117267b40dccSKalderon, Michal 117367b40dccSKalderon, Michal if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) { 117467b40dccSKalderon, Michal DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n"); 117567b40dccSKalderon, Michal return -EINVAL; 117667b40dccSKalderon, Michal } 117767b40dccSKalderon, Michal 117867b40dccSKalderon, Michal DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n"); 117967b40dccSKalderon, Michal return 0; 118067b40dccSKalderon, Michal } 1181