11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 251ff1725SRam Amrani /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 451ff1725SRam Amrani */ 51f4d4ed6SAlexander Lobakin 651ff1725SRam Amrani #include <linux/types.h> 751ff1725SRam Amrani #include <asm/byteorder.h> 851ff1725SRam Amrani #include <linux/bitops.h> 951ff1725SRam Amrani #include <linux/delay.h> 1051ff1725SRam Amrani #include <linux/dma-mapping.h> 1151ff1725SRam Amrani #include <linux/errno.h> 1251ff1725SRam Amrani #include <linux/io.h> 1351ff1725SRam Amrani #include <linux/kernel.h> 1451ff1725SRam Amrani #include <linux/list.h> 1551ff1725SRam Amrani #include <linux/module.h> 1651ff1725SRam Amrani #include <linux/mutex.h> 1751ff1725SRam Amrani #include <linux/pci.h> 1851ff1725SRam Amrani #include <linux/slab.h> 1951ff1725SRam Amrani #include <linux/spinlock.h> 2051ff1725SRam Amrani #include <linux/string.h> 2161be82b0SDenis Bolotin #include <linux/if_vlan.h> 2251ff1725SRam Amrani #include "qed.h" 2351ff1725SRam Amrani #include "qed_cxt.h" 2461be82b0SDenis Bolotin #include "qed_dcbx.h" 2551ff1725SRam Amrani #include "qed_hsi.h" 2651ff1725SRam Amrani #include "qed_hw.h" 2751ff1725SRam Amrani #include "qed_init_ops.h" 2851ff1725SRam Amrani #include "qed_int.h" 2951ff1725SRam Amrani #include "qed_ll2.h" 3051ff1725SRam Amrani #include "qed_mcp.h" 3151ff1725SRam Amrani #include "qed_reg_addr.h" 327003cdd6SKalderon, Michal #include <linux/qed/qed_rdma_if.h> 33b71b9afdSKalderon, Michal #include "qed_rdma.h" 34b71b9afdSKalderon, Michal #include "qed_roce.h" 358e8dddbaSKalderon, Michal #include "qed_sp.h" 3651ff1725SRam Amrani 37be086e7cSMintz, Yuval static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid); 3851ff1725SRam Amrani 396c9e80eaSMichal Kalderon static int 406c9e80eaSMichal Kalderon qed_roce_async_event(struct qed_hwfn *p_hwfn, 416c9e80eaSMichal Kalderon u8 fw_event_code, 426c9e80eaSMichal Kalderon u16 echo, union event_ring_data *data, u8 fw_return_code) 43be086e7cSMintz, Yuval { 4439dbc646SYuval Bason struct qed_rdma_events events = p_hwfn->p_rdma_info->events; 4539dbc646SYuval Bason 46be086e7cSMintz, Yuval if (fw_event_code == ROCE_ASYNC_EVENT_DESTROY_QP_DONE) { 47be086e7cSMintz, Yuval u16 icid = 486c9e80eaSMichal Kalderon (u16)le32_to_cpu(data->rdma_data.rdma_destroy_qp_data.cid); 49be086e7cSMintz, Yuval 50be086e7cSMintz, Yuval /* icid release in this async event can occur only if the icid 51be086e7cSMintz, Yuval * was offloaded to the FW. In case it wasn't offloaded this is 52be086e7cSMintz, Yuval * handled in qed_roce_sp_destroy_qp. 53be086e7cSMintz, Yuval */ 54be086e7cSMintz, Yuval qed_roce_free_real_icid(p_hwfn, icid); 55be086e7cSMintz, Yuval } else { 5639dbc646SYuval Bason if (fw_event_code == ROCE_ASYNC_EVENT_SRQ_EMPTY || 5739dbc646SYuval Bason fw_event_code == ROCE_ASYNC_EVENT_SRQ_LIMIT) { 5839dbc646SYuval Bason u16 srq_id = (u16)data->rdma_data.async_handle.lo; 59be086e7cSMintz, Yuval 6039dbc646SYuval Bason events.affiliated_event(events.context, fw_event_code, 6139dbc646SYuval Bason &srq_id); 6239dbc646SYuval Bason } else { 6339dbc646SYuval Bason union rdma_eqe_data rdata = data->rdma_data; 6439dbc646SYuval Bason 6539dbc646SYuval Bason events.affiliated_event(events.context, fw_event_code, 6639dbc646SYuval Bason (void *)&rdata.async_handle); 6739dbc646SYuval Bason } 68be086e7cSMintz, Yuval } 696c9e80eaSMichal Kalderon 706c9e80eaSMichal Kalderon return 0; 7151ff1725SRam Amrani } 7251ff1725SRam Amrani 73898fff12SMichal Kalderon void qed_roce_stop(struct qed_hwfn *p_hwfn) 74898fff12SMichal Kalderon { 75898fff12SMichal Kalderon struct qed_bmap *rcid_map = &p_hwfn->p_rdma_info->real_cid_map; 76898fff12SMichal Kalderon int wait_count = 0; 77898fff12SMichal Kalderon 78898fff12SMichal Kalderon /* when destroying a_RoCE QP the control is returned to the user after 79898fff12SMichal Kalderon * the synchronous part. The asynchronous part may take a little longer. 80898fff12SMichal Kalderon * We delay for a short while if an async destroy QP is still expected. 81898fff12SMichal Kalderon * Beyond the added delay we clear the bitmap anyway. 82898fff12SMichal Kalderon */ 83898fff12SMichal Kalderon while (bitmap_weight(rcid_map->bitmap, rcid_map->max_count)) { 84898fff12SMichal Kalderon msleep(100); 85898fff12SMichal Kalderon if (wait_count++ > 20) { 86898fff12SMichal Kalderon DP_NOTICE(p_hwfn, "cid bitmap wait timed out\n"); 87898fff12SMichal Kalderon break; 88898fff12SMichal Kalderon } 89898fff12SMichal Kalderon } 90898fff12SMichal Kalderon } 91898fff12SMichal Kalderon 92f1093940SRam Amrani static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid, 93f1093940SRam Amrani __le32 *dst_gid) 94f1093940SRam Amrani { 95f1093940SRam Amrani u32 i; 96f1093940SRam Amrani 97f1093940SRam Amrani if (qp->roce_mode == ROCE_V2_IPV4) { 98f1093940SRam Amrani /* The IPv4 addresses shall be aligned to the highest word. 99f1093940SRam Amrani * The lower words must be zero. 100f1093940SRam Amrani */ 101f1093940SRam Amrani memset(src_gid, 0, sizeof(union qed_gid)); 102f1093940SRam Amrani memset(dst_gid, 0, sizeof(union qed_gid)); 103f1093940SRam Amrani src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr); 104f1093940SRam Amrani dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr); 105f1093940SRam Amrani } else { 106f1093940SRam Amrani /* GIDs and IPv6 addresses coincide in location and size */ 107f1093940SRam Amrani for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) { 108f1093940SRam Amrani src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]); 109f1093940SRam Amrani dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]); 110f1093940SRam Amrani } 111f1093940SRam Amrani } 112f1093940SRam Amrani } 113f1093940SRam Amrani 114f1093940SRam Amrani static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode) 115f1093940SRam Amrani { 116f1093940SRam Amrani switch (roce_mode) { 117f1093940SRam Amrani case ROCE_V1: 118d3a31579SNathan Chancellor return PLAIN_ROCE; 119f1093940SRam Amrani case ROCE_V2_IPV4: 120d3a31579SNathan Chancellor return RROCE_IPV4; 121f1093940SRam Amrani case ROCE_V2_IPV6: 122d3a31579SNathan Chancellor return RROCE_IPV6; 123f1093940SRam Amrani default: 124d3a31579SNathan Chancellor return MAX_ROCE_FLAVOR; 125f1093940SRam Amrani } 126f1093940SRam Amrani } 127f1093940SRam Amrani 128bf774d14SYueHaibing static void qed_roce_free_cid_pair(struct qed_hwfn *p_hwfn, u16 cid) 129be086e7cSMintz, Yuval { 130be086e7cSMintz, Yuval spin_lock_bh(&p_hwfn->p_rdma_info->lock); 131be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid); 132be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid + 1); 133be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 134be086e7cSMintz, Yuval } 135be086e7cSMintz, Yuval 136b71b9afdSKalderon, Michal int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid) 137f1093940SRam Amrani { 138f1093940SRam Amrani struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 139f1093940SRam Amrani u32 responder_icid; 140f1093940SRam Amrani u32 requester_icid; 141f1093940SRam Amrani int rc; 142f1093940SRam Amrani 143f1093940SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 144f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 145f1093940SRam Amrani &responder_icid); 146f1093940SRam Amrani if (rc) { 147f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 148f1093940SRam Amrani return rc; 149f1093940SRam Amrani } 150f1093940SRam Amrani 151f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 152f1093940SRam Amrani &requester_icid); 153f1093940SRam Amrani 154f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 155f1093940SRam Amrani if (rc) 156f1093940SRam Amrani goto err; 157f1093940SRam Amrani 158f1093940SRam Amrani /* the two icid's should be adjacent */ 159f1093940SRam Amrani if ((requester_icid - responder_icid) != 1) { 160f1093940SRam Amrani DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n"); 161f1093940SRam Amrani rc = -EINVAL; 162f1093940SRam Amrani goto err; 163f1093940SRam Amrani } 164f1093940SRam Amrani 165f1093940SRam Amrani responder_icid += qed_cxt_get_proto_cid_start(p_hwfn, 166f1093940SRam Amrani p_rdma_info->proto); 167f1093940SRam Amrani requester_icid += qed_cxt_get_proto_cid_start(p_hwfn, 168f1093940SRam Amrani p_rdma_info->proto); 169f1093940SRam Amrani 170f1093940SRam Amrani /* If these icids require a new ILT line allocate DMA-able context for 171f1093940SRam Amrani * an ILT page 172f1093940SRam Amrani */ 173f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid); 174f1093940SRam Amrani if (rc) 175f1093940SRam Amrani goto err; 176f1093940SRam Amrani 177f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid); 178f1093940SRam Amrani if (rc) 179f1093940SRam Amrani goto err; 180f1093940SRam Amrani 181f1093940SRam Amrani *cid = (u16)responder_icid; 182f1093940SRam Amrani return rc; 183f1093940SRam Amrani 184f1093940SRam Amrani err: 185f1093940SRam Amrani spin_lock_bh(&p_rdma_info->lock); 186f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid); 187f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid); 188f1093940SRam Amrani 189f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 190f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 191f1093940SRam Amrani "Allocate CID - failed, rc = %d\n", rc); 192f1093940SRam Amrani return rc; 193f1093940SRam Amrani } 194f1093940SRam Amrani 195be086e7cSMintz, Yuval static void qed_roce_set_real_cid(struct qed_hwfn *p_hwfn, u32 cid) 196be086e7cSMintz, Yuval { 197be086e7cSMintz, Yuval spin_lock_bh(&p_hwfn->p_rdma_info->lock); 198be086e7cSMintz, Yuval qed_bmap_set_id(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, cid); 199be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 200be086e7cSMintz, Yuval } 201be086e7cSMintz, Yuval 20261be82b0SDenis Bolotin static u8 qed_roce_get_qp_tc(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 20361be82b0SDenis Bolotin { 20461be82b0SDenis Bolotin u8 pri, tc = 0; 20561be82b0SDenis Bolotin 20661be82b0SDenis Bolotin if (qp->vlan_id) { 20761be82b0SDenis Bolotin pri = (qp->vlan_id & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 20861be82b0SDenis Bolotin tc = qed_dcbx_get_priority_tc(p_hwfn, pri); 20961be82b0SDenis Bolotin } 21061be82b0SDenis Bolotin 21161be82b0SDenis Bolotin DP_VERBOSE(p_hwfn, QED_MSG_SP, 21261be82b0SDenis Bolotin "qp icid %u tc: %u (vlan priority %s)\n", 21361be82b0SDenis Bolotin qp->icid, tc, qp->vlan_id ? "enabled" : "disabled"); 21461be82b0SDenis Bolotin 21561be82b0SDenis Bolotin return tc; 21661be82b0SDenis Bolotin } 21761be82b0SDenis Bolotin 218f1093940SRam Amrani static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn, 219f1093940SRam Amrani struct qed_rdma_qp *qp) 220f1093940SRam Amrani { 221f1093940SRam Amrani struct roce_create_qp_resp_ramrod_data *p_ramrod; 22261be82b0SDenis Bolotin u16 regular_latency_queue, low_latency_queue; 223f1093940SRam Amrani struct qed_sp_init_data init_data; 224f1093940SRam Amrani enum roce_flavor roce_flavor; 225f1093940SRam Amrani struct qed_spq_entry *p_ent; 226be086e7cSMintz, Yuval enum protocol_type proto; 227f1093940SRam Amrani int rc; 22861be82b0SDenis Bolotin u8 tc; 229f1093940SRam Amrani 2307bfb399eSYuval Basson if (!qp->has_resp) 2317bfb399eSYuval Basson return 0; 2327bfb399eSYuval Basson 233f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 234f1093940SRam Amrani 235f1093940SRam Amrani /* Allocate DMA-able memory for IRQ */ 236f1093940SRam Amrani qp->irq_num_pages = 1; 237f1093940SRam Amrani qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 238f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 239f1093940SRam Amrani &qp->irq_phys_addr, GFP_KERNEL); 240f1093940SRam Amrani if (!qp->irq) { 241f1093940SRam Amrani rc = -ENOMEM; 242f1093940SRam Amrani DP_NOTICE(p_hwfn, 243f1093940SRam Amrani "qed create responder failed: cannot allocate memory (irq). rc = %d\n", 244f1093940SRam Amrani rc); 245f1093940SRam Amrani return rc; 246f1093940SRam Amrani } 247f1093940SRam Amrani 248f1093940SRam Amrani /* Get SPQ entry */ 249f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 250f1093940SRam Amrani init_data.cid = qp->icid; 251f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 252f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 253f1093940SRam Amrani 254f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP, 255f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 256f1093940SRam Amrani if (rc) 257f1093940SRam Amrani goto err; 258f1093940SRam Amrani 259f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_resp; 260f1093940SRam Amrani 261f1093940SRam Amrani p_ramrod->flags = 0; 262f1093940SRam Amrani 263f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 264f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 265f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 266f1093940SRam Amrani 267f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 268f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 269f1093940SRam Amrani qp->incoming_rdma_read_en); 270f1093940SRam Amrani 271f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 272f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 273f1093940SRam Amrani qp->incoming_rdma_write_en); 274f1093940SRam Amrani 275f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 276f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN, 277f1093940SRam Amrani qp->incoming_atomic_en); 278f1093940SRam Amrani 279f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 280f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 281f1093940SRam Amrani qp->e2e_flow_control_en); 282f1093940SRam Amrani 283f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 284f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq); 285f1093940SRam Amrani 286f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 287f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN, 288f1093940SRam Amrani qp->fmr_and_reserved_lkey); 289f1093940SRam Amrani 290f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 291f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 292f1093940SRam Amrani qp->min_rnr_nak_timer); 293f1093940SRam Amrani 2947bfb399eSYuval Basson SET_FIELD(p_ramrod->flags, 2957bfb399eSYuval Basson ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG, 2967bfb399eSYuval Basson qed_rdma_is_xrc_qp(qp)); 2977bfb399eSYuval Basson 298f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 299f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 300f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 301f1093940SRam Amrani p_ramrod->irq_num_pages = qp->irq_num_pages; 302f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 303f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 304f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 305f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 306f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn); 307f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 308f1093940SRam Amrani p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages); 309f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr); 310f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr); 311f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 312f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 313f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 314f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 315f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 316f1093940SRam Amrani p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 317f1093940SRam Amrani qp->rq_cq_id); 3187bfb399eSYuval Basson p_ramrod->xrc_domain = cpu_to_le16(qp->xrcd_id); 319f1093940SRam Amrani 32061be82b0SDenis Bolotin tc = qed_roce_get_qp_tc(p_hwfn, qp); 32161be82b0SDenis Bolotin regular_latency_queue = qed_get_cm_pq_idx_ofld_mtc(p_hwfn, tc); 32261be82b0SDenis Bolotin low_latency_queue = qed_get_cm_pq_idx_llt_mtc(p_hwfn, tc); 32361be82b0SDenis Bolotin DP_VERBOSE(p_hwfn, QED_MSG_SP, 32461be82b0SDenis Bolotin "qp icid %u pqs: regular_latency %u low_latency %u\n", 32561be82b0SDenis Bolotin qp->icid, regular_latency_queue - CM_TX_PQ_BASE, 32661be82b0SDenis Bolotin low_latency_queue - CM_TX_PQ_BASE); 327be086e7cSMintz, Yuval p_ramrod->regular_latency_phy_queue = 328be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 329be086e7cSMintz, Yuval p_ramrod->low_latency_phy_queue = 33061be82b0SDenis Bolotin cpu_to_le16(low_latency_queue); 331be086e7cSMintz, Yuval 332f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 333f1093940SRam Amrani 334f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 335f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 336f1093940SRam Amrani 337f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 338f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 339f1093940SRam Amrani p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id); 340f1093940SRam Amrani p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid); 341f1093940SRam Amrani 342f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 343f1093940SRam Amrani qp->stats_queue; 344f1093940SRam Amrani 345f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 346f1093940SRam Amrani if (rc) 347f1093940SRam Amrani goto err; 348f1093940SRam Amrani 349f1093940SRam Amrani qp->resp_offloaded = true; 350be086e7cSMintz, Yuval qp->cq_prod = 0; 351be086e7cSMintz, Yuval 352be086e7cSMintz, Yuval proto = p_hwfn->p_rdma_info->proto; 353be086e7cSMintz, Yuval qed_roce_set_real_cid(p_hwfn, qp->icid - 354be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, proto)); 355f1093940SRam Amrani 356f1093940SRam Amrani return rc; 357f1093940SRam Amrani 358f1093940SRam Amrani err: 359f1093940SRam Amrani DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc); 360f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 361f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 362f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 363f1093940SRam Amrani 364f1093940SRam Amrani return rc; 365f1093940SRam Amrani } 366f1093940SRam Amrani 367f1093940SRam Amrani static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn, 368f1093940SRam Amrani struct qed_rdma_qp *qp) 369f1093940SRam Amrani { 370f1093940SRam Amrani struct roce_create_qp_req_ramrod_data *p_ramrod; 37161be82b0SDenis Bolotin u16 regular_latency_queue, low_latency_queue; 372f1093940SRam Amrani struct qed_sp_init_data init_data; 373f1093940SRam Amrani enum roce_flavor roce_flavor; 374f1093940SRam Amrani struct qed_spq_entry *p_ent; 375be086e7cSMintz, Yuval enum protocol_type proto; 376f1093940SRam Amrani int rc; 37761be82b0SDenis Bolotin u8 tc; 378f1093940SRam Amrani 3797bfb399eSYuval Basson if (!qp->has_req) 3807bfb399eSYuval Basson return 0; 3817bfb399eSYuval Basson 382f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 383f1093940SRam Amrani 384f1093940SRam Amrani /* Allocate DMA-able memory for ORQ */ 385f1093940SRam Amrani qp->orq_num_pages = 1; 386f1093940SRam Amrani qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 387f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 388f1093940SRam Amrani &qp->orq_phys_addr, GFP_KERNEL); 389f1093940SRam Amrani if (!qp->orq) { 390f1093940SRam Amrani rc = -ENOMEM; 391f1093940SRam Amrani DP_NOTICE(p_hwfn, 392f1093940SRam Amrani "qed create requester failed: cannot allocate memory (orq). rc = %d\n", 393f1093940SRam Amrani rc); 394f1093940SRam Amrani return rc; 395f1093940SRam Amrani } 396f1093940SRam Amrani 397f1093940SRam Amrani /* Get SPQ entry */ 398f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 399f1093940SRam Amrani init_data.cid = qp->icid + 1; 400f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 401f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 402f1093940SRam Amrani 403f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 404f1093940SRam Amrani ROCE_RAMROD_CREATE_QP, 405f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 406f1093940SRam Amrani if (rc) 407f1093940SRam Amrani goto err; 408f1093940SRam Amrani 409f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_req; 410f1093940SRam Amrani 411f1093940SRam Amrani p_ramrod->flags = 0; 412f1093940SRam Amrani 413f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 414f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 415f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 416f1093940SRam Amrani 417f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 418f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN, 419f1093940SRam Amrani qp->fmr_and_reserved_lkey); 420f1093940SRam Amrani 421f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 422f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all); 423f1093940SRam Amrani 424f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 425f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 426f1093940SRam Amrani 427f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 428f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 429f1093940SRam Amrani qp->rnr_retry_cnt); 430f1093940SRam Amrani 4317bfb399eSYuval Basson SET_FIELD(p_ramrod->flags, 4327bfb399eSYuval Basson ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG, 4337bfb399eSYuval Basson qed_rdma_is_xrc_qp(qp)); 4347bfb399eSYuval Basson 435ff937b91SYuval Basson SET_FIELD(p_ramrod->flags2, 436ff937b91SYuval Basson ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE, qp->edpm_mode); 437ff937b91SYuval Basson 438f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 439f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 440f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 441f1093940SRam Amrani p_ramrod->orq_num_pages = qp->orq_num_pages; 442f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 443f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 444f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 445f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 446f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 447f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn); 448f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 449f1093940SRam Amrani p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages); 450f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr); 451f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr); 452f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 453f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 454f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 455f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 456f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 457be086e7cSMintz, Yuval p_ramrod->cq_cid = 458be086e7cSMintz, Yuval cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | qp->sq_cq_id); 459f1093940SRam Amrani 46061be82b0SDenis Bolotin tc = qed_roce_get_qp_tc(p_hwfn, qp); 46161be82b0SDenis Bolotin regular_latency_queue = qed_get_cm_pq_idx_ofld_mtc(p_hwfn, tc); 46261be82b0SDenis Bolotin low_latency_queue = qed_get_cm_pq_idx_llt_mtc(p_hwfn, tc); 46361be82b0SDenis Bolotin DP_VERBOSE(p_hwfn, QED_MSG_SP, 46461be82b0SDenis Bolotin "qp icid %u pqs: regular_latency %u low_latency %u\n", 46561be82b0SDenis Bolotin qp->icid, regular_latency_queue - CM_TX_PQ_BASE, 46661be82b0SDenis Bolotin low_latency_queue - CM_TX_PQ_BASE); 467be086e7cSMintz, Yuval p_ramrod->regular_latency_phy_queue = 468be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 469be086e7cSMintz, Yuval p_ramrod->low_latency_phy_queue = 47061be82b0SDenis Bolotin cpu_to_le16(low_latency_queue); 471be086e7cSMintz, Yuval 472f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 473f1093940SRam Amrani 474f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 475f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 476f1093940SRam Amrani 477f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 478f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 479f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 480f1093940SRam Amrani qp->stats_queue; 481f1093940SRam Amrani 482f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 483f1093940SRam Amrani if (rc) 484f1093940SRam Amrani goto err; 485f1093940SRam Amrani 486f1093940SRam Amrani qp->req_offloaded = true; 487be086e7cSMintz, Yuval proto = p_hwfn->p_rdma_info->proto; 488be086e7cSMintz, Yuval qed_roce_set_real_cid(p_hwfn, 489be086e7cSMintz, Yuval qp->icid + 1 - 490be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, proto)); 491f1093940SRam Amrani 492f1093940SRam Amrani return rc; 493f1093940SRam Amrani 494f1093940SRam Amrani err: 495f1093940SRam Amrani DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc); 496f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 497f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 498f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 499f1093940SRam Amrani return rc; 500f1093940SRam Amrani } 501f1093940SRam Amrani 502f1093940SRam Amrani static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn, 503f1093940SRam Amrani struct qed_rdma_qp *qp, 504f1093940SRam Amrani bool move_to_err, u32 modify_flags) 505f1093940SRam Amrani { 506f1093940SRam Amrani struct roce_modify_qp_resp_ramrod_data *p_ramrod; 507f1093940SRam Amrani struct qed_sp_init_data init_data; 508f1093940SRam Amrani struct qed_spq_entry *p_ent; 509f1093940SRam Amrani int rc; 510f1093940SRam Amrani 5117bfb399eSYuval Basson if (!qp->has_resp) 5127bfb399eSYuval Basson return 0; 5137bfb399eSYuval Basson 514f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 515f1093940SRam Amrani 516f1093940SRam Amrani if (move_to_err && !qp->resp_offloaded) 517f1093940SRam Amrani return 0; 518f1093940SRam Amrani 519f1093940SRam Amrani /* Get SPQ entry */ 520f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 521f1093940SRam Amrani init_data.cid = qp->icid; 522f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 523f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 524f1093940SRam Amrani 525f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 526f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 527f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 528f1093940SRam Amrani if (rc) { 529f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 530f1093940SRam Amrani return rc; 531f1093940SRam Amrani } 532f1093940SRam Amrani 533f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_resp; 534f1093940SRam Amrani 535f1093940SRam Amrani p_ramrod->flags = 0; 536f1093940SRam Amrani 537f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 538f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 539f1093940SRam Amrani 540f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 541f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 542f1093940SRam Amrani qp->incoming_rdma_read_en); 543f1093940SRam Amrani 544f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 545f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 546f1093940SRam Amrani qp->incoming_rdma_write_en); 547f1093940SRam Amrani 548f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 549f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN, 550f1093940SRam Amrani qp->incoming_atomic_en); 551f1093940SRam Amrani 552f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 553f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 554f1093940SRam Amrani qp->e2e_flow_control_en); 555f1093940SRam Amrani 556f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 557f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG, 558f1093940SRam Amrani GET_FIELD(modify_flags, 559f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)); 560f1093940SRam Amrani 561f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 562f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG, 563f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 564f1093940SRam Amrani 565f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 566f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG, 567f1093940SRam Amrani GET_FIELD(modify_flags, 568f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 569f1093940SRam Amrani 570f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 571f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG, 572f1093940SRam Amrani GET_FIELD(modify_flags, 573f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)); 574f1093940SRam Amrani 575f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 576f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG, 577f1093940SRam Amrani GET_FIELD(modify_flags, 578f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)); 579f1093940SRam Amrani 580f1093940SRam Amrani p_ramrod->fields = 0; 581f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 582f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 583f1093940SRam Amrani qp->min_rnr_nak_timer); 584f1093940SRam Amrani 585f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 586f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 587f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 588f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 589f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 590f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 591f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 592f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 593f1093940SRam Amrani 594f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc); 595f1093940SRam Amrani return rc; 596f1093940SRam Amrani } 597f1093940SRam Amrani 598f1093940SRam Amrani static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn, 599f1093940SRam Amrani struct qed_rdma_qp *qp, 600f1093940SRam Amrani bool move_to_sqd, 601f1093940SRam Amrani bool move_to_err, u32 modify_flags) 602f1093940SRam Amrani { 603f1093940SRam Amrani struct roce_modify_qp_req_ramrod_data *p_ramrod; 604f1093940SRam Amrani struct qed_sp_init_data init_data; 605f1093940SRam Amrani struct qed_spq_entry *p_ent; 606f1093940SRam Amrani int rc; 607f1093940SRam Amrani 6087bfb399eSYuval Basson if (!qp->has_req) 6097bfb399eSYuval Basson return 0; 6107bfb399eSYuval Basson 611f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 612f1093940SRam Amrani 613f1093940SRam Amrani if (move_to_err && !(qp->req_offloaded)) 614f1093940SRam Amrani return 0; 615f1093940SRam Amrani 616f1093940SRam Amrani /* Get SPQ entry */ 617f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 618f1093940SRam Amrani init_data.cid = qp->icid + 1; 619f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 620f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 621f1093940SRam Amrani 622f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 623f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 624f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 625f1093940SRam Amrani if (rc) { 626f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 627f1093940SRam Amrani return rc; 628f1093940SRam Amrani } 629f1093940SRam Amrani 630f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_req; 631f1093940SRam Amrani 632f1093940SRam Amrani p_ramrod->flags = 0; 633f1093940SRam Amrani 634f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 635f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 636f1093940SRam Amrani 637f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 638f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd); 639f1093940SRam Amrani 640f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 641f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY, 642f1093940SRam Amrani qp->sqd_async); 643f1093940SRam Amrani 644f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 645f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG, 646f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 647f1093940SRam Amrani 648f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 649f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG, 650f1093940SRam Amrani GET_FIELD(modify_flags, 651f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 652f1093940SRam Amrani 653f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 654f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG, 655f1093940SRam Amrani GET_FIELD(modify_flags, 656f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)); 657f1093940SRam Amrani 658f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 659f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG, 660f1093940SRam Amrani GET_FIELD(modify_flags, 661f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)); 662f1093940SRam Amrani 663f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 664f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG, 665f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)); 666f1093940SRam Amrani 667f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 668f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG, 669f1093940SRam Amrani GET_FIELD(modify_flags, 670f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)); 671f1093940SRam Amrani 672f1093940SRam Amrani p_ramrod->fields = 0; 673f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 674f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 675f1093940SRam Amrani 676f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 677f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 678f1093940SRam Amrani qp->rnr_retry_cnt); 679f1093940SRam Amrani 680f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 681f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 682f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 683f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 684f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 685f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 686f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 687f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 688f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 689f1093940SRam Amrani 690f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc); 691f1093940SRam Amrani return rc; 692f1093940SRam Amrani } 693f1093940SRam Amrani 694f1093940SRam Amrani static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn, 695f1093940SRam Amrani struct qed_rdma_qp *qp, 696be086e7cSMintz, Yuval u32 *cq_prod) 697f1093940SRam Amrani { 698f1093940SRam Amrani struct roce_destroy_qp_resp_output_params *p_ramrod_res; 699f1093940SRam Amrani struct roce_destroy_qp_resp_ramrod_data *p_ramrod; 700f1093940SRam Amrani struct qed_sp_init_data init_data; 701f1093940SRam Amrani struct qed_spq_entry *p_ent; 702f1093940SRam Amrani dma_addr_t ramrod_res_phys; 703f1093940SRam Amrani int rc; 704f1093940SRam Amrani 7057bfb399eSYuval Basson if (!qp->has_resp) { 7067bfb399eSYuval Basson *cq_prod = 0; 7077bfb399eSYuval Basson return 0; 7087bfb399eSYuval Basson } 7097bfb399eSYuval Basson 710f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 711be086e7cSMintz, Yuval *cq_prod = qp->cq_prod; 712be086e7cSMintz, Yuval 713be086e7cSMintz, Yuval if (!qp->resp_offloaded) { 714be086e7cSMintz, Yuval /* If a responder was never offload, we need to free the cids 715be086e7cSMintz, Yuval * allocated in create_qp as a FW async event will never arrive 716be086e7cSMintz, Yuval */ 717be086e7cSMintz, Yuval u32 cid; 718be086e7cSMintz, Yuval 719be086e7cSMintz, Yuval cid = qp->icid - 720be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, 721be086e7cSMintz, Yuval p_hwfn->p_rdma_info->proto); 722be086e7cSMintz, Yuval qed_roce_free_cid_pair(p_hwfn, (u16)cid); 723be086e7cSMintz, Yuval 724f1093940SRam Amrani return 0; 725be086e7cSMintz, Yuval } 726f1093940SRam Amrani 727f1093940SRam Amrani /* Get SPQ entry */ 728f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 729f1093940SRam Amrani init_data.cid = qp->icid; 730f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 731f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 732f1093940SRam Amrani 733f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 734f1093940SRam Amrani ROCE_RAMROD_DESTROY_QP, 735f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 736f1093940SRam Amrani if (rc) 737f1093940SRam Amrani return rc; 738f1093940SRam Amrani 739f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp; 740f1093940SRam Amrani 741745e5ad5SAishwarya Ramakrishnan p_ramrod_res = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 742745e5ad5SAishwarya Ramakrishnan sizeof(*p_ramrod_res), 743f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 744f1093940SRam Amrani 745f1093940SRam Amrani if (!p_ramrod_res) { 746f1093940SRam Amrani rc = -ENOMEM; 747f1093940SRam Amrani DP_NOTICE(p_hwfn, 748f1093940SRam Amrani "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n", 749f1093940SRam Amrani rc); 750fb5e7438SDenis Bolotin qed_sp_destroy_request(p_hwfn, p_ent); 751f1093940SRam Amrani return rc; 752f1093940SRam Amrani } 753f1093940SRam Amrani 754f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 755f1093940SRam Amrani 756f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 757f1093940SRam Amrani if (rc) 758f1093940SRam Amrani goto err; 759f1093940SRam Amrani 760be086e7cSMintz, Yuval *cq_prod = le32_to_cpu(p_ramrod_res->cq_prod); 761be086e7cSMintz, Yuval qp->cq_prod = *cq_prod; 762f1093940SRam Amrani 763f1093940SRam Amrani /* Free IRQ - only if ramrod succeeded, in case FW is still using it */ 764f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 765f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 766f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 767f1093940SRam Amrani 768f1093940SRam Amrani qp->resp_offloaded = false; 769f1093940SRam Amrani 770f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc); 771f1093940SRam Amrani 772f1093940SRam Amrani err: 773f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 774f1093940SRam Amrani sizeof(struct roce_destroy_qp_resp_output_params), 775f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 776f1093940SRam Amrani 777f1093940SRam Amrani return rc; 778f1093940SRam Amrani } 779f1093940SRam Amrani 780f1093940SRam Amrani static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn, 781d52c89f1SMichal Kalderon struct qed_rdma_qp *qp) 782f1093940SRam Amrani { 783f1093940SRam Amrani struct roce_destroy_qp_req_output_params *p_ramrod_res; 784f1093940SRam Amrani struct roce_destroy_qp_req_ramrod_data *p_ramrod; 785f1093940SRam Amrani struct qed_sp_init_data init_data; 786f1093940SRam Amrani struct qed_spq_entry *p_ent; 787f1093940SRam Amrani dma_addr_t ramrod_res_phys; 788f1093940SRam Amrani int rc = -ENOMEM; 789f1093940SRam Amrani 7907bfb399eSYuval Basson if (!qp->has_req) 7917bfb399eSYuval Basson return 0; 7927bfb399eSYuval Basson 793f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 794f1093940SRam Amrani 795f1093940SRam Amrani if (!qp->req_offloaded) 796f1093940SRam Amrani return 0; 797f1093940SRam Amrani 798f1093940SRam Amrani p_ramrod_res = (struct roce_destroy_qp_req_output_params *) 799f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 800f1093940SRam Amrani sizeof(*p_ramrod_res), 801f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 802f1093940SRam Amrani if (!p_ramrod_res) { 803f1093940SRam Amrani DP_NOTICE(p_hwfn, 804f1093940SRam Amrani "qed destroy requester failed: cannot allocate memory (ramrod)\n"); 805f1093940SRam Amrani return rc; 806f1093940SRam Amrani } 807f1093940SRam Amrani 808f1093940SRam Amrani /* Get SPQ entry */ 809f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 810f1093940SRam Amrani init_data.cid = qp->icid + 1; 811f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 812f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 813f1093940SRam Amrani 814f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP, 815f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 816f1093940SRam Amrani if (rc) 817f1093940SRam Amrani goto err; 818f1093940SRam Amrani 819f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_req; 820f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 821f1093940SRam Amrani 822f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 823f1093940SRam Amrani if (rc) 824f1093940SRam Amrani goto err; 825f1093940SRam Amrani 826f1093940SRam Amrani 827f1093940SRam Amrani /* Free ORQ - only if ramrod succeeded, in case FW is still using it */ 828f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 829f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 830f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 831f1093940SRam Amrani 832f1093940SRam Amrani qp->req_offloaded = false; 833f1093940SRam Amrani 834f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc); 835f1093940SRam Amrani 836f1093940SRam Amrani err: 837f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 838f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 839f1093940SRam Amrani 840f1093940SRam Amrani return rc; 841f1093940SRam Amrani } 842f1093940SRam Amrani 843b71b9afdSKalderon, Michal int qed_roce_query_qp(struct qed_hwfn *p_hwfn, 844f1093940SRam Amrani struct qed_rdma_qp *qp, 845f1093940SRam Amrani struct qed_rdma_query_qp_out_params *out_params) 846f1093940SRam Amrani { 847f1093940SRam Amrani struct roce_query_qp_resp_output_params *p_resp_ramrod_res; 848f1093940SRam Amrani struct roce_query_qp_req_output_params *p_req_ramrod_res; 849f1093940SRam Amrani struct roce_query_qp_resp_ramrod_data *p_resp_ramrod; 850f1093940SRam Amrani struct roce_query_qp_req_ramrod_data *p_req_ramrod; 851f1093940SRam Amrani struct qed_sp_init_data init_data; 852f1093940SRam Amrani dma_addr_t resp_ramrod_res_phys; 853f1093940SRam Amrani dma_addr_t req_ramrod_res_phys; 854f1093940SRam Amrani struct qed_spq_entry *p_ent; 855f1093940SRam Amrani bool rq_err_state; 856f1093940SRam Amrani bool sq_err_state; 857f1093940SRam Amrani bool sq_draining; 858f1093940SRam Amrani int rc = -ENOMEM; 859f1093940SRam Amrani 860f1093940SRam Amrani if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) { 861f1093940SRam Amrani /* We can't send ramrod to the fw since this qp wasn't offloaded 862f1093940SRam Amrani * to the fw yet 863f1093940SRam Amrani */ 864f1093940SRam Amrani out_params->draining = false; 865f1093940SRam Amrani out_params->rq_psn = qp->rq_psn; 866f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 867f1093940SRam Amrani out_params->state = qp->cur_state; 868f1093940SRam Amrani 869f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n"); 870f1093940SRam Amrani return 0; 871f1093940SRam Amrani } 872f1093940SRam Amrani 873f1093940SRam Amrani if (!(qp->resp_offloaded)) { 874f1093940SRam Amrani DP_NOTICE(p_hwfn, 875df80b8fbSColin Ian King "The responder's qp should be offloaded before requester's\n"); 876f1093940SRam Amrani return -EINVAL; 877f1093940SRam Amrani } 878f1093940SRam Amrani 879f1093940SRam Amrani /* Send a query responder ramrod to FW to get RQ-PSN and state */ 880745e5ad5SAishwarya Ramakrishnan p_resp_ramrod_res = 881f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 882f1093940SRam Amrani sizeof(*p_resp_ramrod_res), 883f1093940SRam Amrani &resp_ramrod_res_phys, GFP_KERNEL); 884f1093940SRam Amrani if (!p_resp_ramrod_res) { 885f1093940SRam Amrani DP_NOTICE(p_hwfn, 886f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 887f1093940SRam Amrani return rc; 888f1093940SRam Amrani } 889f1093940SRam Amrani 890f1093940SRam Amrani /* Get SPQ entry */ 891f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 892f1093940SRam Amrani init_data.cid = qp->icid; 893f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 894f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 895f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 896f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 897f1093940SRam Amrani if (rc) 898f1093940SRam Amrani goto err_resp; 899f1093940SRam Amrani 900f1093940SRam Amrani p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp; 901f1093940SRam Amrani DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys); 902f1093940SRam Amrani 903f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 904f1093940SRam Amrani if (rc) 905f1093940SRam Amrani goto err_resp; 906f1093940SRam Amrani 907f1093940SRam Amrani out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn); 9080500a70dSMichal Kalderon rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->flags), 909f1093940SRam Amrani ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG); 910f1093940SRam Amrani 911c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 912c5212b94SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 913c5212b94SRam Amrani 914f1093940SRam Amrani if (!(qp->req_offloaded)) { 915f1093940SRam Amrani /* Don't send query qp for the requester */ 916f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 917f1093940SRam Amrani out_params->draining = false; 918f1093940SRam Amrani 919f1093940SRam Amrani if (rq_err_state) 920f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 921f1093940SRam Amrani 922f1093940SRam Amrani out_params->state = qp->cur_state; 923f1093940SRam Amrani 924f1093940SRam Amrani return 0; 925f1093940SRam Amrani } 926f1093940SRam Amrani 927f1093940SRam Amrani /* Send a query requester ramrod to FW to get SQ-PSN and state */ 928745e5ad5SAishwarya Ramakrishnan p_req_ramrod_res = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 929f1093940SRam Amrani sizeof(*p_req_ramrod_res), 930f1093940SRam Amrani &req_ramrod_res_phys, 931f1093940SRam Amrani GFP_KERNEL); 932f1093940SRam Amrani if (!p_req_ramrod_res) { 933f1093940SRam Amrani rc = -ENOMEM; 934f1093940SRam Amrani DP_NOTICE(p_hwfn, 935f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 936f1093940SRam Amrani return rc; 937f1093940SRam Amrani } 938f1093940SRam Amrani 939f1093940SRam Amrani /* Get SPQ entry */ 940f1093940SRam Amrani init_data.cid = qp->icid + 1; 941f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 942f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 943f1093940SRam Amrani if (rc) 944f1093940SRam Amrani goto err_req; 945f1093940SRam Amrani 946f1093940SRam Amrani p_req_ramrod = &p_ent->ramrod.roce_query_qp_req; 947f1093940SRam Amrani DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys); 948f1093940SRam Amrani 949f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 950f1093940SRam Amrani if (rc) 951f1093940SRam Amrani goto err_req; 952f1093940SRam Amrani 953f1093940SRam Amrani out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn); 954f1093940SRam Amrani sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 955f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG); 956f1093940SRam Amrani sq_draining = 957f1093940SRam Amrani GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 958f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG); 959f1093940SRam Amrani 960c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 961c5212b94SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 962c5212b94SRam Amrani 963f1093940SRam Amrani out_params->draining = false; 964f1093940SRam Amrani 965be086e7cSMintz, Yuval if (rq_err_state || sq_err_state) 966f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 967f1093940SRam Amrani else if (sq_draining) 968f1093940SRam Amrani out_params->draining = true; 969f1093940SRam Amrani out_params->state = qp->cur_state; 970f1093940SRam Amrani 971f1093940SRam Amrani return 0; 972f1093940SRam Amrani 973f1093940SRam Amrani err_req: 974f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 975f1093940SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 976f1093940SRam Amrani return rc; 977f1093940SRam Amrani err_resp: 978f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 979f1093940SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 980f1093940SRam Amrani return rc; 981f1093940SRam Amrani } 982f1093940SRam Amrani 983b71b9afdSKalderon, Michal int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 984f1093940SRam Amrani { 985be086e7cSMintz, Yuval u32 cq_prod; 986f1093940SRam Amrani int rc; 987f1093940SRam Amrani 988f1093940SRam Amrani /* Destroys the specified QP */ 989f1093940SRam Amrani if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) && 990f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_ERR) && 991f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_INIT)) { 992f1093940SRam Amrani DP_NOTICE(p_hwfn, 993f1093940SRam Amrani "QP must be in error, reset or init state before destroying it\n"); 994f1093940SRam Amrani return -EINVAL; 995f1093940SRam Amrani } 996f1093940SRam Amrani 997300c0d7cSRam Amrani if (qp->cur_state != QED_ROCE_QP_STATE_RESET) { 998300c0d7cSRam Amrani rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, 999be086e7cSMintz, Yuval &cq_prod); 1000f1093940SRam Amrani if (rc) 1001f1093940SRam Amrani return rc; 1002f1093940SRam Amrani 1003f1093940SRam Amrani /* Send destroy requester ramrod */ 1004d52c89f1SMichal Kalderon rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp); 1005f1093940SRam Amrani if (rc) 1006f1093940SRam Amrani return rc; 1007300c0d7cSRam Amrani } 1008f1093940SRam Amrani 1009f1093940SRam Amrani return 0; 1010f1093940SRam Amrani } 1011f1093940SRam Amrani 1012b71b9afdSKalderon, Michal int qed_roce_modify_qp(struct qed_hwfn *p_hwfn, 1013f1093940SRam Amrani struct qed_rdma_qp *qp, 1014f1093940SRam Amrani enum qed_roce_qp_state prev_state, 1015f1093940SRam Amrani struct qed_rdma_modify_qp_in_params *params) 1016f1093940SRam Amrani { 1017f1093940SRam Amrani int rc = 0; 1018f1093940SRam Amrani 1019f1093940SRam Amrani /* Perform additional operations according to the current state and the 1020f1093940SRam Amrani * next state 1021f1093940SRam Amrani */ 1022f1093940SRam Amrani if (((prev_state == QED_ROCE_QP_STATE_INIT) || 1023f1093940SRam Amrani (prev_state == QED_ROCE_QP_STATE_RESET)) && 1024f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTR)) { 1025f1093940SRam Amrani /* Init->RTR or Reset->RTR */ 1026f1093940SRam Amrani rc = qed_roce_sp_create_responder(p_hwfn, qp); 1027f1093940SRam Amrani return rc; 1028f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTR) && 1029f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1030f1093940SRam Amrani /* RTR-> RTS */ 1031f1093940SRam Amrani rc = qed_roce_sp_create_requester(p_hwfn, qp); 1032f1093940SRam Amrani if (rc) 1033f1093940SRam Amrani return rc; 1034f1093940SRam Amrani 1035f1093940SRam Amrani /* Send modify responder ramrod */ 1036f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1037f1093940SRam Amrani params->modify_flags); 1038f1093940SRam Amrani return rc; 1039f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1040f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1041f1093940SRam Amrani /* RTS->RTS */ 1042f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1043f1093940SRam Amrani params->modify_flags); 1044f1093940SRam Amrani if (rc) 1045f1093940SRam Amrani return rc; 1046f1093940SRam Amrani 1047f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1048f1093940SRam Amrani params->modify_flags); 1049f1093940SRam Amrani return rc; 1050f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1051f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1052f1093940SRam Amrani /* RTS->SQD */ 1053f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false, 1054f1093940SRam Amrani params->modify_flags); 1055f1093940SRam Amrani return rc; 1056f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1057f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1058f1093940SRam Amrani /* SQD->SQD */ 1059f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1060f1093940SRam Amrani params->modify_flags); 1061f1093940SRam Amrani if (rc) 1062f1093940SRam Amrani return rc; 1063f1093940SRam Amrani 1064f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1065f1093940SRam Amrani params->modify_flags); 1066f1093940SRam Amrani return rc; 1067f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1068f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1069f1093940SRam Amrani /* SQD->RTS */ 1070f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1071f1093940SRam Amrani params->modify_flags); 1072f1093940SRam Amrani if (rc) 1073f1093940SRam Amrani return rc; 1074f1093940SRam Amrani 1075f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1076f1093940SRam Amrani params->modify_flags); 1077f1093940SRam Amrani 1078f1093940SRam Amrani return rc; 1079ba0154e9SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR) { 1080f1093940SRam Amrani /* ->ERR */ 1081f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, true, 1082f1093940SRam Amrani params->modify_flags); 1083f1093940SRam Amrani if (rc) 1084f1093940SRam Amrani return rc; 1085f1093940SRam Amrani 1086f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true, 1087f1093940SRam Amrani params->modify_flags); 1088f1093940SRam Amrani return rc; 1089f1093940SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) { 1090f1093940SRam Amrani /* Any state -> RESET */ 1091be086e7cSMintz, Yuval u32 cq_prod; 1092f1093940SRam Amrani 1093be086e7cSMintz, Yuval /* Send destroy responder ramrod */ 1094be086e7cSMintz, Yuval rc = qed_roce_sp_destroy_qp_responder(p_hwfn, 1095be086e7cSMintz, Yuval qp, 1096be086e7cSMintz, Yuval &cq_prod); 1097be086e7cSMintz, Yuval 1098f1093940SRam Amrani if (rc) 1099f1093940SRam Amrani return rc; 1100f1093940SRam Amrani 1101be086e7cSMintz, Yuval qp->cq_prod = cq_prod; 1102be086e7cSMintz, Yuval 1103d52c89f1SMichal Kalderon rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp); 1104f1093940SRam Amrani } else { 1105f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 1106f1093940SRam Amrani } 1107f1093940SRam Amrani 1108f1093940SRam Amrani return rc; 1109f1093940SRam Amrani } 1110f1093940SRam Amrani 1111be086e7cSMintz, Yuval static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid) 1112be086e7cSMintz, Yuval { 1113be086e7cSMintz, Yuval struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 1114be086e7cSMintz, Yuval u32 start_cid, cid, xcid; 1115be086e7cSMintz, Yuval 1116be086e7cSMintz, Yuval /* an even icid belongs to a responder while an odd icid belongs to a 1117be086e7cSMintz, Yuval * requester. The 'cid' received as an input can be either. We calculate 1118be086e7cSMintz, Yuval * the "partner" icid and call it xcid. Only if both are free then the 1119be086e7cSMintz, Yuval * "cid" map can be cleared. 1120be086e7cSMintz, Yuval */ 1121be086e7cSMintz, Yuval start_cid = qed_cxt_get_proto_cid_start(p_hwfn, p_rdma_info->proto); 1122be086e7cSMintz, Yuval cid = icid - start_cid; 1123be086e7cSMintz, Yuval xcid = cid ^ 1; 1124be086e7cSMintz, Yuval 1125be086e7cSMintz, Yuval spin_lock_bh(&p_rdma_info->lock); 1126be086e7cSMintz, Yuval 1127be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->real_cid_map, cid); 1128be086e7cSMintz, Yuval if (qed_bmap_test_id(p_hwfn, &p_rdma_info->real_cid_map, xcid) == 0) { 1129be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, cid); 1130be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, xcid); 1131be086e7cSMintz, Yuval } 1132be086e7cSMintz, Yuval 1133be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1134be086e7cSMintz, Yuval } 1135be086e7cSMintz, Yuval 11369331dad1SMintz, Yuval void qed_roce_dpm_dcbx(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11379331dad1SMintz, Yuval { 11389331dad1SMintz, Yuval u8 val; 11399331dad1SMintz, Yuval 11409331dad1SMintz, Yuval /* if any QPs are already active, we want to disable DPM, since their 11419331dad1SMintz, Yuval * context information contains information from before the latest DCBx 11429331dad1SMintz, Yuval * update. Otherwise enable it. 11439331dad1SMintz, Yuval */ 11449331dad1SMintz, Yuval val = qed_rdma_allocated_qps(p_hwfn) ? true : false; 11459331dad1SMintz, Yuval p_hwfn->dcbx_no_edpm = (u8)val; 11469331dad1SMintz, Yuval 11479331dad1SMintz, Yuval qed_rdma_dpm_conf(p_hwfn, p_ptt); 11489331dad1SMintz, Yuval } 11499331dad1SMintz, Yuval 1150b71b9afdSKalderon, Michal int qed_roce_setup(struct qed_hwfn *p_hwfn) 115151ff1725SRam Amrani { 1152b71b9afdSKalderon, Michal return qed_spq_register_async_cb(p_hwfn, PROTOCOLID_ROCE, 1153b71b9afdSKalderon, Michal qed_roce_async_event); 115451ff1725SRam Amrani } 115551ff1725SRam Amrani 115667b40dccSKalderon, Michal int qed_roce_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 115767b40dccSKalderon, Michal { 115867b40dccSKalderon, Michal u32 ll2_ethertype_en; 115967b40dccSKalderon, Michal 116067b40dccSKalderon, Michal qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 116167b40dccSKalderon, Michal 116267b40dccSKalderon, Michal p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE; 116367b40dccSKalderon, Michal 116467b40dccSKalderon, Michal ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 116567b40dccSKalderon, Michal qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 116667b40dccSKalderon, Michal (ll2_ethertype_en | 0x01)); 116767b40dccSKalderon, Michal 116867b40dccSKalderon, Michal if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) { 116967b40dccSKalderon, Michal DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n"); 117067b40dccSKalderon, Michal return -EINVAL; 117167b40dccSKalderon, Michal } 117267b40dccSKalderon, Michal 117367b40dccSKalderon, Michal DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n"); 117467b40dccSKalderon, Michal return 0; 117567b40dccSKalderon, Michal } 1176