151ff1725SRam Amrani /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 351ff1725SRam Amrani * 451ff1725SRam Amrani * This software is available to you under a choice of one of two 551ff1725SRam Amrani * licenses. You may choose to be licensed under the terms of the GNU 651ff1725SRam Amrani * General Public License (GPL) Version 2, available from the file 751ff1725SRam Amrani * COPYING in the main directory of this source tree, or the 851ff1725SRam Amrani * OpenIB.org BSD license below: 951ff1725SRam Amrani * 1051ff1725SRam Amrani * Redistribution and use in source and binary forms, with or 1151ff1725SRam Amrani * without modification, are permitted provided that the following 1251ff1725SRam Amrani * conditions are met: 1351ff1725SRam Amrani * 1451ff1725SRam Amrani * - Redistributions of source code must retain the above 1551ff1725SRam Amrani * copyright notice, this list of conditions and the following 1651ff1725SRam Amrani * disclaimer. 1751ff1725SRam Amrani * 1851ff1725SRam Amrani * - Redistributions in binary form must reproduce the above 1951ff1725SRam Amrani * copyright notice, this list of conditions and the following 2051ff1725SRam Amrani * disclaimer in the documentation and /or other materials 2151ff1725SRam Amrani * provided with the distribution. 2251ff1725SRam Amrani * 2351ff1725SRam Amrani * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 2451ff1725SRam Amrani * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 2551ff1725SRam Amrani * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 2651ff1725SRam Amrani * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 2751ff1725SRam Amrani * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 2851ff1725SRam Amrani * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 2951ff1725SRam Amrani * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 3051ff1725SRam Amrani * SOFTWARE. 3151ff1725SRam Amrani */ 3251ff1725SRam Amrani #include <linux/types.h> 3351ff1725SRam Amrani #include <asm/byteorder.h> 3451ff1725SRam Amrani #include <linux/bitops.h> 3551ff1725SRam Amrani #include <linux/delay.h> 3651ff1725SRam Amrani #include <linux/dma-mapping.h> 3751ff1725SRam Amrani #include <linux/errno.h> 3851ff1725SRam Amrani #include <linux/io.h> 3951ff1725SRam Amrani #include <linux/kernel.h> 4051ff1725SRam Amrani #include <linux/list.h> 4151ff1725SRam Amrani #include <linux/module.h> 4251ff1725SRam Amrani #include <linux/mutex.h> 4351ff1725SRam Amrani #include <linux/pci.h> 4451ff1725SRam Amrani #include <linux/slab.h> 4551ff1725SRam Amrani #include <linux/spinlock.h> 4651ff1725SRam Amrani #include <linux/string.h> 4761be82b0SDenis Bolotin #include <linux/if_vlan.h> 4851ff1725SRam Amrani #include "qed.h" 4951ff1725SRam Amrani #include "qed_cxt.h" 5061be82b0SDenis Bolotin #include "qed_dcbx.h" 5151ff1725SRam Amrani #include "qed_hsi.h" 5251ff1725SRam Amrani #include "qed_hw.h" 5351ff1725SRam Amrani #include "qed_init_ops.h" 5451ff1725SRam Amrani #include "qed_int.h" 5551ff1725SRam Amrani #include "qed_ll2.h" 5651ff1725SRam Amrani #include "qed_mcp.h" 5751ff1725SRam Amrani #include "qed_reg_addr.h" 587003cdd6SKalderon, Michal #include <linux/qed/qed_rdma_if.h> 59b71b9afdSKalderon, Michal #include "qed_rdma.h" 60b71b9afdSKalderon, Michal #include "qed_roce.h" 618e8dddbaSKalderon, Michal #include "qed_sp.h" 6251ff1725SRam Amrani 63be086e7cSMintz, Yuval static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid); 6451ff1725SRam Amrani 656c9e80eaSMichal Kalderon static int 666c9e80eaSMichal Kalderon qed_roce_async_event(struct qed_hwfn *p_hwfn, 676c9e80eaSMichal Kalderon u8 fw_event_code, 686c9e80eaSMichal Kalderon u16 echo, union event_ring_data *data, u8 fw_return_code) 69be086e7cSMintz, Yuval { 7039dbc646SYuval Bason struct qed_rdma_events events = p_hwfn->p_rdma_info->events; 7139dbc646SYuval Bason 72be086e7cSMintz, Yuval if (fw_event_code == ROCE_ASYNC_EVENT_DESTROY_QP_DONE) { 73be086e7cSMintz, Yuval u16 icid = 746c9e80eaSMichal Kalderon (u16)le32_to_cpu(data->rdma_data.rdma_destroy_qp_data.cid); 75be086e7cSMintz, Yuval 76be086e7cSMintz, Yuval /* icid release in this async event can occur only if the icid 77be086e7cSMintz, Yuval * was offloaded to the FW. In case it wasn't offloaded this is 78be086e7cSMintz, Yuval * handled in qed_roce_sp_destroy_qp. 79be086e7cSMintz, Yuval */ 80be086e7cSMintz, Yuval qed_roce_free_real_icid(p_hwfn, icid); 81be086e7cSMintz, Yuval } else { 8239dbc646SYuval Bason if (fw_event_code == ROCE_ASYNC_EVENT_SRQ_EMPTY || 8339dbc646SYuval Bason fw_event_code == ROCE_ASYNC_EVENT_SRQ_LIMIT) { 8439dbc646SYuval Bason u16 srq_id = (u16)data->rdma_data.async_handle.lo; 85be086e7cSMintz, Yuval 8639dbc646SYuval Bason events.affiliated_event(events.context, fw_event_code, 8739dbc646SYuval Bason &srq_id); 8839dbc646SYuval Bason } else { 8939dbc646SYuval Bason union rdma_eqe_data rdata = data->rdma_data; 9039dbc646SYuval Bason 9139dbc646SYuval Bason events.affiliated_event(events.context, fw_event_code, 9239dbc646SYuval Bason (void *)&rdata.async_handle); 9339dbc646SYuval Bason } 94be086e7cSMintz, Yuval } 956c9e80eaSMichal Kalderon 966c9e80eaSMichal Kalderon return 0; 9751ff1725SRam Amrani } 9851ff1725SRam Amrani 99898fff12SMichal Kalderon void qed_roce_stop(struct qed_hwfn *p_hwfn) 100898fff12SMichal Kalderon { 101898fff12SMichal Kalderon struct qed_bmap *rcid_map = &p_hwfn->p_rdma_info->real_cid_map; 102898fff12SMichal Kalderon int wait_count = 0; 103898fff12SMichal Kalderon 104898fff12SMichal Kalderon /* when destroying a_RoCE QP the control is returned to the user after 105898fff12SMichal Kalderon * the synchronous part. The asynchronous part may take a little longer. 106898fff12SMichal Kalderon * We delay for a short while if an async destroy QP is still expected. 107898fff12SMichal Kalderon * Beyond the added delay we clear the bitmap anyway. 108898fff12SMichal Kalderon */ 109898fff12SMichal Kalderon while (bitmap_weight(rcid_map->bitmap, rcid_map->max_count)) { 110898fff12SMichal Kalderon msleep(100); 111898fff12SMichal Kalderon if (wait_count++ > 20) { 112898fff12SMichal Kalderon DP_NOTICE(p_hwfn, "cid bitmap wait timed out\n"); 113898fff12SMichal Kalderon break; 114898fff12SMichal Kalderon } 115898fff12SMichal Kalderon } 1166c9e80eaSMichal Kalderon qed_spq_unregister_async_cb(p_hwfn, PROTOCOLID_ROCE); 117898fff12SMichal Kalderon } 118898fff12SMichal Kalderon 119f1093940SRam Amrani static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid, 120f1093940SRam Amrani __le32 *dst_gid) 121f1093940SRam Amrani { 122f1093940SRam Amrani u32 i; 123f1093940SRam Amrani 124f1093940SRam Amrani if (qp->roce_mode == ROCE_V2_IPV4) { 125f1093940SRam Amrani /* The IPv4 addresses shall be aligned to the highest word. 126f1093940SRam Amrani * The lower words must be zero. 127f1093940SRam Amrani */ 128f1093940SRam Amrani memset(src_gid, 0, sizeof(union qed_gid)); 129f1093940SRam Amrani memset(dst_gid, 0, sizeof(union qed_gid)); 130f1093940SRam Amrani src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr); 131f1093940SRam Amrani dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr); 132f1093940SRam Amrani } else { 133f1093940SRam Amrani /* GIDs and IPv6 addresses coincide in location and size */ 134f1093940SRam Amrani for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) { 135f1093940SRam Amrani src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]); 136f1093940SRam Amrani dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]); 137f1093940SRam Amrani } 138f1093940SRam Amrani } 139f1093940SRam Amrani } 140f1093940SRam Amrani 141f1093940SRam Amrani static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode) 142f1093940SRam Amrani { 143f1093940SRam Amrani switch (roce_mode) { 144f1093940SRam Amrani case ROCE_V1: 145d3a31579SNathan Chancellor return PLAIN_ROCE; 146f1093940SRam Amrani case ROCE_V2_IPV4: 147d3a31579SNathan Chancellor return RROCE_IPV4; 148f1093940SRam Amrani case ROCE_V2_IPV6: 149d3a31579SNathan Chancellor return RROCE_IPV6; 150f1093940SRam Amrani default: 151d3a31579SNathan Chancellor return MAX_ROCE_FLAVOR; 152f1093940SRam Amrani } 153f1093940SRam Amrani } 154f1093940SRam Amrani 155bf774d14SYueHaibing static void qed_roce_free_cid_pair(struct qed_hwfn *p_hwfn, u16 cid) 156be086e7cSMintz, Yuval { 157be086e7cSMintz, Yuval spin_lock_bh(&p_hwfn->p_rdma_info->lock); 158be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid); 159be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid + 1); 160be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 161be086e7cSMintz, Yuval } 162be086e7cSMintz, Yuval 163b71b9afdSKalderon, Michal int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid) 164f1093940SRam Amrani { 165f1093940SRam Amrani struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 166f1093940SRam Amrani u32 responder_icid; 167f1093940SRam Amrani u32 requester_icid; 168f1093940SRam Amrani int rc; 169f1093940SRam Amrani 170f1093940SRam Amrani spin_lock_bh(&p_hwfn->p_rdma_info->lock); 171f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 172f1093940SRam Amrani &responder_icid); 173f1093940SRam Amrani if (rc) { 174f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 175f1093940SRam Amrani return rc; 176f1093940SRam Amrani } 177f1093940SRam Amrani 178f1093940SRam Amrani rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map, 179f1093940SRam Amrani &requester_icid); 180f1093940SRam Amrani 181f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 182f1093940SRam Amrani if (rc) 183f1093940SRam Amrani goto err; 184f1093940SRam Amrani 185f1093940SRam Amrani /* the two icid's should be adjacent */ 186f1093940SRam Amrani if ((requester_icid - responder_icid) != 1) { 187f1093940SRam Amrani DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n"); 188f1093940SRam Amrani rc = -EINVAL; 189f1093940SRam Amrani goto err; 190f1093940SRam Amrani } 191f1093940SRam Amrani 192f1093940SRam Amrani responder_icid += qed_cxt_get_proto_cid_start(p_hwfn, 193f1093940SRam Amrani p_rdma_info->proto); 194f1093940SRam Amrani requester_icid += qed_cxt_get_proto_cid_start(p_hwfn, 195f1093940SRam Amrani p_rdma_info->proto); 196f1093940SRam Amrani 197f1093940SRam Amrani /* If these icids require a new ILT line allocate DMA-able context for 198f1093940SRam Amrani * an ILT page 199f1093940SRam Amrani */ 200f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid); 201f1093940SRam Amrani if (rc) 202f1093940SRam Amrani goto err; 203f1093940SRam Amrani 204f1093940SRam Amrani rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid); 205f1093940SRam Amrani if (rc) 206f1093940SRam Amrani goto err; 207f1093940SRam Amrani 208f1093940SRam Amrani *cid = (u16)responder_icid; 209f1093940SRam Amrani return rc; 210f1093940SRam Amrani 211f1093940SRam Amrani err: 212f1093940SRam Amrani spin_lock_bh(&p_rdma_info->lock); 213f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid); 214f1093940SRam Amrani qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid); 215f1093940SRam Amrani 216f1093940SRam Amrani spin_unlock_bh(&p_rdma_info->lock); 217f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 218f1093940SRam Amrani "Allocate CID - failed, rc = %d\n", rc); 219f1093940SRam Amrani return rc; 220f1093940SRam Amrani } 221f1093940SRam Amrani 222be086e7cSMintz, Yuval static void qed_roce_set_real_cid(struct qed_hwfn *p_hwfn, u32 cid) 223be086e7cSMintz, Yuval { 224be086e7cSMintz, Yuval spin_lock_bh(&p_hwfn->p_rdma_info->lock); 225be086e7cSMintz, Yuval qed_bmap_set_id(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, cid); 226be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 227be086e7cSMintz, Yuval } 228be086e7cSMintz, Yuval 22961be82b0SDenis Bolotin static u8 qed_roce_get_qp_tc(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 23061be82b0SDenis Bolotin { 23161be82b0SDenis Bolotin u8 pri, tc = 0; 23261be82b0SDenis Bolotin 23361be82b0SDenis Bolotin if (qp->vlan_id) { 23461be82b0SDenis Bolotin pri = (qp->vlan_id & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 23561be82b0SDenis Bolotin tc = qed_dcbx_get_priority_tc(p_hwfn, pri); 23661be82b0SDenis Bolotin } 23761be82b0SDenis Bolotin 23861be82b0SDenis Bolotin DP_VERBOSE(p_hwfn, QED_MSG_SP, 23961be82b0SDenis Bolotin "qp icid %u tc: %u (vlan priority %s)\n", 24061be82b0SDenis Bolotin qp->icid, tc, qp->vlan_id ? "enabled" : "disabled"); 24161be82b0SDenis Bolotin 24261be82b0SDenis Bolotin return tc; 24361be82b0SDenis Bolotin } 24461be82b0SDenis Bolotin 245f1093940SRam Amrani static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn, 246f1093940SRam Amrani struct qed_rdma_qp *qp) 247f1093940SRam Amrani { 248f1093940SRam Amrani struct roce_create_qp_resp_ramrod_data *p_ramrod; 24961be82b0SDenis Bolotin u16 regular_latency_queue, low_latency_queue; 250f1093940SRam Amrani struct qed_sp_init_data init_data; 251f1093940SRam Amrani enum roce_flavor roce_flavor; 252f1093940SRam Amrani struct qed_spq_entry *p_ent; 253be086e7cSMintz, Yuval enum protocol_type proto; 254f1093940SRam Amrani int rc; 25561be82b0SDenis Bolotin u8 tc; 256f1093940SRam Amrani 257f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 258f1093940SRam Amrani 259f1093940SRam Amrani /* Allocate DMA-able memory for IRQ */ 260f1093940SRam Amrani qp->irq_num_pages = 1; 261f1093940SRam Amrani qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 262f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 263f1093940SRam Amrani &qp->irq_phys_addr, GFP_KERNEL); 264f1093940SRam Amrani if (!qp->irq) { 265f1093940SRam Amrani rc = -ENOMEM; 266f1093940SRam Amrani DP_NOTICE(p_hwfn, 267f1093940SRam Amrani "qed create responder failed: cannot allocate memory (irq). rc = %d\n", 268f1093940SRam Amrani rc); 269f1093940SRam Amrani return rc; 270f1093940SRam Amrani } 271f1093940SRam Amrani 272f1093940SRam Amrani /* Get SPQ entry */ 273f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 274f1093940SRam Amrani init_data.cid = qp->icid; 275f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 276f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 277f1093940SRam Amrani 278f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP, 279f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 280f1093940SRam Amrani if (rc) 281f1093940SRam Amrani goto err; 282f1093940SRam Amrani 283f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_resp; 284f1093940SRam Amrani 285f1093940SRam Amrani p_ramrod->flags = 0; 286f1093940SRam Amrani 287f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 288f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 289f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 290f1093940SRam Amrani 291f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 292f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 293f1093940SRam Amrani qp->incoming_rdma_read_en); 294f1093940SRam Amrani 295f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 296f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 297f1093940SRam Amrani qp->incoming_rdma_write_en); 298f1093940SRam Amrani 299f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 300f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN, 301f1093940SRam Amrani qp->incoming_atomic_en); 302f1093940SRam Amrani 303f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 304f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 305f1093940SRam Amrani qp->e2e_flow_control_en); 306f1093940SRam Amrani 307f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 308f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq); 309f1093940SRam Amrani 310f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 311f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN, 312f1093940SRam Amrani qp->fmr_and_reserved_lkey); 313f1093940SRam Amrani 314f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 315f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 316f1093940SRam Amrani qp->min_rnr_nak_timer); 317f1093940SRam Amrani 318f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 319f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 320f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 321f1093940SRam Amrani p_ramrod->irq_num_pages = qp->irq_num_pages; 322f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 323f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 324f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 325f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 326f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn); 327f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 328f1093940SRam Amrani p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages); 329f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr); 330f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr); 331f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 332f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 333f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 334f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 335f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 336f1093940SRam Amrani p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 337f1093940SRam Amrani qp->rq_cq_id); 338f1093940SRam Amrani 33961be82b0SDenis Bolotin tc = qed_roce_get_qp_tc(p_hwfn, qp); 34061be82b0SDenis Bolotin regular_latency_queue = qed_get_cm_pq_idx_ofld_mtc(p_hwfn, tc); 34161be82b0SDenis Bolotin low_latency_queue = qed_get_cm_pq_idx_llt_mtc(p_hwfn, tc); 34261be82b0SDenis Bolotin DP_VERBOSE(p_hwfn, QED_MSG_SP, 34361be82b0SDenis Bolotin "qp icid %u pqs: regular_latency %u low_latency %u\n", 34461be82b0SDenis Bolotin qp->icid, regular_latency_queue - CM_TX_PQ_BASE, 34561be82b0SDenis Bolotin low_latency_queue - CM_TX_PQ_BASE); 346be086e7cSMintz, Yuval p_ramrod->regular_latency_phy_queue = 347be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 348be086e7cSMintz, Yuval p_ramrod->low_latency_phy_queue = 34961be82b0SDenis Bolotin cpu_to_le16(low_latency_queue); 350be086e7cSMintz, Yuval 351f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 352f1093940SRam Amrani 353f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 354f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 355f1093940SRam Amrani 356f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 357f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 358f1093940SRam Amrani p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id); 359f1093940SRam Amrani p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid); 360f1093940SRam Amrani 361f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 362f1093940SRam Amrani qp->stats_queue; 363f1093940SRam Amrani 364f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 365f1093940SRam Amrani if (rc) 366f1093940SRam Amrani goto err; 367f1093940SRam Amrani 368f1093940SRam Amrani qp->resp_offloaded = true; 369be086e7cSMintz, Yuval qp->cq_prod = 0; 370be086e7cSMintz, Yuval 371be086e7cSMintz, Yuval proto = p_hwfn->p_rdma_info->proto; 372be086e7cSMintz, Yuval qed_roce_set_real_cid(p_hwfn, qp->icid - 373be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, proto)); 374f1093940SRam Amrani 375f1093940SRam Amrani return rc; 376f1093940SRam Amrani 377f1093940SRam Amrani err: 378f1093940SRam Amrani DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc); 379f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 380f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 381f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 382f1093940SRam Amrani 383f1093940SRam Amrani return rc; 384f1093940SRam Amrani } 385f1093940SRam Amrani 386f1093940SRam Amrani static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn, 387f1093940SRam Amrani struct qed_rdma_qp *qp) 388f1093940SRam Amrani { 389f1093940SRam Amrani struct roce_create_qp_req_ramrod_data *p_ramrod; 39061be82b0SDenis Bolotin u16 regular_latency_queue, low_latency_queue; 391f1093940SRam Amrani struct qed_sp_init_data init_data; 392f1093940SRam Amrani enum roce_flavor roce_flavor; 393f1093940SRam Amrani struct qed_spq_entry *p_ent; 394be086e7cSMintz, Yuval enum protocol_type proto; 395f1093940SRam Amrani int rc; 39661be82b0SDenis Bolotin u8 tc; 397f1093940SRam Amrani 398f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 399f1093940SRam Amrani 400f1093940SRam Amrani /* Allocate DMA-able memory for ORQ */ 401f1093940SRam Amrani qp->orq_num_pages = 1; 402f1093940SRam Amrani qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 403f1093940SRam Amrani RDMA_RING_PAGE_SIZE, 404f1093940SRam Amrani &qp->orq_phys_addr, GFP_KERNEL); 405f1093940SRam Amrani if (!qp->orq) { 406f1093940SRam Amrani rc = -ENOMEM; 407f1093940SRam Amrani DP_NOTICE(p_hwfn, 408f1093940SRam Amrani "qed create requester failed: cannot allocate memory (orq). rc = %d\n", 409f1093940SRam Amrani rc); 410f1093940SRam Amrani return rc; 411f1093940SRam Amrani } 412f1093940SRam Amrani 413f1093940SRam Amrani /* Get SPQ entry */ 414f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 415f1093940SRam Amrani init_data.cid = qp->icid + 1; 416f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 417f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 418f1093940SRam Amrani 419f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 420f1093940SRam Amrani ROCE_RAMROD_CREATE_QP, 421f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 422f1093940SRam Amrani if (rc) 423f1093940SRam Amrani goto err; 424f1093940SRam Amrani 425f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_create_qp_req; 426f1093940SRam Amrani 427f1093940SRam Amrani p_ramrod->flags = 0; 428f1093940SRam Amrani 429f1093940SRam Amrani roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode); 430f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 431f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor); 432f1093940SRam Amrani 433f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 434f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN, 435f1093940SRam Amrani qp->fmr_and_reserved_lkey); 436f1093940SRam Amrani 437f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 438f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all); 439f1093940SRam Amrani 440f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 441f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 442f1093940SRam Amrani 443f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 444f1093940SRam Amrani ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 445f1093940SRam Amrani qp->rnr_retry_cnt); 446f1093940SRam Amrani 447f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 448f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 449f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 450f1093940SRam Amrani p_ramrod->orq_num_pages = qp->orq_num_pages; 451f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 452f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 453f1093940SRam Amrani p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp); 454f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 455f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 456f1093940SRam Amrani p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn); 457f1093940SRam Amrani p_ramrod->pd = cpu_to_le16(qp->pd); 458f1093940SRam Amrani p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages); 459f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr); 460f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr); 461f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 462f1093940SRam Amrani p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi); 463f1093940SRam Amrani p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo); 464f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi); 465f1093940SRam Amrani p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo); 466be086e7cSMintz, Yuval p_ramrod->cq_cid = 467be086e7cSMintz, Yuval cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | qp->sq_cq_id); 468f1093940SRam Amrani 46961be82b0SDenis Bolotin tc = qed_roce_get_qp_tc(p_hwfn, qp); 47061be82b0SDenis Bolotin regular_latency_queue = qed_get_cm_pq_idx_ofld_mtc(p_hwfn, tc); 47161be82b0SDenis Bolotin low_latency_queue = qed_get_cm_pq_idx_llt_mtc(p_hwfn, tc); 47261be82b0SDenis Bolotin DP_VERBOSE(p_hwfn, QED_MSG_SP, 47361be82b0SDenis Bolotin "qp icid %u pqs: regular_latency %u low_latency %u\n", 47461be82b0SDenis Bolotin qp->icid, regular_latency_queue - CM_TX_PQ_BASE, 47561be82b0SDenis Bolotin low_latency_queue - CM_TX_PQ_BASE); 476be086e7cSMintz, Yuval p_ramrod->regular_latency_phy_queue = 477be086e7cSMintz, Yuval cpu_to_le16(regular_latency_queue); 478be086e7cSMintz, Yuval p_ramrod->low_latency_phy_queue = 47961be82b0SDenis Bolotin cpu_to_le16(low_latency_queue); 480be086e7cSMintz, Yuval 481f1093940SRam Amrani p_ramrod->dpi = cpu_to_le16(qp->dpi); 482f1093940SRam Amrani 483f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr); 484f1093940SRam Amrani qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr); 485f1093940SRam Amrani 486f1093940SRam Amrani p_ramrod->udp_src_port = qp->udp_src_port; 487f1093940SRam Amrani p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id); 488f1093940SRam Amrani p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) + 489f1093940SRam Amrani qp->stats_queue; 490f1093940SRam Amrani 491f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 492f1093940SRam Amrani if (rc) 493f1093940SRam Amrani goto err; 494f1093940SRam Amrani 495f1093940SRam Amrani qp->req_offloaded = true; 496be086e7cSMintz, Yuval proto = p_hwfn->p_rdma_info->proto; 497be086e7cSMintz, Yuval qed_roce_set_real_cid(p_hwfn, 498be086e7cSMintz, Yuval qp->icid + 1 - 499be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, proto)); 500f1093940SRam Amrani 501f1093940SRam Amrani return rc; 502f1093940SRam Amrani 503f1093940SRam Amrani err: 504f1093940SRam Amrani DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc); 505f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 506f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 507f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 508f1093940SRam Amrani return rc; 509f1093940SRam Amrani } 510f1093940SRam Amrani 511f1093940SRam Amrani static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn, 512f1093940SRam Amrani struct qed_rdma_qp *qp, 513f1093940SRam Amrani bool move_to_err, u32 modify_flags) 514f1093940SRam Amrani { 515f1093940SRam Amrani struct roce_modify_qp_resp_ramrod_data *p_ramrod; 516f1093940SRam Amrani struct qed_sp_init_data init_data; 517f1093940SRam Amrani struct qed_spq_entry *p_ent; 518f1093940SRam Amrani int rc; 519f1093940SRam Amrani 520f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 521f1093940SRam Amrani 522f1093940SRam Amrani if (move_to_err && !qp->resp_offloaded) 523f1093940SRam Amrani return 0; 524f1093940SRam Amrani 525f1093940SRam Amrani /* Get SPQ entry */ 526f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 527f1093940SRam Amrani init_data.cid = qp->icid; 528f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 529f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 530f1093940SRam Amrani 531f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 532f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 533f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 534f1093940SRam Amrani if (rc) { 535f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 536f1093940SRam Amrani return rc; 537f1093940SRam Amrani } 538f1093940SRam Amrani 539f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_resp; 540f1093940SRam Amrani 541f1093940SRam Amrani p_ramrod->flags = 0; 542f1093940SRam Amrani 543f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 544f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 545f1093940SRam Amrani 546f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 547f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN, 548f1093940SRam Amrani qp->incoming_rdma_read_en); 549f1093940SRam Amrani 550f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 551f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN, 552f1093940SRam Amrani qp->incoming_rdma_write_en); 553f1093940SRam Amrani 554f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 555f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN, 556f1093940SRam Amrani qp->incoming_atomic_en); 557f1093940SRam Amrani 558f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 559f1093940SRam Amrani ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN, 560f1093940SRam Amrani qp->e2e_flow_control_en); 561f1093940SRam Amrani 562f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 563f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG, 564f1093940SRam Amrani GET_FIELD(modify_flags, 565f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)); 566f1093940SRam Amrani 567f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 568f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG, 569f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 570f1093940SRam Amrani 571f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 572f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG, 573f1093940SRam Amrani GET_FIELD(modify_flags, 574f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 575f1093940SRam Amrani 576f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 577f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG, 578f1093940SRam Amrani GET_FIELD(modify_flags, 579f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)); 580f1093940SRam Amrani 581f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 582f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG, 583f1093940SRam Amrani GET_FIELD(modify_flags, 584f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)); 585f1093940SRam Amrani 586f1093940SRam Amrani p_ramrod->fields = 0; 587f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 588f1093940SRam Amrani ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER, 589f1093940SRam Amrani qp->min_rnr_nak_timer); 590f1093940SRam Amrani 591f1093940SRam Amrani p_ramrod->max_ird = qp->max_rd_atomic_resp; 592f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 593f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 594f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 595f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 596f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 597f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 598f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 599f1093940SRam Amrani 600f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc); 601f1093940SRam Amrani return rc; 602f1093940SRam Amrani } 603f1093940SRam Amrani 604f1093940SRam Amrani static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn, 605f1093940SRam Amrani struct qed_rdma_qp *qp, 606f1093940SRam Amrani bool move_to_sqd, 607f1093940SRam Amrani bool move_to_err, u32 modify_flags) 608f1093940SRam Amrani { 609f1093940SRam Amrani struct roce_modify_qp_req_ramrod_data *p_ramrod; 610f1093940SRam Amrani struct qed_sp_init_data init_data; 611f1093940SRam Amrani struct qed_spq_entry *p_ent; 612f1093940SRam Amrani int rc; 613f1093940SRam Amrani 614f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 615f1093940SRam Amrani 616f1093940SRam Amrani if (move_to_err && !(qp->req_offloaded)) 617f1093940SRam Amrani return 0; 618f1093940SRam Amrani 619f1093940SRam Amrani /* Get SPQ entry */ 620f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 621f1093940SRam Amrani init_data.cid = qp->icid + 1; 622f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 623f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 624f1093940SRam Amrani 625f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 626f1093940SRam Amrani ROCE_EVENT_MODIFY_QP, 627f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 628f1093940SRam Amrani if (rc) { 629f1093940SRam Amrani DP_NOTICE(p_hwfn, "rc = %d\n", rc); 630f1093940SRam Amrani return rc; 631f1093940SRam Amrani } 632f1093940SRam Amrani 633f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_modify_qp_req; 634f1093940SRam Amrani 635f1093940SRam Amrani p_ramrod->flags = 0; 636f1093940SRam Amrani 637f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 638f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err); 639f1093940SRam Amrani 640f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 641f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd); 642f1093940SRam Amrani 643f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 644f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY, 645f1093940SRam Amrani qp->sqd_async); 646f1093940SRam Amrani 647f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 648f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG, 649f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)); 650f1093940SRam Amrani 651f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 652f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG, 653f1093940SRam Amrani GET_FIELD(modify_flags, 654f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)); 655f1093940SRam Amrani 656f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 657f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG, 658f1093940SRam Amrani GET_FIELD(modify_flags, 659f1093940SRam Amrani QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)); 660f1093940SRam Amrani 661f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 662f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG, 663f1093940SRam Amrani GET_FIELD(modify_flags, 664f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)); 665f1093940SRam Amrani 666f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 667f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG, 668f1093940SRam Amrani GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)); 669f1093940SRam Amrani 670f1093940SRam Amrani SET_FIELD(p_ramrod->flags, 671f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG, 672f1093940SRam Amrani GET_FIELD(modify_flags, 673f1093940SRam Amrani QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)); 674f1093940SRam Amrani 675f1093940SRam Amrani p_ramrod->fields = 0; 676f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 677f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt); 678f1093940SRam Amrani 679f1093940SRam Amrani SET_FIELD(p_ramrod->fields, 680f1093940SRam Amrani ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT, 681f1093940SRam Amrani qp->rnr_retry_cnt); 682f1093940SRam Amrani 683f1093940SRam Amrani p_ramrod->max_ord = qp->max_rd_atomic_req; 684f1093940SRam Amrani p_ramrod->traffic_class = qp->traffic_class_tos; 685f1093940SRam Amrani p_ramrod->hop_limit = qp->hop_limit_ttl; 686f1093940SRam Amrani p_ramrod->p_key = cpu_to_le16(qp->pkey); 687f1093940SRam Amrani p_ramrod->flow_label = cpu_to_le32(qp->flow_label); 688f1093940SRam Amrani p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout); 689f1093940SRam Amrani p_ramrod->mtu = cpu_to_le16(qp->mtu); 690f1093940SRam Amrani qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid); 691f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 692f1093940SRam Amrani 693f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc); 694f1093940SRam Amrani return rc; 695f1093940SRam Amrani } 696f1093940SRam Amrani 697f1093940SRam Amrani static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn, 698f1093940SRam Amrani struct qed_rdma_qp *qp, 699be086e7cSMintz, Yuval u32 *cq_prod) 700f1093940SRam Amrani { 701f1093940SRam Amrani struct roce_destroy_qp_resp_output_params *p_ramrod_res; 702f1093940SRam Amrani struct roce_destroy_qp_resp_ramrod_data *p_ramrod; 703f1093940SRam Amrani struct qed_sp_init_data init_data; 704f1093940SRam Amrani struct qed_spq_entry *p_ent; 705f1093940SRam Amrani dma_addr_t ramrod_res_phys; 706f1093940SRam Amrani int rc; 707f1093940SRam Amrani 708f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 709be086e7cSMintz, Yuval *cq_prod = qp->cq_prod; 710be086e7cSMintz, Yuval 711be086e7cSMintz, Yuval if (!qp->resp_offloaded) { 712be086e7cSMintz, Yuval /* If a responder was never offload, we need to free the cids 713be086e7cSMintz, Yuval * allocated in create_qp as a FW async event will never arrive 714be086e7cSMintz, Yuval */ 715be086e7cSMintz, Yuval u32 cid; 716be086e7cSMintz, Yuval 717be086e7cSMintz, Yuval cid = qp->icid - 718be086e7cSMintz, Yuval qed_cxt_get_proto_cid_start(p_hwfn, 719be086e7cSMintz, Yuval p_hwfn->p_rdma_info->proto); 720be086e7cSMintz, Yuval qed_roce_free_cid_pair(p_hwfn, (u16)cid); 721be086e7cSMintz, Yuval 722f1093940SRam Amrani return 0; 723be086e7cSMintz, Yuval } 724f1093940SRam Amrani 725f1093940SRam Amrani /* Get SPQ entry */ 726f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 727f1093940SRam Amrani init_data.cid = qp->icid; 728f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 729f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 730f1093940SRam Amrani 731f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, 732f1093940SRam Amrani ROCE_RAMROD_DESTROY_QP, 733f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 734f1093940SRam Amrani if (rc) 735f1093940SRam Amrani return rc; 736f1093940SRam Amrani 737f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp; 738f1093940SRam Amrani 739f1093940SRam Amrani p_ramrod_res = (struct roce_destroy_qp_resp_output_params *) 740f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 741f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 742f1093940SRam Amrani 743f1093940SRam Amrani if (!p_ramrod_res) { 744f1093940SRam Amrani rc = -ENOMEM; 745f1093940SRam Amrani DP_NOTICE(p_hwfn, 746f1093940SRam Amrani "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n", 747f1093940SRam Amrani rc); 748fb5e7438SDenis Bolotin qed_sp_destroy_request(p_hwfn, p_ent); 749f1093940SRam Amrani return rc; 750f1093940SRam Amrani } 751f1093940SRam Amrani 752f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 753f1093940SRam Amrani 754f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 755f1093940SRam Amrani if (rc) 756f1093940SRam Amrani goto err; 757f1093940SRam Amrani 758be086e7cSMintz, Yuval *cq_prod = le32_to_cpu(p_ramrod_res->cq_prod); 759be086e7cSMintz, Yuval qp->cq_prod = *cq_prod; 760f1093940SRam Amrani 761f1093940SRam Amrani /* Free IRQ - only if ramrod succeeded, in case FW is still using it */ 762f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 763f1093940SRam Amrani qp->irq_num_pages * RDMA_RING_PAGE_SIZE, 764f1093940SRam Amrani qp->irq, qp->irq_phys_addr); 765f1093940SRam Amrani 766f1093940SRam Amrani qp->resp_offloaded = false; 767f1093940SRam Amrani 768f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc); 769f1093940SRam Amrani 770f1093940SRam Amrani err: 771f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 772f1093940SRam Amrani sizeof(struct roce_destroy_qp_resp_output_params), 773f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 774f1093940SRam Amrani 775f1093940SRam Amrani return rc; 776f1093940SRam Amrani } 777f1093940SRam Amrani 778f1093940SRam Amrani static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn, 779d52c89f1SMichal Kalderon struct qed_rdma_qp *qp) 780f1093940SRam Amrani { 781f1093940SRam Amrani struct roce_destroy_qp_req_output_params *p_ramrod_res; 782f1093940SRam Amrani struct roce_destroy_qp_req_ramrod_data *p_ramrod; 783f1093940SRam Amrani struct qed_sp_init_data init_data; 784f1093940SRam Amrani struct qed_spq_entry *p_ent; 785f1093940SRam Amrani dma_addr_t ramrod_res_phys; 786f1093940SRam Amrani int rc = -ENOMEM; 787f1093940SRam Amrani 788f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 789f1093940SRam Amrani 790f1093940SRam Amrani if (!qp->req_offloaded) 791f1093940SRam Amrani return 0; 792f1093940SRam Amrani 793f1093940SRam Amrani p_ramrod_res = (struct roce_destroy_qp_req_output_params *) 794f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 795f1093940SRam Amrani sizeof(*p_ramrod_res), 796f1093940SRam Amrani &ramrod_res_phys, GFP_KERNEL); 797f1093940SRam Amrani if (!p_ramrod_res) { 798f1093940SRam Amrani DP_NOTICE(p_hwfn, 799f1093940SRam Amrani "qed destroy requester failed: cannot allocate memory (ramrod)\n"); 800f1093940SRam Amrani return rc; 801f1093940SRam Amrani } 802f1093940SRam Amrani 803f1093940SRam Amrani /* Get SPQ entry */ 804f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 805f1093940SRam Amrani init_data.cid = qp->icid + 1; 806f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 807f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 808f1093940SRam Amrani 809f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP, 810f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 811f1093940SRam Amrani if (rc) 812f1093940SRam Amrani goto err; 813f1093940SRam Amrani 814f1093940SRam Amrani p_ramrod = &p_ent->ramrod.roce_destroy_qp_req; 815f1093940SRam Amrani DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 816f1093940SRam Amrani 817f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 818f1093940SRam Amrani if (rc) 819f1093940SRam Amrani goto err; 820f1093940SRam Amrani 821f1093940SRam Amrani 822f1093940SRam Amrani /* Free ORQ - only if ramrod succeeded, in case FW is still using it */ 823f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, 824f1093940SRam Amrani qp->orq_num_pages * RDMA_RING_PAGE_SIZE, 825f1093940SRam Amrani qp->orq, qp->orq_phys_addr); 826f1093940SRam Amrani 827f1093940SRam Amrani qp->req_offloaded = false; 828f1093940SRam Amrani 829f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc); 830f1093940SRam Amrani 831f1093940SRam Amrani err: 832f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res), 833f1093940SRam Amrani p_ramrod_res, ramrod_res_phys); 834f1093940SRam Amrani 835f1093940SRam Amrani return rc; 836f1093940SRam Amrani } 837f1093940SRam Amrani 838b71b9afdSKalderon, Michal int qed_roce_query_qp(struct qed_hwfn *p_hwfn, 839f1093940SRam Amrani struct qed_rdma_qp *qp, 840f1093940SRam Amrani struct qed_rdma_query_qp_out_params *out_params) 841f1093940SRam Amrani { 842f1093940SRam Amrani struct roce_query_qp_resp_output_params *p_resp_ramrod_res; 843f1093940SRam Amrani struct roce_query_qp_req_output_params *p_req_ramrod_res; 844f1093940SRam Amrani struct roce_query_qp_resp_ramrod_data *p_resp_ramrod; 845f1093940SRam Amrani struct roce_query_qp_req_ramrod_data *p_req_ramrod; 846f1093940SRam Amrani struct qed_sp_init_data init_data; 847f1093940SRam Amrani dma_addr_t resp_ramrod_res_phys; 848f1093940SRam Amrani dma_addr_t req_ramrod_res_phys; 849f1093940SRam Amrani struct qed_spq_entry *p_ent; 850f1093940SRam Amrani bool rq_err_state; 851f1093940SRam Amrani bool sq_err_state; 852f1093940SRam Amrani bool sq_draining; 853f1093940SRam Amrani int rc = -ENOMEM; 854f1093940SRam Amrani 855f1093940SRam Amrani if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) { 856f1093940SRam Amrani /* We can't send ramrod to the fw since this qp wasn't offloaded 857f1093940SRam Amrani * to the fw yet 858f1093940SRam Amrani */ 859f1093940SRam Amrani out_params->draining = false; 860f1093940SRam Amrani out_params->rq_psn = qp->rq_psn; 861f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 862f1093940SRam Amrani out_params->state = qp->cur_state; 863f1093940SRam Amrani 864f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n"); 865f1093940SRam Amrani return 0; 866f1093940SRam Amrani } 867f1093940SRam Amrani 868f1093940SRam Amrani if (!(qp->resp_offloaded)) { 869f1093940SRam Amrani DP_NOTICE(p_hwfn, 870df80b8fbSColin Ian King "The responder's qp should be offloaded before requester's\n"); 871f1093940SRam Amrani return -EINVAL; 872f1093940SRam Amrani } 873f1093940SRam Amrani 874f1093940SRam Amrani /* Send a query responder ramrod to FW to get RQ-PSN and state */ 875f1093940SRam Amrani p_resp_ramrod_res = (struct roce_query_qp_resp_output_params *) 876f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 877f1093940SRam Amrani sizeof(*p_resp_ramrod_res), 878f1093940SRam Amrani &resp_ramrod_res_phys, GFP_KERNEL); 879f1093940SRam Amrani if (!p_resp_ramrod_res) { 880f1093940SRam Amrani DP_NOTICE(p_hwfn, 881f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 882f1093940SRam Amrani return rc; 883f1093940SRam Amrani } 884f1093940SRam Amrani 885f1093940SRam Amrani /* Get SPQ entry */ 886f1093940SRam Amrani memset(&init_data, 0, sizeof(init_data)); 887f1093940SRam Amrani init_data.cid = qp->icid; 888f1093940SRam Amrani init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 889f1093940SRam Amrani init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 890f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 891f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 892f1093940SRam Amrani if (rc) 893f1093940SRam Amrani goto err_resp; 894f1093940SRam Amrani 895f1093940SRam Amrani p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp; 896f1093940SRam Amrani DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys); 897f1093940SRam Amrani 898f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 899f1093940SRam Amrani if (rc) 900f1093940SRam Amrani goto err_resp; 901f1093940SRam Amrani 902f1093940SRam Amrani out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn); 9030500a70dSMichal Kalderon rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->flags), 904f1093940SRam Amrani ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG); 905f1093940SRam Amrani 906c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 907c5212b94SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 908c5212b94SRam Amrani 909f1093940SRam Amrani if (!(qp->req_offloaded)) { 910f1093940SRam Amrani /* Don't send query qp for the requester */ 911f1093940SRam Amrani out_params->sq_psn = qp->sq_psn; 912f1093940SRam Amrani out_params->draining = false; 913f1093940SRam Amrani 914f1093940SRam Amrani if (rq_err_state) 915f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 916f1093940SRam Amrani 917f1093940SRam Amrani out_params->state = qp->cur_state; 918f1093940SRam Amrani 919f1093940SRam Amrani return 0; 920f1093940SRam Amrani } 921f1093940SRam Amrani 922f1093940SRam Amrani /* Send a query requester ramrod to FW to get SQ-PSN and state */ 923f1093940SRam Amrani p_req_ramrod_res = (struct roce_query_qp_req_output_params *) 924f1093940SRam Amrani dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 925f1093940SRam Amrani sizeof(*p_req_ramrod_res), 926f1093940SRam Amrani &req_ramrod_res_phys, 927f1093940SRam Amrani GFP_KERNEL); 928f1093940SRam Amrani if (!p_req_ramrod_res) { 929f1093940SRam Amrani rc = -ENOMEM; 930f1093940SRam Amrani DP_NOTICE(p_hwfn, 931f1093940SRam Amrani "qed query qp failed: cannot allocate memory (ramrod)\n"); 932f1093940SRam Amrani return rc; 933f1093940SRam Amrani } 934f1093940SRam Amrani 935f1093940SRam Amrani /* Get SPQ entry */ 936f1093940SRam Amrani init_data.cid = qp->icid + 1; 937f1093940SRam Amrani rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP, 938f1093940SRam Amrani PROTOCOLID_ROCE, &init_data); 939f1093940SRam Amrani if (rc) 940f1093940SRam Amrani goto err_req; 941f1093940SRam Amrani 942f1093940SRam Amrani p_req_ramrod = &p_ent->ramrod.roce_query_qp_req; 943f1093940SRam Amrani DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys); 944f1093940SRam Amrani 945f1093940SRam Amrani rc = qed_spq_post(p_hwfn, p_ent, NULL); 946f1093940SRam Amrani if (rc) 947f1093940SRam Amrani goto err_req; 948f1093940SRam Amrani 949f1093940SRam Amrani out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn); 950f1093940SRam Amrani sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 951f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG); 952f1093940SRam Amrani sq_draining = 953f1093940SRam Amrani GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags), 954f1093940SRam Amrani ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG); 955f1093940SRam Amrani 956c5212b94SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 957c5212b94SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 958c5212b94SRam Amrani 959f1093940SRam Amrani out_params->draining = false; 960f1093940SRam Amrani 961be086e7cSMintz, Yuval if (rq_err_state || sq_err_state) 962f1093940SRam Amrani qp->cur_state = QED_ROCE_QP_STATE_ERR; 963f1093940SRam Amrani else if (sq_draining) 964f1093940SRam Amrani out_params->draining = true; 965f1093940SRam Amrani out_params->state = qp->cur_state; 966f1093940SRam Amrani 967f1093940SRam Amrani return 0; 968f1093940SRam Amrani 969f1093940SRam Amrani err_req: 970f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res), 971f1093940SRam Amrani p_req_ramrod_res, req_ramrod_res_phys); 972f1093940SRam Amrani return rc; 973f1093940SRam Amrani err_resp: 974f1093940SRam Amrani dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res), 975f1093940SRam Amrani p_resp_ramrod_res, resp_ramrod_res_phys); 976f1093940SRam Amrani return rc; 977f1093940SRam Amrani } 978f1093940SRam Amrani 979b71b9afdSKalderon, Michal int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp) 980f1093940SRam Amrani { 981be086e7cSMintz, Yuval u32 cq_prod; 982f1093940SRam Amrani int rc; 983f1093940SRam Amrani 984f1093940SRam Amrani /* Destroys the specified QP */ 985f1093940SRam Amrani if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) && 986f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_ERR) && 987f1093940SRam Amrani (qp->cur_state != QED_ROCE_QP_STATE_INIT)) { 988f1093940SRam Amrani DP_NOTICE(p_hwfn, 989f1093940SRam Amrani "QP must be in error, reset or init state before destroying it\n"); 990f1093940SRam Amrani return -EINVAL; 991f1093940SRam Amrani } 992f1093940SRam Amrani 993300c0d7cSRam Amrani if (qp->cur_state != QED_ROCE_QP_STATE_RESET) { 994300c0d7cSRam Amrani rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, 995be086e7cSMintz, Yuval &cq_prod); 996f1093940SRam Amrani if (rc) 997f1093940SRam Amrani return rc; 998f1093940SRam Amrani 999f1093940SRam Amrani /* Send destroy requester ramrod */ 1000d52c89f1SMichal Kalderon rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp); 1001f1093940SRam Amrani if (rc) 1002f1093940SRam Amrani return rc; 1003300c0d7cSRam Amrani } 1004f1093940SRam Amrani 1005f1093940SRam Amrani return 0; 1006f1093940SRam Amrani } 1007f1093940SRam Amrani 1008b71b9afdSKalderon, Michal int qed_roce_modify_qp(struct qed_hwfn *p_hwfn, 1009f1093940SRam Amrani struct qed_rdma_qp *qp, 1010f1093940SRam Amrani enum qed_roce_qp_state prev_state, 1011f1093940SRam Amrani struct qed_rdma_modify_qp_in_params *params) 1012f1093940SRam Amrani { 1013f1093940SRam Amrani int rc = 0; 1014f1093940SRam Amrani 1015f1093940SRam Amrani /* Perform additional operations according to the current state and the 1016f1093940SRam Amrani * next state 1017f1093940SRam Amrani */ 1018f1093940SRam Amrani if (((prev_state == QED_ROCE_QP_STATE_INIT) || 1019f1093940SRam Amrani (prev_state == QED_ROCE_QP_STATE_RESET)) && 1020f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTR)) { 1021f1093940SRam Amrani /* Init->RTR or Reset->RTR */ 1022f1093940SRam Amrani rc = qed_roce_sp_create_responder(p_hwfn, qp); 1023f1093940SRam Amrani return rc; 1024f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTR) && 1025f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1026f1093940SRam Amrani /* RTR-> RTS */ 1027f1093940SRam Amrani rc = qed_roce_sp_create_requester(p_hwfn, qp); 1028f1093940SRam Amrani if (rc) 1029f1093940SRam Amrani return rc; 1030f1093940SRam Amrani 1031f1093940SRam Amrani /* Send modify responder ramrod */ 1032f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1033f1093940SRam Amrani params->modify_flags); 1034f1093940SRam Amrani return rc; 1035f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1036f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1037f1093940SRam Amrani /* RTS->RTS */ 1038f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1039f1093940SRam Amrani params->modify_flags); 1040f1093940SRam Amrani if (rc) 1041f1093940SRam Amrani return rc; 1042f1093940SRam Amrani 1043f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1044f1093940SRam Amrani params->modify_flags); 1045f1093940SRam Amrani return rc; 1046f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_RTS) && 1047f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1048f1093940SRam Amrani /* RTS->SQD */ 1049f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false, 1050f1093940SRam Amrani params->modify_flags); 1051f1093940SRam Amrani return rc; 1052f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1053f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_SQD)) { 1054f1093940SRam Amrani /* SQD->SQD */ 1055f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1056f1093940SRam Amrani params->modify_flags); 1057f1093940SRam Amrani if (rc) 1058f1093940SRam Amrani return rc; 1059f1093940SRam Amrani 1060f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1061f1093940SRam Amrani params->modify_flags); 1062f1093940SRam Amrani return rc; 1063f1093940SRam Amrani } else if ((prev_state == QED_ROCE_QP_STATE_SQD) && 1064f1093940SRam Amrani (qp->cur_state == QED_ROCE_QP_STATE_RTS)) { 1065f1093940SRam Amrani /* SQD->RTS */ 1066f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, false, 1067f1093940SRam Amrani params->modify_flags); 1068f1093940SRam Amrani if (rc) 1069f1093940SRam Amrani return rc; 1070f1093940SRam Amrani 1071f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false, 1072f1093940SRam Amrani params->modify_flags); 1073f1093940SRam Amrani 1074f1093940SRam Amrani return rc; 1075ba0154e9SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR) { 1076f1093940SRam Amrani /* ->ERR */ 1077f1093940SRam Amrani rc = qed_roce_sp_modify_responder(p_hwfn, qp, true, 1078f1093940SRam Amrani params->modify_flags); 1079f1093940SRam Amrani if (rc) 1080f1093940SRam Amrani return rc; 1081f1093940SRam Amrani 1082f1093940SRam Amrani rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true, 1083f1093940SRam Amrani params->modify_flags); 1084f1093940SRam Amrani return rc; 1085f1093940SRam Amrani } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) { 1086f1093940SRam Amrani /* Any state -> RESET */ 1087be086e7cSMintz, Yuval u32 cq_prod; 1088f1093940SRam Amrani 1089be086e7cSMintz, Yuval /* Send destroy responder ramrod */ 1090be086e7cSMintz, Yuval rc = qed_roce_sp_destroy_qp_responder(p_hwfn, 1091be086e7cSMintz, Yuval qp, 1092be086e7cSMintz, Yuval &cq_prod); 1093be086e7cSMintz, Yuval 1094f1093940SRam Amrani if (rc) 1095f1093940SRam Amrani return rc; 1096f1093940SRam Amrani 1097be086e7cSMintz, Yuval qp->cq_prod = cq_prod; 1098be086e7cSMintz, Yuval 1099d52c89f1SMichal Kalderon rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp); 1100f1093940SRam Amrani } else { 1101f1093940SRam Amrani DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 1102f1093940SRam Amrani } 1103f1093940SRam Amrani 1104f1093940SRam Amrani return rc; 1105f1093940SRam Amrani } 1106f1093940SRam Amrani 1107be086e7cSMintz, Yuval static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid) 1108be086e7cSMintz, Yuval { 1109be086e7cSMintz, Yuval struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 1110be086e7cSMintz, Yuval u32 start_cid, cid, xcid; 1111be086e7cSMintz, Yuval 1112be086e7cSMintz, Yuval /* an even icid belongs to a responder while an odd icid belongs to a 1113be086e7cSMintz, Yuval * requester. The 'cid' received as an input can be either. We calculate 1114be086e7cSMintz, Yuval * the "partner" icid and call it xcid. Only if both are free then the 1115be086e7cSMintz, Yuval * "cid" map can be cleared. 1116be086e7cSMintz, Yuval */ 1117be086e7cSMintz, Yuval start_cid = qed_cxt_get_proto_cid_start(p_hwfn, p_rdma_info->proto); 1118be086e7cSMintz, Yuval cid = icid - start_cid; 1119be086e7cSMintz, Yuval xcid = cid ^ 1; 1120be086e7cSMintz, Yuval 1121be086e7cSMintz, Yuval spin_lock_bh(&p_rdma_info->lock); 1122be086e7cSMintz, Yuval 1123be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->real_cid_map, cid); 1124be086e7cSMintz, Yuval if (qed_bmap_test_id(p_hwfn, &p_rdma_info->real_cid_map, xcid) == 0) { 1125be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, cid); 1126be086e7cSMintz, Yuval qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, xcid); 1127be086e7cSMintz, Yuval } 1128be086e7cSMintz, Yuval 1129be086e7cSMintz, Yuval spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1130be086e7cSMintz, Yuval } 1131be086e7cSMintz, Yuval 11329331dad1SMintz, Yuval void qed_roce_dpm_dcbx(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11339331dad1SMintz, Yuval { 11349331dad1SMintz, Yuval u8 val; 11359331dad1SMintz, Yuval 11369331dad1SMintz, Yuval /* if any QPs are already active, we want to disable DPM, since their 11379331dad1SMintz, Yuval * context information contains information from before the latest DCBx 11389331dad1SMintz, Yuval * update. Otherwise enable it. 11399331dad1SMintz, Yuval */ 11409331dad1SMintz, Yuval val = qed_rdma_allocated_qps(p_hwfn) ? true : false; 11419331dad1SMintz, Yuval p_hwfn->dcbx_no_edpm = (u8)val; 11429331dad1SMintz, Yuval 11439331dad1SMintz, Yuval qed_rdma_dpm_conf(p_hwfn, p_ptt); 11449331dad1SMintz, Yuval } 11459331dad1SMintz, Yuval 1146b71b9afdSKalderon, Michal int qed_roce_setup(struct qed_hwfn *p_hwfn) 114751ff1725SRam Amrani { 1148b71b9afdSKalderon, Michal return qed_spq_register_async_cb(p_hwfn, PROTOCOLID_ROCE, 1149b71b9afdSKalderon, Michal qed_roce_async_event); 115051ff1725SRam Amrani } 115151ff1725SRam Amrani 115267b40dccSKalderon, Michal int qed_roce_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 115367b40dccSKalderon, Michal { 115467b40dccSKalderon, Michal u32 ll2_ethertype_en; 115567b40dccSKalderon, Michal 115667b40dccSKalderon, Michal qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 115767b40dccSKalderon, Michal 115867b40dccSKalderon, Michal p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE; 115967b40dccSKalderon, Michal 116067b40dccSKalderon, Michal ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 116167b40dccSKalderon, Michal qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 116267b40dccSKalderon, Michal (ll2_ethertype_en | 0x01)); 116367b40dccSKalderon, Michal 116467b40dccSKalderon, Michal if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) { 116567b40dccSKalderon, Michal DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n"); 116667b40dccSKalderon, Michal return -EINVAL; 116767b40dccSKalderon, Michal } 116867b40dccSKalderon, Michal 116967b40dccSKalderon, Michal DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n"); 117067b40dccSKalderon, Michal return 0; 117167b40dccSKalderon, Michal } 1172