1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #ifndef REG_ADDR_H 10 #define REG_ADDR_H 11 12 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ 13 0 14 15 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ 16 0xfff << 0) 17 18 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 19 12 20 21 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ 22 0xfff << 12) 23 24 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 25 24 26 27 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \ 28 0xff << 24) 29 30 #define XSDM_REG_OPERATION_GEN \ 31 0xf80408UL 32 #define NIG_REG_RX_BRB_OUT_EN \ 33 0x500e18UL 34 #define NIG_REG_STORM_OUT_EN \ 35 0x500e08UL 36 #define PSWRQ2_REG_L2P_VALIDATE_VFID \ 37 0x240c50UL 38 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \ 39 0x2aae04UL 40 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ 41 0x2aa16cUL 42 #define BAR0_MAP_REG_MSDM_RAM \ 43 0x1d00000UL 44 #define BAR0_MAP_REG_USDM_RAM \ 45 0x1d80000UL 46 #define BAR0_MAP_REG_PSDM_RAM \ 47 0x1f00000UL 48 #define BAR0_MAP_REG_TSDM_RAM \ 49 0x1c80000UL 50 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \ 51 0x5011f4UL 52 #define PRS_REG_SEARCH_TCP \ 53 0x1f0400UL 54 #define PRS_REG_SEARCH_UDP \ 55 0x1f0404UL 56 #define PRS_REG_SEARCH_FCOE \ 57 0x1f0408UL 58 #define PRS_REG_SEARCH_ROCE \ 59 0x1f040cUL 60 #define PRS_REG_SEARCH_OPENFLOW \ 61 0x1f0434UL 62 #define TM_REG_PF_ENABLE_CONN \ 63 0x2c043cUL 64 #define TM_REG_PF_ENABLE_TASK \ 65 0x2c0444UL 66 #define TM_REG_PF_SCAN_ACTIVE_CONN \ 67 0x2c04fcUL 68 #define TM_REG_PF_SCAN_ACTIVE_TASK \ 69 0x2c0500UL 70 #define IGU_REG_LEADING_EDGE_LATCH \ 71 0x18082cUL 72 #define IGU_REG_TRAILING_EDGE_LATCH \ 73 0x180830UL 74 #define QM_REG_USG_CNT_PF_TX \ 75 0x2f2eacUL 76 #define QM_REG_USG_CNT_PF_OTHER \ 77 0x2f2eb0UL 78 #define DORQ_REG_PF_DB_ENABLE \ 79 0x100508UL 80 #define QM_REG_PF_EN \ 81 0x2f2ea4UL 82 #define TCFC_REG_STRONG_ENABLE_PF \ 83 0x2d0708UL 84 #define CCFC_REG_STRONG_ENABLE_PF \ 85 0x2e0708UL 86 #define PGLUE_B_REG_PGL_ADDR_88_F0 \ 87 0x2aa404UL 88 #define PGLUE_B_REG_PGL_ADDR_8C_F0 \ 89 0x2aa408UL 90 #define PGLUE_B_REG_PGL_ADDR_90_F0 \ 91 0x2aa40cUL 92 #define PGLUE_B_REG_PGL_ADDR_94_F0 \ 93 0x2aa410UL 94 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \ 95 0x2aa138UL 96 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ 97 0x2aa174UL 98 #define MISC_REG_GEN_PURP_CR0 \ 99 0x008c80UL 100 #define MCP_REG_SCRATCH \ 101 0xe20000UL 102 #define CNIG_REG_NW_PORT_MODE_BB_B0 \ 103 0x218200UL 104 #define MISCS_REG_CHIP_NUM \ 105 0x00976cUL 106 #define MISCS_REG_CHIP_REV \ 107 0x009770UL 108 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \ 109 0x00971cUL 110 #define MISCS_REG_CHIP_TEST_REG \ 111 0x009778UL 112 #define MISCS_REG_CHIP_METAL \ 113 0x009774UL 114 #define BRB_REG_HEADER_SIZE \ 115 0x340804UL 116 #define BTB_REG_HEADER_SIZE \ 117 0xdb0804UL 118 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \ 119 0x1c0708UL 120 #define CCFC_REG_ACTIVITY_COUNTER \ 121 0x2e8800UL 122 #define CDU_REG_CID_ADDR_PARAMS \ 123 0x580900UL 124 #define DBG_REG_CLIENT_ENABLE \ 125 0x010004UL 126 #define DMAE_REG_INIT \ 127 0x00c000UL 128 #define DORQ_REG_IFEN \ 129 0x100040UL 130 #define GRC_REG_TIMEOUT_EN \ 131 0x050404UL 132 #define IGU_REG_BLOCK_CONFIGURATION \ 133 0x180040UL 134 #define MCM_REG_INIT \ 135 0x1200000UL 136 #define MCP2_REG_DBG_DWORD_ENABLE \ 137 0x052404UL 138 #define MISC_REG_PORT_MODE \ 139 0x008c00UL 140 #define MISCS_REG_CLK_100G_MODE \ 141 0x009070UL 142 #define MSDM_REG_ENABLE_IN1 \ 143 0xfc0004UL 144 #define MSEM_REG_ENABLE_IN \ 145 0x1800004UL 146 #define NIG_REG_CM_HDR \ 147 0x500840UL 148 #define NCSI_REG_CONFIG \ 149 0x040200UL 150 #define PBF_REG_INIT \ 151 0xd80000UL 152 #define PTU_REG_ATC_INIT_ARRAY \ 153 0x560000UL 154 #define PCM_REG_INIT \ 155 0x1100000UL 156 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \ 157 0x2a9000UL 158 #define PRM_REG_DISABLE_PRM \ 159 0x230000UL 160 #define PRS_REG_SOFT_RST \ 161 0x1f0000UL 162 #define PSDM_REG_ENABLE_IN1 \ 163 0xfa0004UL 164 #define PSEM_REG_ENABLE_IN \ 165 0x1600004UL 166 #define PSWRQ_REG_DBG_SELECT \ 167 0x280020UL 168 #define PSWRQ2_REG_CDUT_P_SIZE \ 169 0x24000cUL 170 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \ 171 0x2a0040UL 172 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ 173 0x29e050UL 174 #define PSWRD_REG_DBG_SELECT \ 175 0x29c040UL 176 #define PSWRD2_REG_CONF11 \ 177 0x29d064UL 178 #define PSWWR_REG_USDM_FULL_TH \ 179 0x29a040UL 180 #define PSWWR2_REG_CDU_FULL_TH2 \ 181 0x29b040UL 182 #define QM_REG_MAXPQSIZE_0 \ 183 0x2f0434UL 184 #define RSS_REG_RSS_INIT_EN \ 185 0x238804UL 186 #define RDIF_REG_STOP_ON_ERROR \ 187 0x300040UL 188 #define SRC_REG_SOFT_RST \ 189 0x23874cUL 190 #define TCFC_REG_ACTIVITY_COUNTER \ 191 0x2d8800UL 192 #define TCM_REG_INIT \ 193 0x1180000UL 194 #define TM_REG_PXP_READ_DATA_FIFO_INIT \ 195 0x2c0014UL 196 #define TSDM_REG_ENABLE_IN1 \ 197 0xfb0004UL 198 #define TSEM_REG_ENABLE_IN \ 199 0x1700004UL 200 #define TDIF_REG_STOP_ON_ERROR \ 201 0x310040UL 202 #define UCM_REG_INIT \ 203 0x1280000UL 204 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \ 205 0x051004UL 206 #define USDM_REG_ENABLE_IN1 \ 207 0xfd0004UL 208 #define USEM_REG_ENABLE_IN \ 209 0x1900004UL 210 #define XCM_REG_INIT \ 211 0x1000000UL 212 #define XSDM_REG_ENABLE_IN1 \ 213 0xf80004UL 214 #define XSEM_REG_ENABLE_IN \ 215 0x1400004UL 216 #define YCM_REG_INIT \ 217 0x1080000UL 218 #define YSDM_REG_ENABLE_IN1 \ 219 0xf90004UL 220 #define YSEM_REG_ENABLE_IN \ 221 0x1500004UL 222 #define XYLD_REG_SCBD_STRICT_PRIO \ 223 0x4c0000UL 224 #define TMLD_REG_SCBD_STRICT_PRIO \ 225 0x4d0000UL 226 #define MULD_REG_SCBD_STRICT_PRIO \ 227 0x4e0000UL 228 #define YULD_REG_SCBD_STRICT_PRIO \ 229 0x4c8000UL 230 #define MISC_REG_SHARED_MEM_ADDR \ 231 0x008c20UL 232 #define DMAE_REG_GO_C0 \ 233 0x00c048UL 234 #define DMAE_REG_GO_C1 \ 235 0x00c04cUL 236 #define DMAE_REG_GO_C2 \ 237 0x00c050UL 238 #define DMAE_REG_GO_C3 \ 239 0x00c054UL 240 #define DMAE_REG_GO_C4 \ 241 0x00c058UL 242 #define DMAE_REG_GO_C5 \ 243 0x00c05cUL 244 #define DMAE_REG_GO_C6 \ 245 0x00c060UL 246 #define DMAE_REG_GO_C7 \ 247 0x00c064UL 248 #define DMAE_REG_GO_C8 \ 249 0x00c068UL 250 #define DMAE_REG_GO_C9 \ 251 0x00c06cUL 252 #define DMAE_REG_GO_C10 \ 253 0x00c070UL 254 #define DMAE_REG_GO_C11 \ 255 0x00c074UL 256 #define DMAE_REG_GO_C12 \ 257 0x00c078UL 258 #define DMAE_REG_GO_C13 \ 259 0x00c07cUL 260 #define DMAE_REG_GO_C14 \ 261 0x00c080UL 262 #define DMAE_REG_GO_C15 \ 263 0x00c084UL 264 #define DMAE_REG_GO_C16 \ 265 0x00c088UL 266 #define DMAE_REG_GO_C17 \ 267 0x00c08cUL 268 #define DMAE_REG_GO_C18 \ 269 0x00c090UL 270 #define DMAE_REG_GO_C19 \ 271 0x00c094UL 272 #define DMAE_REG_GO_C20 \ 273 0x00c098UL 274 #define DMAE_REG_GO_C21 \ 275 0x00c09cUL 276 #define DMAE_REG_GO_C22 \ 277 0x00c0a0UL 278 #define DMAE_REG_GO_C23 \ 279 0x00c0a4UL 280 #define DMAE_REG_GO_C24 \ 281 0x00c0a8UL 282 #define DMAE_REG_GO_C25 \ 283 0x00c0acUL 284 #define DMAE_REG_GO_C26 \ 285 0x00c0b0UL 286 #define DMAE_REG_GO_C27 \ 287 0x00c0b4UL 288 #define DMAE_REG_GO_C28 \ 289 0x00c0b8UL 290 #define DMAE_REG_GO_C29 \ 291 0x00c0bcUL 292 #define DMAE_REG_GO_C30 \ 293 0x00c0c0UL 294 #define DMAE_REG_GO_C31 \ 295 0x00c0c4UL 296 #define DMAE_REG_CMD_MEM \ 297 0x00c800UL 298 #define QM_REG_MAXPQSIZETXSEL_0 \ 299 0x2f0440UL 300 #define QM_REG_SDMCMDREADY \ 301 0x2f1e10UL 302 #define QM_REG_SDMCMDADDR \ 303 0x2f1e04UL 304 #define QM_REG_SDMCMDDATALSB \ 305 0x2f1e08UL 306 #define QM_REG_SDMCMDDATAMSB \ 307 0x2f1e0cUL 308 #define QM_REG_SDMCMDGO \ 309 0x2f1e14UL 310 #define QM_REG_RLPFCRD \ 311 0x2f4d80UL 312 #define QM_REG_RLPFINCVAL \ 313 0x2f4c80UL 314 #define QM_REG_RLGLBLCRD \ 315 0x2f4400UL 316 #define QM_REG_RLGLBLINCVAL \ 317 0x2f3400UL 318 #define IGU_REG_ATTENTION_ENABLE \ 319 0x18083cUL 320 #define IGU_REG_ATTN_MSG_ADDR_L \ 321 0x180820UL 322 #define IGU_REG_ATTN_MSG_ADDR_H \ 323 0x180824UL 324 #define MISC_REG_AEU_GENERAL_ATTN_0 \ 325 0x008400UL 326 #define CAU_REG_SB_ADDR_MEMORY \ 327 0x1c8000UL 328 #define CAU_REG_SB_VAR_MEMORY \ 329 0x1c6000UL 330 #define CAU_REG_PI_MEMORY \ 331 0x1d0000UL 332 #define IGU_REG_PF_CONFIGURATION \ 333 0x180800UL 334 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \ 335 0x00849cUL 336 #define MISC_REG_AEU_MASK_ATTN_IGU \ 337 0x008494UL 338 #define IGU_REG_CLEANUP_STATUS_0 \ 339 0x180980UL 340 #define IGU_REG_CLEANUP_STATUS_1 \ 341 0x180a00UL 342 #define IGU_REG_CLEANUP_STATUS_2 \ 343 0x180a80UL 344 #define IGU_REG_CLEANUP_STATUS_3 \ 345 0x180b00UL 346 #define IGU_REG_CLEANUP_STATUS_4 \ 347 0x180b80UL 348 #define IGU_REG_COMMAND_REG_32LSB_DATA \ 349 0x180840UL 350 #define IGU_REG_COMMAND_REG_CTRL \ 351 0x180848UL 352 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ 353 0x1 << 1) 354 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ 355 0x1 << 0) 356 #define IGU_REG_MAPPING_MEMORY \ 357 0x184000UL 358 #define MISCS_REG_GENERIC_POR_0 \ 359 0x0096d4UL 360 #define MCP_REG_NVM_CFG4 \ 361 0xe0642cUL 362 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ 363 0x7 << 0) 364 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 365 0 366 #endif 367