1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #ifndef REG_ADDR_H 10 #define REG_ADDR_H 11 12 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ 13 0 14 15 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ 16 0xfff << 0) 17 18 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 19 12 20 21 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ 22 0xfff << 12) 23 24 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 25 24 26 27 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \ 28 0xff << 24) 29 30 #define XSDM_REG_OPERATION_GEN \ 31 0xf80408UL 32 #define NIG_REG_RX_BRB_OUT_EN \ 33 0x500e18UL 34 #define NIG_REG_STORM_OUT_EN \ 35 0x500e08UL 36 #define PSWRQ2_REG_L2P_VALIDATE_VFID \ 37 0x240c50UL 38 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \ 39 0x2aae04UL 40 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ 41 0x2aa16cUL 42 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \ 43 0x2aa118UL 44 #define PSWHST_REG_ZONE_PERMISSION_TABLE \ 45 0x2a0800UL 46 #define BAR0_MAP_REG_MSDM_RAM \ 47 0x1d00000UL 48 #define BAR0_MAP_REG_USDM_RAM \ 49 0x1d80000UL 50 #define BAR0_MAP_REG_PSDM_RAM \ 51 0x1f00000UL 52 #define BAR0_MAP_REG_TSDM_RAM \ 53 0x1c80000UL 54 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \ 55 0x5011f4UL 56 #define PRS_REG_SEARCH_TCP \ 57 0x1f0400UL 58 #define PRS_REG_SEARCH_UDP \ 59 0x1f0404UL 60 #define PRS_REG_SEARCH_FCOE \ 61 0x1f0408UL 62 #define PRS_REG_SEARCH_ROCE \ 63 0x1f040cUL 64 #define PRS_REG_SEARCH_OPENFLOW \ 65 0x1f0434UL 66 #define TM_REG_PF_ENABLE_CONN \ 67 0x2c043cUL 68 #define TM_REG_PF_ENABLE_TASK \ 69 0x2c0444UL 70 #define TM_REG_PF_SCAN_ACTIVE_CONN \ 71 0x2c04fcUL 72 #define TM_REG_PF_SCAN_ACTIVE_TASK \ 73 0x2c0500UL 74 #define IGU_REG_LEADING_EDGE_LATCH \ 75 0x18082cUL 76 #define IGU_REG_TRAILING_EDGE_LATCH \ 77 0x180830UL 78 #define QM_REG_USG_CNT_PF_TX \ 79 0x2f2eacUL 80 #define QM_REG_USG_CNT_PF_OTHER \ 81 0x2f2eb0UL 82 #define DORQ_REG_PF_DB_ENABLE \ 83 0x100508UL 84 #define DORQ_REG_VF_USAGE_CNT \ 85 0x1009c4UL 86 #define QM_REG_PF_EN \ 87 0x2f2ea4UL 88 #define TCFC_REG_STRONG_ENABLE_PF \ 89 0x2d0708UL 90 #define CCFC_REG_STRONG_ENABLE_PF \ 91 0x2e0708UL 92 #define PGLUE_B_REG_PGL_ADDR_88_F0 \ 93 0x2aa404UL 94 #define PGLUE_B_REG_PGL_ADDR_8C_F0 \ 95 0x2aa408UL 96 #define PGLUE_B_REG_PGL_ADDR_90_F0 \ 97 0x2aa40cUL 98 #define PGLUE_B_REG_PGL_ADDR_94_F0 \ 99 0x2aa410UL 100 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \ 101 0x2aa138UL 102 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ 103 0x2aa174UL 104 #define MISC_REG_GEN_PURP_CR0 \ 105 0x008c80UL 106 #define MCP_REG_SCRATCH \ 107 0xe20000UL 108 #define CNIG_REG_NW_PORT_MODE_BB_B0 \ 109 0x218200UL 110 #define MISCS_REG_CHIP_NUM \ 111 0x00976cUL 112 #define MISCS_REG_CHIP_REV \ 113 0x009770UL 114 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \ 115 0x00971cUL 116 #define MISCS_REG_CHIP_TEST_REG \ 117 0x009778UL 118 #define MISCS_REG_CHIP_METAL \ 119 0x009774UL 120 #define MISCS_REG_FUNCTION_HIDE \ 121 0x0096f0UL 122 #define BRB_REG_HEADER_SIZE \ 123 0x340804UL 124 #define BTB_REG_HEADER_SIZE \ 125 0xdb0804UL 126 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \ 127 0x1c0708UL 128 #define CCFC_REG_ACTIVITY_COUNTER \ 129 0x2e8800UL 130 #define CCFC_REG_STRONG_ENABLE_VF \ 131 0x2e070cUL 132 #define CDU_REG_CID_ADDR_PARAMS \ 133 0x580900UL 134 #define DBG_REG_CLIENT_ENABLE \ 135 0x010004UL 136 #define DMAE_REG_INIT \ 137 0x00c000UL 138 #define DORQ_REG_IFEN \ 139 0x100040UL 140 #define DORQ_REG_DB_DROP_REASON \ 141 0x100a2cUL 142 #define DORQ_REG_DB_DROP_DETAILS \ 143 0x100a24UL 144 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \ 145 0x100a1cUL 146 #define GRC_REG_TIMEOUT_EN \ 147 0x050404UL 148 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \ 149 0x050054UL 150 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \ 151 0x05004cUL 152 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \ 153 0x050050UL 154 #define IGU_REG_BLOCK_CONFIGURATION \ 155 0x180040UL 156 #define MCM_REG_INIT \ 157 0x1200000UL 158 #define MCP2_REG_DBG_DWORD_ENABLE \ 159 0x052404UL 160 #define MISC_REG_PORT_MODE \ 161 0x008c00UL 162 #define MISCS_REG_CLK_100G_MODE \ 163 0x009070UL 164 #define MSDM_REG_ENABLE_IN1 \ 165 0xfc0004UL 166 #define MSEM_REG_ENABLE_IN \ 167 0x1800004UL 168 #define NIG_REG_CM_HDR \ 169 0x500840UL 170 #define NCSI_REG_CONFIG \ 171 0x040200UL 172 #define PBF_REG_INIT \ 173 0xd80000UL 174 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \ 175 0xd806c8UL 176 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \ 177 0xd806ccUL 178 #define PTU_REG_ATC_INIT_ARRAY \ 179 0x560000UL 180 #define PCM_REG_INIT \ 181 0x1100000UL 182 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \ 183 0x2a9000UL 184 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \ 185 0x2aa150UL 186 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \ 187 0x2aa144UL 188 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \ 189 0x2aa148UL 190 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \ 191 0x2aa14cUL 192 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \ 193 0x2aa154UL 194 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \ 195 0x2aa158UL 196 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \ 197 0x2aa15cUL 198 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \ 199 0x2aa160UL 200 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \ 201 0x2aa164UL 202 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \ 203 0x2aa54cUL 204 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \ 205 0x2aa544UL 206 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \ 207 0x2aa548UL 208 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \ 209 0x2aae74UL 210 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \ 211 0x2aae78UL 212 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \ 213 0x2aae7cUL 214 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \ 215 0x2aae80UL 216 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \ 217 0x2aa3bcUL 218 #define PRM_REG_DISABLE_PRM \ 219 0x230000UL 220 #define PRS_REG_SOFT_RST \ 221 0x1f0000UL 222 #define PSDM_REG_ENABLE_IN1 \ 223 0xfa0004UL 224 #define PSEM_REG_ENABLE_IN \ 225 0x1600004UL 226 #define PSWRQ_REG_DBG_SELECT \ 227 0x280020UL 228 #define PSWRQ2_REG_CDUT_P_SIZE \ 229 0x24000cUL 230 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \ 231 0x2a0040UL 232 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ 233 0x29e050UL 234 #define PSWHST_REG_INCORRECT_ACCESS_VALID \ 235 0x2a0070UL 236 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \ 237 0x2a0074UL 238 #define PSWHST_REG_INCORRECT_ACCESS_DATA \ 239 0x2a0068UL 240 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \ 241 0x2a006cUL 242 #define PSWRD_REG_DBG_SELECT \ 243 0x29c040UL 244 #define PSWRD2_REG_CONF11 \ 245 0x29d064UL 246 #define PSWWR_REG_USDM_FULL_TH \ 247 0x29a040UL 248 #define PSWWR2_REG_CDU_FULL_TH2 \ 249 0x29b040UL 250 #define QM_REG_MAXPQSIZE_0 \ 251 0x2f0434UL 252 #define RSS_REG_RSS_INIT_EN \ 253 0x238804UL 254 #define RDIF_REG_STOP_ON_ERROR \ 255 0x300040UL 256 #define SRC_REG_SOFT_RST \ 257 0x23874cUL 258 #define TCFC_REG_ACTIVITY_COUNTER \ 259 0x2d8800UL 260 #define TCM_REG_INIT \ 261 0x1180000UL 262 #define TM_REG_PXP_READ_DATA_FIFO_INIT \ 263 0x2c0014UL 264 #define TSDM_REG_ENABLE_IN1 \ 265 0xfb0004UL 266 #define TSEM_REG_ENABLE_IN \ 267 0x1700004UL 268 #define TDIF_REG_STOP_ON_ERROR \ 269 0x310040UL 270 #define UCM_REG_INIT \ 271 0x1280000UL 272 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \ 273 0x051004UL 274 #define USDM_REG_ENABLE_IN1 \ 275 0xfd0004UL 276 #define USEM_REG_ENABLE_IN \ 277 0x1900004UL 278 #define XCM_REG_INIT \ 279 0x1000000UL 280 #define XSDM_REG_ENABLE_IN1 \ 281 0xf80004UL 282 #define XSEM_REG_ENABLE_IN \ 283 0x1400004UL 284 #define YCM_REG_INIT \ 285 0x1080000UL 286 #define YSDM_REG_ENABLE_IN1 \ 287 0xf90004UL 288 #define YSEM_REG_ENABLE_IN \ 289 0x1500004UL 290 #define XYLD_REG_SCBD_STRICT_PRIO \ 291 0x4c0000UL 292 #define TMLD_REG_SCBD_STRICT_PRIO \ 293 0x4d0000UL 294 #define MULD_REG_SCBD_STRICT_PRIO \ 295 0x4e0000UL 296 #define YULD_REG_SCBD_STRICT_PRIO \ 297 0x4c8000UL 298 #define MISC_REG_SHARED_MEM_ADDR \ 299 0x008c20UL 300 #define DMAE_REG_GO_C0 \ 301 0x00c048UL 302 #define DMAE_REG_GO_C1 \ 303 0x00c04cUL 304 #define DMAE_REG_GO_C2 \ 305 0x00c050UL 306 #define DMAE_REG_GO_C3 \ 307 0x00c054UL 308 #define DMAE_REG_GO_C4 \ 309 0x00c058UL 310 #define DMAE_REG_GO_C5 \ 311 0x00c05cUL 312 #define DMAE_REG_GO_C6 \ 313 0x00c060UL 314 #define DMAE_REG_GO_C7 \ 315 0x00c064UL 316 #define DMAE_REG_GO_C8 \ 317 0x00c068UL 318 #define DMAE_REG_GO_C9 \ 319 0x00c06cUL 320 #define DMAE_REG_GO_C10 \ 321 0x00c070UL 322 #define DMAE_REG_GO_C11 \ 323 0x00c074UL 324 #define DMAE_REG_GO_C12 \ 325 0x00c078UL 326 #define DMAE_REG_GO_C13 \ 327 0x00c07cUL 328 #define DMAE_REG_GO_C14 \ 329 0x00c080UL 330 #define DMAE_REG_GO_C15 \ 331 0x00c084UL 332 #define DMAE_REG_GO_C16 \ 333 0x00c088UL 334 #define DMAE_REG_GO_C17 \ 335 0x00c08cUL 336 #define DMAE_REG_GO_C18 \ 337 0x00c090UL 338 #define DMAE_REG_GO_C19 \ 339 0x00c094UL 340 #define DMAE_REG_GO_C20 \ 341 0x00c098UL 342 #define DMAE_REG_GO_C21 \ 343 0x00c09cUL 344 #define DMAE_REG_GO_C22 \ 345 0x00c0a0UL 346 #define DMAE_REG_GO_C23 \ 347 0x00c0a4UL 348 #define DMAE_REG_GO_C24 \ 349 0x00c0a8UL 350 #define DMAE_REG_GO_C25 \ 351 0x00c0acUL 352 #define DMAE_REG_GO_C26 \ 353 0x00c0b0UL 354 #define DMAE_REG_GO_C27 \ 355 0x00c0b4UL 356 #define DMAE_REG_GO_C28 \ 357 0x00c0b8UL 358 #define DMAE_REG_GO_C29 \ 359 0x00c0bcUL 360 #define DMAE_REG_GO_C30 \ 361 0x00c0c0UL 362 #define DMAE_REG_GO_C31 \ 363 0x00c0c4UL 364 #define DMAE_REG_CMD_MEM \ 365 0x00c800UL 366 #define QM_REG_MAXPQSIZETXSEL_0 \ 367 0x2f0440UL 368 #define QM_REG_SDMCMDREADY \ 369 0x2f1e10UL 370 #define QM_REG_SDMCMDADDR \ 371 0x2f1e04UL 372 #define QM_REG_SDMCMDDATALSB \ 373 0x2f1e08UL 374 #define QM_REG_SDMCMDDATAMSB \ 375 0x2f1e0cUL 376 #define QM_REG_SDMCMDGO \ 377 0x2f1e14UL 378 #define QM_REG_RLPFCRD \ 379 0x2f4d80UL 380 #define QM_REG_RLPFINCVAL \ 381 0x2f4c80UL 382 #define QM_REG_RLGLBLCRD \ 383 0x2f4400UL 384 #define QM_REG_RLGLBLINCVAL \ 385 0x2f3400UL 386 #define IGU_REG_ATTENTION_ENABLE \ 387 0x18083cUL 388 #define IGU_REG_ATTN_MSG_ADDR_L \ 389 0x180820UL 390 #define IGU_REG_ATTN_MSG_ADDR_H \ 391 0x180824UL 392 #define MISC_REG_AEU_GENERAL_ATTN_0 \ 393 0x008400UL 394 #define CAU_REG_SB_ADDR_MEMORY \ 395 0x1c8000UL 396 #define CAU_REG_SB_VAR_MEMORY \ 397 0x1c6000UL 398 #define CAU_REG_PI_MEMORY \ 399 0x1d0000UL 400 #define IGU_REG_PF_CONFIGURATION \ 401 0x180800UL 402 #define IGU_REG_VF_CONFIGURATION \ 403 0x180804UL 404 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \ 405 0x00849cUL 406 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \ 407 0x0087b4UL 408 #define MISC_REG_AEU_MASK_ATTN_IGU \ 409 0x008494UL 410 #define IGU_REG_CLEANUP_STATUS_0 \ 411 0x180980UL 412 #define IGU_REG_CLEANUP_STATUS_1 \ 413 0x180a00UL 414 #define IGU_REG_CLEANUP_STATUS_2 \ 415 0x180a80UL 416 #define IGU_REG_CLEANUP_STATUS_3 \ 417 0x180b00UL 418 #define IGU_REG_CLEANUP_STATUS_4 \ 419 0x180b80UL 420 #define IGU_REG_COMMAND_REG_32LSB_DATA \ 421 0x180840UL 422 #define IGU_REG_COMMAND_REG_CTRL \ 423 0x180848UL 424 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ 425 0x1 << 1) 426 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ 427 0x1 << 0) 428 #define IGU_REG_MAPPING_MEMORY \ 429 0x184000UL 430 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \ 431 0x180408UL 432 #define IGU_REG_WRITE_DONE_PENDING \ 433 0x180900UL 434 #define MISCS_REG_GENERIC_POR_0 \ 435 0x0096d4UL 436 #define MCP_REG_NVM_CFG4 \ 437 0xe0642cUL 438 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ 439 0x7 << 0) 440 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 441 0 442 #define MCP_REG_CPU_STATE \ 443 0xe05004UL 444 #define MCP_REG_CPU_EVENT_MASK \ 445 0xe05008UL 446 #define PGLUE_B_REG_PF_BAR0_SIZE \ 447 0x2aae60UL 448 #define PGLUE_B_REG_PF_BAR1_SIZE \ 449 0x2aae64UL 450 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL 451 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL 452 #define PRS_REG_VXLAN_PORT 0x1f0738UL 453 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL 454 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL 455 456 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0) 457 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0 458 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1) 459 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1 460 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2) 461 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2 462 463 #define NIG_REG_VXLAN_PORT 0x50105cUL 464 #define PBF_REG_VXLAN_PORT 0xd80518UL 465 #define PBF_REG_NGE_PORT 0xd8051cUL 466 #define PRS_REG_NGE_PORT 0x1f086cUL 467 #define NIG_REG_NGE_PORT 0x508b38UL 468 469 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL 470 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL 471 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL 472 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL 473 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL 474 475 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL 476 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL 477 #define NIG_REG_NGE_COMP_VER 0x508b30UL 478 #define PBF_REG_NGE_COMP_VER 0xd80524UL 479 #define PRS_REG_NGE_COMP_VER 0x1f0878UL 480 481 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL 482 #define QM_REG_WFQVPWEIGHT 0x2fa000UL 483 #endif 484