11f4d4ed6SAlexander Lobakin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2f1372ee1SKalderon, Michal /* QLogic qed NIC Driver 3f1372ee1SKalderon, Michal * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5f1372ee1SKalderon, Michal */ 61f4d4ed6SAlexander Lobakin 7b71b9afdSKalderon, Michal #ifndef _QED_RDMA_H 8b71b9afdSKalderon, Michal #define _QED_RDMA_H 9f1372ee1SKalderon, Michal #include <linux/types.h> 10f1372ee1SKalderon, Michal #include <linux/bitops.h> 11f1372ee1SKalderon, Michal #include <linux/kernel.h> 12f1372ee1SKalderon, Michal #include <linux/list.h> 13f1372ee1SKalderon, Michal #include <linux/slab.h> 14f1372ee1SKalderon, Michal #include <linux/spinlock.h> 15f1372ee1SKalderon, Michal #include <linux/qed/qed_if.h> 167003cdd6SKalderon, Michal #include <linux/qed/qed_rdma_if.h> 17f1372ee1SKalderon, Michal #include "qed.h" 18f1372ee1SKalderon, Michal #include "qed_dev_api.h" 19f1372ee1SKalderon, Michal #include "qed_hsi.h" 2067b40dccSKalderon, Michal #include "qed_iwarp.h" 21b71b9afdSKalderon, Michal #include "qed_roce.h" 22f1372ee1SKalderon, Michal 23f1372ee1SKalderon, Michal #define QED_RDMA_MAX_P_KEY (1) 24f1372ee1SKalderon, Michal #define QED_RDMA_MAX_WQE (0x7FFF) 25f1372ee1SKalderon, Michal #define QED_RDMA_MAX_SRQ_WQE_ELEM (0x7FFF) 26f1372ee1SKalderon, Michal #define QED_RDMA_PAGE_SIZE_CAPS (0xFFFFF000) 27f1372ee1SKalderon, Michal #define QED_RDMA_ACK_DELAY (15) 28f1372ee1SKalderon, Michal #define QED_RDMA_MAX_MR_SIZE (0x10000000000ULL) 29f1372ee1SKalderon, Michal #define QED_RDMA_MAX_CQS (RDMA_MAX_CQS) 30f1372ee1SKalderon, Michal #define QED_RDMA_MAX_MRS (RDMA_MAX_TIDS) 31f1372ee1SKalderon, Michal /* Add 1 for header element */ 32f1372ee1SKalderon, Michal #define QED_RDMA_MAX_SRQ_ELEM_PER_WQE (RDMA_MAX_SGE_PER_RQ_WQE + 1) 33f1372ee1SKalderon, Michal #define QED_RDMA_MAX_SGE_PER_SRQ_WQE (RDMA_MAX_SGE_PER_RQ_WQE) 34f1372ee1SKalderon, Michal #define QED_RDMA_SRQ_WQE_ELEM_SIZE (16) 35f1372ee1SKalderon, Michal #define QED_RDMA_MAX_SRQS (32 * 1024) 36f1372ee1SKalderon, Michal 37f1372ee1SKalderon, Michal #define QED_RDMA_MAX_CQE_32_BIT (0x7FFFFFFF - 1) 38f1372ee1SKalderon, Michal #define QED_RDMA_MAX_CQE_16_BIT (0x7FFF - 1) 39f1372ee1SKalderon, Michal 407bfb399eSYuval Basson /* Up to 2^16 XRC Domains are supported, but the actual number of supported XRC 417bfb399eSYuval Basson * SRQs is much smaller so there's no need to have that many domains. 427bfb399eSYuval Basson */ 437bfb399eSYuval Basson #define QED_RDMA_MAX_XRCDS (roundup_pow_of_two(RDMA_MAX_XRC_SRQS)) 447bfb399eSYuval Basson 45f1372ee1SKalderon, Michal enum qed_rdma_toggle_bit { 46f1372ee1SKalderon, Michal QED_RDMA_TOGGLE_BIT_CLEAR = 0, 47f1372ee1SKalderon, Michal QED_RDMA_TOGGLE_BIT_SET = 1 48f1372ee1SKalderon, Michal }; 49f1372ee1SKalderon, Michal 50f1372ee1SKalderon, Michal #define QED_RDMA_MAX_BMAP_NAME (10) 51f1372ee1SKalderon, Michal struct qed_bmap { 52f1372ee1SKalderon, Michal unsigned long *bitmap; 53f1372ee1SKalderon, Michal u32 max_count; 54f1372ee1SKalderon, Michal char name[QED_RDMA_MAX_BMAP_NAME]; 55f1372ee1SKalderon, Michal }; 56f1372ee1SKalderon, Michal 57f1372ee1SKalderon, Michal struct qed_rdma_info { 58f1372ee1SKalderon, Michal /* spin lock to protect bitmaps */ 59f1372ee1SKalderon, Michal spinlock_t lock; 60f1372ee1SKalderon, Michal 61f1372ee1SKalderon, Michal struct qed_bmap cq_map; 62f1372ee1SKalderon, Michal struct qed_bmap pd_map; 637bfb399eSYuval Basson struct qed_bmap xrcd_map; 64f1372ee1SKalderon, Michal struct qed_bmap tid_map; 65f1372ee1SKalderon, Michal struct qed_bmap qp_map; 66f1372ee1SKalderon, Michal struct qed_bmap srq_map; 677bfb399eSYuval Basson struct qed_bmap xrc_srq_map; 68f1372ee1SKalderon, Michal struct qed_bmap cid_map; 69456a5849SKalderon, Michal struct qed_bmap tcp_cid_map; 70f1372ee1SKalderon, Michal struct qed_bmap real_cid_map; 71f1372ee1SKalderon, Michal struct qed_bmap dpi_map; 72f1372ee1SKalderon, Michal struct qed_bmap toggle_bits; 73f1372ee1SKalderon, Michal struct qed_rdma_events events; 74f1372ee1SKalderon, Michal struct qed_rdma_device *dev; 75f1372ee1SKalderon, Michal struct qed_rdma_port *port; 76f1372ee1SKalderon, Michal u32 last_tid; 77f1372ee1SKalderon, Michal u8 num_cnqs; 78f1372ee1SKalderon, Michal u32 num_qps; 79f1372ee1SKalderon, Michal u32 num_mrs; 8039dbc646SYuval Bason u32 num_srqs; 8139dbc646SYuval Bason u16 srq_id_offset; 82f1372ee1SKalderon, Michal u16 queue_zone_base; 83f1372ee1SKalderon, Michal u16 max_queue_zones; 84f1372ee1SKalderon, Michal enum protocol_type proto; 8567b40dccSKalderon, Michal struct qed_iwarp_info iwarp; 86291d57f6SMichal Kalderon u8 active:1; 87f1372ee1SKalderon, Michal }; 88f1372ee1SKalderon, Michal 89f1372ee1SKalderon, Michal struct qed_rdma_qp { 90f1372ee1SKalderon, Michal struct regpair qp_handle; 91f1372ee1SKalderon, Michal struct regpair qp_handle_async; 92f1372ee1SKalderon, Michal u32 qpid; 93f1372ee1SKalderon, Michal u16 icid; 94f1372ee1SKalderon, Michal enum qed_roce_qp_state cur_state; 957bfb399eSYuval Basson enum qed_rdma_qp_type qp_type; 9667b40dccSKalderon, Michal enum qed_iwarp_qp_state iwarp_state; 97f1372ee1SKalderon, Michal bool use_srq; 98f1372ee1SKalderon, Michal bool signal_all; 99f1372ee1SKalderon, Michal bool fmr_and_reserved_lkey; 100f1372ee1SKalderon, Michal 101f1372ee1SKalderon, Michal bool incoming_rdma_read_en; 102f1372ee1SKalderon, Michal bool incoming_rdma_write_en; 103f1372ee1SKalderon, Michal bool incoming_atomic_en; 104f1372ee1SKalderon, Michal bool e2e_flow_control_en; 105f1372ee1SKalderon, Michal 106f1372ee1SKalderon, Michal u16 pd; 107f1372ee1SKalderon, Michal u16 pkey; 108f1372ee1SKalderon, Michal u32 dest_qp; 109f1372ee1SKalderon, Michal u16 mtu; 110f1372ee1SKalderon, Michal u16 srq_id; 111f1372ee1SKalderon, Michal u8 traffic_class_tos; 112f1372ee1SKalderon, Michal u8 hop_limit_ttl; 113f1372ee1SKalderon, Michal u16 dpi; 114f1372ee1SKalderon, Michal u32 flow_label; 115f1372ee1SKalderon, Michal bool lb_indication; 116f1372ee1SKalderon, Michal u16 vlan_id; 117f1372ee1SKalderon, Michal u32 ack_timeout; 118f1372ee1SKalderon, Michal u8 retry_cnt; 119f1372ee1SKalderon, Michal u8 rnr_retry_cnt; 120f1372ee1SKalderon, Michal u8 min_rnr_nak_timer; 121f1372ee1SKalderon, Michal bool sqd_async; 122f1372ee1SKalderon, Michal union qed_gid sgid; 123f1372ee1SKalderon, Michal union qed_gid dgid; 124f1372ee1SKalderon, Michal enum roce_mode roce_mode; 125f1372ee1SKalderon, Michal u16 udp_src_port; 126f1372ee1SKalderon, Michal u8 stats_queue; 127f1372ee1SKalderon, Michal 128f1372ee1SKalderon, Michal /* requeseter */ 129f1372ee1SKalderon, Michal u8 max_rd_atomic_req; 130f1372ee1SKalderon, Michal u32 sq_psn; 131f1372ee1SKalderon, Michal u16 sq_cq_id; 132f1372ee1SKalderon, Michal u16 sq_num_pages; 133f1372ee1SKalderon, Michal dma_addr_t sq_pbl_ptr; 134f1372ee1SKalderon, Michal void *orq; 135f1372ee1SKalderon, Michal dma_addr_t orq_phys_addr; 136f1372ee1SKalderon, Michal u8 orq_num_pages; 137f1372ee1SKalderon, Michal bool req_offloaded; 1387bfb399eSYuval Basson bool has_req; 139f1372ee1SKalderon, Michal 140f1372ee1SKalderon, Michal /* responder */ 141f1372ee1SKalderon, Michal u8 max_rd_atomic_resp; 142f1372ee1SKalderon, Michal u32 rq_psn; 143f1372ee1SKalderon, Michal u16 rq_cq_id; 144f1372ee1SKalderon, Michal u16 rq_num_pages; 1457bfb399eSYuval Basson u16 xrcd_id; 146f1372ee1SKalderon, Michal dma_addr_t rq_pbl_ptr; 147f1372ee1SKalderon, Michal void *irq; 148f1372ee1SKalderon, Michal dma_addr_t irq_phys_addr; 149f1372ee1SKalderon, Michal u8 irq_num_pages; 150f1372ee1SKalderon, Michal bool resp_offloaded; 151f1372ee1SKalderon, Michal u32 cq_prod; 1527bfb399eSYuval Basson bool has_resp; 153f1372ee1SKalderon, Michal 154f1372ee1SKalderon, Michal u8 remote_mac_addr[6]; 155f1372ee1SKalderon, Michal u8 local_mac_addr[6]; 156f1372ee1SKalderon, Michal 157f1372ee1SKalderon, Michal void *shared_queue; 158f1372ee1SKalderon, Michal dma_addr_t shared_queue_phys_addr; 159456a5849SKalderon, Michal struct qed_iwarp_ep *ep; 160ff937b91SYuval Basson u8 edpm_mode; 161f1372ee1SKalderon, Michal }; 162f1372ee1SKalderon, Michal 1637bfb399eSYuval Basson static inline bool qed_rdma_is_xrc_qp(struct qed_rdma_qp *qp) 1647bfb399eSYuval Basson { 1657bfb399eSYuval Basson if (qp->qp_type == QED_RDMA_QP_TYPE_XRC_TGT || 1667bfb399eSYuval Basson qp->qp_type == QED_RDMA_QP_TYPE_XRC_INI) 1677bfb399eSYuval Basson return true; 1687bfb399eSYuval Basson 1697bfb399eSYuval Basson return false; 1707bfb399eSYuval Basson } 171f1372ee1SKalderon, Michal #if IS_ENABLED(CONFIG_QED_RDMA) 172f1372ee1SKalderon, Michal void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 173b71b9afdSKalderon, Michal void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 174291d57f6SMichal Kalderon int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn); 175291d57f6SMichal Kalderon void qed_rdma_info_free(struct qed_hwfn *p_hwfn); 176f1372ee1SKalderon, Michal #else 177b71b9afdSKalderon, Michal static inline void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) {} 178b71b9afdSKalderon, Michal static inline void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, 179f1372ee1SKalderon, Michal struct qed_ptt *p_ptt) {} 180a97b9565SAndrew Morton static inline int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn) {return -EINVAL;} 181291d57f6SMichal Kalderon static inline void qed_rdma_info_free(struct qed_hwfn *p_hwfn) {} 182f1372ee1SKalderon, Michal #endif 183b71b9afdSKalderon, Michal 184b71b9afdSKalderon, Michal int 185b71b9afdSKalderon, Michal qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn, 186b71b9afdSKalderon, Michal struct qed_bmap *bmap, u32 max_count, char *name); 187b71b9afdSKalderon, Michal 188b71b9afdSKalderon, Michal void 189b71b9afdSKalderon, Michal qed_rdma_bmap_free(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, bool check); 190b71b9afdSKalderon, Michal 191b71b9afdSKalderon, Michal int 192b71b9afdSKalderon, Michal qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn, 193b71b9afdSKalderon, Michal struct qed_bmap *bmap, u32 *id_num); 194b71b9afdSKalderon, Michal 195b71b9afdSKalderon, Michal void 196b71b9afdSKalderon, Michal qed_bmap_set_id(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, u32 id_num); 197b71b9afdSKalderon, Michal 198b71b9afdSKalderon, Michal void 199b71b9afdSKalderon, Michal qed_bmap_release_id(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, u32 id_num); 200b71b9afdSKalderon, Michal 201b71b9afdSKalderon, Michal int 202b71b9afdSKalderon, Michal qed_bmap_test_id(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, u32 id_num); 203b71b9afdSKalderon, Michal 2045ab90341SAlexander Lobakin void qed_rdma_set_fw_mac(__le16 *p_fw_mac, const u8 *p_qed_mac); 205b71b9afdSKalderon, Michal 206b71b9afdSKalderon, Michal bool qed_rdma_allocated_qps(struct qed_hwfn *p_hwfn); 207f1372ee1SKalderon, Michal #endif 208