1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/types.h> 33 #include <asm/byteorder.h> 34 #include <linux/bitops.h> 35 #include <linux/delay.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/errno.h> 38 #include <linux/io.h> 39 #include <linux/kernel.h> 40 #include <linux/list.h> 41 #include <linux/module.h> 42 #include <linux/mutex.h> 43 #include <linux/pci.h> 44 #include <linux/slab.h> 45 #include <linux/spinlock.h> 46 #include <linux/string.h> 47 #include "qed.h" 48 #include "qed_cxt.h" 49 #include "qed_hsi.h" 50 #include "qed_hw.h" 51 #include "qed_init_ops.h" 52 #include "qed_int.h" 53 #include "qed_ll2.h" 54 #include "qed_mcp.h" 55 #include "qed_reg_addr.h" 56 #include <linux/qed/qed_rdma_if.h> 57 #include "qed_rdma.h" 58 #include "qed_roce.h" 59 #include "qed_sp.h" 60 61 62 int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn, 63 struct qed_bmap *bmap, u32 max_count, char *name) 64 { 65 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count); 66 67 bmap->max_count = max_count; 68 69 bmap->bitmap = kcalloc(BITS_TO_LONGS(max_count), sizeof(long), 70 GFP_KERNEL); 71 if (!bmap->bitmap) 72 return -ENOMEM; 73 74 snprintf(bmap->name, QED_RDMA_MAX_BMAP_NAME, "%s", name); 75 76 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 77 return 0; 78 } 79 80 int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn, 81 struct qed_bmap *bmap, u32 *id_num) 82 { 83 *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count); 84 if (*id_num >= bmap->max_count) 85 return -EINVAL; 86 87 __set_bit(*id_num, bmap->bitmap); 88 89 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: allocated id %d\n", 90 bmap->name, *id_num); 91 92 return 0; 93 } 94 95 void qed_bmap_set_id(struct qed_hwfn *p_hwfn, 96 struct qed_bmap *bmap, u32 id_num) 97 { 98 if (id_num >= bmap->max_count) 99 return; 100 101 __set_bit(id_num, bmap->bitmap); 102 } 103 104 void qed_bmap_release_id(struct qed_hwfn *p_hwfn, 105 struct qed_bmap *bmap, u32 id_num) 106 { 107 bool b_acquired; 108 109 if (id_num >= bmap->max_count) 110 return; 111 112 b_acquired = test_and_clear_bit(id_num, bmap->bitmap); 113 if (!b_acquired) { 114 DP_NOTICE(p_hwfn, "%s bitmap: id %d already released\n", 115 bmap->name, id_num); 116 return; 117 } 118 119 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: released id %d\n", 120 bmap->name, id_num); 121 } 122 123 int qed_bmap_test_id(struct qed_hwfn *p_hwfn, 124 struct qed_bmap *bmap, u32 id_num) 125 { 126 if (id_num >= bmap->max_count) 127 return -1; 128 129 return test_bit(id_num, bmap->bitmap); 130 } 131 132 static bool qed_bmap_is_empty(struct qed_bmap *bmap) 133 { 134 return bmap->max_count == find_first_bit(bmap->bitmap, bmap->max_count); 135 } 136 137 static u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id) 138 { 139 /* First sb id for RoCE is after all the l2 sb */ 140 return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id; 141 } 142 143 int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn) 144 { 145 struct qed_rdma_info *p_rdma_info; 146 147 p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL); 148 if (!p_rdma_info) 149 return -ENOMEM; 150 151 spin_lock_init(&p_rdma_info->lock); 152 153 p_hwfn->p_rdma_info = p_rdma_info; 154 return 0; 155 } 156 157 void qed_rdma_info_free(struct qed_hwfn *p_hwfn) 158 { 159 kfree(p_hwfn->p_rdma_info); 160 p_hwfn->p_rdma_info = NULL; 161 } 162 163 static int qed_rdma_alloc(struct qed_hwfn *p_hwfn) 164 { 165 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 166 u32 num_cons, num_tasks; 167 int rc = -ENOMEM; 168 169 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n"); 170 171 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 172 p_rdma_info->proto = PROTOCOLID_IWARP; 173 else 174 p_rdma_info->proto = PROTOCOLID_ROCE; 175 176 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto, 177 NULL); 178 179 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 180 p_rdma_info->num_qps = num_cons; 181 else 182 p_rdma_info->num_qps = num_cons / 2; /* 2 cids per qp */ 183 184 num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE); 185 186 /* Each MR uses a single task */ 187 p_rdma_info->num_mrs = num_tasks; 188 189 /* Queue zone lines are shared between RoCE and L2 in such a way that 190 * they can be used by each without obstructing the other. 191 */ 192 p_rdma_info->queue_zone_base = (u16)RESC_START(p_hwfn, QED_L2_QUEUE); 193 p_rdma_info->max_queue_zones = (u16)RESC_NUM(p_hwfn, QED_L2_QUEUE); 194 195 /* Allocate a struct with device params and fill it */ 196 p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL); 197 if (!p_rdma_info->dev) 198 return rc; 199 200 /* Allocate a struct with port params and fill it */ 201 p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL); 202 if (!p_rdma_info->port) 203 goto free_rdma_dev; 204 205 /* Allocate bit map for pd's */ 206 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS, 207 "PD"); 208 if (rc) { 209 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 210 "Failed to allocate pd_map, rc = %d\n", 211 rc); 212 goto free_rdma_port; 213 } 214 215 /* Allocate DPI bitmap */ 216 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map, 217 p_hwfn->dpi_count, "DPI"); 218 if (rc) { 219 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 220 "Failed to allocate DPI bitmap, rc = %d\n", rc); 221 goto free_pd_map; 222 } 223 224 /* Allocate bitmap for cq's. The maximum number of CQs is bound to 225 * the number of connections we support. (num_qps in iWARP or 226 * num_qps/2 in RoCE). 227 */ 228 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map, num_cons, "CQ"); 229 if (rc) { 230 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 231 "Failed to allocate cq bitmap, rc = %d\n", rc); 232 goto free_dpi_map; 233 } 234 235 /* Allocate bitmap for toggle bit for cq icids 236 * We toggle the bit every time we create or resize cq for a given icid. 237 * Size needs to equal the size of the cq bmap. 238 */ 239 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits, 240 num_cons, "Toggle"); 241 if (rc) { 242 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 243 "Failed to allocate toggle bits, rc = %d\n", rc); 244 goto free_cq_map; 245 } 246 247 /* Allocate bitmap for itids */ 248 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map, 249 p_rdma_info->num_mrs, "MR"); 250 if (rc) { 251 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 252 "Failed to allocate itids bitmaps, rc = %d\n", rc); 253 goto free_toggle_map; 254 } 255 256 /* Allocate bitmap for cids used for qps. */ 257 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons, 258 "CID"); 259 if (rc) { 260 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 261 "Failed to allocate cid bitmap, rc = %d\n", rc); 262 goto free_tid_map; 263 } 264 265 /* Allocate bitmap for cids used for responders/requesters. */ 266 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->real_cid_map, num_cons, 267 "REAL_CID"); 268 if (rc) { 269 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 270 "Failed to allocate real cid bitmap, rc = %d\n", rc); 271 goto free_cid_map; 272 } 273 274 /* Allocate bitmap for srqs */ 275 p_rdma_info->num_srqs = qed_cxt_get_srq_count(p_hwfn); 276 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->srq_map, 277 p_rdma_info->num_srqs, "SRQ"); 278 if (rc) { 279 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 280 "Failed to allocate srq bitmap, rc = %d\n", rc); 281 goto free_real_cid_map; 282 } 283 284 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 285 rc = qed_iwarp_alloc(p_hwfn); 286 287 if (rc) 288 goto free_srq_map; 289 290 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n"); 291 return 0; 292 293 free_srq_map: 294 kfree(p_rdma_info->srq_map.bitmap); 295 free_real_cid_map: 296 kfree(p_rdma_info->real_cid_map.bitmap); 297 free_cid_map: 298 kfree(p_rdma_info->cid_map.bitmap); 299 free_tid_map: 300 kfree(p_rdma_info->tid_map.bitmap); 301 free_toggle_map: 302 kfree(p_rdma_info->toggle_bits.bitmap); 303 free_cq_map: 304 kfree(p_rdma_info->cq_map.bitmap); 305 free_dpi_map: 306 kfree(p_rdma_info->dpi_map.bitmap); 307 free_pd_map: 308 kfree(p_rdma_info->pd_map.bitmap); 309 free_rdma_port: 310 kfree(p_rdma_info->port); 311 free_rdma_dev: 312 kfree(p_rdma_info->dev); 313 314 return rc; 315 } 316 317 void qed_rdma_bmap_free(struct qed_hwfn *p_hwfn, 318 struct qed_bmap *bmap, bool check) 319 { 320 int weight = bitmap_weight(bmap->bitmap, bmap->max_count); 321 int last_line = bmap->max_count / (64 * 8); 322 int last_item = last_line * 8 + 323 DIV_ROUND_UP(bmap->max_count % (64 * 8), 64); 324 u64 *pmap = (u64 *)bmap->bitmap; 325 int line, item, offset; 326 u8 str_last_line[200] = { 0 }; 327 328 if (!weight || !check) 329 goto end; 330 331 DP_NOTICE(p_hwfn, 332 "%s bitmap not free - size=%d, weight=%d, 512 bits per line\n", 333 bmap->name, bmap->max_count, weight); 334 335 /* print aligned non-zero lines, if any */ 336 for (item = 0, line = 0; line < last_line; line++, item += 8) 337 if (bitmap_weight((unsigned long *)&pmap[item], 64 * 8)) 338 DP_NOTICE(p_hwfn, 339 "line 0x%04x: 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx\n", 340 line, 341 pmap[item], 342 pmap[item + 1], 343 pmap[item + 2], 344 pmap[item + 3], 345 pmap[item + 4], 346 pmap[item + 5], 347 pmap[item + 6], pmap[item + 7]); 348 349 /* print last unaligned non-zero line, if any */ 350 if ((bmap->max_count % (64 * 8)) && 351 (bitmap_weight((unsigned long *)&pmap[item], 352 bmap->max_count - item * 64))) { 353 offset = sprintf(str_last_line, "line 0x%04x: ", line); 354 for (; item < last_item; item++) 355 offset += sprintf(str_last_line + offset, 356 "0x%016llx ", pmap[item]); 357 DP_NOTICE(p_hwfn, "%s\n", str_last_line); 358 } 359 360 end: 361 kfree(bmap->bitmap); 362 bmap->bitmap = NULL; 363 } 364 365 static void qed_rdma_resc_free(struct qed_hwfn *p_hwfn) 366 { 367 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 368 369 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 370 qed_iwarp_resc_free(p_hwfn); 371 372 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cid_map, 1); 373 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->pd_map, 1); 374 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 1); 375 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cq_map, 1); 376 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->toggle_bits, 0); 377 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->tid_map, 1); 378 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->srq_map, 1); 379 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, 1); 380 381 kfree(p_rdma_info->port); 382 kfree(p_rdma_info->dev); 383 } 384 385 static void qed_rdma_free_tid(void *rdma_cxt, u32 itid) 386 { 387 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 388 389 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 390 391 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 392 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->tid_map, itid); 393 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 394 } 395 396 static void qed_rdma_free_reserved_lkey(struct qed_hwfn *p_hwfn) 397 { 398 qed_rdma_free_tid(p_hwfn, p_hwfn->p_rdma_info->dev->reserved_lkey); 399 } 400 401 static void qed_rdma_free(struct qed_hwfn *p_hwfn) 402 { 403 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n"); 404 405 qed_rdma_free_reserved_lkey(p_hwfn); 406 qed_cxt_free_proto_ilt(p_hwfn, p_hwfn->p_rdma_info->proto); 407 qed_rdma_resc_free(p_hwfn); 408 } 409 410 static void qed_rdma_get_guid(struct qed_hwfn *p_hwfn, u8 *guid) 411 { 412 guid[0] = p_hwfn->hw_info.hw_mac_addr[0] ^ 2; 413 guid[1] = p_hwfn->hw_info.hw_mac_addr[1]; 414 guid[2] = p_hwfn->hw_info.hw_mac_addr[2]; 415 guid[3] = 0xff; 416 guid[4] = 0xfe; 417 guid[5] = p_hwfn->hw_info.hw_mac_addr[3]; 418 guid[6] = p_hwfn->hw_info.hw_mac_addr[4]; 419 guid[7] = p_hwfn->hw_info.hw_mac_addr[5]; 420 } 421 422 static void qed_rdma_init_events(struct qed_hwfn *p_hwfn, 423 struct qed_rdma_start_in_params *params) 424 { 425 struct qed_rdma_events *events; 426 427 events = &p_hwfn->p_rdma_info->events; 428 429 events->unaffiliated_event = params->events->unaffiliated_event; 430 events->affiliated_event = params->events->affiliated_event; 431 events->context = params->events->context; 432 } 433 434 static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn, 435 struct qed_rdma_start_in_params *params) 436 { 437 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 438 struct qed_dev *cdev = p_hwfn->cdev; 439 u32 pci_status_control; 440 u32 num_qps; 441 442 /* Vendor specific information */ 443 dev->vendor_id = cdev->vendor_id; 444 dev->vendor_part_id = cdev->device_id; 445 dev->hw_ver = 0; 446 dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | 447 (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION); 448 449 qed_rdma_get_guid(p_hwfn, (u8 *)&dev->sys_image_guid); 450 dev->node_guid = dev->sys_image_guid; 451 452 dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE, 453 RDMA_MAX_SGE_PER_RQ_WQE); 454 455 if (cdev->rdma_max_sge) 456 dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge); 457 458 dev->max_srq_sge = QED_RDMA_MAX_SGE_PER_SRQ_WQE; 459 if (p_hwfn->cdev->rdma_max_srq_sge) { 460 dev->max_srq_sge = min_t(u32, 461 p_hwfn->cdev->rdma_max_srq_sge, 462 dev->max_srq_sge); 463 } 464 dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE; 465 466 dev->max_inline = (cdev->rdma_max_inline) ? 467 min_t(u32, cdev->rdma_max_inline, dev->max_inline) : 468 dev->max_inline; 469 470 dev->max_wqe = QED_RDMA_MAX_WQE; 471 dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ); 472 473 /* The number of QPs may be higher than QED_ROCE_MAX_QPS, because 474 * it is up-aligned to 16 and then to ILT page size within qed cxt. 475 * This is OK in terms of ILT but we don't want to configure the FW 476 * above its abilities 477 */ 478 num_qps = ROCE_MAX_QPS; 479 num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps); 480 dev->max_qp = num_qps; 481 482 /* CQs uses the same icids that QPs use hence they are limited by the 483 * number of icids. There are two icids per QP. 484 */ 485 dev->max_cq = num_qps * 2; 486 487 /* The number of mrs is smaller by 1 since the first is reserved */ 488 dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1; 489 dev->max_mr_size = QED_RDMA_MAX_MR_SIZE; 490 491 /* The maximum CQE capacity per CQ supported. 492 * max number of cqes will be in two layer pbl, 493 * 8 is the pointer size in bytes 494 * 32 is the size of cq element in bytes 495 */ 496 if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS) 497 dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT; 498 else 499 dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT; 500 501 dev->max_mw = 0; 502 dev->max_fmr = QED_RDMA_MAX_FMR; 503 dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8); 504 dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE; 505 dev->max_pkey = QED_RDMA_MAX_P_KEY; 506 507 dev->max_srq = p_hwfn->p_rdma_info->num_srqs; 508 dev->max_srq_wr = QED_RDMA_MAX_SRQ_WQE_ELEM; 509 dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 510 (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2); 511 dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 512 RDMA_REQ_RD_ATOMIC_ELM_SIZE; 513 dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc * 514 p_hwfn->p_rdma_info->num_qps; 515 dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS; 516 dev->dev_ack_delay = QED_RDMA_ACK_DELAY; 517 dev->max_pd = RDMA_MAX_PDS; 518 dev->max_ah = p_hwfn->p_rdma_info->num_qps; 519 dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE); 520 521 /* Set capablities */ 522 dev->dev_caps = 0; 523 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1); 524 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1); 525 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1); 526 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1); 527 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1); 528 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1); 529 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1); 530 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1); 531 532 /* Check atomic operations support in PCI configuration space. */ 533 pcie_capability_read_dword(cdev->pdev, PCI_EXP_DEVCTL2, 534 &pci_status_control); 535 536 if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN) 537 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1); 538 539 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 540 qed_iwarp_init_devinfo(p_hwfn); 541 } 542 543 static void qed_rdma_init_port(struct qed_hwfn *p_hwfn) 544 { 545 struct qed_rdma_port *port = p_hwfn->p_rdma_info->port; 546 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 547 548 port->port_state = p_hwfn->mcp_info->link_output.link_up ? 549 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN; 550 551 port->max_msg_size = min_t(u64, 552 (dev->max_mr_mw_fmr_size * 553 p_hwfn->cdev->rdma_max_sge), 554 BIT(31)); 555 556 port->pkey_bad_counter = 0; 557 } 558 559 static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 560 { 561 int rc = 0; 562 563 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n"); 564 p_hwfn->b_rdma_enabled_in_prs = false; 565 566 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 567 qed_iwarp_init_hw(p_hwfn, p_ptt); 568 else 569 rc = qed_roce_init_hw(p_hwfn, p_ptt); 570 571 return rc; 572 } 573 574 static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn, 575 struct qed_rdma_start_in_params *params, 576 struct qed_ptt *p_ptt) 577 { 578 struct rdma_init_func_ramrod_data *p_ramrod; 579 struct qed_rdma_cnq_params *p_cnq_pbl_list; 580 struct rdma_init_func_hdr *p_params_header; 581 struct rdma_cnq_params *p_cnq_params; 582 struct qed_sp_init_data init_data; 583 struct qed_spq_entry *p_ent; 584 u32 cnq_id, sb_id; 585 u16 igu_sb_id; 586 int rc; 587 588 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n"); 589 590 /* Save the number of cnqs for the function close ramrod */ 591 p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq; 592 593 /* Get SPQ entry */ 594 memset(&init_data, 0, sizeof(init_data)); 595 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 596 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 597 598 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT, 599 p_hwfn->p_rdma_info->proto, &init_data); 600 if (rc) 601 return rc; 602 603 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 604 qed_iwarp_init_fw_ramrod(p_hwfn, 605 &p_ent->ramrod.iwarp_init_func); 606 p_ramrod = &p_ent->ramrod.iwarp_init_func.rdma; 607 } else { 608 p_ramrod = &p_ent->ramrod.roce_init_func.rdma; 609 } 610 611 p_params_header = &p_ramrod->params_header; 612 p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn, 613 QED_RDMA_CNQ_RAM); 614 p_params_header->num_cnqs = params->desired_cnq; 615 616 if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS) 617 p_params_header->cq_ring_mode = 1; 618 else 619 p_params_header->cq_ring_mode = 0; 620 621 for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) { 622 sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id); 623 igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 624 p_ramrod->cnq_params[cnq_id].sb_num = cpu_to_le16(igu_sb_id); 625 p_cnq_params = &p_ramrod->cnq_params[cnq_id]; 626 p_cnq_pbl_list = ¶ms->cnq_pbl_list[cnq_id]; 627 628 p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi; 629 p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages; 630 631 DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr, 632 p_cnq_pbl_list->pbl_ptr); 633 634 /* we assume here that cnq_id and qz_offset are the same */ 635 p_cnq_params->queue_zone_num = 636 cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base + 637 cnq_id); 638 } 639 640 return qed_spq_post(p_hwfn, p_ent, NULL); 641 } 642 643 static int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid) 644 { 645 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 646 int rc; 647 648 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n"); 649 650 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 651 rc = qed_rdma_bmap_alloc_id(p_hwfn, 652 &p_hwfn->p_rdma_info->tid_map, itid); 653 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 654 if (rc) 655 goto out; 656 657 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid); 658 out: 659 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc); 660 return rc; 661 } 662 663 static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn) 664 { 665 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 666 667 /* Tid 0 will be used as the key for "reserved MR". 668 * The driver should allocate memory for it so it can be loaded but no 669 * ramrod should be passed on it. 670 */ 671 qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey); 672 if (dev->reserved_lkey != RDMA_RESERVED_LKEY) { 673 DP_NOTICE(p_hwfn, 674 "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n"); 675 return -EINVAL; 676 } 677 678 return 0; 679 } 680 681 static int qed_rdma_setup(struct qed_hwfn *p_hwfn, 682 struct qed_ptt *p_ptt, 683 struct qed_rdma_start_in_params *params) 684 { 685 int rc; 686 687 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n"); 688 689 qed_rdma_init_devinfo(p_hwfn, params); 690 qed_rdma_init_port(p_hwfn); 691 qed_rdma_init_events(p_hwfn, params); 692 693 rc = qed_rdma_reserve_lkey(p_hwfn); 694 if (rc) 695 return rc; 696 697 rc = qed_rdma_init_hw(p_hwfn, p_ptt); 698 if (rc) 699 return rc; 700 701 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 702 rc = qed_iwarp_setup(p_hwfn, params); 703 if (rc) 704 return rc; 705 } else { 706 rc = qed_roce_setup(p_hwfn); 707 if (rc) 708 return rc; 709 } 710 711 return qed_rdma_start_fw(p_hwfn, params, p_ptt); 712 } 713 714 static int qed_rdma_stop(void *rdma_cxt) 715 { 716 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 717 struct rdma_close_func_ramrod_data *p_ramrod; 718 struct qed_sp_init_data init_data; 719 struct qed_spq_entry *p_ent; 720 struct qed_ptt *p_ptt; 721 u32 ll2_ethertype_en; 722 int rc = -EBUSY; 723 724 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n"); 725 726 p_ptt = qed_ptt_acquire(p_hwfn); 727 if (!p_ptt) { 728 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n"); 729 return rc; 730 } 731 732 /* Disable RoCE search */ 733 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0); 734 p_hwfn->b_rdma_enabled_in_prs = false; 735 p_hwfn->p_rdma_info->active = 0; 736 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 737 738 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 739 740 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 741 (ll2_ethertype_en & 0xFFFE)); 742 743 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 744 rc = qed_iwarp_stop(p_hwfn); 745 if (rc) { 746 qed_ptt_release(p_hwfn, p_ptt); 747 return rc; 748 } 749 } else { 750 qed_roce_stop(p_hwfn); 751 } 752 753 qed_ptt_release(p_hwfn, p_ptt); 754 755 /* Get SPQ entry */ 756 memset(&init_data, 0, sizeof(init_data)); 757 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 758 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 759 760 /* Stop RoCE */ 761 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE, 762 p_hwfn->p_rdma_info->proto, &init_data); 763 if (rc) 764 goto out; 765 766 p_ramrod = &p_ent->ramrod.rdma_close_func; 767 768 p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs; 769 p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM); 770 771 rc = qed_spq_post(p_hwfn, p_ent, NULL); 772 773 out: 774 qed_rdma_free(p_hwfn); 775 776 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc); 777 return rc; 778 } 779 780 static int qed_rdma_add_user(void *rdma_cxt, 781 struct qed_rdma_add_user_out_params *out_params) 782 { 783 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 784 u32 dpi_start_offset; 785 u32 returned_id = 0; 786 int rc; 787 788 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n"); 789 790 /* Allocate DPI */ 791 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 792 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 793 &returned_id); 794 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 795 796 out_params->dpi = (u16)returned_id; 797 798 /* Calculate the corresponding DPI address */ 799 dpi_start_offset = p_hwfn->dpi_start_offset; 800 801 out_params->dpi_addr = (u64)((u8 __iomem *)p_hwfn->doorbells + 802 dpi_start_offset + 803 ((out_params->dpi) * p_hwfn->dpi_size)); 804 805 out_params->dpi_phys_addr = p_hwfn->db_phys_addr + 806 dpi_start_offset + 807 ((out_params->dpi) * p_hwfn->dpi_size); 808 809 out_params->dpi_size = p_hwfn->dpi_size; 810 out_params->wid_count = p_hwfn->wid_count; 811 812 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc); 813 return rc; 814 } 815 816 static struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt) 817 { 818 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 819 struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port; 820 struct qed_mcp_link_state *p_link_output; 821 822 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n"); 823 824 /* The link state is saved only for the leading hwfn */ 825 p_link_output = &QED_LEADING_HWFN(p_hwfn->cdev)->mcp_info->link_output; 826 827 p_port->port_state = p_link_output->link_up ? QED_RDMA_PORT_UP 828 : QED_RDMA_PORT_DOWN; 829 830 p_port->link_speed = p_link_output->speed; 831 832 p_port->max_msg_size = RDMA_MAX_DATA_SIZE_IN_WQE; 833 834 return p_port; 835 } 836 837 static struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt) 838 { 839 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 840 841 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n"); 842 843 /* Return struct with device parameters */ 844 return p_hwfn->p_rdma_info->dev; 845 } 846 847 static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod) 848 { 849 struct qed_hwfn *p_hwfn; 850 u16 qz_num; 851 u32 addr; 852 853 p_hwfn = (struct qed_hwfn *)rdma_cxt; 854 855 if (qz_offset > p_hwfn->p_rdma_info->max_queue_zones) { 856 DP_NOTICE(p_hwfn, 857 "queue zone offset %d is too large (max is %d)\n", 858 qz_offset, p_hwfn->p_rdma_info->max_queue_zones); 859 return; 860 } 861 862 qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset; 863 addr = GTT_BAR0_MAP_REG_USDM_RAM + 864 USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num); 865 866 REG_WR16(p_hwfn, addr, prod); 867 868 /* keep prod updates ordered */ 869 wmb(); 870 } 871 872 static int qed_fill_rdma_dev_info(struct qed_dev *cdev, 873 struct qed_dev_rdma_info *info) 874 { 875 struct qed_hwfn *p_hwfn = QED_AFFIN_HWFN(cdev); 876 877 memset(info, 0, sizeof(*info)); 878 879 info->rdma_type = QED_IS_ROCE_PERSONALITY(p_hwfn) ? 880 QED_RDMA_TYPE_ROCE : QED_RDMA_TYPE_IWARP; 881 882 info->user_dpm_enabled = (p_hwfn->db_bar_no_edpm == 0); 883 884 qed_fill_dev_info(cdev, &info->common); 885 886 return 0; 887 } 888 889 static int qed_rdma_get_sb_start(struct qed_dev *cdev) 890 { 891 int feat_num; 892 893 if (cdev->num_hwfns > 1) 894 feat_num = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_PF_L2_QUE); 895 else 896 feat_num = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_PF_L2_QUE) * 897 cdev->num_hwfns; 898 899 return feat_num; 900 } 901 902 static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev) 903 { 904 int n_cnq = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_RDMA_CNQ); 905 int n_msix = cdev->int_params.rdma_msix_cnt; 906 907 return min_t(int, n_cnq, n_msix); 908 } 909 910 static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt) 911 { 912 int limit = 0; 913 914 /* Mark the fastpath as free/used */ 915 cdev->int_params.fp_initialized = cnt ? true : false; 916 917 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) { 918 DP_ERR(cdev, 919 "qed roce supports only MSI-X interrupts (detected %d).\n", 920 cdev->int_params.out.int_mode); 921 return -EINVAL; 922 } else if (cdev->int_params.fp_msix_cnt) { 923 limit = cdev->int_params.rdma_msix_cnt; 924 } 925 926 if (!limit) 927 return -ENOMEM; 928 929 return min_t(int, cnt, limit); 930 } 931 932 static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info) 933 { 934 memset(info, 0, sizeof(*info)); 935 936 if (!cdev->int_params.fp_initialized) { 937 DP_INFO(cdev, 938 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 939 return -EINVAL; 940 } 941 942 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 943 int msix_base = cdev->int_params.rdma_msix_base; 944 945 info->msix_cnt = cdev->int_params.rdma_msix_cnt; 946 info->msix = &cdev->int_params.msix_table[msix_base]; 947 948 DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n", 949 info->msix_cnt, msix_base); 950 } 951 952 return 0; 953 } 954 955 static int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd) 956 { 957 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 958 u32 returned_id; 959 int rc; 960 961 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n"); 962 963 /* Allocates an unused protection domain */ 964 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 965 rc = qed_rdma_bmap_alloc_id(p_hwfn, 966 &p_hwfn->p_rdma_info->pd_map, &returned_id); 967 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 968 969 *pd = (u16)returned_id; 970 971 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc); 972 return rc; 973 } 974 975 static void qed_rdma_free_pd(void *rdma_cxt, u16 pd) 976 { 977 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 978 979 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd); 980 981 /* Returns a previously allocated protection domain for reuse */ 982 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 983 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd); 984 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 985 } 986 987 static enum qed_rdma_toggle_bit 988 qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid) 989 { 990 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 991 enum qed_rdma_toggle_bit toggle_bit; 992 u32 bmap_id; 993 994 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid); 995 996 /* the function toggle the bit that is related to a given icid 997 * and returns the new toggle bit's value 998 */ 999 bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto); 1000 1001 spin_lock_bh(&p_info->lock); 1002 toggle_bit = !test_and_change_bit(bmap_id, 1003 p_info->toggle_bits.bitmap); 1004 spin_unlock_bh(&p_info->lock); 1005 1006 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n", 1007 toggle_bit); 1008 1009 return toggle_bit; 1010 } 1011 1012 static int qed_rdma_create_cq(void *rdma_cxt, 1013 struct qed_rdma_create_cq_in_params *params, 1014 u16 *icid) 1015 { 1016 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1017 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 1018 struct rdma_create_cq_ramrod_data *p_ramrod; 1019 enum qed_rdma_toggle_bit toggle_bit; 1020 struct qed_sp_init_data init_data; 1021 struct qed_spq_entry *p_ent; 1022 u32 returned_id, start_cid; 1023 int rc; 1024 1025 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n", 1026 params->cq_handle_hi, params->cq_handle_lo); 1027 1028 /* Allocate icid */ 1029 spin_lock_bh(&p_info->lock); 1030 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_info->cq_map, &returned_id); 1031 spin_unlock_bh(&p_info->lock); 1032 1033 if (rc) { 1034 DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc); 1035 return rc; 1036 } 1037 1038 start_cid = qed_cxt_get_proto_cid_start(p_hwfn, 1039 p_info->proto); 1040 *icid = returned_id + start_cid; 1041 1042 /* Check if icid requires a page allocation */ 1043 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid); 1044 if (rc) 1045 goto err; 1046 1047 /* Get SPQ entry */ 1048 memset(&init_data, 0, sizeof(init_data)); 1049 init_data.cid = *icid; 1050 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1051 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1052 1053 /* Send create CQ ramrod */ 1054 rc = qed_sp_init_request(p_hwfn, &p_ent, 1055 RDMA_RAMROD_CREATE_CQ, 1056 p_info->proto, &init_data); 1057 if (rc) 1058 goto err; 1059 1060 p_ramrod = &p_ent->ramrod.rdma_create_cq; 1061 1062 p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi); 1063 p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo); 1064 p_ramrod->dpi = cpu_to_le16(params->dpi); 1065 p_ramrod->is_two_level_pbl = params->pbl_two_level; 1066 p_ramrod->max_cqes = cpu_to_le32(params->cq_size); 1067 DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr); 1068 p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages); 1069 p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) + 1070 params->cnq_id; 1071 p_ramrod->int_timeout = params->int_timeout; 1072 1073 /* toggle the bit for every resize or create cq for a given icid */ 1074 toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 1075 1076 p_ramrod->toggle_bit = toggle_bit; 1077 1078 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1079 if (rc) { 1080 /* restore toggle bit */ 1081 qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 1082 goto err; 1083 } 1084 1085 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc); 1086 return rc; 1087 1088 err: 1089 /* release allocated icid */ 1090 spin_lock_bh(&p_info->lock); 1091 qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id); 1092 spin_unlock_bh(&p_info->lock); 1093 DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc); 1094 1095 return rc; 1096 } 1097 1098 static int 1099 qed_rdma_destroy_cq(void *rdma_cxt, 1100 struct qed_rdma_destroy_cq_in_params *in_params, 1101 struct qed_rdma_destroy_cq_out_params *out_params) 1102 { 1103 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1104 struct rdma_destroy_cq_output_params *p_ramrod_res; 1105 struct rdma_destroy_cq_ramrod_data *p_ramrod; 1106 struct qed_sp_init_data init_data; 1107 struct qed_spq_entry *p_ent; 1108 dma_addr_t ramrod_res_phys; 1109 enum protocol_type proto; 1110 int rc = -ENOMEM; 1111 1112 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid); 1113 1114 p_ramrod_res = 1115 (struct rdma_destroy_cq_output_params *) 1116 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1117 sizeof(struct rdma_destroy_cq_output_params), 1118 &ramrod_res_phys, GFP_KERNEL); 1119 if (!p_ramrod_res) { 1120 DP_NOTICE(p_hwfn, 1121 "qed destroy cq failed: cannot allocate memory (ramrod)\n"); 1122 return rc; 1123 } 1124 1125 /* Get SPQ entry */ 1126 memset(&init_data, 0, sizeof(init_data)); 1127 init_data.cid = in_params->icid; 1128 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1129 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1130 proto = p_hwfn->p_rdma_info->proto; 1131 /* Send destroy CQ ramrod */ 1132 rc = qed_sp_init_request(p_hwfn, &p_ent, 1133 RDMA_RAMROD_DESTROY_CQ, 1134 proto, &init_data); 1135 if (rc) 1136 goto err; 1137 1138 p_ramrod = &p_ent->ramrod.rdma_destroy_cq; 1139 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1140 1141 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1142 if (rc) 1143 goto err; 1144 1145 out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num); 1146 1147 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1148 sizeof(struct rdma_destroy_cq_output_params), 1149 p_ramrod_res, ramrod_res_phys); 1150 1151 /* Free icid */ 1152 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1153 1154 qed_bmap_release_id(p_hwfn, 1155 &p_hwfn->p_rdma_info->cq_map, 1156 (in_params->icid - 1157 qed_cxt_get_proto_cid_start(p_hwfn, proto))); 1158 1159 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1160 1161 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc); 1162 return rc; 1163 1164 err: dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1165 sizeof(struct rdma_destroy_cq_output_params), 1166 p_ramrod_res, ramrod_res_phys); 1167 1168 return rc; 1169 } 1170 1171 void qed_rdma_set_fw_mac(u16 *p_fw_mac, u8 *p_qed_mac) 1172 { 1173 p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]); 1174 p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]); 1175 p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]); 1176 } 1177 1178 static int qed_rdma_query_qp(void *rdma_cxt, 1179 struct qed_rdma_qp *qp, 1180 struct qed_rdma_query_qp_out_params *out_params) 1181 { 1182 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1183 int rc = 0; 1184 1185 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1186 1187 /* The following fields are filled in from qp and not FW as they can't 1188 * be modified by FW 1189 */ 1190 out_params->mtu = qp->mtu; 1191 out_params->dest_qp = qp->dest_qp; 1192 out_params->incoming_atomic_en = qp->incoming_atomic_en; 1193 out_params->e2e_flow_control_en = qp->e2e_flow_control_en; 1194 out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en; 1195 out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en; 1196 out_params->dgid = qp->dgid; 1197 out_params->flow_label = qp->flow_label; 1198 out_params->hop_limit_ttl = qp->hop_limit_ttl; 1199 out_params->traffic_class_tos = qp->traffic_class_tos; 1200 out_params->timeout = qp->ack_timeout; 1201 out_params->rnr_retry = qp->rnr_retry_cnt; 1202 out_params->retry_cnt = qp->retry_cnt; 1203 out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer; 1204 out_params->pkey_index = 0; 1205 out_params->max_rd_atomic = qp->max_rd_atomic_req; 1206 out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp; 1207 out_params->sqd_async = qp->sqd_async; 1208 1209 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 1210 qed_iwarp_query_qp(qp, out_params); 1211 else 1212 rc = qed_roce_query_qp(p_hwfn, qp, out_params); 1213 1214 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc); 1215 return rc; 1216 } 1217 1218 static int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp) 1219 { 1220 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1221 int rc = 0; 1222 1223 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1224 1225 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 1226 rc = qed_iwarp_destroy_qp(p_hwfn, qp); 1227 else 1228 rc = qed_roce_destroy_qp(p_hwfn, qp); 1229 1230 /* free qp params struct */ 1231 kfree(qp); 1232 1233 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n"); 1234 return rc; 1235 } 1236 1237 static struct qed_rdma_qp * 1238 qed_rdma_create_qp(void *rdma_cxt, 1239 struct qed_rdma_create_qp_in_params *in_params, 1240 struct qed_rdma_create_qp_out_params *out_params) 1241 { 1242 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1243 struct qed_rdma_qp *qp; 1244 u8 max_stats_queues; 1245 int rc; 1246 1247 if (!rdma_cxt || !in_params || !out_params || 1248 !p_hwfn->p_rdma_info->active) { 1249 DP_ERR(p_hwfn->cdev, 1250 "qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n", 1251 rdma_cxt, in_params, out_params); 1252 return NULL; 1253 } 1254 1255 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1256 "qed rdma create qp called with qp_handle = %08x%08x\n", 1257 in_params->qp_handle_hi, in_params->qp_handle_lo); 1258 1259 /* Some sanity checks... */ 1260 max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues; 1261 if (in_params->stats_queue >= max_stats_queues) { 1262 DP_ERR(p_hwfn->cdev, 1263 "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n", 1264 in_params->stats_queue, max_stats_queues); 1265 return NULL; 1266 } 1267 1268 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 1269 if (in_params->sq_num_pages * sizeof(struct regpair) > 1270 IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE) { 1271 DP_NOTICE(p_hwfn->cdev, 1272 "Sq num pages: %d exceeds maximum\n", 1273 in_params->sq_num_pages); 1274 return NULL; 1275 } 1276 if (in_params->rq_num_pages * sizeof(struct regpair) > 1277 IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE) { 1278 DP_NOTICE(p_hwfn->cdev, 1279 "Rq num pages: %d exceeds maximum\n", 1280 in_params->rq_num_pages); 1281 return NULL; 1282 } 1283 } 1284 1285 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1286 if (!qp) 1287 return NULL; 1288 1289 qp->cur_state = QED_ROCE_QP_STATE_RESET; 1290 qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi); 1291 qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo); 1292 qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi); 1293 qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo); 1294 qp->use_srq = in_params->use_srq; 1295 qp->signal_all = in_params->signal_all; 1296 qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey; 1297 qp->pd = in_params->pd; 1298 qp->dpi = in_params->dpi; 1299 qp->sq_cq_id = in_params->sq_cq_id; 1300 qp->sq_num_pages = in_params->sq_num_pages; 1301 qp->sq_pbl_ptr = in_params->sq_pbl_ptr; 1302 qp->rq_cq_id = in_params->rq_cq_id; 1303 qp->rq_num_pages = in_params->rq_num_pages; 1304 qp->rq_pbl_ptr = in_params->rq_pbl_ptr; 1305 qp->srq_id = in_params->srq_id; 1306 qp->req_offloaded = false; 1307 qp->resp_offloaded = false; 1308 qp->e2e_flow_control_en = qp->use_srq ? false : true; 1309 qp->stats_queue = in_params->stats_queue; 1310 1311 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 1312 rc = qed_iwarp_create_qp(p_hwfn, qp, out_params); 1313 qp->qpid = qp->icid; 1314 } else { 1315 rc = qed_roce_alloc_cid(p_hwfn, &qp->icid); 1316 qp->qpid = ((0xFF << 16) | qp->icid); 1317 } 1318 1319 if (rc) { 1320 kfree(qp); 1321 return NULL; 1322 } 1323 1324 out_params->icid = qp->icid; 1325 out_params->qp_id = qp->qpid; 1326 1327 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc); 1328 return qp; 1329 } 1330 1331 static int qed_rdma_modify_qp(void *rdma_cxt, 1332 struct qed_rdma_qp *qp, 1333 struct qed_rdma_modify_qp_in_params *params) 1334 { 1335 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1336 enum qed_roce_qp_state prev_state; 1337 int rc = 0; 1338 1339 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n", 1340 qp->icid, params->new_state); 1341 1342 if (rc) { 1343 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1344 return rc; 1345 } 1346 1347 if (GET_FIELD(params->modify_flags, 1348 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) { 1349 qp->incoming_rdma_read_en = params->incoming_rdma_read_en; 1350 qp->incoming_rdma_write_en = params->incoming_rdma_write_en; 1351 qp->incoming_atomic_en = params->incoming_atomic_en; 1352 } 1353 1354 /* Update QP structure with the updated values */ 1355 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE)) 1356 qp->roce_mode = params->roce_mode; 1357 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)) 1358 qp->pkey = params->pkey; 1359 if (GET_FIELD(params->modify_flags, 1360 QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN)) 1361 qp->e2e_flow_control_en = params->e2e_flow_control_en; 1362 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP)) 1363 qp->dest_qp = params->dest_qp; 1364 if (GET_FIELD(params->modify_flags, 1365 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) { 1366 /* Indicates that the following parameters have changed: 1367 * Traffic class, flow label, hop limit, source GID, 1368 * destination GID, loopback indicator 1369 */ 1370 qp->traffic_class_tos = params->traffic_class_tos; 1371 qp->flow_label = params->flow_label; 1372 qp->hop_limit_ttl = params->hop_limit_ttl; 1373 1374 qp->sgid = params->sgid; 1375 qp->dgid = params->dgid; 1376 qp->udp_src_port = 0; 1377 qp->vlan_id = params->vlan_id; 1378 qp->mtu = params->mtu; 1379 qp->lb_indication = params->lb_indication; 1380 memcpy((u8 *)&qp->remote_mac_addr[0], 1381 (u8 *)¶ms->remote_mac_addr[0], ETH_ALEN); 1382 if (params->use_local_mac) { 1383 memcpy((u8 *)&qp->local_mac_addr[0], 1384 (u8 *)¶ms->local_mac_addr[0], ETH_ALEN); 1385 } else { 1386 memcpy((u8 *)&qp->local_mac_addr[0], 1387 (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN); 1388 } 1389 } 1390 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN)) 1391 qp->rq_psn = params->rq_psn; 1392 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN)) 1393 qp->sq_psn = params->sq_psn; 1394 if (GET_FIELD(params->modify_flags, 1395 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)) 1396 qp->max_rd_atomic_req = params->max_rd_atomic_req; 1397 if (GET_FIELD(params->modify_flags, 1398 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)) 1399 qp->max_rd_atomic_resp = params->max_rd_atomic_resp; 1400 if (GET_FIELD(params->modify_flags, 1401 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)) 1402 qp->ack_timeout = params->ack_timeout; 1403 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)) 1404 qp->retry_cnt = params->retry_cnt; 1405 if (GET_FIELD(params->modify_flags, 1406 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)) 1407 qp->rnr_retry_cnt = params->rnr_retry_cnt; 1408 if (GET_FIELD(params->modify_flags, 1409 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)) 1410 qp->min_rnr_nak_timer = params->min_rnr_nak_timer; 1411 1412 qp->sqd_async = params->sqd_async; 1413 1414 prev_state = qp->cur_state; 1415 if (GET_FIELD(params->modify_flags, 1416 QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) { 1417 qp->cur_state = params->new_state; 1418 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n", 1419 qp->cur_state); 1420 } 1421 1422 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 1423 enum qed_iwarp_qp_state new_state = 1424 qed_roce2iwarp_state(qp->cur_state); 1425 1426 rc = qed_iwarp_modify_qp(p_hwfn, qp, new_state, 0); 1427 } else { 1428 rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params); 1429 } 1430 1431 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc); 1432 return rc; 1433 } 1434 1435 static int 1436 qed_rdma_register_tid(void *rdma_cxt, 1437 struct qed_rdma_register_tid_in_params *params) 1438 { 1439 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1440 struct rdma_register_tid_ramrod_data *p_ramrod; 1441 struct qed_sp_init_data init_data; 1442 struct qed_spq_entry *p_ent; 1443 enum rdma_tid_type tid_type; 1444 u8 fw_return_code; 1445 int rc; 1446 1447 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", params->itid); 1448 1449 /* Get SPQ entry */ 1450 memset(&init_data, 0, sizeof(init_data)); 1451 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1452 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1453 1454 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_REGISTER_MR, 1455 p_hwfn->p_rdma_info->proto, &init_data); 1456 if (rc) { 1457 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1458 return rc; 1459 } 1460 1461 if (p_hwfn->p_rdma_info->last_tid < params->itid) 1462 p_hwfn->p_rdma_info->last_tid = params->itid; 1463 1464 p_ramrod = &p_ent->ramrod.rdma_register_tid; 1465 1466 p_ramrod->flags = 0; 1467 SET_FIELD(p_ramrod->flags, 1468 RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL, 1469 params->pbl_two_level); 1470 1471 SET_FIELD(p_ramrod->flags, 1472 RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED, params->zbva); 1473 1474 SET_FIELD(p_ramrod->flags, 1475 RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR, params->phy_mr); 1476 1477 /* Don't initialize D/C field, as it may override other bits. */ 1478 if (!(params->tid_type == QED_RDMA_TID_FMR) && !(params->dma_mr)) 1479 SET_FIELD(p_ramrod->flags, 1480 RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG, 1481 params->page_size_log - 12); 1482 1483 SET_FIELD(p_ramrod->flags, 1484 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ, 1485 params->remote_read); 1486 1487 SET_FIELD(p_ramrod->flags, 1488 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE, 1489 params->remote_write); 1490 1491 SET_FIELD(p_ramrod->flags, 1492 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC, 1493 params->remote_atomic); 1494 1495 SET_FIELD(p_ramrod->flags, 1496 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE, 1497 params->local_write); 1498 1499 SET_FIELD(p_ramrod->flags, 1500 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ, params->local_read); 1501 1502 SET_FIELD(p_ramrod->flags, 1503 RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND, 1504 params->mw_bind); 1505 1506 SET_FIELD(p_ramrod->flags1, 1507 RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG, 1508 params->pbl_page_size_log - 12); 1509 1510 SET_FIELD(p_ramrod->flags2, 1511 RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR, params->dma_mr); 1512 1513 switch (params->tid_type) { 1514 case QED_RDMA_TID_REGISTERED_MR: 1515 tid_type = RDMA_TID_REGISTERED_MR; 1516 break; 1517 case QED_RDMA_TID_FMR: 1518 tid_type = RDMA_TID_FMR; 1519 break; 1520 case QED_RDMA_TID_MW: 1521 tid_type = RDMA_TID_MW; 1522 break; 1523 default: 1524 rc = -EINVAL; 1525 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1526 qed_sp_destroy_request(p_hwfn, p_ent); 1527 return rc; 1528 } 1529 SET_FIELD(p_ramrod->flags1, 1530 RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE, tid_type); 1531 1532 p_ramrod->itid = cpu_to_le32(params->itid); 1533 p_ramrod->key = params->key; 1534 p_ramrod->pd = cpu_to_le16(params->pd); 1535 p_ramrod->length_hi = (u8)(params->length >> 32); 1536 p_ramrod->length_lo = DMA_LO_LE(params->length); 1537 if (params->zbva) { 1538 /* Lower 32 bits of the registered MR address. 1539 * In case of zero based MR, will hold FBO 1540 */ 1541 p_ramrod->va.hi = 0; 1542 p_ramrod->va.lo = cpu_to_le32(params->fbo); 1543 } else { 1544 DMA_REGPAIR_LE(p_ramrod->va, params->vaddr); 1545 } 1546 DMA_REGPAIR_LE(p_ramrod->pbl_base, params->pbl_ptr); 1547 1548 /* DIF */ 1549 if (params->dif_enabled) { 1550 SET_FIELD(p_ramrod->flags2, 1551 RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG, 1); 1552 DMA_REGPAIR_LE(p_ramrod->dif_error_addr, 1553 params->dif_error_addr); 1554 } 1555 1556 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 1557 if (rc) 1558 return rc; 1559 1560 if (fw_return_code != RDMA_RETURN_OK) { 1561 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 1562 return -EINVAL; 1563 } 1564 1565 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Register TID, rc = %d\n", rc); 1566 return rc; 1567 } 1568 1569 static int qed_rdma_deregister_tid(void *rdma_cxt, u32 itid) 1570 { 1571 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1572 struct rdma_deregister_tid_ramrod_data *p_ramrod; 1573 struct qed_sp_init_data init_data; 1574 struct qed_spq_entry *p_ent; 1575 struct qed_ptt *p_ptt; 1576 u8 fw_return_code; 1577 int rc; 1578 1579 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 1580 1581 /* Get SPQ entry */ 1582 memset(&init_data, 0, sizeof(init_data)); 1583 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1584 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1585 1586 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_DEREGISTER_MR, 1587 p_hwfn->p_rdma_info->proto, &init_data); 1588 if (rc) { 1589 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1590 return rc; 1591 } 1592 1593 p_ramrod = &p_ent->ramrod.rdma_deregister_tid; 1594 p_ramrod->itid = cpu_to_le32(itid); 1595 1596 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 1597 if (rc) { 1598 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1599 return rc; 1600 } 1601 1602 if (fw_return_code == RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR) { 1603 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 1604 return -EINVAL; 1605 } else if (fw_return_code == RDMA_RETURN_NIG_DRAIN_REQ) { 1606 /* Bit indicating that the TID is in use and a nig drain is 1607 * required before sending the ramrod again 1608 */ 1609 p_ptt = qed_ptt_acquire(p_hwfn); 1610 if (!p_ptt) { 1611 rc = -EBUSY; 1612 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1613 "Failed to acquire PTT\n"); 1614 return rc; 1615 } 1616 1617 rc = qed_mcp_drain(p_hwfn, p_ptt); 1618 if (rc) { 1619 qed_ptt_release(p_hwfn, p_ptt); 1620 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1621 "Drain failed\n"); 1622 return rc; 1623 } 1624 1625 qed_ptt_release(p_hwfn, p_ptt); 1626 1627 /* Resend the ramrod */ 1628 rc = qed_sp_init_request(p_hwfn, &p_ent, 1629 RDMA_RAMROD_DEREGISTER_MR, 1630 p_hwfn->p_rdma_info->proto, 1631 &init_data); 1632 if (rc) { 1633 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1634 "Failed to init sp-element\n"); 1635 return rc; 1636 } 1637 1638 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 1639 if (rc) { 1640 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1641 "Ramrod failed\n"); 1642 return rc; 1643 } 1644 1645 if (fw_return_code != RDMA_RETURN_OK) { 1646 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", 1647 fw_return_code); 1648 return rc; 1649 } 1650 } 1651 1652 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "De-registered TID, rc = %d\n", rc); 1653 return rc; 1654 } 1655 1656 static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev) 1657 { 1658 return QED_AFFIN_HWFN(cdev); 1659 } 1660 1661 static int qed_rdma_modify_srq(void *rdma_cxt, 1662 struct qed_rdma_modify_srq_in_params *in_params) 1663 { 1664 struct rdma_srq_modify_ramrod_data *p_ramrod; 1665 struct qed_sp_init_data init_data = {}; 1666 struct qed_hwfn *p_hwfn = rdma_cxt; 1667 struct qed_spq_entry *p_ent; 1668 u16 opaque_fid; 1669 int rc; 1670 1671 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1672 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1673 1674 rc = qed_sp_init_request(p_hwfn, &p_ent, 1675 RDMA_RAMROD_MODIFY_SRQ, 1676 p_hwfn->p_rdma_info->proto, &init_data); 1677 if (rc) 1678 return rc; 1679 1680 p_ramrod = &p_ent->ramrod.rdma_modify_srq; 1681 p_ramrod->srq_id.srq_idx = cpu_to_le16(in_params->srq_id); 1682 opaque_fid = p_hwfn->hw_info.opaque_fid; 1683 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid); 1684 p_ramrod->wqe_limit = cpu_to_le32(in_params->wqe_limit); 1685 1686 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1687 if (rc) 1688 return rc; 1689 1690 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "modified SRQ id = %x", 1691 in_params->srq_id); 1692 1693 return rc; 1694 } 1695 1696 static int 1697 qed_rdma_destroy_srq(void *rdma_cxt, 1698 struct qed_rdma_destroy_srq_in_params *in_params) 1699 { 1700 struct rdma_srq_destroy_ramrod_data *p_ramrod; 1701 struct qed_sp_init_data init_data = {}; 1702 struct qed_hwfn *p_hwfn = rdma_cxt; 1703 struct qed_spq_entry *p_ent; 1704 struct qed_bmap *bmap; 1705 u16 opaque_fid; 1706 int rc; 1707 1708 opaque_fid = p_hwfn->hw_info.opaque_fid; 1709 1710 init_data.opaque_fid = opaque_fid; 1711 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1712 1713 rc = qed_sp_init_request(p_hwfn, &p_ent, 1714 RDMA_RAMROD_DESTROY_SRQ, 1715 p_hwfn->p_rdma_info->proto, &init_data); 1716 if (rc) 1717 return rc; 1718 1719 p_ramrod = &p_ent->ramrod.rdma_destroy_srq; 1720 p_ramrod->srq_id.srq_idx = cpu_to_le16(in_params->srq_id); 1721 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid); 1722 1723 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1724 if (rc) 1725 return rc; 1726 1727 bmap = &p_hwfn->p_rdma_info->srq_map; 1728 1729 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1730 qed_bmap_release_id(p_hwfn, bmap, in_params->srq_id); 1731 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1732 1733 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "SRQ destroyed Id = %x", 1734 in_params->srq_id); 1735 1736 return rc; 1737 } 1738 1739 static int 1740 qed_rdma_create_srq(void *rdma_cxt, 1741 struct qed_rdma_create_srq_in_params *in_params, 1742 struct qed_rdma_create_srq_out_params *out_params) 1743 { 1744 struct rdma_srq_create_ramrod_data *p_ramrod; 1745 struct qed_sp_init_data init_data = {}; 1746 struct qed_hwfn *p_hwfn = rdma_cxt; 1747 enum qed_cxt_elem_type elem_type; 1748 struct qed_spq_entry *p_ent; 1749 u16 opaque_fid, srq_id; 1750 struct qed_bmap *bmap; 1751 u32 returned_id; 1752 int rc; 1753 1754 bmap = &p_hwfn->p_rdma_info->srq_map; 1755 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1756 rc = qed_rdma_bmap_alloc_id(p_hwfn, bmap, &returned_id); 1757 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1758 1759 if (rc) { 1760 DP_NOTICE(p_hwfn, "failed to allocate srq id\n"); 1761 return rc; 1762 } 1763 1764 elem_type = QED_ELEM_SRQ; 1765 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, elem_type, returned_id); 1766 if (rc) 1767 goto err; 1768 /* returned id is no greater than u16 */ 1769 srq_id = (u16)returned_id; 1770 opaque_fid = p_hwfn->hw_info.opaque_fid; 1771 1772 opaque_fid = p_hwfn->hw_info.opaque_fid; 1773 init_data.opaque_fid = opaque_fid; 1774 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1775 1776 rc = qed_sp_init_request(p_hwfn, &p_ent, 1777 RDMA_RAMROD_CREATE_SRQ, 1778 p_hwfn->p_rdma_info->proto, &init_data); 1779 if (rc) 1780 goto err; 1781 1782 p_ramrod = &p_ent->ramrod.rdma_create_srq; 1783 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, in_params->pbl_base_addr); 1784 p_ramrod->pages_in_srq_pbl = cpu_to_le16(in_params->num_pages); 1785 p_ramrod->pd_id = cpu_to_le16(in_params->pd_id); 1786 p_ramrod->srq_id.srq_idx = cpu_to_le16(srq_id); 1787 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid); 1788 p_ramrod->page_size = cpu_to_le16(in_params->page_size); 1789 DMA_REGPAIR_LE(p_ramrod->producers_addr, in_params->prod_pair_addr); 1790 1791 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1792 if (rc) 1793 goto err; 1794 1795 out_params->srq_id = srq_id; 1796 1797 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1798 "SRQ created Id = %x\n", out_params->srq_id); 1799 1800 return rc; 1801 1802 err: 1803 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1804 qed_bmap_release_id(p_hwfn, bmap, returned_id); 1805 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1806 1807 return rc; 1808 } 1809 1810 bool qed_rdma_allocated_qps(struct qed_hwfn *p_hwfn) 1811 { 1812 bool result; 1813 1814 /* if rdma wasn't activated yet, naturally there are no qps */ 1815 if (!p_hwfn->p_rdma_info->active) 1816 return false; 1817 1818 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1819 if (!p_hwfn->p_rdma_info->cid_map.bitmap) 1820 result = false; 1821 else 1822 result = !qed_bmap_is_empty(&p_hwfn->p_rdma_info->cid_map); 1823 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1824 return result; 1825 } 1826 1827 void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1828 { 1829 u32 val; 1830 1831 val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1; 1832 1833 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val); 1834 DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA), 1835 "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n", 1836 val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm); 1837 } 1838 1839 1840 void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1841 { 1842 p_hwfn->db_bar_no_edpm = true; 1843 1844 qed_rdma_dpm_conf(p_hwfn, p_ptt); 1845 } 1846 1847 static int qed_rdma_start(void *rdma_cxt, 1848 struct qed_rdma_start_in_params *params) 1849 { 1850 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1851 struct qed_ptt *p_ptt; 1852 int rc = -EBUSY; 1853 1854 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1855 "desired_cnq = %08x\n", params->desired_cnq); 1856 1857 p_ptt = qed_ptt_acquire(p_hwfn); 1858 if (!p_ptt) 1859 goto err; 1860 1861 rc = qed_rdma_alloc(p_hwfn); 1862 if (rc) 1863 goto err1; 1864 1865 rc = qed_rdma_setup(p_hwfn, p_ptt, params); 1866 if (rc) 1867 goto err2; 1868 1869 qed_ptt_release(p_hwfn, p_ptt); 1870 p_hwfn->p_rdma_info->active = 1; 1871 1872 return rc; 1873 1874 err2: 1875 qed_rdma_free(p_hwfn); 1876 err1: 1877 qed_ptt_release(p_hwfn, p_ptt); 1878 err: 1879 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc); 1880 return rc; 1881 } 1882 1883 static int qed_rdma_init(struct qed_dev *cdev, 1884 struct qed_rdma_start_in_params *params) 1885 { 1886 return qed_rdma_start(QED_AFFIN_HWFN(cdev), params); 1887 } 1888 1889 static void qed_rdma_remove_user(void *rdma_cxt, u16 dpi) 1890 { 1891 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1892 1893 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi); 1894 1895 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1896 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi); 1897 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1898 } 1899 1900 static int qed_roce_ll2_set_mac_filter(struct qed_dev *cdev, 1901 u8 *old_mac_address, 1902 u8 *new_mac_address) 1903 { 1904 int rc = 0; 1905 1906 if (old_mac_address) 1907 qed_llh_remove_mac_filter(cdev, 0, old_mac_address); 1908 if (new_mac_address) 1909 rc = qed_llh_add_mac_filter(cdev, 0, new_mac_address); 1910 1911 if (rc) 1912 DP_ERR(cdev, 1913 "qed roce ll2 mac filter set: failed to add MAC filter\n"); 1914 1915 return rc; 1916 } 1917 1918 static int qed_iwarp_set_engine_affin(struct qed_dev *cdev, bool b_reset) 1919 { 1920 enum qed_eng eng; 1921 u8 ppfid = 0; 1922 int rc; 1923 1924 /* Make sure iwarp cmt mode is enabled before setting affinity */ 1925 if (!cdev->iwarp_cmt) 1926 return -EINVAL; 1927 1928 if (b_reset) 1929 eng = QED_BOTH_ENG; 1930 else 1931 eng = cdev->l2_affin_hint ? QED_ENG1 : QED_ENG0; 1932 1933 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng); 1934 if (rc) { 1935 DP_NOTICE(cdev, 1936 "Failed to set the engine affinity of ppfid %d\n", 1937 ppfid); 1938 return rc; 1939 } 1940 1941 DP_VERBOSE(cdev, (QED_MSG_RDMA | QED_MSG_SP), 1942 "LLH: Set the engine affinity of non-RoCE packets as %d\n", 1943 eng); 1944 1945 return 0; 1946 } 1947 1948 static const struct qed_rdma_ops qed_rdma_ops_pass = { 1949 .common = &qed_common_ops_pass, 1950 .fill_dev_info = &qed_fill_rdma_dev_info, 1951 .rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx, 1952 .rdma_init = &qed_rdma_init, 1953 .rdma_add_user = &qed_rdma_add_user, 1954 .rdma_remove_user = &qed_rdma_remove_user, 1955 .rdma_stop = &qed_rdma_stop, 1956 .rdma_query_port = &qed_rdma_query_port, 1957 .rdma_query_device = &qed_rdma_query_device, 1958 .rdma_get_start_sb = &qed_rdma_get_sb_start, 1959 .rdma_get_rdma_int = &qed_rdma_get_int, 1960 .rdma_set_rdma_int = &qed_rdma_set_int, 1961 .rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix, 1962 .rdma_cnq_prod_update = &qed_rdma_cnq_prod_update, 1963 .rdma_alloc_pd = &qed_rdma_alloc_pd, 1964 .rdma_dealloc_pd = &qed_rdma_free_pd, 1965 .rdma_create_cq = &qed_rdma_create_cq, 1966 .rdma_destroy_cq = &qed_rdma_destroy_cq, 1967 .rdma_create_qp = &qed_rdma_create_qp, 1968 .rdma_modify_qp = &qed_rdma_modify_qp, 1969 .rdma_query_qp = &qed_rdma_query_qp, 1970 .rdma_destroy_qp = &qed_rdma_destroy_qp, 1971 .rdma_alloc_tid = &qed_rdma_alloc_tid, 1972 .rdma_free_tid = &qed_rdma_free_tid, 1973 .rdma_register_tid = &qed_rdma_register_tid, 1974 .rdma_deregister_tid = &qed_rdma_deregister_tid, 1975 .rdma_create_srq = &qed_rdma_create_srq, 1976 .rdma_modify_srq = &qed_rdma_modify_srq, 1977 .rdma_destroy_srq = &qed_rdma_destroy_srq, 1978 .ll2_acquire_connection = &qed_ll2_acquire_connection, 1979 .ll2_establish_connection = &qed_ll2_establish_connection, 1980 .ll2_terminate_connection = &qed_ll2_terminate_connection, 1981 .ll2_release_connection = &qed_ll2_release_connection, 1982 .ll2_post_rx_buffer = &qed_ll2_post_rx_buffer, 1983 .ll2_prepare_tx_packet = &qed_ll2_prepare_tx_packet, 1984 .ll2_set_fragment_of_tx_packet = &qed_ll2_set_fragment_of_tx_packet, 1985 .ll2_set_mac_filter = &qed_roce_ll2_set_mac_filter, 1986 .ll2_get_stats = &qed_ll2_get_stats, 1987 .iwarp_set_engine_affin = &qed_iwarp_set_engine_affin, 1988 .iwarp_connect = &qed_iwarp_connect, 1989 .iwarp_create_listen = &qed_iwarp_create_listen, 1990 .iwarp_destroy_listen = &qed_iwarp_destroy_listen, 1991 .iwarp_accept = &qed_iwarp_accept, 1992 .iwarp_reject = &qed_iwarp_reject, 1993 .iwarp_send_rtr = &qed_iwarp_send_rtr, 1994 }; 1995 1996 const struct qed_rdma_ops *qed_get_rdma_ops(void) 1997 { 1998 return &qed_rdma_ops_pass; 1999 } 2000 EXPORT_SYMBOL(qed_get_rdma_ops); 2001