1 /* QLogic qed NIC Driver
2  * Copyright (c) 2015-2017  QLogic Corporation
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and /or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #include <linux/types.h>
33 #include <asm/byteorder.h>
34 #include <linux/bitops.h>
35 #include <linux/delay.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/errno.h>
38 #include <linux/io.h>
39 #include <linux/kernel.h>
40 #include <linux/list.h>
41 #include <linux/module.h>
42 #include <linux/mutex.h>
43 #include <linux/pci.h>
44 #include <linux/slab.h>
45 #include <linux/spinlock.h>
46 #include <linux/string.h>
47 #include "qed.h"
48 #include "qed_cxt.h"
49 #include "qed_hsi.h"
50 #include "qed_hw.h"
51 #include "qed_init_ops.h"
52 #include "qed_int.h"
53 #include "qed_ll2.h"
54 #include "qed_mcp.h"
55 #include "qed_reg_addr.h"
56 #include <linux/qed/qed_rdma_if.h>
57 #include "qed_rdma.h"
58 #include "qed_roce.h"
59 #include "qed_sp.h"
60 
61 
62 int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn,
63 			struct qed_bmap *bmap, u32 max_count, char *name)
64 {
65 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count);
66 
67 	bmap->max_count = max_count;
68 
69 	bmap->bitmap = kcalloc(BITS_TO_LONGS(max_count), sizeof(long),
70 			       GFP_KERNEL);
71 	if (!bmap->bitmap)
72 		return -ENOMEM;
73 
74 	snprintf(bmap->name, QED_RDMA_MAX_BMAP_NAME, "%s", name);
75 
76 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n");
77 	return 0;
78 }
79 
80 int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn,
81 			   struct qed_bmap *bmap, u32 *id_num)
82 {
83 	*id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count);
84 	if (*id_num >= bmap->max_count)
85 		return -EINVAL;
86 
87 	__set_bit(*id_num, bmap->bitmap);
88 
89 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: allocated id %d\n",
90 		   bmap->name, *id_num);
91 
92 	return 0;
93 }
94 
95 void qed_bmap_set_id(struct qed_hwfn *p_hwfn,
96 		     struct qed_bmap *bmap, u32 id_num)
97 {
98 	if (id_num >= bmap->max_count)
99 		return;
100 
101 	__set_bit(id_num, bmap->bitmap);
102 }
103 
104 void qed_bmap_release_id(struct qed_hwfn *p_hwfn,
105 			 struct qed_bmap *bmap, u32 id_num)
106 {
107 	bool b_acquired;
108 
109 	if (id_num >= bmap->max_count)
110 		return;
111 
112 	b_acquired = test_and_clear_bit(id_num, bmap->bitmap);
113 	if (!b_acquired) {
114 		DP_NOTICE(p_hwfn, "%s bitmap: id %d already released\n",
115 			  bmap->name, id_num);
116 		return;
117 	}
118 
119 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: released id %d\n",
120 		   bmap->name, id_num);
121 }
122 
123 int qed_bmap_test_id(struct qed_hwfn *p_hwfn,
124 		     struct qed_bmap *bmap, u32 id_num)
125 {
126 	if (id_num >= bmap->max_count)
127 		return -1;
128 
129 	return test_bit(id_num, bmap->bitmap);
130 }
131 
132 static bool qed_bmap_is_empty(struct qed_bmap *bmap)
133 {
134 	return bmap->max_count == find_first_bit(bmap->bitmap, bmap->max_count);
135 }
136 
137 u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id)
138 {
139 	/* First sb id for RoCE is after all the l2 sb */
140 	return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id;
141 }
142 
143 static int qed_rdma_alloc(struct qed_hwfn *p_hwfn,
144 			  struct qed_ptt *p_ptt,
145 			  struct qed_rdma_start_in_params *params)
146 {
147 	struct qed_rdma_info *p_rdma_info;
148 	u32 num_cons, num_tasks;
149 	int rc = -ENOMEM;
150 
151 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n");
152 
153 	/* Allocate a struct with current pf rdma info */
154 	p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL);
155 	if (!p_rdma_info)
156 		return rc;
157 
158 	p_hwfn->p_rdma_info = p_rdma_info;
159 	p_rdma_info->proto = PROTOCOLID_ROCE;
160 
161 	num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto,
162 					       NULL);
163 
164 	if (QED_IS_IWARP_PERSONALITY(p_hwfn))
165 		p_rdma_info->num_qps = num_cons;
166 	else
167 		p_rdma_info->num_qps = num_cons / 2; /* 2 cids per qp */
168 
169 	num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE);
170 
171 	/* Each MR uses a single task */
172 	p_rdma_info->num_mrs = num_tasks;
173 
174 	/* Queue zone lines are shared between RoCE and L2 in such a way that
175 	 * they can be used by each without obstructing the other.
176 	 */
177 	p_rdma_info->queue_zone_base = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
178 	p_rdma_info->max_queue_zones = (u16)RESC_NUM(p_hwfn, QED_L2_QUEUE);
179 
180 	/* Allocate a struct with device params and fill it */
181 	p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL);
182 	if (!p_rdma_info->dev)
183 		goto free_rdma_info;
184 
185 	/* Allocate a struct with port params and fill it */
186 	p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL);
187 	if (!p_rdma_info->port)
188 		goto free_rdma_dev;
189 
190 	/* Allocate bit map for pd's */
191 	rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS,
192 				 "PD");
193 	if (rc) {
194 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
195 			   "Failed to allocate pd_map, rc = %d\n",
196 			   rc);
197 		goto free_rdma_port;
198 	}
199 
200 	/* Allocate DPI bitmap */
201 	rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map,
202 				 p_hwfn->dpi_count, "DPI");
203 	if (rc) {
204 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
205 			   "Failed to allocate DPI bitmap, rc = %d\n", rc);
206 		goto free_pd_map;
207 	}
208 
209 	/* Allocate bitmap for cq's. The maximum number of CQs is bounded to
210 	 * twice the number of QPs.
211 	 */
212 	rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map,
213 				 p_rdma_info->num_qps * 2, "CQ");
214 	if (rc) {
215 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
216 			   "Failed to allocate cq bitmap, rc = %d\n", rc);
217 		goto free_dpi_map;
218 	}
219 
220 	/* Allocate bitmap for toggle bit for cq icids
221 	 * We toggle the bit every time we create or resize cq for a given icid.
222 	 * The maximum number of CQs is bounded to  twice the number of QPs.
223 	 */
224 	rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits,
225 				 p_rdma_info->num_qps * 2, "Toggle");
226 	if (rc) {
227 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
228 			   "Failed to allocate toogle bits, rc = %d\n", rc);
229 		goto free_cq_map;
230 	}
231 
232 	/* Allocate bitmap for itids */
233 	rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map,
234 				 p_rdma_info->num_mrs, "MR");
235 	if (rc) {
236 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
237 			   "Failed to allocate itids bitmaps, rc = %d\n", rc);
238 		goto free_toggle_map;
239 	}
240 
241 	/* Allocate bitmap for cids used for qps. */
242 	rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons,
243 				 "CID");
244 	if (rc) {
245 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
246 			   "Failed to allocate cid bitmap, rc = %d\n", rc);
247 		goto free_tid_map;
248 	}
249 
250 	/* Allocate bitmap for cids used for responders/requesters. */
251 	rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->real_cid_map, num_cons,
252 				 "REAL_CID");
253 	if (rc) {
254 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
255 			   "Failed to allocate real cid bitmap, rc = %d\n", rc);
256 		goto free_cid_map;
257 	}
258 
259 	if (QED_IS_IWARP_PERSONALITY(p_hwfn))
260 		rc = qed_iwarp_alloc(p_hwfn);
261 
262 	if (rc)
263 		goto free_cid_map;
264 
265 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n");
266 	return 0;
267 
268 free_cid_map:
269 	kfree(p_rdma_info->cid_map.bitmap);
270 free_tid_map:
271 	kfree(p_rdma_info->tid_map.bitmap);
272 free_toggle_map:
273 	kfree(p_rdma_info->toggle_bits.bitmap);
274 free_cq_map:
275 	kfree(p_rdma_info->cq_map.bitmap);
276 free_dpi_map:
277 	kfree(p_rdma_info->dpi_map.bitmap);
278 free_pd_map:
279 	kfree(p_rdma_info->pd_map.bitmap);
280 free_rdma_port:
281 	kfree(p_rdma_info->port);
282 free_rdma_dev:
283 	kfree(p_rdma_info->dev);
284 free_rdma_info:
285 	kfree(p_rdma_info);
286 
287 	return rc;
288 }
289 
290 void qed_rdma_bmap_free(struct qed_hwfn *p_hwfn,
291 			struct qed_bmap *bmap, bool check)
292 {
293 	int weight = bitmap_weight(bmap->bitmap, bmap->max_count);
294 	int last_line = bmap->max_count / (64 * 8);
295 	int last_item = last_line * 8 +
296 	    DIV_ROUND_UP(bmap->max_count % (64 * 8), 64);
297 	u64 *pmap = (u64 *)bmap->bitmap;
298 	int line, item, offset;
299 	u8 str_last_line[200] = { 0 };
300 
301 	if (!weight || !check)
302 		goto end;
303 
304 	DP_NOTICE(p_hwfn,
305 		  "%s bitmap not free - size=%d, weight=%d, 512 bits per line\n",
306 		  bmap->name, bmap->max_count, weight);
307 
308 	/* print aligned non-zero lines, if any */
309 	for (item = 0, line = 0; line < last_line; line++, item += 8)
310 		if (bitmap_weight((unsigned long *)&pmap[item], 64 * 8))
311 			DP_NOTICE(p_hwfn,
312 				  "line 0x%04x: 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx\n",
313 				  line,
314 				  pmap[item],
315 				  pmap[item + 1],
316 				  pmap[item + 2],
317 				  pmap[item + 3],
318 				  pmap[item + 4],
319 				  pmap[item + 5],
320 				  pmap[item + 6], pmap[item + 7]);
321 
322 	/* print last unaligned non-zero line, if any */
323 	if ((bmap->max_count % (64 * 8)) &&
324 	    (bitmap_weight((unsigned long *)&pmap[item],
325 			   bmap->max_count - item * 64))) {
326 		offset = sprintf(str_last_line, "line 0x%04x: ", line);
327 		for (; item < last_item; item++)
328 			offset += sprintf(str_last_line + offset,
329 					  "0x%016llx ", pmap[item]);
330 		DP_NOTICE(p_hwfn, "%s\n", str_last_line);
331 	}
332 
333 end:
334 	kfree(bmap->bitmap);
335 	bmap->bitmap = NULL;
336 }
337 
338 static void qed_rdma_resc_free(struct qed_hwfn *p_hwfn)
339 {
340 	struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
341 
342 	if (QED_IS_IWARP_PERSONALITY(p_hwfn))
343 		qed_iwarp_resc_free(p_hwfn);
344 
345 	qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cid_map, 1);
346 	qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->pd_map, 1);
347 	qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 1);
348 	qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cq_map, 1);
349 	qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->toggle_bits, 0);
350 	qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->tid_map, 1);
351 
352 	kfree(p_rdma_info->port);
353 	kfree(p_rdma_info->dev);
354 
355 	kfree(p_rdma_info);
356 }
357 
358 static void qed_rdma_free(struct qed_hwfn *p_hwfn)
359 {
360 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n");
361 
362 	qed_rdma_resc_free(p_hwfn);
363 }
364 
365 static void qed_rdma_get_guid(struct qed_hwfn *p_hwfn, u8 *guid)
366 {
367 	guid[0] = p_hwfn->hw_info.hw_mac_addr[0] ^ 2;
368 	guid[1] = p_hwfn->hw_info.hw_mac_addr[1];
369 	guid[2] = p_hwfn->hw_info.hw_mac_addr[2];
370 	guid[3] = 0xff;
371 	guid[4] = 0xfe;
372 	guid[5] = p_hwfn->hw_info.hw_mac_addr[3];
373 	guid[6] = p_hwfn->hw_info.hw_mac_addr[4];
374 	guid[7] = p_hwfn->hw_info.hw_mac_addr[5];
375 }
376 
377 static void qed_rdma_init_events(struct qed_hwfn *p_hwfn,
378 				 struct qed_rdma_start_in_params *params)
379 {
380 	struct qed_rdma_events *events;
381 
382 	events = &p_hwfn->p_rdma_info->events;
383 
384 	events->unaffiliated_event = params->events->unaffiliated_event;
385 	events->affiliated_event = params->events->affiliated_event;
386 	events->context = params->events->context;
387 }
388 
389 static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn,
390 				  struct qed_rdma_start_in_params *params)
391 {
392 	struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
393 	struct qed_dev *cdev = p_hwfn->cdev;
394 	u32 pci_status_control;
395 	u32 num_qps;
396 
397 	/* Vendor specific information */
398 	dev->vendor_id = cdev->vendor_id;
399 	dev->vendor_part_id = cdev->device_id;
400 	dev->hw_ver = 0;
401 	dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |
402 		      (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION);
403 
404 	qed_rdma_get_guid(p_hwfn, (u8 *)&dev->sys_image_guid);
405 	dev->node_guid = dev->sys_image_guid;
406 
407 	dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE,
408 			     RDMA_MAX_SGE_PER_RQ_WQE);
409 
410 	if (cdev->rdma_max_sge)
411 		dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge);
412 
413 	dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE;
414 
415 	dev->max_inline = (cdev->rdma_max_inline) ?
416 			  min_t(u32, cdev->rdma_max_inline, dev->max_inline) :
417 			  dev->max_inline;
418 
419 	dev->max_wqe = QED_RDMA_MAX_WQE;
420 	dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ);
421 
422 	/* The number of QPs may be higher than QED_ROCE_MAX_QPS, because
423 	 * it is up-aligned to 16 and then to ILT page size within qed cxt.
424 	 * This is OK in terms of ILT but we don't want to configure the FW
425 	 * above its abilities
426 	 */
427 	num_qps = ROCE_MAX_QPS;
428 	num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps);
429 	dev->max_qp = num_qps;
430 
431 	/* CQs uses the same icids that QPs use hence they are limited by the
432 	 * number of icids. There are two icids per QP.
433 	 */
434 	dev->max_cq = num_qps * 2;
435 
436 	/* The number of mrs is smaller by 1 since the first is reserved */
437 	dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1;
438 	dev->max_mr_size = QED_RDMA_MAX_MR_SIZE;
439 
440 	/* The maximum CQE capacity per CQ supported.
441 	 * max number of cqes will be in two layer pbl,
442 	 * 8 is the pointer size in bytes
443 	 * 32 is the size of cq element in bytes
444 	 */
445 	if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS)
446 		dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT;
447 	else
448 		dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT;
449 
450 	dev->max_mw = 0;
451 	dev->max_fmr = QED_RDMA_MAX_FMR;
452 	dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8);
453 	dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE;
454 	dev->max_pkey = QED_RDMA_MAX_P_KEY;
455 
456 	dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
457 					  (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2);
458 	dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
459 					 RDMA_REQ_RD_ATOMIC_ELM_SIZE;
460 	dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc *
461 					   p_hwfn->p_rdma_info->num_qps;
462 	dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS;
463 	dev->dev_ack_delay = QED_RDMA_ACK_DELAY;
464 	dev->max_pd = RDMA_MAX_PDS;
465 	dev->max_ah = p_hwfn->p_rdma_info->num_qps;
466 	dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE);
467 
468 	/* Set capablities */
469 	dev->dev_caps = 0;
470 	SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1);
471 	SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1);
472 	SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1);
473 	SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1);
474 	SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1);
475 	SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1);
476 	SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1);
477 	SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1);
478 
479 	/* Check atomic operations support in PCI configuration space. */
480 	pci_read_config_dword(cdev->pdev,
481 			      cdev->pdev->pcie_cap + PCI_EXP_DEVCTL2,
482 			      &pci_status_control);
483 
484 	if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN)
485 		SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1);
486 
487 	if (QED_IS_IWARP_PERSONALITY(p_hwfn))
488 		qed_iwarp_init_devinfo(p_hwfn);
489 }
490 
491 static void qed_rdma_init_port(struct qed_hwfn *p_hwfn)
492 {
493 	struct qed_rdma_port *port = p_hwfn->p_rdma_info->port;
494 	struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
495 
496 	port->port_state = p_hwfn->mcp_info->link_output.link_up ?
497 			   QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN;
498 
499 	port->max_msg_size = min_t(u64,
500 				   (dev->max_mr_mw_fmr_size *
501 				    p_hwfn->cdev->rdma_max_sge),
502 				   BIT(31));
503 
504 	port->pkey_bad_counter = 0;
505 }
506 
507 static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
508 {
509 	int rc = 0;
510 
511 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n");
512 	p_hwfn->b_rdma_enabled_in_prs = false;
513 
514 	if (QED_IS_IWARP_PERSONALITY(p_hwfn))
515 		qed_iwarp_init_hw(p_hwfn, p_ptt);
516 	else
517 		rc = qed_roce_init_hw(p_hwfn, p_ptt);
518 
519 	return rc;
520 }
521 
522 static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn,
523 			     struct qed_rdma_start_in_params *params,
524 			     struct qed_ptt *p_ptt)
525 {
526 	struct rdma_init_func_ramrod_data *p_ramrod;
527 	struct qed_rdma_cnq_params *p_cnq_pbl_list;
528 	struct rdma_init_func_hdr *p_params_header;
529 	struct rdma_cnq_params *p_cnq_params;
530 	struct qed_sp_init_data init_data;
531 	struct qed_spq_entry *p_ent;
532 	u32 cnq_id, sb_id;
533 	u16 igu_sb_id;
534 	int rc;
535 
536 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n");
537 
538 	/* Save the number of cnqs for the function close ramrod */
539 	p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq;
540 
541 	/* Get SPQ entry */
542 	memset(&init_data, 0, sizeof(init_data));
543 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
544 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
545 
546 	rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT,
547 				 p_hwfn->p_rdma_info->proto, &init_data);
548 	if (rc)
549 		return rc;
550 
551 	if (QED_IS_IWARP_PERSONALITY(p_hwfn))
552 		p_ramrod = &p_ent->ramrod.iwarp_init_func.rdma;
553 	else
554 		p_ramrod = &p_ent->ramrod.roce_init_func.rdma;
555 
556 	p_params_header = &p_ramrod->params_header;
557 	p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn,
558 							   QED_RDMA_CNQ_RAM);
559 	p_params_header->num_cnqs = params->desired_cnq;
560 
561 	if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS)
562 		p_params_header->cq_ring_mode = 1;
563 	else
564 		p_params_header->cq_ring_mode = 0;
565 
566 	for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) {
567 		sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id);
568 		igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
569 		p_ramrod->cnq_params[cnq_id].sb_num = cpu_to_le16(igu_sb_id);
570 		p_cnq_params = &p_ramrod->cnq_params[cnq_id];
571 		p_cnq_pbl_list = &params->cnq_pbl_list[cnq_id];
572 
573 		p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi;
574 		p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages;
575 
576 		DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr,
577 			       p_cnq_pbl_list->pbl_ptr);
578 
579 		/* we assume here that cnq_id and qz_offset are the same */
580 		p_cnq_params->queue_zone_num =
581 			cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base +
582 				    cnq_id);
583 	}
584 
585 	return qed_spq_post(p_hwfn, p_ent, NULL);
586 }
587 
588 static int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid)
589 {
590 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
591 	int rc;
592 
593 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n");
594 
595 	spin_lock_bh(&p_hwfn->p_rdma_info->lock);
596 	rc = qed_rdma_bmap_alloc_id(p_hwfn,
597 				    &p_hwfn->p_rdma_info->tid_map, itid);
598 	spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
599 	if (rc)
600 		goto out;
601 
602 	rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid);
603 out:
604 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc);
605 	return rc;
606 }
607 
608 static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn)
609 {
610 	struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
611 
612 	/* The first DPI is reserved for the Kernel */
613 	__set_bit(0, p_hwfn->p_rdma_info->dpi_map.bitmap);
614 
615 	/* Tid 0 will be used as the key for "reserved MR".
616 	 * The driver should allocate memory for it so it can be loaded but no
617 	 * ramrod should be passed on it.
618 	 */
619 	qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey);
620 	if (dev->reserved_lkey != RDMA_RESERVED_LKEY) {
621 		DP_NOTICE(p_hwfn,
622 			  "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n");
623 		return -EINVAL;
624 	}
625 
626 	return 0;
627 }
628 
629 static int qed_rdma_setup(struct qed_hwfn *p_hwfn,
630 			  struct qed_ptt *p_ptt,
631 			  struct qed_rdma_start_in_params *params)
632 {
633 	int rc;
634 
635 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n");
636 
637 	spin_lock_init(&p_hwfn->p_rdma_info->lock);
638 
639 	qed_rdma_init_devinfo(p_hwfn, params);
640 	qed_rdma_init_port(p_hwfn);
641 	qed_rdma_init_events(p_hwfn, params);
642 
643 	rc = qed_rdma_reserve_lkey(p_hwfn);
644 	if (rc)
645 		return rc;
646 
647 	rc = qed_rdma_init_hw(p_hwfn, p_ptt);
648 	if (rc)
649 		return rc;
650 
651 	if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
652 		rc = qed_iwarp_setup(p_hwfn, p_ptt, params);
653 		if (rc)
654 			return rc;
655 	} else {
656 		rc = qed_roce_setup(p_hwfn);
657 		if (rc)
658 			return rc;
659 	}
660 
661 	return qed_rdma_start_fw(p_hwfn, params, p_ptt);
662 }
663 
664 int qed_rdma_stop(void *rdma_cxt)
665 {
666 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
667 	struct rdma_close_func_ramrod_data *p_ramrod;
668 	struct qed_sp_init_data init_data;
669 	struct qed_spq_entry *p_ent;
670 	struct qed_ptt *p_ptt;
671 	u32 ll2_ethertype_en;
672 	int rc = -EBUSY;
673 
674 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n");
675 
676 	p_ptt = qed_ptt_acquire(p_hwfn);
677 	if (!p_ptt) {
678 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n");
679 		return rc;
680 	}
681 
682 	/* Disable RoCE search */
683 	qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0);
684 	p_hwfn->b_rdma_enabled_in_prs = false;
685 
686 	qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0);
687 
688 	ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
689 
690 	qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN,
691 	       (ll2_ethertype_en & 0xFFFE));
692 
693 	if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
694 		rc = qed_iwarp_stop(p_hwfn, p_ptt);
695 		if (rc) {
696 			qed_ptt_release(p_hwfn, p_ptt);
697 			return rc;
698 		}
699 	} else {
700 		qed_roce_stop(p_hwfn);
701 	}
702 
703 	qed_ptt_release(p_hwfn, p_ptt);
704 
705 	/* Get SPQ entry */
706 	memset(&init_data, 0, sizeof(init_data));
707 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
708 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
709 
710 	/* Stop RoCE */
711 	rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE,
712 				 p_hwfn->p_rdma_info->proto, &init_data);
713 	if (rc)
714 		goto out;
715 
716 	p_ramrod = &p_ent->ramrod.rdma_close_func;
717 
718 	p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs;
719 	p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM);
720 
721 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
722 
723 out:
724 	qed_rdma_free(p_hwfn);
725 
726 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc);
727 	return rc;
728 }
729 
730 static int qed_rdma_add_user(void *rdma_cxt,
731 			     struct qed_rdma_add_user_out_params *out_params)
732 {
733 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
734 	u32 dpi_start_offset;
735 	u32 returned_id = 0;
736 	int rc;
737 
738 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n");
739 
740 	/* Allocate DPI */
741 	spin_lock_bh(&p_hwfn->p_rdma_info->lock);
742 	rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map,
743 				    &returned_id);
744 	spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
745 
746 	out_params->dpi = (u16)returned_id;
747 
748 	/* Calculate the corresponding DPI address */
749 	dpi_start_offset = p_hwfn->dpi_start_offset;
750 
751 	out_params->dpi_addr = (u64)((u8 __iomem *)p_hwfn->doorbells +
752 				     dpi_start_offset +
753 				     ((out_params->dpi) * p_hwfn->dpi_size));
754 
755 	out_params->dpi_phys_addr = p_hwfn->cdev->db_phys_addr +
756 				    dpi_start_offset +
757 				    ((out_params->dpi) * p_hwfn->dpi_size);
758 
759 	out_params->dpi_size = p_hwfn->dpi_size;
760 	out_params->wid_count = p_hwfn->wid_count;
761 
762 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc);
763 	return rc;
764 }
765 
766 static struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt)
767 {
768 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
769 	struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port;
770 
771 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n");
772 
773 	/* Link may have changed */
774 	p_port->port_state = p_hwfn->mcp_info->link_output.link_up ?
775 			     QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN;
776 
777 	p_port->link_speed = p_hwfn->mcp_info->link_output.speed;
778 
779 	p_port->max_msg_size = RDMA_MAX_DATA_SIZE_IN_WQE;
780 
781 	return p_port;
782 }
783 
784 static struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt)
785 {
786 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
787 
788 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n");
789 
790 	/* Return struct with device parameters */
791 	return p_hwfn->p_rdma_info->dev;
792 }
793 
794 static void qed_rdma_free_tid(void *rdma_cxt, u32 itid)
795 {
796 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
797 
798 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid);
799 
800 	spin_lock_bh(&p_hwfn->p_rdma_info->lock);
801 	qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->tid_map, itid);
802 	spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
803 }
804 
805 static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod)
806 {
807 	struct qed_hwfn *p_hwfn;
808 	u16 qz_num;
809 	u32 addr;
810 
811 	p_hwfn = (struct qed_hwfn *)rdma_cxt;
812 
813 	if (qz_offset > p_hwfn->p_rdma_info->max_queue_zones) {
814 		DP_NOTICE(p_hwfn,
815 			  "queue zone offset %d is too large (max is %d)\n",
816 			  qz_offset, p_hwfn->p_rdma_info->max_queue_zones);
817 		return;
818 	}
819 
820 	qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset;
821 	addr = GTT_BAR0_MAP_REG_USDM_RAM +
822 	       USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num);
823 
824 	REG_WR16(p_hwfn, addr, prod);
825 
826 	/* keep prod updates ordered */
827 	wmb();
828 }
829 
830 static int qed_fill_rdma_dev_info(struct qed_dev *cdev,
831 				  struct qed_dev_rdma_info *info)
832 {
833 	struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
834 
835 	memset(info, 0, sizeof(*info));
836 
837 	info->rdma_type = QED_IS_ROCE_PERSONALITY(p_hwfn) ?
838 	    QED_RDMA_TYPE_ROCE : QED_RDMA_TYPE_IWARP;
839 
840 	info->user_dpm_enabled = (p_hwfn->db_bar_no_edpm == 0);
841 
842 	qed_fill_dev_info(cdev, &info->common);
843 
844 	return 0;
845 }
846 
847 static int qed_rdma_get_sb_start(struct qed_dev *cdev)
848 {
849 	int feat_num;
850 
851 	if (cdev->num_hwfns > 1)
852 		feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE);
853 	else
854 		feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE) *
855 			   cdev->num_hwfns;
856 
857 	return feat_num;
858 }
859 
860 static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev)
861 {
862 	int n_cnq = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_RDMA_CNQ);
863 	int n_msix = cdev->int_params.rdma_msix_cnt;
864 
865 	return min_t(int, n_cnq, n_msix);
866 }
867 
868 static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt)
869 {
870 	int limit = 0;
871 
872 	/* Mark the fastpath as free/used */
873 	cdev->int_params.fp_initialized = cnt ? true : false;
874 
875 	if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) {
876 		DP_ERR(cdev,
877 		       "qed roce supports only MSI-X interrupts (detected %d).\n",
878 		       cdev->int_params.out.int_mode);
879 		return -EINVAL;
880 	} else if (cdev->int_params.fp_msix_cnt) {
881 		limit = cdev->int_params.rdma_msix_cnt;
882 	}
883 
884 	if (!limit)
885 		return -ENOMEM;
886 
887 	return min_t(int, cnt, limit);
888 }
889 
890 static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info)
891 {
892 	memset(info, 0, sizeof(*info));
893 
894 	if (!cdev->int_params.fp_initialized) {
895 		DP_INFO(cdev,
896 			"Protocol driver requested interrupt information, but its support is not yet configured\n");
897 		return -EINVAL;
898 	}
899 
900 	if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
901 		int msix_base = cdev->int_params.rdma_msix_base;
902 
903 		info->msix_cnt = cdev->int_params.rdma_msix_cnt;
904 		info->msix = &cdev->int_params.msix_table[msix_base];
905 
906 		DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n",
907 			   info->msix_cnt, msix_base);
908 	}
909 
910 	return 0;
911 }
912 
913 static int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd)
914 {
915 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
916 	u32 returned_id;
917 	int rc;
918 
919 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n");
920 
921 	/* Allocates an unused protection domain */
922 	spin_lock_bh(&p_hwfn->p_rdma_info->lock);
923 	rc = qed_rdma_bmap_alloc_id(p_hwfn,
924 				    &p_hwfn->p_rdma_info->pd_map, &returned_id);
925 	spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
926 
927 	*pd = (u16)returned_id;
928 
929 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc);
930 	return rc;
931 }
932 
933 static void qed_rdma_free_pd(void *rdma_cxt, u16 pd)
934 {
935 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
936 
937 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd);
938 
939 	/* Returns a previously allocated protection domain for reuse */
940 	spin_lock_bh(&p_hwfn->p_rdma_info->lock);
941 	qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd);
942 	spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
943 }
944 
945 static enum qed_rdma_toggle_bit
946 qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid)
947 {
948 	struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
949 	enum qed_rdma_toggle_bit toggle_bit;
950 	u32 bmap_id;
951 
952 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid);
953 
954 	/* the function toggle the bit that is related to a given icid
955 	 * and returns the new toggle bit's value
956 	 */
957 	bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto);
958 
959 	spin_lock_bh(&p_info->lock);
960 	toggle_bit = !test_and_change_bit(bmap_id,
961 					  p_info->toggle_bits.bitmap);
962 	spin_unlock_bh(&p_info->lock);
963 
964 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n",
965 		   toggle_bit);
966 
967 	return toggle_bit;
968 }
969 
970 static int qed_rdma_create_cq(void *rdma_cxt,
971 			      struct qed_rdma_create_cq_in_params *params,
972 			      u16 *icid)
973 {
974 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
975 	struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
976 	struct rdma_create_cq_ramrod_data *p_ramrod;
977 	enum qed_rdma_toggle_bit toggle_bit;
978 	struct qed_sp_init_data init_data;
979 	struct qed_spq_entry *p_ent;
980 	u32 returned_id, start_cid;
981 	int rc;
982 
983 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n",
984 		   params->cq_handle_hi, params->cq_handle_lo);
985 
986 	/* Allocate icid */
987 	spin_lock_bh(&p_info->lock);
988 	rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_info->cq_map, &returned_id);
989 	spin_unlock_bh(&p_info->lock);
990 
991 	if (rc) {
992 		DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc);
993 		return rc;
994 	}
995 
996 	start_cid = qed_cxt_get_proto_cid_start(p_hwfn,
997 						p_info->proto);
998 	*icid = returned_id + start_cid;
999 
1000 	/* Check if icid requires a page allocation */
1001 	rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid);
1002 	if (rc)
1003 		goto err;
1004 
1005 	/* Get SPQ entry */
1006 	memset(&init_data, 0, sizeof(init_data));
1007 	init_data.cid = *icid;
1008 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1009 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1010 
1011 	/* Send create CQ ramrod */
1012 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1013 				 RDMA_RAMROD_CREATE_CQ,
1014 				 p_info->proto, &init_data);
1015 	if (rc)
1016 		goto err;
1017 
1018 	p_ramrod = &p_ent->ramrod.rdma_create_cq;
1019 
1020 	p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi);
1021 	p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo);
1022 	p_ramrod->dpi = cpu_to_le16(params->dpi);
1023 	p_ramrod->is_two_level_pbl = params->pbl_two_level;
1024 	p_ramrod->max_cqes = cpu_to_le32(params->cq_size);
1025 	DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr);
1026 	p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages);
1027 	p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) +
1028 			   params->cnq_id;
1029 	p_ramrod->int_timeout = params->int_timeout;
1030 
1031 	/* toggle the bit for every resize or create cq for a given icid */
1032 	toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
1033 
1034 	p_ramrod->toggle_bit = toggle_bit;
1035 
1036 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
1037 	if (rc) {
1038 		/* restore toggle bit */
1039 		qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
1040 		goto err;
1041 	}
1042 
1043 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc);
1044 	return rc;
1045 
1046 err:
1047 	/* release allocated icid */
1048 	spin_lock_bh(&p_info->lock);
1049 	qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id);
1050 	spin_unlock_bh(&p_info->lock);
1051 	DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc);
1052 
1053 	return rc;
1054 }
1055 
1056 static int
1057 qed_rdma_destroy_cq(void *rdma_cxt,
1058 		    struct qed_rdma_destroy_cq_in_params *in_params,
1059 		    struct qed_rdma_destroy_cq_out_params *out_params)
1060 {
1061 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1062 	struct rdma_destroy_cq_output_params *p_ramrod_res;
1063 	struct rdma_destroy_cq_ramrod_data *p_ramrod;
1064 	struct qed_sp_init_data init_data;
1065 	struct qed_spq_entry *p_ent;
1066 	dma_addr_t ramrod_res_phys;
1067 	enum protocol_type proto;
1068 	int rc = -ENOMEM;
1069 
1070 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid);
1071 
1072 	p_ramrod_res =
1073 	    (struct rdma_destroy_cq_output_params *)
1074 	    dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1075 			       sizeof(struct rdma_destroy_cq_output_params),
1076 			       &ramrod_res_phys, GFP_KERNEL);
1077 	if (!p_ramrod_res) {
1078 		DP_NOTICE(p_hwfn,
1079 			  "qed destroy cq failed: cannot allocate memory (ramrod)\n");
1080 		return rc;
1081 	}
1082 
1083 	/* Get SPQ entry */
1084 	memset(&init_data, 0, sizeof(init_data));
1085 	init_data.cid = in_params->icid;
1086 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1087 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1088 	proto = p_hwfn->p_rdma_info->proto;
1089 	/* Send destroy CQ ramrod */
1090 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1091 				 RDMA_RAMROD_DESTROY_CQ,
1092 				 proto, &init_data);
1093 	if (rc)
1094 		goto err;
1095 
1096 	p_ramrod = &p_ent->ramrod.rdma_destroy_cq;
1097 	DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1098 
1099 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
1100 	if (rc)
1101 		goto err;
1102 
1103 	out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num);
1104 
1105 	dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1106 			  sizeof(struct rdma_destroy_cq_output_params),
1107 			  p_ramrod_res, ramrod_res_phys);
1108 
1109 	/* Free icid */
1110 	spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1111 
1112 	qed_bmap_release_id(p_hwfn,
1113 			    &p_hwfn->p_rdma_info->cq_map,
1114 			    (in_params->icid -
1115 			     qed_cxt_get_proto_cid_start(p_hwfn, proto)));
1116 
1117 	spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1118 
1119 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc);
1120 	return rc;
1121 
1122 err:	dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1123 			  sizeof(struct rdma_destroy_cq_output_params),
1124 			  p_ramrod_res, ramrod_res_phys);
1125 
1126 	return rc;
1127 }
1128 
1129 void qed_rdma_set_fw_mac(u16 *p_fw_mac, u8 *p_qed_mac)
1130 {
1131 	p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]);
1132 	p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]);
1133 	p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]);
1134 }
1135 
1136 static int qed_rdma_query_qp(void *rdma_cxt,
1137 			     struct qed_rdma_qp *qp,
1138 			     struct qed_rdma_query_qp_out_params *out_params)
1139 {
1140 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1141 	int rc = 0;
1142 
1143 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1144 
1145 	/* The following fields are filled in from qp and not FW as they can't
1146 	 * be modified by FW
1147 	 */
1148 	out_params->mtu = qp->mtu;
1149 	out_params->dest_qp = qp->dest_qp;
1150 	out_params->incoming_atomic_en = qp->incoming_atomic_en;
1151 	out_params->e2e_flow_control_en = qp->e2e_flow_control_en;
1152 	out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en;
1153 	out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en;
1154 	out_params->dgid = qp->dgid;
1155 	out_params->flow_label = qp->flow_label;
1156 	out_params->hop_limit_ttl = qp->hop_limit_ttl;
1157 	out_params->traffic_class_tos = qp->traffic_class_tos;
1158 	out_params->timeout = qp->ack_timeout;
1159 	out_params->rnr_retry = qp->rnr_retry_cnt;
1160 	out_params->retry_cnt = qp->retry_cnt;
1161 	out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer;
1162 	out_params->pkey_index = 0;
1163 	out_params->max_rd_atomic = qp->max_rd_atomic_req;
1164 	out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp;
1165 	out_params->sqd_async = qp->sqd_async;
1166 
1167 	if (QED_IS_IWARP_PERSONALITY(p_hwfn))
1168 		qed_iwarp_query_qp(qp, out_params);
1169 	else
1170 		rc = qed_roce_query_qp(p_hwfn, qp, out_params);
1171 
1172 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc);
1173 	return rc;
1174 }
1175 
1176 static int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp)
1177 {
1178 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1179 	int rc = 0;
1180 
1181 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1182 
1183 	if (QED_IS_IWARP_PERSONALITY(p_hwfn))
1184 		rc = qed_iwarp_destroy_qp(p_hwfn, qp);
1185 	else
1186 		rc = qed_roce_destroy_qp(p_hwfn, qp);
1187 
1188 	/* free qp params struct */
1189 	kfree(qp);
1190 
1191 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n");
1192 	return rc;
1193 }
1194 
1195 static struct qed_rdma_qp *
1196 qed_rdma_create_qp(void *rdma_cxt,
1197 		   struct qed_rdma_create_qp_in_params *in_params,
1198 		   struct qed_rdma_create_qp_out_params *out_params)
1199 {
1200 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1201 	struct qed_rdma_qp *qp;
1202 	u8 max_stats_queues;
1203 	int rc;
1204 
1205 	if (!rdma_cxt || !in_params || !out_params || !p_hwfn->p_rdma_info) {
1206 		DP_ERR(p_hwfn->cdev,
1207 		       "qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n",
1208 		       rdma_cxt, in_params, out_params);
1209 		return NULL;
1210 	}
1211 
1212 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1213 		   "qed rdma create qp called with qp_handle = %08x%08x\n",
1214 		   in_params->qp_handle_hi, in_params->qp_handle_lo);
1215 
1216 	/* Some sanity checks... */
1217 	max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues;
1218 	if (in_params->stats_queue >= max_stats_queues) {
1219 		DP_ERR(p_hwfn->cdev,
1220 		       "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n",
1221 		       in_params->stats_queue, max_stats_queues);
1222 		return NULL;
1223 	}
1224 
1225 	if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
1226 		if (in_params->sq_num_pages * sizeof(struct regpair) >
1227 		    IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE) {
1228 			DP_NOTICE(p_hwfn->cdev,
1229 				  "Sq num pages: %d exceeds maximum\n",
1230 				  in_params->sq_num_pages);
1231 			return NULL;
1232 		}
1233 		if (in_params->rq_num_pages * sizeof(struct regpair) >
1234 		    IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE) {
1235 			DP_NOTICE(p_hwfn->cdev,
1236 				  "Rq num pages: %d exceeds maximum\n",
1237 				  in_params->rq_num_pages);
1238 			return NULL;
1239 		}
1240 	}
1241 
1242 	qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1243 	if (!qp)
1244 		return NULL;
1245 
1246 	qp->cur_state = QED_ROCE_QP_STATE_RESET;
1247 	qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi);
1248 	qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo);
1249 	qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi);
1250 	qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo);
1251 	qp->use_srq = in_params->use_srq;
1252 	qp->signal_all = in_params->signal_all;
1253 	qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey;
1254 	qp->pd = in_params->pd;
1255 	qp->dpi = in_params->dpi;
1256 	qp->sq_cq_id = in_params->sq_cq_id;
1257 	qp->sq_num_pages = in_params->sq_num_pages;
1258 	qp->sq_pbl_ptr = in_params->sq_pbl_ptr;
1259 	qp->rq_cq_id = in_params->rq_cq_id;
1260 	qp->rq_num_pages = in_params->rq_num_pages;
1261 	qp->rq_pbl_ptr = in_params->rq_pbl_ptr;
1262 	qp->srq_id = in_params->srq_id;
1263 	qp->req_offloaded = false;
1264 	qp->resp_offloaded = false;
1265 	qp->e2e_flow_control_en = qp->use_srq ? false : true;
1266 	qp->stats_queue = in_params->stats_queue;
1267 
1268 	if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
1269 		rc = qed_iwarp_create_qp(p_hwfn, qp, out_params);
1270 		qp->qpid = qp->icid;
1271 	} else {
1272 		rc = qed_roce_alloc_cid(p_hwfn, &qp->icid);
1273 		qp->qpid = ((0xFF << 16) | qp->icid);
1274 	}
1275 
1276 	if (rc) {
1277 		kfree(qp);
1278 		return NULL;
1279 	}
1280 
1281 	out_params->icid = qp->icid;
1282 	out_params->qp_id = qp->qpid;
1283 
1284 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc);
1285 	return qp;
1286 }
1287 
1288 static int qed_rdma_modify_qp(void *rdma_cxt,
1289 			      struct qed_rdma_qp *qp,
1290 			      struct qed_rdma_modify_qp_in_params *params)
1291 {
1292 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1293 	enum qed_roce_qp_state prev_state;
1294 	int rc = 0;
1295 
1296 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n",
1297 		   qp->icid, params->new_state);
1298 
1299 	if (rc) {
1300 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1301 		return rc;
1302 	}
1303 
1304 	if (GET_FIELD(params->modify_flags,
1305 		      QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) {
1306 		qp->incoming_rdma_read_en = params->incoming_rdma_read_en;
1307 		qp->incoming_rdma_write_en = params->incoming_rdma_write_en;
1308 		qp->incoming_atomic_en = params->incoming_atomic_en;
1309 	}
1310 
1311 	/* Update QP structure with the updated values */
1312 	if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE))
1313 		qp->roce_mode = params->roce_mode;
1314 	if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY))
1315 		qp->pkey = params->pkey;
1316 	if (GET_FIELD(params->modify_flags,
1317 		      QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN))
1318 		qp->e2e_flow_control_en = params->e2e_flow_control_en;
1319 	if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP))
1320 		qp->dest_qp = params->dest_qp;
1321 	if (GET_FIELD(params->modify_flags,
1322 		      QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) {
1323 		/* Indicates that the following parameters have changed:
1324 		 * Traffic class, flow label, hop limit, source GID,
1325 		 * destination GID, loopback indicator
1326 		 */
1327 		qp->traffic_class_tos = params->traffic_class_tos;
1328 		qp->flow_label = params->flow_label;
1329 		qp->hop_limit_ttl = params->hop_limit_ttl;
1330 
1331 		qp->sgid = params->sgid;
1332 		qp->dgid = params->dgid;
1333 		qp->udp_src_port = 0;
1334 		qp->vlan_id = params->vlan_id;
1335 		qp->mtu = params->mtu;
1336 		qp->lb_indication = params->lb_indication;
1337 		memcpy((u8 *)&qp->remote_mac_addr[0],
1338 		       (u8 *)&params->remote_mac_addr[0], ETH_ALEN);
1339 		if (params->use_local_mac) {
1340 			memcpy((u8 *)&qp->local_mac_addr[0],
1341 			       (u8 *)&params->local_mac_addr[0], ETH_ALEN);
1342 		} else {
1343 			memcpy((u8 *)&qp->local_mac_addr[0],
1344 			       (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN);
1345 		}
1346 	}
1347 	if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN))
1348 		qp->rq_psn = params->rq_psn;
1349 	if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN))
1350 		qp->sq_psn = params->sq_psn;
1351 	if (GET_FIELD(params->modify_flags,
1352 		      QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ))
1353 		qp->max_rd_atomic_req = params->max_rd_atomic_req;
1354 	if (GET_FIELD(params->modify_flags,
1355 		      QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP))
1356 		qp->max_rd_atomic_resp = params->max_rd_atomic_resp;
1357 	if (GET_FIELD(params->modify_flags,
1358 		      QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT))
1359 		qp->ack_timeout = params->ack_timeout;
1360 	if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT))
1361 		qp->retry_cnt = params->retry_cnt;
1362 	if (GET_FIELD(params->modify_flags,
1363 		      QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT))
1364 		qp->rnr_retry_cnt = params->rnr_retry_cnt;
1365 	if (GET_FIELD(params->modify_flags,
1366 		      QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER))
1367 		qp->min_rnr_nak_timer = params->min_rnr_nak_timer;
1368 
1369 	qp->sqd_async = params->sqd_async;
1370 
1371 	prev_state = qp->cur_state;
1372 	if (GET_FIELD(params->modify_flags,
1373 		      QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) {
1374 		qp->cur_state = params->new_state;
1375 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n",
1376 			   qp->cur_state);
1377 	}
1378 
1379 	if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
1380 		enum qed_iwarp_qp_state new_state =
1381 		    qed_roce2iwarp_state(qp->cur_state);
1382 
1383 		rc = qed_iwarp_modify_qp(p_hwfn, qp, new_state, 0);
1384 	} else {
1385 		rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params);
1386 	}
1387 
1388 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc);
1389 	return rc;
1390 }
1391 
1392 static int
1393 qed_rdma_register_tid(void *rdma_cxt,
1394 		      struct qed_rdma_register_tid_in_params *params)
1395 {
1396 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1397 	struct rdma_register_tid_ramrod_data *p_ramrod;
1398 	struct qed_sp_init_data init_data;
1399 	struct qed_spq_entry *p_ent;
1400 	enum rdma_tid_type tid_type;
1401 	u8 fw_return_code;
1402 	int rc;
1403 
1404 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", params->itid);
1405 
1406 	/* Get SPQ entry */
1407 	memset(&init_data, 0, sizeof(init_data));
1408 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1409 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1410 
1411 	rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_REGISTER_MR,
1412 				 p_hwfn->p_rdma_info->proto, &init_data);
1413 	if (rc) {
1414 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1415 		return rc;
1416 	}
1417 
1418 	if (p_hwfn->p_rdma_info->last_tid < params->itid)
1419 		p_hwfn->p_rdma_info->last_tid = params->itid;
1420 
1421 	p_ramrod = &p_ent->ramrod.rdma_register_tid;
1422 
1423 	p_ramrod->flags = 0;
1424 	SET_FIELD(p_ramrod->flags,
1425 		  RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL,
1426 		  params->pbl_two_level);
1427 
1428 	SET_FIELD(p_ramrod->flags,
1429 		  RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED, params->zbva);
1430 
1431 	SET_FIELD(p_ramrod->flags,
1432 		  RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR, params->phy_mr);
1433 
1434 	/* Don't initialize D/C field, as it may override other bits. */
1435 	if (!(params->tid_type == QED_RDMA_TID_FMR) && !(params->dma_mr))
1436 		SET_FIELD(p_ramrod->flags,
1437 			  RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG,
1438 			  params->page_size_log - 12);
1439 
1440 	SET_FIELD(p_ramrod->flags,
1441 		  RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ,
1442 		  params->remote_read);
1443 
1444 	SET_FIELD(p_ramrod->flags,
1445 		  RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE,
1446 		  params->remote_write);
1447 
1448 	SET_FIELD(p_ramrod->flags,
1449 		  RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC,
1450 		  params->remote_atomic);
1451 
1452 	SET_FIELD(p_ramrod->flags,
1453 		  RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE,
1454 		  params->local_write);
1455 
1456 	SET_FIELD(p_ramrod->flags,
1457 		  RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ, params->local_read);
1458 
1459 	SET_FIELD(p_ramrod->flags,
1460 		  RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND,
1461 		  params->mw_bind);
1462 
1463 	SET_FIELD(p_ramrod->flags1,
1464 		  RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG,
1465 		  params->pbl_page_size_log - 12);
1466 
1467 	SET_FIELD(p_ramrod->flags2,
1468 		  RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR, params->dma_mr);
1469 
1470 	switch (params->tid_type) {
1471 	case QED_RDMA_TID_REGISTERED_MR:
1472 		tid_type = RDMA_TID_REGISTERED_MR;
1473 		break;
1474 	case QED_RDMA_TID_FMR:
1475 		tid_type = RDMA_TID_FMR;
1476 		break;
1477 	case QED_RDMA_TID_MW_TYPE1:
1478 		tid_type = RDMA_TID_MW_TYPE1;
1479 		break;
1480 	case QED_RDMA_TID_MW_TYPE2A:
1481 		tid_type = RDMA_TID_MW_TYPE2A;
1482 		break;
1483 	default:
1484 		rc = -EINVAL;
1485 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1486 		return rc;
1487 	}
1488 	SET_FIELD(p_ramrod->flags1,
1489 		  RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE, tid_type);
1490 
1491 	p_ramrod->itid = cpu_to_le32(params->itid);
1492 	p_ramrod->key = params->key;
1493 	p_ramrod->pd = cpu_to_le16(params->pd);
1494 	p_ramrod->length_hi = (u8)(params->length >> 32);
1495 	p_ramrod->length_lo = DMA_LO_LE(params->length);
1496 	if (params->zbva) {
1497 		/* Lower 32 bits of the registered MR address.
1498 		 * In case of zero based MR, will hold FBO
1499 		 */
1500 		p_ramrod->va.hi = 0;
1501 		p_ramrod->va.lo = cpu_to_le32(params->fbo);
1502 	} else {
1503 		DMA_REGPAIR_LE(p_ramrod->va, params->vaddr);
1504 	}
1505 	DMA_REGPAIR_LE(p_ramrod->pbl_base, params->pbl_ptr);
1506 
1507 	/* DIF */
1508 	if (params->dif_enabled) {
1509 		SET_FIELD(p_ramrod->flags2,
1510 			  RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG, 1);
1511 		DMA_REGPAIR_LE(p_ramrod->dif_error_addr,
1512 			       params->dif_error_addr);
1513 		DMA_REGPAIR_LE(p_ramrod->dif_runt_addr, params->dif_runt_addr);
1514 	}
1515 
1516 	rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
1517 	if (rc)
1518 		return rc;
1519 
1520 	if (fw_return_code != RDMA_RETURN_OK) {
1521 		DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
1522 		return -EINVAL;
1523 	}
1524 
1525 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Register TID, rc = %d\n", rc);
1526 	return rc;
1527 }
1528 
1529 static int qed_rdma_deregister_tid(void *rdma_cxt, u32 itid)
1530 {
1531 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1532 	struct rdma_deregister_tid_ramrod_data *p_ramrod;
1533 	struct qed_sp_init_data init_data;
1534 	struct qed_spq_entry *p_ent;
1535 	struct qed_ptt *p_ptt;
1536 	u8 fw_return_code;
1537 	int rc;
1538 
1539 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid);
1540 
1541 	/* Get SPQ entry */
1542 	memset(&init_data, 0, sizeof(init_data));
1543 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1544 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1545 
1546 	rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_DEREGISTER_MR,
1547 				 p_hwfn->p_rdma_info->proto, &init_data);
1548 	if (rc) {
1549 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1550 		return rc;
1551 	}
1552 
1553 	p_ramrod = &p_ent->ramrod.rdma_deregister_tid;
1554 	p_ramrod->itid = cpu_to_le32(itid);
1555 
1556 	rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
1557 	if (rc) {
1558 		DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1559 		return rc;
1560 	}
1561 
1562 	if (fw_return_code == RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR) {
1563 		DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
1564 		return -EINVAL;
1565 	} else if (fw_return_code == RDMA_RETURN_NIG_DRAIN_REQ) {
1566 		/* Bit indicating that the TID is in use and a nig drain is
1567 		 * required before sending the ramrod again
1568 		 */
1569 		p_ptt = qed_ptt_acquire(p_hwfn);
1570 		if (!p_ptt) {
1571 			rc = -EBUSY;
1572 			DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1573 				   "Failed to acquire PTT\n");
1574 			return rc;
1575 		}
1576 
1577 		rc = qed_mcp_drain(p_hwfn, p_ptt);
1578 		if (rc) {
1579 			qed_ptt_release(p_hwfn, p_ptt);
1580 			DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1581 				   "Drain failed\n");
1582 			return rc;
1583 		}
1584 
1585 		qed_ptt_release(p_hwfn, p_ptt);
1586 
1587 		/* Resend the ramrod */
1588 		rc = qed_sp_init_request(p_hwfn, &p_ent,
1589 					 RDMA_RAMROD_DEREGISTER_MR,
1590 					 p_hwfn->p_rdma_info->proto,
1591 					 &init_data);
1592 		if (rc) {
1593 			DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1594 				   "Failed to init sp-element\n");
1595 			return rc;
1596 		}
1597 
1598 		rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
1599 		if (rc) {
1600 			DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1601 				   "Ramrod failed\n");
1602 			return rc;
1603 		}
1604 
1605 		if (fw_return_code != RDMA_RETURN_OK) {
1606 			DP_NOTICE(p_hwfn, "fw_return_code = %d\n",
1607 				  fw_return_code);
1608 			return rc;
1609 		}
1610 	}
1611 
1612 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "De-registered TID, rc = %d\n", rc);
1613 	return rc;
1614 }
1615 
1616 static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev)
1617 {
1618 	return QED_LEADING_HWFN(cdev);
1619 }
1620 
1621 bool qed_rdma_allocated_qps(struct qed_hwfn *p_hwfn)
1622 {
1623 	bool result;
1624 
1625 	/* if rdma info has not been allocated, naturally there are no qps */
1626 	if (!p_hwfn->p_rdma_info)
1627 		return false;
1628 
1629 	spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1630 	if (!p_hwfn->p_rdma_info->cid_map.bitmap)
1631 		result = false;
1632 	else
1633 		result = !qed_bmap_is_empty(&p_hwfn->p_rdma_info->cid_map);
1634 	spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1635 	return result;
1636 }
1637 
1638 void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1639 {
1640 	u32 val;
1641 
1642 	val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1;
1643 
1644 	qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val);
1645 	DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA),
1646 		   "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n",
1647 		   val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm);
1648 }
1649 
1650 
1651 void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1652 {
1653 	p_hwfn->db_bar_no_edpm = true;
1654 
1655 	qed_rdma_dpm_conf(p_hwfn, p_ptt);
1656 }
1657 
1658 static int qed_rdma_start(void *rdma_cxt,
1659 			  struct qed_rdma_start_in_params *params)
1660 {
1661 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1662 	struct qed_ptt *p_ptt;
1663 	int rc = -EBUSY;
1664 
1665 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1666 		   "desired_cnq = %08x\n", params->desired_cnq);
1667 
1668 	p_ptt = qed_ptt_acquire(p_hwfn);
1669 	if (!p_ptt)
1670 		goto err;
1671 
1672 	rc = qed_rdma_alloc(p_hwfn, p_ptt, params);
1673 	if (rc)
1674 		goto err1;
1675 
1676 	rc = qed_rdma_setup(p_hwfn, p_ptt, params);
1677 	if (rc)
1678 		goto err2;
1679 
1680 	qed_ptt_release(p_hwfn, p_ptt);
1681 
1682 	return rc;
1683 
1684 err2:
1685 	qed_rdma_free(p_hwfn);
1686 err1:
1687 	qed_ptt_release(p_hwfn, p_ptt);
1688 err:
1689 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc);
1690 	return rc;
1691 }
1692 
1693 static int qed_rdma_init(struct qed_dev *cdev,
1694 			 struct qed_rdma_start_in_params *params)
1695 {
1696 	return qed_rdma_start(QED_LEADING_HWFN(cdev), params);
1697 }
1698 
1699 static void qed_rdma_remove_user(void *rdma_cxt, u16 dpi)
1700 {
1701 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1702 
1703 	DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi);
1704 
1705 	spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1706 	qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi);
1707 	spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1708 }
1709 
1710 static int qed_roce_ll2_set_mac_filter(struct qed_dev *cdev,
1711 				       u8 *old_mac_address,
1712 				       u8 *new_mac_address)
1713 {
1714 	struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1715 	struct qed_ptt *p_ptt;
1716 	int rc = 0;
1717 
1718 	p_ptt = qed_ptt_acquire(p_hwfn);
1719 	if (!p_ptt) {
1720 		DP_ERR(cdev,
1721 		       "qed roce ll2 mac filter set: failed to acquire PTT\n");
1722 		return -EINVAL;
1723 	}
1724 
1725 	if (old_mac_address)
1726 		qed_llh_remove_mac_filter(p_hwfn, p_ptt, old_mac_address);
1727 	if (new_mac_address)
1728 		rc = qed_llh_add_mac_filter(p_hwfn, p_ptt, new_mac_address);
1729 
1730 	qed_ptt_release(p_hwfn, p_ptt);
1731 
1732 	if (rc)
1733 		DP_ERR(cdev,
1734 		       "qed roce ll2 mac filter set: failed to add MAC filter\n");
1735 
1736 	return rc;
1737 }
1738 
1739 static const struct qed_rdma_ops qed_rdma_ops_pass = {
1740 	.common = &qed_common_ops_pass,
1741 	.fill_dev_info = &qed_fill_rdma_dev_info,
1742 	.rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx,
1743 	.rdma_init = &qed_rdma_init,
1744 	.rdma_add_user = &qed_rdma_add_user,
1745 	.rdma_remove_user = &qed_rdma_remove_user,
1746 	.rdma_stop = &qed_rdma_stop,
1747 	.rdma_query_port = &qed_rdma_query_port,
1748 	.rdma_query_device = &qed_rdma_query_device,
1749 	.rdma_get_start_sb = &qed_rdma_get_sb_start,
1750 	.rdma_get_rdma_int = &qed_rdma_get_int,
1751 	.rdma_set_rdma_int = &qed_rdma_set_int,
1752 	.rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix,
1753 	.rdma_cnq_prod_update = &qed_rdma_cnq_prod_update,
1754 	.rdma_alloc_pd = &qed_rdma_alloc_pd,
1755 	.rdma_dealloc_pd = &qed_rdma_free_pd,
1756 	.rdma_create_cq = &qed_rdma_create_cq,
1757 	.rdma_destroy_cq = &qed_rdma_destroy_cq,
1758 	.rdma_create_qp = &qed_rdma_create_qp,
1759 	.rdma_modify_qp = &qed_rdma_modify_qp,
1760 	.rdma_query_qp = &qed_rdma_query_qp,
1761 	.rdma_destroy_qp = &qed_rdma_destroy_qp,
1762 	.rdma_alloc_tid = &qed_rdma_alloc_tid,
1763 	.rdma_free_tid = &qed_rdma_free_tid,
1764 	.rdma_register_tid = &qed_rdma_register_tid,
1765 	.rdma_deregister_tid = &qed_rdma_deregister_tid,
1766 	.ll2_acquire_connection = &qed_ll2_acquire_connection,
1767 	.ll2_establish_connection = &qed_ll2_establish_connection,
1768 	.ll2_terminate_connection = &qed_ll2_terminate_connection,
1769 	.ll2_release_connection = &qed_ll2_release_connection,
1770 	.ll2_post_rx_buffer = &qed_ll2_post_rx_buffer,
1771 	.ll2_prepare_tx_packet = &qed_ll2_prepare_tx_packet,
1772 	.ll2_set_fragment_of_tx_packet = &qed_ll2_set_fragment_of_tx_packet,
1773 	.ll2_set_mac_filter = &qed_roce_ll2_set_mac_filter,
1774 	.ll2_get_stats = &qed_ll2_get_stats,
1775 	.iwarp_connect = &qed_iwarp_connect,
1776 	.iwarp_create_listen = &qed_iwarp_create_listen,
1777 	.iwarp_destroy_listen = &qed_iwarp_destroy_listen,
1778 	.iwarp_accept = &qed_iwarp_accept,
1779 	.iwarp_reject = &qed_iwarp_reject,
1780 	.iwarp_send_rtr = &qed_iwarp_send_rtr,
1781 };
1782 
1783 const struct qed_rdma_ops *qed_get_rdma_ops(void)
1784 {
1785 	return &qed_rdma_ops_pass;
1786 }
1787 EXPORT_SYMBOL(qed_get_rdma_ops);
1788