1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 /* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7 #include <linux/types.h> 8 #include <asm/byteorder.h> 9 #include <linux/bitops.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/errno.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/list.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/pci.h> 19 #include <linux/slab.h> 20 #include <linux/spinlock.h> 21 #include <linux/string.h> 22 #include <net/addrconf.h> 23 #include "qed.h" 24 #include "qed_cxt.h" 25 #include "qed_hsi.h" 26 #include "qed_hw.h" 27 #include "qed_init_ops.h" 28 #include "qed_int.h" 29 #include "qed_ll2.h" 30 #include "qed_mcp.h" 31 #include "qed_reg_addr.h" 32 #include <linux/qed/qed_rdma_if.h> 33 #include "qed_rdma.h" 34 #include "qed_roce.h" 35 #include "qed_sp.h" 36 37 38 int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn, 39 struct qed_bmap *bmap, u32 max_count, char *name) 40 { 41 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count); 42 43 bmap->max_count = max_count; 44 45 bmap->bitmap = kcalloc(BITS_TO_LONGS(max_count), sizeof(long), 46 GFP_KERNEL); 47 if (!bmap->bitmap) 48 return -ENOMEM; 49 50 snprintf(bmap->name, QED_RDMA_MAX_BMAP_NAME, "%s", name); 51 52 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 53 return 0; 54 } 55 56 int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn, 57 struct qed_bmap *bmap, u32 *id_num) 58 { 59 *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count); 60 if (*id_num >= bmap->max_count) 61 return -EINVAL; 62 63 __set_bit(*id_num, bmap->bitmap); 64 65 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: allocated id %d\n", 66 bmap->name, *id_num); 67 68 return 0; 69 } 70 71 void qed_bmap_set_id(struct qed_hwfn *p_hwfn, 72 struct qed_bmap *bmap, u32 id_num) 73 { 74 if (id_num >= bmap->max_count) 75 return; 76 77 __set_bit(id_num, bmap->bitmap); 78 } 79 80 void qed_bmap_release_id(struct qed_hwfn *p_hwfn, 81 struct qed_bmap *bmap, u32 id_num) 82 { 83 bool b_acquired; 84 85 if (id_num >= bmap->max_count) 86 return; 87 88 b_acquired = test_and_clear_bit(id_num, bmap->bitmap); 89 if (!b_acquired) { 90 DP_NOTICE(p_hwfn, "%s bitmap: id %d already released\n", 91 bmap->name, id_num); 92 return; 93 } 94 95 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: released id %d\n", 96 bmap->name, id_num); 97 } 98 99 int qed_bmap_test_id(struct qed_hwfn *p_hwfn, 100 struct qed_bmap *bmap, u32 id_num) 101 { 102 if (id_num >= bmap->max_count) 103 return -1; 104 105 return test_bit(id_num, bmap->bitmap); 106 } 107 108 static bool qed_bmap_is_empty(struct qed_bmap *bmap) 109 { 110 return bmap->max_count == find_first_bit(bmap->bitmap, bmap->max_count); 111 } 112 113 static u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id) 114 { 115 /* First sb id for RoCE is after all the l2 sb */ 116 return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id; 117 } 118 119 int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn) 120 { 121 struct qed_rdma_info *p_rdma_info; 122 123 p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL); 124 if (!p_rdma_info) 125 return -ENOMEM; 126 127 spin_lock_init(&p_rdma_info->lock); 128 129 p_hwfn->p_rdma_info = p_rdma_info; 130 return 0; 131 } 132 133 void qed_rdma_info_free(struct qed_hwfn *p_hwfn) 134 { 135 kfree(p_hwfn->p_rdma_info); 136 p_hwfn->p_rdma_info = NULL; 137 } 138 139 static int qed_rdma_alloc(struct qed_hwfn *p_hwfn) 140 { 141 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 142 u32 num_cons, num_tasks; 143 int rc = -ENOMEM; 144 145 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n"); 146 147 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 148 p_rdma_info->proto = PROTOCOLID_IWARP; 149 else 150 p_rdma_info->proto = PROTOCOLID_ROCE; 151 152 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto, 153 NULL); 154 155 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 156 p_rdma_info->num_qps = num_cons; 157 else 158 p_rdma_info->num_qps = num_cons / 2; /* 2 cids per qp */ 159 160 num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE); 161 162 /* Each MR uses a single task */ 163 p_rdma_info->num_mrs = num_tasks; 164 165 /* Queue zone lines are shared between RoCE and L2 in such a way that 166 * they can be used by each without obstructing the other. 167 */ 168 p_rdma_info->queue_zone_base = (u16)RESC_START(p_hwfn, QED_L2_QUEUE); 169 p_rdma_info->max_queue_zones = (u16)RESC_NUM(p_hwfn, QED_L2_QUEUE); 170 171 /* Allocate a struct with device params and fill it */ 172 p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL); 173 if (!p_rdma_info->dev) 174 return rc; 175 176 /* Allocate a struct with port params and fill it */ 177 p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL); 178 if (!p_rdma_info->port) 179 goto free_rdma_dev; 180 181 /* Allocate bit map for pd's */ 182 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS, 183 "PD"); 184 if (rc) { 185 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 186 "Failed to allocate pd_map, rc = %d\n", 187 rc); 188 goto free_rdma_port; 189 } 190 191 /* Allocate bit map for XRC Domains */ 192 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->xrcd_map, 193 QED_RDMA_MAX_XRCDS, "XRCD"); 194 if (rc) { 195 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 196 "Failed to allocate xrcd_map,rc = %d\n", rc); 197 goto free_pd_map; 198 } 199 200 /* Allocate DPI bitmap */ 201 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map, 202 p_hwfn->dpi_count, "DPI"); 203 if (rc) { 204 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 205 "Failed to allocate DPI bitmap, rc = %d\n", rc); 206 goto free_xrcd_map; 207 } 208 209 /* Allocate bitmap for cq's. The maximum number of CQs is bound to 210 * the number of connections we support. (num_qps in iWARP or 211 * num_qps/2 in RoCE). 212 */ 213 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map, num_cons, "CQ"); 214 if (rc) { 215 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 216 "Failed to allocate cq bitmap, rc = %d\n", rc); 217 goto free_dpi_map; 218 } 219 220 /* Allocate bitmap for toggle bit for cq icids 221 * We toggle the bit every time we create or resize cq for a given icid. 222 * Size needs to equal the size of the cq bmap. 223 */ 224 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits, 225 num_cons, "Toggle"); 226 if (rc) { 227 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 228 "Failed to allocate toggle bits, rc = %d\n", rc); 229 goto free_cq_map; 230 } 231 232 /* Allocate bitmap for itids */ 233 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map, 234 p_rdma_info->num_mrs, "MR"); 235 if (rc) { 236 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 237 "Failed to allocate itids bitmaps, rc = %d\n", rc); 238 goto free_toggle_map; 239 } 240 241 /* Allocate bitmap for cids used for qps. */ 242 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons, 243 "CID"); 244 if (rc) { 245 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 246 "Failed to allocate cid bitmap, rc = %d\n", rc); 247 goto free_tid_map; 248 } 249 250 /* Allocate bitmap for cids used for responders/requesters. */ 251 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->real_cid_map, num_cons, 252 "REAL_CID"); 253 if (rc) { 254 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 255 "Failed to allocate real cid bitmap, rc = %d\n", rc); 256 goto free_cid_map; 257 } 258 259 /* The first SRQ follows the last XRC SRQ. This means that the 260 * SRQ IDs start from an offset equals to max_xrc_srqs. 261 */ 262 p_rdma_info->srq_id_offset = p_hwfn->p_cxt_mngr->xrc_srq_count; 263 rc = qed_rdma_bmap_alloc(p_hwfn, 264 &p_rdma_info->xrc_srq_map, 265 p_hwfn->p_cxt_mngr->xrc_srq_count, "XRC SRQ"); 266 if (rc) { 267 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 268 "Failed to allocate xrc srq bitmap, rc = %d\n", rc); 269 goto free_real_cid_map; 270 } 271 272 /* Allocate bitmap for srqs */ 273 p_rdma_info->num_srqs = p_hwfn->p_cxt_mngr->srq_count; 274 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->srq_map, 275 p_rdma_info->num_srqs, "SRQ"); 276 if (rc) { 277 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 278 "Failed to allocate srq bitmap, rc = %d\n", rc); 279 goto free_xrc_srq_map; 280 } 281 282 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 283 rc = qed_iwarp_alloc(p_hwfn); 284 285 if (rc) 286 goto free_srq_map; 287 288 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n"); 289 return 0; 290 291 free_srq_map: 292 kfree(p_rdma_info->srq_map.bitmap); 293 free_xrc_srq_map: 294 kfree(p_rdma_info->xrc_srq_map.bitmap); 295 free_real_cid_map: 296 kfree(p_rdma_info->real_cid_map.bitmap); 297 free_cid_map: 298 kfree(p_rdma_info->cid_map.bitmap); 299 free_tid_map: 300 kfree(p_rdma_info->tid_map.bitmap); 301 free_toggle_map: 302 kfree(p_rdma_info->toggle_bits.bitmap); 303 free_cq_map: 304 kfree(p_rdma_info->cq_map.bitmap); 305 free_dpi_map: 306 kfree(p_rdma_info->dpi_map.bitmap); 307 free_xrcd_map: 308 kfree(p_rdma_info->xrcd_map.bitmap); 309 free_pd_map: 310 kfree(p_rdma_info->pd_map.bitmap); 311 free_rdma_port: 312 kfree(p_rdma_info->port); 313 free_rdma_dev: 314 kfree(p_rdma_info->dev); 315 316 return rc; 317 } 318 319 void qed_rdma_bmap_free(struct qed_hwfn *p_hwfn, 320 struct qed_bmap *bmap, bool check) 321 { 322 int weight = bitmap_weight(bmap->bitmap, bmap->max_count); 323 int last_line = bmap->max_count / (64 * 8); 324 int last_item = last_line * 8 + 325 DIV_ROUND_UP(bmap->max_count % (64 * 8), 64); 326 u64 *pmap = (u64 *)bmap->bitmap; 327 int line, item, offset; 328 u8 str_last_line[200] = { 0 }; 329 330 if (!weight || !check) 331 goto end; 332 333 DP_NOTICE(p_hwfn, 334 "%s bitmap not free - size=%d, weight=%d, 512 bits per line\n", 335 bmap->name, bmap->max_count, weight); 336 337 /* print aligned non-zero lines, if any */ 338 for (item = 0, line = 0; line < last_line; line++, item += 8) 339 if (bitmap_weight((unsigned long *)&pmap[item], 64 * 8)) 340 DP_NOTICE(p_hwfn, 341 "line 0x%04x: 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx\n", 342 line, 343 pmap[item], 344 pmap[item + 1], 345 pmap[item + 2], 346 pmap[item + 3], 347 pmap[item + 4], 348 pmap[item + 5], 349 pmap[item + 6], pmap[item + 7]); 350 351 /* print last unaligned non-zero line, if any */ 352 if ((bmap->max_count % (64 * 8)) && 353 (bitmap_weight((unsigned long *)&pmap[item], 354 bmap->max_count - item * 64))) { 355 offset = sprintf(str_last_line, "line 0x%04x: ", line); 356 for (; item < last_item; item++) 357 offset += sprintf(str_last_line + offset, 358 "0x%016llx ", pmap[item]); 359 DP_NOTICE(p_hwfn, "%s\n", str_last_line); 360 } 361 362 end: 363 kfree(bmap->bitmap); 364 bmap->bitmap = NULL; 365 } 366 367 static void qed_rdma_resc_free(struct qed_hwfn *p_hwfn) 368 { 369 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 370 371 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 372 qed_iwarp_resc_free(p_hwfn); 373 374 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cid_map, 1); 375 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->pd_map, 1); 376 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 1); 377 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cq_map, 1); 378 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->toggle_bits, 0); 379 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->tid_map, 1); 380 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->srq_map, 1); 381 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, 1); 382 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->xrc_srq_map, 1); 383 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->xrcd_map, 1); 384 385 kfree(p_rdma_info->port); 386 kfree(p_rdma_info->dev); 387 } 388 389 static void qed_rdma_free_tid(void *rdma_cxt, u32 itid) 390 { 391 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 392 393 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 394 395 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 396 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->tid_map, itid); 397 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 398 } 399 400 static void qed_rdma_free_reserved_lkey(struct qed_hwfn *p_hwfn) 401 { 402 qed_rdma_free_tid(p_hwfn, p_hwfn->p_rdma_info->dev->reserved_lkey); 403 } 404 405 static void qed_rdma_free(struct qed_hwfn *p_hwfn) 406 { 407 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n"); 408 409 qed_rdma_free_reserved_lkey(p_hwfn); 410 qed_cxt_free_proto_ilt(p_hwfn, p_hwfn->p_rdma_info->proto); 411 qed_rdma_resc_free(p_hwfn); 412 } 413 414 static void qed_rdma_init_events(struct qed_hwfn *p_hwfn, 415 struct qed_rdma_start_in_params *params) 416 { 417 struct qed_rdma_events *events; 418 419 events = &p_hwfn->p_rdma_info->events; 420 421 events->unaffiliated_event = params->events->unaffiliated_event; 422 events->affiliated_event = params->events->affiliated_event; 423 events->context = params->events->context; 424 } 425 426 static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn, 427 struct qed_rdma_start_in_params *params) 428 { 429 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 430 struct qed_dev *cdev = p_hwfn->cdev; 431 u32 pci_status_control; 432 u32 num_qps; 433 434 /* Vendor specific information */ 435 dev->vendor_id = cdev->vendor_id; 436 dev->vendor_part_id = cdev->device_id; 437 dev->hw_ver = cdev->chip_rev; 438 dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | 439 (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION); 440 441 addrconf_addr_eui48((u8 *)&dev->sys_image_guid, 442 p_hwfn->hw_info.hw_mac_addr); 443 444 dev->node_guid = dev->sys_image_guid; 445 446 dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE, 447 RDMA_MAX_SGE_PER_RQ_WQE); 448 449 if (cdev->rdma_max_sge) 450 dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge); 451 452 dev->max_srq_sge = QED_RDMA_MAX_SGE_PER_SRQ_WQE; 453 if (p_hwfn->cdev->rdma_max_srq_sge) { 454 dev->max_srq_sge = min_t(u32, 455 p_hwfn->cdev->rdma_max_srq_sge, 456 dev->max_srq_sge); 457 } 458 dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE; 459 460 dev->max_inline = (cdev->rdma_max_inline) ? 461 min_t(u32, cdev->rdma_max_inline, dev->max_inline) : 462 dev->max_inline; 463 464 dev->max_wqe = QED_RDMA_MAX_WQE; 465 dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ); 466 467 /* The number of QPs may be higher than QED_ROCE_MAX_QPS, because 468 * it is up-aligned to 16 and then to ILT page size within qed cxt. 469 * This is OK in terms of ILT but we don't want to configure the FW 470 * above its abilities 471 */ 472 num_qps = ROCE_MAX_QPS; 473 num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps); 474 dev->max_qp = num_qps; 475 476 /* CQs uses the same icids that QPs use hence they are limited by the 477 * number of icids. There are two icids per QP. 478 */ 479 dev->max_cq = num_qps * 2; 480 481 /* The number of mrs is smaller by 1 since the first is reserved */ 482 dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1; 483 dev->max_mr_size = QED_RDMA_MAX_MR_SIZE; 484 485 /* The maximum CQE capacity per CQ supported. 486 * max number of cqes will be in two layer pbl, 487 * 8 is the pointer size in bytes 488 * 32 is the size of cq element in bytes 489 */ 490 if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS) 491 dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT; 492 else 493 dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT; 494 495 dev->max_mw = 0; 496 dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8); 497 dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE; 498 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 499 dev->max_pkey = QED_RDMA_MAX_P_KEY; 500 501 dev->max_srq = p_hwfn->p_rdma_info->num_srqs; 502 dev->max_srq_wr = QED_RDMA_MAX_SRQ_WQE_ELEM; 503 dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 504 (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2); 505 dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 506 RDMA_REQ_RD_ATOMIC_ELM_SIZE; 507 dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc * 508 p_hwfn->p_rdma_info->num_qps; 509 dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS; 510 dev->dev_ack_delay = QED_RDMA_ACK_DELAY; 511 dev->max_pd = RDMA_MAX_PDS; 512 dev->max_ah = p_hwfn->p_rdma_info->num_qps; 513 dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE); 514 515 /* Set capablities */ 516 dev->dev_caps = 0; 517 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1); 518 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1); 519 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1); 520 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1); 521 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1); 522 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1); 523 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1); 524 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1); 525 526 /* Check atomic operations support in PCI configuration space. */ 527 pcie_capability_read_dword(cdev->pdev, PCI_EXP_DEVCTL2, 528 &pci_status_control); 529 530 if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN) 531 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1); 532 533 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 534 qed_iwarp_init_devinfo(p_hwfn); 535 } 536 537 static void qed_rdma_init_port(struct qed_hwfn *p_hwfn) 538 { 539 struct qed_rdma_port *port = p_hwfn->p_rdma_info->port; 540 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 541 542 port->port_state = p_hwfn->mcp_info->link_output.link_up ? 543 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN; 544 545 port->max_msg_size = min_t(u64, 546 (dev->max_mr_mw_fmr_size * 547 p_hwfn->cdev->rdma_max_sge), 548 BIT(31)); 549 550 port->pkey_bad_counter = 0; 551 } 552 553 static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 554 { 555 int rc = 0; 556 557 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n"); 558 p_hwfn->b_rdma_enabled_in_prs = false; 559 560 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 561 qed_iwarp_init_hw(p_hwfn, p_ptt); 562 else 563 rc = qed_roce_init_hw(p_hwfn, p_ptt); 564 565 return rc; 566 } 567 568 static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn, 569 struct qed_rdma_start_in_params *params, 570 struct qed_ptt *p_ptt) 571 { 572 struct rdma_init_func_ramrod_data *p_ramrod; 573 struct qed_rdma_cnq_params *p_cnq_pbl_list; 574 struct rdma_init_func_hdr *p_params_header; 575 struct rdma_cnq_params *p_cnq_params; 576 struct qed_sp_init_data init_data; 577 struct qed_spq_entry *p_ent; 578 u32 cnq_id, sb_id; 579 u16 igu_sb_id; 580 int rc; 581 582 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n"); 583 584 /* Save the number of cnqs for the function close ramrod */ 585 p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq; 586 587 /* Get SPQ entry */ 588 memset(&init_data, 0, sizeof(init_data)); 589 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 590 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 591 592 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT, 593 p_hwfn->p_rdma_info->proto, &init_data); 594 if (rc) 595 return rc; 596 597 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 598 qed_iwarp_init_fw_ramrod(p_hwfn, 599 &p_ent->ramrod.iwarp_init_func); 600 p_ramrod = &p_ent->ramrod.iwarp_init_func.rdma; 601 } else { 602 p_ramrod = &p_ent->ramrod.roce_init_func.rdma; 603 } 604 605 p_params_header = &p_ramrod->params_header; 606 p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn, 607 QED_RDMA_CNQ_RAM); 608 p_params_header->num_cnqs = params->desired_cnq; 609 p_params_header->first_reg_srq_id = 610 cpu_to_le16(p_hwfn->p_rdma_info->srq_id_offset); 611 p_params_header->reg_srq_base_addr = 612 cpu_to_le32(qed_cxt_get_ilt_page_size(p_hwfn, ILT_CLI_TSDM)); 613 if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS) 614 p_params_header->cq_ring_mode = 1; 615 else 616 p_params_header->cq_ring_mode = 0; 617 618 for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) { 619 sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id); 620 igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 621 p_ramrod->cnq_params[cnq_id].sb_num = cpu_to_le16(igu_sb_id); 622 p_cnq_params = &p_ramrod->cnq_params[cnq_id]; 623 p_cnq_pbl_list = ¶ms->cnq_pbl_list[cnq_id]; 624 625 p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi; 626 p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages; 627 628 DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr, 629 p_cnq_pbl_list->pbl_ptr); 630 631 /* we assume here that cnq_id and qz_offset are the same */ 632 p_cnq_params->queue_zone_num = 633 cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base + 634 cnq_id); 635 } 636 637 return qed_spq_post(p_hwfn, p_ent, NULL); 638 } 639 640 static int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid) 641 { 642 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 643 int rc; 644 645 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n"); 646 647 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 648 rc = qed_rdma_bmap_alloc_id(p_hwfn, 649 &p_hwfn->p_rdma_info->tid_map, itid); 650 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 651 if (rc) 652 goto out; 653 654 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid); 655 out: 656 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc); 657 return rc; 658 } 659 660 static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn) 661 { 662 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 663 664 /* Tid 0 will be used as the key for "reserved MR". 665 * The driver should allocate memory for it so it can be loaded but no 666 * ramrod should be passed on it. 667 */ 668 qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey); 669 if (dev->reserved_lkey != RDMA_RESERVED_LKEY) { 670 DP_NOTICE(p_hwfn, 671 "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n"); 672 return -EINVAL; 673 } 674 675 return 0; 676 } 677 678 static int qed_rdma_setup(struct qed_hwfn *p_hwfn, 679 struct qed_ptt *p_ptt, 680 struct qed_rdma_start_in_params *params) 681 { 682 int rc; 683 684 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n"); 685 686 qed_rdma_init_devinfo(p_hwfn, params); 687 qed_rdma_init_port(p_hwfn); 688 qed_rdma_init_events(p_hwfn, params); 689 690 rc = qed_rdma_reserve_lkey(p_hwfn); 691 if (rc) 692 return rc; 693 694 rc = qed_rdma_init_hw(p_hwfn, p_ptt); 695 if (rc) 696 return rc; 697 698 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 699 rc = qed_iwarp_setup(p_hwfn, params); 700 if (rc) 701 return rc; 702 } else { 703 rc = qed_roce_setup(p_hwfn); 704 if (rc) 705 return rc; 706 } 707 708 return qed_rdma_start_fw(p_hwfn, params, p_ptt); 709 } 710 711 static int qed_rdma_stop(void *rdma_cxt) 712 { 713 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 714 struct rdma_close_func_ramrod_data *p_ramrod; 715 struct qed_sp_init_data init_data; 716 struct qed_spq_entry *p_ent; 717 struct qed_ptt *p_ptt; 718 u32 ll2_ethertype_en; 719 int rc = -EBUSY; 720 721 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n"); 722 723 p_ptt = qed_ptt_acquire(p_hwfn); 724 if (!p_ptt) { 725 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n"); 726 return rc; 727 } 728 729 /* Disable RoCE search */ 730 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0); 731 p_hwfn->b_rdma_enabled_in_prs = false; 732 p_hwfn->p_rdma_info->active = 0; 733 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 734 735 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 736 737 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 738 (ll2_ethertype_en & 0xFFFE)); 739 740 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 741 rc = qed_iwarp_stop(p_hwfn); 742 if (rc) { 743 qed_ptt_release(p_hwfn, p_ptt); 744 return rc; 745 } 746 } else { 747 qed_roce_stop(p_hwfn); 748 } 749 750 qed_ptt_release(p_hwfn, p_ptt); 751 752 /* Get SPQ entry */ 753 memset(&init_data, 0, sizeof(init_data)); 754 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 755 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 756 757 /* Stop RoCE */ 758 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE, 759 p_hwfn->p_rdma_info->proto, &init_data); 760 if (rc) 761 goto out; 762 763 p_ramrod = &p_ent->ramrod.rdma_close_func; 764 765 p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs; 766 p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM); 767 768 rc = qed_spq_post(p_hwfn, p_ent, NULL); 769 770 out: 771 qed_rdma_free(p_hwfn); 772 773 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc); 774 return rc; 775 } 776 777 static int qed_rdma_add_user(void *rdma_cxt, 778 struct qed_rdma_add_user_out_params *out_params) 779 { 780 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 781 u32 dpi_start_offset; 782 u32 returned_id = 0; 783 int rc; 784 785 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n"); 786 787 /* Allocate DPI */ 788 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 789 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 790 &returned_id); 791 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 792 793 out_params->dpi = (u16)returned_id; 794 795 /* Calculate the corresponding DPI address */ 796 dpi_start_offset = p_hwfn->dpi_start_offset; 797 798 out_params->dpi_addr = p_hwfn->doorbells + dpi_start_offset + 799 out_params->dpi * p_hwfn->dpi_size; 800 801 out_params->dpi_phys_addr = p_hwfn->db_phys_addr + 802 dpi_start_offset + 803 ((out_params->dpi) * p_hwfn->dpi_size); 804 805 out_params->dpi_size = p_hwfn->dpi_size; 806 out_params->wid_count = p_hwfn->wid_count; 807 808 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc); 809 return rc; 810 } 811 812 static struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt) 813 { 814 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 815 struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port; 816 struct qed_mcp_link_state *p_link_output; 817 818 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n"); 819 820 /* The link state is saved only for the leading hwfn */ 821 p_link_output = &QED_LEADING_HWFN(p_hwfn->cdev)->mcp_info->link_output; 822 823 p_port->port_state = p_link_output->link_up ? QED_RDMA_PORT_UP 824 : QED_RDMA_PORT_DOWN; 825 826 p_port->link_speed = p_link_output->speed; 827 828 p_port->max_msg_size = RDMA_MAX_DATA_SIZE_IN_WQE; 829 830 return p_port; 831 } 832 833 static struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt) 834 { 835 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 836 837 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n"); 838 839 /* Return struct with device parameters */ 840 return p_hwfn->p_rdma_info->dev; 841 } 842 843 static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod) 844 { 845 struct qed_hwfn *p_hwfn; 846 u16 qz_num; 847 u32 addr; 848 849 p_hwfn = (struct qed_hwfn *)rdma_cxt; 850 851 if (qz_offset > p_hwfn->p_rdma_info->max_queue_zones) { 852 DP_NOTICE(p_hwfn, 853 "queue zone offset %d is too large (max is %d)\n", 854 qz_offset, p_hwfn->p_rdma_info->max_queue_zones); 855 return; 856 } 857 858 qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset; 859 addr = GTT_BAR0_MAP_REG_USDM_RAM + 860 USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num); 861 862 REG_WR16(p_hwfn, addr, prod); 863 864 /* keep prod updates ordered */ 865 wmb(); 866 } 867 868 static int qed_fill_rdma_dev_info(struct qed_dev *cdev, 869 struct qed_dev_rdma_info *info) 870 { 871 struct qed_hwfn *p_hwfn = QED_AFFIN_HWFN(cdev); 872 873 memset(info, 0, sizeof(*info)); 874 875 info->rdma_type = QED_IS_ROCE_PERSONALITY(p_hwfn) ? 876 QED_RDMA_TYPE_ROCE : QED_RDMA_TYPE_IWARP; 877 878 info->user_dpm_enabled = (p_hwfn->db_bar_no_edpm == 0); 879 880 qed_fill_dev_info(cdev, &info->common); 881 882 return 0; 883 } 884 885 static int qed_rdma_get_sb_start(struct qed_dev *cdev) 886 { 887 int feat_num; 888 889 if (cdev->num_hwfns > 1) 890 feat_num = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_PF_L2_QUE); 891 else 892 feat_num = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_PF_L2_QUE) * 893 cdev->num_hwfns; 894 895 return feat_num; 896 } 897 898 static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev) 899 { 900 int n_cnq = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_RDMA_CNQ); 901 int n_msix = cdev->int_params.rdma_msix_cnt; 902 903 return min_t(int, n_cnq, n_msix); 904 } 905 906 static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt) 907 { 908 int limit = 0; 909 910 /* Mark the fastpath as free/used */ 911 cdev->int_params.fp_initialized = cnt ? true : false; 912 913 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) { 914 DP_ERR(cdev, 915 "qed roce supports only MSI-X interrupts (detected %d).\n", 916 cdev->int_params.out.int_mode); 917 return -EINVAL; 918 } else if (cdev->int_params.fp_msix_cnt) { 919 limit = cdev->int_params.rdma_msix_cnt; 920 } 921 922 if (!limit) 923 return -ENOMEM; 924 925 return min_t(int, cnt, limit); 926 } 927 928 static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info) 929 { 930 memset(info, 0, sizeof(*info)); 931 932 if (!cdev->int_params.fp_initialized) { 933 DP_INFO(cdev, 934 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 935 return -EINVAL; 936 } 937 938 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 939 int msix_base = cdev->int_params.rdma_msix_base; 940 941 info->msix_cnt = cdev->int_params.rdma_msix_cnt; 942 info->msix = &cdev->int_params.msix_table[msix_base]; 943 944 DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n", 945 info->msix_cnt, msix_base); 946 } 947 948 return 0; 949 } 950 951 static int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd) 952 { 953 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 954 u32 returned_id; 955 int rc; 956 957 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n"); 958 959 /* Allocates an unused protection domain */ 960 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 961 rc = qed_rdma_bmap_alloc_id(p_hwfn, 962 &p_hwfn->p_rdma_info->pd_map, &returned_id); 963 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 964 965 *pd = (u16)returned_id; 966 967 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc); 968 return rc; 969 } 970 971 static void qed_rdma_free_pd(void *rdma_cxt, u16 pd) 972 { 973 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 974 975 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd); 976 977 /* Returns a previously allocated protection domain for reuse */ 978 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 979 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd); 980 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 981 } 982 983 static int qed_rdma_alloc_xrcd(void *rdma_cxt, u16 *xrcd_id) 984 { 985 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 986 u32 returned_id; 987 int rc; 988 989 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc XRCD\n"); 990 991 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 992 rc = qed_rdma_bmap_alloc_id(p_hwfn, 993 &p_hwfn->p_rdma_info->xrcd_map, 994 &returned_id); 995 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 996 if (rc) { 997 DP_NOTICE(p_hwfn, "Failed in allocating xrcd id\n"); 998 return rc; 999 } 1000 1001 *xrcd_id = (u16)returned_id; 1002 1003 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc XRCD - done, rc = %d\n", rc); 1004 return rc; 1005 } 1006 1007 static void qed_rdma_free_xrcd(void *rdma_cxt, u16 xrcd_id) 1008 { 1009 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1010 1011 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "xrcd_id = %08x\n", xrcd_id); 1012 1013 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1014 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->xrcd_map, xrcd_id); 1015 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1016 } 1017 1018 static enum qed_rdma_toggle_bit 1019 qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid) 1020 { 1021 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 1022 enum qed_rdma_toggle_bit toggle_bit; 1023 u32 bmap_id; 1024 1025 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid); 1026 1027 /* the function toggle the bit that is related to a given icid 1028 * and returns the new toggle bit's value 1029 */ 1030 bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto); 1031 1032 spin_lock_bh(&p_info->lock); 1033 toggle_bit = !test_and_change_bit(bmap_id, 1034 p_info->toggle_bits.bitmap); 1035 spin_unlock_bh(&p_info->lock); 1036 1037 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n", 1038 toggle_bit); 1039 1040 return toggle_bit; 1041 } 1042 1043 static int qed_rdma_create_cq(void *rdma_cxt, 1044 struct qed_rdma_create_cq_in_params *params, 1045 u16 *icid) 1046 { 1047 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1048 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 1049 struct rdma_create_cq_ramrod_data *p_ramrod; 1050 enum qed_rdma_toggle_bit toggle_bit; 1051 struct qed_sp_init_data init_data; 1052 struct qed_spq_entry *p_ent; 1053 u32 returned_id, start_cid; 1054 int rc; 1055 1056 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n", 1057 params->cq_handle_hi, params->cq_handle_lo); 1058 1059 /* Allocate icid */ 1060 spin_lock_bh(&p_info->lock); 1061 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_info->cq_map, &returned_id); 1062 spin_unlock_bh(&p_info->lock); 1063 1064 if (rc) { 1065 DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc); 1066 return rc; 1067 } 1068 1069 start_cid = qed_cxt_get_proto_cid_start(p_hwfn, 1070 p_info->proto); 1071 *icid = returned_id + start_cid; 1072 1073 /* Check if icid requires a page allocation */ 1074 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid); 1075 if (rc) 1076 goto err; 1077 1078 /* Get SPQ entry */ 1079 memset(&init_data, 0, sizeof(init_data)); 1080 init_data.cid = *icid; 1081 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1082 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1083 1084 /* Send create CQ ramrod */ 1085 rc = qed_sp_init_request(p_hwfn, &p_ent, 1086 RDMA_RAMROD_CREATE_CQ, 1087 p_info->proto, &init_data); 1088 if (rc) 1089 goto err; 1090 1091 p_ramrod = &p_ent->ramrod.rdma_create_cq; 1092 1093 p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi); 1094 p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo); 1095 p_ramrod->dpi = cpu_to_le16(params->dpi); 1096 p_ramrod->is_two_level_pbl = params->pbl_two_level; 1097 p_ramrod->max_cqes = cpu_to_le32(params->cq_size); 1098 DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr); 1099 p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages); 1100 p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) + 1101 params->cnq_id; 1102 p_ramrod->int_timeout = cpu_to_le16(params->int_timeout); 1103 1104 /* toggle the bit for every resize or create cq for a given icid */ 1105 toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 1106 1107 p_ramrod->toggle_bit = toggle_bit; 1108 1109 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1110 if (rc) { 1111 /* restore toggle bit */ 1112 qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 1113 goto err; 1114 } 1115 1116 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc); 1117 return rc; 1118 1119 err: 1120 /* release allocated icid */ 1121 spin_lock_bh(&p_info->lock); 1122 qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id); 1123 spin_unlock_bh(&p_info->lock); 1124 DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc); 1125 1126 return rc; 1127 } 1128 1129 static int 1130 qed_rdma_destroy_cq(void *rdma_cxt, 1131 struct qed_rdma_destroy_cq_in_params *in_params, 1132 struct qed_rdma_destroy_cq_out_params *out_params) 1133 { 1134 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1135 struct rdma_destroy_cq_output_params *p_ramrod_res; 1136 struct rdma_destroy_cq_ramrod_data *p_ramrod; 1137 struct qed_sp_init_data init_data; 1138 struct qed_spq_entry *p_ent; 1139 dma_addr_t ramrod_res_phys; 1140 enum protocol_type proto; 1141 int rc = -ENOMEM; 1142 1143 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid); 1144 1145 p_ramrod_res = 1146 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1147 sizeof(struct rdma_destroy_cq_output_params), 1148 &ramrod_res_phys, GFP_KERNEL); 1149 if (!p_ramrod_res) { 1150 DP_NOTICE(p_hwfn, 1151 "qed destroy cq failed: cannot allocate memory (ramrod)\n"); 1152 return rc; 1153 } 1154 1155 /* Get SPQ entry */ 1156 memset(&init_data, 0, sizeof(init_data)); 1157 init_data.cid = in_params->icid; 1158 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1159 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1160 proto = p_hwfn->p_rdma_info->proto; 1161 /* Send destroy CQ ramrod */ 1162 rc = qed_sp_init_request(p_hwfn, &p_ent, 1163 RDMA_RAMROD_DESTROY_CQ, 1164 proto, &init_data); 1165 if (rc) 1166 goto err; 1167 1168 p_ramrod = &p_ent->ramrod.rdma_destroy_cq; 1169 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1170 1171 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1172 if (rc) 1173 goto err; 1174 1175 out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num); 1176 1177 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1178 sizeof(struct rdma_destroy_cq_output_params), 1179 p_ramrod_res, ramrod_res_phys); 1180 1181 /* Free icid */ 1182 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1183 1184 qed_bmap_release_id(p_hwfn, 1185 &p_hwfn->p_rdma_info->cq_map, 1186 (in_params->icid - 1187 qed_cxt_get_proto_cid_start(p_hwfn, proto))); 1188 1189 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1190 1191 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc); 1192 return rc; 1193 1194 err: dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1195 sizeof(struct rdma_destroy_cq_output_params), 1196 p_ramrod_res, ramrod_res_phys); 1197 1198 return rc; 1199 } 1200 1201 void qed_rdma_set_fw_mac(__le16 *p_fw_mac, const u8 *p_qed_mac) 1202 { 1203 p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]); 1204 p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]); 1205 p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]); 1206 } 1207 1208 static int qed_rdma_query_qp(void *rdma_cxt, 1209 struct qed_rdma_qp *qp, 1210 struct qed_rdma_query_qp_out_params *out_params) 1211 { 1212 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1213 int rc = 0; 1214 1215 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1216 1217 /* The following fields are filled in from qp and not FW as they can't 1218 * be modified by FW 1219 */ 1220 out_params->mtu = qp->mtu; 1221 out_params->dest_qp = qp->dest_qp; 1222 out_params->incoming_atomic_en = qp->incoming_atomic_en; 1223 out_params->e2e_flow_control_en = qp->e2e_flow_control_en; 1224 out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en; 1225 out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en; 1226 out_params->dgid = qp->dgid; 1227 out_params->flow_label = qp->flow_label; 1228 out_params->hop_limit_ttl = qp->hop_limit_ttl; 1229 out_params->traffic_class_tos = qp->traffic_class_tos; 1230 out_params->timeout = qp->ack_timeout; 1231 out_params->rnr_retry = qp->rnr_retry_cnt; 1232 out_params->retry_cnt = qp->retry_cnt; 1233 out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer; 1234 out_params->pkey_index = 0; 1235 out_params->max_rd_atomic = qp->max_rd_atomic_req; 1236 out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp; 1237 out_params->sqd_async = qp->sqd_async; 1238 1239 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 1240 qed_iwarp_query_qp(qp, out_params); 1241 else 1242 rc = qed_roce_query_qp(p_hwfn, qp, out_params); 1243 1244 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc); 1245 return rc; 1246 } 1247 1248 static int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp) 1249 { 1250 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1251 int rc = 0; 1252 1253 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1254 1255 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 1256 rc = qed_iwarp_destroy_qp(p_hwfn, qp); 1257 else 1258 rc = qed_roce_destroy_qp(p_hwfn, qp); 1259 1260 /* free qp params struct */ 1261 kfree(qp); 1262 1263 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n"); 1264 return rc; 1265 } 1266 1267 static struct qed_rdma_qp * 1268 qed_rdma_create_qp(void *rdma_cxt, 1269 struct qed_rdma_create_qp_in_params *in_params, 1270 struct qed_rdma_create_qp_out_params *out_params) 1271 { 1272 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1273 struct qed_rdma_qp *qp; 1274 u8 max_stats_queues; 1275 int rc; 1276 1277 if (!rdma_cxt || !in_params || !out_params || 1278 !p_hwfn->p_rdma_info->active) { 1279 pr_err("qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n", 1280 rdma_cxt, in_params, out_params); 1281 return NULL; 1282 } 1283 1284 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1285 "qed rdma create qp called with qp_handle = %08x%08x\n", 1286 in_params->qp_handle_hi, in_params->qp_handle_lo); 1287 1288 /* Some sanity checks... */ 1289 max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues; 1290 if (in_params->stats_queue >= max_stats_queues) { 1291 DP_ERR(p_hwfn->cdev, 1292 "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n", 1293 in_params->stats_queue, max_stats_queues); 1294 return NULL; 1295 } 1296 1297 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 1298 if (in_params->sq_num_pages * sizeof(struct regpair) > 1299 IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE) { 1300 DP_NOTICE(p_hwfn->cdev, 1301 "Sq num pages: %d exceeds maximum\n", 1302 in_params->sq_num_pages); 1303 return NULL; 1304 } 1305 if (in_params->rq_num_pages * sizeof(struct regpair) > 1306 IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE) { 1307 DP_NOTICE(p_hwfn->cdev, 1308 "Rq num pages: %d exceeds maximum\n", 1309 in_params->rq_num_pages); 1310 return NULL; 1311 } 1312 } 1313 1314 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1315 if (!qp) 1316 return NULL; 1317 1318 qp->cur_state = QED_ROCE_QP_STATE_RESET; 1319 qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi); 1320 qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo); 1321 qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi); 1322 qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo); 1323 qp->use_srq = in_params->use_srq; 1324 qp->signal_all = in_params->signal_all; 1325 qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey; 1326 qp->pd = in_params->pd; 1327 qp->dpi = in_params->dpi; 1328 qp->sq_cq_id = in_params->sq_cq_id; 1329 qp->sq_num_pages = in_params->sq_num_pages; 1330 qp->sq_pbl_ptr = in_params->sq_pbl_ptr; 1331 qp->rq_cq_id = in_params->rq_cq_id; 1332 qp->rq_num_pages = in_params->rq_num_pages; 1333 qp->rq_pbl_ptr = in_params->rq_pbl_ptr; 1334 qp->srq_id = in_params->srq_id; 1335 qp->req_offloaded = false; 1336 qp->resp_offloaded = false; 1337 qp->e2e_flow_control_en = qp->use_srq ? false : true; 1338 qp->stats_queue = in_params->stats_queue; 1339 qp->qp_type = in_params->qp_type; 1340 qp->xrcd_id = in_params->xrcd_id; 1341 1342 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 1343 rc = qed_iwarp_create_qp(p_hwfn, qp, out_params); 1344 qp->qpid = qp->icid; 1345 } else { 1346 qp->edpm_mode = GET_FIELD(in_params->flags, QED_ROCE_EDPM_MODE); 1347 rc = qed_roce_alloc_cid(p_hwfn, &qp->icid); 1348 qp->qpid = ((0xFF << 16) | qp->icid); 1349 } 1350 1351 if (rc) { 1352 kfree(qp); 1353 return NULL; 1354 } 1355 1356 out_params->icid = qp->icid; 1357 out_params->qp_id = qp->qpid; 1358 1359 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc); 1360 return qp; 1361 } 1362 1363 static int qed_rdma_modify_qp(void *rdma_cxt, 1364 struct qed_rdma_qp *qp, 1365 struct qed_rdma_modify_qp_in_params *params) 1366 { 1367 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1368 enum qed_roce_qp_state prev_state; 1369 int rc = 0; 1370 1371 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n", 1372 qp->icid, params->new_state); 1373 1374 if (rc) { 1375 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1376 return rc; 1377 } 1378 1379 if (GET_FIELD(params->modify_flags, 1380 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) { 1381 qp->incoming_rdma_read_en = params->incoming_rdma_read_en; 1382 qp->incoming_rdma_write_en = params->incoming_rdma_write_en; 1383 qp->incoming_atomic_en = params->incoming_atomic_en; 1384 } 1385 1386 /* Update QP structure with the updated values */ 1387 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE)) 1388 qp->roce_mode = params->roce_mode; 1389 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)) 1390 qp->pkey = params->pkey; 1391 if (GET_FIELD(params->modify_flags, 1392 QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN)) 1393 qp->e2e_flow_control_en = params->e2e_flow_control_en; 1394 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP)) 1395 qp->dest_qp = params->dest_qp; 1396 if (GET_FIELD(params->modify_flags, 1397 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) { 1398 /* Indicates that the following parameters have changed: 1399 * Traffic class, flow label, hop limit, source GID, 1400 * destination GID, loopback indicator 1401 */ 1402 qp->traffic_class_tos = params->traffic_class_tos; 1403 qp->flow_label = params->flow_label; 1404 qp->hop_limit_ttl = params->hop_limit_ttl; 1405 1406 qp->sgid = params->sgid; 1407 qp->dgid = params->dgid; 1408 qp->udp_src_port = 0; 1409 qp->vlan_id = params->vlan_id; 1410 qp->mtu = params->mtu; 1411 qp->lb_indication = params->lb_indication; 1412 memcpy((u8 *)&qp->remote_mac_addr[0], 1413 (u8 *)¶ms->remote_mac_addr[0], ETH_ALEN); 1414 if (params->use_local_mac) { 1415 memcpy((u8 *)&qp->local_mac_addr[0], 1416 (u8 *)¶ms->local_mac_addr[0], ETH_ALEN); 1417 } else { 1418 memcpy((u8 *)&qp->local_mac_addr[0], 1419 (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN); 1420 } 1421 } 1422 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN)) 1423 qp->rq_psn = params->rq_psn; 1424 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN)) 1425 qp->sq_psn = params->sq_psn; 1426 if (GET_FIELD(params->modify_flags, 1427 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)) 1428 qp->max_rd_atomic_req = params->max_rd_atomic_req; 1429 if (GET_FIELD(params->modify_flags, 1430 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)) 1431 qp->max_rd_atomic_resp = params->max_rd_atomic_resp; 1432 if (GET_FIELD(params->modify_flags, 1433 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)) 1434 qp->ack_timeout = params->ack_timeout; 1435 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)) 1436 qp->retry_cnt = params->retry_cnt; 1437 if (GET_FIELD(params->modify_flags, 1438 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)) 1439 qp->rnr_retry_cnt = params->rnr_retry_cnt; 1440 if (GET_FIELD(params->modify_flags, 1441 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)) 1442 qp->min_rnr_nak_timer = params->min_rnr_nak_timer; 1443 1444 qp->sqd_async = params->sqd_async; 1445 1446 prev_state = qp->cur_state; 1447 if (GET_FIELD(params->modify_flags, 1448 QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) { 1449 qp->cur_state = params->new_state; 1450 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n", 1451 qp->cur_state); 1452 } 1453 1454 switch (qp->qp_type) { 1455 case QED_RDMA_QP_TYPE_XRC_INI: 1456 qp->has_req = true; 1457 break; 1458 case QED_RDMA_QP_TYPE_XRC_TGT: 1459 qp->has_resp = true; 1460 break; 1461 default: 1462 qp->has_req = true; 1463 qp->has_resp = true; 1464 } 1465 1466 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 1467 enum qed_iwarp_qp_state new_state = 1468 qed_roce2iwarp_state(qp->cur_state); 1469 1470 rc = qed_iwarp_modify_qp(p_hwfn, qp, new_state, 0); 1471 } else { 1472 rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params); 1473 } 1474 1475 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc); 1476 return rc; 1477 } 1478 1479 static int 1480 qed_rdma_register_tid(void *rdma_cxt, 1481 struct qed_rdma_register_tid_in_params *params) 1482 { 1483 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1484 struct rdma_register_tid_ramrod_data *p_ramrod; 1485 struct qed_sp_init_data init_data; 1486 struct qed_spq_entry *p_ent; 1487 enum rdma_tid_type tid_type; 1488 u8 fw_return_code; 1489 u16 flags = 0; 1490 int rc; 1491 1492 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", params->itid); 1493 1494 /* Get SPQ entry */ 1495 memset(&init_data, 0, sizeof(init_data)); 1496 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1497 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1498 1499 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_REGISTER_MR, 1500 p_hwfn->p_rdma_info->proto, &init_data); 1501 if (rc) { 1502 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1503 return rc; 1504 } 1505 1506 if (p_hwfn->p_rdma_info->last_tid < params->itid) 1507 p_hwfn->p_rdma_info->last_tid = params->itid; 1508 1509 SET_FIELD(flags, RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL, 1510 params->pbl_two_level); 1511 1512 SET_FIELD(flags, RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED, 1513 false); 1514 1515 SET_FIELD(flags, RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR, params->phy_mr); 1516 1517 /* Don't initialize D/C field, as it may override other bits. */ 1518 if (!(params->tid_type == QED_RDMA_TID_FMR) && !(params->dma_mr)) 1519 SET_FIELD(flags, RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG, 1520 params->page_size_log - 12); 1521 1522 SET_FIELD(flags, RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ, 1523 params->remote_read); 1524 1525 SET_FIELD(flags, RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE, 1526 params->remote_write); 1527 1528 SET_FIELD(flags, RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC, 1529 params->remote_atomic); 1530 1531 SET_FIELD(flags, RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE, 1532 params->local_write); 1533 1534 SET_FIELD(flags, RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ, 1535 params->local_read); 1536 1537 SET_FIELD(flags, RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND, 1538 params->mw_bind); 1539 1540 p_ramrod = &p_ent->ramrod.rdma_register_tid; 1541 p_ramrod->flags = cpu_to_le16(flags); 1542 1543 SET_FIELD(p_ramrod->flags1, 1544 RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG, 1545 params->pbl_page_size_log - 12); 1546 1547 SET_FIELD(p_ramrod->flags2, RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR, 1548 params->dma_mr); 1549 1550 switch (params->tid_type) { 1551 case QED_RDMA_TID_REGISTERED_MR: 1552 tid_type = RDMA_TID_REGISTERED_MR; 1553 break; 1554 case QED_RDMA_TID_FMR: 1555 tid_type = RDMA_TID_FMR; 1556 break; 1557 case QED_RDMA_TID_MW: 1558 tid_type = RDMA_TID_MW; 1559 break; 1560 default: 1561 rc = -EINVAL; 1562 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1563 qed_sp_destroy_request(p_hwfn, p_ent); 1564 return rc; 1565 } 1566 1567 SET_FIELD(p_ramrod->flags1, RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE, 1568 tid_type); 1569 1570 p_ramrod->itid = cpu_to_le32(params->itid); 1571 p_ramrod->key = params->key; 1572 p_ramrod->pd = cpu_to_le16(params->pd); 1573 p_ramrod->length_hi = (u8)(params->length >> 32); 1574 p_ramrod->length_lo = DMA_LO_LE(params->length); 1575 DMA_REGPAIR_LE(p_ramrod->va, params->vaddr); 1576 DMA_REGPAIR_LE(p_ramrod->pbl_base, params->pbl_ptr); 1577 1578 /* DIF */ 1579 if (params->dif_enabled) { 1580 SET_FIELD(p_ramrod->flags2, 1581 RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG, 1); 1582 DMA_REGPAIR_LE(p_ramrod->dif_error_addr, 1583 params->dif_error_addr); 1584 } 1585 1586 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 1587 if (rc) 1588 return rc; 1589 1590 if (fw_return_code != RDMA_RETURN_OK) { 1591 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 1592 return -EINVAL; 1593 } 1594 1595 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Register TID, rc = %d\n", rc); 1596 return rc; 1597 } 1598 1599 static int qed_rdma_deregister_tid(void *rdma_cxt, u32 itid) 1600 { 1601 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1602 struct rdma_deregister_tid_ramrod_data *p_ramrod; 1603 struct qed_sp_init_data init_data; 1604 struct qed_spq_entry *p_ent; 1605 struct qed_ptt *p_ptt; 1606 u8 fw_return_code; 1607 int rc; 1608 1609 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 1610 1611 /* Get SPQ entry */ 1612 memset(&init_data, 0, sizeof(init_data)); 1613 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1614 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1615 1616 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_DEREGISTER_MR, 1617 p_hwfn->p_rdma_info->proto, &init_data); 1618 if (rc) { 1619 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1620 return rc; 1621 } 1622 1623 p_ramrod = &p_ent->ramrod.rdma_deregister_tid; 1624 p_ramrod->itid = cpu_to_le32(itid); 1625 1626 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 1627 if (rc) { 1628 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1629 return rc; 1630 } 1631 1632 if (fw_return_code == RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR) { 1633 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 1634 return -EINVAL; 1635 } else if (fw_return_code == RDMA_RETURN_NIG_DRAIN_REQ) { 1636 /* Bit indicating that the TID is in use and a nig drain is 1637 * required before sending the ramrod again 1638 */ 1639 p_ptt = qed_ptt_acquire(p_hwfn); 1640 if (!p_ptt) { 1641 rc = -EBUSY; 1642 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1643 "Failed to acquire PTT\n"); 1644 return rc; 1645 } 1646 1647 rc = qed_mcp_drain(p_hwfn, p_ptt); 1648 if (rc) { 1649 qed_ptt_release(p_hwfn, p_ptt); 1650 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1651 "Drain failed\n"); 1652 return rc; 1653 } 1654 1655 qed_ptt_release(p_hwfn, p_ptt); 1656 1657 /* Resend the ramrod */ 1658 rc = qed_sp_init_request(p_hwfn, &p_ent, 1659 RDMA_RAMROD_DEREGISTER_MR, 1660 p_hwfn->p_rdma_info->proto, 1661 &init_data); 1662 if (rc) { 1663 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1664 "Failed to init sp-element\n"); 1665 return rc; 1666 } 1667 1668 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 1669 if (rc) { 1670 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1671 "Ramrod failed\n"); 1672 return rc; 1673 } 1674 1675 if (fw_return_code != RDMA_RETURN_OK) { 1676 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", 1677 fw_return_code); 1678 return rc; 1679 } 1680 } 1681 1682 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "De-registered TID, rc = %d\n", rc); 1683 return rc; 1684 } 1685 1686 static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev) 1687 { 1688 return QED_AFFIN_HWFN(cdev); 1689 } 1690 1691 static struct qed_bmap *qed_rdma_get_srq_bmap(struct qed_hwfn *p_hwfn, 1692 bool is_xrc) 1693 { 1694 if (is_xrc) 1695 return &p_hwfn->p_rdma_info->xrc_srq_map; 1696 1697 return &p_hwfn->p_rdma_info->srq_map; 1698 } 1699 1700 static int qed_rdma_modify_srq(void *rdma_cxt, 1701 struct qed_rdma_modify_srq_in_params *in_params) 1702 { 1703 struct rdma_srq_modify_ramrod_data *p_ramrod; 1704 struct qed_sp_init_data init_data = {}; 1705 struct qed_hwfn *p_hwfn = rdma_cxt; 1706 struct qed_spq_entry *p_ent; 1707 u16 opaque_fid; 1708 int rc; 1709 1710 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1711 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1712 1713 rc = qed_sp_init_request(p_hwfn, &p_ent, 1714 RDMA_RAMROD_MODIFY_SRQ, 1715 p_hwfn->p_rdma_info->proto, &init_data); 1716 if (rc) 1717 return rc; 1718 1719 p_ramrod = &p_ent->ramrod.rdma_modify_srq; 1720 p_ramrod->srq_id.srq_idx = cpu_to_le16(in_params->srq_id); 1721 opaque_fid = p_hwfn->hw_info.opaque_fid; 1722 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid); 1723 p_ramrod->wqe_limit = cpu_to_le32(in_params->wqe_limit); 1724 1725 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1726 if (rc) 1727 return rc; 1728 1729 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "modified SRQ id = %x, is_xrc=%u\n", 1730 in_params->srq_id, in_params->is_xrc); 1731 1732 return rc; 1733 } 1734 1735 static int 1736 qed_rdma_destroy_srq(void *rdma_cxt, 1737 struct qed_rdma_destroy_srq_in_params *in_params) 1738 { 1739 struct rdma_srq_destroy_ramrod_data *p_ramrod; 1740 struct qed_sp_init_data init_data = {}; 1741 struct qed_hwfn *p_hwfn = rdma_cxt; 1742 struct qed_spq_entry *p_ent; 1743 struct qed_bmap *bmap; 1744 u16 opaque_fid; 1745 u16 offset; 1746 int rc; 1747 1748 opaque_fid = p_hwfn->hw_info.opaque_fid; 1749 1750 init_data.opaque_fid = opaque_fid; 1751 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1752 1753 rc = qed_sp_init_request(p_hwfn, &p_ent, 1754 RDMA_RAMROD_DESTROY_SRQ, 1755 p_hwfn->p_rdma_info->proto, &init_data); 1756 if (rc) 1757 return rc; 1758 1759 p_ramrod = &p_ent->ramrod.rdma_destroy_srq; 1760 p_ramrod->srq_id.srq_idx = cpu_to_le16(in_params->srq_id); 1761 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid); 1762 1763 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1764 if (rc) 1765 return rc; 1766 1767 bmap = qed_rdma_get_srq_bmap(p_hwfn, in_params->is_xrc); 1768 offset = (in_params->is_xrc) ? 0 : p_hwfn->p_rdma_info->srq_id_offset; 1769 1770 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1771 qed_bmap_release_id(p_hwfn, bmap, in_params->srq_id - offset); 1772 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1773 1774 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1775 "XRC/SRQ destroyed Id = %x, is_xrc=%u\n", 1776 in_params->srq_id, in_params->is_xrc); 1777 1778 return rc; 1779 } 1780 1781 static int 1782 qed_rdma_create_srq(void *rdma_cxt, 1783 struct qed_rdma_create_srq_in_params *in_params, 1784 struct qed_rdma_create_srq_out_params *out_params) 1785 { 1786 struct rdma_srq_create_ramrod_data *p_ramrod; 1787 struct qed_sp_init_data init_data = {}; 1788 struct qed_hwfn *p_hwfn = rdma_cxt; 1789 enum qed_cxt_elem_type elem_type; 1790 struct qed_spq_entry *p_ent; 1791 u16 opaque_fid, srq_id; 1792 struct qed_bmap *bmap; 1793 u32 returned_id; 1794 u16 offset; 1795 int rc; 1796 1797 bmap = qed_rdma_get_srq_bmap(p_hwfn, in_params->is_xrc); 1798 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1799 rc = qed_rdma_bmap_alloc_id(p_hwfn, bmap, &returned_id); 1800 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1801 1802 if (rc) { 1803 DP_NOTICE(p_hwfn, 1804 "failed to allocate xrc/srq id (is_xrc=%u)\n", 1805 in_params->is_xrc); 1806 return rc; 1807 } 1808 1809 elem_type = (in_params->is_xrc) ? (QED_ELEM_XRC_SRQ) : (QED_ELEM_SRQ); 1810 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, elem_type, returned_id); 1811 if (rc) 1812 goto err; 1813 1814 opaque_fid = p_hwfn->hw_info.opaque_fid; 1815 1816 opaque_fid = p_hwfn->hw_info.opaque_fid; 1817 init_data.opaque_fid = opaque_fid; 1818 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1819 1820 rc = qed_sp_init_request(p_hwfn, &p_ent, 1821 RDMA_RAMROD_CREATE_SRQ, 1822 p_hwfn->p_rdma_info->proto, &init_data); 1823 if (rc) 1824 goto err; 1825 1826 p_ramrod = &p_ent->ramrod.rdma_create_srq; 1827 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, in_params->pbl_base_addr); 1828 p_ramrod->pages_in_srq_pbl = cpu_to_le16(in_params->num_pages); 1829 p_ramrod->pd_id = cpu_to_le16(in_params->pd_id); 1830 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid); 1831 p_ramrod->page_size = cpu_to_le16(in_params->page_size); 1832 DMA_REGPAIR_LE(p_ramrod->producers_addr, in_params->prod_pair_addr); 1833 offset = (in_params->is_xrc) ? 0 : p_hwfn->p_rdma_info->srq_id_offset; 1834 srq_id = (u16)returned_id + offset; 1835 p_ramrod->srq_id.srq_idx = cpu_to_le16(srq_id); 1836 1837 if (in_params->is_xrc) { 1838 SET_FIELD(p_ramrod->flags, 1839 RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG, 1); 1840 SET_FIELD(p_ramrod->flags, 1841 RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN, 1842 in_params->reserved_key_en); 1843 p_ramrod->xrc_srq_cq_cid = 1844 cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 1845 in_params->cq_cid); 1846 p_ramrod->xrc_domain = cpu_to_le16(in_params->xrcd_id); 1847 } 1848 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1849 if (rc) 1850 goto err; 1851 1852 out_params->srq_id = srq_id; 1853 1854 DP_VERBOSE(p_hwfn, 1855 QED_MSG_RDMA, 1856 "XRC/SRQ created Id = %x (is_xrc=%u)\n", 1857 out_params->srq_id, in_params->is_xrc); 1858 return rc; 1859 1860 err: 1861 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1862 qed_bmap_release_id(p_hwfn, bmap, returned_id); 1863 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1864 1865 return rc; 1866 } 1867 1868 bool qed_rdma_allocated_qps(struct qed_hwfn *p_hwfn) 1869 { 1870 bool result; 1871 1872 /* if rdma wasn't activated yet, naturally there are no qps */ 1873 if (!p_hwfn->p_rdma_info->active) 1874 return false; 1875 1876 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1877 if (!p_hwfn->p_rdma_info->cid_map.bitmap) 1878 result = false; 1879 else 1880 result = !qed_bmap_is_empty(&p_hwfn->p_rdma_info->cid_map); 1881 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1882 return result; 1883 } 1884 1885 void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1886 { 1887 u32 val; 1888 1889 val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1; 1890 1891 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val); 1892 DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA), 1893 "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n", 1894 val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm); 1895 } 1896 1897 1898 void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1899 { 1900 p_hwfn->db_bar_no_edpm = true; 1901 1902 qed_rdma_dpm_conf(p_hwfn, p_ptt); 1903 } 1904 1905 static int qed_rdma_start(void *rdma_cxt, 1906 struct qed_rdma_start_in_params *params) 1907 { 1908 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1909 struct qed_ptt *p_ptt; 1910 int rc = -EBUSY; 1911 1912 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1913 "desired_cnq = %08x\n", params->desired_cnq); 1914 1915 p_ptt = qed_ptt_acquire(p_hwfn); 1916 if (!p_ptt) 1917 goto err; 1918 1919 rc = qed_rdma_alloc(p_hwfn); 1920 if (rc) 1921 goto err1; 1922 1923 rc = qed_rdma_setup(p_hwfn, p_ptt, params); 1924 if (rc) 1925 goto err2; 1926 1927 qed_ptt_release(p_hwfn, p_ptt); 1928 p_hwfn->p_rdma_info->active = 1; 1929 1930 return rc; 1931 1932 err2: 1933 qed_rdma_free(p_hwfn); 1934 err1: 1935 qed_ptt_release(p_hwfn, p_ptt); 1936 err: 1937 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc); 1938 return rc; 1939 } 1940 1941 static int qed_rdma_init(struct qed_dev *cdev, 1942 struct qed_rdma_start_in_params *params) 1943 { 1944 return qed_rdma_start(QED_AFFIN_HWFN(cdev), params); 1945 } 1946 1947 static void qed_rdma_remove_user(void *rdma_cxt, u16 dpi) 1948 { 1949 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1950 1951 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi); 1952 1953 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1954 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi); 1955 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1956 } 1957 1958 static int qed_roce_ll2_set_mac_filter(struct qed_dev *cdev, 1959 u8 *old_mac_address, 1960 u8 *new_mac_address) 1961 { 1962 int rc = 0; 1963 1964 if (old_mac_address) 1965 qed_llh_remove_mac_filter(cdev, 0, old_mac_address); 1966 if (new_mac_address) 1967 rc = qed_llh_add_mac_filter(cdev, 0, new_mac_address); 1968 1969 if (rc) 1970 DP_ERR(cdev, 1971 "qed roce ll2 mac filter set: failed to add MAC filter\n"); 1972 1973 return rc; 1974 } 1975 1976 static int qed_iwarp_set_engine_affin(struct qed_dev *cdev, bool b_reset) 1977 { 1978 enum qed_eng eng; 1979 u8 ppfid = 0; 1980 int rc; 1981 1982 /* Make sure iwarp cmt mode is enabled before setting affinity */ 1983 if (!cdev->iwarp_cmt) 1984 return -EINVAL; 1985 1986 if (b_reset) 1987 eng = QED_BOTH_ENG; 1988 else 1989 eng = cdev->l2_affin_hint ? QED_ENG1 : QED_ENG0; 1990 1991 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng); 1992 if (rc) { 1993 DP_NOTICE(cdev, 1994 "Failed to set the engine affinity of ppfid %d\n", 1995 ppfid); 1996 return rc; 1997 } 1998 1999 DP_VERBOSE(cdev, (QED_MSG_RDMA | QED_MSG_SP), 2000 "LLH: Set the engine affinity of non-RoCE packets as %d\n", 2001 eng); 2002 2003 return 0; 2004 } 2005 2006 static const struct qed_rdma_ops qed_rdma_ops_pass = { 2007 .common = &qed_common_ops_pass, 2008 .fill_dev_info = &qed_fill_rdma_dev_info, 2009 .rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx, 2010 .rdma_init = &qed_rdma_init, 2011 .rdma_add_user = &qed_rdma_add_user, 2012 .rdma_remove_user = &qed_rdma_remove_user, 2013 .rdma_stop = &qed_rdma_stop, 2014 .rdma_query_port = &qed_rdma_query_port, 2015 .rdma_query_device = &qed_rdma_query_device, 2016 .rdma_get_start_sb = &qed_rdma_get_sb_start, 2017 .rdma_get_rdma_int = &qed_rdma_get_int, 2018 .rdma_set_rdma_int = &qed_rdma_set_int, 2019 .rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix, 2020 .rdma_cnq_prod_update = &qed_rdma_cnq_prod_update, 2021 .rdma_alloc_pd = &qed_rdma_alloc_pd, 2022 .rdma_dealloc_pd = &qed_rdma_free_pd, 2023 .rdma_alloc_xrcd = &qed_rdma_alloc_xrcd, 2024 .rdma_dealloc_xrcd = &qed_rdma_free_xrcd, 2025 .rdma_create_cq = &qed_rdma_create_cq, 2026 .rdma_destroy_cq = &qed_rdma_destroy_cq, 2027 .rdma_create_qp = &qed_rdma_create_qp, 2028 .rdma_modify_qp = &qed_rdma_modify_qp, 2029 .rdma_query_qp = &qed_rdma_query_qp, 2030 .rdma_destroy_qp = &qed_rdma_destroy_qp, 2031 .rdma_alloc_tid = &qed_rdma_alloc_tid, 2032 .rdma_free_tid = &qed_rdma_free_tid, 2033 .rdma_register_tid = &qed_rdma_register_tid, 2034 .rdma_deregister_tid = &qed_rdma_deregister_tid, 2035 .rdma_create_srq = &qed_rdma_create_srq, 2036 .rdma_modify_srq = &qed_rdma_modify_srq, 2037 .rdma_destroy_srq = &qed_rdma_destroy_srq, 2038 .ll2_acquire_connection = &qed_ll2_acquire_connection, 2039 .ll2_establish_connection = &qed_ll2_establish_connection, 2040 .ll2_terminate_connection = &qed_ll2_terminate_connection, 2041 .ll2_release_connection = &qed_ll2_release_connection, 2042 .ll2_post_rx_buffer = &qed_ll2_post_rx_buffer, 2043 .ll2_prepare_tx_packet = &qed_ll2_prepare_tx_packet, 2044 .ll2_set_fragment_of_tx_packet = &qed_ll2_set_fragment_of_tx_packet, 2045 .ll2_set_mac_filter = &qed_roce_ll2_set_mac_filter, 2046 .ll2_get_stats = &qed_ll2_get_stats, 2047 .iwarp_set_engine_affin = &qed_iwarp_set_engine_affin, 2048 .iwarp_connect = &qed_iwarp_connect, 2049 .iwarp_create_listen = &qed_iwarp_create_listen, 2050 .iwarp_destroy_listen = &qed_iwarp_destroy_listen, 2051 .iwarp_accept = &qed_iwarp_accept, 2052 .iwarp_reject = &qed_iwarp_reject, 2053 .iwarp_send_rtr = &qed_iwarp_send_rtr, 2054 }; 2055 2056 const struct qed_rdma_ops *qed_get_rdma_ops(void) 2057 { 2058 return &qed_rdma_ops_pass; 2059 } 2060 EXPORT_SYMBOL(qed_get_rdma_ops); 2061