11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2c78c70faSSudarsana Reddy Kalluru /* QLogic qed NIC Driver
3c78c70faSSudarsana Reddy Kalluru * Copyright (c) 2015-2017 QLogic Corporation
4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd.
5c78c70faSSudarsana Reddy Kalluru */
61f4d4ed6SAlexander Lobakin
7c78c70faSSudarsana Reddy Kalluru #include <linux/types.h>
8c78c70faSSudarsana Reddy Kalluru #include "qed.h"
9c78c70faSSudarsana Reddy Kalluru #include "qed_dev_api.h"
10c78c70faSSudarsana Reddy Kalluru #include "qed_hw.h"
11c78c70faSSudarsana Reddy Kalluru #include "qed_l2.h"
12db82f70eSsudarsana.kalluru@cavium.com #include "qed_mcp.h"
13c6b7314dSAlexander Lobakin #include "qed_ptp.h"
14c78c70faSSudarsana Reddy Kalluru #include "qed_reg_addr.h"
15c78c70faSSudarsana Reddy Kalluru
16c78c70faSSudarsana Reddy Kalluru /* 16 nano second time quantas to wait before making a Drift adjustment */
17c78c70faSSudarsana Reddy Kalluru #define QED_DRIFT_CNTR_TIME_QUANTA_SHIFT 0
18c78c70faSSudarsana Reddy Kalluru /* Nano seconds to add/subtract when making a Drift adjustment */
19c78c70faSSudarsana Reddy Kalluru #define QED_DRIFT_CNTR_ADJUSTMENT_SHIFT 28
20c78c70faSSudarsana Reddy Kalluru /* Add/subtract the Adjustment_Value when making a Drift adjustment */
21c78c70faSSudarsana Reddy Kalluru #define QED_DRIFT_CNTR_DIRECTION_SHIFT 31
22c78c70faSSudarsana Reddy Kalluru #define QED_TIMESTAMP_MASK BIT(16)
230202d293SSudarsana Reddy Kalluru /* Param mask for Hardware to detect/timestamp the L2/L4 unicast PTP packets */
240202d293SSudarsana Reddy Kalluru #define QED_PTP_UCAST_PARAM_MASK 0x70F
25c78c70faSSudarsana Reddy Kalluru
qed_ptcdev_to_resc(struct qed_hwfn * p_hwfn)26db82f70eSsudarsana.kalluru@cavium.com static enum qed_resc_lock qed_ptcdev_to_resc(struct qed_hwfn *p_hwfn)
27db82f70eSsudarsana.kalluru@cavium.com {
280ebcebbeSSudarsana Reddy Kalluru switch (MFW_PORT(p_hwfn)) {
29db82f70eSsudarsana.kalluru@cavium.com case 0:
30db82f70eSsudarsana.kalluru@cavium.com return QED_RESC_LOCK_PTP_PORT0;
31db82f70eSsudarsana.kalluru@cavium.com case 1:
32db82f70eSsudarsana.kalluru@cavium.com return QED_RESC_LOCK_PTP_PORT1;
33db82f70eSsudarsana.kalluru@cavium.com case 2:
34db82f70eSsudarsana.kalluru@cavium.com return QED_RESC_LOCK_PTP_PORT2;
35db82f70eSsudarsana.kalluru@cavium.com case 3:
36db82f70eSsudarsana.kalluru@cavium.com return QED_RESC_LOCK_PTP_PORT3;
37db82f70eSsudarsana.kalluru@cavium.com default:
38db82f70eSsudarsana.kalluru@cavium.com return QED_RESC_LOCK_RESC_INVALID;
39db82f70eSsudarsana.kalluru@cavium.com }
40db82f70eSsudarsana.kalluru@cavium.com }
41db82f70eSsudarsana.kalluru@cavium.com
qed_ptp_res_lock(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)42db82f70eSsudarsana.kalluru@cavium.com static int qed_ptp_res_lock(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
43db82f70eSsudarsana.kalluru@cavium.com {
44db82f70eSsudarsana.kalluru@cavium.com struct qed_resc_lock_params params;
45db82f70eSsudarsana.kalluru@cavium.com enum qed_resc_lock resource;
46db82f70eSsudarsana.kalluru@cavium.com int rc;
47db82f70eSsudarsana.kalluru@cavium.com
48db82f70eSsudarsana.kalluru@cavium.com resource = qed_ptcdev_to_resc(p_hwfn);
49db82f70eSsudarsana.kalluru@cavium.com if (resource == QED_RESC_LOCK_RESC_INVALID)
50db82f70eSsudarsana.kalluru@cavium.com return -EINVAL;
51db82f70eSsudarsana.kalluru@cavium.com
52db82f70eSsudarsana.kalluru@cavium.com qed_mcp_resc_lock_default_init(¶ms, NULL, resource, true);
53db82f70eSsudarsana.kalluru@cavium.com
54db82f70eSsudarsana.kalluru@cavium.com rc = qed_mcp_resc_lock(p_hwfn, p_ptt, ¶ms);
55db82f70eSsudarsana.kalluru@cavium.com if (rc && rc != -EINVAL) {
56db82f70eSsudarsana.kalluru@cavium.com return rc;
57db82f70eSsudarsana.kalluru@cavium.com } else if (rc == -EINVAL) {
58db82f70eSsudarsana.kalluru@cavium.com /* MFW doesn't support resource locking, first PF on the port
59db82f70eSsudarsana.kalluru@cavium.com * has lock ownership.
60db82f70eSsudarsana.kalluru@cavium.com */
6178cea9ffSTomer Tayar if (p_hwfn->abs_pf_id < p_hwfn->cdev->num_ports_in_engine)
62db82f70eSsudarsana.kalluru@cavium.com return 0;
63db82f70eSsudarsana.kalluru@cavium.com
64db82f70eSsudarsana.kalluru@cavium.com DP_INFO(p_hwfn, "PF doesn't have lock ownership\n");
65db82f70eSsudarsana.kalluru@cavium.com return -EBUSY;
66*165f8e82SJean Sacren } else if (!params.b_granted) {
67db82f70eSsudarsana.kalluru@cavium.com DP_INFO(p_hwfn, "Failed to acquire ptp resource lock\n");
68db82f70eSsudarsana.kalluru@cavium.com return -EBUSY;
69db82f70eSsudarsana.kalluru@cavium.com }
70db82f70eSsudarsana.kalluru@cavium.com
71*165f8e82SJean Sacren return 0;
72db82f70eSsudarsana.kalluru@cavium.com }
73db82f70eSsudarsana.kalluru@cavium.com
qed_ptp_res_unlock(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)74db82f70eSsudarsana.kalluru@cavium.com static int qed_ptp_res_unlock(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
75db82f70eSsudarsana.kalluru@cavium.com {
76db82f70eSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params params;
77db82f70eSsudarsana.kalluru@cavium.com enum qed_resc_lock resource;
78db82f70eSsudarsana.kalluru@cavium.com int rc;
79db82f70eSsudarsana.kalluru@cavium.com
80db82f70eSsudarsana.kalluru@cavium.com resource = qed_ptcdev_to_resc(p_hwfn);
81db82f70eSsudarsana.kalluru@cavium.com if (resource == QED_RESC_LOCK_RESC_INVALID)
82db82f70eSsudarsana.kalluru@cavium.com return -EINVAL;
83db82f70eSsudarsana.kalluru@cavium.com
84db82f70eSsudarsana.kalluru@cavium.com qed_mcp_resc_lock_default_init(NULL, ¶ms, resource, true);
85db82f70eSsudarsana.kalluru@cavium.com
86db82f70eSsudarsana.kalluru@cavium.com rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, ¶ms);
87db82f70eSsudarsana.kalluru@cavium.com if (rc == -EINVAL) {
88db82f70eSsudarsana.kalluru@cavium.com /* MFW doesn't support locking, first PF has lock ownership */
8978cea9ffSTomer Tayar if (p_hwfn->abs_pf_id < p_hwfn->cdev->num_ports_in_engine) {
90db82f70eSsudarsana.kalluru@cavium.com rc = 0;
91db82f70eSsudarsana.kalluru@cavium.com } else {
92db82f70eSsudarsana.kalluru@cavium.com DP_INFO(p_hwfn, "PF doesn't have lock ownership\n");
93db82f70eSsudarsana.kalluru@cavium.com return -EINVAL;
94db82f70eSsudarsana.kalluru@cavium.com }
95db82f70eSsudarsana.kalluru@cavium.com } else if (rc) {
96db82f70eSsudarsana.kalluru@cavium.com DP_INFO(p_hwfn, "Failed to release the ptp resource lock\n");
97db82f70eSsudarsana.kalluru@cavium.com }
98db82f70eSsudarsana.kalluru@cavium.com
99db82f70eSsudarsana.kalluru@cavium.com return rc;
100db82f70eSsudarsana.kalluru@cavium.com }
101db82f70eSsudarsana.kalluru@cavium.com
102c78c70faSSudarsana Reddy Kalluru /* Read Rx timestamp */
qed_ptp_hw_read_rx_ts(struct qed_dev * cdev,u64 * timestamp)103c78c70faSSudarsana Reddy Kalluru static int qed_ptp_hw_read_rx_ts(struct qed_dev *cdev, u64 *timestamp)
104c78c70faSSudarsana Reddy Kalluru {
105c78c70faSSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
106c78c70faSSudarsana Reddy Kalluru struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
107c78c70faSSudarsana Reddy Kalluru u32 val;
108c78c70faSSudarsana Reddy Kalluru
109c78c70faSSudarsana Reddy Kalluru *timestamp = 0;
110c78c70faSSudarsana Reddy Kalluru val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID);
111c78c70faSSudarsana Reddy Kalluru if (!(val & QED_TIMESTAMP_MASK)) {
112c78c70faSSudarsana Reddy Kalluru DP_INFO(p_hwfn, "Invalid Rx timestamp, buf_seqid = %d\n", val);
113c78c70faSSudarsana Reddy Kalluru return -EINVAL;
114c78c70faSSudarsana Reddy Kalluru }
115c78c70faSSudarsana Reddy Kalluru
116c78c70faSSudarsana Reddy Kalluru val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_LSB);
117c78c70faSSudarsana Reddy Kalluru *timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_MSB);
118c78c70faSSudarsana Reddy Kalluru *timestamp <<= 32;
119c78c70faSSudarsana Reddy Kalluru *timestamp |= val;
120c78c70faSSudarsana Reddy Kalluru
121c78c70faSSudarsana Reddy Kalluru /* Reset timestamp register to allow new timestamp */
122c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
123c78c70faSSudarsana Reddy Kalluru QED_TIMESTAMP_MASK);
124c78c70faSSudarsana Reddy Kalluru
125c78c70faSSudarsana Reddy Kalluru return 0;
126c78c70faSSudarsana Reddy Kalluru }
127c78c70faSSudarsana Reddy Kalluru
128c78c70faSSudarsana Reddy Kalluru /* Read Tx timestamp */
qed_ptp_hw_read_tx_ts(struct qed_dev * cdev,u64 * timestamp)129c78c70faSSudarsana Reddy Kalluru static int qed_ptp_hw_read_tx_ts(struct qed_dev *cdev, u64 *timestamp)
130c78c70faSSudarsana Reddy Kalluru {
131c78c70faSSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
132c78c70faSSudarsana Reddy Kalluru struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
133c78c70faSSudarsana Reddy Kalluru u32 val;
134c78c70faSSudarsana Reddy Kalluru
135c78c70faSSudarsana Reddy Kalluru *timestamp = 0;
136c78c70faSSudarsana Reddy Kalluru val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID);
137c78c70faSSudarsana Reddy Kalluru if (!(val & QED_TIMESTAMP_MASK)) {
13824c6203bSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_DEBUG,
13924c6203bSSudarsana Reddy Kalluru "Invalid Tx timestamp, buf_seqid = %08x\n", val);
140c78c70faSSudarsana Reddy Kalluru return -EINVAL;
141c78c70faSSudarsana Reddy Kalluru }
142c78c70faSSudarsana Reddy Kalluru
143c78c70faSSudarsana Reddy Kalluru val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_LSB);
144c78c70faSSudarsana Reddy Kalluru *timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_MSB);
145c78c70faSSudarsana Reddy Kalluru *timestamp <<= 32;
146c78c70faSSudarsana Reddy Kalluru *timestamp |= val;
147c78c70faSSudarsana Reddy Kalluru
148c78c70faSSudarsana Reddy Kalluru /* Reset timestamp register to allow new timestamp */
149c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID, QED_TIMESTAMP_MASK);
150c78c70faSSudarsana Reddy Kalluru
151c78c70faSSudarsana Reddy Kalluru return 0;
152c78c70faSSudarsana Reddy Kalluru }
153c78c70faSSudarsana Reddy Kalluru
154c78c70faSSudarsana Reddy Kalluru /* Read Phy Hardware Clock */
qed_ptp_hw_read_cc(struct qed_dev * cdev,u64 * phc_cycles)155c78c70faSSudarsana Reddy Kalluru static int qed_ptp_hw_read_cc(struct qed_dev *cdev, u64 *phc_cycles)
156c78c70faSSudarsana Reddy Kalluru {
157c78c70faSSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
158c78c70faSSudarsana Reddy Kalluru struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
159c78c70faSSudarsana Reddy Kalluru u32 temp = 0;
160c78c70faSSudarsana Reddy Kalluru
161c78c70faSSudarsana Reddy Kalluru temp = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_LSB);
162c78c70faSSudarsana Reddy Kalluru *phc_cycles = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_MSB);
163c78c70faSSudarsana Reddy Kalluru *phc_cycles <<= 32;
164c78c70faSSudarsana Reddy Kalluru *phc_cycles |= temp;
165c78c70faSSudarsana Reddy Kalluru
166c78c70faSSudarsana Reddy Kalluru return 0;
167c78c70faSSudarsana Reddy Kalluru }
168c78c70faSSudarsana Reddy Kalluru
169c78c70faSSudarsana Reddy Kalluru /* Filter PTP protocol packets that need to be timestamped */
qed_ptp_hw_cfg_filters(struct qed_dev * cdev,enum qed_ptp_filter_type rx_type,enum qed_ptp_hwtstamp_tx_type tx_type)1708d3f87d8Ssudarsana.kalluru@cavium.com static int qed_ptp_hw_cfg_filters(struct qed_dev *cdev,
1718d3f87d8Ssudarsana.kalluru@cavium.com enum qed_ptp_filter_type rx_type,
1728d3f87d8Ssudarsana.kalluru@cavium.com enum qed_ptp_hwtstamp_tx_type tx_type)
173c78c70faSSudarsana Reddy Kalluru {
174c78c70faSSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
175c78c70faSSudarsana Reddy Kalluru struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
1768d3f87d8Ssudarsana.kalluru@cavium.com u32 rule_mask, enable_cfg = 0x0;
177c78c70faSSudarsana Reddy Kalluru
1788d3f87d8Ssudarsana.kalluru@cavium.com switch (rx_type) {
1798d3f87d8Ssudarsana.kalluru@cavium.com case QED_PTP_FILTER_NONE:
1808d3f87d8Ssudarsana.kalluru@cavium.com enable_cfg = 0x0;
1818d3f87d8Ssudarsana.kalluru@cavium.com rule_mask = 0x3FFF;
182c78c70faSSudarsana Reddy Kalluru break;
1838d3f87d8Ssudarsana.kalluru@cavium.com case QED_PTP_FILTER_ALL:
1848d3f87d8Ssudarsana.kalluru@cavium.com enable_cfg = 0x7;
1858d3f87d8Ssudarsana.kalluru@cavium.com rule_mask = 0x3CAA;
1868d3f87d8Ssudarsana.kalluru@cavium.com break;
1878d3f87d8Ssudarsana.kalluru@cavium.com case QED_PTP_FILTER_V1_L4_EVENT:
1888d3f87d8Ssudarsana.kalluru@cavium.com enable_cfg = 0x3;
1898d3f87d8Ssudarsana.kalluru@cavium.com rule_mask = 0x3FFA;
1908d3f87d8Ssudarsana.kalluru@cavium.com break;
1918d3f87d8Ssudarsana.kalluru@cavium.com case QED_PTP_FILTER_V1_L4_GEN:
1928d3f87d8Ssudarsana.kalluru@cavium.com enable_cfg = 0x3;
1938d3f87d8Ssudarsana.kalluru@cavium.com rule_mask = 0x3FFE;
1948d3f87d8Ssudarsana.kalluru@cavium.com break;
1958d3f87d8Ssudarsana.kalluru@cavium.com case QED_PTP_FILTER_V2_L4_EVENT:
1968d3f87d8Ssudarsana.kalluru@cavium.com enable_cfg = 0x5;
1978d3f87d8Ssudarsana.kalluru@cavium.com rule_mask = 0x3FAA;
1988d3f87d8Ssudarsana.kalluru@cavium.com break;
1998d3f87d8Ssudarsana.kalluru@cavium.com case QED_PTP_FILTER_V2_L4_GEN:
2008d3f87d8Ssudarsana.kalluru@cavium.com enable_cfg = 0x5;
2018d3f87d8Ssudarsana.kalluru@cavium.com rule_mask = 0x3FEE;
2028d3f87d8Ssudarsana.kalluru@cavium.com break;
2038d3f87d8Ssudarsana.kalluru@cavium.com case QED_PTP_FILTER_V2_L2_EVENT:
2048d3f87d8Ssudarsana.kalluru@cavium.com enable_cfg = 0x5;
2058d3f87d8Ssudarsana.kalluru@cavium.com rule_mask = 0x3CFF;
2068d3f87d8Ssudarsana.kalluru@cavium.com break;
2078d3f87d8Ssudarsana.kalluru@cavium.com case QED_PTP_FILTER_V2_L2_GEN:
2088d3f87d8Ssudarsana.kalluru@cavium.com enable_cfg = 0x5;
209c78c70faSSudarsana Reddy Kalluru rule_mask = 0x3EFF;
210c78c70faSSudarsana Reddy Kalluru break;
2118d3f87d8Ssudarsana.kalluru@cavium.com case QED_PTP_FILTER_V2_EVENT:
2128d3f87d8Ssudarsana.kalluru@cavium.com enable_cfg = 0x5;
2138d3f87d8Ssudarsana.kalluru@cavium.com rule_mask = 0x3CAA;
214c78c70faSSudarsana Reddy Kalluru break;
2158d3f87d8Ssudarsana.kalluru@cavium.com case QED_PTP_FILTER_V2_GEN:
2168d3f87d8Ssudarsana.kalluru@cavium.com enable_cfg = 0x5;
2178d3f87d8Ssudarsana.kalluru@cavium.com rule_mask = 0x3EEE;
218c78c70faSSudarsana Reddy Kalluru break;
219c78c70faSSudarsana Reddy Kalluru default:
2208d3f87d8Ssudarsana.kalluru@cavium.com DP_INFO(p_hwfn, "Invalid PTP filter type %d\n", rx_type);
221c78c70faSSudarsana Reddy Kalluru return -EINVAL;
222c78c70faSSudarsana Reddy Kalluru }
223c78c70faSSudarsana Reddy Kalluru
224cedeac9dSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK,
225cedeac9dSSudarsana Reddy Kalluru QED_PTP_UCAST_PARAM_MASK);
226c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, rule_mask);
2278d3f87d8Ssudarsana.kalluru@cavium.com qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, enable_cfg);
228c78c70faSSudarsana Reddy Kalluru
2298d3f87d8Ssudarsana.kalluru@cavium.com if (tx_type == QED_PTP_HWTSTAMP_TX_OFF) {
2308d3f87d8Ssudarsana.kalluru@cavium.com qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 0x0);
2318d3f87d8Ssudarsana.kalluru@cavium.com qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
2328d3f87d8Ssudarsana.kalluru@cavium.com qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
2338d3f87d8Ssudarsana.kalluru@cavium.com } else {
2348d3f87d8Ssudarsana.kalluru@cavium.com qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, enable_cfg);
235cedeac9dSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK,
236cedeac9dSSudarsana Reddy Kalluru QED_PTP_UCAST_PARAM_MASK);
2378d3f87d8Ssudarsana.kalluru@cavium.com qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, rule_mask);
2388d3f87d8Ssudarsana.kalluru@cavium.com }
239c78c70faSSudarsana Reddy Kalluru
240c78c70faSSudarsana Reddy Kalluru /* Reset possibly old timestamps */
241c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
242c78c70faSSudarsana Reddy Kalluru QED_TIMESTAMP_MASK);
243c78c70faSSudarsana Reddy Kalluru
244c78c70faSSudarsana Reddy Kalluru return 0;
245c78c70faSSudarsana Reddy Kalluru }
246c78c70faSSudarsana Reddy Kalluru
247c78c70faSSudarsana Reddy Kalluru /* Adjust the HW clock by a rate given in parts-per-billion (ppb) units.
248c78c70faSSudarsana Reddy Kalluru * FW/HW accepts the adjustment value in terms of 3 parameters:
249c78c70faSSudarsana Reddy Kalluru * Drift period - adjustment happens once in certain number of nano seconds.
250c78c70faSSudarsana Reddy Kalluru * Drift value - time is adjusted by a certain value, for example by 5 ns.
251c78c70faSSudarsana Reddy Kalluru * Drift direction - add or subtract the adjustment value.
252c78c70faSSudarsana Reddy Kalluru * The routine translates ppb into the adjustment triplet in an optimal manner.
253c78c70faSSudarsana Reddy Kalluru */
qed_ptp_hw_adjfreq(struct qed_dev * cdev,s32 ppb)254c78c70faSSudarsana Reddy Kalluru static int qed_ptp_hw_adjfreq(struct qed_dev *cdev, s32 ppb)
255c78c70faSSudarsana Reddy Kalluru {
256c78c70faSSudarsana Reddy Kalluru s64 best_val = 0, val, best_period = 0, period, approx_dev, dif, dif2;
257c78c70faSSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
258c78c70faSSudarsana Reddy Kalluru struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
259c78c70faSSudarsana Reddy Kalluru u32 drift_ctr_cfg = 0, drift_state;
260c78c70faSSudarsana Reddy Kalluru int drift_dir = 1;
261c78c70faSSudarsana Reddy Kalluru
262c78c70faSSudarsana Reddy Kalluru if (ppb < 0) {
263c78c70faSSudarsana Reddy Kalluru ppb = -ppb;
264c78c70faSSudarsana Reddy Kalluru drift_dir = 0;
265c78c70faSSudarsana Reddy Kalluru }
266c78c70faSSudarsana Reddy Kalluru
267c78c70faSSudarsana Reddy Kalluru if (ppb > 1) {
268c78c70faSSudarsana Reddy Kalluru s64 best_dif = ppb, best_approx_dev = 1;
269c78c70faSSudarsana Reddy Kalluru
270c78c70faSSudarsana Reddy Kalluru /* Adjustment value is up to +/-7ns, find an optimal value in
271c78c70faSSudarsana Reddy Kalluru * this range.
272c78c70faSSudarsana Reddy Kalluru */
273c78c70faSSudarsana Reddy Kalluru for (val = 7; val > 0; val--) {
274c78c70faSSudarsana Reddy Kalluru period = div_s64(val * 1000000000, ppb);
275c78c70faSSudarsana Reddy Kalluru period -= 8;
276c78c70faSSudarsana Reddy Kalluru period >>= 4;
277c78c70faSSudarsana Reddy Kalluru if (period < 1)
278c78c70faSSudarsana Reddy Kalluru period = 1;
279c78c70faSSudarsana Reddy Kalluru if (period > 0xFFFFFFE)
280c78c70faSSudarsana Reddy Kalluru period = 0xFFFFFFE;
281c78c70faSSudarsana Reddy Kalluru
282c78c70faSSudarsana Reddy Kalluru /* Check both rounding ends for approximate error */
283c78c70faSSudarsana Reddy Kalluru approx_dev = period * 16 + 8;
284c78c70faSSudarsana Reddy Kalluru dif = ppb * approx_dev - val * 1000000000;
285c78c70faSSudarsana Reddy Kalluru dif2 = dif + 16 * ppb;
286c78c70faSSudarsana Reddy Kalluru
287c78c70faSSudarsana Reddy Kalluru if (dif < 0)
288c78c70faSSudarsana Reddy Kalluru dif = -dif;
289c78c70faSSudarsana Reddy Kalluru if (dif2 < 0)
290c78c70faSSudarsana Reddy Kalluru dif2 = -dif2;
291c78c70faSSudarsana Reddy Kalluru
292c78c70faSSudarsana Reddy Kalluru /* Determine which end gives better approximation */
293c78c70faSSudarsana Reddy Kalluru if (dif * (approx_dev + 16) > dif2 * approx_dev) {
294c78c70faSSudarsana Reddy Kalluru period++;
295c78c70faSSudarsana Reddy Kalluru approx_dev += 16;
296c78c70faSSudarsana Reddy Kalluru dif = dif2;
297c78c70faSSudarsana Reddy Kalluru }
298c78c70faSSudarsana Reddy Kalluru
299c78c70faSSudarsana Reddy Kalluru /* Track best approximation found so far */
300c78c70faSSudarsana Reddy Kalluru if (best_dif * approx_dev > dif * best_approx_dev) {
301c78c70faSSudarsana Reddy Kalluru best_dif = dif;
302c78c70faSSudarsana Reddy Kalluru best_val = val;
303c78c70faSSudarsana Reddy Kalluru best_period = period;
304c78c70faSSudarsana Reddy Kalluru best_approx_dev = approx_dev;
305c78c70faSSudarsana Reddy Kalluru }
306c78c70faSSudarsana Reddy Kalluru }
307c78c70faSSudarsana Reddy Kalluru } else if (ppb == 1) {
308c78c70faSSudarsana Reddy Kalluru /* This is a special case as its the only value which wouldn't
309c78c70faSSudarsana Reddy Kalluru * fit in a s64 variable. In order to prevent castings simple
310c78c70faSSudarsana Reddy Kalluru * handle it seperately.
311c78c70faSSudarsana Reddy Kalluru */
312c78c70faSSudarsana Reddy Kalluru best_val = 4;
313c78c70faSSudarsana Reddy Kalluru best_period = 0xee6b27f;
314c78c70faSSudarsana Reddy Kalluru } else {
315c78c70faSSudarsana Reddy Kalluru best_val = 0;
316c78c70faSSudarsana Reddy Kalluru best_period = 0xFFFFFFF;
317c78c70faSSudarsana Reddy Kalluru }
318c78c70faSSudarsana Reddy Kalluru
319c78c70faSSudarsana Reddy Kalluru drift_ctr_cfg = (best_period << QED_DRIFT_CNTR_TIME_QUANTA_SHIFT) |
320c78c70faSSudarsana Reddy Kalluru (((int)best_val) << QED_DRIFT_CNTR_ADJUSTMENT_SHIFT) |
321c78c70faSSudarsana Reddy Kalluru (((int)drift_dir) << QED_DRIFT_CNTR_DIRECTION_SHIFT);
322c78c70faSSudarsana Reddy Kalluru
323c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x1);
324c78c70faSSudarsana Reddy Kalluru
325c78c70faSSudarsana Reddy Kalluru drift_state = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR);
326c78c70faSSudarsana Reddy Kalluru if (drift_state & 1) {
327c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_DRIFT_CNTR_CONF,
328c78c70faSSudarsana Reddy Kalluru drift_ctr_cfg);
329c78c70faSSudarsana Reddy Kalluru } else {
330c78c70faSSudarsana Reddy Kalluru DP_INFO(p_hwfn, "Drift counter is not reset\n");
331c78c70faSSudarsana Reddy Kalluru return -EINVAL;
332c78c70faSSudarsana Reddy Kalluru }
333c78c70faSSudarsana Reddy Kalluru
334c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x0);
335c78c70faSSudarsana Reddy Kalluru
336c78c70faSSudarsana Reddy Kalluru return 0;
337c78c70faSSudarsana Reddy Kalluru }
338c78c70faSSudarsana Reddy Kalluru
qed_ptp_hw_enable(struct qed_dev * cdev)339c78c70faSSudarsana Reddy Kalluru static int qed_ptp_hw_enable(struct qed_dev *cdev)
340c78c70faSSudarsana Reddy Kalluru {
341c78c70faSSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
342d179bd16Ssudarsana.kalluru@cavium.com struct qed_ptt *p_ptt;
343db82f70eSsudarsana.kalluru@cavium.com int rc;
344db82f70eSsudarsana.kalluru@cavium.com
345d179bd16Ssudarsana.kalluru@cavium.com p_ptt = qed_ptt_acquire(p_hwfn);
346d179bd16Ssudarsana.kalluru@cavium.com if (!p_ptt) {
347d179bd16Ssudarsana.kalluru@cavium.com DP_NOTICE(p_hwfn, "Failed to acquire PTT for PTP\n");
348d179bd16Ssudarsana.kalluru@cavium.com return -EBUSY;
349d179bd16Ssudarsana.kalluru@cavium.com }
350d179bd16Ssudarsana.kalluru@cavium.com
351d179bd16Ssudarsana.kalluru@cavium.com p_hwfn->p_ptp_ptt = p_ptt;
352d179bd16Ssudarsana.kalluru@cavium.com
353db82f70eSsudarsana.kalluru@cavium.com rc = qed_ptp_res_lock(p_hwfn, p_ptt);
354db82f70eSsudarsana.kalluru@cavium.com if (rc) {
355db82f70eSsudarsana.kalluru@cavium.com DP_INFO(p_hwfn,
356db82f70eSsudarsana.kalluru@cavium.com "Couldn't acquire the resource lock, skip ptp enable for this PF\n");
357d179bd16Ssudarsana.kalluru@cavium.com qed_ptt_release(p_hwfn, p_ptt);
358d179bd16Ssudarsana.kalluru@cavium.com p_hwfn->p_ptp_ptt = NULL;
359db82f70eSsudarsana.kalluru@cavium.com return rc;
360db82f70eSsudarsana.kalluru@cavium.com }
361c78c70faSSudarsana Reddy Kalluru
362c78c70faSSudarsana Reddy Kalluru /* Reset PTP event detection rules - will be configured in the IOCTL */
363c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0x7FF);
364c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, 0x3FFF);
365c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
366c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
367c78c70faSSudarsana Reddy Kalluru
368c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 7);
369c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, 7);
370c78c70faSSudarsana Reddy Kalluru
371c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TS_OUTPUT_ENABLE_PDA, 0x1);
372c78c70faSSudarsana Reddy Kalluru
373c78c70faSSudarsana Reddy Kalluru /* Pause free running counter */
3749c79ddaaSMintz, Yuval if (QED_IS_BB_B0(p_hwfn->cdev))
375c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TIMESYNC_GEN_REG_BB, 2);
3769c79ddaaSMintz, Yuval if (QED_IS_AH(p_hwfn->cdev))
3779c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREECNT_UPDATE_K2, 2);
378c78c70faSSudarsana Reddy Kalluru
379c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREE_CNT_VALUE_LSB, 0);
380c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREE_CNT_VALUE_MSB, 0);
381c78c70faSSudarsana Reddy Kalluru /* Resume free running counter */
3829c79ddaaSMintz, Yuval if (QED_IS_BB_B0(p_hwfn->cdev))
383c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TIMESYNC_GEN_REG_BB, 4);
3849c79ddaaSMintz, Yuval if (QED_IS_AH(p_hwfn->cdev)) {
3859c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREECNT_UPDATE_K2, 4);
3869c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_ptt, NIG_REG_PTP_LATCH_OSTS_PKT_TIME, 1);
3879c79ddaaSMintz, Yuval }
388c78c70faSSudarsana Reddy Kalluru
389c78c70faSSudarsana Reddy Kalluru /* Disable drift register */
390c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_DRIFT_CNTR_CONF, 0x0);
391c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x0);
392c78c70faSSudarsana Reddy Kalluru
393c78c70faSSudarsana Reddy Kalluru /* Reset possibly old timestamps */
394c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
395c78c70faSSudarsana Reddy Kalluru QED_TIMESTAMP_MASK);
396c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID, QED_TIMESTAMP_MASK);
397c78c70faSSudarsana Reddy Kalluru
398c78c70faSSudarsana Reddy Kalluru return 0;
399c78c70faSSudarsana Reddy Kalluru }
400c78c70faSSudarsana Reddy Kalluru
qed_ptp_hw_disable(struct qed_dev * cdev)401c78c70faSSudarsana Reddy Kalluru static int qed_ptp_hw_disable(struct qed_dev *cdev)
402c78c70faSSudarsana Reddy Kalluru {
403c78c70faSSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
404c78c70faSSudarsana Reddy Kalluru struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
405c78c70faSSudarsana Reddy Kalluru
406db82f70eSsudarsana.kalluru@cavium.com qed_ptp_res_unlock(p_hwfn, p_ptt);
407db82f70eSsudarsana.kalluru@cavium.com
408c78c70faSSudarsana Reddy Kalluru /* Reset PTP event detection rules */
409c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0x7FF);
410c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, 0x3FFF);
411c78c70faSSudarsana Reddy Kalluru
412c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
413c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
414c78c70faSSudarsana Reddy Kalluru
415c78c70faSSudarsana Reddy Kalluru /* Disable the PTP feature */
416c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, 0x0);
417c78c70faSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 0x0);
418c78c70faSSudarsana Reddy Kalluru
419d179bd16Ssudarsana.kalluru@cavium.com qed_ptt_release(p_hwfn, p_ptt);
420d179bd16Ssudarsana.kalluru@cavium.com p_hwfn->p_ptp_ptt = NULL;
421d179bd16Ssudarsana.kalluru@cavium.com
422c78c70faSSudarsana Reddy Kalluru return 0;
423c78c70faSSudarsana Reddy Kalluru }
424c78c70faSSudarsana Reddy Kalluru
425c78c70faSSudarsana Reddy Kalluru const struct qed_eth_ptp_ops qed_ptp_ops_pass = {
4268d3f87d8Ssudarsana.kalluru@cavium.com .cfg_filters = qed_ptp_hw_cfg_filters,
427c78c70faSSudarsana Reddy Kalluru .read_rx_ts = qed_ptp_hw_read_rx_ts,
428c78c70faSSudarsana Reddy Kalluru .read_tx_ts = qed_ptp_hw_read_tx_ts,
429c78c70faSSudarsana Reddy Kalluru .read_cc = qed_ptp_hw_read_cc,
430c78c70faSSudarsana Reddy Kalluru .adjfreq = qed_ptp_hw_adjfreq,
431c78c70faSSudarsana Reddy Kalluru .disable = qed_ptp_hw_disable,
432c78c70faSSudarsana Reddy Kalluru .enable = qed_ptp_hw_enable,
433c78c70faSSudarsana Reddy Kalluru };
434