1ee824f4bSOmkar Kulkarni /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2ee824f4bSOmkar Kulkarni /* QLogic qed NIC Driver 3ee824f4bSOmkar Kulkarni * Copyright (c) 2019-2021 Marvell International Ltd. 4ee824f4bSOmkar Kulkarni */ 5ee824f4bSOmkar Kulkarni 6ee824f4bSOmkar Kulkarni #ifndef _QED_MFW_HSI_H 7ee824f4bSOmkar Kulkarni #define _QED_MFW_HSI_H 8ee824f4bSOmkar Kulkarni 9ee824f4bSOmkar Kulkarni #define MFW_TRACE_SIGNATURE 0x25071946 10ee824f4bSOmkar Kulkarni 11ee824f4bSOmkar Kulkarni /* The trace in the buffer */ 12ee824f4bSOmkar Kulkarni #define MFW_TRACE_EVENTID_MASK 0x00ffff 13ee824f4bSOmkar Kulkarni #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000 14ee824f4bSOmkar Kulkarni #define MFW_TRACE_PRM_SIZE_OFFSET 16 15ee824f4bSOmkar Kulkarni #define MFW_TRACE_ENTRY_SIZE 3 16ee824f4bSOmkar Kulkarni 17ee824f4bSOmkar Kulkarni struct mcp_trace { 18ee824f4bSOmkar Kulkarni u32 signature; /* Help to identify that the trace is valid */ 19ee824f4bSOmkar Kulkarni u32 size; /* the size of the trace buffer in bytes */ 20ee824f4bSOmkar Kulkarni u32 curr_level; /* 2 - all will be written to the buffer 21ee824f4bSOmkar Kulkarni * 1 - debug trace will not be written 22ee824f4bSOmkar Kulkarni * 0 - just errors will be written to the buffer 23ee824f4bSOmkar Kulkarni */ 24ee824f4bSOmkar Kulkarni u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means 25ee824f4bSOmkar Kulkarni * mask it. 26ee824f4bSOmkar Kulkarni */ 27ee824f4bSOmkar Kulkarni 28ee824f4bSOmkar Kulkarni /* Warning: the following pointers are assumed to be 32bits as they are 29ee824f4bSOmkar Kulkarni * used only in the MFW. 30ee824f4bSOmkar Kulkarni */ 31ee824f4bSOmkar Kulkarni u32 trace_prod; /* The next trace will be written to this offset */ 32ee824f4bSOmkar Kulkarni u32 trace_oldest; /* The oldest valid trace starts at this offset 33ee824f4bSOmkar Kulkarni * (usually very close after the current producer). 34ee824f4bSOmkar Kulkarni */ 35ee824f4bSOmkar Kulkarni }; 36ee824f4bSOmkar Kulkarni 37ee824f4bSOmkar Kulkarni #define VF_MAX_STATIC 192 38f2a74107SPrabhakar Kushwaha #define VF_BITMAP_SIZE_IN_DWORDS (VF_MAX_STATIC / 32) 39f2a74107SPrabhakar Kushwaha #define VF_BITMAP_SIZE_IN_BYTES (VF_BITMAP_SIZE_IN_DWORDS * sizeof(u32)) 40f2a74107SPrabhakar Kushwaha 41f2a74107SPrabhakar Kushwaha #define EXT_VF_MAX_STATIC 240 42f2a74107SPrabhakar Kushwaha #define EXT_VF_BITMAP_SIZE_IN_DWORDS (((EXT_VF_MAX_STATIC - 1) / 32) + 1) 43f2a74107SPrabhakar Kushwaha #define EXT_VF_BITMAP_SIZE_IN_BYTES (EXT_VF_BITMAP_SIZE_IN_DWORDS * sizeof(u32)) 44f2a74107SPrabhakar Kushwaha #define ADDED_VF_BITMAP_SIZE 2 45ee824f4bSOmkar Kulkarni 46ee824f4bSOmkar Kulkarni #define MCP_GLOB_PATH_MAX 2 47ee824f4bSOmkar Kulkarni #define MCP_PORT_MAX 2 48ee824f4bSOmkar Kulkarni #define MCP_GLOB_PORT_MAX 4 49ee824f4bSOmkar Kulkarni #define MCP_GLOB_FUNC_MAX 16 50ee824f4bSOmkar Kulkarni 51ee824f4bSOmkar Kulkarni typedef u32 offsize_t; /* In DWORDS !!! */ 52ee824f4bSOmkar Kulkarni /* Offset from the beginning of the MCP scratchpad */ 53ee824f4bSOmkar Kulkarni #define OFFSIZE_OFFSET_SHIFT 0 54ee824f4bSOmkar Kulkarni #define OFFSIZE_OFFSET_MASK 0x0000ffff 55ee824f4bSOmkar Kulkarni /* Size of specific element (not the whole array if any) */ 56ee824f4bSOmkar Kulkarni #define OFFSIZE_SIZE_SHIFT 16 57ee824f4bSOmkar Kulkarni #define OFFSIZE_SIZE_MASK 0xffff0000 58ee824f4bSOmkar Kulkarni 59ee824f4bSOmkar Kulkarni #define SECTION_OFFSET(_offsize) (((((_offsize) & \ 60ee824f4bSOmkar Kulkarni OFFSIZE_OFFSET_MASK) >> \ 61ee824f4bSOmkar Kulkarni OFFSIZE_OFFSET_SHIFT) << 2)) 62ee824f4bSOmkar Kulkarni 63ee824f4bSOmkar Kulkarni #define QED_SECTION_SIZE(_offsize) ((((_offsize) & \ 64ee824f4bSOmkar Kulkarni OFFSIZE_SIZE_MASK) >> \ 65ee824f4bSOmkar Kulkarni OFFSIZE_SIZE_SHIFT) << 2) 66ee824f4bSOmkar Kulkarni 67ee824f4bSOmkar Kulkarni #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \ 68ee824f4bSOmkar Kulkarni SECTION_OFFSET((_offsize)) + \ 69ee824f4bSOmkar Kulkarni (QED_SECTION_SIZE((_offsize)) * (idx))) 70ee824f4bSOmkar Kulkarni 71ee824f4bSOmkar Kulkarni #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ 72ee824f4bSOmkar Kulkarni ((_pub_base) + offsetof(struct mcp_public_data, sections[_section])) 73ee824f4bSOmkar Kulkarni 74ee824f4bSOmkar Kulkarni /* PHY configuration */ 75ee824f4bSOmkar Kulkarni struct eth_phy_cfg { 76ee824f4bSOmkar Kulkarni u32 speed; 77ee824f4bSOmkar Kulkarni #define ETH_SPEED_AUTONEG 0x0 78ee824f4bSOmkar Kulkarni #define ETH_SPEED_SMARTLINQ 0x8 79ee824f4bSOmkar Kulkarni 80ee824f4bSOmkar Kulkarni u32 pause; 81ee824f4bSOmkar Kulkarni #define ETH_PAUSE_NONE 0x0 82ee824f4bSOmkar Kulkarni #define ETH_PAUSE_AUTONEG 0x1 83ee824f4bSOmkar Kulkarni #define ETH_PAUSE_RX 0x2 84ee824f4bSOmkar Kulkarni #define ETH_PAUSE_TX 0x4 85ee824f4bSOmkar Kulkarni 86ee824f4bSOmkar Kulkarni u32 adv_speed; 87ee824f4bSOmkar Kulkarni 88ee824f4bSOmkar Kulkarni u32 loopback_mode; 89ee824f4bSOmkar Kulkarni #define ETH_LOOPBACK_NONE 0x0 90ee824f4bSOmkar Kulkarni #define ETH_LOOPBACK_INT_PHY 0x1 91ee824f4bSOmkar Kulkarni #define ETH_LOOPBACK_EXT_PHY 0x2 92ee824f4bSOmkar Kulkarni #define ETH_LOOPBACK_EXT 0x3 93ee824f4bSOmkar Kulkarni #define ETH_LOOPBACK_MAC 0x4 94ee824f4bSOmkar Kulkarni #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 0x5 95ee824f4bSOmkar Kulkarni #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 0x6 96ee824f4bSOmkar Kulkarni #define ETH_LOOPBACK_PCS_AH_ONLY 0x7 97ee824f4bSOmkar Kulkarni #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY 0x8 98ee824f4bSOmkar Kulkarni #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY 0x9 99ee824f4bSOmkar Kulkarni 100ee824f4bSOmkar Kulkarni u32 eee_cfg; 101ee824f4bSOmkar Kulkarni #define EEE_CFG_EEE_ENABLED BIT(0) 102ee824f4bSOmkar Kulkarni #define EEE_CFG_TX_LPI BIT(1) 103ee824f4bSOmkar Kulkarni #define EEE_CFG_ADV_SPEED_1G BIT(2) 104ee824f4bSOmkar Kulkarni #define EEE_CFG_ADV_SPEED_10G BIT(3) 105ee824f4bSOmkar Kulkarni #define EEE_TX_TIMER_USEC_MASK 0xfffffff0 106ee824f4bSOmkar Kulkarni #define EEE_TX_TIMER_USEC_OFFSET 4 107ee824f4bSOmkar Kulkarni #define EEE_TX_TIMER_USEC_BALANCED_TIME 0xa00 108ee824f4bSOmkar Kulkarni #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME 0x100 109ee824f4bSOmkar Kulkarni #define EEE_TX_TIMER_USEC_LATENCY_TIME 0x6000 110ee824f4bSOmkar Kulkarni 111f2a74107SPrabhakar Kushwaha u32 link_modes; 112ee824f4bSOmkar Kulkarni 113ee824f4bSOmkar Kulkarni u32 fec_mode; 114ee824f4bSOmkar Kulkarni #define FEC_FORCE_MODE_MASK 0x000000ff 115ee824f4bSOmkar Kulkarni #define FEC_FORCE_MODE_OFFSET 0 116ee824f4bSOmkar Kulkarni #define FEC_FORCE_MODE_NONE 0x00 117ee824f4bSOmkar Kulkarni #define FEC_FORCE_MODE_FIRECODE 0x01 118ee824f4bSOmkar Kulkarni #define FEC_FORCE_MODE_RS 0x02 119ee824f4bSOmkar Kulkarni #define FEC_FORCE_MODE_AUTO 0x07 120ee824f4bSOmkar Kulkarni #define FEC_EXTENDED_MODE_MASK 0xffffff00 121ee824f4bSOmkar Kulkarni #define FEC_EXTENDED_MODE_OFFSET 8 122f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_NONE 0x00000000 123f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_10G_NONE 0x00000100 124f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_10G_BASE_R 0x00000200 125f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_25G_NONE 0x00000400 126f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_25G_BASE_R 0x00000800 127f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_25G_RS528 0x00001000 128f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_40G_NONE 0x00002000 129f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_40G_BASE_R 0x00004000 130f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_50G_NONE 0x00008000 131f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_50G_BASE_R 0x00010000 132f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_50G_RS528 0x00020000 133f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_50G_RS544 0x00040000 134f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_100G_NONE 0x00080000 135f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_100G_BASE_R 0x00100000 136f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_100G_RS528 0x00200000 137f2a74107SPrabhakar Kushwaha #define ETH_EXT_FEC_100G_RS544 0x00400000 138ee824f4bSOmkar Kulkarni 139ee824f4bSOmkar Kulkarni u32 extended_speed; 140ee824f4bSOmkar Kulkarni #define ETH_EXT_SPEED_MASK 0x0000ffff 141ee824f4bSOmkar Kulkarni #define ETH_EXT_SPEED_OFFSET 0 142f2a74107SPrabhakar Kushwaha #define ETH_EXT_SPEED_NONE 0x00000001 143ee824f4bSOmkar Kulkarni #define ETH_EXT_SPEED_1G 0x00000002 144ee824f4bSOmkar Kulkarni #define ETH_EXT_SPEED_10G 0x00000004 145f2a74107SPrabhakar Kushwaha #define ETH_EXT_SPEED_25G 0x00000008 146f2a74107SPrabhakar Kushwaha #define ETH_EXT_SPEED_40G 0x00000010 147f2a74107SPrabhakar Kushwaha #define ETH_EXT_SPEED_50G_BASE_R 0x00000020 148f2a74107SPrabhakar Kushwaha #define ETH_EXT_SPEED_50G_BASE_R2 0x00000040 149f2a74107SPrabhakar Kushwaha #define ETH_EXT_SPEED_100G_BASE_R2 0x00000080 150f2a74107SPrabhakar Kushwaha #define ETH_EXT_SPEED_100G_BASE_R4 0x00000100 151f2a74107SPrabhakar Kushwaha #define ETH_EXT_SPEED_100G_BASE_P4 0x00000200 152f2a74107SPrabhakar Kushwaha #define ETH_EXT_ADV_SPEED_MASK 0xFFFF0000 153ee824f4bSOmkar Kulkarni #define ETH_EXT_ADV_SPEED_OFFSET 16 154f2a74107SPrabhakar Kushwaha #define ETH_EXT_ADV_SPEED_1G 0x00010000 155f2a74107SPrabhakar Kushwaha #define ETH_EXT_ADV_SPEED_10G 0x00020000 156f2a74107SPrabhakar Kushwaha #define ETH_EXT_ADV_SPEED_25G 0x00040000 157f2a74107SPrabhakar Kushwaha #define ETH_EXT_ADV_SPEED_40G 0x00080000 158f2a74107SPrabhakar Kushwaha #define ETH_EXT_ADV_SPEED_50G_BASE_R 0x00100000 159f2a74107SPrabhakar Kushwaha #define ETH_EXT_ADV_SPEED_50G_BASE_R2 0x00200000 160f2a74107SPrabhakar Kushwaha #define ETH_EXT_ADV_SPEED_100G_BASE_R2 0x00400000 161f2a74107SPrabhakar Kushwaha #define ETH_EXT_ADV_SPEED_100G_BASE_R4 0x00800000 162f2a74107SPrabhakar Kushwaha #define ETH_EXT_ADV_SPEED_100G_BASE_P4 0x01000000 163ee824f4bSOmkar Kulkarni }; 164ee824f4bSOmkar Kulkarni 165ee824f4bSOmkar Kulkarni struct port_mf_cfg { 166ee824f4bSOmkar Kulkarni u32 dynamic_cfg; 167ee824f4bSOmkar Kulkarni #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff 168ee824f4bSOmkar Kulkarni #define PORT_MF_CFG_OV_TAG_SHIFT 0 169ee824f4bSOmkar Kulkarni #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK 170ee824f4bSOmkar Kulkarni 171ee824f4bSOmkar Kulkarni u32 reserved[1]; 172ee824f4bSOmkar Kulkarni }; 173ee824f4bSOmkar Kulkarni 174ee824f4bSOmkar Kulkarni struct eth_stats { 175ee824f4bSOmkar Kulkarni u64 r64; 176ee824f4bSOmkar Kulkarni u64 r127; 177ee824f4bSOmkar Kulkarni u64 r255; 178ee824f4bSOmkar Kulkarni u64 r511; 179ee824f4bSOmkar Kulkarni u64 r1023; 180ee824f4bSOmkar Kulkarni u64 r1518; 181ee824f4bSOmkar Kulkarni 182ee824f4bSOmkar Kulkarni union { 183ee824f4bSOmkar Kulkarni struct { 184ee824f4bSOmkar Kulkarni u64 r1522; 185ee824f4bSOmkar Kulkarni u64 r2047; 186ee824f4bSOmkar Kulkarni u64 r4095; 187ee824f4bSOmkar Kulkarni u64 r9216; 188ee824f4bSOmkar Kulkarni u64 r16383; 189ee824f4bSOmkar Kulkarni } bb0; 190ee824f4bSOmkar Kulkarni struct { 191ee824f4bSOmkar Kulkarni u64 unused1; 192ee824f4bSOmkar Kulkarni u64 r1519_to_max; 193ee824f4bSOmkar Kulkarni u64 unused2; 194ee824f4bSOmkar Kulkarni u64 unused3; 195ee824f4bSOmkar Kulkarni u64 unused4; 196ee824f4bSOmkar Kulkarni } ah0; 197ee824f4bSOmkar Kulkarni } u0; 198ee824f4bSOmkar Kulkarni 199ee824f4bSOmkar Kulkarni u64 rfcs; 200ee824f4bSOmkar Kulkarni u64 rxcf; 201ee824f4bSOmkar Kulkarni u64 rxpf; 202ee824f4bSOmkar Kulkarni u64 rxpp; 203ee824f4bSOmkar Kulkarni u64 raln; 204ee824f4bSOmkar Kulkarni u64 rfcr; 205ee824f4bSOmkar Kulkarni u64 rovr; 206ee824f4bSOmkar Kulkarni u64 rjbr; 207ee824f4bSOmkar Kulkarni u64 rund; 208ee824f4bSOmkar Kulkarni u64 rfrg; 209ee824f4bSOmkar Kulkarni u64 t64; 210ee824f4bSOmkar Kulkarni u64 t127; 211ee824f4bSOmkar Kulkarni u64 t255; 212ee824f4bSOmkar Kulkarni u64 t511; 213ee824f4bSOmkar Kulkarni u64 t1023; 214ee824f4bSOmkar Kulkarni u64 t1518; 215ee824f4bSOmkar Kulkarni 216ee824f4bSOmkar Kulkarni union { 217ee824f4bSOmkar Kulkarni struct { 218ee824f4bSOmkar Kulkarni u64 t2047; 219ee824f4bSOmkar Kulkarni u64 t4095; 220ee824f4bSOmkar Kulkarni u64 t9216; 221ee824f4bSOmkar Kulkarni u64 t16383; 222ee824f4bSOmkar Kulkarni } bb1; 223ee824f4bSOmkar Kulkarni struct { 224ee824f4bSOmkar Kulkarni u64 t1519_to_max; 225ee824f4bSOmkar Kulkarni u64 unused6; 226ee824f4bSOmkar Kulkarni u64 unused7; 227ee824f4bSOmkar Kulkarni u64 unused8; 228ee824f4bSOmkar Kulkarni } ah1; 229ee824f4bSOmkar Kulkarni } u1; 230ee824f4bSOmkar Kulkarni 231ee824f4bSOmkar Kulkarni u64 txpf; 232ee824f4bSOmkar Kulkarni u64 txpp; 233ee824f4bSOmkar Kulkarni 234ee824f4bSOmkar Kulkarni union { 235ee824f4bSOmkar Kulkarni struct { 236ee824f4bSOmkar Kulkarni u64 tlpiec; 237ee824f4bSOmkar Kulkarni u64 tncl; 238ee824f4bSOmkar Kulkarni } bb2; 239ee824f4bSOmkar Kulkarni struct { 240ee824f4bSOmkar Kulkarni u64 unused9; 241ee824f4bSOmkar Kulkarni u64 unused10; 242ee824f4bSOmkar Kulkarni } ah2; 243ee824f4bSOmkar Kulkarni } u2; 244ee824f4bSOmkar Kulkarni 245ee824f4bSOmkar Kulkarni u64 rbyte; 246ee824f4bSOmkar Kulkarni u64 rxuca; 247ee824f4bSOmkar Kulkarni u64 rxmca; 248ee824f4bSOmkar Kulkarni u64 rxbca; 249ee824f4bSOmkar Kulkarni u64 rxpok; 250ee824f4bSOmkar Kulkarni u64 tbyte; 251ee824f4bSOmkar Kulkarni u64 txuca; 252ee824f4bSOmkar Kulkarni u64 txmca; 253ee824f4bSOmkar Kulkarni u64 txbca; 254ee824f4bSOmkar Kulkarni u64 txcf; 255ee824f4bSOmkar Kulkarni }; 256ee824f4bSOmkar Kulkarni 257f2a74107SPrabhakar Kushwaha struct pkt_type_cnt { 258f2a74107SPrabhakar Kushwaha u64 tc_tx_pkt_cnt[8]; 259f2a74107SPrabhakar Kushwaha u64 tc_tx_oct_cnt[8]; 260f2a74107SPrabhakar Kushwaha u64 priority_rx_pkt_cnt[8]; 261f2a74107SPrabhakar Kushwaha u64 priority_rx_oct_cnt[8]; 262f2a74107SPrabhakar Kushwaha }; 263f2a74107SPrabhakar Kushwaha 264ee824f4bSOmkar Kulkarni struct brb_stats { 265ee824f4bSOmkar Kulkarni u64 brb_truncate[8]; 266ee824f4bSOmkar Kulkarni u64 brb_discard[8]; 267ee824f4bSOmkar Kulkarni }; 268ee824f4bSOmkar Kulkarni 269ee824f4bSOmkar Kulkarni struct port_stats { 270ee824f4bSOmkar Kulkarni struct brb_stats brb; 271ee824f4bSOmkar Kulkarni struct eth_stats eth; 272ee824f4bSOmkar Kulkarni }; 273ee824f4bSOmkar Kulkarni 274ee824f4bSOmkar Kulkarni struct couple_mode_teaming { 275ee824f4bSOmkar Kulkarni u8 port_cmt[MCP_GLOB_PORT_MAX]; 276ee824f4bSOmkar Kulkarni #define PORT_CMT_IN_TEAM BIT(0) 277ee824f4bSOmkar Kulkarni 278ee824f4bSOmkar Kulkarni #define PORT_CMT_PORT_ROLE BIT(1) 279ee824f4bSOmkar Kulkarni #define PORT_CMT_PORT_INACTIVE (0 << 1) 280ee824f4bSOmkar Kulkarni #define PORT_CMT_PORT_ACTIVE BIT(1) 281ee824f4bSOmkar Kulkarni 282ee824f4bSOmkar Kulkarni #define PORT_CMT_TEAM_MASK BIT(2) 283ee824f4bSOmkar Kulkarni #define PORT_CMT_TEAM0 (0 << 2) 284ee824f4bSOmkar Kulkarni #define PORT_CMT_TEAM1 BIT(2) 285ee824f4bSOmkar Kulkarni }; 286ee824f4bSOmkar Kulkarni 287ee824f4bSOmkar Kulkarni #define LLDP_CHASSIS_ID_STAT_LEN 4 288ee824f4bSOmkar Kulkarni #define LLDP_PORT_ID_STAT_LEN 4 289ee824f4bSOmkar Kulkarni #define DCBX_MAX_APP_PROTOCOL 32 290ee824f4bSOmkar Kulkarni #define MAX_SYSTEM_LLDP_TLV_DATA 32 291f2a74107SPrabhakar Kushwaha #define MAX_TLV_BUFFER 128 292ee824f4bSOmkar Kulkarni 293ee824f4bSOmkar Kulkarni enum _lldp_agent { 294ee824f4bSOmkar Kulkarni LLDP_NEAREST_BRIDGE = 0, 295ee824f4bSOmkar Kulkarni LLDP_NEAREST_NON_TPMR_BRIDGE, 296ee824f4bSOmkar Kulkarni LLDP_NEAREST_CUSTOMER_BRIDGE, 297ee824f4bSOmkar Kulkarni LLDP_MAX_LLDP_AGENTS 298ee824f4bSOmkar Kulkarni }; 299ee824f4bSOmkar Kulkarni 300ee824f4bSOmkar Kulkarni struct lldp_config_params_s { 301ee824f4bSOmkar Kulkarni u32 config; 302ee824f4bSOmkar Kulkarni #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff 303ee824f4bSOmkar Kulkarni #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0 304ee824f4bSOmkar Kulkarni #define LLDP_CONFIG_HOLD_MASK 0x00000f00 305ee824f4bSOmkar Kulkarni #define LLDP_CONFIG_HOLD_SHIFT 8 306ee824f4bSOmkar Kulkarni #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 307ee824f4bSOmkar Kulkarni #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12 308ee824f4bSOmkar Kulkarni #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 309ee824f4bSOmkar Kulkarni #define LLDP_CONFIG_ENABLE_RX_SHIFT 30 310ee824f4bSOmkar Kulkarni #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 311ee824f4bSOmkar Kulkarni #define LLDP_CONFIG_ENABLE_TX_SHIFT 31 312ee824f4bSOmkar Kulkarni u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 313ee824f4bSOmkar Kulkarni u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; 314ee824f4bSOmkar Kulkarni }; 315ee824f4bSOmkar Kulkarni 316ee824f4bSOmkar Kulkarni struct lldp_status_params_s { 317ee824f4bSOmkar Kulkarni u32 prefix_seq_num; 318ee824f4bSOmkar Kulkarni u32 status; 319ee824f4bSOmkar Kulkarni u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 320ee824f4bSOmkar Kulkarni u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; 321ee824f4bSOmkar Kulkarni u32 suffix_seq_num; 322ee824f4bSOmkar Kulkarni }; 323ee824f4bSOmkar Kulkarni 324ee824f4bSOmkar Kulkarni struct dcbx_ets_feature { 325ee824f4bSOmkar Kulkarni u32 flags; 326ee824f4bSOmkar Kulkarni #define DCBX_ETS_ENABLED_MASK 0x00000001 327ee824f4bSOmkar Kulkarni #define DCBX_ETS_ENABLED_SHIFT 0 328ee824f4bSOmkar Kulkarni #define DCBX_ETS_WILLING_MASK 0x00000002 329ee824f4bSOmkar Kulkarni #define DCBX_ETS_WILLING_SHIFT 1 330ee824f4bSOmkar Kulkarni #define DCBX_ETS_ERROR_MASK 0x00000004 331ee824f4bSOmkar Kulkarni #define DCBX_ETS_ERROR_SHIFT 2 332ee824f4bSOmkar Kulkarni #define DCBX_ETS_CBS_MASK 0x00000008 333ee824f4bSOmkar Kulkarni #define DCBX_ETS_CBS_SHIFT 3 334ee824f4bSOmkar Kulkarni #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 335ee824f4bSOmkar Kulkarni #define DCBX_ETS_MAX_TCS_SHIFT 4 336ee824f4bSOmkar Kulkarni #define DCBX_OOO_TC_MASK 0x00000f00 337ee824f4bSOmkar Kulkarni #define DCBX_OOO_TC_SHIFT 8 338ee824f4bSOmkar Kulkarni u32 pri_tc_tbl[1]; 339ee824f4bSOmkar Kulkarni #define DCBX_TCP_OOO_TC (4) 340f2a74107SPrabhakar Kushwaha #define DCBX_TCP_OOO_K2_4PORT_TC (3) 341ee824f4bSOmkar Kulkarni 342ee824f4bSOmkar Kulkarni #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1) 343ee824f4bSOmkar Kulkarni #define DCBX_CEE_STRICT_PRIORITY 0xf 344ee824f4bSOmkar Kulkarni u32 tc_bw_tbl[2]; 345ee824f4bSOmkar Kulkarni u32 tc_tsa_tbl[2]; 346ee824f4bSOmkar Kulkarni #define DCBX_ETS_TSA_STRICT 0 347ee824f4bSOmkar Kulkarni #define DCBX_ETS_TSA_CBS 1 348ee824f4bSOmkar Kulkarni #define DCBX_ETS_TSA_ETS 2 349ee824f4bSOmkar Kulkarni }; 350ee824f4bSOmkar Kulkarni 351ee824f4bSOmkar Kulkarni #define DCBX_TCP_OOO_TC (4) 352ee824f4bSOmkar Kulkarni #define DCBX_TCP_OOO_K2_4PORT_TC (3) 353ee824f4bSOmkar Kulkarni 354ee824f4bSOmkar Kulkarni struct dcbx_app_priority_entry { 355ee824f4bSOmkar Kulkarni u32 entry; 356ee824f4bSOmkar Kulkarni #define DCBX_APP_PRI_MAP_MASK 0x000000ff 357ee824f4bSOmkar Kulkarni #define DCBX_APP_PRI_MAP_SHIFT 0 358ee824f4bSOmkar Kulkarni #define DCBX_APP_PRI_0 0x01 359ee824f4bSOmkar Kulkarni #define DCBX_APP_PRI_1 0x02 360ee824f4bSOmkar Kulkarni #define DCBX_APP_PRI_2 0x04 361ee824f4bSOmkar Kulkarni #define DCBX_APP_PRI_3 0x08 362ee824f4bSOmkar Kulkarni #define DCBX_APP_PRI_4 0x10 363ee824f4bSOmkar Kulkarni #define DCBX_APP_PRI_5 0x20 364ee824f4bSOmkar Kulkarni #define DCBX_APP_PRI_6 0x40 365ee824f4bSOmkar Kulkarni #define DCBX_APP_PRI_7 0x80 366ee824f4bSOmkar Kulkarni #define DCBX_APP_SF_MASK 0x00000300 367ee824f4bSOmkar Kulkarni #define DCBX_APP_SF_SHIFT 8 368ee824f4bSOmkar Kulkarni #define DCBX_APP_SF_ETHTYPE 0 369ee824f4bSOmkar Kulkarni #define DCBX_APP_SF_PORT 1 370ee824f4bSOmkar Kulkarni #define DCBX_APP_SF_IEEE_MASK 0x0000f000 371ee824f4bSOmkar Kulkarni #define DCBX_APP_SF_IEEE_SHIFT 12 372ee824f4bSOmkar Kulkarni #define DCBX_APP_SF_IEEE_RESERVED 0 373ee824f4bSOmkar Kulkarni #define DCBX_APP_SF_IEEE_ETHTYPE 1 374ee824f4bSOmkar Kulkarni #define DCBX_APP_SF_IEEE_TCP_PORT 2 375ee824f4bSOmkar Kulkarni #define DCBX_APP_SF_IEEE_UDP_PORT 3 376ee824f4bSOmkar Kulkarni #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 377ee824f4bSOmkar Kulkarni 378ee824f4bSOmkar Kulkarni #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 379ee824f4bSOmkar Kulkarni #define DCBX_APP_PROTOCOL_ID_SHIFT 16 380ee824f4bSOmkar Kulkarni }; 381ee824f4bSOmkar Kulkarni 382ee824f4bSOmkar Kulkarni struct dcbx_app_priority_feature { 383ee824f4bSOmkar Kulkarni u32 flags; 384ee824f4bSOmkar Kulkarni #define DCBX_APP_ENABLED_MASK 0x00000001 385ee824f4bSOmkar Kulkarni #define DCBX_APP_ENABLED_SHIFT 0 386ee824f4bSOmkar Kulkarni #define DCBX_APP_WILLING_MASK 0x00000002 387ee824f4bSOmkar Kulkarni #define DCBX_APP_WILLING_SHIFT 1 388ee824f4bSOmkar Kulkarni #define DCBX_APP_ERROR_MASK 0x00000004 389ee824f4bSOmkar Kulkarni #define DCBX_APP_ERROR_SHIFT 2 390ee824f4bSOmkar Kulkarni #define DCBX_APP_MAX_TCS_MASK 0x0000f000 391ee824f4bSOmkar Kulkarni #define DCBX_APP_MAX_TCS_SHIFT 12 392ee824f4bSOmkar Kulkarni #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 393ee824f4bSOmkar Kulkarni #define DCBX_APP_NUM_ENTRIES_SHIFT 16 394ee824f4bSOmkar Kulkarni struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 395ee824f4bSOmkar Kulkarni }; 396ee824f4bSOmkar Kulkarni 397ee824f4bSOmkar Kulkarni struct dcbx_features { 398ee824f4bSOmkar Kulkarni struct dcbx_ets_feature ets; 399ee824f4bSOmkar Kulkarni u32 pfc; 400ee824f4bSOmkar Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff 401ee824f4bSOmkar Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0 402ee824f4bSOmkar Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 403ee824f4bSOmkar Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 404ee824f4bSOmkar Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 405ee824f4bSOmkar Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 406ee824f4bSOmkar Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 407ee824f4bSOmkar Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 408ee824f4bSOmkar Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 409ee824f4bSOmkar Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 410ee824f4bSOmkar Kulkarni 411ee824f4bSOmkar Kulkarni #define DCBX_PFC_FLAGS_MASK 0x0000ff00 412ee824f4bSOmkar Kulkarni #define DCBX_PFC_FLAGS_SHIFT 8 413ee824f4bSOmkar Kulkarni #define DCBX_PFC_CAPS_MASK 0x00000f00 414ee824f4bSOmkar Kulkarni #define DCBX_PFC_CAPS_SHIFT 8 415ee824f4bSOmkar Kulkarni #define DCBX_PFC_MBC_MASK 0x00004000 416ee824f4bSOmkar Kulkarni #define DCBX_PFC_MBC_SHIFT 14 417ee824f4bSOmkar Kulkarni #define DCBX_PFC_WILLING_MASK 0x00008000 418ee824f4bSOmkar Kulkarni #define DCBX_PFC_WILLING_SHIFT 15 419ee824f4bSOmkar Kulkarni #define DCBX_PFC_ENABLED_MASK 0x00010000 420ee824f4bSOmkar Kulkarni #define DCBX_PFC_ENABLED_SHIFT 16 421ee824f4bSOmkar Kulkarni #define DCBX_PFC_ERROR_MASK 0x00020000 422ee824f4bSOmkar Kulkarni #define DCBX_PFC_ERROR_SHIFT 17 423ee824f4bSOmkar Kulkarni 424ee824f4bSOmkar Kulkarni struct dcbx_app_priority_feature app; 425ee824f4bSOmkar Kulkarni }; 426ee824f4bSOmkar Kulkarni 427ee824f4bSOmkar Kulkarni struct dcbx_local_params { 428ee824f4bSOmkar Kulkarni u32 config; 429ee824f4bSOmkar Kulkarni #define DCBX_CONFIG_VERSION_MASK 0x00000007 430ee824f4bSOmkar Kulkarni #define DCBX_CONFIG_VERSION_SHIFT 0 431ee824f4bSOmkar Kulkarni #define DCBX_CONFIG_VERSION_DISABLED 0 432ee824f4bSOmkar Kulkarni #define DCBX_CONFIG_VERSION_IEEE 1 433ee824f4bSOmkar Kulkarni #define DCBX_CONFIG_VERSION_CEE 2 434ee824f4bSOmkar Kulkarni #define DCBX_CONFIG_VERSION_STATIC 4 435ee824f4bSOmkar Kulkarni 436ee824f4bSOmkar Kulkarni u32 flags; 437ee824f4bSOmkar Kulkarni struct dcbx_features features; 438ee824f4bSOmkar Kulkarni }; 439ee824f4bSOmkar Kulkarni 440ee824f4bSOmkar Kulkarni struct dcbx_mib { 441ee824f4bSOmkar Kulkarni u32 prefix_seq_num; 442ee824f4bSOmkar Kulkarni u32 flags; 443ee824f4bSOmkar Kulkarni struct dcbx_features features; 444ee824f4bSOmkar Kulkarni u32 suffix_seq_num; 445ee824f4bSOmkar Kulkarni }; 446ee824f4bSOmkar Kulkarni 447ee824f4bSOmkar Kulkarni struct lldp_system_tlvs_buffer_s { 448f2a74107SPrabhakar Kushwaha u32 flags; 449f2a74107SPrabhakar Kushwaha #define LLDP_SYSTEM_TLV_VALID_MASK 0x1 450f2a74107SPrabhakar Kushwaha #define LLDP_SYSTEM_TLV_VALID_OFFSET 0 451f2a74107SPrabhakar Kushwaha #define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2 452f2a74107SPrabhakar Kushwaha #define LLDP_SYSTEM_TLV_MANDATORY_SHIFT 1 453f2a74107SPrabhakar Kushwaha #define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000 454f2a74107SPrabhakar Kushwaha #define LLDP_SYSTEM_TLV_LENGTH_SHIFT 16 455ee824f4bSOmkar Kulkarni u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; 456ee824f4bSOmkar Kulkarni }; 457ee824f4bSOmkar Kulkarni 458f2a74107SPrabhakar Kushwaha struct lldp_received_tlvs_s { 459f2a74107SPrabhakar Kushwaha u32 prefix_seq_num; 460f2a74107SPrabhakar Kushwaha u32 length; 461f2a74107SPrabhakar Kushwaha u32 tlvs_buffer[MAX_TLV_BUFFER]; 462f2a74107SPrabhakar Kushwaha u32 suffix_seq_num; 463f2a74107SPrabhakar Kushwaha }; 464f2a74107SPrabhakar Kushwaha 465ee824f4bSOmkar Kulkarni struct dcb_dscp_map { 466ee824f4bSOmkar Kulkarni u32 flags; 467ee824f4bSOmkar Kulkarni #define DCB_DSCP_ENABLE_MASK 0x1 468ee824f4bSOmkar Kulkarni #define DCB_DSCP_ENABLE_SHIFT 0 469ee824f4bSOmkar Kulkarni #define DCB_DSCP_ENABLE 1 470ee824f4bSOmkar Kulkarni u32 dscp_pri_map[8]; 471ee824f4bSOmkar Kulkarni }; 472ee824f4bSOmkar Kulkarni 473f2a74107SPrabhakar Kushwaha struct mcp_val64 { 474f2a74107SPrabhakar Kushwaha u32 lo; 475f2a74107SPrabhakar Kushwaha u32 hi; 476f2a74107SPrabhakar Kushwaha }; 477f2a74107SPrabhakar Kushwaha 478f2a74107SPrabhakar Kushwaha struct generic_idc_msg_s { 479f2a74107SPrabhakar Kushwaha u32 source_pf; 480f2a74107SPrabhakar Kushwaha struct mcp_val64 msg; 481f2a74107SPrabhakar Kushwaha }; 482f2a74107SPrabhakar Kushwaha 483f2a74107SPrabhakar Kushwaha struct pcie_stats_stc { 484f2a74107SPrabhakar Kushwaha u32 sr_cnt_wr_byte_msb; 485f2a74107SPrabhakar Kushwaha u32 sr_cnt_wr_byte_lsb; 486f2a74107SPrabhakar Kushwaha u32 sr_cnt_wr_cnt; 487f2a74107SPrabhakar Kushwaha u32 sr_cnt_rd_byte_msb; 488f2a74107SPrabhakar Kushwaha u32 sr_cnt_rd_byte_lsb; 489f2a74107SPrabhakar Kushwaha u32 sr_cnt_rd_cnt; 490f2a74107SPrabhakar Kushwaha }; 491f2a74107SPrabhakar Kushwaha 492f2a74107SPrabhakar Kushwaha enum _attribute_commands_e { 493f2a74107SPrabhakar Kushwaha ATTRIBUTE_CMD_READ = 0, 494f2a74107SPrabhakar Kushwaha ATTRIBUTE_CMD_WRITE, 495f2a74107SPrabhakar Kushwaha ATTRIBUTE_CMD_READ_CLEAR, 496f2a74107SPrabhakar Kushwaha ATTRIBUTE_CMD_CLEAR, 497f2a74107SPrabhakar Kushwaha ATTRIBUTE_NUM_OF_COMMANDS 498f2a74107SPrabhakar Kushwaha }; 499f2a74107SPrabhakar Kushwaha 500ee824f4bSOmkar Kulkarni struct public_global { 501ee824f4bSOmkar Kulkarni u32 max_path; 502ee824f4bSOmkar Kulkarni u32 max_ports; 503ee824f4bSOmkar Kulkarni #define MODE_1P 1 504ee824f4bSOmkar Kulkarni #define MODE_2P 2 505ee824f4bSOmkar Kulkarni #define MODE_3P 3 506ee824f4bSOmkar Kulkarni #define MODE_4P 4 507ee824f4bSOmkar Kulkarni u32 debug_mb_offset; 508ee824f4bSOmkar Kulkarni u32 phymod_dbg_mb_offset; 509ee824f4bSOmkar Kulkarni struct couple_mode_teaming cmt; 510ee824f4bSOmkar Kulkarni s32 internal_temperature; 511ee824f4bSOmkar Kulkarni u32 mfw_ver; 512ee824f4bSOmkar Kulkarni u32 running_bundle_id; 513ee824f4bSOmkar Kulkarni s32 external_temperature; 514ee824f4bSOmkar Kulkarni u32 mdump_reason; 515f2a74107SPrabhakar Kushwaha u32 ext_phy_upgrade_fw; 516f2a74107SPrabhakar Kushwaha u8 runtime_port_swap_map[MODE_4P]; 517ee824f4bSOmkar Kulkarni u32 data_ptr; 518ee824f4bSOmkar Kulkarni u32 data_size; 519f2a74107SPrabhakar Kushwaha u32 bmb_error_status_cnt; 520f2a74107SPrabhakar Kushwaha u32 bmb_jumbo_frame_cnt; 521f2a74107SPrabhakar Kushwaha u32 sent_to_bmc_cnt; 522f2a74107SPrabhakar Kushwaha u32 handled_by_mfw; 523f2a74107SPrabhakar Kushwaha u32 sent_to_nw_cnt; 524f2a74107SPrabhakar Kushwaha u32 to_bmc_kb_per_second; 525f2a74107SPrabhakar Kushwaha u32 bcast_dropped_to_bmc_cnt; 526f2a74107SPrabhakar Kushwaha u32 mcast_dropped_to_bmc_cnt; 527f2a74107SPrabhakar Kushwaha u32 ucast_dropped_to_bmc_cnt; 528f2a74107SPrabhakar Kushwaha u32 ncsi_response_failure_cnt; 529f2a74107SPrabhakar Kushwaha u32 device_attr; 530f2a74107SPrabhakar Kushwaha u32 vpd_warning; 531ee824f4bSOmkar Kulkarni }; 532ee824f4bSOmkar Kulkarni 533ee824f4bSOmkar Kulkarni struct fw_flr_mb { 534ee824f4bSOmkar Kulkarni u32 aggint; 535ee824f4bSOmkar Kulkarni u32 opgen_addr; 536ee824f4bSOmkar Kulkarni u32 accum_ack; 537ee824f4bSOmkar Kulkarni }; 538ee824f4bSOmkar Kulkarni 539ee824f4bSOmkar Kulkarni struct public_path { 540ee824f4bSOmkar Kulkarni struct fw_flr_mb flr_mb; 541ee824f4bSOmkar Kulkarni u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; 542ee824f4bSOmkar Kulkarni 543ee824f4bSOmkar Kulkarni u32 process_kill; 544ee824f4bSOmkar Kulkarni #define PROCESS_KILL_COUNTER_MASK 0x0000ffff 545ee824f4bSOmkar Kulkarni #define PROCESS_KILL_COUNTER_SHIFT 0 546ee824f4bSOmkar Kulkarni #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 547ee824f4bSOmkar Kulkarni #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16 548ee824f4bSOmkar Kulkarni #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) ((aeu_reg_id) * 32 + (aeu_bit)) 549ee824f4bSOmkar Kulkarni }; 550ee824f4bSOmkar Kulkarni 551f2a74107SPrabhakar Kushwaha #define FC_NPIV_WWPN_SIZE 8 552f2a74107SPrabhakar Kushwaha #define FC_NPIV_WWNN_SIZE 8 553f2a74107SPrabhakar Kushwaha struct dci_npiv_settings { 554f2a74107SPrabhakar Kushwaha u8 npiv_wwpn[FC_NPIV_WWPN_SIZE]; 555f2a74107SPrabhakar Kushwaha u8 npiv_wwnn[FC_NPIV_WWNN_SIZE]; 556f2a74107SPrabhakar Kushwaha }; 557f2a74107SPrabhakar Kushwaha 558f2a74107SPrabhakar Kushwaha struct dci_fc_npiv_cfg { 559f2a74107SPrabhakar Kushwaha /* hdr used internally by the MFW */ 560f2a74107SPrabhakar Kushwaha u32 hdr; 561f2a74107SPrabhakar Kushwaha u32 num_of_npiv; 562f2a74107SPrabhakar Kushwaha }; 563f2a74107SPrabhakar Kushwaha 564f2a74107SPrabhakar Kushwaha #define MAX_NUMBER_NPIV 64 565f2a74107SPrabhakar Kushwaha struct dci_fc_npiv_tbl { 566f2a74107SPrabhakar Kushwaha struct dci_fc_npiv_cfg fc_npiv_cfg; 567f2a74107SPrabhakar Kushwaha struct dci_npiv_settings settings[MAX_NUMBER_NPIV]; 568f2a74107SPrabhakar Kushwaha }; 569f2a74107SPrabhakar Kushwaha 570f2a74107SPrabhakar Kushwaha struct pause_flood_monitor { 571f2a74107SPrabhakar Kushwaha u8 period_cnt; 572f2a74107SPrabhakar Kushwaha u8 any_brb_prs_packet_hist; 573f2a74107SPrabhakar Kushwaha u8 any_brb_block_is_full_hist; 574f2a74107SPrabhakar Kushwaha u8 flags; 575f2a74107SPrabhakar Kushwaha u32 num_of_state_changes; 576f2a74107SPrabhakar Kushwaha }; 577f2a74107SPrabhakar Kushwaha 578ee824f4bSOmkar Kulkarni struct public_port { 579ee824f4bSOmkar Kulkarni u32 validity_map; 580ee824f4bSOmkar Kulkarni 581ee824f4bSOmkar Kulkarni u32 link_status; 582ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_UP 0x00000001 583ee824f4bSOmkar Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e 584ee824f4bSOmkar Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD BIT(1) 585ee824f4bSOmkar Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) 586ee824f4bSOmkar Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1) 587ee824f4bSOmkar Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1) 588ee824f4bSOmkar Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1) 589ee824f4bSOmkar Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1) 590ee824f4bSOmkar Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1) 591ee824f4bSOmkar Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1) 592ee824f4bSOmkar Kulkarni #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 593ee824f4bSOmkar Kulkarni #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 594ee824f4bSOmkar Kulkarni #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 595ee824f4bSOmkar Kulkarni #define LINK_STATUS_PFC_ENABLED 0x00000100 596ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 597ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 598ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 599ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 600ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 601ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 602ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 603ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 604ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000c0000 605ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18) 606ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE BIT(18) 607ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18) 608ee824f4bSOmkar Kulkarni #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18) 609ee824f4bSOmkar Kulkarni #define LINK_STATUS_SFP_TX_FAULT 0x00100000 610ee824f4bSOmkar Kulkarni #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 611ee824f4bSOmkar Kulkarni #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 612ee824f4bSOmkar Kulkarni #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 613ee824f4bSOmkar Kulkarni #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 614ee824f4bSOmkar Kulkarni #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 615ee824f4bSOmkar Kulkarni #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 616ee824f4bSOmkar Kulkarni 617ee824f4bSOmkar Kulkarni #define LINK_STATUS_FEC_MODE_MASK 0x38000000 618ee824f4bSOmkar Kulkarni #define LINK_STATUS_FEC_MODE_NONE (0 << 27) 619ee824f4bSOmkar Kulkarni #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 BIT(27) 620ee824f4bSOmkar Kulkarni #define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27) 621f2a74107SPrabhakar Kushwaha #define LINK_STATUS_EXT_PHY_LINK_UP BIT(30) 622ee824f4bSOmkar Kulkarni 623ee824f4bSOmkar Kulkarni u32 link_status1; 624ee824f4bSOmkar Kulkarni u32 ext_phy_fw_version; 625ee824f4bSOmkar Kulkarni u32 drv_phy_cfg_addr; 626ee824f4bSOmkar Kulkarni 627ee824f4bSOmkar Kulkarni u32 port_stx; 628ee824f4bSOmkar Kulkarni 629ee824f4bSOmkar Kulkarni u32 stat_nig_timer; 630ee824f4bSOmkar Kulkarni 631ee824f4bSOmkar Kulkarni struct port_mf_cfg port_mf_config; 632ee824f4bSOmkar Kulkarni struct port_stats stats; 633ee824f4bSOmkar Kulkarni 634ee824f4bSOmkar Kulkarni u32 media_type; 635ee824f4bSOmkar Kulkarni #define MEDIA_UNSPECIFIED 0x0 636ee824f4bSOmkar Kulkarni #define MEDIA_SFPP_10G_FIBER 0x1 637ee824f4bSOmkar Kulkarni #define MEDIA_XFP_FIBER 0x2 638ee824f4bSOmkar Kulkarni #define MEDIA_DA_TWINAX 0x3 639ee824f4bSOmkar Kulkarni #define MEDIA_BASE_T 0x4 640ee824f4bSOmkar Kulkarni #define MEDIA_SFP_1G_FIBER 0x5 641ee824f4bSOmkar Kulkarni #define MEDIA_MODULE_FIBER 0x6 642ee824f4bSOmkar Kulkarni #define MEDIA_KR 0xf0 643ee824f4bSOmkar Kulkarni #define MEDIA_NOT_PRESENT 0xff 644ee824f4bSOmkar Kulkarni 645ee824f4bSOmkar Kulkarni u32 lfa_status; 646ee824f4bSOmkar Kulkarni u32 link_change_count; 647ee824f4bSOmkar Kulkarni 648ee824f4bSOmkar Kulkarni struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; 649ee824f4bSOmkar Kulkarni struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; 650ee824f4bSOmkar Kulkarni struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; 651ee824f4bSOmkar Kulkarni 652ee824f4bSOmkar Kulkarni /* DCBX related MIB */ 653ee824f4bSOmkar Kulkarni struct dcbx_local_params local_admin_dcbx_mib; 654ee824f4bSOmkar Kulkarni struct dcbx_mib remote_dcbx_mib; 655ee824f4bSOmkar Kulkarni struct dcbx_mib operational_dcbx_mib; 656ee824f4bSOmkar Kulkarni 657f2a74107SPrabhakar Kushwaha u32 fc_npiv_nvram_tbl_addr; 658f2a74107SPrabhakar Kushwaha u32 fc_npiv_nvram_tbl_size; 659ee824f4bSOmkar Kulkarni 660ee824f4bSOmkar Kulkarni u32 transceiver_data; 661ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_STATE_MASK 0x000000ff 662ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000 663ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000 664ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 665ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 666ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 667ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 668f2a74107SPrabhakar Kushwaha #define ETH_TRANSCEIVER_STATE_IN_SETUP 0x10 669ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MASK 0x0000ff00 670ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_OFFSET 0x8 671ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_NONE 0x00 672ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xff 673ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 674ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 675ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03 676ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04 677ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05 678ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06 679ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07 680ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08 681ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 682ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a 683ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b 684ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c 685ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d 686ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e 687ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f 688ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10 689ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11 690ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12 691ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 692ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14 693ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15 694ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 695ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 696ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 697ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 698ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a 699ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b 700ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c 701ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d 702ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e 703ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f 704ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 705ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21 706ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22 707ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 708ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 709ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 710ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33 711ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34 712ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35 713ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36 714ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR 0x37 715ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR 0x38 716ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR 0x39 717ee824f4bSOmkar Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR 0x3a 718ee824f4bSOmkar Kulkarni 719ee824f4bSOmkar Kulkarni u32 wol_info; 720ee824f4bSOmkar Kulkarni u32 wol_pkt_len; 721ee824f4bSOmkar Kulkarni u32 wol_pkt_details; 722ee824f4bSOmkar Kulkarni struct dcb_dscp_map dcb_dscp_map; 723ee824f4bSOmkar Kulkarni 724ee824f4bSOmkar Kulkarni u32 eee_status; 725ee824f4bSOmkar Kulkarni #define EEE_ACTIVE_BIT BIT(0) 726ee824f4bSOmkar Kulkarni #define EEE_LD_ADV_STATUS_MASK 0x000000f0 727ee824f4bSOmkar Kulkarni #define EEE_LD_ADV_STATUS_OFFSET 4 728ee824f4bSOmkar Kulkarni #define EEE_1G_ADV BIT(1) 729ee824f4bSOmkar Kulkarni #define EEE_10G_ADV BIT(2) 730ee824f4bSOmkar Kulkarni #define EEE_LP_ADV_STATUS_MASK 0x00000f00 731ee824f4bSOmkar Kulkarni #define EEE_LP_ADV_STATUS_OFFSET 8 732ee824f4bSOmkar Kulkarni #define EEE_SUPPORTED_SPEED_MASK 0x0000f000 733ee824f4bSOmkar Kulkarni #define EEE_SUPPORTED_SPEED_OFFSET 12 734ee824f4bSOmkar Kulkarni #define EEE_1G_SUPPORTED BIT(1) 735ee824f4bSOmkar Kulkarni #define EEE_10G_SUPPORTED BIT(2) 736ee824f4bSOmkar Kulkarni 737ee824f4bSOmkar Kulkarni u32 eee_remote; 738ee824f4bSOmkar Kulkarni #define EEE_REMOTE_TW_TX_MASK 0x0000ffff 739ee824f4bSOmkar Kulkarni #define EEE_REMOTE_TW_TX_OFFSET 0 740ee824f4bSOmkar Kulkarni #define EEE_REMOTE_TW_RX_MASK 0xffff0000 741ee824f4bSOmkar Kulkarni #define EEE_REMOTE_TW_RX_OFFSET 16 742ee824f4bSOmkar Kulkarni 743f2a74107SPrabhakar Kushwaha u32 module_info; 744f2a74107SPrabhakar Kushwaha 745ee824f4bSOmkar Kulkarni u32 oem_cfg_port; 746ee824f4bSOmkar Kulkarni #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003 747ee824f4bSOmkar Kulkarni #define OEM_CFG_CHANNEL_TYPE_OFFSET 0 748ee824f4bSOmkar Kulkarni #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1 749ee824f4bSOmkar Kulkarni #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2 750ee824f4bSOmkar Kulkarni #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C 751ee824f4bSOmkar Kulkarni #define OEM_CFG_SCHED_TYPE_OFFSET 2 752ee824f4bSOmkar Kulkarni #define OEM_CFG_SCHED_TYPE_ETS 0x1 753ee824f4bSOmkar Kulkarni #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2 754f2a74107SPrabhakar Kushwaha 755f2a74107SPrabhakar Kushwaha struct lldp_received_tlvs_s lldp_received_tlvs[LLDP_MAX_LLDP_AGENTS]; 756f2a74107SPrabhakar Kushwaha u32 system_lldp_tlvs_buf2[MAX_SYSTEM_LLDP_TLV_DATA]; 757f2a74107SPrabhakar Kushwaha u32 phy_module_temperature; 758f2a74107SPrabhakar Kushwaha u32 nig_reg_stat_rx_bmb_packet; 759f2a74107SPrabhakar Kushwaha u32 nig_reg_rx_llh_ncsi_mcp_mask; 760f2a74107SPrabhakar Kushwaha u32 nig_reg_rx_llh_ncsi_mcp_mask_2; 761f2a74107SPrabhakar Kushwaha struct pause_flood_monitor pause_flood_monitor; 762f2a74107SPrabhakar Kushwaha u32 nig_drain_cnt; 763f2a74107SPrabhakar Kushwaha struct pkt_type_cnt pkt_tc_priority_cnt; 764f2a74107SPrabhakar Kushwaha }; 765f2a74107SPrabhakar Kushwaha 766f2a74107SPrabhakar Kushwaha #define MCP_DRV_VER_STR_SIZE 16 767f2a74107SPrabhakar Kushwaha #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) 768f2a74107SPrabhakar Kushwaha #define MCP_DRV_NVM_BUF_LEN 32 769f2a74107SPrabhakar Kushwaha struct drv_version_stc { 770f2a74107SPrabhakar Kushwaha u32 version; 771f2a74107SPrabhakar Kushwaha u8 name[MCP_DRV_VER_STR_SIZE - 4]; 772ee824f4bSOmkar Kulkarni }; 773ee824f4bSOmkar Kulkarni 774ee824f4bSOmkar Kulkarni struct public_func { 775f2a74107SPrabhakar Kushwaha u32 iscsi_boot_signature; 776f2a74107SPrabhakar Kushwaha u32 iscsi_boot_block_offset; 777ee824f4bSOmkar Kulkarni 778ee824f4bSOmkar Kulkarni u32 mtu_size; 779ee824f4bSOmkar Kulkarni 780f2a74107SPrabhakar Kushwaha u32 c2s_pcp_map_lower; 781f2a74107SPrabhakar Kushwaha u32 c2s_pcp_map_upper; 782f2a74107SPrabhakar Kushwaha u32 c2s_pcp_map_default; 783f2a74107SPrabhakar Kushwaha 784f2a74107SPrabhakar Kushwaha struct generic_idc_msg_s generic_idc_msg; 785f2a74107SPrabhakar Kushwaha 786f2a74107SPrabhakar Kushwaha u32 num_of_msix; 787ee824f4bSOmkar Kulkarni 788ee824f4bSOmkar Kulkarni u32 config; 789ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 790ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 791ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001 792ee824f4bSOmkar Kulkarni 793ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 794ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_PROTOCOL_SHIFT 4 795ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 796ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 797ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 798ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 799f2a74107SPrabhakar Kushwaha #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 800ee824f4bSOmkar Kulkarni 801ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 802ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_MIN_BW_SHIFT 8 803ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 804ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 805ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_MAX_BW_SHIFT 16 806ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 807ee824f4bSOmkar Kulkarni 808ee824f4bSOmkar Kulkarni u32 status; 809ee824f4bSOmkar Kulkarni #define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001 810ee824f4bSOmkar Kulkarni 811ee824f4bSOmkar Kulkarni u32 mac_upper; 812ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 813ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 814ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 815ee824f4bSOmkar Kulkarni u32 mac_lower; 816ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 817ee824f4bSOmkar Kulkarni 818ee824f4bSOmkar Kulkarni u32 fcoe_wwn_port_name_upper; 819ee824f4bSOmkar Kulkarni u32 fcoe_wwn_port_name_lower; 820ee824f4bSOmkar Kulkarni 821ee824f4bSOmkar Kulkarni u32 fcoe_wwn_node_name_upper; 822ee824f4bSOmkar Kulkarni u32 fcoe_wwn_node_name_lower; 823ee824f4bSOmkar Kulkarni 824ee824f4bSOmkar Kulkarni u32 ovlan_stag; 825ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff 826ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_OV_STAG_SHIFT 0 827ee824f4bSOmkar Kulkarni #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK 828ee824f4bSOmkar Kulkarni 829ee824f4bSOmkar Kulkarni u32 pf_allocation; 830ee824f4bSOmkar Kulkarni 831ee824f4bSOmkar Kulkarni u32 preserve_data; 832ee824f4bSOmkar Kulkarni 833ee824f4bSOmkar Kulkarni u32 driver_last_activity_ts; 834ee824f4bSOmkar Kulkarni 835ee824f4bSOmkar Kulkarni u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; 836ee824f4bSOmkar Kulkarni 837ee824f4bSOmkar Kulkarni u32 drv_id; 838ee824f4bSOmkar Kulkarni #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff 839ee824f4bSOmkar Kulkarni #define DRV_ID_PDA_COMP_VER_SHIFT 0 840ee824f4bSOmkar Kulkarni 841ee824f4bSOmkar Kulkarni #define LOAD_REQ_HSI_VERSION 2 842ee824f4bSOmkar Kulkarni #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 843ee824f4bSOmkar Kulkarni #define DRV_ID_MCP_HSI_VER_SHIFT 16 844ee824f4bSOmkar Kulkarni #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \ 845ee824f4bSOmkar Kulkarni DRV_ID_MCP_HSI_VER_SHIFT) 846ee824f4bSOmkar Kulkarni 847ee824f4bSOmkar Kulkarni #define DRV_ID_DRV_TYPE_MASK 0x7f000000 848ee824f4bSOmkar Kulkarni #define DRV_ID_DRV_TYPE_SHIFT 24 849ee824f4bSOmkar Kulkarni #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT) 850ee824f4bSOmkar Kulkarni #define DRV_ID_DRV_TYPE_LINUX BIT(DRV_ID_DRV_TYPE_SHIFT) 851ee824f4bSOmkar Kulkarni 852ee824f4bSOmkar Kulkarni #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 853ee824f4bSOmkar Kulkarni #define DRV_ID_DRV_INIT_HW_SHIFT 31 854ee824f4bSOmkar Kulkarni #define DRV_ID_DRV_INIT_HW_FLAG BIT(DRV_ID_DRV_INIT_HW_SHIFT) 855ee824f4bSOmkar Kulkarni 856ee824f4bSOmkar Kulkarni u32 oem_cfg_func; 857ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_TC_MASK 0x0000000F 858ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_TC_OFFSET 0 859ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_TC_0 0x0 860ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_TC_1 0x1 861ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_TC_2 0x2 862ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_TC_3 0x3 863ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_TC_4 0x4 864ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_TC_5 0x5 865ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_TC_6 0x6 866ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_TC_7 0x7 867ee824f4bSOmkar Kulkarni 868ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030 869ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4 870ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1 871ee824f4bSOmkar Kulkarni #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2 872f2a74107SPrabhakar Kushwaha 873f2a74107SPrabhakar Kushwaha struct drv_version_stc drv_ver; 874ee824f4bSOmkar Kulkarni }; 875ee824f4bSOmkar Kulkarni 876ee824f4bSOmkar Kulkarni struct mcp_mac { 877ee824f4bSOmkar Kulkarni u32 mac_upper; 878ee824f4bSOmkar Kulkarni u32 mac_lower; 879ee824f4bSOmkar Kulkarni }; 880ee824f4bSOmkar Kulkarni 881ee824f4bSOmkar Kulkarni struct mcp_file_att { 882ee824f4bSOmkar Kulkarni u32 nvm_start_addr; 883ee824f4bSOmkar Kulkarni u32 len; 884ee824f4bSOmkar Kulkarni }; 885ee824f4bSOmkar Kulkarni 886ee824f4bSOmkar Kulkarni struct bist_nvm_image_att { 887ee824f4bSOmkar Kulkarni u32 return_code; 888ee824f4bSOmkar Kulkarni u32 image_type; 889ee824f4bSOmkar Kulkarni u32 nvm_start_addr; 890ee824f4bSOmkar Kulkarni u32 len; 891ee824f4bSOmkar Kulkarni }; 892ee824f4bSOmkar Kulkarni 893ee824f4bSOmkar Kulkarni struct lan_stats_stc { 894ee824f4bSOmkar Kulkarni u64 ucast_rx_pkts; 895ee824f4bSOmkar Kulkarni u64 ucast_tx_pkts; 896ee824f4bSOmkar Kulkarni u32 fcs_err; 897ee824f4bSOmkar Kulkarni u32 rserved; 898ee824f4bSOmkar Kulkarni }; 899ee824f4bSOmkar Kulkarni 900ee824f4bSOmkar Kulkarni struct fcoe_stats_stc { 901ee824f4bSOmkar Kulkarni u64 rx_pkts; 902ee824f4bSOmkar Kulkarni u64 tx_pkts; 903ee824f4bSOmkar Kulkarni u32 fcs_err; 904ee824f4bSOmkar Kulkarni u32 login_failure; 905ee824f4bSOmkar Kulkarni }; 906ee824f4bSOmkar Kulkarni 907f2a74107SPrabhakar Kushwaha struct iscsi_stats_stc { 908f2a74107SPrabhakar Kushwaha u64 rx_pdus; 909f2a74107SPrabhakar Kushwaha u64 tx_pdus; 910f2a74107SPrabhakar Kushwaha u64 rx_bytes; 911f2a74107SPrabhakar Kushwaha u64 tx_bytes; 912f2a74107SPrabhakar Kushwaha }; 913f2a74107SPrabhakar Kushwaha 914f2a74107SPrabhakar Kushwaha struct rdma_stats_stc { 915f2a74107SPrabhakar Kushwaha u64 rx_pkts; 916f2a74107SPrabhakar Kushwaha u64 tx_pkts; 917f2a74107SPrabhakar Kushwaha u64 rx_bytes; 918f2a74107SPrabhakar Kushwaha u64 tx_bytes; 919f2a74107SPrabhakar Kushwaha }; 920f2a74107SPrabhakar Kushwaha 921ee824f4bSOmkar Kulkarni struct ocbb_data_stc { 922ee824f4bSOmkar Kulkarni u32 ocbb_host_addr; 923ee824f4bSOmkar Kulkarni u32 ocsd_host_addr; 924ee824f4bSOmkar Kulkarni u32 ocsd_req_update_interval; 925ee824f4bSOmkar Kulkarni }; 926ee824f4bSOmkar Kulkarni 927f2a74107SPrabhakar Kushwaha struct fcoe_cap_stc { 928f2a74107SPrabhakar Kushwaha u32 max_ios; 929f2a74107SPrabhakar Kushwaha u32 max_log; 930f2a74107SPrabhakar Kushwaha u32 max_exch; 931f2a74107SPrabhakar Kushwaha u32 max_npiv; 932f2a74107SPrabhakar Kushwaha u32 max_tgt; 933f2a74107SPrabhakar Kushwaha u32 max_outstnd; 934f2a74107SPrabhakar Kushwaha }; 935f2a74107SPrabhakar Kushwaha 936ee824f4bSOmkar Kulkarni #define MAX_NUM_OF_SENSORS 7 937ee824f4bSOmkar Kulkarni struct temperature_status_stc { 938ee824f4bSOmkar Kulkarni u32 num_of_sensors; 939ee824f4bSOmkar Kulkarni u32 sensor[MAX_NUM_OF_SENSORS]; 940ee824f4bSOmkar Kulkarni }; 941ee824f4bSOmkar Kulkarni 942ee824f4bSOmkar Kulkarni /* crash dump configuration header */ 943ee824f4bSOmkar Kulkarni struct mdump_config_stc { 944ee824f4bSOmkar Kulkarni u32 version; 945ee824f4bSOmkar Kulkarni u32 config; 946ee824f4bSOmkar Kulkarni u32 epoc; 947ee824f4bSOmkar Kulkarni u32 num_of_logs; 948ee824f4bSOmkar Kulkarni u32 valid_logs; 949ee824f4bSOmkar Kulkarni }; 950ee824f4bSOmkar Kulkarni 951ee824f4bSOmkar Kulkarni enum resource_id_enum { 952ee824f4bSOmkar Kulkarni RESOURCE_NUM_SB_E = 0, 953ee824f4bSOmkar Kulkarni RESOURCE_NUM_L2_QUEUE_E = 1, 954ee824f4bSOmkar Kulkarni RESOURCE_NUM_VPORT_E = 2, 955ee824f4bSOmkar Kulkarni RESOURCE_NUM_VMQ_E = 3, 956ee824f4bSOmkar Kulkarni RESOURCE_FACTOR_NUM_RSS_PF_E = 4, 957ee824f4bSOmkar Kulkarni RESOURCE_FACTOR_RSS_PER_VF_E = 5, 958ee824f4bSOmkar Kulkarni RESOURCE_NUM_RL_E = 6, 959ee824f4bSOmkar Kulkarni RESOURCE_NUM_PQ_E = 7, 960ee824f4bSOmkar Kulkarni RESOURCE_NUM_VF_E = 8, 961ee824f4bSOmkar Kulkarni RESOURCE_VFC_FILTER_E = 9, 962ee824f4bSOmkar Kulkarni RESOURCE_ILT_E = 10, 963ee824f4bSOmkar Kulkarni RESOURCE_CQS_E = 11, 964ee824f4bSOmkar Kulkarni RESOURCE_GFT_PROFILES_E = 12, 965ee824f4bSOmkar Kulkarni RESOURCE_NUM_TC_E = 13, 966ee824f4bSOmkar Kulkarni RESOURCE_NUM_RSS_ENGINES_E = 14, 967ee824f4bSOmkar Kulkarni RESOURCE_LL2_QUEUE_E = 15, 968ee824f4bSOmkar Kulkarni RESOURCE_RDMA_STATS_QUEUE_E = 16, 969ee824f4bSOmkar Kulkarni RESOURCE_BDQ_E = 17, 970ee824f4bSOmkar Kulkarni RESOURCE_QCN_E = 18, 971ee824f4bSOmkar Kulkarni RESOURCE_LLH_FILTER_E = 19, 972ee824f4bSOmkar Kulkarni RESOURCE_VF_MAC_ADDR = 20, 973ee824f4bSOmkar Kulkarni RESOURCE_LL2_CQS_E = 21, 974ee824f4bSOmkar Kulkarni RESOURCE_VF_CNQS = 22, 975ee824f4bSOmkar Kulkarni RESOURCE_MAX_NUM, 976ee824f4bSOmkar Kulkarni RESOURCE_NUM_INVALID = 0xFFFFFFFF 977ee824f4bSOmkar Kulkarni }; 978ee824f4bSOmkar Kulkarni 979ee824f4bSOmkar Kulkarni /* Resource ID is to be filled by the driver in the MB request 980ee824f4bSOmkar Kulkarni * Size, offset & flags to be filled by the MFW in the MB response 981ee824f4bSOmkar Kulkarni */ 982ee824f4bSOmkar Kulkarni struct resource_info { 983ee824f4bSOmkar Kulkarni enum resource_id_enum res_id; 984ee824f4bSOmkar Kulkarni u32 size; /* number of allocated resources */ 985ee824f4bSOmkar Kulkarni u32 offset; /* Offset of the 1st resource */ 986ee824f4bSOmkar Kulkarni u32 vf_size; 987ee824f4bSOmkar Kulkarni u32 vf_offset; 988ee824f4bSOmkar Kulkarni u32 flags; 989ee824f4bSOmkar Kulkarni #define RESOURCE_ELEMENT_STRICT BIT(0) 990ee824f4bSOmkar Kulkarni }; 991ee824f4bSOmkar Kulkarni 992f2a74107SPrabhakar Kushwaha struct mcp_wwn { 993f2a74107SPrabhakar Kushwaha u32 wwn_upper; 994f2a74107SPrabhakar Kushwaha u32 wwn_lower; 995f2a74107SPrabhakar Kushwaha }; 996f2a74107SPrabhakar Kushwaha 997ee824f4bSOmkar Kulkarni #define DRV_ROLE_NONE 0 998ee824f4bSOmkar Kulkarni #define DRV_ROLE_PREBOOT 1 999ee824f4bSOmkar Kulkarni #define DRV_ROLE_OS 2 1000ee824f4bSOmkar Kulkarni #define DRV_ROLE_KDUMP 3 1001ee824f4bSOmkar Kulkarni 1002ee824f4bSOmkar Kulkarni struct load_req_stc { 1003ee824f4bSOmkar Kulkarni u32 drv_ver_0; 1004ee824f4bSOmkar Kulkarni u32 drv_ver_1; 1005ee824f4bSOmkar Kulkarni u32 fw_ver; 1006ee824f4bSOmkar Kulkarni u32 misc0; 1007ee824f4bSOmkar Kulkarni #define LOAD_REQ_ROLE_MASK 0x000000FF 1008ee824f4bSOmkar Kulkarni #define LOAD_REQ_ROLE_SHIFT 0 1009ee824f4bSOmkar Kulkarni #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 1010ee824f4bSOmkar Kulkarni #define LOAD_REQ_LOCK_TO_SHIFT 8 1011ee824f4bSOmkar Kulkarni #define LOAD_REQ_LOCK_TO_DEFAULT 0 1012ee824f4bSOmkar Kulkarni #define LOAD_REQ_LOCK_TO_NONE 255 1013ee824f4bSOmkar Kulkarni #define LOAD_REQ_FORCE_MASK 0x000F0000 1014ee824f4bSOmkar Kulkarni #define LOAD_REQ_FORCE_SHIFT 16 1015ee824f4bSOmkar Kulkarni #define LOAD_REQ_FORCE_NONE 0 1016ee824f4bSOmkar Kulkarni #define LOAD_REQ_FORCE_PF 1 1017ee824f4bSOmkar Kulkarni #define LOAD_REQ_FORCE_ALL 2 1018ee824f4bSOmkar Kulkarni #define LOAD_REQ_FLAGS0_MASK 0x00F00000 1019ee824f4bSOmkar Kulkarni #define LOAD_REQ_FLAGS0_SHIFT 20 1020ee824f4bSOmkar Kulkarni #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) 1021ee824f4bSOmkar Kulkarni }; 1022ee824f4bSOmkar Kulkarni 1023ee824f4bSOmkar Kulkarni struct load_rsp_stc { 1024ee824f4bSOmkar Kulkarni u32 drv_ver_0; 1025ee824f4bSOmkar Kulkarni u32 drv_ver_1; 1026ee824f4bSOmkar Kulkarni u32 fw_ver; 1027ee824f4bSOmkar Kulkarni u32 misc0; 1028ee824f4bSOmkar Kulkarni #define LOAD_RSP_ROLE_MASK 0x000000FF 1029ee824f4bSOmkar Kulkarni #define LOAD_RSP_ROLE_SHIFT 0 1030ee824f4bSOmkar Kulkarni #define LOAD_RSP_HSI_MASK 0x0000FF00 1031ee824f4bSOmkar Kulkarni #define LOAD_RSP_HSI_SHIFT 8 1032ee824f4bSOmkar Kulkarni #define LOAD_RSP_FLAGS0_MASK 0x000F0000 1033ee824f4bSOmkar Kulkarni #define LOAD_RSP_FLAGS0_SHIFT 16 1034ee824f4bSOmkar Kulkarni #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) 1035ee824f4bSOmkar Kulkarni }; 1036ee824f4bSOmkar Kulkarni 1037ee824f4bSOmkar Kulkarni struct mdump_retain_data_stc { 1038ee824f4bSOmkar Kulkarni u32 valid; 1039ee824f4bSOmkar Kulkarni u32 epoch; 1040ee824f4bSOmkar Kulkarni u32 pf; 1041ee824f4bSOmkar Kulkarni u32 status; 1042ee824f4bSOmkar Kulkarni }; 1043ee824f4bSOmkar Kulkarni 1044f2a74107SPrabhakar Kushwaha struct attribute_cmd_write_stc { 1045f2a74107SPrabhakar Kushwaha u32 val; 1046f2a74107SPrabhakar Kushwaha u32 mask; 1047f2a74107SPrabhakar Kushwaha u32 offset; 1048f2a74107SPrabhakar Kushwaha }; 1049f2a74107SPrabhakar Kushwaha 1050f2a74107SPrabhakar Kushwaha struct lldp_stats_stc { 1051f2a74107SPrabhakar Kushwaha u32 tx_frames_total; 1052f2a74107SPrabhakar Kushwaha u32 rx_frames_total; 1053f2a74107SPrabhakar Kushwaha u32 rx_frames_discarded; 1054f2a74107SPrabhakar Kushwaha u32 rx_age_outs; 1055f2a74107SPrabhakar Kushwaha }; 1056f2a74107SPrabhakar Kushwaha 1057f2a74107SPrabhakar Kushwaha struct get_att_ctrl_stc { 1058f2a74107SPrabhakar Kushwaha u32 disabled_attns; 1059f2a74107SPrabhakar Kushwaha u32 controllable_attns; 1060f2a74107SPrabhakar Kushwaha }; 1061f2a74107SPrabhakar Kushwaha 1062f2a74107SPrabhakar Kushwaha struct trace_filter_stc { 1063f2a74107SPrabhakar Kushwaha u32 level; 1064f2a74107SPrabhakar Kushwaha u32 modules; 1065f2a74107SPrabhakar Kushwaha }; 1066f2a74107SPrabhakar Kushwaha 1067ee824f4bSOmkar Kulkarni union drv_union_data { 1068ee824f4bSOmkar Kulkarni struct mcp_mac wol_mac; 1069ee824f4bSOmkar Kulkarni 1070ee824f4bSOmkar Kulkarni struct eth_phy_cfg drv_phy_cfg; 1071ee824f4bSOmkar Kulkarni 1072ee824f4bSOmkar Kulkarni struct mcp_val64 val64; 1073ee824f4bSOmkar Kulkarni 1074ee824f4bSOmkar Kulkarni u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 1075ee824f4bSOmkar Kulkarni 1076ee824f4bSOmkar Kulkarni struct mcp_file_att file_att; 1077ee824f4bSOmkar Kulkarni 1078f2a74107SPrabhakar Kushwaha u32 ack_vf_disabled[EXT_VF_BITMAP_SIZE_IN_DWORDS]; 1079ee824f4bSOmkar Kulkarni 1080ee824f4bSOmkar Kulkarni struct drv_version_stc drv_version; 1081ee824f4bSOmkar Kulkarni 1082ee824f4bSOmkar Kulkarni struct lan_stats_stc lan_stats; 1083ee824f4bSOmkar Kulkarni struct fcoe_stats_stc fcoe_stats; 1084f2a74107SPrabhakar Kushwaha struct iscsi_stats_stc iscsi_stats; 1085f2a74107SPrabhakar Kushwaha struct rdma_stats_stc rdma_stats; 1086ee824f4bSOmkar Kulkarni struct ocbb_data_stc ocbb_info; 1087ee824f4bSOmkar Kulkarni struct temperature_status_stc temp_info; 1088ee824f4bSOmkar Kulkarni struct resource_info resource; 1089ee824f4bSOmkar Kulkarni struct bist_nvm_image_att nvm_image_att; 1090ee824f4bSOmkar Kulkarni struct mdump_config_stc mdump_config; 1091f2a74107SPrabhakar Kushwaha struct mcp_mac lldp_mac; 1092f2a74107SPrabhakar Kushwaha struct mcp_wwn fcoe_fabric_name; 1093f2a74107SPrabhakar Kushwaha u32 dword; 1094f2a74107SPrabhakar Kushwaha 1095f2a74107SPrabhakar Kushwaha struct load_req_stc load_req; 1096f2a74107SPrabhakar Kushwaha struct load_rsp_stc load_rsp; 1097f2a74107SPrabhakar Kushwaha struct mdump_retain_data_stc mdump_retain; 1098f2a74107SPrabhakar Kushwaha struct attribute_cmd_write_stc attribute_cmd_write; 1099f2a74107SPrabhakar Kushwaha struct lldp_stats_stc lldp_stats; 1100f2a74107SPrabhakar Kushwaha struct pcie_stats_stc pcie_stats; 1101f2a74107SPrabhakar Kushwaha 1102f2a74107SPrabhakar Kushwaha struct get_att_ctrl_stc get_att_ctrl; 1103f2a74107SPrabhakar Kushwaha struct fcoe_cap_stc fcoe_cap; 1104f2a74107SPrabhakar Kushwaha struct trace_filter_stc trace_filter; 1105ee824f4bSOmkar Kulkarni }; 1106ee824f4bSOmkar Kulkarni 1107ee824f4bSOmkar Kulkarni struct public_drv_mb { 1108ee824f4bSOmkar Kulkarni u32 drv_mb_header; 1109f2a74107SPrabhakar Kushwaha #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1110f2a74107SPrabhakar Kushwaha #define DRV_MSG_SEQ_NUMBER_OFFSET 0 1111ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_MASK 0xffff0000 1112f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_OFFSET 16 1113ee824f4bSOmkar Kulkarni 1114f2a74107SPrabhakar Kushwaha u32 drv_mb_param; 1115f2a74107SPrabhakar Kushwaha 1116f2a74107SPrabhakar Kushwaha u32 fw_mb_header; 1117f2a74107SPrabhakar Kushwaha #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1118f2a74107SPrabhakar Kushwaha #define FW_MSG_SEQ_NUMBER_OFFSET 0 1119f2a74107SPrabhakar Kushwaha #define FW_MSG_CODE_MASK 0xffff0000 1120f2a74107SPrabhakar Kushwaha #define FW_MSG_CODE_OFFSET 16 1121f2a74107SPrabhakar Kushwaha 1122f2a74107SPrabhakar Kushwaha u32 fw_mb_param; 1123f2a74107SPrabhakar Kushwaha 1124f2a74107SPrabhakar Kushwaha u32 drv_pulse_mb; 1125f2a74107SPrabhakar Kushwaha #define DRV_PULSE_SEQ_MASK 0x00007fff 1126f2a74107SPrabhakar Kushwaha #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1127f2a74107SPrabhakar Kushwaha #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1128f2a74107SPrabhakar Kushwaha 1129f2a74107SPrabhakar Kushwaha u32 mcp_pulse_mb; 1130f2a74107SPrabhakar Kushwaha #define MCP_PULSE_SEQ_MASK 0x00007fff 1131f2a74107SPrabhakar Kushwaha #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1132f2a74107SPrabhakar Kushwaha #define MCP_EVENT_MASK 0xffff0000 1133f2a74107SPrabhakar Kushwaha #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1134f2a74107SPrabhakar Kushwaha 1135f2a74107SPrabhakar Kushwaha union drv_union_data union_data; 1136f2a74107SPrabhakar Kushwaha }; 1137f2a74107SPrabhakar Kushwaha 1138f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE(_code_) ((_code_) << DRV_MSG_CODE_OFFSET) 1139f2a74107SPrabhakar Kushwaha enum drv_msg_code_enum { 1140f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_NVM_PUT_FILE_BEGIN = DRV_MSG_CODE(0x0001), 1141f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_NVM_PUT_FILE_DATA = DRV_MSG_CODE(0x0002), 1142f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_NVM_GET_FILE_ATT = DRV_MSG_CODE(0x0003), 1143f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_NVM_READ_NVRAM = DRV_MSG_CODE(0x0005), 1144f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_NVM_WRITE_NVRAM = DRV_MSG_CODE(0x0006), 1145f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_MCP_RESET = DRV_MSG_CODE(0x0009), 1146f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_SET_VERSION = DRV_MSG_CODE(0x000f), 1147f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_MCP_HALT = DRV_MSG_CODE(0x0010), 1148f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_SET_VMAC = DRV_MSG_CODE(0x0011), 1149f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_GET_VMAC = DRV_MSG_CODE(0x0012), 1150f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_GET_STATS = DRV_MSG_CODE(0x0013), 1151f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_TRANSCEIVER_READ = DRV_MSG_CODE(0x0016), 1152f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_MASK_PARITIES = DRV_MSG_CODE(0x001a), 1153f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_BIST_TEST = DRV_MSG_CODE(0x001e), 1154f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_SET_LED_MODE = DRV_MSG_CODE(0x0020), 1155f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_RESOURCE_CMD = DRV_MSG_CODE(0x0023), 1156f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_MDUMP_CMD = DRV_MSG_CODE(0x0025), 1157f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL = DRV_MSG_CODE(0x002b), 1158f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_OS_WOL = DRV_MSG_CODE(0x002e), 1159f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_GET_TLV_DONE = DRV_MSG_CODE(0x002f), 1160f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_FEATURE_SUPPORT = DRV_MSG_CODE(0x0030), 1161f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT = DRV_MSG_CODE(0x0031), 1162f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_GET_ENGINE_CONFIG = DRV_MSG_CODE(0x0037), 1163f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_GET_NVM_CFG_OPTION = DRV_MSG_CODE(0x003e), 1164f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_SET_NVM_CFG_OPTION = DRV_MSG_CODE(0x003f), 1165f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_INITIATE_PF_FLR = DRV_MSG_CODE(0x0201), 1166f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_LOAD_REQ = DRV_MSG_CODE(0x1000), 1167f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_LOAD_DONE = DRV_MSG_CODE(0x1100), 1168f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_INIT_HW = DRV_MSG_CODE(0x1200), 1169f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_CANCEL_LOAD_REQ = DRV_MSG_CODE(0x1300), 1170f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_UNLOAD_REQ = DRV_MSG_CODE(0x2000), 1171f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_UNLOAD_DONE = DRV_MSG_CODE(0x2100), 1172f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_INIT_PHY = DRV_MSG_CODE(0x2200), 1173f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_LINK_RESET = DRV_MSG_CODE(0x2300), 1174f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_SET_DCBX = DRV_MSG_CODE(0x2500), 1175f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_OV_UPDATE_CURR_CFG = DRV_MSG_CODE(0x2600), 1176f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_OV_UPDATE_BUS_NUM = DRV_MSG_CODE(0x2700), 1177f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS = DRV_MSG_CODE(0x2800), 1178f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER = DRV_MSG_CODE(0x2900), 1179f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_NIG_DRAIN = DRV_MSG_CODE(0x3000), 1180f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE = DRV_MSG_CODE(0x3100), 1181f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_BW_UPDATE_ACK = DRV_MSG_CODE(0x3200), 1182f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_OV_UPDATE_MTU = DRV_MSG_CODE(0x3300), 1183f2a74107SPrabhakar Kushwaha DRV_MSG_GET_RESOURCE_ALLOC_MSG = DRV_MSG_CODE(0x3400), 1184f2a74107SPrabhakar Kushwaha DRV_MSG_SET_RESOURCE_VALUE_MSG = DRV_MSG_CODE(0x3500), 1185f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_OV_UPDATE_WOL = DRV_MSG_CODE(0x3800), 1186f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE = DRV_MSG_CODE(0x3900), 1187f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_S_TAG_UPDATE_ACK = DRV_MSG_CODE(0x3b00), 1188f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_GET_OEM_UPDATES = DRV_MSG_CODE(0x4100), 1189f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_GET_PPFID_BITMAP = DRV_MSG_CODE(0x4300), 1190f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_VF_DISABLED_DONE = DRV_MSG_CODE(0xc000), 1191f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_CFG_VF_MSIX = DRV_MSG_CODE(0xc001), 1192f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_CFG_PF_VFS_MSIX = DRV_MSG_CODE(0xc002), 1193f2a74107SPrabhakar Kushwaha DRV_MSG_CODE_DEBUG_DATA_SEND = DRV_MSG_CODE(0xc004), 1194823163baSManish Chopra DRV_MSG_CODE_GET_MANAGEMENT_STATUS = DRV_MSG_CODE(0xc007), 1195f2a74107SPrabhakar Kushwaha }; 1196f2a74107SPrabhakar Kushwaha 1197ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4 1198ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 1199ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 1200ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 1201ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 1202ee824f4bSOmkar Kulkarni 1203f2a74107SPrabhakar Kushwaha /* DRV_MSG_CODE_RETAIN_VMAC parameters */ 1204f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_RETAIN_VMAC_FUNC_SHIFT 0 1205f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_RETAIN_VMAC_FUNC_MASK 0xf 1206f2a74107SPrabhakar Kushwaha 1207f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_SHIFT 4 1208f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_MASK 0x70 1209f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_L2 0 1210f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_ISCSI 1 1211f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_FCOE 2 1212f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_WWNN 3 1213f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_WWPN 4 1214f2a74107SPrabhakar Kushwaha 1215f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_MCP_RESET_FORCE 0xf04ce 1216f2a74107SPrabhakar Kushwaha 1217ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_STATS_TYPE_LAN 1 1218ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 1219ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 1220ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 1221ee824f4bSOmkar Kulkarni 1222f2a74107SPrabhakar Kushwaha #define BW_MAX_MASK 0x000000ff 1223f2a74107SPrabhakar Kushwaha #define BW_MAX_OFFSET 0 1224f2a74107SPrabhakar Kushwaha #define BW_MIN_MASK 0x0000ff00 1225f2a74107SPrabhakar Kushwaha #define BW_MIN_OFFSET 8 1226ee824f4bSOmkar Kulkarni 1227f2a74107SPrabhakar Kushwaha #define DRV_MSG_FAN_FAILURE_TYPE BIT(0) 1228f2a74107SPrabhakar Kushwaha #define DRV_MSG_TEMPERATURE_FAILURE_TYPE BIT(1) 1229ee824f4bSOmkar Kulkarni 1230ee824f4bSOmkar Kulkarni #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F 1231ee824f4bSOmkar Kulkarni #define RESOURCE_CMD_REQ_RESC_SHIFT 0 1232ee824f4bSOmkar Kulkarni #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 1233ee824f4bSOmkar Kulkarni #define RESOURCE_CMD_REQ_OPCODE_SHIFT 5 1234ee824f4bSOmkar Kulkarni #define RESOURCE_OPCODE_REQ 1 1235ee824f4bSOmkar Kulkarni #define RESOURCE_OPCODE_REQ_WO_AGING 2 1236ee824f4bSOmkar Kulkarni #define RESOURCE_OPCODE_REQ_W_AGING 3 1237ee824f4bSOmkar Kulkarni #define RESOURCE_OPCODE_RELEASE 4 1238ee824f4bSOmkar Kulkarni #define RESOURCE_OPCODE_FORCE_RELEASE 5 1239ee824f4bSOmkar Kulkarni #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 1240ee824f4bSOmkar Kulkarni #define RESOURCE_CMD_REQ_AGE_SHIFT 8 1241ee824f4bSOmkar Kulkarni 1242ee824f4bSOmkar Kulkarni #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF 1243ee824f4bSOmkar Kulkarni #define RESOURCE_CMD_RSP_OWNER_SHIFT 0 1244ee824f4bSOmkar Kulkarni #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 1245ee824f4bSOmkar Kulkarni #define RESOURCE_CMD_RSP_OPCODE_SHIFT 8 1246ee824f4bSOmkar Kulkarni #define RESOURCE_OPCODE_GNT 1 1247ee824f4bSOmkar Kulkarni #define RESOURCE_OPCODE_BUSY 2 1248ee824f4bSOmkar Kulkarni #define RESOURCE_OPCODE_RELEASED 3 1249ee824f4bSOmkar Kulkarni #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 1250ee824f4bSOmkar Kulkarni #define RESOURCE_OPCODE_WRONG_OWNER 5 1251ee824f4bSOmkar Kulkarni #define RESOURCE_OPCODE_UNKNOWN_CMD 255 1252ee824f4bSOmkar Kulkarni 1253ee824f4bSOmkar Kulkarni #define RESOURCE_DUMP 0 1254ee824f4bSOmkar Kulkarni 1255ee824f4bSOmkar Kulkarni /* DRV_MSG_CODE_MDUMP_CMD parameters */ 1256f2a74107SPrabhakar Kushwaha #define MDUMP_DRV_PARAM_OPCODE_MASK 0x000000ff 1257ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_MDUMP_ACK 0x01 1258ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 1259ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 1260ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 1261ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 1262ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 1263ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 1264ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 1265ee824f4bSOmkar Kulkarni 1266ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_HW_DUMP_TRIGGER 0x0a 1267ee824f4bSOmkar Kulkarni 1268f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_MDUMP_FREE_DRIVER_BUF 0x0b 1269f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_MDUMP_GEN_LINK_DUMP 0x0c 1270f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_MDUMP_GEN_IDLE_CHK 0x0d 1271ee824f4bSOmkar Kulkarni 1272f2a74107SPrabhakar Kushwaha /* DRV_MSG_CODE_MDUMP_CMD options */ 1273f2a74107SPrabhakar Kushwaha #define MDUMP_DRV_PARAM_OPTION_MASK 0x00000f00 1274f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_MDUMP_USE_DRIVER_BUF_OFFSET 8 1275f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_MDUMP_USE_DRIVER_BUF_MASK 0x100 1276ee824f4bSOmkar Kulkarni 1277f2a74107SPrabhakar Kushwaha /* DRV_MSG_CODE_EXT_PHY_READ/DRV_MSG_CODE_EXT_PHY_WRITE parameters */ 1278f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_ADDR_SHIFT 0 1279f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF 1280f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_DEVAD_SHIFT 16 1281f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000 1282f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_PORT_SHIFT 21 1283f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_PORT_MASK 0x00600000 1284f2a74107SPrabhakar Kushwaha 1285f2a74107SPrabhakar Kushwaha /* DRV_MSG_CODE_PMBUS_READ/DRV_MSG_CODE_PMBUS_WRITE parameters */ 1286f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_PMBUS_CMD_SHIFT 0 1287f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_PMBUS_CMD_MASK 0xFF 1288f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_PMBUS_LEN_SHIFT 8 1289f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_PMBUS_LEN_MASK 0x300 1290f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_PMBUS_DATA_SHIFT 16 1291f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_PMBUS_DATA_MASK 0xFFFF0000 1292f2a74107SPrabhakar Kushwaha 1293f2a74107SPrabhakar Kushwaha /* UNLOAD_REQ params */ 1294ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 1295ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 1296ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 1297ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 1298f2a74107SPrabhakar Kushwaha 1299f2a74107SPrabhakar Kushwaha /* UNLOAD_DONE_params */ 1300f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001 1301f2a74107SPrabhakar Kushwaha 1302f2a74107SPrabhakar Kushwaha /* INIT_PHY params */ 1303f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001 1304f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 1305f2a74107SPrabhakar Kushwaha 1306f2a74107SPrabhakar Kushwaha /* LLDP / DCBX params*/ 1307f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 1308f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0 1309f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 1310f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1 1311f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001 1312f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_SHIFT 0 1313f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0 1314f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_SHIFT 4 1315f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 1316ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3 1317f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_DCBX_ADMIN_CFG_NOTIFY_MASK 0x00000010 1318f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_DCBX_ADMIN_CFG_NOTIFY_SHIFT 4 1319f2a74107SPrabhakar Kushwaha 1320f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF 1321f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0 1322f2a74107SPrabhakar Kushwaha 1323f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_NVM_PUT_FILE_TYPE_MASK 0x000000ff 1324f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_NVM_PUT_FILE_TYPE_SHIFT 0 1325f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1 1326f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2 1327ee824f4bSOmkar Kulkarni 1328ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI 0x3 1329ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0 1330ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF 1331ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_LEN_OFFSET 24 1332ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 1333ee824f4bSOmkar Kulkarni 1334ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0 1335ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF 1336ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8 1337ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 1338ee824f4bSOmkar Kulkarni 1339ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0 1340ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F 1341ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 1342ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 1343ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 1344ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 1345ee824f4bSOmkar Kulkarni 1346ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0 1347ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF 1348ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 1349ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 1350ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 1351ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF 1352ee824f4bSOmkar Kulkarni 1353ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0 1354ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF 1355ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 1356ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 1357ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 1358ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 1359ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 1360ee824f4bSOmkar Kulkarni 1361ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0 1362ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF 1363ee824f4bSOmkar Kulkarni 1364ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \ 1365ee824f4bSOmkar Kulkarni DRV_MB_PARAM_WOL_DISABLED | \ 1366ee824f4bSOmkar Kulkarni DRV_MB_PARAM_WOL_ENABLED) 1367ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP 1368ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED 1369ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED 1370ee824f4bSOmkar Kulkarni 1371ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \ 1372ee824f4bSOmkar Kulkarni DRV_MB_PARAM_ESWITCH_MODE_VEB | \ 1373ee824f4bSOmkar Kulkarni DRV_MB_PARAM_ESWITCH_MODE_VEPA) 1374ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0 1375ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1 1376ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2 1377ee824f4bSOmkar Kulkarni 1378ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1 1379ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0 1380ee824f4bSOmkar Kulkarni 1381ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 1382ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 1383ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 1384ee824f4bSOmkar Kulkarni 1385ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0 1386ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 1387ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2 1388ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000fc 1389ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8 1390ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000ff00 1391ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16 1392ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xffff0000 1393ee824f4bSOmkar Kulkarni 1394ee824f4bSOmkar Kulkarni /* Resource Allocation params - Driver version support */ 1395ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000 1396ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 1397ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff 1398ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 1399ee824f4bSOmkar Kulkarni 1400f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0 1401ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 1402ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 1403ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 1404ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 1405ee824f4bSOmkar Kulkarni 1406ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 1407ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_RC_PASSED 1 1408ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_RC_FAILED 2 1409ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 1410ee824f4bSOmkar Kulkarni 1411ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0 1412ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000ff 1413ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8 1414ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000ff00 1415ee824f4bSOmkar Kulkarni 1416ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000ffff 1417ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0 1418f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 1419ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 1420ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL 0x00000004 1421ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EXT_SPEED_FEC_CONTROL 0x00000008 1422ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 1423ee824f4bSOmkar Kulkarni 1424ee824f4bSOmkar Kulkarni /* DRV_MSG_CODE_DEBUG_DATA_SEND parameters */ 1425ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET 0 1426ee824f4bSOmkar Kulkarni #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK 0xff 1427ee824f4bSOmkar Kulkarni 1428ee824f4bSOmkar Kulkarni /* Driver attributes params */ 1429ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0 1430ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00ffffff 1431ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24 1432ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xff000000 1433ee824f4bSOmkar Kulkarni 1434ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 0 1435ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000ffff 1436f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_IGNORE 0x0000ffff 1437f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 0 1438ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT 16 1439ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000 1440ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT 17 1441ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000 1442ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT 18 1443ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000 1444ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT 19 1445ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000 1446ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT 20 1447ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK 0x00100000 1448f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_NVM_CFG_OPTION_DEFAULT_RESTORE_ALL_SHIFT 21 1449f2a74107SPrabhakar Kushwaha #define DRV_MB_PARAM_NVM_CFG_OPTION_DEFAULT_RESTORE_ALL_MASK 0x00200000 1450ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT 24 1451ee824f4bSOmkar Kulkarni #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK 0x0f000000 1452ee824f4bSOmkar Kulkarni 1453f2a74107SPrabhakar Kushwaha /*DRV_MSG_CODE_GET_PERM_MAC parametres*/ 1454f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_SHIFT 0 1455f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_MASK 0xF 1456f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_PF 0 1457f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_BMC 1 1458f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_VF 2 1459f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_LLDP 3 1460f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_MAX 4 1461f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_GET_PERM_MAC_INDEX_SHIFT 8 1462f2a74107SPrabhakar Kushwaha #define DRV_MSG_CODE_GET_PERM_MAC_INDEX_MASK 0xFFFF00 1463ee824f4bSOmkar Kulkarni 1464f2a74107SPrabhakar Kushwaha #define FW_MSG_CODE(_code_) ((_code_) << FW_MSG_CODE_OFFSET) 1465f2a74107SPrabhakar Kushwaha enum fw_msg_code_enum { 1466f2a74107SPrabhakar Kushwaha FW_MSG_CODE_UNSUPPORTED = FW_MSG_CODE(0x0000), 1467f2a74107SPrabhakar Kushwaha FW_MSG_CODE_NVM_OK = FW_MSG_CODE(0x0001), 1468f2a74107SPrabhakar Kushwaha FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK = FW_MSG_CODE(0x0040), 1469f2a74107SPrabhakar Kushwaha FW_MSG_CODE_PHY_OK = FW_MSG_CODE(0x0011), 1470f2a74107SPrabhakar Kushwaha FW_MSG_CODE_OK = FW_MSG_CODE(0x0016), 1471f2a74107SPrabhakar Kushwaha FW_MSG_CODE_ERROR = FW_MSG_CODE(0x0017), 1472f2a74107SPrabhakar Kushwaha FW_MSG_CODE_TRANSCEIVER_DIAG_OK = FW_MSG_CODE(0x0016), 1473f2a74107SPrabhakar Kushwaha FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT = FW_MSG_CODE(0x0002), 1474f2a74107SPrabhakar Kushwaha FW_MSG_CODE_MDUMP_INVALID_CMD = FW_MSG_CODE(0x0003), 1475f2a74107SPrabhakar Kushwaha FW_MSG_CODE_OS_WOL_SUPPORTED = FW_MSG_CODE(0x0080), 1476f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE = FW_MSG_CODE(0x0087), 1477f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_LOAD_ENGINE = FW_MSG_CODE(0x1010), 1478f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_LOAD_PORT = FW_MSG_CODE(0x1011), 1479f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_LOAD_FUNCTION = FW_MSG_CODE(0x1012), 1480f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_LOAD_REFUSED_PDA = FW_MSG_CODE(0x1020), 1481f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 = FW_MSG_CODE(0x1021), 1482f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG = FW_MSG_CODE(0x1022), 1483f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_LOAD_REFUSED_HSI = FW_MSG_CODE(0x1023), 1484f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE = FW_MSG_CODE(0x1030), 1485f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT = FW_MSG_CODE(0x1031), 1486f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_LOAD_DONE = FW_MSG_CODE(0x1110), 1487f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_UNLOAD_ENGINE = FW_MSG_CODE(0x2011), 1488f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_UNLOAD_PORT = FW_MSG_CODE(0x2012), 1489f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_UNLOAD_FUNCTION = FW_MSG_CODE(0x2013), 1490f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_UNLOAD_DONE = FW_MSG_CODE(0x2110), 1491f2a74107SPrabhakar Kushwaha FW_MSG_CODE_RESOURCE_ALLOC_OK = FW_MSG_CODE(0x3400), 1492f2a74107SPrabhakar Kushwaha FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN = FW_MSG_CODE(0x3500), 1493f2a74107SPrabhakar Kushwaha FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE = FW_MSG_CODE(0x3b00), 1494f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE = FW_MSG_CODE(0xb001), 1495f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DEBUG_NOT_ENABLED = FW_MSG_CODE(0xb00a), 1496f2a74107SPrabhakar Kushwaha FW_MSG_CODE_DEBUG_DATA_SEND_OK = FW_MSG_CODE(0xb00b), 1497f2a74107SPrabhakar Kushwaha }; 1498ee824f4bSOmkar Kulkarni 1499ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000 1500ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 1501ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff 1502ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 1503ee824f4bSOmkar Kulkarni 1504ee824f4bSOmkar Kulkarni /* Get PF RDMA protocol command response */ 1505ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0 1506ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1 1507ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2 1508ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3 1509ee824f4bSOmkar Kulkarni 1510ee824f4bSOmkar Kulkarni /* Get MFW feature support response */ 1511ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ BIT(0) 1512ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_FEATURE_SUPPORT_EEE BIT(1) 1513f2a74107SPrabhakar Kushwaha #define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO BIT(2) 1514f2a74107SPrabhakar Kushwaha #define FW_MB_PARAM_FEATURE_SUPPORT_LP_PRES_DET BIT(3) 1515f2a74107SPrabhakar Kushwaha #define FW_MB_PARAM_FEATURE_SUPPORT_RELAXED_ORD BIT(4) 1516ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL BIT(5) 1517ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL BIT(6) 1518f2a74107SPrabhakar Kushwaha #define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP BIT(7) 1519f2a74107SPrabhakar Kushwaha #define FW_MB_PARAM_FEATURE_SUPPORT_VF_DPM BIT(8) 1520f2a74107SPrabhakar Kushwaha #define FW_MB_PARAM_FEATURE_SUPPORT_IDLE_CHK BIT(9) 1521ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK BIT(16) 1522f2a74107SPrabhakar Kushwaha #define FW_MB_PARAM_FEATURE_SUPPORT_DISABLE_LLDP BIT(17) 1523f2a74107SPrabhakar Kushwaha #define FW_MB_PARAM_FEATURE_SUPPORT_ENHANCED_SYS_LCK BIT(18) 1524f2a74107SPrabhakar Kushwaha #define FW_MB_PARAM_FEATURE_SUPPORT_RESTORE_DEFAULT_CFG BIT(19) 1525f2a74107SPrabhakar Kushwaha 1526f2a74107SPrabhakar Kushwaha #define FW_MB_PARAM_MANAGEMENT_STATUS_LOCKDOWN_ENABLED 0x00000001 1527ee824f4bSOmkar Kulkarni 1528ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR BIT(0) 1529ee824f4bSOmkar Kulkarni 1530ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001 1531ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT 0 1532ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002 1533ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_SHIFT 1 1534ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004 1535ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_SHIFT 2 1536ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008 1537ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT 3 1538ee824f4bSOmkar Kulkarni 1539ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_PPFID_BITMAP_MASK 0xff 1540ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_PPFID_BITMAP_SHIFT 0 1541ee824f4bSOmkar Kulkarni 1542ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK 0x00ffffff 1543ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT 0 1544ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK 0xff000000 1545ee824f4bSOmkar Kulkarni #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_SHIFT 24 1546ee824f4bSOmkar Kulkarni 1547ee824f4bSOmkar Kulkarni enum MFW_DRV_MSG_TYPE { 1548ee824f4bSOmkar Kulkarni MFW_DRV_MSG_LINK_CHANGE, 1549ee824f4bSOmkar Kulkarni MFW_DRV_MSG_FLR_FW_ACK_FAILED, 1550ee824f4bSOmkar Kulkarni MFW_DRV_MSG_VF_DISABLED, 1551ee824f4bSOmkar Kulkarni MFW_DRV_MSG_LLDP_DATA_UPDATED, 1552ee824f4bSOmkar Kulkarni MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, 1553ee824f4bSOmkar Kulkarni MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, 1554ee824f4bSOmkar Kulkarni MFW_DRV_MSG_ERROR_RECOVERY, 1555ee824f4bSOmkar Kulkarni MFW_DRV_MSG_BW_UPDATE, 1556ee824f4bSOmkar Kulkarni MFW_DRV_MSG_S_TAG_UPDATE, 1557ee824f4bSOmkar Kulkarni MFW_DRV_MSG_GET_LAN_STATS, 1558ee824f4bSOmkar Kulkarni MFW_DRV_MSG_GET_FCOE_STATS, 1559ee824f4bSOmkar Kulkarni MFW_DRV_MSG_GET_ISCSI_STATS, 1560ee824f4bSOmkar Kulkarni MFW_DRV_MSG_GET_RDMA_STATS, 1561ee824f4bSOmkar Kulkarni MFW_DRV_MSG_FAILURE_DETECTED, 1562ee824f4bSOmkar Kulkarni MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, 1563ee824f4bSOmkar Kulkarni MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, 1564f2a74107SPrabhakar Kushwaha MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE, 1565ee824f4bSOmkar Kulkarni MFW_DRV_MSG_GET_TLV_REQ, 1566ee824f4bSOmkar Kulkarni MFW_DRV_MSG_OEM_CFG_UPDATE, 1567f2a74107SPrabhakar Kushwaha MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED, 1568f2a74107SPrabhakar Kushwaha MFW_DRV_MSG_GENERIC_IDC, 1569f2a74107SPrabhakar Kushwaha MFW_DRV_MSG_XCVR_TX_FAULT, 1570f2a74107SPrabhakar Kushwaha MFW_DRV_MSG_XCVR_RX_LOS, 1571f2a74107SPrabhakar Kushwaha MFW_DRV_MSG_GET_FCOE_CAP, 1572f2a74107SPrabhakar Kushwaha MFW_DRV_MSG_GEN_LINK_DUMP, 1573f2a74107SPrabhakar Kushwaha MFW_DRV_MSG_GEN_IDLE_CHK, 1574f2a74107SPrabhakar Kushwaha MFW_DRV_MSG_DCBX_ADMIN_CFG_APPLIED, 1575ee824f4bSOmkar Kulkarni MFW_DRV_MSG_MAX 1576ee824f4bSOmkar Kulkarni }; 1577ee824f4bSOmkar Kulkarni 1578ee824f4bSOmkar Kulkarni #define MFW_DRV_MSG_MAX_DWORDS(msgs) ((((msgs) - 1) >> 2) + 1) 1579ee824f4bSOmkar Kulkarni #define MFW_DRV_MSG_DWORD(msg_id) ((msg_id) >> 2) 1580ee824f4bSOmkar Kulkarni #define MFW_DRV_MSG_OFFSET(msg_id) (((msg_id) & 0x3) << 3) 1581ee824f4bSOmkar Kulkarni #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) 1582ee824f4bSOmkar Kulkarni 1583ee824f4bSOmkar Kulkarni struct public_mfw_mb { 1584ee824f4bSOmkar Kulkarni u32 sup_msgs; 1585ee824f4bSOmkar Kulkarni u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1586ee824f4bSOmkar Kulkarni u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1587ee824f4bSOmkar Kulkarni }; 1588ee824f4bSOmkar Kulkarni 1589ee824f4bSOmkar Kulkarni enum public_sections { 1590ee824f4bSOmkar Kulkarni PUBLIC_DRV_MB, 1591ee824f4bSOmkar Kulkarni PUBLIC_MFW_MB, 1592ee824f4bSOmkar Kulkarni PUBLIC_GLOBAL, 1593ee824f4bSOmkar Kulkarni PUBLIC_PATH, 1594ee824f4bSOmkar Kulkarni PUBLIC_PORT, 1595ee824f4bSOmkar Kulkarni PUBLIC_FUNC, 1596ee824f4bSOmkar Kulkarni PUBLIC_MAX_SECTIONS 1597ee824f4bSOmkar Kulkarni }; 1598ee824f4bSOmkar Kulkarni 1599f2a74107SPrabhakar Kushwaha struct drv_ver_info_stc { 1600f2a74107SPrabhakar Kushwaha u32 ver; 1601f2a74107SPrabhakar Kushwaha u8 name[32]; 1602f2a74107SPrabhakar Kushwaha }; 1603f2a74107SPrabhakar Kushwaha 1604f2a74107SPrabhakar Kushwaha /* Runtime data needs about 1/2K. We use 2K to be on the safe side. 1605f2a74107SPrabhakar Kushwaha * Please make sure data does not exceed this size. 1606f2a74107SPrabhakar Kushwaha */ 1607f2a74107SPrabhakar Kushwaha #define NUM_RUNTIME_DWORDS 16 1608f2a74107SPrabhakar Kushwaha struct drv_init_hw_stc { 1609f2a74107SPrabhakar Kushwaha u32 init_hw_bitmask[NUM_RUNTIME_DWORDS]; 1610f2a74107SPrabhakar Kushwaha u32 init_hw_data[NUM_RUNTIME_DWORDS * 32]; 1611f2a74107SPrabhakar Kushwaha }; 1612f2a74107SPrabhakar Kushwaha 1613ee824f4bSOmkar Kulkarni struct mcp_public_data { 1614ee824f4bSOmkar Kulkarni u32 num_sections; 1615ee824f4bSOmkar Kulkarni u32 sections[PUBLIC_MAX_SECTIONS]; 1616ee824f4bSOmkar Kulkarni struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; 1617ee824f4bSOmkar Kulkarni struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; 1618ee824f4bSOmkar Kulkarni struct public_global global; 1619ee824f4bSOmkar Kulkarni struct public_path path[MCP_GLOB_PATH_MAX]; 1620ee824f4bSOmkar Kulkarni struct public_port port[MCP_GLOB_PORT_MAX]; 1621ee824f4bSOmkar Kulkarni struct public_func func[MCP_GLOB_FUNC_MAX]; 1622ee824f4bSOmkar Kulkarni }; 1623ee824f4bSOmkar Kulkarni 1624f2a74107SPrabhakar Kushwaha #define I2C_TRANSCEIVER_ADDR 0xa0 1625ee824f4bSOmkar Kulkarni #define MAX_I2C_TRANSACTION_SIZE 16 1626f2a74107SPrabhakar Kushwaha #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256 1627ee824f4bSOmkar Kulkarni 1628ee824f4bSOmkar Kulkarni /* OCBB definitions */ 1629ee824f4bSOmkar Kulkarni enum tlvs { 1630ee824f4bSOmkar Kulkarni /* Category 1: Device Properties */ 1631ee824f4bSOmkar Kulkarni DRV_TLV_CLP_STR, 1632ee824f4bSOmkar Kulkarni DRV_TLV_CLP_STR_CTD, 1633ee824f4bSOmkar Kulkarni /* Category 6: Device Configuration */ 1634ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_TO, 1635ee824f4bSOmkar Kulkarni DRV_TLV_R_T_TOV, 1636ee824f4bSOmkar Kulkarni DRV_TLV_R_A_TOV, 1637ee824f4bSOmkar Kulkarni DRV_TLV_E_D_TOV, 1638ee824f4bSOmkar Kulkarni DRV_TLV_CR_TOV, 1639ee824f4bSOmkar Kulkarni DRV_TLV_BOOT_TYPE, 1640ee824f4bSOmkar Kulkarni /* Category 8: Port Configuration */ 1641ee824f4bSOmkar Kulkarni DRV_TLV_NPIV_ENABLED, 1642ee824f4bSOmkar Kulkarni /* Category 10: Function Configuration */ 1643ee824f4bSOmkar Kulkarni DRV_TLV_FEATURE_FLAGS, 1644ee824f4bSOmkar Kulkarni DRV_TLV_LOCAL_ADMIN_ADDR, 1645ee824f4bSOmkar Kulkarni DRV_TLV_ADDITIONAL_MAC_ADDR_1, 1646ee824f4bSOmkar Kulkarni DRV_TLV_ADDITIONAL_MAC_ADDR_2, 1647ee824f4bSOmkar Kulkarni DRV_TLV_LSO_MAX_OFFLOAD_SIZE, 1648ee824f4bSOmkar Kulkarni DRV_TLV_LSO_MIN_SEGMENT_COUNT, 1649ee824f4bSOmkar Kulkarni DRV_TLV_PROMISCUOUS_MODE, 1650ee824f4bSOmkar Kulkarni DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE, 1651ee824f4bSOmkar Kulkarni DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE, 1652ee824f4bSOmkar Kulkarni DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG, 1653ee824f4bSOmkar Kulkarni DRV_TLV_FLEX_NIC_OUTER_VLAN_ID, 1654ee824f4bSOmkar Kulkarni DRV_TLV_OS_DRIVER_STATES, 1655ee824f4bSOmkar Kulkarni DRV_TLV_PXE_BOOT_PROGRESS, 1656ee824f4bSOmkar Kulkarni /* Category 12: FC/FCoE Configuration */ 1657ee824f4bSOmkar Kulkarni DRV_TLV_NPIV_STATE, 1658ee824f4bSOmkar Kulkarni DRV_TLV_NUM_OF_NPIV_IDS, 1659ee824f4bSOmkar Kulkarni DRV_TLV_SWITCH_NAME, 1660ee824f4bSOmkar Kulkarni DRV_TLV_SWITCH_PORT_NUM, 1661ee824f4bSOmkar Kulkarni DRV_TLV_SWITCH_PORT_ID, 1662ee824f4bSOmkar Kulkarni DRV_TLV_VENDOR_NAME, 1663ee824f4bSOmkar Kulkarni DRV_TLV_SWITCH_MODEL, 1664ee824f4bSOmkar Kulkarni DRV_TLV_SWITCH_FW_VER, 1665ee824f4bSOmkar Kulkarni DRV_TLV_QOS_PRIORITY_PER_802_1P, 1666ee824f4bSOmkar Kulkarni DRV_TLV_PORT_ALIAS, 1667ee824f4bSOmkar Kulkarni DRV_TLV_PORT_STATE, 1668ee824f4bSOmkar Kulkarni DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE, 1669ee824f4bSOmkar Kulkarni DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE, 1670ee824f4bSOmkar Kulkarni DRV_TLV_LINK_FAILURE_COUNT, 1671ee824f4bSOmkar Kulkarni DRV_TLV_FCOE_BOOT_PROGRESS, 1672ee824f4bSOmkar Kulkarni /* Category 13: iSCSI Configuration */ 1673ee824f4bSOmkar Kulkarni DRV_TLV_TARGET_LLMNR_ENABLED, 1674ee824f4bSOmkar Kulkarni DRV_TLV_HEADER_DIGEST_FLAG_ENABLED, 1675ee824f4bSOmkar Kulkarni DRV_TLV_DATA_DIGEST_FLAG_ENABLED, 1676ee824f4bSOmkar Kulkarni DRV_TLV_AUTHENTICATION_METHOD, 1677ee824f4bSOmkar Kulkarni DRV_TLV_ISCSI_BOOT_TARGET_PORTAL, 1678ee824f4bSOmkar Kulkarni DRV_TLV_MAX_FRAME_SIZE, 1679ee824f4bSOmkar Kulkarni DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE, 1680ee824f4bSOmkar Kulkarni DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE, 1681ee824f4bSOmkar Kulkarni DRV_TLV_ISCSI_BOOT_PROGRESS, 1682ee824f4bSOmkar Kulkarni /* Category 20: Device Data */ 1683ee824f4bSOmkar Kulkarni DRV_TLV_PCIE_BUS_RX_UTILIZATION, 1684ee824f4bSOmkar Kulkarni DRV_TLV_PCIE_BUS_TX_UTILIZATION, 1685ee824f4bSOmkar Kulkarni DRV_TLV_DEVICE_CPU_CORES_UTILIZATION, 1686ee824f4bSOmkar Kulkarni DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED, 1687ee824f4bSOmkar Kulkarni DRV_TLV_NCSI_RX_BYTES_RECEIVED, 1688ee824f4bSOmkar Kulkarni DRV_TLV_NCSI_TX_BYTES_SENT, 1689ee824f4bSOmkar Kulkarni /* Category 22: Base Port Data */ 1690ee824f4bSOmkar Kulkarni DRV_TLV_RX_DISCARDS, 1691ee824f4bSOmkar Kulkarni DRV_TLV_RX_ERRORS, 1692ee824f4bSOmkar Kulkarni DRV_TLV_TX_ERRORS, 1693ee824f4bSOmkar Kulkarni DRV_TLV_TX_DISCARDS, 1694ee824f4bSOmkar Kulkarni DRV_TLV_RX_FRAMES_RECEIVED, 1695ee824f4bSOmkar Kulkarni DRV_TLV_TX_FRAMES_SENT, 1696ee824f4bSOmkar Kulkarni /* Category 23: FC/FCoE Port Data */ 1697ee824f4bSOmkar Kulkarni DRV_TLV_RX_BROADCAST_PACKETS, 1698ee824f4bSOmkar Kulkarni DRV_TLV_TX_BROADCAST_PACKETS, 1699ee824f4bSOmkar Kulkarni /* Category 28: Base Function Data */ 1700ee824f4bSOmkar Kulkarni DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4, 1701ee824f4bSOmkar Kulkarni DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6, 1702ee824f4bSOmkar Kulkarni DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 1703ee824f4bSOmkar Kulkarni DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 1704ee824f4bSOmkar Kulkarni DRV_TLV_PF_RX_FRAMES_RECEIVED, 1705ee824f4bSOmkar Kulkarni DRV_TLV_RX_BYTES_RECEIVED, 1706ee824f4bSOmkar Kulkarni DRV_TLV_PF_TX_FRAMES_SENT, 1707ee824f4bSOmkar Kulkarni DRV_TLV_TX_BYTES_SENT, 1708ee824f4bSOmkar Kulkarni DRV_TLV_IOV_OFFLOAD, 1709ee824f4bSOmkar Kulkarni DRV_TLV_PCI_ERRORS_CAP_ID, 1710ee824f4bSOmkar Kulkarni DRV_TLV_UNCORRECTABLE_ERROR_STATUS, 1711ee824f4bSOmkar Kulkarni DRV_TLV_UNCORRECTABLE_ERROR_MASK, 1712ee824f4bSOmkar Kulkarni DRV_TLV_CORRECTABLE_ERROR_STATUS, 1713ee824f4bSOmkar Kulkarni DRV_TLV_CORRECTABLE_ERROR_MASK, 1714ee824f4bSOmkar Kulkarni DRV_TLV_PCI_ERRORS_AECC_REGISTER, 1715ee824f4bSOmkar Kulkarni DRV_TLV_TX_QUEUES_EMPTY, 1716ee824f4bSOmkar Kulkarni DRV_TLV_RX_QUEUES_EMPTY, 1717ee824f4bSOmkar Kulkarni DRV_TLV_TX_QUEUES_FULL, 1718ee824f4bSOmkar Kulkarni DRV_TLV_RX_QUEUES_FULL, 1719ee824f4bSOmkar Kulkarni /* Category 29: FC/FCoE Function Data */ 1720ee824f4bSOmkar Kulkarni DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 1721ee824f4bSOmkar Kulkarni DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 1722ee824f4bSOmkar Kulkarni DRV_TLV_FCOE_RX_FRAMES_RECEIVED, 1723ee824f4bSOmkar Kulkarni DRV_TLV_FCOE_RX_BYTES_RECEIVED, 1724ee824f4bSOmkar Kulkarni DRV_TLV_FCOE_TX_FRAMES_SENT, 1725ee824f4bSOmkar Kulkarni DRV_TLV_FCOE_TX_BYTES_SENT, 1726ee824f4bSOmkar Kulkarni DRV_TLV_CRC_ERROR_COUNT, 1727ee824f4bSOmkar Kulkarni DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID, 1728ee824f4bSOmkar Kulkarni DRV_TLV_CRC_ERROR_1_TIMESTAMP, 1729ee824f4bSOmkar Kulkarni DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID, 1730ee824f4bSOmkar Kulkarni DRV_TLV_CRC_ERROR_2_TIMESTAMP, 1731ee824f4bSOmkar Kulkarni DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID, 1732ee824f4bSOmkar Kulkarni DRV_TLV_CRC_ERROR_3_TIMESTAMP, 1733ee824f4bSOmkar Kulkarni DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID, 1734ee824f4bSOmkar Kulkarni DRV_TLV_CRC_ERROR_4_TIMESTAMP, 1735ee824f4bSOmkar Kulkarni DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID, 1736ee824f4bSOmkar Kulkarni DRV_TLV_CRC_ERROR_5_TIMESTAMP, 1737ee824f4bSOmkar Kulkarni DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT, 1738ee824f4bSOmkar Kulkarni DRV_TLV_LOSS_OF_SIGNAL_ERRORS, 1739ee824f4bSOmkar Kulkarni DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT, 1740ee824f4bSOmkar Kulkarni DRV_TLV_DISPARITY_ERROR_COUNT, 1741ee824f4bSOmkar Kulkarni DRV_TLV_CODE_VIOLATION_ERROR_COUNT, 1742ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1, 1743ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2, 1744ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3, 1745ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4, 1746ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_TIMESTAMP, 1747ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1, 1748ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2, 1749ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3, 1750ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4, 1751ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP, 1752ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_RJT, 1753ee824f4bSOmkar Kulkarni DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP, 1754ee824f4bSOmkar Kulkarni DRV_TLV_FDISCS_SENT_COUNT, 1755ee824f4bSOmkar Kulkarni DRV_TLV_FDISC_ACCS_RECEIVED, 1756ee824f4bSOmkar Kulkarni DRV_TLV_FDISC_RJTS_RECEIVED, 1757ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_SENT_COUNT, 1758ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_ACCS_RECEIVED, 1759ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_RJTS_RECEIVED, 1760ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID, 1761ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_1_TIMESTAMP, 1762ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID, 1763ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_2_TIMESTAMP, 1764ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID, 1765ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_3_TIMESTAMP, 1766ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID, 1767ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_4_TIMESTAMP, 1768ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID, 1769ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_5_TIMESTAMP, 1770ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID, 1771ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_1_ACC_TIMESTAMP, 1772ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID, 1773ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_2_ACC_TIMESTAMP, 1774ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID, 1775ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_3_ACC_TIMESTAMP, 1776ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID, 1777ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_4_ACC_TIMESTAMP, 1778ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID, 1779ee824f4bSOmkar Kulkarni DRV_TLV_PLOGI_5_ACC_TIMESTAMP, 1780ee824f4bSOmkar Kulkarni DRV_TLV_LOGOS_ISSUED, 1781ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_ACCS_RECEIVED, 1782ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_RJTS_RECEIVED, 1783ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID, 1784ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_1_TIMESTAMP, 1785ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID, 1786ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_2_TIMESTAMP, 1787ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID, 1788ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_3_TIMESTAMP, 1789ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID, 1790ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_4_TIMESTAMP, 1791ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID, 1792ee824f4bSOmkar Kulkarni DRV_TLV_LOGO_5_TIMESTAMP, 1793ee824f4bSOmkar Kulkarni DRV_TLV_LOGOS_RECEIVED, 1794ee824f4bSOmkar Kulkarni DRV_TLV_ACCS_ISSUED, 1795ee824f4bSOmkar Kulkarni DRV_TLV_PRLIS_ISSUED, 1796ee824f4bSOmkar Kulkarni DRV_TLV_ACCS_RECEIVED, 1797ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_SENT_COUNT, 1798ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_ACCS_RECEIVED, 1799ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_RJTS_RECEIVED, 1800ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID, 1801ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_1_TIMESTAMP, 1802ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID, 1803ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_2_TIMESTAMP, 1804ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID, 1805ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_3_TIMESTAMP, 1806ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID, 1807ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_4_TIMESTAMP, 1808ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID, 1809ee824f4bSOmkar Kulkarni DRV_TLV_ABTS_5_TIMESTAMP, 1810ee824f4bSOmkar Kulkarni DRV_TLV_RSCNS_RECEIVED, 1811ee824f4bSOmkar Kulkarni DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1, 1812ee824f4bSOmkar Kulkarni DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2, 1813ee824f4bSOmkar Kulkarni DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3, 1814ee824f4bSOmkar Kulkarni DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4, 1815ee824f4bSOmkar Kulkarni DRV_TLV_LUN_RESETS_ISSUED, 1816ee824f4bSOmkar Kulkarni DRV_TLV_ABORT_TASK_SETS_ISSUED, 1817ee824f4bSOmkar Kulkarni DRV_TLV_TPRLOS_SENT, 1818ee824f4bSOmkar Kulkarni DRV_TLV_NOS_SENT_COUNT, 1819ee824f4bSOmkar Kulkarni DRV_TLV_NOS_RECEIVED_COUNT, 1820ee824f4bSOmkar Kulkarni DRV_TLV_OLS_COUNT, 1821ee824f4bSOmkar Kulkarni DRV_TLV_LR_COUNT, 1822ee824f4bSOmkar Kulkarni DRV_TLV_LRR_COUNT, 1823ee824f4bSOmkar Kulkarni DRV_TLV_LIP_SENT_COUNT, 1824ee824f4bSOmkar Kulkarni DRV_TLV_LIP_RECEIVED_COUNT, 1825ee824f4bSOmkar Kulkarni DRV_TLV_EOFA_COUNT, 1826ee824f4bSOmkar Kulkarni DRV_TLV_EOFNI_COUNT, 1827ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT, 1828ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT, 1829ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_STATUS_BUSY_COUNT, 1830ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT, 1831ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT, 1832ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT, 1833ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT, 1834ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT, 1835ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT, 1836ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ, 1837ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_CHECK_1_TIMESTAMP, 1838ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ, 1839ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_CHECK_2_TIMESTAMP, 1840ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ, 1841ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_CHECK_3_TIMESTAMP, 1842ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ, 1843ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_CHECK_4_TIMESTAMP, 1844ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ, 1845ee824f4bSOmkar Kulkarni DRV_TLV_SCSI_CHECK_5_TIMESTAMP, 1846ee824f4bSOmkar Kulkarni /* Category 30: iSCSI Function Data */ 1847ee824f4bSOmkar Kulkarni DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 1848ee824f4bSOmkar Kulkarni DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 1849ee824f4bSOmkar Kulkarni DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED, 1850ee824f4bSOmkar Kulkarni DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED, 1851ee824f4bSOmkar Kulkarni DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT, 1852f2a74107SPrabhakar Kushwaha DRV_TLV_ISCSI_PDU_TX_BYTES_SENT, 1853f2a74107SPrabhakar Kushwaha DRV_TLV_RDMA_DRV_VERSION 1854ee824f4bSOmkar Kulkarni }; 1855ee824f4bSOmkar Kulkarni 1856f2a74107SPrabhakar Kushwaha #define I2C_DEV_ADDR_A2 0xa2 1857f2a74107SPrabhakar Kushwaha #define SFP_EEPROM_A2_TEMPERATURE_ADDR 0x60 1858f2a74107SPrabhakar Kushwaha #define SFP_EEPROM_A2_TEMPERATURE_SIZE 2 1859f2a74107SPrabhakar Kushwaha #define SFP_EEPROM_A2_VCC_ADDR 0x62 1860f2a74107SPrabhakar Kushwaha #define SFP_EEPROM_A2_VCC_SIZE 2 1861f2a74107SPrabhakar Kushwaha #define SFP_EEPROM_A2_TX_BIAS_ADDR 0x64 1862f2a74107SPrabhakar Kushwaha #define SFP_EEPROM_A2_TX_BIAS_SIZE 2 1863f2a74107SPrabhakar Kushwaha #define SFP_EEPROM_A2_TX_POWER_ADDR 0x66 1864f2a74107SPrabhakar Kushwaha #define SFP_EEPROM_A2_TX_POWER_SIZE 2 1865f2a74107SPrabhakar Kushwaha #define SFP_EEPROM_A2_RX_POWER_ADDR 0x68 1866f2a74107SPrabhakar Kushwaha #define SFP_EEPROM_A2_RX_POWER_SIZE 2 1867f2a74107SPrabhakar Kushwaha 1868f2a74107SPrabhakar Kushwaha #define I2C_DEV_ADDR_A0 0xa0 1869f2a74107SPrabhakar Kushwaha #define QSFP_EEPROM_A0_TEMPERATURE_ADDR 0x16 1870f2a74107SPrabhakar Kushwaha #define QSFP_EEPROM_A0_TEMPERATURE_SIZE 2 1871f2a74107SPrabhakar Kushwaha #define QSFP_EEPROM_A0_VCC_ADDR 0x1a 1872f2a74107SPrabhakar Kushwaha #define QSFP_EEPROM_A0_VCC_SIZE 2 1873f2a74107SPrabhakar Kushwaha #define QSFP_EEPROM_A0_TX1_BIAS_ADDR 0x2a 1874f2a74107SPrabhakar Kushwaha #define QSFP_EEPROM_A0_TX1_BIAS_SIZE 2 1875f2a74107SPrabhakar Kushwaha #define QSFP_EEPROM_A0_TX1_POWER_ADDR 0x32 1876f2a74107SPrabhakar Kushwaha #define QSFP_EEPROM_A0_TX1_POWER_SIZE 2 1877f2a74107SPrabhakar Kushwaha #define QSFP_EEPROM_A0_RX1_POWER_ADDR 0x22 1878f2a74107SPrabhakar Kushwaha #define QSFP_EEPROM_A0_RX1_POWER_SIZE 2 1879f2a74107SPrabhakar Kushwaha 1880ee824f4bSOmkar Kulkarni struct nvm_cfg_mac_address { 1881ee824f4bSOmkar Kulkarni u32 mac_addr_hi; 1882ee824f4bSOmkar Kulkarni #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000ffff 1883ee824f4bSOmkar Kulkarni #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 1884ee824f4bSOmkar Kulkarni 1885ee824f4bSOmkar Kulkarni u32 mac_addr_lo; 1886ee824f4bSOmkar Kulkarni }; 1887ee824f4bSOmkar Kulkarni 1888ee824f4bSOmkar Kulkarni struct nvm_cfg1_glob { 1889ee824f4bSOmkar Kulkarni u32 generic_cont0; 1890ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000ff0 1891ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 1892ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 1893ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 1894ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 1895ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 1896ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 1897ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 1898ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 1899ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 1900ee824f4bSOmkar Kulkarni 1901ee824f4bSOmkar Kulkarni u32 engineering_change[3]; 1902ee824f4bSOmkar Kulkarni u32 manufacturing_id; 1903ee824f4bSOmkar Kulkarni u32 serial_number[4]; 1904ee824f4bSOmkar Kulkarni u32 pcie_cfg; 1905ee824f4bSOmkar Kulkarni u32 mgmt_traffic; 1906ee824f4bSOmkar Kulkarni 1907ee824f4bSOmkar Kulkarni u32 core_cfg; 1908ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000ff 1909ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 1910ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 1911ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 1912ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 1913ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 1914ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 1915ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 1916ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xb 1917ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xc 1918ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xd 1919ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xe 1920ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xf 1921ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1 0x11 1922ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1 0x12 1923ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2 0x13 1924ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2 0x14 1925ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4 0x15 1926ee824f4bSOmkar Kulkarni 1927ee824f4bSOmkar Kulkarni u32 e_lane_cfg1; 1928ee824f4bSOmkar Kulkarni u32 e_lane_cfg2; 1929ee824f4bSOmkar Kulkarni u32 f_lane_cfg1; 1930ee824f4bSOmkar Kulkarni u32 f_lane_cfg2; 1931ee824f4bSOmkar Kulkarni u32 mps10_preemphasis; 1932ee824f4bSOmkar Kulkarni u32 mps10_driver_current; 1933ee824f4bSOmkar Kulkarni u32 mps25_preemphasis; 1934ee824f4bSOmkar Kulkarni u32 mps25_driver_current; 1935ee824f4bSOmkar Kulkarni u32 pci_id; 1936ee824f4bSOmkar Kulkarni u32 pci_subsys_id; 1937ee824f4bSOmkar Kulkarni u32 bar; 1938ee824f4bSOmkar Kulkarni u32 mps10_txfir_main; 1939ee824f4bSOmkar Kulkarni u32 mps10_txfir_post; 1940ee824f4bSOmkar Kulkarni u32 mps25_txfir_main; 1941ee824f4bSOmkar Kulkarni u32 mps25_txfir_post; 1942ee824f4bSOmkar Kulkarni u32 manufacture_ver; 1943ee824f4bSOmkar Kulkarni u32 manufacture_time; 1944ee824f4bSOmkar Kulkarni u32 led_global_settings; 1945ee824f4bSOmkar Kulkarni u32 generic_cont1; 1946ee824f4bSOmkar Kulkarni 1947ee824f4bSOmkar Kulkarni u32 mbi_version; 1948ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000ff 1949ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 1950ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000ff00 1951ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 1952ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00ff0000 1953ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 1954ee824f4bSOmkar Kulkarni 1955ee824f4bSOmkar Kulkarni u32 mbi_date; 1956ee824f4bSOmkar Kulkarni u32 misc_sig; 1957ee824f4bSOmkar Kulkarni 1958ee824f4bSOmkar Kulkarni u32 device_capabilities; 1959ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 1960ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2 1961ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 1962ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 1963ee824f4bSOmkar Kulkarni #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10 1964ee824f4bSOmkar Kulkarni 1965ee824f4bSOmkar Kulkarni u32 power_dissipated; 1966ee824f4bSOmkar Kulkarni u32 power_consumed; 1967ee824f4bSOmkar Kulkarni u32 efi_version; 1968ee824f4bSOmkar Kulkarni u32 multi_network_modes_capability; 1969f2a74107SPrabhakar Kushwaha u32 nvm_cfg_version; 1970f2a74107SPrabhakar Kushwaha u32 nvm_cfg_new_option_seq; 1971f2a74107SPrabhakar Kushwaha u32 nvm_cfg_removed_option_seq; 1972f2a74107SPrabhakar Kushwaha u32 nvm_cfg_updated_value_seq; 1973f2a74107SPrabhakar Kushwaha u32 extended_serial_number[8]; 1974f2a74107SPrabhakar Kushwaha u32 option_kit_pn[8]; 1975f2a74107SPrabhakar Kushwaha u32 spare_pn[8]; 1976f2a74107SPrabhakar Kushwaha u32 mps25_active_txfir_pre; 1977f2a74107SPrabhakar Kushwaha u32 mps25_active_txfir_main; 1978f2a74107SPrabhakar Kushwaha u32 mps25_active_txfir_post; 1979f2a74107SPrabhakar Kushwaha u32 features; 1980f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_25g_hlpc; 1981f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_25g_llpc; 1982f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_25g_ac; 1983f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_10g_pc; 1984f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_10g_ac; 1985f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_1g; 1986f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_25g_bt; 1987f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_10g_bt; 1988f2a74107SPrabhakar Kushwaha u32 generic_cont4; 1989f2a74107SPrabhakar Kushwaha u32 preboot_debug_mode_std; 1990f2a74107SPrabhakar Kushwaha u32 preboot_debug_mode_ext; 1991f2a74107SPrabhakar Kushwaha u32 ext_phy_cfg1; 1992f2a74107SPrabhakar Kushwaha u32 clocks; 1993f2a74107SPrabhakar Kushwaha u32 pre2_generic_cont_1; 1994f2a74107SPrabhakar Kushwaha u32 pre2_generic_cont_2; 1995f2a74107SPrabhakar Kushwaha u32 pre2_generic_cont_3; 1996f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_50g_hlpc; 1997f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_50g_mlpc; 1998f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_50g_llpc; 1999f2a74107SPrabhakar Kushwaha u32 tx_rx_eq_50g_ac; 2000f2a74107SPrabhakar Kushwaha u32 trace_modules; 2001f2a74107SPrabhakar Kushwaha u32 pcie_class_code_fcoe; 2002f2a74107SPrabhakar Kushwaha u32 pcie_class_code_iscsi; 2003f2a74107SPrabhakar Kushwaha u32 no_provisioned_mac; 2004f2a74107SPrabhakar Kushwaha u32 lowest_mbi_version; 2005f2a74107SPrabhakar Kushwaha u32 generic_cont5; 2006f2a74107SPrabhakar Kushwaha u32 pre2_generic_cont_4; 2007f2a74107SPrabhakar Kushwaha u32 reserved[40]; 2008ee824f4bSOmkar Kulkarni }; 2009ee824f4bSOmkar Kulkarni 2010ee824f4bSOmkar Kulkarni struct nvm_cfg1_path { 2011f2a74107SPrabhakar Kushwaha u32 reserved[1]; 2012ee824f4bSOmkar Kulkarni }; 2013ee824f4bSOmkar Kulkarni 2014ee824f4bSOmkar Kulkarni struct nvm_cfg1_port { 2015ee824f4bSOmkar Kulkarni u32 rel_to_opt123; 2016ee824f4bSOmkar Kulkarni u32 rel_to_opt124; 2017ee824f4bSOmkar Kulkarni 2018ee824f4bSOmkar Kulkarni u32 generic_cont0; 2019ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000f0000 2020ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 2021ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 2022ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 2023ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 2024ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 2025ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00f00000 2026ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 2027ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 2028ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 2029ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 2030ee824f4bSOmkar Kulkarni 2031ee824f4bSOmkar Kulkarni u32 pcie_cfg; 2032ee824f4bSOmkar Kulkarni u32 features; 2033ee824f4bSOmkar Kulkarni 2034ee824f4bSOmkar Kulkarni u32 speed_cap_mask; 2035ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000ffff 2036ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 2037ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 2038ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 2039ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4 2040ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 2041ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 2042ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 2043ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 2044ee824f4bSOmkar Kulkarni 2045ee824f4bSOmkar Kulkarni u32 link_settings; 2046ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000f 2047ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 2048ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 2049ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 2050ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 2051ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3 2052ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 2053ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 2054ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 2055ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 2056ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8 2057ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 2058ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 2059ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 2060ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 2061ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 2062ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000e0000 2063ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17 2064ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0 2065ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1 2066ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2 2067ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7 2068ee824f4bSOmkar Kulkarni 2069ee824f4bSOmkar Kulkarni u32 phy_cfg; 2070ee824f4bSOmkar Kulkarni u32 mgmt_traffic; 2071ee824f4bSOmkar Kulkarni 2072ee824f4bSOmkar Kulkarni u32 ext_phy; 2073ee824f4bSOmkar Kulkarni /* EEE power saving mode */ 2074ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00ff0000 2075ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16 2076ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0 2077ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1 2078ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2 2079ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3 2080ee824f4bSOmkar Kulkarni 2081ee824f4bSOmkar Kulkarni u32 mba_cfg1; 2082ee824f4bSOmkar Kulkarni u32 mba_cfg2; 2083ee824f4bSOmkar Kulkarni u32 vf_cfg; 2084ee824f4bSOmkar Kulkarni struct nvm_cfg_mac_address lldp_mac_address; 2085ee824f4bSOmkar Kulkarni u32 led_port_settings; 2086ee824f4bSOmkar Kulkarni u32 transceiver_00; 2087ee824f4bSOmkar Kulkarni u32 device_ids; 2088ee824f4bSOmkar Kulkarni 2089ee824f4bSOmkar Kulkarni u32 board_cfg; 2090ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000ff 2091ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0 2092ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0 2093ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1 2094ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2 2095ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3 2096ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4 2097ee824f4bSOmkar Kulkarni 2098ee824f4bSOmkar Kulkarni u32 mnm_10g_cap; 2099ee824f4bSOmkar Kulkarni u32 mnm_10g_ctrl; 2100ee824f4bSOmkar Kulkarni u32 mnm_10g_misc; 2101ee824f4bSOmkar Kulkarni u32 mnm_25g_cap; 2102ee824f4bSOmkar Kulkarni u32 mnm_25g_ctrl; 2103ee824f4bSOmkar Kulkarni u32 mnm_25g_misc; 2104ee824f4bSOmkar Kulkarni u32 mnm_40g_cap; 2105ee824f4bSOmkar Kulkarni u32 mnm_40g_ctrl; 2106ee824f4bSOmkar Kulkarni u32 mnm_40g_misc; 2107ee824f4bSOmkar Kulkarni u32 mnm_50g_cap; 2108ee824f4bSOmkar Kulkarni u32 mnm_50g_ctrl; 2109ee824f4bSOmkar Kulkarni u32 mnm_50g_misc; 2110ee824f4bSOmkar Kulkarni u32 mnm_100g_cap; 2111ee824f4bSOmkar Kulkarni u32 mnm_100g_ctrl; 2112ee824f4bSOmkar Kulkarni u32 mnm_100g_misc; 2113ee824f4bSOmkar Kulkarni 2114ee824f4bSOmkar Kulkarni u32 temperature; 2115ee824f4bSOmkar Kulkarni u32 ext_phy_cfg1; 2116ee824f4bSOmkar Kulkarni 2117ee824f4bSOmkar Kulkarni u32 extended_speed; 2118ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_MASK 0x0000ffff 2119ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_OFFSET 0 2120ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN 0x1 2121ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G 0x2 2122ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G 0x4 2123ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G 0x8 2124ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G 0x10 2125ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G 0x20 2126ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R 0x40 2127ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2 0x80 2128ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2 0x100 2129ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4 0x200 2130ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4 0x400 2131ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_MASK 0xffff0000 2132ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_OFFSET 16 2133ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED 0x1 2134ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G 0x2 2135ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G 0x4 2136ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G 0x8 2137ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G 0x10 2138ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G 0x20 2139ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R 0x40 2140ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2 0x80 2141ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2 0x100 2142ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4 0x200 2143ee824f4bSOmkar Kulkarni #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4 0x400 2144ee824f4bSOmkar Kulkarni 2145ee824f4bSOmkar Kulkarni u32 extended_fec_mode; 2146f2a74107SPrabhakar Kushwaha u32 port_generic_cont_01; 2147f2a74107SPrabhakar Kushwaha u32 port_generic_cont_02; 2148f2a74107SPrabhakar Kushwaha u32 phy_temp_monitor; 2149f2a74107SPrabhakar Kushwaha u32 reserved[109]; 2150ee824f4bSOmkar Kulkarni }; 2151ee824f4bSOmkar Kulkarni 2152ee824f4bSOmkar Kulkarni struct nvm_cfg1_func { 2153ee824f4bSOmkar Kulkarni struct nvm_cfg_mac_address mac_address; 2154ee824f4bSOmkar Kulkarni u32 rsrv1; 2155ee824f4bSOmkar Kulkarni u32 rsrv2; 2156ee824f4bSOmkar Kulkarni u32 device_id; 2157ee824f4bSOmkar Kulkarni u32 cmn_cfg; 2158ee824f4bSOmkar Kulkarni u32 pci_cfg; 2159ee824f4bSOmkar Kulkarni struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; 2160ee824f4bSOmkar Kulkarni struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; 2161ee824f4bSOmkar Kulkarni u32 preboot_generic_cfg; 2162f2a74107SPrabhakar Kushwaha u32 features; 2163f2a74107SPrabhakar Kushwaha u32 mf_mode_feature; 2164f2a74107SPrabhakar Kushwaha u32 reserved[6]; 2165ee824f4bSOmkar Kulkarni }; 2166ee824f4bSOmkar Kulkarni 2167ee824f4bSOmkar Kulkarni struct nvm_cfg1 { 2168ee824f4bSOmkar Kulkarni struct nvm_cfg1_glob glob; 2169ee824f4bSOmkar Kulkarni struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; 2170ee824f4bSOmkar Kulkarni struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; 2171ee824f4bSOmkar Kulkarni struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; 2172ee824f4bSOmkar Kulkarni }; 2173ee824f4bSOmkar Kulkarni 2174f2a74107SPrabhakar Kushwaha struct board_info { 2175f2a74107SPrabhakar Kushwaha u16 vendor_id; 2176f2a74107SPrabhakar Kushwaha u16 eth_did_suffix; 2177f2a74107SPrabhakar Kushwaha u16 sub_vendor_id; 2178f2a74107SPrabhakar Kushwaha u16 sub_device_id; 2179f2a74107SPrabhakar Kushwaha char *board_name; 2180f2a74107SPrabhakar Kushwaha char *friendly_name; 2181f2a74107SPrabhakar Kushwaha }; 2182f2a74107SPrabhakar Kushwaha 2183f2a74107SPrabhakar Kushwaha struct trace_module_info { 2184f2a74107SPrabhakar Kushwaha char *module_name; 2185f2a74107SPrabhakar Kushwaha }; 2186f2a74107SPrabhakar Kushwaha 2187f2a74107SPrabhakar Kushwaha #define NUM_TRACE_MODULES 25 2188f2a74107SPrabhakar Kushwaha 2189f2a74107SPrabhakar Kushwaha enum nvm_cfg_sections { 2190f2a74107SPrabhakar Kushwaha NVM_CFG_SECTION_NVM_CFG1, 2191f2a74107SPrabhakar Kushwaha NVM_CFG_SECTION_MAX 2192f2a74107SPrabhakar Kushwaha }; 2193f2a74107SPrabhakar Kushwaha 2194f2a74107SPrabhakar Kushwaha struct nvm_cfg { 2195f2a74107SPrabhakar Kushwaha u32 num_sections; 2196f2a74107SPrabhakar Kushwaha u32 sections_offset[NVM_CFG_SECTION_MAX]; 2197f2a74107SPrabhakar Kushwaha struct nvm_cfg1 cfg1; 2198f2a74107SPrabhakar Kushwaha }; 2199f2a74107SPrabhakar Kushwaha 2200f2a74107SPrabhakar Kushwaha #define PORT_0 0 2201f2a74107SPrabhakar Kushwaha #define PORT_1 1 2202f2a74107SPrabhakar Kushwaha #define PORT_2 2 2203f2a74107SPrabhakar Kushwaha #define PORT_3 3 2204f2a74107SPrabhakar Kushwaha 2205f2a74107SPrabhakar Kushwaha extern struct spad_layout g_spad; 2206f2a74107SPrabhakar Kushwaha struct spad_layout { 2207f2a74107SPrabhakar Kushwaha struct nvm_cfg nvm_cfg; 2208f2a74107SPrabhakar Kushwaha struct mcp_public_data public_data; 2209f2a74107SPrabhakar Kushwaha }; 2210f2a74107SPrabhakar Kushwaha 2211f2a74107SPrabhakar Kushwaha #define MCP_SPAD_SIZE 0x00028000 /* 160 KB */ 2212f2a74107SPrabhakar Kushwaha 2213f2a74107SPrabhakar Kushwaha #define SPAD_OFFSET(addr) (((u32)(addr) - (u32)CPU_SPAD_BASE)) 2214f2a74107SPrabhakar Kushwaha 2215f2a74107SPrabhakar Kushwaha #define TO_OFFSIZE(_offset, _size) \ 2216f2a74107SPrabhakar Kushwaha ((u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_OFFSET) | \ 2217f2a74107SPrabhakar Kushwaha (((u32)(_size) >> 2) << OFFSIZE_SIZE_OFFSET))) 2218f2a74107SPrabhakar Kushwaha 2219ee824f4bSOmkar Kulkarni enum spad_sections { 2220ee824f4bSOmkar Kulkarni SPAD_SECTION_TRACE, 2221ee824f4bSOmkar Kulkarni SPAD_SECTION_NVM_CFG, 2222ee824f4bSOmkar Kulkarni SPAD_SECTION_PUBLIC, 2223ee824f4bSOmkar Kulkarni SPAD_SECTION_PRIVATE, 2224ee824f4bSOmkar Kulkarni SPAD_SECTION_MAX 2225ee824f4bSOmkar Kulkarni }; 2226ee824f4bSOmkar Kulkarni 2227f2a74107SPrabhakar Kushwaha #define STRUCT_OFFSET(f) (STATIC_INIT_BASE + \ 2228f2a74107SPrabhakar Kushwaha __builtin_offsetof(struct static_init, f)) 2229ee824f4bSOmkar Kulkarni 2230ee824f4bSOmkar Kulkarni /* This section is located at a fixed location in the beginning of the 2231ee824f4bSOmkar Kulkarni * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade. 2232ee824f4bSOmkar Kulkarni * All the rest of data has a floating location which differs from version to 2233ee824f4bSOmkar Kulkarni * version, and is pointed by the mcp_meta_data below. 2234ee824f4bSOmkar Kulkarni * Moreover, the spad_layout section is part of the MFW firmware, and is loaded 2235ee824f4bSOmkar Kulkarni * with it from nvram in order to clear this portion. 2236ee824f4bSOmkar Kulkarni */ 2237ee824f4bSOmkar Kulkarni struct static_init { 2238ee824f4bSOmkar Kulkarni u32 num_sections; 2239ee824f4bSOmkar Kulkarni offsize_t sections[SPAD_SECTION_MAX]; 2240ee824f4bSOmkar Kulkarni #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_])))) 2241ee824f4bSOmkar Kulkarni 2242f2a74107SPrabhakar Kushwaha u32 tim_hash[8]; 2243f2a74107SPrabhakar Kushwaha #define PRESERVED_TIM_HASH ((u8 *)(STRUCT_OFFSET(tim_hash))) 2244f2a74107SPrabhakar Kushwaha u32 tpu_hash[8]; 2245f2a74107SPrabhakar Kushwaha #define PRESERVED_TPU_HASH ((u8 *)(STRUCT_OFFSET(tpu_hash))) 2246f2a74107SPrabhakar Kushwaha u32 secure_pcie_fw_ver; 2247f2a74107SPrabhakar Kushwaha #define SECURE_PCIE_FW_VER (*((u32 *)(STRUCT_OFFSET(secure_pcie_fw_ver)))) 2248f2a74107SPrabhakar Kushwaha u32 secure_running_mfw; 2249f2a74107SPrabhakar Kushwaha #define SECURE_RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(secure_running_mfw)))) 2250ee824f4bSOmkar Kulkarni struct mcp_trace trace; 2251ee824f4bSOmkar Kulkarni }; 2252ee824f4bSOmkar Kulkarni 2253f2a74107SPrabhakar Kushwaha #define CRC_MAGIC_VALUE 0xDEBB20E3 2254f2a74107SPrabhakar Kushwaha #define CRC32_POLYNOMIAL 0xEDB88320 2255f2a74107SPrabhakar Kushwaha #define _KB(x) ((x) * 1024) 2256f2a74107SPrabhakar Kushwaha #define _MB(x) (_KB(x) * 1024) 2257f2a74107SPrabhakar Kushwaha #define NVM_CRC_SIZE (sizeof(u32)) 2258f2a74107SPrabhakar Kushwaha enum nvm_sw_arbitrator { 2259f2a74107SPrabhakar Kushwaha NVM_SW_ARB_HOST, 2260f2a74107SPrabhakar Kushwaha NVM_SW_ARB_MCP, 2261f2a74107SPrabhakar Kushwaha NVM_SW_ARB_UART, 2262f2a74107SPrabhakar Kushwaha NVM_SW_ARB_RESERVED 2263f2a74107SPrabhakar Kushwaha }; 2264f2a74107SPrabhakar Kushwaha 2265f2a74107SPrabhakar Kushwaha struct legacy_bootstrap_region { 2266f2a74107SPrabhakar Kushwaha u32 magic_value; 2267ee824f4bSOmkar Kulkarni #define NVM_MAGIC_VALUE 0x669955aa 2268f2a74107SPrabhakar Kushwaha u32 sram_start_addr; 2269f2a74107SPrabhakar Kushwaha u32 code_len; 2270f2a74107SPrabhakar Kushwaha u32 code_start_addr; 2271f2a74107SPrabhakar Kushwaha u32 crc; 2272f2a74107SPrabhakar Kushwaha }; 2273f2a74107SPrabhakar Kushwaha 2274f2a74107SPrabhakar Kushwaha struct nvm_code_entry { 2275f2a74107SPrabhakar Kushwaha u32 image_type; 2276f2a74107SPrabhakar Kushwaha u32 nvm_start_addr; 2277f2a74107SPrabhakar Kushwaha u32 len; 2278f2a74107SPrabhakar Kushwaha u32 sram_start_addr; 2279f2a74107SPrabhakar Kushwaha u32 sram_run_addr; 2280f2a74107SPrabhakar Kushwaha }; 2281ee824f4bSOmkar Kulkarni 2282ee824f4bSOmkar Kulkarni enum nvm_image_type { 2283ee824f4bSOmkar Kulkarni NVM_TYPE_TIM1 = 0x01, 2284ee824f4bSOmkar Kulkarni NVM_TYPE_TIM2 = 0x02, 2285ee824f4bSOmkar Kulkarni NVM_TYPE_MIM1 = 0x03, 2286ee824f4bSOmkar Kulkarni NVM_TYPE_MIM2 = 0x04, 2287ee824f4bSOmkar Kulkarni NVM_TYPE_MBA = 0x05, 2288ee824f4bSOmkar Kulkarni NVM_TYPE_MODULES_PN = 0x06, 2289ee824f4bSOmkar Kulkarni NVM_TYPE_VPD = 0x07, 2290ee824f4bSOmkar Kulkarni NVM_TYPE_MFW_TRACE1 = 0x08, 2291ee824f4bSOmkar Kulkarni NVM_TYPE_MFW_TRACE2 = 0x09, 2292ee824f4bSOmkar Kulkarni NVM_TYPE_NVM_CFG1 = 0x0a, 2293ee824f4bSOmkar Kulkarni NVM_TYPE_L2B = 0x0b, 2294ee824f4bSOmkar Kulkarni NVM_TYPE_DIR1 = 0x0c, 2295ee824f4bSOmkar Kulkarni NVM_TYPE_EAGLE_FW1 = 0x0d, 2296ee824f4bSOmkar Kulkarni NVM_TYPE_FALCON_FW1 = 0x0e, 2297ee824f4bSOmkar Kulkarni NVM_TYPE_PCIE_FW1 = 0x0f, 2298ee824f4bSOmkar Kulkarni NVM_TYPE_HW_SET = 0x10, 2299ee824f4bSOmkar Kulkarni NVM_TYPE_LIM = 0x11, 2300ee824f4bSOmkar Kulkarni NVM_TYPE_AVS_FW1 = 0x12, 2301ee824f4bSOmkar Kulkarni NVM_TYPE_DIR2 = 0x13, 2302ee824f4bSOmkar Kulkarni NVM_TYPE_CCM = 0x14, 2303ee824f4bSOmkar Kulkarni NVM_TYPE_EAGLE_FW2 = 0x15, 2304ee824f4bSOmkar Kulkarni NVM_TYPE_FALCON_FW2 = 0x16, 2305ee824f4bSOmkar Kulkarni NVM_TYPE_PCIE_FW2 = 0x17, 2306ee824f4bSOmkar Kulkarni NVM_TYPE_AVS_FW2 = 0x18, 2307ee824f4bSOmkar Kulkarni NVM_TYPE_INIT_HW = 0x19, 2308ee824f4bSOmkar Kulkarni NVM_TYPE_DEFAULT_CFG = 0x1a, 2309ee824f4bSOmkar Kulkarni NVM_TYPE_MDUMP = 0x1b, 2310f2a74107SPrabhakar Kushwaha NVM_TYPE_NVM_META = 0x1c, 2311ee824f4bSOmkar Kulkarni NVM_TYPE_ISCSI_CFG = 0x1d, 2312ee824f4bSOmkar Kulkarni NVM_TYPE_FCOE_CFG = 0x1f, 2313ee824f4bSOmkar Kulkarni NVM_TYPE_ETH_PHY_FW1 = 0x20, 2314ee824f4bSOmkar Kulkarni NVM_TYPE_ETH_PHY_FW2 = 0x21, 2315ee824f4bSOmkar Kulkarni NVM_TYPE_BDN = 0x22, 2316ee824f4bSOmkar Kulkarni NVM_TYPE_8485X_PHY_FW = 0x23, 2317ee824f4bSOmkar Kulkarni NVM_TYPE_PUB_KEY = 0x24, 2318ee824f4bSOmkar Kulkarni NVM_TYPE_RECOVERY = 0x25, 2319ee824f4bSOmkar Kulkarni NVM_TYPE_PLDM = 0x26, 2320ee824f4bSOmkar Kulkarni NVM_TYPE_UPK1 = 0x27, 2321ee824f4bSOmkar Kulkarni NVM_TYPE_UPK2 = 0x28, 2322ee824f4bSOmkar Kulkarni NVM_TYPE_MASTER_KC = 0x29, 2323ee824f4bSOmkar Kulkarni NVM_TYPE_BACKUP_KC = 0x2a, 2324ee824f4bSOmkar Kulkarni NVM_TYPE_HW_DUMP = 0x2b, 2325ee824f4bSOmkar Kulkarni NVM_TYPE_HW_DUMP_OUT = 0x2c, 2326ee824f4bSOmkar Kulkarni NVM_TYPE_BIN_NVM_META = 0x30, 2327ee824f4bSOmkar Kulkarni NVM_TYPE_ROM_TEST = 0xf0, 2328ee824f4bSOmkar Kulkarni NVM_TYPE_88X33X0_PHY_FW = 0x31, 2329ee824f4bSOmkar Kulkarni NVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32, 2330f2a74107SPrabhakar Kushwaha NVM_TYPE_IDLE_CHK = 0x33, 2331ee824f4bSOmkar Kulkarni NVM_TYPE_MAX, 2332ee824f4bSOmkar Kulkarni }; 2333ee824f4bSOmkar Kulkarni 2334f2a74107SPrabhakar Kushwaha #define MAX_NVM_DIR_ENTRIES 100 2335ee824f4bSOmkar Kulkarni 2336f2a74107SPrabhakar Kushwaha struct nvm_dir_meta { 2337f2a74107SPrabhakar Kushwaha u32 dir_id; 2338f2a74107SPrabhakar Kushwaha u32 nvm_dir_addr; 2339f2a74107SPrabhakar Kushwaha u32 num_images; 2340f2a74107SPrabhakar Kushwaha u32 next_mfw_to_run; 2341f2a74107SPrabhakar Kushwaha }; 2342f2a74107SPrabhakar Kushwaha 2343f2a74107SPrabhakar Kushwaha struct nvm_dir { 2344f2a74107SPrabhakar Kushwaha s32 seq; 2345f2a74107SPrabhakar Kushwaha #define NVM_DIR_NEXT_MFW_MASK 0x00000001 2346f2a74107SPrabhakar Kushwaha #define NVM_DIR_SEQ_MASK 0xfffffffe 2347f2a74107SPrabhakar Kushwaha #define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK) 2348f2a74107SPrabhakar Kushwaha #define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw)\ 2349f2a74107SPrabhakar Kushwaha ({ \ 2350f2a74107SPrabhakar Kushwaha _seq = (((_seq + 2) & \ 2351f2a74107SPrabhakar Kushwaha NVM_DIR_SEQ_MASK) | \ 2352f2a74107SPrabhakar Kushwaha (NVM_DIR_NEXT_MFW(_seq ^ (swap_mfw))));\ 2353f2a74107SPrabhakar Kushwaha }) 2354f2a74107SPrabhakar Kushwaha 2355f2a74107SPrabhakar Kushwaha #define IS_DIR_SEQ_VALID(seq) (((seq) & NVM_DIR_SEQ_MASK) != \ 2356f2a74107SPrabhakar Kushwaha NVM_DIR_SEQ_MASK) 2357f2a74107SPrabhakar Kushwaha 2358f2a74107SPrabhakar Kushwaha u32 num_images; 2359f2a74107SPrabhakar Kushwaha u32 rsrv; 2360f2a74107SPrabhakar Kushwaha struct nvm_code_entry code[1]; /* Up to MAX_NVM_DIR_ENTRIES */ 2361f2a74107SPrabhakar Kushwaha }; 2362f2a74107SPrabhakar Kushwaha 2363f2a74107SPrabhakar Kushwaha #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + \ 2364f2a74107SPrabhakar Kushwaha ((_num_images) - 1) *\ 2365f2a74107SPrabhakar Kushwaha sizeof(struct nvm_code_entry) +\ 2366f2a74107SPrabhakar Kushwaha NVM_CRC_SIZE) 2367f2a74107SPrabhakar Kushwaha 2368f2a74107SPrabhakar Kushwaha struct nvm_vpd_image { 2369f2a74107SPrabhakar Kushwaha u32 format_revision; 2370f2a74107SPrabhakar Kushwaha #define VPD_IMAGE_VERSION 1 2371f2a74107SPrabhakar Kushwaha 2372f2a74107SPrabhakar Kushwaha u8 vpd_data[1]; 2373f2a74107SPrabhakar Kushwaha }; 2374f2a74107SPrabhakar Kushwaha 2375f2a74107SPrabhakar Kushwaha #define DIR_ID_1 (0) 2376f2a74107SPrabhakar Kushwaha #define DIR_ID_2 (1) 2377f2a74107SPrabhakar Kushwaha #define MAX_DIR_IDS (2) 2378f2a74107SPrabhakar Kushwaha 2379f2a74107SPrabhakar Kushwaha #define MFW_BUNDLE_1 (0) 2380f2a74107SPrabhakar Kushwaha #define MFW_BUNDLE_2 (1) 2381f2a74107SPrabhakar Kushwaha #define MAX_MFW_BUNDLES (2) 2382f2a74107SPrabhakar Kushwaha 2383f2a74107SPrabhakar Kushwaha #define FLASH_PAGE_SIZE 0x1000 2384f2a74107SPrabhakar Kushwaha #define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) 2385f2a74107SPrabhakar Kushwaha #define LEGACY_ASIC_MIM_MAX_SIZE (_KB(1200)) 2386f2a74107SPrabhakar Kushwaha 2387f2a74107SPrabhakar Kushwaha #define FPGA_MIM_MAX_SIZE (0x40000) 2388f2a74107SPrabhakar Kushwaha 2389f2a74107SPrabhakar Kushwaha #define LIM_MAX_SIZE ((2 * FLASH_PAGE_SIZE) - \ 2390f2a74107SPrabhakar Kushwaha sizeof(struct legacy_bootstrap_region) \ 2391f2a74107SPrabhakar Kushwaha - NVM_RSV_SIZE) 2392f2a74107SPrabhakar Kushwaha #define LIM_OFFSET (NVM_OFFSET(lim_image)) 2393f2a74107SPrabhakar Kushwaha #define NVM_RSV_SIZE (44) 2394f2a74107SPrabhakar Kushwaha #define GET_MIM_MAX_SIZE(is_asic, is_e4) (LEGACY_ASIC_MIM_MAX_SIZE) 2395f2a74107SPrabhakar Kushwaha #define GET_MIM_OFFSET(idx, is_asic, is_e4) (NVM_OFFSET(dir[MAX_MFW_BUNDLES])\ 2396f2a74107SPrabhakar Kushwaha + (((idx) == NVM_TYPE_MIM2) ? \ 2397f2a74107SPrabhakar Kushwaha GET_MIM_MAX_SIZE(is_asic, is_e4)\ 2398f2a74107SPrabhakar Kushwaha : 0)) 2399f2a74107SPrabhakar Kushwaha #define GET_NVM_FIXED_AREA_SIZE(is_asic, is_e4) (sizeof(struct nvm_image) + \ 2400f2a74107SPrabhakar Kushwaha GET_MIM_MAX_SIZE(is_asic,\ 2401f2a74107SPrabhakar Kushwaha is_e4) * 2) 2402f2a74107SPrabhakar Kushwaha 2403f2a74107SPrabhakar Kushwaha union nvm_dir_union { 2404f2a74107SPrabhakar Kushwaha struct nvm_dir dir; 2405f2a74107SPrabhakar Kushwaha u8 page[FLASH_PAGE_SIZE]; 2406f2a74107SPrabhakar Kushwaha }; 2407f2a74107SPrabhakar Kushwaha 2408f2a74107SPrabhakar Kushwaha struct nvm_image { 2409f2a74107SPrabhakar Kushwaha struct legacy_bootstrap_region bootstrap; 2410f2a74107SPrabhakar Kushwaha u8 rsrv[NVM_RSV_SIZE]; 2411f2a74107SPrabhakar Kushwaha u8 lim_image[LIM_MAX_SIZE]; 2412f2a74107SPrabhakar Kushwaha union nvm_dir_union dir[MAX_MFW_BUNDLES]; 2413f2a74107SPrabhakar Kushwaha }; 2414f2a74107SPrabhakar Kushwaha 2415f2a74107SPrabhakar Kushwaha #define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image *)0)->(f))))) 2416f2a74107SPrabhakar Kushwaha 2417f2a74107SPrabhakar Kushwaha struct hw_set_info { 2418f2a74107SPrabhakar Kushwaha u32 reg_type; 2419f2a74107SPrabhakar Kushwaha #define GRC_REG_TYPE 1 2420f2a74107SPrabhakar Kushwaha #define PHY_REG_TYPE 2 2421f2a74107SPrabhakar Kushwaha #define PCI_REG_TYPE 4 2422f2a74107SPrabhakar Kushwaha 2423f2a74107SPrabhakar Kushwaha u32 bank_num; 2424f2a74107SPrabhakar Kushwaha u32 pf_num; 2425f2a74107SPrabhakar Kushwaha u32 operation; 2426f2a74107SPrabhakar Kushwaha #define READ_OP 1 2427f2a74107SPrabhakar Kushwaha #define WRITE_OP 2 2428f2a74107SPrabhakar Kushwaha #define RMW_SET_OP 3 2429f2a74107SPrabhakar Kushwaha #define RMW_CLR_OP 4 2430f2a74107SPrabhakar Kushwaha 2431f2a74107SPrabhakar Kushwaha u32 reg_addr; 2432f2a74107SPrabhakar Kushwaha u32 reg_data; 2433f2a74107SPrabhakar Kushwaha 2434f2a74107SPrabhakar Kushwaha u32 reset_type; 2435f2a74107SPrabhakar Kushwaha #define POR_RESET_TYPE BIT(0) 2436f2a74107SPrabhakar Kushwaha #define HARD_RESET_TYPE BIT(1) 2437f2a74107SPrabhakar Kushwaha #define CORE_RESET_TYPE BIT(2) 2438f2a74107SPrabhakar Kushwaha #define MCP_RESET_TYPE BIT(3) 2439f2a74107SPrabhakar Kushwaha #define PERSET_ASSERT BIT(4) 2440f2a74107SPrabhakar Kushwaha #define PERSET_DEASSERT BIT(5) 2441f2a74107SPrabhakar Kushwaha }; 2442f2a74107SPrabhakar Kushwaha 2443f2a74107SPrabhakar Kushwaha struct hw_set_image { 2444f2a74107SPrabhakar Kushwaha u32 format_version; 2445f2a74107SPrabhakar Kushwaha #define HW_SET_IMAGE_VERSION 1 2446f2a74107SPrabhakar Kushwaha u32 no_hw_sets; 2447f2a74107SPrabhakar Kushwaha struct hw_set_info hw_sets[1]; 2448f2a74107SPrabhakar Kushwaha }; 2449f2a74107SPrabhakar Kushwaha 2450f2a74107SPrabhakar Kushwaha #define MAX_SUPPORTED_NVM_OPTIONS 1000 2451f2a74107SPrabhakar Kushwaha 2452f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_OFFSET_MASK 0x0000ffff 2453f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_OFFSET_SHIFT 0 2454f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_LEN_MASK 0x00ff0000 2455f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_LEN_OFFSET 16 2456f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_ENTITY_MASK 0x03000000 2457f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_ENTITY_SHIFT 24 2458f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_ENTITY_GLOB 0 2459f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_ENTITY_PORT 1 2460f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_ENTITY_FUNC 2 2461f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_CONFIG_TYPE_MASK 0x0c000000 2462f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_CONFIG_TYPE_SHIFT 26 2463f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_CONFIG_TYPE_USER 0 2464f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_CONFIG_TYPE_FIXED 1 2465f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_OPTION_CONFIG_TYPE_FORCED 2 2466f2a74107SPrabhakar Kushwaha 2467f2a74107SPrabhakar Kushwaha struct nvm_meta_bin_t { 2468f2a74107SPrabhakar Kushwaha u32 magic; 2469f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_MAGIC 0x669955bb 2470f2a74107SPrabhakar Kushwaha u32 version; 2471f2a74107SPrabhakar Kushwaha #define NVM_META_BIN_VERSION 1 2472f2a74107SPrabhakar Kushwaha u32 num_options; 2473*5224f790SGustavo A. R. Silva u32 options[]; 2474f2a74107SPrabhakar Kushwaha }; 2475ee824f4bSOmkar Kulkarni #endif 2476