1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_MCP_H 34fe56b9e6SYuval Mintz #define _QED_MCP_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/delay.h> 38fe56b9e6SYuval Mintz #include <linux/slab.h> 395529bad9STomer Tayar #include <linux/spinlock.h> 401e128c81SArun Easi #include <linux/qed/qed_fcoe_if.h> 41fe56b9e6SYuval Mintz #include "qed_hsi.h" 425d24bcf1STomer Tayar #include "qed_dev_api.h" 43fe56b9e6SYuval Mintz 44cc875c2eSYuval Mintz struct qed_mcp_link_speed_params { 45cc875c2eSYuval Mintz bool autoneg; 46cc875c2eSYuval Mintz u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */ 47cc875c2eSYuval Mintz u32 forced_speed; /* In Mb/s */ 48cc875c2eSYuval Mintz }; 49cc875c2eSYuval Mintz 50cc875c2eSYuval Mintz struct qed_mcp_link_pause_params { 51cc875c2eSYuval Mintz bool autoneg; 52cc875c2eSYuval Mintz bool forced_rx; 53cc875c2eSYuval Mintz bool forced_tx; 54cc875c2eSYuval Mintz }; 55cc875c2eSYuval Mintz 56645874e5SSudarsana Reddy Kalluru enum qed_mcp_eee_mode { 57645874e5SSudarsana Reddy Kalluru QED_MCP_EEE_DISABLED, 58645874e5SSudarsana Reddy Kalluru QED_MCP_EEE_ENABLED, 59645874e5SSudarsana Reddy Kalluru QED_MCP_EEE_UNSUPPORTED 60645874e5SSudarsana Reddy Kalluru }; 61645874e5SSudarsana Reddy Kalluru 62cc875c2eSYuval Mintz struct qed_mcp_link_params { 63cc875c2eSYuval Mintz struct qed_mcp_link_speed_params speed; 64cc875c2eSYuval Mintz struct qed_mcp_link_pause_params pause; 65cc875c2eSYuval Mintz u32 loopback_mode; 66645874e5SSudarsana Reddy Kalluru struct qed_link_eee_params eee; 67cc875c2eSYuval Mintz }; 68cc875c2eSYuval Mintz 69cc875c2eSYuval Mintz struct qed_mcp_link_capabilities { 70cc875c2eSYuval Mintz u32 speed_capabilities; 7134f9199cSsudarsana.kalluru@cavium.com bool default_speed_autoneg; 72645874e5SSudarsana Reddy Kalluru enum qed_mcp_eee_mode default_eee; 73645874e5SSudarsana Reddy Kalluru u32 eee_lpi_timer; 74645874e5SSudarsana Reddy Kalluru u8 eee_speed_caps; 75cc875c2eSYuval Mintz }; 76cc875c2eSYuval Mintz 77cc875c2eSYuval Mintz struct qed_mcp_link_state { 78cc875c2eSYuval Mintz bool link_up; 79cc875c2eSYuval Mintz 80a64b02d5SManish Chopra u32 min_pf_rate; 81a64b02d5SManish Chopra 824b01e519SManish Chopra /* Actual link speed in Mb/s */ 834b01e519SManish Chopra u32 line_speed; 844b01e519SManish Chopra 854b01e519SManish Chopra /* PF max speed in Mb/s, deduced from line_speed 864b01e519SManish Chopra * according to PF max bandwidth configuration. 874b01e519SManish Chopra */ 884b01e519SManish Chopra u32 speed; 89cc875c2eSYuval Mintz bool full_duplex; 90cc875c2eSYuval Mintz 91cc875c2eSYuval Mintz bool an; 92cc875c2eSYuval Mintz bool an_complete; 93cc875c2eSYuval Mintz bool parallel_detection; 94cc875c2eSYuval Mintz bool pfc_enabled; 95cc875c2eSYuval Mintz 96cc875c2eSYuval Mintz #define QED_LINK_PARTNER_SPEED_1G_HD BIT(0) 97cc875c2eSYuval Mintz #define QED_LINK_PARTNER_SPEED_1G_FD BIT(1) 98cc875c2eSYuval Mintz #define QED_LINK_PARTNER_SPEED_10G BIT(2) 99cc875c2eSYuval Mintz #define QED_LINK_PARTNER_SPEED_20G BIT(3) 100054c67d1SSudarsana Reddy Kalluru #define QED_LINK_PARTNER_SPEED_25G BIT(4) 101054c67d1SSudarsana Reddy Kalluru #define QED_LINK_PARTNER_SPEED_40G BIT(5) 102054c67d1SSudarsana Reddy Kalluru #define QED_LINK_PARTNER_SPEED_50G BIT(6) 103054c67d1SSudarsana Reddy Kalluru #define QED_LINK_PARTNER_SPEED_100G BIT(7) 104cc875c2eSYuval Mintz u32 partner_adv_speed; 105cc875c2eSYuval Mintz 106cc875c2eSYuval Mintz bool partner_tx_flow_ctrl_en; 107cc875c2eSYuval Mintz bool partner_rx_flow_ctrl_en; 108cc875c2eSYuval Mintz 109cc875c2eSYuval Mintz #define QED_LINK_PARTNER_SYMMETRIC_PAUSE (1) 110cc875c2eSYuval Mintz #define QED_LINK_PARTNER_ASYMMETRIC_PAUSE (2) 111cc875c2eSYuval Mintz #define QED_LINK_PARTNER_BOTH_PAUSE (3) 112cc875c2eSYuval Mintz u8 partner_adv_pause; 113cc875c2eSYuval Mintz 114cc875c2eSYuval Mintz bool sfp_tx_fault; 115645874e5SSudarsana Reddy Kalluru bool eee_active; 116645874e5SSudarsana Reddy Kalluru u8 eee_adv_caps; 117645874e5SSudarsana Reddy Kalluru u8 eee_lp_adv_caps; 118cc875c2eSYuval Mintz }; 119cc875c2eSYuval Mintz 120fe56b9e6SYuval Mintz struct qed_mcp_function_info { 121fe56b9e6SYuval Mintz u8 pause_on_host; 122fe56b9e6SYuval Mintz 123fe56b9e6SYuval Mintz enum qed_pci_personality protocol; 124fe56b9e6SYuval Mintz 125fe56b9e6SYuval Mintz u8 bandwidth_min; 126fe56b9e6SYuval Mintz u8 bandwidth_max; 127fe56b9e6SYuval Mintz 128fe56b9e6SYuval Mintz u8 mac[ETH_ALEN]; 129fe56b9e6SYuval Mintz 130fe56b9e6SYuval Mintz u64 wwn_port; 131fe56b9e6SYuval Mintz u64 wwn_node; 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz #define QED_MCP_VLAN_UNSET (0xffff) 134fe56b9e6SYuval Mintz u16 ovlan; 1350fefbfbaSSudarsana Kalluru 1360fefbfbaSSudarsana Kalluru u16 mtu; 137fe56b9e6SYuval Mintz }; 138fe56b9e6SYuval Mintz 139fe56b9e6SYuval Mintz struct qed_mcp_nvm_common { 140fe56b9e6SYuval Mintz u32 offset; 141fe56b9e6SYuval Mintz u32 param; 142fe56b9e6SYuval Mintz u32 resp; 143fe56b9e6SYuval Mintz u32 cmd; 144fe56b9e6SYuval Mintz }; 145fe56b9e6SYuval Mintz 146fe56b9e6SYuval Mintz struct qed_mcp_drv_version { 147fe56b9e6SYuval Mintz u32 version; 148fe56b9e6SYuval Mintz u8 name[MCP_DRV_VER_STR_SIZE - 4]; 149fe56b9e6SYuval Mintz }; 150fe56b9e6SYuval Mintz 1516c754246SSudarsana Reddy Kalluru struct qed_mcp_lan_stats { 1526c754246SSudarsana Reddy Kalluru u64 ucast_rx_pkts; 1536c754246SSudarsana Reddy Kalluru u64 ucast_tx_pkts; 1546c754246SSudarsana Reddy Kalluru u32 fcs_err; 1556c754246SSudarsana Reddy Kalluru }; 1566c754246SSudarsana Reddy Kalluru 1576c754246SSudarsana Reddy Kalluru struct qed_mcp_fcoe_stats { 1586c754246SSudarsana Reddy Kalluru u64 rx_pkts; 1596c754246SSudarsana Reddy Kalluru u64 tx_pkts; 1606c754246SSudarsana Reddy Kalluru u32 fcs_err; 1616c754246SSudarsana Reddy Kalluru u32 login_failure; 1626c754246SSudarsana Reddy Kalluru }; 1636c754246SSudarsana Reddy Kalluru 1646c754246SSudarsana Reddy Kalluru struct qed_mcp_iscsi_stats { 1656c754246SSudarsana Reddy Kalluru u64 rx_pdus; 1666c754246SSudarsana Reddy Kalluru u64 tx_pdus; 1676c754246SSudarsana Reddy Kalluru u64 rx_bytes; 1686c754246SSudarsana Reddy Kalluru u64 tx_bytes; 1696c754246SSudarsana Reddy Kalluru }; 1706c754246SSudarsana Reddy Kalluru 1716c754246SSudarsana Reddy Kalluru struct qed_mcp_rdma_stats { 1726c754246SSudarsana Reddy Kalluru u64 rx_pkts; 1736c754246SSudarsana Reddy Kalluru u64 tx_pkts; 1746c754246SSudarsana Reddy Kalluru u64 rx_bytes; 1756c754246SSudarsana Reddy Kalluru u64 tx_byts; 1766c754246SSudarsana Reddy Kalluru }; 1776c754246SSudarsana Reddy Kalluru 1786c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type { 1796c754246SSudarsana Reddy Kalluru QED_MCP_LAN_STATS, 1806c754246SSudarsana Reddy Kalluru QED_MCP_FCOE_STATS, 1816c754246SSudarsana Reddy Kalluru QED_MCP_ISCSI_STATS, 1826c754246SSudarsana Reddy Kalluru QED_MCP_RDMA_STATS 1836c754246SSudarsana Reddy Kalluru }; 1846c754246SSudarsana Reddy Kalluru 1856c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats { 1866c754246SSudarsana Reddy Kalluru struct qed_mcp_lan_stats lan_stats; 1876c754246SSudarsana Reddy Kalluru struct qed_mcp_fcoe_stats fcoe_stats; 1886c754246SSudarsana Reddy Kalluru struct qed_mcp_iscsi_stats iscsi_stats; 1896c754246SSudarsana Reddy Kalluru struct qed_mcp_rdma_stats rdma_stats; 1906c754246SSudarsana Reddy Kalluru }; 1916c754246SSudarsana Reddy Kalluru 1920fefbfbaSSudarsana Kalluru enum qed_ov_eswitch { 1930fefbfbaSSudarsana Kalluru QED_OV_ESWITCH_NONE, 1940fefbfbaSSudarsana Kalluru QED_OV_ESWITCH_VEB, 1950fefbfbaSSudarsana Kalluru QED_OV_ESWITCH_VEPA 1960fefbfbaSSudarsana Kalluru }; 1970fefbfbaSSudarsana Kalluru 1980fefbfbaSSudarsana Kalluru enum qed_ov_client { 1990fefbfbaSSudarsana Kalluru QED_OV_CLIENT_DRV, 2000fefbfbaSSudarsana Kalluru QED_OV_CLIENT_USER, 2010fefbfbaSSudarsana Kalluru QED_OV_CLIENT_VENDOR_SPEC 2020fefbfbaSSudarsana Kalluru }; 2030fefbfbaSSudarsana Kalluru 2040fefbfbaSSudarsana Kalluru enum qed_ov_driver_state { 2050fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_NOT_LOADED, 2060fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_DISABLED, 2070fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_ACTIVE 2080fefbfbaSSudarsana Kalluru }; 2090fefbfbaSSudarsana Kalluru 2100fefbfbaSSudarsana Kalluru enum qed_ov_wol { 2110fefbfbaSSudarsana Kalluru QED_OV_WOL_DEFAULT, 2120fefbfbaSSudarsana Kalluru QED_OV_WOL_DISABLED, 2130fefbfbaSSudarsana Kalluru QED_OV_WOL_ENABLED 2140fefbfbaSSudarsana Kalluru }; 2150fefbfbaSSudarsana Kalluru 2162528c389SSudarsana Reddy Kalluru enum qed_mfw_tlv_type { 2172528c389SSudarsana Reddy Kalluru QED_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */ 2182528c389SSudarsana Reddy Kalluru QED_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */ 219f240b688SSudarsana Reddy Kalluru QED_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */ 22077a509e4SSudarsana Reddy Kalluru QED_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */ 22177a509e4SSudarsana Reddy Kalluru QED_MFW_TLV_MAX = 0x16, 2222528c389SSudarsana Reddy Kalluru }; 2232528c389SSudarsana Reddy Kalluru 2242528c389SSudarsana Reddy Kalluru struct qed_mfw_tlv_generic { 2252528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_FLAGS_SIZE 2 2262528c389SSudarsana Reddy Kalluru struct { 2272528c389SSudarsana Reddy Kalluru u8 ipv4_csum_offload; 2282528c389SSudarsana Reddy Kalluru u8 lso_supported; 2292528c389SSudarsana Reddy Kalluru bool b_set; 2302528c389SSudarsana Reddy Kalluru } flags; 2312528c389SSudarsana Reddy Kalluru 2322528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_MAC_COUNT 3 2332528c389SSudarsana Reddy Kalluru /* First entry for primary MAC, 2 secondary MACs possible */ 2342528c389SSudarsana Reddy Kalluru u8 mac[QED_MFW_TLV_MAC_COUNT][6]; 2352528c389SSudarsana Reddy Kalluru bool mac_set[QED_MFW_TLV_MAC_COUNT]; 2362528c389SSudarsana Reddy Kalluru 2372528c389SSudarsana Reddy Kalluru u64 rx_frames; 2382528c389SSudarsana Reddy Kalluru bool rx_frames_set; 2392528c389SSudarsana Reddy Kalluru u64 rx_bytes; 2402528c389SSudarsana Reddy Kalluru bool rx_bytes_set; 2412528c389SSudarsana Reddy Kalluru u64 tx_frames; 2422528c389SSudarsana Reddy Kalluru bool tx_frames_set; 2432528c389SSudarsana Reddy Kalluru u64 tx_bytes; 2442528c389SSudarsana Reddy Kalluru bool tx_bytes_set; 2452528c389SSudarsana Reddy Kalluru }; 2462528c389SSudarsana Reddy Kalluru 2472528c389SSudarsana Reddy Kalluru union qed_mfw_tlv_data { 2482528c389SSudarsana Reddy Kalluru struct qed_mfw_tlv_generic generic; 2492528c389SSudarsana Reddy Kalluru struct qed_mfw_tlv_eth eth; 250f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_fcoe fcoe; 25177a509e4SSudarsana Reddy Kalluru struct qed_mfw_tlv_iscsi iscsi; 2522528c389SSudarsana Reddy Kalluru }; 2532528c389SSudarsana Reddy Kalluru 254fe56b9e6SYuval Mintz /** 255cc875c2eSYuval Mintz * @brief - returns the link params of the hw function 256cc875c2eSYuval Mintz * 257cc875c2eSYuval Mintz * @param p_hwfn 258cc875c2eSYuval Mintz * 259cc875c2eSYuval Mintz * @returns pointer to link params 260cc875c2eSYuval Mintz */ 261cc875c2eSYuval Mintz struct qed_mcp_link_params *qed_mcp_get_link_params(struct qed_hwfn *); 262cc875c2eSYuval Mintz 263cc875c2eSYuval Mintz /** 264cc875c2eSYuval Mintz * @brief - return the link state of the hw function 265cc875c2eSYuval Mintz * 266cc875c2eSYuval Mintz * @param p_hwfn 267cc875c2eSYuval Mintz * 268cc875c2eSYuval Mintz * @returns pointer to link state 269cc875c2eSYuval Mintz */ 270cc875c2eSYuval Mintz struct qed_mcp_link_state *qed_mcp_get_link_state(struct qed_hwfn *); 271cc875c2eSYuval Mintz 272cc875c2eSYuval Mintz /** 273cc875c2eSYuval Mintz * @brief - return the link capabilities of the hw function 274cc875c2eSYuval Mintz * 275cc875c2eSYuval Mintz * @param p_hwfn 276cc875c2eSYuval Mintz * 277cc875c2eSYuval Mintz * @returns pointer to link capabilities 278cc875c2eSYuval Mintz */ 279cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 280cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn); 281cc875c2eSYuval Mintz 282cc875c2eSYuval Mintz /** 283cc875c2eSYuval Mintz * @brief Request the MFW to set the the link according to 'link_input'. 284cc875c2eSYuval Mintz * 285cc875c2eSYuval Mintz * @param p_hwfn 286cc875c2eSYuval Mintz * @param p_ptt 287cc875c2eSYuval Mintz * @param b_up - raise link if `true'. Reset link if `false'. 288cc875c2eSYuval Mintz * 289cc875c2eSYuval Mintz * @return int 290cc875c2eSYuval Mintz */ 291cc875c2eSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, 292cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 293cc875c2eSYuval Mintz bool b_up); 294cc875c2eSYuval Mintz 295cc875c2eSYuval Mintz /** 296fe56b9e6SYuval Mintz * @brief Get the management firmware version value 297fe56b9e6SYuval Mintz * 2981408cc1fSYuval Mintz * @param p_hwfn 2991408cc1fSYuval Mintz * @param p_ptt 3001408cc1fSYuval Mintz * @param p_mfw_ver - mfw version value 3011408cc1fSYuval Mintz * @param p_running_bundle_id - image id in nvram; Optional. 302fe56b9e6SYuval Mintz * 3031408cc1fSYuval Mintz * @return int - 0 - operation was successful. 304fe56b9e6SYuval Mintz */ 3051408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 3061408cc1fSYuval Mintz struct qed_ptt *p_ptt, 3071408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id); 308fe56b9e6SYuval Mintz 309fe56b9e6SYuval Mintz /** 310ae33666aSTomer Tayar * @brief Get the MBI version value 311ae33666aSTomer Tayar * 312ae33666aSTomer Tayar * @param p_hwfn 313ae33666aSTomer Tayar * @param p_ptt 314ae33666aSTomer Tayar * @param p_mbi_ver - A pointer to a variable to be filled with the MBI version. 315ae33666aSTomer Tayar * 316ae33666aSTomer Tayar * @return int - 0 - operation was successful. 317ae33666aSTomer Tayar */ 318ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 319ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver); 320ae33666aSTomer Tayar 321ae33666aSTomer Tayar /** 322cc875c2eSYuval Mintz * @brief Get media type value of the port. 323cc875c2eSYuval Mintz * 324cc875c2eSYuval Mintz * @param cdev - qed dev pointer 325706d0891SRahul Verma * @param p_ptt 326cc875c2eSYuval Mintz * @param mfw_ver - media type value 327cc875c2eSYuval Mintz * 328cc875c2eSYuval Mintz * @return int - 329cc875c2eSYuval Mintz * 0 - Operation was successul. 330cc875c2eSYuval Mintz * -EBUSY - Operation failed 331cc875c2eSYuval Mintz */ 332706d0891SRahul Verma int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, 333706d0891SRahul Verma struct qed_ptt *p_ptt, u32 *media_type); 334cc875c2eSYuval Mintz 335cc875c2eSYuval Mintz /** 336c56a8be7SRahul Verma * @brief Get transceiver data of the port. 337c56a8be7SRahul Verma * 338c56a8be7SRahul Verma * @param cdev - qed dev pointer 339c56a8be7SRahul Verma * @param p_ptt 340c56a8be7SRahul Verma * @param p_transceiver_state - transceiver state. 341c56a8be7SRahul Verma * @param p_transceiver_type - media type value 342c56a8be7SRahul Verma * 343c56a8be7SRahul Verma * @return int - 344c56a8be7SRahul Verma * 0 - Operation was successful. 345c56a8be7SRahul Verma * -EBUSY - Operation failed 346c56a8be7SRahul Verma */ 347c56a8be7SRahul Verma int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, 348c56a8be7SRahul Verma struct qed_ptt *p_ptt, 349c56a8be7SRahul Verma u32 *p_transceiver_state, 350c56a8be7SRahul Verma u32 *p_tranceiver_type); 351c56a8be7SRahul Verma 352c56a8be7SRahul Verma /** 353c56a8be7SRahul Verma * @brief Get transceiver supported speed mask. 354c56a8be7SRahul Verma * 355c56a8be7SRahul Verma * @param cdev - qed dev pointer 356c56a8be7SRahul Verma * @param p_ptt 357c56a8be7SRahul Verma * @param p_speed_mask - Bit mask of all supported speeds. 358c56a8be7SRahul Verma * 359c56a8be7SRahul Verma * @return int - 360c56a8be7SRahul Verma * 0 - Operation was successful. 361c56a8be7SRahul Verma * -EBUSY - Operation failed 362c56a8be7SRahul Verma */ 363c56a8be7SRahul Verma 364c56a8be7SRahul Verma int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, 365c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_speed_mask); 366c56a8be7SRahul Verma 367c56a8be7SRahul Verma /** 368c56a8be7SRahul Verma * @brief Get board configuration. 369c56a8be7SRahul Verma * 370c56a8be7SRahul Verma * @param cdev - qed dev pointer 371c56a8be7SRahul Verma * @param p_ptt 372c56a8be7SRahul Verma * @param p_board_config - Board config. 373c56a8be7SRahul Verma * 374c56a8be7SRahul Verma * @return int - 375c56a8be7SRahul Verma * 0 - Operation was successful. 376c56a8be7SRahul Verma * -EBUSY - Operation failed 377c56a8be7SRahul Verma */ 378c56a8be7SRahul Verma int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, 379c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_board_config); 380c56a8be7SRahul Verma 381c56a8be7SRahul Verma /** 382fe56b9e6SYuval Mintz * @brief General function for sending commands to the MCP 383fe56b9e6SYuval Mintz * mailbox. It acquire mutex lock for the entire 384fe56b9e6SYuval Mintz * operation, from sending the request until the MCP 385fe56b9e6SYuval Mintz * response. Waiting for MCP response will be checked up 386fe56b9e6SYuval Mintz * to 5 seconds every 5ms. 387fe56b9e6SYuval Mintz * 388fe56b9e6SYuval Mintz * @param p_hwfn - hw function 389fe56b9e6SYuval Mintz * @param p_ptt - PTT required for register access 390fe56b9e6SYuval Mintz * @param cmd - command to be sent to the MCP. 391fe56b9e6SYuval Mintz * @param param - Optional param 392fe56b9e6SYuval Mintz * @param o_mcp_resp - The MCP response code (exclude sequence). 393fe56b9e6SYuval Mintz * @param o_mcp_param- Optional parameter provided by the MCP 394fe56b9e6SYuval Mintz * response 395fe56b9e6SYuval Mintz * @return int - 0 - operation 396fe56b9e6SYuval Mintz * was successul. 397fe56b9e6SYuval Mintz */ 398fe56b9e6SYuval Mintz int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 399fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 400fe56b9e6SYuval Mintz u32 cmd, 401fe56b9e6SYuval Mintz u32 param, 402fe56b9e6SYuval Mintz u32 *o_mcp_resp, 403fe56b9e6SYuval Mintz u32 *o_mcp_param); 404fe56b9e6SYuval Mintz 405fe56b9e6SYuval Mintz /** 406fe56b9e6SYuval Mintz * @brief - drains the nig, allowing completion to pass in case of pauses. 407fe56b9e6SYuval Mintz * (Should be called only from sleepable context) 408fe56b9e6SYuval Mintz * 409fe56b9e6SYuval Mintz * @param p_hwfn 410fe56b9e6SYuval Mintz * @param p_ptt 411fe56b9e6SYuval Mintz */ 412fe56b9e6SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, 413fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 414fe56b9e6SYuval Mintz 415fe56b9e6SYuval Mintz /** 416cee4d264SManish Chopra * @brief Get the flash size value 417cee4d264SManish Chopra * 418cee4d264SManish Chopra * @param p_hwfn 419cee4d264SManish Chopra * @param p_ptt 420cee4d264SManish Chopra * @param p_flash_size - flash size in bytes to be filled. 421cee4d264SManish Chopra * 422cee4d264SManish Chopra * @return int - 0 - operation was successul. 423cee4d264SManish Chopra */ 424cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 425cee4d264SManish Chopra struct qed_ptt *p_ptt, 426cee4d264SManish Chopra u32 *p_flash_size); 427cee4d264SManish Chopra 428cee4d264SManish Chopra /** 429fe56b9e6SYuval Mintz * @brief Send driver version to MFW 430fe56b9e6SYuval Mintz * 431fe56b9e6SYuval Mintz * @param p_hwfn 432fe56b9e6SYuval Mintz * @param p_ptt 433fe56b9e6SYuval Mintz * @param version - Version value 434fe56b9e6SYuval Mintz * @param name - Protocol driver name 435fe56b9e6SYuval Mintz * 436fe56b9e6SYuval Mintz * @return int - 0 - operation was successul. 437fe56b9e6SYuval Mintz */ 438fe56b9e6SYuval Mintz int 439fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 440fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 441fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver); 442fe56b9e6SYuval Mintz 44391420b83SSudarsana Kalluru /** 4440fefbfbaSSudarsana Kalluru * @brief Notify MFW about the change in base device properties 4450fefbfbaSSudarsana Kalluru * 4460fefbfbaSSudarsana Kalluru * @param p_hwfn 4470fefbfbaSSudarsana Kalluru * @param p_ptt 4480fefbfbaSSudarsana Kalluru * @param client - qed client type 4490fefbfbaSSudarsana Kalluru * 4500fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 4510fefbfbaSSudarsana Kalluru */ 4520fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 4530fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 4540fefbfbaSSudarsana Kalluru enum qed_ov_client client); 4550fefbfbaSSudarsana Kalluru 4560fefbfbaSSudarsana Kalluru /** 4570fefbfbaSSudarsana Kalluru * @brief Notify MFW about the driver state 4580fefbfbaSSudarsana Kalluru * 4590fefbfbaSSudarsana Kalluru * @param p_hwfn 4600fefbfbaSSudarsana Kalluru * @param p_ptt 4610fefbfbaSSudarsana Kalluru * @param drv_state - Driver state 4620fefbfbaSSudarsana Kalluru * 4630fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 4640fefbfbaSSudarsana Kalluru */ 4650fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 4660fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 4670fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state); 4680fefbfbaSSudarsana Kalluru 4690fefbfbaSSudarsana Kalluru /** 4700fefbfbaSSudarsana Kalluru * @brief Send MTU size to MFW 4710fefbfbaSSudarsana Kalluru * 4720fefbfbaSSudarsana Kalluru * @param p_hwfn 4730fefbfbaSSudarsana Kalluru * @param p_ptt 4740fefbfbaSSudarsana Kalluru * @param mtu - MTU size 4750fefbfbaSSudarsana Kalluru * 4760fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 4770fefbfbaSSudarsana Kalluru */ 4780fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 4790fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu); 4800fefbfbaSSudarsana Kalluru 4810fefbfbaSSudarsana Kalluru /** 4820fefbfbaSSudarsana Kalluru * @brief Send MAC address to MFW 4830fefbfbaSSudarsana Kalluru * 4840fefbfbaSSudarsana Kalluru * @param p_hwfn 4850fefbfbaSSudarsana Kalluru * @param p_ptt 4860fefbfbaSSudarsana Kalluru * @param mac - MAC address 4870fefbfbaSSudarsana Kalluru * 4880fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 4890fefbfbaSSudarsana Kalluru */ 4900fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 4910fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac); 4920fefbfbaSSudarsana Kalluru 4930fefbfbaSSudarsana Kalluru /** 4940fefbfbaSSudarsana Kalluru * @brief Send WOL mode to MFW 4950fefbfbaSSudarsana Kalluru * 4960fefbfbaSSudarsana Kalluru * @param p_hwfn 4970fefbfbaSSudarsana Kalluru * @param p_ptt 4980fefbfbaSSudarsana Kalluru * @param wol - WOL mode 4990fefbfbaSSudarsana Kalluru * 5000fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 5010fefbfbaSSudarsana Kalluru */ 5020fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 5030fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 5040fefbfbaSSudarsana Kalluru enum qed_ov_wol wol); 5050fefbfbaSSudarsana Kalluru 5060fefbfbaSSudarsana Kalluru /** 50791420b83SSudarsana Kalluru * @brief Set LED status 50891420b83SSudarsana Kalluru * 50991420b83SSudarsana Kalluru * @param p_hwfn 51091420b83SSudarsana Kalluru * @param p_ptt 51191420b83SSudarsana Kalluru * @param mode - LED mode 51291420b83SSudarsana Kalluru * 51391420b83SSudarsana Kalluru * @return int - 0 - operation was successful. 51491420b83SSudarsana Kalluru */ 51591420b83SSudarsana Kalluru int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 51691420b83SSudarsana Kalluru struct qed_ptt *p_ptt, 51791420b83SSudarsana Kalluru enum qed_led_mode mode); 51891420b83SSudarsana Kalluru 51903dc76caSSudarsana Reddy Kalluru /** 5207a4b21b7SMintz, Yuval * @brief Read from nvm 5217a4b21b7SMintz, Yuval * 5227a4b21b7SMintz, Yuval * @param cdev 5237a4b21b7SMintz, Yuval * @param addr - nvm offset 5247a4b21b7SMintz, Yuval * @param p_buf - nvm read buffer 5257a4b21b7SMintz, Yuval * @param len - buffer len 5267a4b21b7SMintz, Yuval * 5277a4b21b7SMintz, Yuval * @return int - 0 - operation was successful. 5287a4b21b7SMintz, Yuval */ 5297a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len); 5307a4b21b7SMintz, Yuval 53162e4d438SSudarsana Reddy Kalluru /** 53262e4d438SSudarsana Reddy Kalluru * @brief Write to nvm 53362e4d438SSudarsana Reddy Kalluru * 53462e4d438SSudarsana Reddy Kalluru * @param cdev 53562e4d438SSudarsana Reddy Kalluru * @param addr - nvm offset 53662e4d438SSudarsana Reddy Kalluru * @param cmd - nvm command 53762e4d438SSudarsana Reddy Kalluru * @param p_buf - nvm write buffer 53862e4d438SSudarsana Reddy Kalluru * @param len - buffer len 53962e4d438SSudarsana Reddy Kalluru * 54062e4d438SSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 54162e4d438SSudarsana Reddy Kalluru */ 54262e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 54362e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len); 54462e4d438SSudarsana Reddy Kalluru 54562e4d438SSudarsana Reddy Kalluru /** 54662e4d438SSudarsana Reddy Kalluru * @brief Put file begin 54762e4d438SSudarsana Reddy Kalluru * 54862e4d438SSudarsana Reddy Kalluru * @param cdev 54962e4d438SSudarsana Reddy Kalluru * @param addr - nvm offset 55062e4d438SSudarsana Reddy Kalluru * 55162e4d438SSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 55262e4d438SSudarsana Reddy Kalluru */ 55362e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr); 55462e4d438SSudarsana Reddy Kalluru 55562e4d438SSudarsana Reddy Kalluru /** 55662e4d438SSudarsana Reddy Kalluru * @brief Check latest response 55762e4d438SSudarsana Reddy Kalluru * 55862e4d438SSudarsana Reddy Kalluru * @param cdev 55962e4d438SSudarsana Reddy Kalluru * @param p_buf - nvm write buffer 56062e4d438SSudarsana Reddy Kalluru * 56162e4d438SSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 56262e4d438SSudarsana Reddy Kalluru */ 56362e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf); 56462e4d438SSudarsana Reddy Kalluru 56520675b37SMintz, Yuval struct qed_nvm_image_att { 56620675b37SMintz, Yuval u32 start_addr; 56720675b37SMintz, Yuval u32 length; 56820675b37SMintz, Yuval }; 56920675b37SMintz, Yuval 57020675b37SMintz, Yuval /** 57120675b37SMintz, Yuval * @brief Allows reading a whole nvram image 57220675b37SMintz, Yuval * 57320675b37SMintz, Yuval * @param p_hwfn 5741ac4329aSDenis Bolotin * @param image_id - image to get attributes for 5751ac4329aSDenis Bolotin * @param p_image_att - image attributes structure into which to fill data 5761ac4329aSDenis Bolotin * 5771ac4329aSDenis Bolotin * @return int - 0 - operation was successful. 5781ac4329aSDenis Bolotin */ 5791ac4329aSDenis Bolotin int 5801ac4329aSDenis Bolotin qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 5811ac4329aSDenis Bolotin enum qed_nvm_images image_id, 5821ac4329aSDenis Bolotin struct qed_nvm_image_att *p_image_att); 5831ac4329aSDenis Bolotin 5841ac4329aSDenis Bolotin /** 5851ac4329aSDenis Bolotin * @brief Allows reading a whole nvram image 5861ac4329aSDenis Bolotin * 5871ac4329aSDenis Bolotin * @param p_hwfn 58820675b37SMintz, Yuval * @param image_id - image requested for reading 58920675b37SMintz, Yuval * @param p_buffer - allocated buffer into which to fill data 59020675b37SMintz, Yuval * @param buffer_len - length of the allocated buffer. 59120675b37SMintz, Yuval * 59220675b37SMintz, Yuval * @return 0 iff p_buffer now contains the nvram image. 59320675b37SMintz, Yuval */ 59420675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 59520675b37SMintz, Yuval enum qed_nvm_images image_id, 59620675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len); 59720675b37SMintz, Yuval 5987a4b21b7SMintz, Yuval /** 59903dc76caSSudarsana Reddy Kalluru * @brief Bist register test 60003dc76caSSudarsana Reddy Kalluru * 60103dc76caSSudarsana Reddy Kalluru * @param p_hwfn - hw function 60203dc76caSSudarsana Reddy Kalluru * @param p_ptt - PTT required for register access 60303dc76caSSudarsana Reddy Kalluru * 60403dc76caSSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 60503dc76caSSudarsana Reddy Kalluru */ 60603dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, 60703dc76caSSudarsana Reddy Kalluru struct qed_ptt *p_ptt); 60803dc76caSSudarsana Reddy Kalluru 60903dc76caSSudarsana Reddy Kalluru /** 61003dc76caSSudarsana Reddy Kalluru * @brief Bist clock test 61103dc76caSSudarsana Reddy Kalluru * 61203dc76caSSudarsana Reddy Kalluru * @param p_hwfn - hw function 61303dc76caSSudarsana Reddy Kalluru * @param p_ptt - PTT required for register access 61403dc76caSSudarsana Reddy Kalluru * 61503dc76caSSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 61603dc76caSSudarsana Reddy Kalluru */ 61703dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, 61803dc76caSSudarsana Reddy Kalluru struct qed_ptt *p_ptt); 61903dc76caSSudarsana Reddy Kalluru 6207a4b21b7SMintz, Yuval /** 6217a4b21b7SMintz, Yuval * @brief Bist nvm test - get number of images 6227a4b21b7SMintz, Yuval * 6237a4b21b7SMintz, Yuval * @param p_hwfn - hw function 6247a4b21b7SMintz, Yuval * @param p_ptt - PTT required for register access 6257a4b21b7SMintz, Yuval * @param num_images - number of images if operation was 6267a4b21b7SMintz, Yuval * successful. 0 if not. 6277a4b21b7SMintz, Yuval * 6287a4b21b7SMintz, Yuval * @return int - 0 - operation was successful. 6297a4b21b7SMintz, Yuval */ 63043645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 6317a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 6327a4b21b7SMintz, Yuval u32 *num_images); 6337a4b21b7SMintz, Yuval 6347a4b21b7SMintz, Yuval /** 6357a4b21b7SMintz, Yuval * @brief Bist nvm test - get image attributes by index 6367a4b21b7SMintz, Yuval * 6377a4b21b7SMintz, Yuval * @param p_hwfn - hw function 6387a4b21b7SMintz, Yuval * @param p_ptt - PTT required for register access 6397a4b21b7SMintz, Yuval * @param p_image_att - Attributes of image 6407a4b21b7SMintz, Yuval * @param image_index - Index of image to get information for 6417a4b21b7SMintz, Yuval * 6427a4b21b7SMintz, Yuval * @return int - 0 - operation was successful. 6437a4b21b7SMintz, Yuval */ 64443645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 6457a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 6467a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 6477a4b21b7SMintz, Yuval u32 image_index); 6487a4b21b7SMintz, Yuval 6492528c389SSudarsana Reddy Kalluru /** 6502528c389SSudarsana Reddy Kalluru * @brief - Processes the TLV request from MFW i.e., get the required TLV info 6512528c389SSudarsana Reddy Kalluru * from the qed client and send it to the MFW. 6522528c389SSudarsana Reddy Kalluru * 6532528c389SSudarsana Reddy Kalluru * @param p_hwfn 6542528c389SSudarsana Reddy Kalluru * @param p_ptt 6552528c389SSudarsana Reddy Kalluru * 6562528c389SSudarsana Reddy Kalluru * @param return 0 upon success. 6572528c389SSudarsana Reddy Kalluru */ 6582528c389SSudarsana Reddy Kalluru int qed_mfw_process_tlv_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 6592528c389SSudarsana Reddy Kalluru 660fe56b9e6SYuval Mintz /* Using hwfn number (and not pf_num) is required since in CMT mode, 661fe56b9e6SYuval Mintz * same pf_num may be used by two different hwfn 662fe56b9e6SYuval Mintz * TODO - this shouldn't really be in .h file, but until all fields 663fe56b9e6SYuval Mintz * required during hw-init will be placed in their correct place in shmem 664fe56b9e6SYuval Mintz * we need it in qed_dev.c [for readin the nvram reflection in shmem]. 665fe56b9e6SYuval Mintz */ 666fe56b9e6SYuval Mintz #define MCP_PF_ID_BY_REL(p_hwfn, rel_pfid) (QED_IS_BB((p_hwfn)->cdev) ? \ 667fe56b9e6SYuval Mintz ((rel_pfid) | \ 668fe56b9e6SYuval Mintz ((p_hwfn)->abs_pf_id & 1) << 3) : \ 669fe56b9e6SYuval Mintz rel_pfid) 670fe56b9e6SYuval Mintz #define MCP_PF_ID(p_hwfn) MCP_PF_ID_BY_REL(p_hwfn, (p_hwfn)->rel_pf_id) 671fe56b9e6SYuval Mintz 672fe56b9e6SYuval Mintz #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \ 67378cea9ffSTomer Tayar ((_p_hwfn)->cdev->num_ports_in_engine * \ 6749c79ddaaSMintz, Yuval qed_device_num_engines((_p_hwfn)->cdev))) 6759c79ddaaSMintz, Yuval 676fe56b9e6SYuval Mintz struct qed_mcp_info { 6774ed1eea8STomer Tayar /* List for mailbox commands which were sent and wait for a response */ 6784ed1eea8STomer Tayar struct list_head cmd_list; 6794ed1eea8STomer Tayar 6804ed1eea8STomer Tayar /* Spinlock used for protecting the access to the mailbox commands list 6814ed1eea8STomer Tayar * and the sending of the commands. 6824ed1eea8STomer Tayar */ 6834ed1eea8STomer Tayar spinlock_t cmd_lock; 68465ed2ffdSMintz, Yuval 685b310974eSTomer Tayar /* Flag to indicate whether sending a MFW mailbox command is blocked */ 686b310974eSTomer Tayar bool b_block_cmd; 687b310974eSTomer Tayar 68865ed2ffdSMintz, Yuval /* Spinlock used for syncing SW link-changes and link-changes 68965ed2ffdSMintz, Yuval * originating from attention context. 69065ed2ffdSMintz, Yuval */ 69165ed2ffdSMintz, Yuval spinlock_t link_lock; 692b310974eSTomer Tayar 693fe56b9e6SYuval Mintz u32 public_base; 694fe56b9e6SYuval Mintz u32 drv_mb_addr; 695fe56b9e6SYuval Mintz u32 mfw_mb_addr; 696fe56b9e6SYuval Mintz u32 port_addr; 697fe56b9e6SYuval Mintz u16 drv_mb_seq; 698fe56b9e6SYuval Mintz u16 drv_pulse_seq; 699cc875c2eSYuval Mintz struct qed_mcp_link_params link_input; 700cc875c2eSYuval Mintz struct qed_mcp_link_state link_output; 701cc875c2eSYuval Mintz struct qed_mcp_link_capabilities link_capabilities; 702fe56b9e6SYuval Mintz struct qed_mcp_function_info func_info; 703fe56b9e6SYuval Mintz u8 *mfw_mb_cur; 704fe56b9e6SYuval Mintz u8 *mfw_mb_shadow; 705fe56b9e6SYuval Mintz u16 mfw_mb_length; 7064ed1eea8STomer Tayar u32 mcp_hist; 707645874e5SSudarsana Reddy Kalluru 708645874e5SSudarsana Reddy Kalluru /* Capabilties negotiated with the MFW */ 709645874e5SSudarsana Reddy Kalluru u32 capabilities; 710fe56b9e6SYuval Mintz }; 711fe56b9e6SYuval Mintz 7125529bad9STomer Tayar struct qed_mcp_mb_params { 7135529bad9STomer Tayar u32 cmd; 7145529bad9STomer Tayar u32 param; 7152f67af8cSTomer Tayar void *p_data_src; 7162f67af8cSTomer Tayar void *p_data_dst; 717eaa50fc5STomer Tayar u8 data_src_size; 7182f67af8cSTomer Tayar u8 data_dst_size; 7195529bad9STomer Tayar u32 mcp_resp; 7205529bad9STomer Tayar u32 mcp_param; 721eaa50fc5STomer Tayar u32 flags; 722eaa50fc5STomer Tayar #define QED_MB_FLAG_CAN_SLEEP (0x1 << 0) 723b310974eSTomer Tayar #define QED_MB_FLAG_AVOID_BLOCK (0x1 << 1) 724eaa50fc5STomer Tayar #define QED_MB_FLAGS_IS_SET(params, flag) \ 725eaa50fc5STomer Tayar ({ typeof(params) __params = (params); \ 726eaa50fc5STomer Tayar (__params && (__params->flags & QED_MB_FLAG_ ## flag)); }) 7275529bad9STomer Tayar }; 7285529bad9STomer Tayar 7292528c389SSudarsana Reddy Kalluru struct qed_drv_tlv_hdr { 7302528c389SSudarsana Reddy Kalluru u8 tlv_type; 7312528c389SSudarsana Reddy Kalluru u8 tlv_length; /* In dwords - not including this header */ 7322528c389SSudarsana Reddy Kalluru u8 tlv_reserved; 7332528c389SSudarsana Reddy Kalluru #define QED_DRV_TLV_FLAGS_CHANGED 0x01 7342528c389SSudarsana Reddy Kalluru u8 tlv_flags; 7352528c389SSudarsana Reddy Kalluru }; 7362528c389SSudarsana Reddy Kalluru 737fe56b9e6SYuval Mintz /** 738fe56b9e6SYuval Mintz * @brief Initialize the interface with the MCP 739fe56b9e6SYuval Mintz * 740fe56b9e6SYuval Mintz * @param p_hwfn - HW func 741fe56b9e6SYuval Mintz * @param p_ptt - PTT required for register access 742fe56b9e6SYuval Mintz * 743fe56b9e6SYuval Mintz * @return int 744fe56b9e6SYuval Mintz */ 745fe56b9e6SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, 746fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 747fe56b9e6SYuval Mintz 748fe56b9e6SYuval Mintz /** 749fe56b9e6SYuval Mintz * @brief Initialize the port interface with the MCP 750fe56b9e6SYuval Mintz * 751fe56b9e6SYuval Mintz * @param p_hwfn 752fe56b9e6SYuval Mintz * @param p_ptt 753fe56b9e6SYuval Mintz * Can only be called after `num_ports_in_engines' is set 754fe56b9e6SYuval Mintz */ 755fe56b9e6SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, 756fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 757fe56b9e6SYuval Mintz /** 758fe56b9e6SYuval Mintz * @brief Releases resources allocated during the init process. 759fe56b9e6SYuval Mintz * 760fe56b9e6SYuval Mintz * @param p_hwfn - HW func 761fe56b9e6SYuval Mintz * @param p_ptt - PTT required for register access 762fe56b9e6SYuval Mintz * 763fe56b9e6SYuval Mintz * @return int 764fe56b9e6SYuval Mintz */ 765fe56b9e6SYuval Mintz 766fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn); 767fe56b9e6SYuval Mintz 768fe56b9e6SYuval Mintz /** 769cc875c2eSYuval Mintz * @brief This function is called from the DPC context. After 770cc875c2eSYuval Mintz * pointing PTT to the mfw mb, check for events sent by the MCP 771cc875c2eSYuval Mintz * to the driver and ack them. In case a critical event 772cc875c2eSYuval Mintz * detected, it will be handled here, otherwise the work will be 773cc875c2eSYuval Mintz * queued to a sleepable work-queue. 774cc875c2eSYuval Mintz * 775cc875c2eSYuval Mintz * @param p_hwfn - HW function 776cc875c2eSYuval Mintz * @param p_ptt - PTT required for register access 777cc875c2eSYuval Mintz * @return int - 0 - operation 778cc875c2eSYuval Mintz * was successul. 779cc875c2eSYuval Mintz */ 780cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 781cc875c2eSYuval Mintz struct qed_ptt *p_ptt); 782cc875c2eSYuval Mintz 7835d24bcf1STomer Tayar enum qed_drv_role { 7845d24bcf1STomer Tayar QED_DRV_ROLE_OS, 7855d24bcf1STomer Tayar QED_DRV_ROLE_KDUMP, 7865d24bcf1STomer Tayar }; 7875d24bcf1STomer Tayar 7885d24bcf1STomer Tayar struct qed_load_req_params { 7895d24bcf1STomer Tayar /* Input params */ 7905d24bcf1STomer Tayar enum qed_drv_role drv_role; 7915d24bcf1STomer Tayar u8 timeout_val; 7925d24bcf1STomer Tayar bool avoid_eng_reset; 7935d24bcf1STomer Tayar enum qed_override_force_load override_force_load; 7945d24bcf1STomer Tayar 7955d24bcf1STomer Tayar /* Output params */ 7965d24bcf1STomer Tayar u32 load_code; 7975d24bcf1STomer Tayar }; 7985d24bcf1STomer Tayar 799cc875c2eSYuval Mintz /** 8005d24bcf1STomer Tayar * @brief Sends a LOAD_REQ to the MFW, and in case the operation succeeds, 8015d24bcf1STomer Tayar * returns whether this PF is the first on the engine/port or function. 802fe56b9e6SYuval Mintz * 8035d24bcf1STomer Tayar * @param p_hwfn 8045d24bcf1STomer Tayar * @param p_ptt 8055d24bcf1STomer Tayar * @param p_params 8065d24bcf1STomer Tayar * 8075d24bcf1STomer Tayar * @return int - 0 - Operation was successful. 808fe56b9e6SYuval Mintz */ 809fe56b9e6SYuval Mintz int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 810fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 8115d24bcf1STomer Tayar struct qed_load_req_params *p_params); 812fe56b9e6SYuval Mintz 813fe56b9e6SYuval Mintz /** 8141226337aSTomer Tayar * @brief Sends a UNLOAD_REQ message to the MFW 8151226337aSTomer Tayar * 8161226337aSTomer Tayar * @param p_hwfn 8171226337aSTomer Tayar * @param p_ptt 8181226337aSTomer Tayar * 8191226337aSTomer Tayar * @return int - 0 - Operation was successful. 8201226337aSTomer Tayar */ 8211226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 8221226337aSTomer Tayar 8231226337aSTomer Tayar /** 8241226337aSTomer Tayar * @brief Sends a UNLOAD_DONE message to the MFW 8251226337aSTomer Tayar * 8261226337aSTomer Tayar * @param p_hwfn 8271226337aSTomer Tayar * @param p_ptt 8281226337aSTomer Tayar * 8291226337aSTomer Tayar * @return int - 0 - Operation was successful. 8301226337aSTomer Tayar */ 8311226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 8321226337aSTomer Tayar 8331226337aSTomer Tayar /** 834fe56b9e6SYuval Mintz * @brief Read the MFW mailbox into Current buffer. 835fe56b9e6SYuval Mintz * 836fe56b9e6SYuval Mintz * @param p_hwfn 837fe56b9e6SYuval Mintz * @param p_ptt 838fe56b9e6SYuval Mintz */ 839fe56b9e6SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, 840fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 841fe56b9e6SYuval Mintz 842fe56b9e6SYuval Mintz /** 8430b55e27dSYuval Mintz * @brief Ack to mfw that driver finished FLR process for VFs 8440b55e27dSYuval Mintz * 8450b55e27dSYuval Mintz * @param p_hwfn 8460b55e27dSYuval Mintz * @param p_ptt 8470b55e27dSYuval Mintz * @param vfs_to_ack - bit mask of all engine VFs for which the PF acks. 8480b55e27dSYuval Mintz * 8490b55e27dSYuval Mintz * @param return int - 0 upon success. 8500b55e27dSYuval Mintz */ 8510b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 8520b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack); 8530b55e27dSYuval Mintz 8540b55e27dSYuval Mintz /** 855fe56b9e6SYuval Mintz * @brief - calls during init to read shmem of all function-related info. 856fe56b9e6SYuval Mintz * 857fe56b9e6SYuval Mintz * @param p_hwfn 858fe56b9e6SYuval Mintz * 859fe56b9e6SYuval Mintz * @param return 0 upon success. 860fe56b9e6SYuval Mintz */ 861fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 862fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 863fe56b9e6SYuval Mintz 864fe56b9e6SYuval Mintz /** 865fe56b9e6SYuval Mintz * @brief - Reset the MCP using mailbox command. 866fe56b9e6SYuval Mintz * 867fe56b9e6SYuval Mintz * @param p_hwfn 868fe56b9e6SYuval Mintz * @param p_ptt 869fe56b9e6SYuval Mintz * 870fe56b9e6SYuval Mintz * @param return 0 upon success. 871fe56b9e6SYuval Mintz */ 872fe56b9e6SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, 873fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 874fe56b9e6SYuval Mintz 875fe56b9e6SYuval Mintz /** 8764102426fSTomer Tayar * @brief - Sends an NVM read command request to the MFW to get 8774102426fSTomer Tayar * a buffer. 8784102426fSTomer Tayar * 8794102426fSTomer Tayar * @param p_hwfn 8804102426fSTomer Tayar * @param p_ptt 8814102426fSTomer Tayar * @param cmd - Command: DRV_MSG_CODE_NVM_GET_FILE_DATA or 8824102426fSTomer Tayar * DRV_MSG_CODE_NVM_READ_NVRAM commands 8834102426fSTomer Tayar * @param param - [0:23] - Offset [24:31] - Size 8844102426fSTomer Tayar * @param o_mcp_resp - MCP response 8854102426fSTomer Tayar * @param o_mcp_param - MCP response param 8864102426fSTomer Tayar * @param o_txn_size - Buffer size output 8874102426fSTomer Tayar * @param o_buf - Pointer to the buffer returned by the MFW. 8884102426fSTomer Tayar * 8894102426fSTomer Tayar * @param return 0 upon success. 8904102426fSTomer Tayar */ 8914102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 8924102426fSTomer Tayar struct qed_ptt *p_ptt, 8934102426fSTomer Tayar u32 cmd, 8944102426fSTomer Tayar u32 param, 8954102426fSTomer Tayar u32 *o_mcp_resp, 8964102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf); 8974102426fSTomer Tayar 8984102426fSTomer Tayar /** 899b51dab46SSudarsana Reddy Kalluru * @brief Read from sfp 900b51dab46SSudarsana Reddy Kalluru * 901b51dab46SSudarsana Reddy Kalluru * @param p_hwfn - hw function 902b51dab46SSudarsana Reddy Kalluru * @param p_ptt - PTT required for register access 903b51dab46SSudarsana Reddy Kalluru * @param port - transceiver port 904b51dab46SSudarsana Reddy Kalluru * @param addr - I2C address 905b51dab46SSudarsana Reddy Kalluru * @param offset - offset in sfp 906b51dab46SSudarsana Reddy Kalluru * @param len - buffer length 907b51dab46SSudarsana Reddy Kalluru * @param p_buf - buffer to read into 908b51dab46SSudarsana Reddy Kalluru * 909b51dab46SSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 910b51dab46SSudarsana Reddy Kalluru */ 911b51dab46SSudarsana Reddy Kalluru int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 912b51dab46SSudarsana Reddy Kalluru u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf); 913b51dab46SSudarsana Reddy Kalluru 914b51dab46SSudarsana Reddy Kalluru /** 915fe56b9e6SYuval Mintz * @brief indicates whether the MFW objects [under mcp_info] are accessible 916fe56b9e6SYuval Mintz * 917fe56b9e6SYuval Mintz * @param p_hwfn 918fe56b9e6SYuval Mintz * 919fe56b9e6SYuval Mintz * @return true iff MFW is running and mcp_info is initialized 920fe56b9e6SYuval Mintz */ 921fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn); 9221408cc1fSYuval Mintz 9231408cc1fSYuval Mintz /** 9241408cc1fSYuval Mintz * @brief request MFW to configure MSI-X for a VF 9251408cc1fSYuval Mintz * 9261408cc1fSYuval Mintz * @param p_hwfn 9271408cc1fSYuval Mintz * @param p_ptt 9281408cc1fSYuval Mintz * @param vf_id - absolute inside engine 9291408cc1fSYuval Mintz * @param num_sbs - number of entries to request 9301408cc1fSYuval Mintz * 9311408cc1fSYuval Mintz * @return int 9321408cc1fSYuval Mintz */ 9331408cc1fSYuval Mintz int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 9341408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num); 9351408cc1fSYuval Mintz 9364102426fSTomer Tayar /** 9374102426fSTomer Tayar * @brief - Halt the MCP. 9384102426fSTomer Tayar * 9394102426fSTomer Tayar * @param p_hwfn 9404102426fSTomer Tayar * @param p_ptt 9414102426fSTomer Tayar * 9424102426fSTomer Tayar * @param return 0 upon success. 9434102426fSTomer Tayar */ 9444102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 9454102426fSTomer Tayar 9464102426fSTomer Tayar /** 9474102426fSTomer Tayar * @brief - Wake up the MCP. 9484102426fSTomer Tayar * 9494102426fSTomer Tayar * @param p_hwfn 9504102426fSTomer Tayar * @param p_ptt 9514102426fSTomer Tayar * 9524102426fSTomer Tayar * @param return 0 upon success. 9534102426fSTomer Tayar */ 9544102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 9554102426fSTomer Tayar 956a64b02d5SManish Chopra int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw); 9574b01e519SManish Chopra int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw); 9584b01e519SManish Chopra int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 9594b01e519SManish Chopra struct qed_ptt *p_ptt, 9604b01e519SManish Chopra struct qed_mcp_link_state *p_link, 9614b01e519SManish Chopra u8 max_bw); 962a64b02d5SManish Chopra int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 963a64b02d5SManish Chopra struct qed_ptt *p_ptt, 964a64b02d5SManish Chopra struct qed_mcp_link_state *p_link, 965a64b02d5SManish Chopra u8 min_bw); 966351a4dedSYuval Mintz 9674102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 9684102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities); 9694102426fSTomer Tayar 9700fefbfbaSSudarsana Kalluru /** 9719c8517c4STomer Tayar * @brief - Sets the MFW's max value for the given resource 9729c8517c4STomer Tayar * 9739c8517c4STomer Tayar * @param p_hwfn 9749c8517c4STomer Tayar * @param p_ptt 9759c8517c4STomer Tayar * @param res_id 9769c8517c4STomer Tayar * @param resc_max_val 9779c8517c4STomer Tayar * @param p_mcp_resp 9789c8517c4STomer Tayar * 9799c8517c4STomer Tayar * @return int - 0 - operation was successful. 9809c8517c4STomer Tayar */ 9819c8517c4STomer Tayar int 9829c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 9839c8517c4STomer Tayar struct qed_ptt *p_ptt, 9849c8517c4STomer Tayar enum qed_resources res_id, 9859c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp); 9869c8517c4STomer Tayar 9879c8517c4STomer Tayar /** 9889c8517c4STomer Tayar * @brief - Gets the MFW allocation info for the given resource 9899c8517c4STomer Tayar * 9909c8517c4STomer Tayar * @param p_hwfn 9919c8517c4STomer Tayar * @param p_ptt 9929c8517c4STomer Tayar * @param res_id 9939c8517c4STomer Tayar * @param p_mcp_resp 9949c8517c4STomer Tayar * @param p_resc_num 9959c8517c4STomer Tayar * @param p_resc_start 9969c8517c4STomer Tayar * 9979c8517c4STomer Tayar * @return int - 0 - operation was successful. 9989c8517c4STomer Tayar */ 9999c8517c4STomer Tayar int 10009c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 10019c8517c4STomer Tayar struct qed_ptt *p_ptt, 10029c8517c4STomer Tayar enum qed_resources res_id, 10039c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start); 10049c8517c4STomer Tayar 10059c8517c4STomer Tayar /** 10060fefbfbaSSudarsana Kalluru * @brief Send eswitch mode to MFW 10070fefbfbaSSudarsana Kalluru * 10080fefbfbaSSudarsana Kalluru * @param p_hwfn 10090fefbfbaSSudarsana Kalluru * @param p_ptt 10100fefbfbaSSudarsana Kalluru * @param eswitch - eswitch mode 10110fefbfbaSSudarsana Kalluru * 10120fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 10130fefbfbaSSudarsana Kalluru */ 10140fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 10150fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 10160fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch); 10170fefbfbaSSudarsana Kalluru 10189c8517c4STomer Tayar #define QED_MCP_RESC_LOCK_MIN_VAL RESOURCE_DUMP 10199c8517c4STomer Tayar #define QED_MCP_RESC_LOCK_MAX_VAL 31 10209c8517c4STomer Tayar 10219c8517c4STomer Tayar enum qed_resc_lock { 10229c8517c4STomer Tayar QED_RESC_LOCK_DBG_DUMP = QED_MCP_RESC_LOCK_MIN_VAL, 1023db82f70eSsudarsana.kalluru@cavium.com QED_RESC_LOCK_PTP_PORT0, 1024db82f70eSsudarsana.kalluru@cavium.com QED_RESC_LOCK_PTP_PORT1, 1025db82f70eSsudarsana.kalluru@cavium.com QED_RESC_LOCK_PTP_PORT2, 1026db82f70eSsudarsana.kalluru@cavium.com QED_RESC_LOCK_PTP_PORT3, 1027f470f22cSsudarsana.kalluru@cavium.com QED_RESC_LOCK_RESC_ALLOC = QED_MCP_RESC_LOCK_MAX_VAL, 1028f470f22cSsudarsana.kalluru@cavium.com QED_RESC_LOCK_RESC_INVALID 10299c8517c4STomer Tayar }; 103018a69e36SMintz, Yuval 103118a69e36SMintz, Yuval /** 103218a69e36SMintz, Yuval * @brief - Initiates PF FLR 103318a69e36SMintz, Yuval * 103418a69e36SMintz, Yuval * @param p_hwfn 103518a69e36SMintz, Yuval * @param p_ptt 103618a69e36SMintz, Yuval * 103718a69e36SMintz, Yuval * @return int - 0 - operation was successful. 103818a69e36SMintz, Yuval */ 103918a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 104095691c9cSTomer Tayar struct qed_resc_lock_params { 104195691c9cSTomer Tayar /* Resource number [valid values are 0..31] */ 104295691c9cSTomer Tayar u8 resource; 104395691c9cSTomer Tayar 104495691c9cSTomer Tayar /* Lock timeout value in seconds [default, none or 1..254] */ 104595691c9cSTomer Tayar u8 timeout; 104695691c9cSTomer Tayar #define QED_MCP_RESC_LOCK_TO_DEFAULT 0 104795691c9cSTomer Tayar #define QED_MCP_RESC_LOCK_TO_NONE 255 104895691c9cSTomer Tayar 104995691c9cSTomer Tayar /* Number of times to retry locking */ 105095691c9cSTomer Tayar u8 retry_num; 1051f470f22cSsudarsana.kalluru@cavium.com #define QED_MCP_RESC_LOCK_RETRY_CNT_DFLT 10 105295691c9cSTomer Tayar 105395691c9cSTomer Tayar /* The interval in usec between retries */ 105495691c9cSTomer Tayar u16 retry_interval; 1055f470f22cSsudarsana.kalluru@cavium.com #define QED_MCP_RESC_LOCK_RETRY_VAL_DFLT 10000 105695691c9cSTomer Tayar 105795691c9cSTomer Tayar /* Use sleep or delay between retries */ 105895691c9cSTomer Tayar bool sleep_b4_retry; 105995691c9cSTomer Tayar 106095691c9cSTomer Tayar /* Will be set as true if the resource is free and granted */ 106195691c9cSTomer Tayar bool b_granted; 106295691c9cSTomer Tayar 106395691c9cSTomer Tayar /* Will be filled with the resource owner. 106495691c9cSTomer Tayar * [0..15 = PF0-15, 16 = MFW] 106595691c9cSTomer Tayar */ 106695691c9cSTomer Tayar u8 owner; 106795691c9cSTomer Tayar }; 106895691c9cSTomer Tayar 106995691c9cSTomer Tayar /** 107095691c9cSTomer Tayar * @brief Acquires MFW generic resource lock 107195691c9cSTomer Tayar * 107295691c9cSTomer Tayar * @param p_hwfn 107395691c9cSTomer Tayar * @param p_ptt 107495691c9cSTomer Tayar * @param p_params 107595691c9cSTomer Tayar * 107695691c9cSTomer Tayar * @return int - 0 - operation was successful. 107795691c9cSTomer Tayar */ 107895691c9cSTomer Tayar int 107995691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 108095691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params); 108195691c9cSTomer Tayar 108295691c9cSTomer Tayar struct qed_resc_unlock_params { 108395691c9cSTomer Tayar /* Resource number [valid values are 0..31] */ 108495691c9cSTomer Tayar u8 resource; 108595691c9cSTomer Tayar 108695691c9cSTomer Tayar /* Allow to release a resource even if belongs to another PF */ 108795691c9cSTomer Tayar bool b_force; 108895691c9cSTomer Tayar 108995691c9cSTomer Tayar /* Will be set as true if the resource is released */ 109095691c9cSTomer Tayar bool b_released; 109195691c9cSTomer Tayar }; 109295691c9cSTomer Tayar 109395691c9cSTomer Tayar /** 109495691c9cSTomer Tayar * @brief Releases MFW generic resource lock 109595691c9cSTomer Tayar * 109695691c9cSTomer Tayar * @param p_hwfn 109795691c9cSTomer Tayar * @param p_ptt 109895691c9cSTomer Tayar * @param p_params 109995691c9cSTomer Tayar * 110095691c9cSTomer Tayar * @return int - 0 - operation was successful. 110195691c9cSTomer Tayar */ 110295691c9cSTomer Tayar int 110395691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 110495691c9cSTomer Tayar struct qed_ptt *p_ptt, 110595691c9cSTomer Tayar struct qed_resc_unlock_params *p_params); 110695691c9cSTomer Tayar 1107f470f22cSsudarsana.kalluru@cavium.com /** 1108f470f22cSsudarsana.kalluru@cavium.com * @brief - default initialization for lock/unlock resource structs 1109f470f22cSsudarsana.kalluru@cavium.com * 1110f470f22cSsudarsana.kalluru@cavium.com * @param p_lock - lock params struct to be initialized; Can be NULL 1111f470f22cSsudarsana.kalluru@cavium.com * @param p_unlock - unlock params struct to be initialized; Can be NULL 1112f470f22cSsudarsana.kalluru@cavium.com * @param resource - the requested resource 1113f470f22cSsudarsana.kalluru@cavium.com * @paral b_is_permanent - disable retries & aging when set 1114f470f22cSsudarsana.kalluru@cavium.com */ 1115f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 1116f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 1117f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 1118f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent); 1119645874e5SSudarsana Reddy Kalluru /** 1120645874e5SSudarsana Reddy Kalluru * @brief Learn of supported MFW features; To be done during early init 1121645874e5SSudarsana Reddy Kalluru * 1122645874e5SSudarsana Reddy Kalluru * @param p_hwfn 1123645874e5SSudarsana Reddy Kalluru * @param p_ptt 1124645874e5SSudarsana Reddy Kalluru */ 1125645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1126f470f22cSsudarsana.kalluru@cavium.com 1127645874e5SSudarsana Reddy Kalluru /** 1128645874e5SSudarsana Reddy Kalluru * @brief Inform MFW of set of features supported by driver. Should be done 1129645874e5SSudarsana Reddy Kalluru * inside the content of the LOAD_REQ. 1130645874e5SSudarsana Reddy Kalluru * 1131645874e5SSudarsana Reddy Kalluru * @param p_hwfn 1132645874e5SSudarsana Reddy Kalluru * @param p_ptt 1133645874e5SSudarsana Reddy Kalluru */ 1134645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 113543645ce0SSudarsana Reddy Kalluru 113643645ce0SSudarsana Reddy Kalluru /** 1137cac6f691SSudarsana Reddy Kalluru * @brief Read ufp config from the shared memory. 1138cac6f691SSudarsana Reddy Kalluru * 1139cac6f691SSudarsana Reddy Kalluru * @param p_hwfn 1140cac6f691SSudarsana Reddy Kalluru * @param p_ptt 1141cac6f691SSudarsana Reddy Kalluru */ 1142cac6f691SSudarsana Reddy Kalluru void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1143cac6f691SSudarsana Reddy Kalluru 1144cac6f691SSudarsana Reddy Kalluru /** 114543645ce0SSudarsana Reddy Kalluru * @brief Populate the nvm info shadow in the given hardware function 114643645ce0SSudarsana Reddy Kalluru * 114743645ce0SSudarsana Reddy Kalluru * @param p_hwfn 114843645ce0SSudarsana Reddy Kalluru */ 114943645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn); 115043645ce0SSudarsana Reddy Kalluru 1151fe56b9e6SYuval Mintz #endif 1152