1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <asm/byteorder.h> 35 #include <linux/delay.h> 36 #include <linux/errno.h> 37 #include <linux/kernel.h> 38 #include <linux/slab.h> 39 #include <linux/spinlock.h> 40 #include <linux/string.h> 41 #include <linux/etherdevice.h> 42 #include "qed.h" 43 #include "qed_dcbx.h" 44 #include "qed_hsi.h" 45 #include "qed_hw.h" 46 #include "qed_mcp.h" 47 #include "qed_reg_addr.h" 48 #include "qed_sriov.h" 49 50 #define CHIP_MCP_RESP_ITER_US 10 51 52 #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 53 #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 54 55 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 56 qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 57 _val) 58 59 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 60 qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 61 62 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 63 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 64 offsetof(struct public_drv_mb, _field), _val) 65 66 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 67 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 68 offsetof(struct public_drv_mb, _field)) 69 70 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 71 DRV_ID_PDA_COMP_VER_SHIFT) 72 73 #define MCP_BYTES_PER_MBIT_SHIFT 17 74 75 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 76 { 77 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 78 return false; 79 return true; 80 } 81 82 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 83 { 84 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 85 PUBLIC_PORT); 86 u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 87 88 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 89 MFW_PORT(p_hwfn)); 90 DP_VERBOSE(p_hwfn, QED_MSG_SP, 91 "port_addr = 0x%x, port_id 0x%02x\n", 92 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 93 } 94 95 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 96 { 97 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 98 u32 tmp, i; 99 100 if (!p_hwfn->mcp_info->public_base) 101 return; 102 103 for (i = 0; i < length; i++) { 104 tmp = qed_rd(p_hwfn, p_ptt, 105 p_hwfn->mcp_info->mfw_mb_addr + 106 (i << 2) + sizeof(u32)); 107 108 /* The MB data is actually BE; Need to force it to cpu */ 109 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 110 be32_to_cpu((__force __be32)tmp); 111 } 112 } 113 114 int qed_mcp_free(struct qed_hwfn *p_hwfn) 115 { 116 if (p_hwfn->mcp_info) { 117 kfree(p_hwfn->mcp_info->mfw_mb_cur); 118 kfree(p_hwfn->mcp_info->mfw_mb_shadow); 119 } 120 kfree(p_hwfn->mcp_info); 121 122 return 0; 123 } 124 125 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 126 { 127 struct qed_mcp_info *p_info = p_hwfn->mcp_info; 128 u32 drv_mb_offsize, mfw_mb_offsize; 129 u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 130 131 p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 132 if (!p_info->public_base) 133 return 0; 134 135 p_info->public_base |= GRCBASE_MCP; 136 137 /* Calculate the driver and MFW mailbox address */ 138 drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 139 SECTION_OFFSIZE_ADDR(p_info->public_base, 140 PUBLIC_DRV_MB)); 141 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 142 DP_VERBOSE(p_hwfn, QED_MSG_SP, 143 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 144 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 145 146 /* Set the MFW MB address */ 147 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 148 SECTION_OFFSIZE_ADDR(p_info->public_base, 149 PUBLIC_MFW_MB)); 150 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 151 p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr); 152 153 /* Get the current driver mailbox sequence before sending 154 * the first command 155 */ 156 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 157 DRV_MSG_SEQ_NUMBER_MASK; 158 159 /* Get current FW pulse sequence */ 160 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 161 DRV_PULSE_SEQ_MASK; 162 163 p_info->mcp_hist = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 164 165 return 0; 166 } 167 168 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 169 { 170 struct qed_mcp_info *p_info; 171 u32 size; 172 173 /* Allocate mcp_info structure */ 174 p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 175 if (!p_hwfn->mcp_info) 176 goto err; 177 p_info = p_hwfn->mcp_info; 178 179 if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 180 DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 181 /* Do not free mcp_info here, since public_base indicate that 182 * the MCP is not initialized 183 */ 184 return 0; 185 } 186 187 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 188 p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 189 p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 190 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr) 191 goto err; 192 193 /* Initialize the MFW spinlock */ 194 spin_lock_init(&p_info->lock); 195 196 return 0; 197 198 err: 199 qed_mcp_free(p_hwfn); 200 return -ENOMEM; 201 } 202 203 /* Locks the MFW mailbox of a PF to ensure a single access. 204 * The lock is achieved in most cases by holding a spinlock, causing other 205 * threads to wait till a previous access is done. 206 * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single 207 * access is achieved by setting a blocking flag, which will fail other 208 * competing contexts to send their mailboxes. 209 */ 210 static int qed_mcp_mb_lock(struct qed_hwfn *p_hwfn, u32 cmd) 211 { 212 spin_lock_bh(&p_hwfn->mcp_info->lock); 213 214 /* The spinlock shouldn't be acquired when the mailbox command is 215 * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel 216 * pending [UN]LOAD_REQ command of another PF together with a spinlock 217 * (i.e. interrupts are disabled) - can lead to a deadlock. 218 * It is assumed that for a single PF, no other mailbox commands can be 219 * sent from another context while sending LOAD_REQ, and that any 220 * parallel commands to UNLOAD_REQ can be cancelled. 221 */ 222 if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE) 223 p_hwfn->mcp_info->block_mb_sending = false; 224 225 if (p_hwfn->mcp_info->block_mb_sending) { 226 DP_NOTICE(p_hwfn, 227 "Trying to send a MFW mailbox command [0x%x] in parallel to [UN]LOAD_REQ. Aborting.\n", 228 cmd); 229 spin_unlock_bh(&p_hwfn->mcp_info->lock); 230 return -EBUSY; 231 } 232 233 if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) { 234 p_hwfn->mcp_info->block_mb_sending = true; 235 spin_unlock_bh(&p_hwfn->mcp_info->lock); 236 } 237 238 return 0; 239 } 240 241 static void qed_mcp_mb_unlock(struct qed_hwfn *p_hwfn, u32 cmd) 242 { 243 if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ) 244 spin_unlock_bh(&p_hwfn->mcp_info->lock); 245 } 246 247 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 248 { 249 u32 seq = ++p_hwfn->mcp_info->drv_mb_seq; 250 u8 delay = CHIP_MCP_RESP_ITER_US; 251 u32 org_mcp_reset_seq, cnt = 0; 252 int rc = 0; 253 254 /* Ensure that only a single thread is accessing the mailbox at a 255 * certain time. 256 */ 257 rc = qed_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET); 258 if (rc != 0) 259 return rc; 260 261 /* Set drv command along with the updated sequence */ 262 org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 263 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, 264 (DRV_MSG_CODE_MCP_RESET | seq)); 265 266 do { 267 /* Wait for MFW response */ 268 udelay(delay); 269 /* Give the FW up to 500 second (50*1000*10usec) */ 270 } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 271 MISCS_REG_GENERIC_POR_0)) && 272 (cnt++ < QED_MCP_RESET_RETRIES)); 273 274 if (org_mcp_reset_seq != 275 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 276 DP_VERBOSE(p_hwfn, QED_MSG_SP, 277 "MCP was reset after %d usec\n", cnt * delay); 278 } else { 279 DP_ERR(p_hwfn, "Failed to reset MCP\n"); 280 rc = -EAGAIN; 281 } 282 283 qed_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET); 284 285 return rc; 286 } 287 288 static int qed_do_mcp_cmd(struct qed_hwfn *p_hwfn, 289 struct qed_ptt *p_ptt, 290 u32 cmd, 291 u32 param, 292 u32 *o_mcp_resp, 293 u32 *o_mcp_param) 294 { 295 u8 delay = CHIP_MCP_RESP_ITER_US; 296 u32 seq, cnt = 1, actual_mb_seq; 297 int rc = 0; 298 299 /* Get actual driver mailbox sequence */ 300 actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 301 DRV_MSG_SEQ_NUMBER_MASK; 302 303 /* Use MCP history register to check if MCP reset occurred between 304 * init time and now. 305 */ 306 if (p_hwfn->mcp_info->mcp_hist != 307 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 308 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Rereading MCP offsets\n"); 309 qed_load_mcp_offsets(p_hwfn, p_ptt); 310 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 311 } 312 seq = ++p_hwfn->mcp_info->drv_mb_seq; 313 314 /* Set drv param */ 315 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param); 316 317 /* Set drv command along with the updated sequence */ 318 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq)); 319 320 DP_VERBOSE(p_hwfn, QED_MSG_SP, 321 "wrote command (%x) to MFW MB param 0x%08x\n", 322 (cmd | seq), param); 323 324 do { 325 /* Wait for MFW response */ 326 udelay(delay); 327 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 328 329 /* Give the FW up to 5 second (500*10ms) */ 330 } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) && 331 (cnt++ < QED_DRV_MB_MAX_RETRIES)); 332 333 DP_VERBOSE(p_hwfn, QED_MSG_SP, 334 "[after %d ms] read (%x) seq is (%x) from FW MB\n", 335 cnt * delay, *o_mcp_resp, seq); 336 337 /* Is this a reply to our command? */ 338 if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) { 339 *o_mcp_resp &= FW_MSG_CODE_MASK; 340 /* Get the MCP param */ 341 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 342 } else { 343 /* FW BUG! */ 344 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n", 345 cmd, param); 346 *o_mcp_resp = 0; 347 rc = -EAGAIN; 348 } 349 return rc; 350 } 351 352 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 353 struct qed_ptt *p_ptt, 354 struct qed_mcp_mb_params *p_mb_params) 355 { 356 u32 union_data_addr; 357 358 int rc; 359 360 /* MCP not initialized */ 361 if (!qed_mcp_is_init(p_hwfn)) { 362 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 363 return -EBUSY; 364 } 365 366 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 367 offsetof(struct public_drv_mb, union_data); 368 369 /* Ensure that only a single thread is accessing the mailbox at a 370 * certain time. 371 */ 372 rc = qed_mcp_mb_lock(p_hwfn, p_mb_params->cmd); 373 if (rc) 374 return rc; 375 376 if (p_mb_params->p_data_src != NULL) 377 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, 378 p_mb_params->p_data_src, 379 sizeof(*p_mb_params->p_data_src)); 380 381 rc = qed_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd, 382 p_mb_params->param, &p_mb_params->mcp_resp, 383 &p_mb_params->mcp_param); 384 385 if (p_mb_params->p_data_dst != NULL) 386 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 387 union_data_addr, 388 sizeof(*p_mb_params->p_data_dst)); 389 390 qed_mcp_mb_unlock(p_hwfn, p_mb_params->cmd); 391 392 return rc; 393 } 394 395 int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 396 struct qed_ptt *p_ptt, 397 u32 cmd, 398 u32 param, 399 u32 *o_mcp_resp, 400 u32 *o_mcp_param) 401 { 402 struct qed_mcp_mb_params mb_params; 403 union drv_union_data data_src; 404 int rc; 405 406 memset(&mb_params, 0, sizeof(mb_params)); 407 memset(&data_src, 0, sizeof(data_src)); 408 mb_params.cmd = cmd; 409 mb_params.param = param; 410 411 /* In case of UNLOAD_DONE, set the primary MAC */ 412 if ((cmd == DRV_MSG_CODE_UNLOAD_DONE) && 413 (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED)) { 414 u8 *p_mac = p_hwfn->cdev->wol_mac; 415 416 data_src.wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 417 data_src.wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 418 p_mac[4] << 8 | p_mac[5]; 419 420 DP_VERBOSE(p_hwfn, 421 (QED_MSG_SP | NETIF_MSG_IFDOWN), 422 "Setting WoL MAC: %pM --> [%08x,%08x]\n", 423 p_mac, data_src.wol_mac.mac_upper, 424 data_src.wol_mac.mac_lower); 425 426 mb_params.p_data_src = &data_src; 427 } 428 429 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 430 if (rc) 431 return rc; 432 433 *o_mcp_resp = mb_params.mcp_resp; 434 *o_mcp_param = mb_params.mcp_param; 435 436 return 0; 437 } 438 439 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 440 struct qed_ptt *p_ptt, 441 u32 cmd, 442 u32 param, 443 u32 *o_mcp_resp, 444 u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 445 { 446 struct qed_mcp_mb_params mb_params; 447 union drv_union_data union_data; 448 int rc; 449 450 memset(&mb_params, 0, sizeof(mb_params)); 451 mb_params.cmd = cmd; 452 mb_params.param = param; 453 mb_params.p_data_dst = &union_data; 454 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 455 if (rc) 456 return rc; 457 458 *o_mcp_resp = mb_params.mcp_resp; 459 *o_mcp_param = mb_params.mcp_param; 460 461 *o_txn_size = *o_mcp_param; 462 memcpy(o_buf, &union_data.raw_data, *o_txn_size); 463 464 return 0; 465 } 466 467 int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 468 struct qed_ptt *p_ptt, u32 *p_load_code) 469 { 470 struct qed_dev *cdev = p_hwfn->cdev; 471 struct qed_mcp_mb_params mb_params; 472 union drv_union_data union_data; 473 int rc; 474 475 memset(&mb_params, 0, sizeof(mb_params)); 476 /* Load Request */ 477 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 478 mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT | 479 cdev->drv_type; 480 memcpy(&union_data.ver_str, cdev->ver_str, MCP_DRV_VER_STR_SIZE); 481 mb_params.p_data_src = &union_data; 482 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 483 484 /* if mcp fails to respond we must abort */ 485 if (rc) { 486 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 487 return rc; 488 } 489 490 *p_load_code = mb_params.mcp_resp; 491 492 /* If MFW refused (e.g. other port is in diagnostic mode) we 493 * must abort. This can happen in the following cases: 494 * - Other port is in diagnostic mode 495 * - Previously loaded function on the engine is not compliant with 496 * the requester. 497 * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION. 498 * - 499 */ 500 if (!(*p_load_code) || 501 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) || 502 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) || 503 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) { 504 DP_ERR(p_hwfn, "MCP refused load request, aborting\n"); 505 return -EBUSY; 506 } 507 508 return 0; 509 } 510 511 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 512 struct qed_ptt *p_ptt) 513 { 514 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 515 PUBLIC_PATH); 516 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 517 u32 path_addr = SECTION_ADDR(mfw_path_offsize, 518 QED_PATH_ID(p_hwfn)); 519 u32 disabled_vfs[VF_MAX_STATIC / 32]; 520 int i; 521 522 DP_VERBOSE(p_hwfn, 523 QED_MSG_SP, 524 "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 525 mfw_path_offsize, path_addr); 526 527 for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 528 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 529 path_addr + 530 offsetof(struct public_path, 531 mcp_vf_disabled) + 532 sizeof(u32) * i); 533 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 534 "FLR-ed VFs [%08x,...,%08x] - %08x\n", 535 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 536 } 537 538 if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 539 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 540 } 541 542 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 543 struct qed_ptt *p_ptt, u32 *vfs_to_ack) 544 { 545 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 546 PUBLIC_FUNC); 547 u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 548 u32 func_addr = SECTION_ADDR(mfw_func_offsize, 549 MCP_PF_ID(p_hwfn)); 550 struct qed_mcp_mb_params mb_params; 551 union drv_union_data union_data; 552 int rc; 553 int i; 554 555 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 556 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 557 "Acking VFs [%08x,...,%08x] - %08x\n", 558 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 559 560 memset(&mb_params, 0, sizeof(mb_params)); 561 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 562 memcpy(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8); 563 mb_params.p_data_src = &union_data; 564 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 565 if (rc) { 566 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 567 return -EBUSY; 568 } 569 570 /* Clear the ACK bits */ 571 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 572 qed_wr(p_hwfn, p_ptt, 573 func_addr + 574 offsetof(struct public_func, drv_ack_vf_disabled) + 575 i * sizeof(u32), 0); 576 577 return rc; 578 } 579 580 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 581 struct qed_ptt *p_ptt) 582 { 583 u32 transceiver_state; 584 585 transceiver_state = qed_rd(p_hwfn, p_ptt, 586 p_hwfn->mcp_info->port_addr + 587 offsetof(struct public_port, 588 transceiver_data)); 589 590 DP_VERBOSE(p_hwfn, 591 (NETIF_MSG_HW | QED_MSG_SP), 592 "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 593 transceiver_state, 594 (u32)(p_hwfn->mcp_info->port_addr + 595 offsetof(struct public_port, transceiver_data))); 596 597 transceiver_state = GET_FIELD(transceiver_state, 598 ETH_TRANSCEIVER_STATE); 599 600 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 601 DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 602 else 603 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 604 } 605 606 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 607 struct qed_ptt *p_ptt, bool b_reset) 608 { 609 struct qed_mcp_link_state *p_link; 610 u8 max_bw, min_bw; 611 u32 status = 0; 612 613 p_link = &p_hwfn->mcp_info->link_output; 614 memset(p_link, 0, sizeof(*p_link)); 615 if (!b_reset) { 616 status = qed_rd(p_hwfn, p_ptt, 617 p_hwfn->mcp_info->port_addr + 618 offsetof(struct public_port, link_status)); 619 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 620 "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 621 status, 622 (u32)(p_hwfn->mcp_info->port_addr + 623 offsetof(struct public_port, link_status))); 624 } else { 625 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 626 "Resetting link indications\n"); 627 return; 628 } 629 630 if (p_hwfn->b_drv_link_init) 631 p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 632 else 633 p_link->link_up = false; 634 635 p_link->full_duplex = true; 636 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 637 case LINK_STATUS_SPEED_AND_DUPLEX_100G: 638 p_link->speed = 100000; 639 break; 640 case LINK_STATUS_SPEED_AND_DUPLEX_50G: 641 p_link->speed = 50000; 642 break; 643 case LINK_STATUS_SPEED_AND_DUPLEX_40G: 644 p_link->speed = 40000; 645 break; 646 case LINK_STATUS_SPEED_AND_DUPLEX_25G: 647 p_link->speed = 25000; 648 break; 649 case LINK_STATUS_SPEED_AND_DUPLEX_20G: 650 p_link->speed = 20000; 651 break; 652 case LINK_STATUS_SPEED_AND_DUPLEX_10G: 653 p_link->speed = 10000; 654 break; 655 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 656 p_link->full_duplex = false; 657 /* Fall-through */ 658 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 659 p_link->speed = 1000; 660 break; 661 default: 662 p_link->speed = 0; 663 } 664 665 if (p_link->link_up && p_link->speed) 666 p_link->line_speed = p_link->speed; 667 else 668 p_link->line_speed = 0; 669 670 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 671 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 672 673 /* Max bandwidth configuration */ 674 __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 675 676 /* Min bandwidth configuration */ 677 __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 678 qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_link->min_pf_rate); 679 680 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 681 p_link->an_complete = !!(status & 682 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 683 p_link->parallel_detection = !!(status & 684 LINK_STATUS_PARALLEL_DETECTION_USED); 685 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 686 687 p_link->partner_adv_speed |= 688 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 689 QED_LINK_PARTNER_SPEED_1G_FD : 0; 690 p_link->partner_adv_speed |= 691 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 692 QED_LINK_PARTNER_SPEED_1G_HD : 0; 693 p_link->partner_adv_speed |= 694 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 695 QED_LINK_PARTNER_SPEED_10G : 0; 696 p_link->partner_adv_speed |= 697 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 698 QED_LINK_PARTNER_SPEED_20G : 0; 699 p_link->partner_adv_speed |= 700 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 701 QED_LINK_PARTNER_SPEED_25G : 0; 702 p_link->partner_adv_speed |= 703 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 704 QED_LINK_PARTNER_SPEED_40G : 0; 705 p_link->partner_adv_speed |= 706 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 707 QED_LINK_PARTNER_SPEED_50G : 0; 708 p_link->partner_adv_speed |= 709 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 710 QED_LINK_PARTNER_SPEED_100G : 0; 711 712 p_link->partner_tx_flow_ctrl_en = 713 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 714 p_link->partner_rx_flow_ctrl_en = 715 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 716 717 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 718 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 719 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 720 break; 721 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 722 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 723 break; 724 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 725 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 726 break; 727 default: 728 p_link->partner_adv_pause = 0; 729 } 730 731 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 732 733 qed_link_update(p_hwfn); 734 } 735 736 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 737 { 738 struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 739 struct qed_mcp_mb_params mb_params; 740 union drv_union_data union_data; 741 struct eth_phy_cfg *phy_cfg; 742 int rc = 0; 743 u32 cmd; 744 745 /* Set the shmem configuration according to params */ 746 phy_cfg = &union_data.drv_phy_cfg; 747 memset(phy_cfg, 0, sizeof(*phy_cfg)); 748 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 749 if (!params->speed.autoneg) 750 phy_cfg->speed = params->speed.forced_speed; 751 phy_cfg->pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 752 phy_cfg->pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 753 phy_cfg->pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 754 phy_cfg->adv_speed = params->speed.advertised_speeds; 755 phy_cfg->loopback_mode = params->loopback_mode; 756 757 p_hwfn->b_drv_link_init = b_up; 758 759 if (b_up) { 760 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 761 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 762 phy_cfg->speed, 763 phy_cfg->pause, 764 phy_cfg->adv_speed, 765 phy_cfg->loopback_mode, 766 phy_cfg->feature_config_flags); 767 } else { 768 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 769 "Resetting link\n"); 770 } 771 772 memset(&mb_params, 0, sizeof(mb_params)); 773 mb_params.cmd = cmd; 774 mb_params.p_data_src = &union_data; 775 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 776 777 /* if mcp fails to respond we must abort */ 778 if (rc) { 779 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 780 return rc; 781 } 782 783 /* Reset the link status if needed */ 784 if (!b_up) 785 qed_mcp_handle_link_change(p_hwfn, p_ptt, true); 786 787 return 0; 788 } 789 790 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 791 struct qed_ptt *p_ptt, 792 enum MFW_DRV_MSG_TYPE type) 793 { 794 enum qed_mcp_protocol_type stats_type; 795 union qed_mcp_protocol_stats stats; 796 struct qed_mcp_mb_params mb_params; 797 union drv_union_data union_data; 798 u32 hsi_param; 799 800 switch (type) { 801 case MFW_DRV_MSG_GET_LAN_STATS: 802 stats_type = QED_MCP_LAN_STATS; 803 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 804 break; 805 case MFW_DRV_MSG_GET_FCOE_STATS: 806 stats_type = QED_MCP_FCOE_STATS; 807 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 808 break; 809 case MFW_DRV_MSG_GET_ISCSI_STATS: 810 stats_type = QED_MCP_ISCSI_STATS; 811 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 812 break; 813 case MFW_DRV_MSG_GET_RDMA_STATS: 814 stats_type = QED_MCP_RDMA_STATS; 815 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 816 break; 817 default: 818 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 819 return; 820 } 821 822 qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 823 824 memset(&mb_params, 0, sizeof(mb_params)); 825 mb_params.cmd = DRV_MSG_CODE_GET_STATS; 826 mb_params.param = hsi_param; 827 memcpy(&union_data, &stats, sizeof(stats)); 828 mb_params.p_data_src = &union_data; 829 qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 830 } 831 832 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 833 struct public_func *p_shmem_info) 834 { 835 struct qed_mcp_function_info *p_info; 836 837 p_info = &p_hwfn->mcp_info->func_info; 838 839 p_info->bandwidth_min = (p_shmem_info->config & 840 FUNC_MF_CFG_MIN_BW_MASK) >> 841 FUNC_MF_CFG_MIN_BW_SHIFT; 842 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 843 DP_INFO(p_hwfn, 844 "bandwidth minimum out of bounds [%02x]. Set to 1\n", 845 p_info->bandwidth_min); 846 p_info->bandwidth_min = 1; 847 } 848 849 p_info->bandwidth_max = (p_shmem_info->config & 850 FUNC_MF_CFG_MAX_BW_MASK) >> 851 FUNC_MF_CFG_MAX_BW_SHIFT; 852 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 853 DP_INFO(p_hwfn, 854 "bandwidth maximum out of bounds [%02x]. Set to 100\n", 855 p_info->bandwidth_max); 856 p_info->bandwidth_max = 100; 857 } 858 } 859 860 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 861 struct qed_ptt *p_ptt, 862 struct public_func *p_data, int pfid) 863 { 864 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 865 PUBLIC_FUNC); 866 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 867 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 868 u32 i, size; 869 870 memset(p_data, 0, sizeof(*p_data)); 871 872 size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 873 for (i = 0; i < size / sizeof(u32); i++) 874 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 875 func_addr + (i << 2)); 876 return size; 877 } 878 879 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 880 { 881 struct qed_mcp_function_info *p_info; 882 struct public_func shmem_info; 883 u32 resp = 0, param = 0; 884 885 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 886 887 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 888 889 p_info = &p_hwfn->mcp_info->func_info; 890 891 qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 892 qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 893 894 /* Acknowledge the MFW */ 895 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 896 ¶m); 897 } 898 899 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 900 struct qed_ptt *p_ptt) 901 { 902 struct qed_mcp_info *info = p_hwfn->mcp_info; 903 int rc = 0; 904 bool found = false; 905 u16 i; 906 907 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 908 909 /* Read Messages from MFW */ 910 qed_mcp_read_mb(p_hwfn, p_ptt); 911 912 /* Compare current messages to old ones */ 913 for (i = 0; i < info->mfw_mb_length; i++) { 914 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 915 continue; 916 917 found = true; 918 919 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 920 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 921 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 922 923 switch (i) { 924 case MFW_DRV_MSG_LINK_CHANGE: 925 qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 926 break; 927 case MFW_DRV_MSG_VF_DISABLED: 928 qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 929 break; 930 case MFW_DRV_MSG_LLDP_DATA_UPDATED: 931 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 932 QED_DCBX_REMOTE_LLDP_MIB); 933 break; 934 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 935 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 936 QED_DCBX_REMOTE_MIB); 937 break; 938 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 939 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 940 QED_DCBX_OPERATIONAL_MIB); 941 break; 942 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 943 qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 944 break; 945 case MFW_DRV_MSG_GET_LAN_STATS: 946 case MFW_DRV_MSG_GET_FCOE_STATS: 947 case MFW_DRV_MSG_GET_ISCSI_STATS: 948 case MFW_DRV_MSG_GET_RDMA_STATS: 949 qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 950 break; 951 case MFW_DRV_MSG_BW_UPDATE: 952 qed_mcp_update_bw(p_hwfn, p_ptt); 953 break; 954 default: 955 DP_NOTICE(p_hwfn, "Unimplemented MFW message %d\n", i); 956 rc = -EINVAL; 957 } 958 } 959 960 /* ACK everything */ 961 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 962 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 963 964 /* MFW expect answer in BE, so we force write in that format */ 965 qed_wr(p_hwfn, p_ptt, 966 info->mfw_mb_addr + sizeof(u32) + 967 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 968 sizeof(u32) + i * sizeof(u32), 969 (__force u32)val); 970 } 971 972 if (!found) { 973 DP_NOTICE(p_hwfn, 974 "Received an MFW message indication but no new message!\n"); 975 rc = -EINVAL; 976 } 977 978 /* Copy the new mfw messages into the shadow */ 979 memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 980 981 return rc; 982 } 983 984 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 985 struct qed_ptt *p_ptt, 986 u32 *p_mfw_ver, u32 *p_running_bundle_id) 987 { 988 u32 global_offsize; 989 990 if (IS_VF(p_hwfn->cdev)) { 991 if (p_hwfn->vf_iov_info) { 992 struct pfvf_acquire_resp_tlv *p_resp; 993 994 p_resp = &p_hwfn->vf_iov_info->acquire_resp; 995 *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 996 return 0; 997 } else { 998 DP_VERBOSE(p_hwfn, 999 QED_MSG_IOV, 1000 "VF requested MFW version prior to ACQUIRE\n"); 1001 return -EINVAL; 1002 } 1003 } 1004 1005 global_offsize = qed_rd(p_hwfn, p_ptt, 1006 SECTION_OFFSIZE_ADDR(p_hwfn-> 1007 mcp_info->public_base, 1008 PUBLIC_GLOBAL)); 1009 *p_mfw_ver = 1010 qed_rd(p_hwfn, p_ptt, 1011 SECTION_ADDR(global_offsize, 1012 0) + offsetof(struct public_global, mfw_ver)); 1013 1014 if (p_running_bundle_id != NULL) { 1015 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 1016 SECTION_ADDR(global_offsize, 0) + 1017 offsetof(struct public_global, 1018 running_bundle_id)); 1019 } 1020 1021 return 0; 1022 } 1023 1024 int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) 1025 { 1026 struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 1027 struct qed_ptt *p_ptt; 1028 1029 if (IS_VF(cdev)) 1030 return -EINVAL; 1031 1032 if (!qed_mcp_is_init(p_hwfn)) { 1033 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1034 return -EBUSY; 1035 } 1036 1037 *p_media_type = MEDIA_UNSPECIFIED; 1038 1039 p_ptt = qed_ptt_acquire(p_hwfn); 1040 if (!p_ptt) 1041 return -EBUSY; 1042 1043 *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1044 offsetof(struct public_port, media_type)); 1045 1046 qed_ptt_release(p_hwfn, p_ptt); 1047 1048 return 0; 1049 } 1050 1051 /* Old MFW has a global configuration for all PFs regarding RDMA support */ 1052 static void 1053 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 1054 enum qed_pci_personality *p_proto) 1055 { 1056 /* There wasn't ever a legacy MFW that published iwarp. 1057 * So at this point, this is either plain l2 or RoCE. 1058 */ 1059 if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 1060 *p_proto = QED_PCI_ETH_ROCE; 1061 else 1062 *p_proto = QED_PCI_ETH; 1063 1064 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 1065 "According to Legacy capabilities, L2 personality is %08x\n", 1066 (u32) *p_proto); 1067 } 1068 1069 static int 1070 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 1071 struct qed_ptt *p_ptt, 1072 enum qed_pci_personality *p_proto) 1073 { 1074 u32 resp = 0, param = 0; 1075 int rc; 1076 1077 rc = qed_mcp_cmd(p_hwfn, p_ptt, 1078 DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 1079 if (rc) 1080 return rc; 1081 if (resp != FW_MSG_CODE_OK) { 1082 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 1083 "MFW lacks support for command; Returns %08x\n", 1084 resp); 1085 return -EINVAL; 1086 } 1087 1088 switch (param) { 1089 case FW_MB_PARAM_GET_PF_RDMA_NONE: 1090 *p_proto = QED_PCI_ETH; 1091 break; 1092 case FW_MB_PARAM_GET_PF_RDMA_ROCE: 1093 *p_proto = QED_PCI_ETH_ROCE; 1094 break; 1095 case FW_MB_PARAM_GET_PF_RDMA_BOTH: 1096 DP_NOTICE(p_hwfn, 1097 "Current day drivers don't support RoCE & iWARP. Default to RoCE-only\n"); 1098 *p_proto = QED_PCI_ETH_ROCE; 1099 break; 1100 case FW_MB_PARAM_GET_PF_RDMA_IWARP: 1101 default: 1102 DP_NOTICE(p_hwfn, 1103 "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 1104 param); 1105 return -EINVAL; 1106 } 1107 1108 DP_VERBOSE(p_hwfn, 1109 NETIF_MSG_IFUP, 1110 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 1111 (u32) *p_proto, resp, param); 1112 return 0; 1113 } 1114 1115 static int 1116 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 1117 struct public_func *p_info, 1118 struct qed_ptt *p_ptt, 1119 enum qed_pci_personality *p_proto) 1120 { 1121 int rc = 0; 1122 1123 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 1124 case FUNC_MF_CFG_PROTOCOL_ETHERNET: 1125 if (!IS_ENABLED(CONFIG_QED_RDMA)) 1126 *p_proto = QED_PCI_ETH; 1127 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 1128 qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 1129 break; 1130 case FUNC_MF_CFG_PROTOCOL_ISCSI: 1131 *p_proto = QED_PCI_ISCSI; 1132 break; 1133 case FUNC_MF_CFG_PROTOCOL_ROCE: 1134 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 1135 /* Fallthrough */ 1136 default: 1137 rc = -EINVAL; 1138 } 1139 1140 return rc; 1141 } 1142 1143 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 1144 struct qed_ptt *p_ptt) 1145 { 1146 struct qed_mcp_function_info *info; 1147 struct public_func shmem_info; 1148 1149 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1150 info = &p_hwfn->mcp_info->func_info; 1151 1152 info->pause_on_host = (shmem_info.config & 1153 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 1154 1155 if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 1156 &info->protocol)) { 1157 DP_ERR(p_hwfn, "Unknown personality %08x\n", 1158 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 1159 return -EINVAL; 1160 } 1161 1162 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1163 1164 if (shmem_info.mac_upper || shmem_info.mac_lower) { 1165 info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 1166 info->mac[1] = (u8)(shmem_info.mac_upper); 1167 info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 1168 info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 1169 info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 1170 info->mac[5] = (u8)(shmem_info.mac_lower); 1171 1172 /* Store primary MAC for later possible WoL */ 1173 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 1174 } else { 1175 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 1176 } 1177 1178 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper | 1179 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32); 1180 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper | 1181 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32); 1182 1183 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 1184 1185 info->mtu = (u16)shmem_info.mtu_size; 1186 1187 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 1188 p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 1189 if (qed_mcp_is_init(p_hwfn)) { 1190 u32 resp = 0, param = 0; 1191 int rc; 1192 1193 rc = qed_mcp_cmd(p_hwfn, p_ptt, 1194 DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 1195 if (rc) 1196 return rc; 1197 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 1198 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 1199 } 1200 1201 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 1202 "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 1203 info->pause_on_host, info->protocol, 1204 info->bandwidth_min, info->bandwidth_max, 1205 info->mac[0], info->mac[1], info->mac[2], 1206 info->mac[3], info->mac[4], info->mac[5], 1207 info->wwn_port, info->wwn_node, 1208 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 1209 1210 return 0; 1211 } 1212 1213 struct qed_mcp_link_params 1214 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 1215 { 1216 if (!p_hwfn || !p_hwfn->mcp_info) 1217 return NULL; 1218 return &p_hwfn->mcp_info->link_input; 1219 } 1220 1221 struct qed_mcp_link_state 1222 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 1223 { 1224 if (!p_hwfn || !p_hwfn->mcp_info) 1225 return NULL; 1226 return &p_hwfn->mcp_info->link_output; 1227 } 1228 1229 struct qed_mcp_link_capabilities 1230 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 1231 { 1232 if (!p_hwfn || !p_hwfn->mcp_info) 1233 return NULL; 1234 return &p_hwfn->mcp_info->link_capabilities; 1235 } 1236 1237 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1238 { 1239 u32 resp = 0, param = 0; 1240 int rc; 1241 1242 rc = qed_mcp_cmd(p_hwfn, p_ptt, 1243 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 1244 1245 /* Wait for the drain to complete before returning */ 1246 msleep(1020); 1247 1248 return rc; 1249 } 1250 1251 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 1252 struct qed_ptt *p_ptt, u32 *p_flash_size) 1253 { 1254 u32 flash_size; 1255 1256 if (IS_VF(p_hwfn->cdev)) 1257 return -EINVAL; 1258 1259 flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 1260 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 1261 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 1262 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 1263 1264 *p_flash_size = flash_size; 1265 1266 return 0; 1267 } 1268 1269 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 1270 struct qed_ptt *p_ptt, u8 vf_id, u8 num) 1271 { 1272 u32 resp = 0, param = 0, rc_param = 0; 1273 int rc; 1274 1275 /* Only Leader can configure MSIX, and need to take CMT into account */ 1276 if (!IS_LEAD_HWFN(p_hwfn)) 1277 return 0; 1278 num *= p_hwfn->cdev->num_hwfns; 1279 1280 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 1281 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 1282 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 1283 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 1284 1285 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 1286 &resp, &rc_param); 1287 1288 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 1289 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 1290 rc = -EINVAL; 1291 } else { 1292 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 1293 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 1294 num, vf_id); 1295 } 1296 1297 return rc; 1298 } 1299 1300 int 1301 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 1302 struct qed_ptt *p_ptt, 1303 struct qed_mcp_drv_version *p_ver) 1304 { 1305 struct drv_version_stc *p_drv_version; 1306 struct qed_mcp_mb_params mb_params; 1307 union drv_union_data union_data; 1308 __be32 val; 1309 u32 i; 1310 int rc; 1311 1312 p_drv_version = &union_data.drv_version; 1313 p_drv_version->version = p_ver->version; 1314 1315 for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 1316 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 1317 *(__be32 *)&p_drv_version->name[i * sizeof(u32)] = val; 1318 } 1319 1320 memset(&mb_params, 0, sizeof(mb_params)); 1321 mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 1322 mb_params.p_data_src = &union_data; 1323 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1324 if (rc) 1325 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1326 1327 return rc; 1328 } 1329 1330 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1331 { 1332 u32 resp = 0, param = 0; 1333 int rc; 1334 1335 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 1336 ¶m); 1337 if (rc) 1338 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1339 1340 return rc; 1341 } 1342 1343 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1344 { 1345 u32 value, cpu_mode; 1346 1347 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 1348 1349 value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 1350 value &= ~MCP_REG_CPU_MODE_SOFT_HALT; 1351 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value); 1352 cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 1353 1354 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0; 1355 } 1356 1357 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 1358 struct qed_ptt *p_ptt, 1359 enum qed_ov_client client) 1360 { 1361 u32 resp = 0, param = 0; 1362 u32 drv_mb_param; 1363 int rc; 1364 1365 switch (client) { 1366 case QED_OV_CLIENT_DRV: 1367 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 1368 break; 1369 case QED_OV_CLIENT_USER: 1370 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 1371 break; 1372 case QED_OV_CLIENT_VENDOR_SPEC: 1373 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 1374 break; 1375 default: 1376 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 1377 return -EINVAL; 1378 } 1379 1380 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 1381 drv_mb_param, &resp, ¶m); 1382 if (rc) 1383 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1384 1385 return rc; 1386 } 1387 1388 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 1389 struct qed_ptt *p_ptt, 1390 enum qed_ov_driver_state drv_state) 1391 { 1392 u32 resp = 0, param = 0; 1393 u32 drv_mb_param; 1394 int rc; 1395 1396 switch (drv_state) { 1397 case QED_OV_DRIVER_STATE_NOT_LOADED: 1398 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 1399 break; 1400 case QED_OV_DRIVER_STATE_DISABLED: 1401 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 1402 break; 1403 case QED_OV_DRIVER_STATE_ACTIVE: 1404 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 1405 break; 1406 default: 1407 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 1408 return -EINVAL; 1409 } 1410 1411 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 1412 drv_mb_param, &resp, ¶m); 1413 if (rc) 1414 DP_ERR(p_hwfn, "Failed to send driver state\n"); 1415 1416 return rc; 1417 } 1418 1419 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 1420 struct qed_ptt *p_ptt, u16 mtu) 1421 { 1422 u32 resp = 0, param = 0; 1423 u32 drv_mb_param; 1424 int rc; 1425 1426 drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 1427 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 1428 drv_mb_param, &resp, ¶m); 1429 if (rc) 1430 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 1431 1432 return rc; 1433 } 1434 1435 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 1436 struct qed_ptt *p_ptt, u8 *mac) 1437 { 1438 struct qed_mcp_mb_params mb_params; 1439 union drv_union_data union_data; 1440 int rc; 1441 1442 memset(&mb_params, 0, sizeof(mb_params)); 1443 mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 1444 mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 1445 DRV_MSG_CODE_VMAC_TYPE_SHIFT; 1446 mb_params.param |= MCP_PF_ID(p_hwfn); 1447 ether_addr_copy(&union_data.raw_data[0], mac); 1448 mb_params.p_data_src = &union_data; 1449 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1450 if (rc) 1451 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 1452 1453 /* Store primary MAC for later possible WoL */ 1454 memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 1455 1456 return rc; 1457 } 1458 1459 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 1460 struct qed_ptt *p_ptt, enum qed_ov_wol wol) 1461 { 1462 u32 resp = 0, param = 0; 1463 u32 drv_mb_param; 1464 int rc; 1465 1466 if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 1467 DP_VERBOSE(p_hwfn, QED_MSG_SP, 1468 "Can't change WoL configuration when WoL isn't supported\n"); 1469 return -EINVAL; 1470 } 1471 1472 switch (wol) { 1473 case QED_OV_WOL_DEFAULT: 1474 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 1475 break; 1476 case QED_OV_WOL_DISABLED: 1477 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 1478 break; 1479 case QED_OV_WOL_ENABLED: 1480 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 1481 break; 1482 default: 1483 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 1484 return -EINVAL; 1485 } 1486 1487 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 1488 drv_mb_param, &resp, ¶m); 1489 if (rc) 1490 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 1491 1492 /* Store the WoL update for a future unload */ 1493 p_hwfn->cdev->wol_config = (u8)wol; 1494 1495 return rc; 1496 } 1497 1498 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 1499 struct qed_ptt *p_ptt, 1500 enum qed_ov_eswitch eswitch) 1501 { 1502 u32 resp = 0, param = 0; 1503 u32 drv_mb_param; 1504 int rc; 1505 1506 switch (eswitch) { 1507 case QED_OV_ESWITCH_NONE: 1508 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 1509 break; 1510 case QED_OV_ESWITCH_VEB: 1511 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 1512 break; 1513 case QED_OV_ESWITCH_VEPA: 1514 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 1515 break; 1516 default: 1517 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 1518 return -EINVAL; 1519 } 1520 1521 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 1522 drv_mb_param, &resp, ¶m); 1523 if (rc) 1524 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 1525 1526 return rc; 1527 } 1528 1529 int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 1530 struct qed_ptt *p_ptt, enum qed_led_mode mode) 1531 { 1532 u32 resp = 0, param = 0, drv_mb_param; 1533 int rc; 1534 1535 switch (mode) { 1536 case QED_LED_MODE_ON: 1537 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 1538 break; 1539 case QED_LED_MODE_OFF: 1540 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 1541 break; 1542 case QED_LED_MODE_RESTORE: 1543 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 1544 break; 1545 default: 1546 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 1547 return -EINVAL; 1548 } 1549 1550 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 1551 drv_mb_param, &resp, ¶m); 1552 1553 return rc; 1554 } 1555 1556 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 1557 struct qed_ptt *p_ptt, u32 mask_parities) 1558 { 1559 u32 resp = 0, param = 0; 1560 int rc; 1561 1562 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 1563 mask_parities, &resp, ¶m); 1564 1565 if (rc) { 1566 DP_ERR(p_hwfn, 1567 "MCP response failure for mask parities, aborting\n"); 1568 } else if (resp != FW_MSG_CODE_OK) { 1569 DP_ERR(p_hwfn, 1570 "MCP did not acknowledge mask parity request. Old MFW?\n"); 1571 rc = -EINVAL; 1572 } 1573 1574 return rc; 1575 } 1576 1577 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 1578 { 1579 u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 1580 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1581 u32 resp = 0, resp_param = 0; 1582 struct qed_ptt *p_ptt; 1583 int rc = 0; 1584 1585 p_ptt = qed_ptt_acquire(p_hwfn); 1586 if (!p_ptt) 1587 return -EBUSY; 1588 1589 while (bytes_left > 0) { 1590 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 1591 1592 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 1593 DRV_MSG_CODE_NVM_READ_NVRAM, 1594 addr + offset + 1595 (bytes_to_copy << 1596 DRV_MB_PARAM_NVM_LEN_SHIFT), 1597 &resp, &resp_param, 1598 &read_len, 1599 (u32 *)(p_buf + offset)); 1600 1601 if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 1602 DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 1603 break; 1604 } 1605 1606 /* This can be a lengthy process, and it's possible scheduler 1607 * isn't preemptable. Sleep a bit to prevent CPU hogging. 1608 */ 1609 if (bytes_left % 0x1000 < 1610 (bytes_left - read_len) % 0x1000) 1611 usleep_range(1000, 2000); 1612 1613 offset += read_len; 1614 bytes_left -= read_len; 1615 } 1616 1617 cdev->mcp_nvm_resp = resp; 1618 qed_ptt_release(p_hwfn, p_ptt); 1619 1620 return rc; 1621 } 1622 1623 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1624 { 1625 u32 drv_mb_param = 0, rsp, param; 1626 int rc = 0; 1627 1628 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 1629 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 1630 1631 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 1632 drv_mb_param, &rsp, ¶m); 1633 1634 if (rc) 1635 return rc; 1636 1637 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 1638 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 1639 rc = -EAGAIN; 1640 1641 return rc; 1642 } 1643 1644 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1645 { 1646 u32 drv_mb_param, rsp, param; 1647 int rc = 0; 1648 1649 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 1650 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 1651 1652 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 1653 drv_mb_param, &rsp, ¶m); 1654 1655 if (rc) 1656 return rc; 1657 1658 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 1659 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 1660 rc = -EAGAIN; 1661 1662 return rc; 1663 } 1664 1665 int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn, 1666 struct qed_ptt *p_ptt, 1667 u32 *num_images) 1668 { 1669 u32 drv_mb_param = 0, rsp; 1670 int rc = 0; 1671 1672 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 1673 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 1674 1675 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 1676 drv_mb_param, &rsp, num_images); 1677 if (rc) 1678 return rc; 1679 1680 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 1681 rc = -EINVAL; 1682 1683 return rc; 1684 } 1685 1686 int qed_mcp_bist_nvm_test_get_image_att(struct qed_hwfn *p_hwfn, 1687 struct qed_ptt *p_ptt, 1688 struct bist_nvm_image_att *p_image_att, 1689 u32 image_index) 1690 { 1691 u32 buf_size = 0, param, resp = 0, resp_param = 0; 1692 int rc; 1693 1694 param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 1695 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 1696 param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 1697 1698 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 1699 DRV_MSG_CODE_BIST_TEST, param, 1700 &resp, &resp_param, 1701 &buf_size, 1702 (u32 *)p_image_att); 1703 if (rc) 1704 return rc; 1705 1706 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 1707 (p_image_att->return_code != 1)) 1708 rc = -EINVAL; 1709 1710 return rc; 1711 } 1712 1713 #define QED_RESC_ALLOC_VERSION_MAJOR 1 1714 #define QED_RESC_ALLOC_VERSION_MINOR 0 1715 #define QED_RESC_ALLOC_VERSION \ 1716 ((QED_RESC_ALLOC_VERSION_MAJOR << \ 1717 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 1718 (QED_RESC_ALLOC_VERSION_MINOR << \ 1719 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 1720 int qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 1721 struct qed_ptt *p_ptt, 1722 struct resource_info *p_resc_info, 1723 u32 *p_mcp_resp, u32 *p_mcp_param) 1724 { 1725 struct qed_mcp_mb_params mb_params; 1726 union drv_union_data union_data; 1727 int rc; 1728 1729 memset(&mb_params, 0, sizeof(mb_params)); 1730 memset(&union_data, 0, sizeof(union_data)); 1731 mb_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 1732 mb_params.param = QED_RESC_ALLOC_VERSION; 1733 1734 /* Need to have a sufficient large struct, as the cmd_and_union 1735 * is going to do memcpy from and to it. 1736 */ 1737 memcpy(&union_data.resource, p_resc_info, sizeof(*p_resc_info)); 1738 1739 mb_params.p_data_src = &union_data; 1740 mb_params.p_data_dst = &union_data; 1741 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1742 if (rc) 1743 return rc; 1744 1745 /* Copy the data back */ 1746 memcpy(p_resc_info, &union_data.resource, sizeof(*p_resc_info)); 1747 *p_mcp_resp = mb_params.mcp_resp; 1748 *p_mcp_param = mb_params.mcp_param; 1749 1750 DP_VERBOSE(p_hwfn, 1751 QED_MSG_SP, 1752 "MFW resource_info: version 0x%x, res_id 0x%x, size 0x%x, offset 0x%x, vf_size 0x%x, vf_offset 0x%x, flags 0x%x\n", 1753 *p_mcp_param, 1754 p_resc_info->res_id, 1755 p_resc_info->size, 1756 p_resc_info->offset, 1757 p_resc_info->vf_size, 1758 p_resc_info->vf_offset, p_resc_info->flags); 1759 1760 return 0; 1761 } 1762