1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <asm/byteorder.h> 35 #include <linux/delay.h> 36 #include <linux/errno.h> 37 #include <linux/kernel.h> 38 #include <linux/slab.h> 39 #include <linux/spinlock.h> 40 #include <linux/string.h> 41 #include <linux/etherdevice.h> 42 #include "qed.h" 43 #include "qed_cxt.h" 44 #include "qed_dcbx.h" 45 #include "qed_hsi.h" 46 #include "qed_hw.h" 47 #include "qed_mcp.h" 48 #include "qed_reg_addr.h" 49 #include "qed_sriov.h" 50 51 #define CHIP_MCP_RESP_ITER_US 10 52 53 #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 54 #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 55 56 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 57 qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 58 _val) 59 60 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 61 qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 62 63 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 64 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 65 offsetof(struct public_drv_mb, _field), _val) 66 67 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 68 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 69 offsetof(struct public_drv_mb, _field)) 70 71 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 72 DRV_ID_PDA_COMP_VER_SHIFT) 73 74 #define MCP_BYTES_PER_MBIT_SHIFT 17 75 76 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 77 { 78 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 79 return false; 80 return true; 81 } 82 83 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 84 { 85 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 86 PUBLIC_PORT); 87 u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 88 89 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 90 MFW_PORT(p_hwfn)); 91 DP_VERBOSE(p_hwfn, QED_MSG_SP, 92 "port_addr = 0x%x, port_id 0x%02x\n", 93 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 94 } 95 96 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 97 { 98 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 99 u32 tmp, i; 100 101 if (!p_hwfn->mcp_info->public_base) 102 return; 103 104 for (i = 0; i < length; i++) { 105 tmp = qed_rd(p_hwfn, p_ptt, 106 p_hwfn->mcp_info->mfw_mb_addr + 107 (i << 2) + sizeof(u32)); 108 109 /* The MB data is actually BE; Need to force it to cpu */ 110 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 111 be32_to_cpu((__force __be32)tmp); 112 } 113 } 114 115 struct qed_mcp_cmd_elem { 116 struct list_head list; 117 struct qed_mcp_mb_params *p_mb_params; 118 u16 expected_seq_num; 119 bool b_is_completed; 120 }; 121 122 /* Must be called while cmd_lock is acquired */ 123 static struct qed_mcp_cmd_elem * 124 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 125 struct qed_mcp_mb_params *p_mb_params, 126 u16 expected_seq_num) 127 { 128 struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 129 130 p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 131 if (!p_cmd_elem) 132 goto out; 133 134 p_cmd_elem->p_mb_params = p_mb_params; 135 p_cmd_elem->expected_seq_num = expected_seq_num; 136 list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 137 out: 138 return p_cmd_elem; 139 } 140 141 /* Must be called while cmd_lock is acquired */ 142 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 143 struct qed_mcp_cmd_elem *p_cmd_elem) 144 { 145 list_del(&p_cmd_elem->list); 146 kfree(p_cmd_elem); 147 } 148 149 /* Must be called while cmd_lock is acquired */ 150 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 151 u16 seq_num) 152 { 153 struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 154 155 list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 156 if (p_cmd_elem->expected_seq_num == seq_num) 157 return p_cmd_elem; 158 } 159 160 return NULL; 161 } 162 163 int qed_mcp_free(struct qed_hwfn *p_hwfn) 164 { 165 if (p_hwfn->mcp_info) { 166 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 167 168 kfree(p_hwfn->mcp_info->mfw_mb_cur); 169 kfree(p_hwfn->mcp_info->mfw_mb_shadow); 170 171 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 172 list_for_each_entry_safe(p_cmd_elem, 173 p_tmp, 174 &p_hwfn->mcp_info->cmd_list, list) { 175 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 176 } 177 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 178 } 179 180 kfree(p_hwfn->mcp_info); 181 p_hwfn->mcp_info = NULL; 182 183 return 0; 184 } 185 186 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 187 { 188 struct qed_mcp_info *p_info = p_hwfn->mcp_info; 189 u32 drv_mb_offsize, mfw_mb_offsize; 190 u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 191 192 p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 193 if (!p_info->public_base) 194 return 0; 195 196 p_info->public_base |= GRCBASE_MCP; 197 198 /* Calculate the driver and MFW mailbox address */ 199 drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 200 SECTION_OFFSIZE_ADDR(p_info->public_base, 201 PUBLIC_DRV_MB)); 202 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 203 DP_VERBOSE(p_hwfn, QED_MSG_SP, 204 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 205 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 206 207 /* Set the MFW MB address */ 208 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 209 SECTION_OFFSIZE_ADDR(p_info->public_base, 210 PUBLIC_MFW_MB)); 211 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 212 p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr); 213 214 /* Get the current driver mailbox sequence before sending 215 * the first command 216 */ 217 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 218 DRV_MSG_SEQ_NUMBER_MASK; 219 220 /* Get current FW pulse sequence */ 221 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 222 DRV_PULSE_SEQ_MASK; 223 224 p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 225 226 return 0; 227 } 228 229 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 230 { 231 struct qed_mcp_info *p_info; 232 u32 size; 233 234 /* Allocate mcp_info structure */ 235 p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 236 if (!p_hwfn->mcp_info) 237 goto err; 238 p_info = p_hwfn->mcp_info; 239 240 /* Initialize the MFW spinlock */ 241 spin_lock_init(&p_info->cmd_lock); 242 spin_lock_init(&p_info->link_lock); 243 244 INIT_LIST_HEAD(&p_info->cmd_list); 245 246 if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 247 DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 248 /* Do not free mcp_info here, since public_base indicate that 249 * the MCP is not initialized 250 */ 251 return 0; 252 } 253 254 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 255 p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 256 p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 257 if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 258 goto err; 259 260 return 0; 261 262 err: 263 qed_mcp_free(p_hwfn); 264 return -ENOMEM; 265 } 266 267 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 268 struct qed_ptt *p_ptt) 269 { 270 u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 271 272 /* Use MCP history register to check if MCP reset occurred between init 273 * time and now. 274 */ 275 if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 276 DP_VERBOSE(p_hwfn, 277 QED_MSG_SP, 278 "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 279 p_hwfn->mcp_info->mcp_hist, generic_por_0); 280 281 qed_load_mcp_offsets(p_hwfn, p_ptt); 282 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 283 } 284 } 285 286 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 287 { 288 u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0; 289 int rc = 0; 290 291 /* Ensure that only a single thread is accessing the mailbox */ 292 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 293 294 org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 295 296 /* Set drv command along with the updated sequence */ 297 qed_mcp_reread_offsets(p_hwfn, p_ptt); 298 seq = ++p_hwfn->mcp_info->drv_mb_seq; 299 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 300 301 do { 302 /* Wait for MFW response */ 303 udelay(delay); 304 /* Give the FW up to 500 second (50*1000*10usec) */ 305 } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 306 MISCS_REG_GENERIC_POR_0)) && 307 (cnt++ < QED_MCP_RESET_RETRIES)); 308 309 if (org_mcp_reset_seq != 310 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 311 DP_VERBOSE(p_hwfn, QED_MSG_SP, 312 "MCP was reset after %d usec\n", cnt * delay); 313 } else { 314 DP_ERR(p_hwfn, "Failed to reset MCP\n"); 315 rc = -EAGAIN; 316 } 317 318 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 319 320 return rc; 321 } 322 323 /* Must be called while cmd_lock is acquired */ 324 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 325 { 326 struct qed_mcp_cmd_elem *p_cmd_elem; 327 328 /* There is at most one pending command at a certain time, and if it 329 * exists - it is placed at the HEAD of the list. 330 */ 331 if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 332 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 333 struct qed_mcp_cmd_elem, list); 334 return !p_cmd_elem->b_is_completed; 335 } 336 337 return false; 338 } 339 340 /* Must be called while cmd_lock is acquired */ 341 static int 342 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 343 { 344 struct qed_mcp_mb_params *p_mb_params; 345 struct qed_mcp_cmd_elem *p_cmd_elem; 346 u32 mcp_resp; 347 u16 seq_num; 348 349 mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 350 seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 351 352 /* Return if no new non-handled response has been received */ 353 if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 354 return -EAGAIN; 355 356 p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 357 if (!p_cmd_elem) { 358 DP_ERR(p_hwfn, 359 "Failed to find a pending mailbox cmd that expects sequence number %d\n", 360 seq_num); 361 return -EINVAL; 362 } 363 364 p_mb_params = p_cmd_elem->p_mb_params; 365 366 /* Get the MFW response along with the sequence number */ 367 p_mb_params->mcp_resp = mcp_resp; 368 369 /* Get the MFW param */ 370 p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 371 372 /* Get the union data */ 373 if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 374 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 375 offsetof(struct public_drv_mb, 376 union_data); 377 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 378 union_data_addr, p_mb_params->data_dst_size); 379 } 380 381 p_cmd_elem->b_is_completed = true; 382 383 return 0; 384 } 385 386 /* Must be called while cmd_lock is acquired */ 387 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 388 struct qed_ptt *p_ptt, 389 struct qed_mcp_mb_params *p_mb_params, 390 u16 seq_num) 391 { 392 union drv_union_data union_data; 393 u32 union_data_addr; 394 395 /* Set the union data */ 396 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 397 offsetof(struct public_drv_mb, union_data); 398 memset(&union_data, 0, sizeof(union_data)); 399 if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 400 memcpy(&union_data, p_mb_params->p_data_src, 401 p_mb_params->data_src_size); 402 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 403 sizeof(union_data)); 404 405 /* Set the drv param */ 406 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 407 408 /* Set the drv command along with the sequence number */ 409 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 410 411 DP_VERBOSE(p_hwfn, QED_MSG_SP, 412 "MFW mailbox: command 0x%08x param 0x%08x\n", 413 (p_mb_params->cmd | seq_num), p_mb_params->param); 414 } 415 416 static int 417 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 418 struct qed_ptt *p_ptt, 419 struct qed_mcp_mb_params *p_mb_params, 420 u32 max_retries, u32 delay) 421 { 422 struct qed_mcp_cmd_elem *p_cmd_elem; 423 u32 cnt = 0; 424 u16 seq_num; 425 int rc = 0; 426 427 /* Wait until the mailbox is non-occupied */ 428 do { 429 /* Exit the loop if there is no pending command, or if the 430 * pending command is completed during this iteration. 431 * The spinlock stays locked until the command is sent. 432 */ 433 434 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 435 436 if (!qed_mcp_has_pending_cmd(p_hwfn)) 437 break; 438 439 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 440 if (!rc) 441 break; 442 else if (rc != -EAGAIN) 443 goto err; 444 445 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 446 udelay(delay); 447 } while (++cnt < max_retries); 448 449 if (cnt >= max_retries) { 450 DP_NOTICE(p_hwfn, 451 "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 452 p_mb_params->cmd, p_mb_params->param); 453 return -EAGAIN; 454 } 455 456 /* Send the mailbox command */ 457 qed_mcp_reread_offsets(p_hwfn, p_ptt); 458 seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 459 p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 460 if (!p_cmd_elem) { 461 rc = -ENOMEM; 462 goto err; 463 } 464 465 __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 466 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 467 468 /* Wait for the MFW response */ 469 do { 470 /* Exit the loop if the command is already completed, or if the 471 * command is completed during this iteration. 472 * The spinlock stays locked until the list element is removed. 473 */ 474 475 udelay(delay); 476 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 477 478 if (p_cmd_elem->b_is_completed) 479 break; 480 481 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 482 if (!rc) 483 break; 484 else if (rc != -EAGAIN) 485 goto err; 486 487 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 488 } while (++cnt < max_retries); 489 490 if (cnt >= max_retries) { 491 DP_NOTICE(p_hwfn, 492 "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 493 p_mb_params->cmd, p_mb_params->param); 494 495 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 496 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 497 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 498 499 return -EAGAIN; 500 } 501 502 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 503 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 504 505 DP_VERBOSE(p_hwfn, 506 QED_MSG_SP, 507 "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 508 p_mb_params->mcp_resp, 509 p_mb_params->mcp_param, 510 (cnt * delay) / 1000, (cnt * delay) % 1000); 511 512 /* Clear the sequence number from the MFW response */ 513 p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 514 515 return 0; 516 517 err: 518 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 519 return rc; 520 } 521 522 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 523 struct qed_ptt *p_ptt, 524 struct qed_mcp_mb_params *p_mb_params) 525 { 526 size_t union_data_size = sizeof(union drv_union_data); 527 u32 max_retries = QED_DRV_MB_MAX_RETRIES; 528 u32 delay = CHIP_MCP_RESP_ITER_US; 529 530 /* MCP not initialized */ 531 if (!qed_mcp_is_init(p_hwfn)) { 532 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 533 return -EBUSY; 534 } 535 536 if (p_mb_params->data_src_size > union_data_size || 537 p_mb_params->data_dst_size > union_data_size) { 538 DP_ERR(p_hwfn, 539 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 540 p_mb_params->data_src_size, 541 p_mb_params->data_dst_size, union_data_size); 542 return -EINVAL; 543 } 544 545 return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 546 delay); 547 } 548 549 int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 550 struct qed_ptt *p_ptt, 551 u32 cmd, 552 u32 param, 553 u32 *o_mcp_resp, 554 u32 *o_mcp_param) 555 { 556 struct qed_mcp_mb_params mb_params; 557 int rc; 558 559 memset(&mb_params, 0, sizeof(mb_params)); 560 mb_params.cmd = cmd; 561 mb_params.param = param; 562 563 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 564 if (rc) 565 return rc; 566 567 *o_mcp_resp = mb_params.mcp_resp; 568 *o_mcp_param = mb_params.mcp_param; 569 570 return 0; 571 } 572 573 static int 574 qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 575 struct qed_ptt *p_ptt, 576 u32 cmd, 577 u32 param, 578 u32 *o_mcp_resp, 579 u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 580 { 581 struct qed_mcp_mb_params mb_params; 582 int rc; 583 584 memset(&mb_params, 0, sizeof(mb_params)); 585 mb_params.cmd = cmd; 586 mb_params.param = param; 587 mb_params.p_data_src = i_buf; 588 mb_params.data_src_size = (u8)i_txn_size; 589 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 590 if (rc) 591 return rc; 592 593 *o_mcp_resp = mb_params.mcp_resp; 594 *o_mcp_param = mb_params.mcp_param; 595 596 /* nvm_info needs to be updated */ 597 p_hwfn->nvm_info.valid = false; 598 599 return 0; 600 } 601 602 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 603 struct qed_ptt *p_ptt, 604 u32 cmd, 605 u32 param, 606 u32 *o_mcp_resp, 607 u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 608 { 609 struct qed_mcp_mb_params mb_params; 610 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 611 int rc; 612 613 memset(&mb_params, 0, sizeof(mb_params)); 614 mb_params.cmd = cmd; 615 mb_params.param = param; 616 mb_params.p_data_dst = raw_data; 617 618 /* Use the maximal value since the actual one is part of the response */ 619 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 620 621 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 622 if (rc) 623 return rc; 624 625 *o_mcp_resp = mb_params.mcp_resp; 626 *o_mcp_param = mb_params.mcp_param; 627 628 *o_txn_size = *o_mcp_param; 629 memcpy(o_buf, raw_data, *o_txn_size); 630 631 return 0; 632 } 633 634 static bool 635 qed_mcp_can_force_load(u8 drv_role, 636 u8 exist_drv_role, 637 enum qed_override_force_load override_force_load) 638 { 639 bool can_force_load = false; 640 641 switch (override_force_load) { 642 case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 643 can_force_load = true; 644 break; 645 case QED_OVERRIDE_FORCE_LOAD_NEVER: 646 can_force_load = false; 647 break; 648 default: 649 can_force_load = (drv_role == DRV_ROLE_OS && 650 exist_drv_role == DRV_ROLE_PREBOOT) || 651 (drv_role == DRV_ROLE_KDUMP && 652 exist_drv_role == DRV_ROLE_OS); 653 break; 654 } 655 656 return can_force_load; 657 } 658 659 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 660 struct qed_ptt *p_ptt) 661 { 662 u32 resp = 0, param = 0; 663 int rc; 664 665 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 666 &resp, ¶m); 667 if (rc) 668 DP_NOTICE(p_hwfn, 669 "Failed to send cancel load request, rc = %d\n", rc); 670 671 return rc; 672 } 673 674 #define CONFIG_QEDE_BITMAP_IDX BIT(0) 675 #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 676 #define CONFIG_QEDR_BITMAP_IDX BIT(2) 677 #define CONFIG_QEDF_BITMAP_IDX BIT(4) 678 #define CONFIG_QEDI_BITMAP_IDX BIT(5) 679 #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 680 681 static u32 qed_get_config_bitmap(void) 682 { 683 u32 config_bitmap = 0x0; 684 685 if (IS_ENABLED(CONFIG_QEDE)) 686 config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 687 688 if (IS_ENABLED(CONFIG_QED_SRIOV)) 689 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 690 691 if (IS_ENABLED(CONFIG_QED_RDMA)) 692 config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 693 694 if (IS_ENABLED(CONFIG_QED_FCOE)) 695 config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 696 697 if (IS_ENABLED(CONFIG_QED_ISCSI)) 698 config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 699 700 if (IS_ENABLED(CONFIG_QED_LL2)) 701 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 702 703 return config_bitmap; 704 } 705 706 struct qed_load_req_in_params { 707 u8 hsi_ver; 708 #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 709 #define QED_LOAD_REQ_HSI_VER_1 1 710 u32 drv_ver_0; 711 u32 drv_ver_1; 712 u32 fw_ver; 713 u8 drv_role; 714 u8 timeout_val; 715 u8 force_cmd; 716 bool avoid_eng_reset; 717 }; 718 719 struct qed_load_req_out_params { 720 u32 load_code; 721 u32 exist_drv_ver_0; 722 u32 exist_drv_ver_1; 723 u32 exist_fw_ver; 724 u8 exist_drv_role; 725 u8 mfw_hsi_ver; 726 bool drv_exists; 727 }; 728 729 static int 730 __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 731 struct qed_ptt *p_ptt, 732 struct qed_load_req_in_params *p_in_params, 733 struct qed_load_req_out_params *p_out_params) 734 { 735 struct qed_mcp_mb_params mb_params; 736 struct load_req_stc load_req; 737 struct load_rsp_stc load_rsp; 738 u32 hsi_ver; 739 int rc; 740 741 memset(&load_req, 0, sizeof(load_req)); 742 load_req.drv_ver_0 = p_in_params->drv_ver_0; 743 load_req.drv_ver_1 = p_in_params->drv_ver_1; 744 load_req.fw_ver = p_in_params->fw_ver; 745 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 746 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 747 p_in_params->timeout_val); 748 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 749 p_in_params->force_cmd); 750 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 751 p_in_params->avoid_eng_reset); 752 753 hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 754 DRV_ID_MCP_HSI_VER_CURRENT : 755 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 756 757 memset(&mb_params, 0, sizeof(mb_params)); 758 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 759 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 760 mb_params.p_data_src = &load_req; 761 mb_params.data_src_size = sizeof(load_req); 762 mb_params.p_data_dst = &load_rsp; 763 mb_params.data_dst_size = sizeof(load_rsp); 764 765 DP_VERBOSE(p_hwfn, QED_MSG_SP, 766 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 767 mb_params.param, 768 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 769 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 770 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 771 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 772 773 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 774 DP_VERBOSE(p_hwfn, QED_MSG_SP, 775 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 776 load_req.drv_ver_0, 777 load_req.drv_ver_1, 778 load_req.fw_ver, 779 load_req.misc0, 780 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 781 QED_MFW_GET_FIELD(load_req.misc0, 782 LOAD_REQ_LOCK_TO), 783 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 784 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 785 } 786 787 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 788 if (rc) { 789 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 790 return rc; 791 } 792 793 DP_VERBOSE(p_hwfn, QED_MSG_SP, 794 "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 795 p_out_params->load_code = mb_params.mcp_resp; 796 797 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 798 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 799 DP_VERBOSE(p_hwfn, 800 QED_MSG_SP, 801 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 802 load_rsp.drv_ver_0, 803 load_rsp.drv_ver_1, 804 load_rsp.fw_ver, 805 load_rsp.misc0, 806 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 807 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 808 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 809 810 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 811 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 812 p_out_params->exist_fw_ver = load_rsp.fw_ver; 813 p_out_params->exist_drv_role = 814 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 815 p_out_params->mfw_hsi_ver = 816 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 817 p_out_params->drv_exists = 818 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 819 LOAD_RSP_FLAGS0_DRV_EXISTS; 820 } 821 822 return 0; 823 } 824 825 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 826 enum qed_drv_role drv_role, 827 u8 *p_mfw_drv_role) 828 { 829 switch (drv_role) { 830 case QED_DRV_ROLE_OS: 831 *p_mfw_drv_role = DRV_ROLE_OS; 832 break; 833 case QED_DRV_ROLE_KDUMP: 834 *p_mfw_drv_role = DRV_ROLE_KDUMP; 835 break; 836 default: 837 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 838 return -EINVAL; 839 } 840 841 return 0; 842 } 843 844 enum qed_load_req_force { 845 QED_LOAD_REQ_FORCE_NONE, 846 QED_LOAD_REQ_FORCE_PF, 847 QED_LOAD_REQ_FORCE_ALL, 848 }; 849 850 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 851 852 enum qed_load_req_force force_cmd, 853 u8 *p_mfw_force_cmd) 854 { 855 switch (force_cmd) { 856 case QED_LOAD_REQ_FORCE_NONE: 857 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 858 break; 859 case QED_LOAD_REQ_FORCE_PF: 860 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 861 break; 862 case QED_LOAD_REQ_FORCE_ALL: 863 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 864 break; 865 } 866 } 867 868 int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 869 struct qed_ptt *p_ptt, 870 struct qed_load_req_params *p_params) 871 { 872 struct qed_load_req_out_params out_params; 873 struct qed_load_req_in_params in_params; 874 u8 mfw_drv_role, mfw_force_cmd; 875 int rc; 876 877 memset(&in_params, 0, sizeof(in_params)); 878 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 879 in_params.drv_ver_0 = QED_VERSION; 880 in_params.drv_ver_1 = qed_get_config_bitmap(); 881 in_params.fw_ver = STORM_FW_VERSION; 882 rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 883 if (rc) 884 return rc; 885 886 in_params.drv_role = mfw_drv_role; 887 in_params.timeout_val = p_params->timeout_val; 888 qed_get_mfw_force_cmd(p_hwfn, 889 QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 890 891 in_params.force_cmd = mfw_force_cmd; 892 in_params.avoid_eng_reset = p_params->avoid_eng_reset; 893 894 memset(&out_params, 0, sizeof(out_params)); 895 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 896 if (rc) 897 return rc; 898 899 /* First handle cases where another load request should/might be sent: 900 * - MFW expects the old interface [HSI version = 1] 901 * - MFW responds that a force load request is required 902 */ 903 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 904 DP_INFO(p_hwfn, 905 "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 906 907 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 908 memset(&out_params, 0, sizeof(out_params)); 909 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 910 if (rc) 911 return rc; 912 } else if (out_params.load_code == 913 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 914 if (qed_mcp_can_force_load(in_params.drv_role, 915 out_params.exist_drv_role, 916 p_params->override_force_load)) { 917 DP_INFO(p_hwfn, 918 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 919 in_params.drv_role, in_params.fw_ver, 920 in_params.drv_ver_0, in_params.drv_ver_1, 921 out_params.exist_drv_role, 922 out_params.exist_fw_ver, 923 out_params.exist_drv_ver_0, 924 out_params.exist_drv_ver_1); 925 926 qed_get_mfw_force_cmd(p_hwfn, 927 QED_LOAD_REQ_FORCE_ALL, 928 &mfw_force_cmd); 929 930 in_params.force_cmd = mfw_force_cmd; 931 memset(&out_params, 0, sizeof(out_params)); 932 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 933 &out_params); 934 if (rc) 935 return rc; 936 } else { 937 DP_NOTICE(p_hwfn, 938 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 939 in_params.drv_role, in_params.fw_ver, 940 in_params.drv_ver_0, in_params.drv_ver_1, 941 out_params.exist_drv_role, 942 out_params.exist_fw_ver, 943 out_params.exist_drv_ver_0, 944 out_params.exist_drv_ver_1); 945 DP_NOTICE(p_hwfn, 946 "Avoid sending a force load request to prevent disruption of active PFs\n"); 947 948 qed_mcp_cancel_load_req(p_hwfn, p_ptt); 949 return -EBUSY; 950 } 951 } 952 953 /* Now handle the other types of responses. 954 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 955 * expected here after the additional revised load requests were sent. 956 */ 957 switch (out_params.load_code) { 958 case FW_MSG_CODE_DRV_LOAD_ENGINE: 959 case FW_MSG_CODE_DRV_LOAD_PORT: 960 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 961 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 962 out_params.drv_exists) { 963 /* The role and fw/driver version match, but the PF is 964 * already loaded and has not been unloaded gracefully. 965 */ 966 DP_NOTICE(p_hwfn, 967 "PF is already loaded\n"); 968 return -EINVAL; 969 } 970 break; 971 default: 972 DP_NOTICE(p_hwfn, 973 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 974 out_params.load_code); 975 return -EBUSY; 976 } 977 978 p_params->load_code = out_params.load_code; 979 980 return 0; 981 } 982 983 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 984 { 985 u32 wol_param, mcp_resp, mcp_param; 986 987 switch (p_hwfn->cdev->wol_config) { 988 case QED_OV_WOL_DISABLED: 989 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 990 break; 991 case QED_OV_WOL_ENABLED: 992 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 993 break; 994 default: 995 DP_NOTICE(p_hwfn, 996 "Unknown WoL configuration %02x\n", 997 p_hwfn->cdev->wol_config); 998 /* Fallthrough */ 999 case QED_OV_WOL_DEFAULT: 1000 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 1001 } 1002 1003 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param, 1004 &mcp_resp, &mcp_param); 1005 } 1006 1007 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1008 { 1009 struct qed_mcp_mb_params mb_params; 1010 struct mcp_mac wol_mac; 1011 1012 memset(&mb_params, 0, sizeof(mb_params)); 1013 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 1014 1015 /* Set the primary MAC if WoL is enabled */ 1016 if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 1017 u8 *p_mac = p_hwfn->cdev->wol_mac; 1018 1019 memset(&wol_mac, 0, sizeof(wol_mac)); 1020 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 1021 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 1022 p_mac[4] << 8 | p_mac[5]; 1023 1024 DP_VERBOSE(p_hwfn, 1025 (QED_MSG_SP | NETIF_MSG_IFDOWN), 1026 "Setting WoL MAC: %pM --> [%08x,%08x]\n", 1027 p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 1028 1029 mb_params.p_data_src = &wol_mac; 1030 mb_params.data_src_size = sizeof(wol_mac); 1031 } 1032 1033 return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1034 } 1035 1036 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 1037 struct qed_ptt *p_ptt) 1038 { 1039 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1040 PUBLIC_PATH); 1041 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1042 u32 path_addr = SECTION_ADDR(mfw_path_offsize, 1043 QED_PATH_ID(p_hwfn)); 1044 u32 disabled_vfs[VF_MAX_STATIC / 32]; 1045 int i; 1046 1047 DP_VERBOSE(p_hwfn, 1048 QED_MSG_SP, 1049 "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 1050 mfw_path_offsize, path_addr); 1051 1052 for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 1053 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 1054 path_addr + 1055 offsetof(struct public_path, 1056 mcp_vf_disabled) + 1057 sizeof(u32) * i); 1058 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 1059 "FLR-ed VFs [%08x,...,%08x] - %08x\n", 1060 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 1061 } 1062 1063 if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 1064 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 1065 } 1066 1067 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 1068 struct qed_ptt *p_ptt, u32 *vfs_to_ack) 1069 { 1070 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1071 PUBLIC_FUNC); 1072 u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 1073 u32 func_addr = SECTION_ADDR(mfw_func_offsize, 1074 MCP_PF_ID(p_hwfn)); 1075 struct qed_mcp_mb_params mb_params; 1076 int rc; 1077 int i; 1078 1079 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 1080 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 1081 "Acking VFs [%08x,...,%08x] - %08x\n", 1082 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 1083 1084 memset(&mb_params, 0, sizeof(mb_params)); 1085 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 1086 mb_params.p_data_src = vfs_to_ack; 1087 mb_params.data_src_size = VF_MAX_STATIC / 8; 1088 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1089 if (rc) { 1090 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 1091 return -EBUSY; 1092 } 1093 1094 /* Clear the ACK bits */ 1095 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 1096 qed_wr(p_hwfn, p_ptt, 1097 func_addr + 1098 offsetof(struct public_func, drv_ack_vf_disabled) + 1099 i * sizeof(u32), 0); 1100 1101 return rc; 1102 } 1103 1104 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1105 struct qed_ptt *p_ptt) 1106 { 1107 u32 transceiver_state; 1108 1109 transceiver_state = qed_rd(p_hwfn, p_ptt, 1110 p_hwfn->mcp_info->port_addr + 1111 offsetof(struct public_port, 1112 transceiver_data)); 1113 1114 DP_VERBOSE(p_hwfn, 1115 (NETIF_MSG_HW | QED_MSG_SP), 1116 "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1117 transceiver_state, 1118 (u32)(p_hwfn->mcp_info->port_addr + 1119 offsetof(struct public_port, transceiver_data))); 1120 1121 transceiver_state = GET_FIELD(transceiver_state, 1122 ETH_TRANSCEIVER_STATE); 1123 1124 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1125 DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1126 else 1127 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1128 } 1129 1130 static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1131 struct qed_ptt *p_ptt, 1132 struct qed_mcp_link_state *p_link) 1133 { 1134 u32 eee_status, val; 1135 1136 p_link->eee_adv_caps = 0; 1137 p_link->eee_lp_adv_caps = 0; 1138 eee_status = qed_rd(p_hwfn, 1139 p_ptt, 1140 p_hwfn->mcp_info->port_addr + 1141 offsetof(struct public_port, eee_status)); 1142 p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1143 val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1144 if (val & EEE_1G_ADV) 1145 p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1146 if (val & EEE_10G_ADV) 1147 p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1148 val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1149 if (val & EEE_1G_ADV) 1150 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1151 if (val & EEE_10G_ADV) 1152 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1153 } 1154 1155 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 1156 struct qed_ptt *p_ptt, bool b_reset) 1157 { 1158 struct qed_mcp_link_state *p_link; 1159 u8 max_bw, min_bw; 1160 u32 status = 0; 1161 1162 /* Prevent SW/attentions from doing this at the same time */ 1163 spin_lock_bh(&p_hwfn->mcp_info->link_lock); 1164 1165 p_link = &p_hwfn->mcp_info->link_output; 1166 memset(p_link, 0, sizeof(*p_link)); 1167 if (!b_reset) { 1168 status = qed_rd(p_hwfn, p_ptt, 1169 p_hwfn->mcp_info->port_addr + 1170 offsetof(struct public_port, link_status)); 1171 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1172 "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1173 status, 1174 (u32)(p_hwfn->mcp_info->port_addr + 1175 offsetof(struct public_port, link_status))); 1176 } else { 1177 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1178 "Resetting link indications\n"); 1179 goto out; 1180 } 1181 1182 if (p_hwfn->b_drv_link_init) 1183 p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1184 else 1185 p_link->link_up = false; 1186 1187 p_link->full_duplex = true; 1188 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1189 case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1190 p_link->speed = 100000; 1191 break; 1192 case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1193 p_link->speed = 50000; 1194 break; 1195 case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1196 p_link->speed = 40000; 1197 break; 1198 case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1199 p_link->speed = 25000; 1200 break; 1201 case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1202 p_link->speed = 20000; 1203 break; 1204 case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1205 p_link->speed = 10000; 1206 break; 1207 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1208 p_link->full_duplex = false; 1209 /* Fall-through */ 1210 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1211 p_link->speed = 1000; 1212 break; 1213 default: 1214 p_link->speed = 0; 1215 p_link->link_up = 0; 1216 } 1217 1218 if (p_link->link_up && p_link->speed) 1219 p_link->line_speed = p_link->speed; 1220 else 1221 p_link->line_speed = 0; 1222 1223 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1224 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 1225 1226 /* Max bandwidth configuration */ 1227 __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1228 1229 /* Min bandwidth configuration */ 1230 __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 1231 qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 1232 p_link->min_pf_rate); 1233 1234 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1235 p_link->an_complete = !!(status & 1236 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1237 p_link->parallel_detection = !!(status & 1238 LINK_STATUS_PARALLEL_DETECTION_USED); 1239 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1240 1241 p_link->partner_adv_speed |= 1242 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1243 QED_LINK_PARTNER_SPEED_1G_FD : 0; 1244 p_link->partner_adv_speed |= 1245 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1246 QED_LINK_PARTNER_SPEED_1G_HD : 0; 1247 p_link->partner_adv_speed |= 1248 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1249 QED_LINK_PARTNER_SPEED_10G : 0; 1250 p_link->partner_adv_speed |= 1251 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1252 QED_LINK_PARTNER_SPEED_20G : 0; 1253 p_link->partner_adv_speed |= 1254 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1255 QED_LINK_PARTNER_SPEED_25G : 0; 1256 p_link->partner_adv_speed |= 1257 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1258 QED_LINK_PARTNER_SPEED_40G : 0; 1259 p_link->partner_adv_speed |= 1260 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1261 QED_LINK_PARTNER_SPEED_50G : 0; 1262 p_link->partner_adv_speed |= 1263 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1264 QED_LINK_PARTNER_SPEED_100G : 0; 1265 1266 p_link->partner_tx_flow_ctrl_en = 1267 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1268 p_link->partner_rx_flow_ctrl_en = 1269 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1270 1271 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1272 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1273 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1274 break; 1275 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1276 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1277 break; 1278 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1279 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1280 break; 1281 default: 1282 p_link->partner_adv_pause = 0; 1283 } 1284 1285 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1286 1287 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1288 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1289 1290 qed_link_update(p_hwfn); 1291 out: 1292 spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1293 } 1294 1295 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1296 { 1297 struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 1298 struct qed_mcp_mb_params mb_params; 1299 struct eth_phy_cfg phy_cfg; 1300 int rc = 0; 1301 u32 cmd; 1302 1303 /* Set the shmem configuration according to params */ 1304 memset(&phy_cfg, 0, sizeof(phy_cfg)); 1305 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1306 if (!params->speed.autoneg) 1307 phy_cfg.speed = params->speed.forced_speed; 1308 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 1309 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 1310 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 1311 phy_cfg.adv_speed = params->speed.advertised_speeds; 1312 phy_cfg.loopback_mode = params->loopback_mode; 1313 1314 /* There are MFWs that share this capability regardless of whether 1315 * this is feasible or not. And given that at the very least adv_caps 1316 * would be set internally by qed, we want to make sure LFA would 1317 * still work. 1318 */ 1319 if ((p_hwfn->mcp_info->capabilities & 1320 FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1321 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1322 if (params->eee.tx_lpi_enable) 1323 phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1324 if (params->eee.adv_caps & QED_EEE_1G_ADV) 1325 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1326 if (params->eee.adv_caps & QED_EEE_10G_ADV) 1327 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1328 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1329 EEE_TX_TIMER_USEC_OFFSET) & 1330 EEE_TX_TIMER_USEC_MASK; 1331 } 1332 1333 p_hwfn->b_drv_link_init = b_up; 1334 1335 if (b_up) { 1336 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1337 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 1338 phy_cfg.speed, 1339 phy_cfg.pause, 1340 phy_cfg.adv_speed, 1341 phy_cfg.loopback_mode, 1342 phy_cfg.feature_config_flags); 1343 } else { 1344 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1345 "Resetting link\n"); 1346 } 1347 1348 memset(&mb_params, 0, sizeof(mb_params)); 1349 mb_params.cmd = cmd; 1350 mb_params.p_data_src = &phy_cfg; 1351 mb_params.data_src_size = sizeof(phy_cfg); 1352 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1353 1354 /* if mcp fails to respond we must abort */ 1355 if (rc) { 1356 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1357 return rc; 1358 } 1359 1360 /* Mimic link-change attention, done for several reasons: 1361 * - On reset, there's no guarantee MFW would trigger 1362 * an attention. 1363 * - On initialization, older MFWs might not indicate link change 1364 * during LFA, so we'll never get an UP indication. 1365 */ 1366 qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1367 1368 return 0; 1369 } 1370 1371 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 1372 struct qed_ptt *p_ptt, 1373 enum MFW_DRV_MSG_TYPE type) 1374 { 1375 enum qed_mcp_protocol_type stats_type; 1376 union qed_mcp_protocol_stats stats; 1377 struct qed_mcp_mb_params mb_params; 1378 u32 hsi_param; 1379 1380 switch (type) { 1381 case MFW_DRV_MSG_GET_LAN_STATS: 1382 stats_type = QED_MCP_LAN_STATS; 1383 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 1384 break; 1385 case MFW_DRV_MSG_GET_FCOE_STATS: 1386 stats_type = QED_MCP_FCOE_STATS; 1387 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 1388 break; 1389 case MFW_DRV_MSG_GET_ISCSI_STATS: 1390 stats_type = QED_MCP_ISCSI_STATS; 1391 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 1392 break; 1393 case MFW_DRV_MSG_GET_RDMA_STATS: 1394 stats_type = QED_MCP_RDMA_STATS; 1395 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 1396 break; 1397 default: 1398 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 1399 return; 1400 } 1401 1402 qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 1403 1404 memset(&mb_params, 0, sizeof(mb_params)); 1405 mb_params.cmd = DRV_MSG_CODE_GET_STATS; 1406 mb_params.param = hsi_param; 1407 mb_params.p_data_src = &stats; 1408 mb_params.data_src_size = sizeof(stats); 1409 qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1410 } 1411 1412 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 1413 struct public_func *p_shmem_info) 1414 { 1415 struct qed_mcp_function_info *p_info; 1416 1417 p_info = &p_hwfn->mcp_info->func_info; 1418 1419 p_info->bandwidth_min = (p_shmem_info->config & 1420 FUNC_MF_CFG_MIN_BW_MASK) >> 1421 FUNC_MF_CFG_MIN_BW_SHIFT; 1422 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 1423 DP_INFO(p_hwfn, 1424 "bandwidth minimum out of bounds [%02x]. Set to 1\n", 1425 p_info->bandwidth_min); 1426 p_info->bandwidth_min = 1; 1427 } 1428 1429 p_info->bandwidth_max = (p_shmem_info->config & 1430 FUNC_MF_CFG_MAX_BW_MASK) >> 1431 FUNC_MF_CFG_MAX_BW_SHIFT; 1432 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 1433 DP_INFO(p_hwfn, 1434 "bandwidth maximum out of bounds [%02x]. Set to 100\n", 1435 p_info->bandwidth_max); 1436 p_info->bandwidth_max = 100; 1437 } 1438 } 1439 1440 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 1441 struct qed_ptt *p_ptt, 1442 struct public_func *p_data, int pfid) 1443 { 1444 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1445 PUBLIC_FUNC); 1446 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1447 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 1448 u32 i, size; 1449 1450 memset(p_data, 0, sizeof(*p_data)); 1451 1452 size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 1453 for (i = 0; i < size / sizeof(u32); i++) 1454 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 1455 func_addr + (i << 2)); 1456 return size; 1457 } 1458 1459 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1460 { 1461 struct qed_mcp_function_info *p_info; 1462 struct public_func shmem_info; 1463 u32 resp = 0, param = 0; 1464 1465 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1466 1467 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1468 1469 p_info = &p_hwfn->mcp_info->func_info; 1470 1471 qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 1472 qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 1473 1474 /* Acknowledge the MFW */ 1475 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 1476 ¶m); 1477 } 1478 1479 static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1480 { 1481 struct public_func shmem_info; 1482 u32 resp = 0, param = 0; 1483 1484 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1485 1486 p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 1487 FUNC_MF_CFG_OV_STAG_MASK; 1488 p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 1489 if ((p_hwfn->hw_info.hw_mode & BIT(MODE_MF_SD)) && 1490 (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET)) { 1491 qed_wr(p_hwfn, p_ptt, 1492 NIG_REG_LLH_FUNC_TAG_VALUE, p_hwfn->hw_info.ovlan); 1493 qed_sp_pf_update_stag(p_hwfn); 1494 } 1495 1496 /* Acknowledge the MFW */ 1497 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 1498 &resp, ¶m); 1499 } 1500 1501 void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1502 { 1503 struct public_func shmem_info; 1504 u32 port_cfg, val; 1505 1506 if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1507 return; 1508 1509 memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1510 port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1511 offsetof(struct public_port, oem_cfg_port)); 1512 val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1513 OEM_CFG_CHANNEL_TYPE_OFFSET; 1514 if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1515 DP_NOTICE(p_hwfn, "Incorrect UFP Channel type %d\n", val); 1516 1517 val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1518 if (val == OEM_CFG_SCHED_TYPE_ETS) { 1519 p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1520 } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1521 p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1522 } else { 1523 p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1524 DP_NOTICE(p_hwfn, "Unknown UFP scheduling mode %d\n", val); 1525 } 1526 1527 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1528 val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1529 OEM_CFG_FUNC_TC_OFFSET; 1530 p_hwfn->ufp_info.tc = (u8)val; 1531 val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1532 OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1533 if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1534 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1535 } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1536 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1537 } else { 1538 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1539 DP_NOTICE(p_hwfn, "Unknown Host priority control %d\n", val); 1540 } 1541 1542 DP_NOTICE(p_hwfn, 1543 "UFP shmem config: mode = %d tc = %d pri_type = %d\n", 1544 p_hwfn->ufp_info.mode, 1545 p_hwfn->ufp_info.tc, p_hwfn->ufp_info.pri_type); 1546 } 1547 1548 static int 1549 qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1550 { 1551 qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1552 1553 if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1554 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1555 qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1556 p_hwfn->ufp_info.tc); 1557 1558 qed_qm_reconf(p_hwfn, p_ptt); 1559 } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1560 /* Merge UFP TC with the dcbx TC data */ 1561 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1562 QED_DCBX_OPERATIONAL_MIB); 1563 } else { 1564 DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1565 return -EINVAL; 1566 } 1567 1568 /* update storm FW with negotiation results */ 1569 qed_sp_pf_update_ufp(p_hwfn); 1570 1571 /* update stag pcp value */ 1572 qed_sp_pf_update_stag(p_hwfn); 1573 1574 return 0; 1575 } 1576 1577 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1578 struct qed_ptt *p_ptt) 1579 { 1580 struct qed_mcp_info *info = p_hwfn->mcp_info; 1581 int rc = 0; 1582 bool found = false; 1583 u16 i; 1584 1585 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1586 1587 /* Read Messages from MFW */ 1588 qed_mcp_read_mb(p_hwfn, p_ptt); 1589 1590 /* Compare current messages to old ones */ 1591 for (i = 0; i < info->mfw_mb_length; i++) { 1592 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1593 continue; 1594 1595 found = true; 1596 1597 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1598 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1599 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1600 1601 switch (i) { 1602 case MFW_DRV_MSG_LINK_CHANGE: 1603 qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1604 break; 1605 case MFW_DRV_MSG_VF_DISABLED: 1606 qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 1607 break; 1608 case MFW_DRV_MSG_LLDP_DATA_UPDATED: 1609 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1610 QED_DCBX_REMOTE_LLDP_MIB); 1611 break; 1612 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 1613 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1614 QED_DCBX_REMOTE_MIB); 1615 break; 1616 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 1617 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1618 QED_DCBX_OPERATIONAL_MIB); 1619 break; 1620 case MFW_DRV_MSG_OEM_CFG_UPDATE: 1621 qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 1622 break; 1623 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1624 qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1625 break; 1626 case MFW_DRV_MSG_GET_LAN_STATS: 1627 case MFW_DRV_MSG_GET_FCOE_STATS: 1628 case MFW_DRV_MSG_GET_ISCSI_STATS: 1629 case MFW_DRV_MSG_GET_RDMA_STATS: 1630 qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 1631 break; 1632 case MFW_DRV_MSG_BW_UPDATE: 1633 qed_mcp_update_bw(p_hwfn, p_ptt); 1634 break; 1635 case MFW_DRV_MSG_S_TAG_UPDATE: 1636 qed_mcp_update_stag(p_hwfn, p_ptt); 1637 break; 1638 case MFW_DRV_MSG_GET_TLV_REQ: 1639 qed_mfw_tlv_req(p_hwfn); 1640 break; 1641 default: 1642 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1643 rc = -EINVAL; 1644 } 1645 } 1646 1647 /* ACK everything */ 1648 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1649 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1650 1651 /* MFW expect answer in BE, so we force write in that format */ 1652 qed_wr(p_hwfn, p_ptt, 1653 info->mfw_mb_addr + sizeof(u32) + 1654 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1655 sizeof(u32) + i * sizeof(u32), 1656 (__force u32)val); 1657 } 1658 1659 if (!found) { 1660 DP_NOTICE(p_hwfn, 1661 "Received an MFW message indication but no new message!\n"); 1662 rc = -EINVAL; 1663 } 1664 1665 /* Copy the new mfw messages into the shadow */ 1666 memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1667 1668 return rc; 1669 } 1670 1671 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 1672 struct qed_ptt *p_ptt, 1673 u32 *p_mfw_ver, u32 *p_running_bundle_id) 1674 { 1675 u32 global_offsize; 1676 1677 if (IS_VF(p_hwfn->cdev)) { 1678 if (p_hwfn->vf_iov_info) { 1679 struct pfvf_acquire_resp_tlv *p_resp; 1680 1681 p_resp = &p_hwfn->vf_iov_info->acquire_resp; 1682 *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 1683 return 0; 1684 } else { 1685 DP_VERBOSE(p_hwfn, 1686 QED_MSG_IOV, 1687 "VF requested MFW version prior to ACQUIRE\n"); 1688 return -EINVAL; 1689 } 1690 } 1691 1692 global_offsize = qed_rd(p_hwfn, p_ptt, 1693 SECTION_OFFSIZE_ADDR(p_hwfn-> 1694 mcp_info->public_base, 1695 PUBLIC_GLOBAL)); 1696 *p_mfw_ver = 1697 qed_rd(p_hwfn, p_ptt, 1698 SECTION_ADDR(global_offsize, 1699 0) + offsetof(struct public_global, mfw_ver)); 1700 1701 if (p_running_bundle_id != NULL) { 1702 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 1703 SECTION_ADDR(global_offsize, 0) + 1704 offsetof(struct public_global, 1705 running_bundle_id)); 1706 } 1707 1708 return 0; 1709 } 1710 1711 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 1712 struct qed_ptt *p_ptt, u32 *p_mbi_ver) 1713 { 1714 u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 1715 1716 if (IS_VF(p_hwfn->cdev)) 1717 return -EINVAL; 1718 1719 /* Read the address of the nvm_cfg */ 1720 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1721 if (!nvm_cfg_addr) { 1722 DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1723 return -EINVAL; 1724 } 1725 1726 /* Read the offset of nvm_cfg1 */ 1727 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1728 1729 mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1730 offsetof(struct nvm_cfg1, glob) + 1731 offsetof(struct nvm_cfg1_glob, mbi_version); 1732 *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 1733 mbi_ver_addr) & 1734 (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 1735 NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 1736 NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 1737 1738 return 0; 1739 } 1740 1741 int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) 1742 { 1743 struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 1744 struct qed_ptt *p_ptt; 1745 1746 if (IS_VF(cdev)) 1747 return -EINVAL; 1748 1749 if (!qed_mcp_is_init(p_hwfn)) { 1750 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1751 return -EBUSY; 1752 } 1753 1754 *p_media_type = MEDIA_UNSPECIFIED; 1755 1756 p_ptt = qed_ptt_acquire(p_hwfn); 1757 if (!p_ptt) 1758 return -EBUSY; 1759 1760 *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1761 offsetof(struct public_port, media_type)); 1762 1763 qed_ptt_release(p_hwfn, p_ptt); 1764 1765 return 0; 1766 } 1767 1768 /* Old MFW has a global configuration for all PFs regarding RDMA support */ 1769 static void 1770 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 1771 enum qed_pci_personality *p_proto) 1772 { 1773 /* There wasn't ever a legacy MFW that published iwarp. 1774 * So at this point, this is either plain l2 or RoCE. 1775 */ 1776 if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 1777 *p_proto = QED_PCI_ETH_ROCE; 1778 else 1779 *p_proto = QED_PCI_ETH; 1780 1781 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 1782 "According to Legacy capabilities, L2 personality is %08x\n", 1783 (u32) *p_proto); 1784 } 1785 1786 static int 1787 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 1788 struct qed_ptt *p_ptt, 1789 enum qed_pci_personality *p_proto) 1790 { 1791 u32 resp = 0, param = 0; 1792 int rc; 1793 1794 rc = qed_mcp_cmd(p_hwfn, p_ptt, 1795 DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 1796 if (rc) 1797 return rc; 1798 if (resp != FW_MSG_CODE_OK) { 1799 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 1800 "MFW lacks support for command; Returns %08x\n", 1801 resp); 1802 return -EINVAL; 1803 } 1804 1805 switch (param) { 1806 case FW_MB_PARAM_GET_PF_RDMA_NONE: 1807 *p_proto = QED_PCI_ETH; 1808 break; 1809 case FW_MB_PARAM_GET_PF_RDMA_ROCE: 1810 *p_proto = QED_PCI_ETH_ROCE; 1811 break; 1812 case FW_MB_PARAM_GET_PF_RDMA_IWARP: 1813 *p_proto = QED_PCI_ETH_IWARP; 1814 break; 1815 case FW_MB_PARAM_GET_PF_RDMA_BOTH: 1816 *p_proto = QED_PCI_ETH_RDMA; 1817 break; 1818 default: 1819 DP_NOTICE(p_hwfn, 1820 "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 1821 param); 1822 return -EINVAL; 1823 } 1824 1825 DP_VERBOSE(p_hwfn, 1826 NETIF_MSG_IFUP, 1827 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 1828 (u32) *p_proto, resp, param); 1829 return 0; 1830 } 1831 1832 static int 1833 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 1834 struct public_func *p_info, 1835 struct qed_ptt *p_ptt, 1836 enum qed_pci_personality *p_proto) 1837 { 1838 int rc = 0; 1839 1840 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 1841 case FUNC_MF_CFG_PROTOCOL_ETHERNET: 1842 if (!IS_ENABLED(CONFIG_QED_RDMA)) 1843 *p_proto = QED_PCI_ETH; 1844 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 1845 qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 1846 break; 1847 case FUNC_MF_CFG_PROTOCOL_ISCSI: 1848 *p_proto = QED_PCI_ISCSI; 1849 break; 1850 case FUNC_MF_CFG_PROTOCOL_FCOE: 1851 *p_proto = QED_PCI_FCOE; 1852 break; 1853 case FUNC_MF_CFG_PROTOCOL_ROCE: 1854 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 1855 /* Fallthrough */ 1856 default: 1857 rc = -EINVAL; 1858 } 1859 1860 return rc; 1861 } 1862 1863 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 1864 struct qed_ptt *p_ptt) 1865 { 1866 struct qed_mcp_function_info *info; 1867 struct public_func shmem_info; 1868 1869 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1870 info = &p_hwfn->mcp_info->func_info; 1871 1872 info->pause_on_host = (shmem_info.config & 1873 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 1874 1875 if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 1876 &info->protocol)) { 1877 DP_ERR(p_hwfn, "Unknown personality %08x\n", 1878 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 1879 return -EINVAL; 1880 } 1881 1882 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1883 1884 if (shmem_info.mac_upper || shmem_info.mac_lower) { 1885 info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 1886 info->mac[1] = (u8)(shmem_info.mac_upper); 1887 info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 1888 info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 1889 info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 1890 info->mac[5] = (u8)(shmem_info.mac_lower); 1891 1892 /* Store primary MAC for later possible WoL */ 1893 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 1894 } else { 1895 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 1896 } 1897 1898 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 1899 (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 1900 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 1901 (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 1902 1903 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 1904 1905 info->mtu = (u16)shmem_info.mtu_size; 1906 1907 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 1908 p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 1909 if (qed_mcp_is_init(p_hwfn)) { 1910 u32 resp = 0, param = 0; 1911 int rc; 1912 1913 rc = qed_mcp_cmd(p_hwfn, p_ptt, 1914 DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 1915 if (rc) 1916 return rc; 1917 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 1918 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 1919 } 1920 1921 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 1922 "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 1923 info->pause_on_host, info->protocol, 1924 info->bandwidth_min, info->bandwidth_max, 1925 info->mac[0], info->mac[1], info->mac[2], 1926 info->mac[3], info->mac[4], info->mac[5], 1927 info->wwn_port, info->wwn_node, 1928 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 1929 1930 return 0; 1931 } 1932 1933 struct qed_mcp_link_params 1934 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 1935 { 1936 if (!p_hwfn || !p_hwfn->mcp_info) 1937 return NULL; 1938 return &p_hwfn->mcp_info->link_input; 1939 } 1940 1941 struct qed_mcp_link_state 1942 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 1943 { 1944 if (!p_hwfn || !p_hwfn->mcp_info) 1945 return NULL; 1946 return &p_hwfn->mcp_info->link_output; 1947 } 1948 1949 struct qed_mcp_link_capabilities 1950 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 1951 { 1952 if (!p_hwfn || !p_hwfn->mcp_info) 1953 return NULL; 1954 return &p_hwfn->mcp_info->link_capabilities; 1955 } 1956 1957 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1958 { 1959 u32 resp = 0, param = 0; 1960 int rc; 1961 1962 rc = qed_mcp_cmd(p_hwfn, p_ptt, 1963 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 1964 1965 /* Wait for the drain to complete before returning */ 1966 msleep(1020); 1967 1968 return rc; 1969 } 1970 1971 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 1972 struct qed_ptt *p_ptt, u32 *p_flash_size) 1973 { 1974 u32 flash_size; 1975 1976 if (IS_VF(p_hwfn->cdev)) 1977 return -EINVAL; 1978 1979 flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 1980 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 1981 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 1982 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 1983 1984 *p_flash_size = flash_size; 1985 1986 return 0; 1987 } 1988 1989 static int 1990 qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 1991 struct qed_ptt *p_ptt, u8 vf_id, u8 num) 1992 { 1993 u32 resp = 0, param = 0, rc_param = 0; 1994 int rc; 1995 1996 /* Only Leader can configure MSIX, and need to take CMT into account */ 1997 if (!IS_LEAD_HWFN(p_hwfn)) 1998 return 0; 1999 num *= p_hwfn->cdev->num_hwfns; 2000 2001 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 2002 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 2003 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 2004 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 2005 2006 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 2007 &resp, &rc_param); 2008 2009 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 2010 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 2011 rc = -EINVAL; 2012 } else { 2013 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 2014 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 2015 num, vf_id); 2016 } 2017 2018 return rc; 2019 } 2020 2021 static int 2022 qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 2023 struct qed_ptt *p_ptt, u8 num) 2024 { 2025 u32 resp = 0, param = num, rc_param = 0; 2026 int rc; 2027 2028 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 2029 param, &resp, &rc_param); 2030 2031 if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 2032 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 2033 rc = -EINVAL; 2034 } else { 2035 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 2036 "Requested 0x%02x MSI-x interrupts for VFs\n", num); 2037 } 2038 2039 return rc; 2040 } 2041 2042 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 2043 struct qed_ptt *p_ptt, u8 vf_id, u8 num) 2044 { 2045 if (QED_IS_BB(p_hwfn->cdev)) 2046 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 2047 else 2048 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 2049 } 2050 2051 int 2052 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2053 struct qed_ptt *p_ptt, 2054 struct qed_mcp_drv_version *p_ver) 2055 { 2056 struct qed_mcp_mb_params mb_params; 2057 struct drv_version_stc drv_version; 2058 __be32 val; 2059 u32 i; 2060 int rc; 2061 2062 memset(&drv_version, 0, sizeof(drv_version)); 2063 drv_version.version = p_ver->version; 2064 for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 2065 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 2066 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2067 } 2068 2069 memset(&mb_params, 0, sizeof(mb_params)); 2070 mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 2071 mb_params.p_data_src = &drv_version; 2072 mb_params.data_src_size = sizeof(drv_version); 2073 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 2074 if (rc) 2075 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2076 2077 return rc; 2078 } 2079 2080 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2081 { 2082 u32 resp = 0, param = 0; 2083 int rc; 2084 2085 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 2086 ¶m); 2087 if (rc) 2088 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2089 2090 return rc; 2091 } 2092 2093 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2094 { 2095 u32 value, cpu_mode; 2096 2097 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 2098 2099 value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 2100 value &= ~MCP_REG_CPU_MODE_SOFT_HALT; 2101 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value); 2102 cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 2103 2104 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0; 2105 } 2106 2107 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 2108 struct qed_ptt *p_ptt, 2109 enum qed_ov_client client) 2110 { 2111 u32 resp = 0, param = 0; 2112 u32 drv_mb_param; 2113 int rc; 2114 2115 switch (client) { 2116 case QED_OV_CLIENT_DRV: 2117 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 2118 break; 2119 case QED_OV_CLIENT_USER: 2120 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 2121 break; 2122 case QED_OV_CLIENT_VENDOR_SPEC: 2123 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 2124 break; 2125 default: 2126 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 2127 return -EINVAL; 2128 } 2129 2130 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 2131 drv_mb_param, &resp, ¶m); 2132 if (rc) 2133 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2134 2135 return rc; 2136 } 2137 2138 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 2139 struct qed_ptt *p_ptt, 2140 enum qed_ov_driver_state drv_state) 2141 { 2142 u32 resp = 0, param = 0; 2143 u32 drv_mb_param; 2144 int rc; 2145 2146 switch (drv_state) { 2147 case QED_OV_DRIVER_STATE_NOT_LOADED: 2148 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 2149 break; 2150 case QED_OV_DRIVER_STATE_DISABLED: 2151 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 2152 break; 2153 case QED_OV_DRIVER_STATE_ACTIVE: 2154 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 2155 break; 2156 default: 2157 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 2158 return -EINVAL; 2159 } 2160 2161 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 2162 drv_mb_param, &resp, ¶m); 2163 if (rc) 2164 DP_ERR(p_hwfn, "Failed to send driver state\n"); 2165 2166 return rc; 2167 } 2168 2169 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 2170 struct qed_ptt *p_ptt, u16 mtu) 2171 { 2172 u32 resp = 0, param = 0; 2173 u32 drv_mb_param; 2174 int rc; 2175 2176 drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 2177 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 2178 drv_mb_param, &resp, ¶m); 2179 if (rc) 2180 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 2181 2182 return rc; 2183 } 2184 2185 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 2186 struct qed_ptt *p_ptt, u8 *mac) 2187 { 2188 struct qed_mcp_mb_params mb_params; 2189 u32 mfw_mac[2]; 2190 int rc; 2191 2192 memset(&mb_params, 0, sizeof(mb_params)); 2193 mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 2194 mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 2195 DRV_MSG_CODE_VMAC_TYPE_SHIFT; 2196 mb_params.param |= MCP_PF_ID(p_hwfn); 2197 2198 /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 2199 * in 32-bit granularity. 2200 * So the MAC has to be set in native order [and not byte order], 2201 * otherwise it would be read incorrectly by MFW after swap. 2202 */ 2203 mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 2204 mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 2205 2206 mb_params.p_data_src = (u8 *)mfw_mac; 2207 mb_params.data_src_size = 8; 2208 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 2209 if (rc) 2210 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 2211 2212 /* Store primary MAC for later possible WoL */ 2213 memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 2214 2215 return rc; 2216 } 2217 2218 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 2219 struct qed_ptt *p_ptt, enum qed_ov_wol wol) 2220 { 2221 u32 resp = 0, param = 0; 2222 u32 drv_mb_param; 2223 int rc; 2224 2225 if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 2226 DP_VERBOSE(p_hwfn, QED_MSG_SP, 2227 "Can't change WoL configuration when WoL isn't supported\n"); 2228 return -EINVAL; 2229 } 2230 2231 switch (wol) { 2232 case QED_OV_WOL_DEFAULT: 2233 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 2234 break; 2235 case QED_OV_WOL_DISABLED: 2236 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 2237 break; 2238 case QED_OV_WOL_ENABLED: 2239 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 2240 break; 2241 default: 2242 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 2243 return -EINVAL; 2244 } 2245 2246 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 2247 drv_mb_param, &resp, ¶m); 2248 if (rc) 2249 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 2250 2251 /* Store the WoL update for a future unload */ 2252 p_hwfn->cdev->wol_config = (u8)wol; 2253 2254 return rc; 2255 } 2256 2257 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 2258 struct qed_ptt *p_ptt, 2259 enum qed_ov_eswitch eswitch) 2260 { 2261 u32 resp = 0, param = 0; 2262 u32 drv_mb_param; 2263 int rc; 2264 2265 switch (eswitch) { 2266 case QED_OV_ESWITCH_NONE: 2267 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 2268 break; 2269 case QED_OV_ESWITCH_VEB: 2270 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 2271 break; 2272 case QED_OV_ESWITCH_VEPA: 2273 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 2274 break; 2275 default: 2276 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 2277 return -EINVAL; 2278 } 2279 2280 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 2281 drv_mb_param, &resp, ¶m); 2282 if (rc) 2283 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 2284 2285 return rc; 2286 } 2287 2288 int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 2289 struct qed_ptt *p_ptt, enum qed_led_mode mode) 2290 { 2291 u32 resp = 0, param = 0, drv_mb_param; 2292 int rc; 2293 2294 switch (mode) { 2295 case QED_LED_MODE_ON: 2296 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 2297 break; 2298 case QED_LED_MODE_OFF: 2299 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 2300 break; 2301 case QED_LED_MODE_RESTORE: 2302 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 2303 break; 2304 default: 2305 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 2306 return -EINVAL; 2307 } 2308 2309 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 2310 drv_mb_param, &resp, ¶m); 2311 2312 return rc; 2313 } 2314 2315 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 2316 struct qed_ptt *p_ptt, u32 mask_parities) 2317 { 2318 u32 resp = 0, param = 0; 2319 int rc; 2320 2321 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 2322 mask_parities, &resp, ¶m); 2323 2324 if (rc) { 2325 DP_ERR(p_hwfn, 2326 "MCP response failure for mask parities, aborting\n"); 2327 } else if (resp != FW_MSG_CODE_OK) { 2328 DP_ERR(p_hwfn, 2329 "MCP did not acknowledge mask parity request. Old MFW?\n"); 2330 rc = -EINVAL; 2331 } 2332 2333 return rc; 2334 } 2335 2336 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 2337 { 2338 u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 2339 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2340 u32 resp = 0, resp_param = 0; 2341 struct qed_ptt *p_ptt; 2342 int rc = 0; 2343 2344 p_ptt = qed_ptt_acquire(p_hwfn); 2345 if (!p_ptt) 2346 return -EBUSY; 2347 2348 while (bytes_left > 0) { 2349 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 2350 2351 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2352 DRV_MSG_CODE_NVM_READ_NVRAM, 2353 addr + offset + 2354 (bytes_to_copy << 2355 DRV_MB_PARAM_NVM_LEN_OFFSET), 2356 &resp, &resp_param, 2357 &read_len, 2358 (u32 *)(p_buf + offset)); 2359 2360 if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 2361 DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 2362 break; 2363 } 2364 2365 /* This can be a lengthy process, and it's possible scheduler 2366 * isn't preemptable. Sleep a bit to prevent CPU hogging. 2367 */ 2368 if (bytes_left % 0x1000 < 2369 (bytes_left - read_len) % 0x1000) 2370 usleep_range(1000, 2000); 2371 2372 offset += read_len; 2373 bytes_left -= read_len; 2374 } 2375 2376 cdev->mcp_nvm_resp = resp; 2377 qed_ptt_release(p_hwfn, p_ptt); 2378 2379 return rc; 2380 } 2381 2382 int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 2383 { 2384 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2385 struct qed_ptt *p_ptt; 2386 2387 p_ptt = qed_ptt_acquire(p_hwfn); 2388 if (!p_ptt) 2389 return -EBUSY; 2390 2391 memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 2392 qed_ptt_release(p_hwfn, p_ptt); 2393 2394 return 0; 2395 } 2396 2397 int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr) 2398 { 2399 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2400 struct qed_ptt *p_ptt; 2401 u32 resp, param; 2402 int rc; 2403 2404 p_ptt = qed_ptt_acquire(p_hwfn); 2405 if (!p_ptt) 2406 return -EBUSY; 2407 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr, 2408 &resp, ¶m); 2409 cdev->mcp_nvm_resp = resp; 2410 qed_ptt_release(p_hwfn, p_ptt); 2411 2412 return rc; 2413 } 2414 2415 int qed_mcp_nvm_write(struct qed_dev *cdev, 2416 u32 cmd, u32 addr, u8 *p_buf, u32 len) 2417 { 2418 u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 2419 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2420 struct qed_ptt *p_ptt; 2421 int rc = -EINVAL; 2422 2423 p_ptt = qed_ptt_acquire(p_hwfn); 2424 if (!p_ptt) 2425 return -EBUSY; 2426 2427 switch (cmd) { 2428 case QED_PUT_FILE_DATA: 2429 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 2430 break; 2431 case QED_NVM_WRITE_NVRAM: 2432 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 2433 break; 2434 default: 2435 DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 2436 rc = -EINVAL; 2437 goto out; 2438 } 2439 2440 while (buf_idx < len) { 2441 buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 2442 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) | 2443 addr) + buf_idx; 2444 rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 2445 &resp, ¶m, buf_size, 2446 (u32 *)&p_buf[buf_idx]); 2447 if (rc) { 2448 DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 2449 resp = FW_MSG_CODE_ERROR; 2450 break; 2451 } 2452 2453 if (resp != FW_MSG_CODE_OK && 2454 resp != FW_MSG_CODE_NVM_OK && 2455 resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 2456 DP_NOTICE(cdev, 2457 "nvm write failed, resp = 0x%08x\n", resp); 2458 rc = -EINVAL; 2459 break; 2460 } 2461 2462 /* This can be a lengthy process, and it's possible scheduler 2463 * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 2464 */ 2465 if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 2466 usleep_range(1000, 2000); 2467 2468 buf_idx += buf_size; 2469 } 2470 2471 cdev->mcp_nvm_resp = resp; 2472 out: 2473 qed_ptt_release(p_hwfn, p_ptt); 2474 2475 return rc; 2476 } 2477 2478 int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2479 u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 2480 { 2481 u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 2482 u32 resp, param; 2483 int rc; 2484 2485 nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 2486 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 2487 nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 2488 DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 2489 2490 addr = offset; 2491 offset = 0; 2492 bytes_left = len; 2493 while (bytes_left > 0) { 2494 bytes_to_copy = min_t(u32, bytes_left, 2495 MAX_I2C_TRANSACTION_SIZE); 2496 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 2497 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 2498 nvm_offset |= ((addr + offset) << 2499 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 2500 DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 2501 nvm_offset |= (bytes_to_copy << 2502 DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 2503 DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 2504 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2505 DRV_MSG_CODE_TRANSCEIVER_READ, 2506 nvm_offset, &resp, ¶m, &buf_size, 2507 (u32 *)(p_buf + offset)); 2508 if (rc) { 2509 DP_NOTICE(p_hwfn, 2510 "Failed to send a transceiver read command to the MFW. rc = %d.\n", 2511 rc); 2512 return rc; 2513 } 2514 2515 if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 2516 return -ENODEV; 2517 else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 2518 return -EINVAL; 2519 2520 offset += buf_size; 2521 bytes_left -= buf_size; 2522 } 2523 2524 return 0; 2525 } 2526 2527 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2528 { 2529 u32 drv_mb_param = 0, rsp, param; 2530 int rc = 0; 2531 2532 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 2533 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2534 2535 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2536 drv_mb_param, &rsp, ¶m); 2537 2538 if (rc) 2539 return rc; 2540 2541 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2542 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 2543 rc = -EAGAIN; 2544 2545 return rc; 2546 } 2547 2548 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2549 { 2550 u32 drv_mb_param, rsp, param; 2551 int rc = 0; 2552 2553 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 2554 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2555 2556 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2557 drv_mb_param, &rsp, ¶m); 2558 2559 if (rc) 2560 return rc; 2561 2562 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2563 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 2564 rc = -EAGAIN; 2565 2566 return rc; 2567 } 2568 2569 int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 2570 struct qed_ptt *p_ptt, 2571 u32 *num_images) 2572 { 2573 u32 drv_mb_param = 0, rsp; 2574 int rc = 0; 2575 2576 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 2577 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2578 2579 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2580 drv_mb_param, &rsp, num_images); 2581 if (rc) 2582 return rc; 2583 2584 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 2585 rc = -EINVAL; 2586 2587 return rc; 2588 } 2589 2590 int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 2591 struct qed_ptt *p_ptt, 2592 struct bist_nvm_image_att *p_image_att, 2593 u32 image_index) 2594 { 2595 u32 buf_size = 0, param, resp = 0, resp_param = 0; 2596 int rc; 2597 2598 param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 2599 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 2600 param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 2601 2602 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2603 DRV_MSG_CODE_BIST_TEST, param, 2604 &resp, &resp_param, 2605 &buf_size, 2606 (u32 *)p_image_att); 2607 if (rc) 2608 return rc; 2609 2610 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2611 (p_image_att->return_code != 1)) 2612 rc = -EINVAL; 2613 2614 return rc; 2615 } 2616 2617 int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 2618 { 2619 struct qed_nvm_image_info nvm_info; 2620 struct qed_ptt *p_ptt; 2621 int rc; 2622 u32 i; 2623 2624 if (p_hwfn->nvm_info.valid) 2625 return 0; 2626 2627 p_ptt = qed_ptt_acquire(p_hwfn); 2628 if (!p_ptt) { 2629 DP_ERR(p_hwfn, "failed to acquire ptt\n"); 2630 return -EBUSY; 2631 } 2632 2633 /* Acquire from MFW the amount of available images */ 2634 nvm_info.num_images = 0; 2635 rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 2636 p_ptt, &nvm_info.num_images); 2637 if (rc == -EOPNOTSUPP) { 2638 DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 2639 goto out; 2640 } else if (rc || !nvm_info.num_images) { 2641 DP_ERR(p_hwfn, "Failed getting number of images\n"); 2642 goto err0; 2643 } 2644 2645 nvm_info.image_att = kmalloc_array(nvm_info.num_images, 2646 sizeof(struct bist_nvm_image_att), 2647 GFP_KERNEL); 2648 if (!nvm_info.image_att) { 2649 rc = -ENOMEM; 2650 goto err0; 2651 } 2652 2653 /* Iterate over images and get their attributes */ 2654 for (i = 0; i < nvm_info.num_images; i++) { 2655 rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 2656 &nvm_info.image_att[i], i); 2657 if (rc) { 2658 DP_ERR(p_hwfn, 2659 "Failed getting image index %d attributes\n", i); 2660 goto err1; 2661 } 2662 2663 DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 2664 nvm_info.image_att[i].len); 2665 } 2666 out: 2667 /* Update hwfn's nvm_info */ 2668 if (nvm_info.num_images) { 2669 p_hwfn->nvm_info.num_images = nvm_info.num_images; 2670 kfree(p_hwfn->nvm_info.image_att); 2671 p_hwfn->nvm_info.image_att = nvm_info.image_att; 2672 p_hwfn->nvm_info.valid = true; 2673 } 2674 2675 qed_ptt_release(p_hwfn, p_ptt); 2676 return 0; 2677 2678 err1: 2679 kfree(nvm_info.image_att); 2680 err0: 2681 qed_ptt_release(p_hwfn, p_ptt); 2682 return rc; 2683 } 2684 2685 int 2686 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 2687 enum qed_nvm_images image_id, 2688 struct qed_nvm_image_att *p_image_att) 2689 { 2690 enum nvm_image_type type; 2691 u32 i; 2692 2693 /* Translate image_id into MFW definitions */ 2694 switch (image_id) { 2695 case QED_NVM_IMAGE_ISCSI_CFG: 2696 type = NVM_TYPE_ISCSI_CFG; 2697 break; 2698 case QED_NVM_IMAGE_FCOE_CFG: 2699 type = NVM_TYPE_FCOE_CFG; 2700 break; 2701 case QED_NVM_IMAGE_NVM_CFG1: 2702 type = NVM_TYPE_NVM_CFG1; 2703 break; 2704 case QED_NVM_IMAGE_DEFAULT_CFG: 2705 type = NVM_TYPE_DEFAULT_CFG; 2706 break; 2707 case QED_NVM_IMAGE_NVM_META: 2708 type = NVM_TYPE_META; 2709 break; 2710 default: 2711 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 2712 image_id); 2713 return -EINVAL; 2714 } 2715 2716 qed_mcp_nvm_info_populate(p_hwfn); 2717 for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 2718 if (type == p_hwfn->nvm_info.image_att[i].image_type) 2719 break; 2720 if (i == p_hwfn->nvm_info.num_images) { 2721 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 2722 "Failed to find nvram image of type %08x\n", 2723 image_id); 2724 return -ENOENT; 2725 } 2726 2727 p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 2728 p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 2729 2730 return 0; 2731 } 2732 2733 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 2734 enum qed_nvm_images image_id, 2735 u8 *p_buffer, u32 buffer_len) 2736 { 2737 struct qed_nvm_image_att image_att; 2738 int rc; 2739 2740 memset(p_buffer, 0, buffer_len); 2741 2742 rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 2743 if (rc) 2744 return rc; 2745 2746 /* Validate sizes - both the image's and the supplied buffer's */ 2747 if (image_att.length <= 4) { 2748 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 2749 "Image [%d] is too small - only %d bytes\n", 2750 image_id, image_att.length); 2751 return -EINVAL; 2752 } 2753 2754 if (image_att.length > buffer_len) { 2755 DP_VERBOSE(p_hwfn, 2756 QED_MSG_STORAGE, 2757 "Image [%d] is too big - %08x bytes where only %08x are available\n", 2758 image_id, image_att.length, buffer_len); 2759 return -ENOMEM; 2760 } 2761 2762 return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 2763 p_buffer, image_att.length); 2764 } 2765 2766 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 2767 { 2768 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 2769 2770 switch (res_id) { 2771 case QED_SB: 2772 mfw_res_id = RESOURCE_NUM_SB_E; 2773 break; 2774 case QED_L2_QUEUE: 2775 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 2776 break; 2777 case QED_VPORT: 2778 mfw_res_id = RESOURCE_NUM_VPORT_E; 2779 break; 2780 case QED_RSS_ENG: 2781 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 2782 break; 2783 case QED_PQ: 2784 mfw_res_id = RESOURCE_NUM_PQ_E; 2785 break; 2786 case QED_RL: 2787 mfw_res_id = RESOURCE_NUM_RL_E; 2788 break; 2789 case QED_MAC: 2790 case QED_VLAN: 2791 /* Each VFC resource can accommodate both a MAC and a VLAN */ 2792 mfw_res_id = RESOURCE_VFC_FILTER_E; 2793 break; 2794 case QED_ILT: 2795 mfw_res_id = RESOURCE_ILT_E; 2796 break; 2797 case QED_LL2_QUEUE: 2798 mfw_res_id = RESOURCE_LL2_QUEUE_E; 2799 break; 2800 case QED_RDMA_CNQ_RAM: 2801 case QED_CMDQS_CQS: 2802 /* CNQ/CMDQS are the same resource */ 2803 mfw_res_id = RESOURCE_CQS_E; 2804 break; 2805 case QED_RDMA_STATS_QUEUE: 2806 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 2807 break; 2808 case QED_BDQ: 2809 mfw_res_id = RESOURCE_BDQ_E; 2810 break; 2811 default: 2812 break; 2813 } 2814 2815 return mfw_res_id; 2816 } 2817 2818 #define QED_RESC_ALLOC_VERSION_MAJOR 2 2819 #define QED_RESC_ALLOC_VERSION_MINOR 0 2820 #define QED_RESC_ALLOC_VERSION \ 2821 ((QED_RESC_ALLOC_VERSION_MAJOR << \ 2822 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 2823 (QED_RESC_ALLOC_VERSION_MINOR << \ 2824 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 2825 2826 struct qed_resc_alloc_in_params { 2827 u32 cmd; 2828 enum qed_resources res_id; 2829 u32 resc_max_val; 2830 }; 2831 2832 struct qed_resc_alloc_out_params { 2833 u32 mcp_resp; 2834 u32 mcp_param; 2835 u32 resc_num; 2836 u32 resc_start; 2837 u32 vf_resc_num; 2838 u32 vf_resc_start; 2839 u32 flags; 2840 }; 2841 2842 static int 2843 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 2844 struct qed_ptt *p_ptt, 2845 struct qed_resc_alloc_in_params *p_in_params, 2846 struct qed_resc_alloc_out_params *p_out_params) 2847 { 2848 struct qed_mcp_mb_params mb_params; 2849 struct resource_info mfw_resc_info; 2850 int rc; 2851 2852 memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 2853 2854 mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 2855 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 2856 DP_ERR(p_hwfn, 2857 "Failed to match resource %d [%s] with the MFW resources\n", 2858 p_in_params->res_id, 2859 qed_hw_get_resc_name(p_in_params->res_id)); 2860 return -EINVAL; 2861 } 2862 2863 switch (p_in_params->cmd) { 2864 case DRV_MSG_SET_RESOURCE_VALUE_MSG: 2865 mfw_resc_info.size = p_in_params->resc_max_val; 2866 /* Fallthrough */ 2867 case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 2868 break; 2869 default: 2870 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 2871 p_in_params->cmd); 2872 return -EINVAL; 2873 } 2874 2875 memset(&mb_params, 0, sizeof(mb_params)); 2876 mb_params.cmd = p_in_params->cmd; 2877 mb_params.param = QED_RESC_ALLOC_VERSION; 2878 mb_params.p_data_src = &mfw_resc_info; 2879 mb_params.data_src_size = sizeof(mfw_resc_info); 2880 mb_params.p_data_dst = mb_params.p_data_src; 2881 mb_params.data_dst_size = mb_params.data_src_size; 2882 2883 DP_VERBOSE(p_hwfn, 2884 QED_MSG_SP, 2885 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 2886 p_in_params->cmd, 2887 p_in_params->res_id, 2888 qed_hw_get_resc_name(p_in_params->res_id), 2889 QED_MFW_GET_FIELD(mb_params.param, 2890 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 2891 QED_MFW_GET_FIELD(mb_params.param, 2892 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 2893 p_in_params->resc_max_val); 2894 2895 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 2896 if (rc) 2897 return rc; 2898 2899 p_out_params->mcp_resp = mb_params.mcp_resp; 2900 p_out_params->mcp_param = mb_params.mcp_param; 2901 p_out_params->resc_num = mfw_resc_info.size; 2902 p_out_params->resc_start = mfw_resc_info.offset; 2903 p_out_params->vf_resc_num = mfw_resc_info.vf_size; 2904 p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 2905 p_out_params->flags = mfw_resc_info.flags; 2906 2907 DP_VERBOSE(p_hwfn, 2908 QED_MSG_SP, 2909 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 2910 QED_MFW_GET_FIELD(p_out_params->mcp_param, 2911 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 2912 QED_MFW_GET_FIELD(p_out_params->mcp_param, 2913 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 2914 p_out_params->resc_num, 2915 p_out_params->resc_start, 2916 p_out_params->vf_resc_num, 2917 p_out_params->vf_resc_start, p_out_params->flags); 2918 2919 return 0; 2920 } 2921 2922 int 2923 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 2924 struct qed_ptt *p_ptt, 2925 enum qed_resources res_id, 2926 u32 resc_max_val, u32 *p_mcp_resp) 2927 { 2928 struct qed_resc_alloc_out_params out_params; 2929 struct qed_resc_alloc_in_params in_params; 2930 int rc; 2931 2932 memset(&in_params, 0, sizeof(in_params)); 2933 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 2934 in_params.res_id = res_id; 2935 in_params.resc_max_val = resc_max_val; 2936 memset(&out_params, 0, sizeof(out_params)); 2937 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 2938 &out_params); 2939 if (rc) 2940 return rc; 2941 2942 *p_mcp_resp = out_params.mcp_resp; 2943 2944 return 0; 2945 } 2946 2947 int 2948 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 2949 struct qed_ptt *p_ptt, 2950 enum qed_resources res_id, 2951 u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 2952 { 2953 struct qed_resc_alloc_out_params out_params; 2954 struct qed_resc_alloc_in_params in_params; 2955 int rc; 2956 2957 memset(&in_params, 0, sizeof(in_params)); 2958 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 2959 in_params.res_id = res_id; 2960 memset(&out_params, 0, sizeof(out_params)); 2961 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 2962 &out_params); 2963 if (rc) 2964 return rc; 2965 2966 *p_mcp_resp = out_params.mcp_resp; 2967 2968 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 2969 *p_resc_num = out_params.resc_num; 2970 *p_resc_start = out_params.resc_start; 2971 } 2972 2973 return 0; 2974 } 2975 2976 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2977 { 2978 u32 mcp_resp, mcp_param; 2979 2980 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 2981 &mcp_resp, &mcp_param); 2982 } 2983 2984 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 2985 struct qed_ptt *p_ptt, 2986 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 2987 { 2988 int rc; 2989 2990 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 2991 p_mcp_resp, p_mcp_param); 2992 if (rc) 2993 return rc; 2994 2995 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 2996 DP_INFO(p_hwfn, 2997 "The resource command is unsupported by the MFW\n"); 2998 return -EINVAL; 2999 } 3000 3001 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 3002 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 3003 3004 DP_NOTICE(p_hwfn, 3005 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 3006 param, opcode); 3007 return -EINVAL; 3008 } 3009 3010 return rc; 3011 } 3012 3013 static int 3014 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 3015 struct qed_ptt *p_ptt, 3016 struct qed_resc_lock_params *p_params) 3017 { 3018 u32 param = 0, mcp_resp, mcp_param; 3019 u8 opcode; 3020 int rc; 3021 3022 switch (p_params->timeout) { 3023 case QED_MCP_RESC_LOCK_TO_DEFAULT: 3024 opcode = RESOURCE_OPCODE_REQ; 3025 p_params->timeout = 0; 3026 break; 3027 case QED_MCP_RESC_LOCK_TO_NONE: 3028 opcode = RESOURCE_OPCODE_REQ_WO_AGING; 3029 p_params->timeout = 0; 3030 break; 3031 default: 3032 opcode = RESOURCE_OPCODE_REQ_W_AGING; 3033 break; 3034 } 3035 3036 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 3037 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 3038 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 3039 3040 DP_VERBOSE(p_hwfn, 3041 QED_MSG_SP, 3042 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 3043 param, p_params->timeout, opcode, p_params->resource); 3044 3045 /* Attempt to acquire the resource */ 3046 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 3047 if (rc) 3048 return rc; 3049 3050 /* Analyze the response */ 3051 p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 3052 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 3053 3054 DP_VERBOSE(p_hwfn, 3055 QED_MSG_SP, 3056 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 3057 mcp_param, opcode, p_params->owner); 3058 3059 switch (opcode) { 3060 case RESOURCE_OPCODE_GNT: 3061 p_params->b_granted = true; 3062 break; 3063 case RESOURCE_OPCODE_BUSY: 3064 p_params->b_granted = false; 3065 break; 3066 default: 3067 DP_NOTICE(p_hwfn, 3068 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 3069 mcp_param, opcode); 3070 return -EINVAL; 3071 } 3072 3073 return 0; 3074 } 3075 3076 int 3077 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 3078 struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 3079 { 3080 u32 retry_cnt = 0; 3081 int rc; 3082 3083 do { 3084 /* No need for an interval before the first iteration */ 3085 if (retry_cnt) { 3086 if (p_params->sleep_b4_retry) { 3087 u16 retry_interval_in_ms = 3088 DIV_ROUND_UP(p_params->retry_interval, 3089 1000); 3090 3091 msleep(retry_interval_in_ms); 3092 } else { 3093 udelay(p_params->retry_interval); 3094 } 3095 } 3096 3097 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 3098 if (rc) 3099 return rc; 3100 3101 if (p_params->b_granted) 3102 break; 3103 } while (retry_cnt++ < p_params->retry_num); 3104 3105 return 0; 3106 } 3107 3108 int 3109 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 3110 struct qed_ptt *p_ptt, 3111 struct qed_resc_unlock_params *p_params) 3112 { 3113 u32 param = 0, mcp_resp, mcp_param; 3114 u8 opcode; 3115 int rc; 3116 3117 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 3118 : RESOURCE_OPCODE_RELEASE; 3119 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 3120 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 3121 3122 DP_VERBOSE(p_hwfn, QED_MSG_SP, 3123 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 3124 param, opcode, p_params->resource); 3125 3126 /* Attempt to release the resource */ 3127 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 3128 if (rc) 3129 return rc; 3130 3131 /* Analyze the response */ 3132 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 3133 3134 DP_VERBOSE(p_hwfn, QED_MSG_SP, 3135 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 3136 mcp_param, opcode); 3137 3138 switch (opcode) { 3139 case RESOURCE_OPCODE_RELEASED_PREVIOUS: 3140 DP_INFO(p_hwfn, 3141 "Resource unlock request for an already released resource [%d]\n", 3142 p_params->resource); 3143 /* Fallthrough */ 3144 case RESOURCE_OPCODE_RELEASED: 3145 p_params->b_released = true; 3146 break; 3147 case RESOURCE_OPCODE_WRONG_OWNER: 3148 p_params->b_released = false; 3149 break; 3150 default: 3151 DP_NOTICE(p_hwfn, 3152 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 3153 mcp_param, opcode); 3154 return -EINVAL; 3155 } 3156 3157 return 0; 3158 } 3159 3160 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3161 struct qed_resc_unlock_params *p_unlock, 3162 enum qed_resc_lock 3163 resource, bool b_is_permanent) 3164 { 3165 if (p_lock) { 3166 memset(p_lock, 0, sizeof(*p_lock)); 3167 3168 /* Permanent resources don't require aging, and there's no 3169 * point in trying to acquire them more than once since it's 3170 * unexpected another entity would release them. 3171 */ 3172 if (b_is_permanent) { 3173 p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3174 } else { 3175 p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3176 p_lock->retry_interval = 3177 QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3178 p_lock->sleep_b4_retry = true; 3179 } 3180 3181 p_lock->resource = resource; 3182 } 3183 3184 if (p_unlock) { 3185 memset(p_unlock, 0, sizeof(*p_unlock)); 3186 p_unlock->resource = resource; 3187 } 3188 } 3189 3190 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3191 { 3192 u32 mcp_resp; 3193 int rc; 3194 3195 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3196 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3197 if (!rc) 3198 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3199 "MFW supported features: %08x\n", 3200 p_hwfn->mcp_info->capabilities); 3201 3202 return rc; 3203 } 3204 3205 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3206 { 3207 u32 mcp_resp, mcp_param, features; 3208 3209 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE; 3210 3211 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3212 features, &mcp_resp, &mcp_param); 3213 } 3214