1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/types.h> 10 #include <asm/byteorder.h> 11 #include <linux/delay.h> 12 #include <linux/errno.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/spinlock.h> 16 #include <linux/string.h> 17 #include "qed.h" 18 #include "qed_dcbx.h" 19 #include "qed_hsi.h" 20 #include "qed_hw.h" 21 #include "qed_mcp.h" 22 #include "qed_reg_addr.h" 23 #include "qed_sriov.h" 24 25 #define CHIP_MCP_RESP_ITER_US 10 26 27 #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 28 #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 29 30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 31 qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 32 _val) 33 34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 35 qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 36 37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 38 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 39 offsetof(struct public_drv_mb, _field), _val) 40 41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 42 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 43 offsetof(struct public_drv_mb, _field)) 44 45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 46 DRV_ID_PDA_COMP_VER_SHIFT) 47 48 #define MCP_BYTES_PER_MBIT_SHIFT 17 49 50 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 51 { 52 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 53 return false; 54 return true; 55 } 56 57 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, 58 struct qed_ptt *p_ptt) 59 { 60 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 61 PUBLIC_PORT); 62 u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 63 64 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 65 MFW_PORT(p_hwfn)); 66 DP_VERBOSE(p_hwfn, QED_MSG_SP, 67 "port_addr = 0x%x, port_id 0x%02x\n", 68 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 69 } 70 71 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, 72 struct qed_ptt *p_ptt) 73 { 74 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 75 u32 tmp, i; 76 77 if (!p_hwfn->mcp_info->public_base) 78 return; 79 80 for (i = 0; i < length; i++) { 81 tmp = qed_rd(p_hwfn, p_ptt, 82 p_hwfn->mcp_info->mfw_mb_addr + 83 (i << 2) + sizeof(u32)); 84 85 /* The MB data is actually BE; Need to force it to cpu */ 86 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 87 be32_to_cpu((__force __be32)tmp); 88 } 89 } 90 91 int qed_mcp_free(struct qed_hwfn *p_hwfn) 92 { 93 if (p_hwfn->mcp_info) { 94 kfree(p_hwfn->mcp_info->mfw_mb_cur); 95 kfree(p_hwfn->mcp_info->mfw_mb_shadow); 96 } 97 kfree(p_hwfn->mcp_info); 98 99 return 0; 100 } 101 102 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, 103 struct qed_ptt *p_ptt) 104 { 105 struct qed_mcp_info *p_info = p_hwfn->mcp_info; 106 u32 drv_mb_offsize, mfw_mb_offsize; 107 u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 108 109 p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 110 if (!p_info->public_base) 111 return 0; 112 113 p_info->public_base |= GRCBASE_MCP; 114 115 /* Calculate the driver and MFW mailbox address */ 116 drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 117 SECTION_OFFSIZE_ADDR(p_info->public_base, 118 PUBLIC_DRV_MB)); 119 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 120 DP_VERBOSE(p_hwfn, QED_MSG_SP, 121 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 122 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 123 124 /* Set the MFW MB address */ 125 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 126 SECTION_OFFSIZE_ADDR(p_info->public_base, 127 PUBLIC_MFW_MB)); 128 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 129 p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr); 130 131 /* Get the current driver mailbox sequence before sending 132 * the first command 133 */ 134 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 135 DRV_MSG_SEQ_NUMBER_MASK; 136 137 /* Get current FW pulse sequence */ 138 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 139 DRV_PULSE_SEQ_MASK; 140 141 p_info->mcp_hist = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 142 143 return 0; 144 } 145 146 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, 147 struct qed_ptt *p_ptt) 148 { 149 struct qed_mcp_info *p_info; 150 u32 size; 151 152 /* Allocate mcp_info structure */ 153 p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 154 if (!p_hwfn->mcp_info) 155 goto err; 156 p_info = p_hwfn->mcp_info; 157 158 if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 159 DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 160 /* Do not free mcp_info here, since public_base indicate that 161 * the MCP is not initialized 162 */ 163 return 0; 164 } 165 166 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 167 p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 168 p_info->mfw_mb_shadow = 169 kzalloc(sizeof(u32) * MFW_DRV_MSG_MAX_DWORDS( 170 p_info->mfw_mb_length), GFP_KERNEL); 171 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr) 172 goto err; 173 174 /* Initialize the MFW spinlock */ 175 spin_lock_init(&p_info->lock); 176 177 return 0; 178 179 err: 180 DP_NOTICE(p_hwfn, "Failed to allocate mcp memory\n"); 181 qed_mcp_free(p_hwfn); 182 return -ENOMEM; 183 } 184 185 /* Locks the MFW mailbox of a PF to ensure a single access. 186 * The lock is achieved in most cases by holding a spinlock, causing other 187 * threads to wait till a previous access is done. 188 * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single 189 * access is achieved by setting a blocking flag, which will fail other 190 * competing contexts to send their mailboxes. 191 */ 192 static int qed_mcp_mb_lock(struct qed_hwfn *p_hwfn, 193 u32 cmd) 194 { 195 spin_lock_bh(&p_hwfn->mcp_info->lock); 196 197 /* The spinlock shouldn't be acquired when the mailbox command is 198 * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel 199 * pending [UN]LOAD_REQ command of another PF together with a spinlock 200 * (i.e. interrupts are disabled) - can lead to a deadlock. 201 * It is assumed that for a single PF, no other mailbox commands can be 202 * sent from another context while sending LOAD_REQ, and that any 203 * parallel commands to UNLOAD_REQ can be cancelled. 204 */ 205 if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE) 206 p_hwfn->mcp_info->block_mb_sending = false; 207 208 if (p_hwfn->mcp_info->block_mb_sending) { 209 DP_NOTICE(p_hwfn, 210 "Trying to send a MFW mailbox command [0x%x] in parallel to [UN]LOAD_REQ. Aborting.\n", 211 cmd); 212 spin_unlock_bh(&p_hwfn->mcp_info->lock); 213 return -EBUSY; 214 } 215 216 if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) { 217 p_hwfn->mcp_info->block_mb_sending = true; 218 spin_unlock_bh(&p_hwfn->mcp_info->lock); 219 } 220 221 return 0; 222 } 223 224 static void qed_mcp_mb_unlock(struct qed_hwfn *p_hwfn, 225 u32 cmd) 226 { 227 if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ) 228 spin_unlock_bh(&p_hwfn->mcp_info->lock); 229 } 230 231 int qed_mcp_reset(struct qed_hwfn *p_hwfn, 232 struct qed_ptt *p_ptt) 233 { 234 u32 seq = ++p_hwfn->mcp_info->drv_mb_seq; 235 u8 delay = CHIP_MCP_RESP_ITER_US; 236 u32 org_mcp_reset_seq, cnt = 0; 237 int rc = 0; 238 239 /* Ensure that only a single thread is accessing the mailbox at a 240 * certain time. 241 */ 242 rc = qed_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET); 243 if (rc != 0) 244 return rc; 245 246 /* Set drv command along with the updated sequence */ 247 org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 248 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, 249 (DRV_MSG_CODE_MCP_RESET | seq)); 250 251 do { 252 /* Wait for MFW response */ 253 udelay(delay); 254 /* Give the FW up to 500 second (50*1000*10usec) */ 255 } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 256 MISCS_REG_GENERIC_POR_0)) && 257 (cnt++ < QED_MCP_RESET_RETRIES)); 258 259 if (org_mcp_reset_seq != 260 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 261 DP_VERBOSE(p_hwfn, QED_MSG_SP, 262 "MCP was reset after %d usec\n", cnt * delay); 263 } else { 264 DP_ERR(p_hwfn, "Failed to reset MCP\n"); 265 rc = -EAGAIN; 266 } 267 268 qed_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET); 269 270 return rc; 271 } 272 273 static int qed_do_mcp_cmd(struct qed_hwfn *p_hwfn, 274 struct qed_ptt *p_ptt, 275 u32 cmd, 276 u32 param, 277 u32 *o_mcp_resp, 278 u32 *o_mcp_param) 279 { 280 u8 delay = CHIP_MCP_RESP_ITER_US; 281 u32 seq, cnt = 1, actual_mb_seq; 282 int rc = 0; 283 284 /* Get actual driver mailbox sequence */ 285 actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 286 DRV_MSG_SEQ_NUMBER_MASK; 287 288 /* Use MCP history register to check if MCP reset occurred between 289 * init time and now. 290 */ 291 if (p_hwfn->mcp_info->mcp_hist != 292 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 293 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Rereading MCP offsets\n"); 294 qed_load_mcp_offsets(p_hwfn, p_ptt); 295 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 296 } 297 seq = ++p_hwfn->mcp_info->drv_mb_seq; 298 299 /* Set drv param */ 300 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param); 301 302 /* Set drv command along with the updated sequence */ 303 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq)); 304 305 DP_VERBOSE(p_hwfn, QED_MSG_SP, 306 "wrote command (%x) to MFW MB param 0x%08x\n", 307 (cmd | seq), param); 308 309 do { 310 /* Wait for MFW response */ 311 udelay(delay); 312 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 313 314 /* Give the FW up to 5 second (500*10ms) */ 315 } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) && 316 (cnt++ < QED_DRV_MB_MAX_RETRIES)); 317 318 DP_VERBOSE(p_hwfn, QED_MSG_SP, 319 "[after %d ms] read (%x) seq is (%x) from FW MB\n", 320 cnt * delay, *o_mcp_resp, seq); 321 322 /* Is this a reply to our command? */ 323 if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) { 324 *o_mcp_resp &= FW_MSG_CODE_MASK; 325 /* Get the MCP param */ 326 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 327 } else { 328 /* FW BUG! */ 329 DP_ERR(p_hwfn, "MFW failed to respond!\n"); 330 *o_mcp_resp = 0; 331 rc = -EAGAIN; 332 } 333 return rc; 334 } 335 336 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 337 struct qed_ptt *p_ptt, 338 struct qed_mcp_mb_params *p_mb_params) 339 { 340 u32 union_data_addr; 341 int rc; 342 343 /* MCP not initialized */ 344 if (!qed_mcp_is_init(p_hwfn)) { 345 DP_NOTICE(p_hwfn, "MFW is not initialized !\n"); 346 return -EBUSY; 347 } 348 349 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 350 offsetof(struct public_drv_mb, union_data); 351 352 /* Ensure that only a single thread is accessing the mailbox at a 353 * certain time. 354 */ 355 rc = qed_mcp_mb_lock(p_hwfn, p_mb_params->cmd); 356 if (rc) 357 return rc; 358 359 if (p_mb_params->p_data_src != NULL) 360 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, 361 p_mb_params->p_data_src, 362 sizeof(*p_mb_params->p_data_src)); 363 364 rc = qed_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd, 365 p_mb_params->param, &p_mb_params->mcp_resp, 366 &p_mb_params->mcp_param); 367 368 if (p_mb_params->p_data_dst != NULL) 369 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 370 union_data_addr, 371 sizeof(*p_mb_params->p_data_dst)); 372 373 qed_mcp_mb_unlock(p_hwfn, p_mb_params->cmd); 374 375 return rc; 376 } 377 378 int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 379 struct qed_ptt *p_ptt, 380 u32 cmd, 381 u32 param, 382 u32 *o_mcp_resp, 383 u32 *o_mcp_param) 384 { 385 struct qed_mcp_mb_params mb_params; 386 int rc; 387 388 memset(&mb_params, 0, sizeof(mb_params)); 389 mb_params.cmd = cmd; 390 mb_params.param = param; 391 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 392 if (rc) 393 return rc; 394 395 *o_mcp_resp = mb_params.mcp_resp; 396 *o_mcp_param = mb_params.mcp_param; 397 398 return 0; 399 } 400 401 int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 402 struct qed_ptt *p_ptt, 403 u32 *p_load_code) 404 { 405 struct qed_dev *cdev = p_hwfn->cdev; 406 struct qed_mcp_mb_params mb_params; 407 union drv_union_data union_data; 408 int rc; 409 410 memset(&mb_params, 0, sizeof(mb_params)); 411 /* Load Request */ 412 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 413 mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT | 414 cdev->drv_type; 415 memcpy(&union_data.ver_str, cdev->ver_str, MCP_DRV_VER_STR_SIZE); 416 mb_params.p_data_src = &union_data; 417 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 418 419 /* if mcp fails to respond we must abort */ 420 if (rc) { 421 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 422 return rc; 423 } 424 425 *p_load_code = mb_params.mcp_resp; 426 427 /* If MFW refused (e.g. other port is in diagnostic mode) we 428 * must abort. This can happen in the following cases: 429 * - Other port is in diagnostic mode 430 * - Previously loaded function on the engine is not compliant with 431 * the requester. 432 * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION. 433 * - 434 */ 435 if (!(*p_load_code) || 436 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) || 437 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) || 438 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) { 439 DP_ERR(p_hwfn, "MCP refused load request, aborting\n"); 440 return -EBUSY; 441 } 442 443 return 0; 444 } 445 446 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 447 struct qed_ptt *p_ptt) 448 { 449 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 450 PUBLIC_PATH); 451 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 452 u32 path_addr = SECTION_ADDR(mfw_path_offsize, 453 QED_PATH_ID(p_hwfn)); 454 u32 disabled_vfs[VF_MAX_STATIC / 32]; 455 int i; 456 457 DP_VERBOSE(p_hwfn, 458 QED_MSG_SP, 459 "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 460 mfw_path_offsize, path_addr); 461 462 for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 463 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 464 path_addr + 465 offsetof(struct public_path, 466 mcp_vf_disabled) + 467 sizeof(u32) * i); 468 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 469 "FLR-ed VFs [%08x,...,%08x] - %08x\n", 470 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 471 } 472 473 if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 474 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 475 } 476 477 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 478 struct qed_ptt *p_ptt, u32 *vfs_to_ack) 479 { 480 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 481 PUBLIC_FUNC); 482 u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 483 u32 func_addr = SECTION_ADDR(mfw_func_offsize, 484 MCP_PF_ID(p_hwfn)); 485 struct qed_mcp_mb_params mb_params; 486 union drv_union_data union_data; 487 int rc; 488 int i; 489 490 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 491 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 492 "Acking VFs [%08x,...,%08x] - %08x\n", 493 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 494 495 memset(&mb_params, 0, sizeof(mb_params)); 496 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 497 memcpy(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8); 498 mb_params.p_data_src = &union_data; 499 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 500 if (rc) { 501 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 502 return -EBUSY; 503 } 504 505 /* Clear the ACK bits */ 506 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 507 qed_wr(p_hwfn, p_ptt, 508 func_addr + 509 offsetof(struct public_func, drv_ack_vf_disabled) + 510 i * sizeof(u32), 0); 511 512 return rc; 513 } 514 515 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 516 struct qed_ptt *p_ptt) 517 { 518 u32 transceiver_state; 519 520 transceiver_state = qed_rd(p_hwfn, p_ptt, 521 p_hwfn->mcp_info->port_addr + 522 offsetof(struct public_port, 523 transceiver_data)); 524 525 DP_VERBOSE(p_hwfn, 526 (NETIF_MSG_HW | QED_MSG_SP), 527 "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 528 transceiver_state, 529 (u32)(p_hwfn->mcp_info->port_addr + 530 offsetof(struct public_port, 531 transceiver_data))); 532 533 transceiver_state = GET_FIELD(transceiver_state, 534 PMM_TRANSCEIVER_STATE); 535 536 if (transceiver_state == PMM_TRANSCEIVER_STATE_PRESENT) 537 DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 538 else 539 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 540 } 541 542 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 543 struct qed_ptt *p_ptt, 544 bool b_reset) 545 { 546 struct qed_mcp_link_state *p_link; 547 u8 max_bw, min_bw; 548 u32 status = 0; 549 550 p_link = &p_hwfn->mcp_info->link_output; 551 memset(p_link, 0, sizeof(*p_link)); 552 if (!b_reset) { 553 status = qed_rd(p_hwfn, p_ptt, 554 p_hwfn->mcp_info->port_addr + 555 offsetof(struct public_port, link_status)); 556 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 557 "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 558 status, 559 (u32)(p_hwfn->mcp_info->port_addr + 560 offsetof(struct public_port, 561 link_status))); 562 } else { 563 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 564 "Resetting link indications\n"); 565 return; 566 } 567 568 if (p_hwfn->b_drv_link_init) 569 p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 570 else 571 p_link->link_up = false; 572 573 p_link->full_duplex = true; 574 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 575 case LINK_STATUS_SPEED_AND_DUPLEX_100G: 576 p_link->speed = 100000; 577 break; 578 case LINK_STATUS_SPEED_AND_DUPLEX_50G: 579 p_link->speed = 50000; 580 break; 581 case LINK_STATUS_SPEED_AND_DUPLEX_40G: 582 p_link->speed = 40000; 583 break; 584 case LINK_STATUS_SPEED_AND_DUPLEX_25G: 585 p_link->speed = 25000; 586 break; 587 case LINK_STATUS_SPEED_AND_DUPLEX_20G: 588 p_link->speed = 20000; 589 break; 590 case LINK_STATUS_SPEED_AND_DUPLEX_10G: 591 p_link->speed = 10000; 592 break; 593 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 594 p_link->full_duplex = false; 595 /* Fall-through */ 596 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 597 p_link->speed = 1000; 598 break; 599 default: 600 p_link->speed = 0; 601 } 602 603 if (p_link->link_up && p_link->speed) 604 p_link->line_speed = p_link->speed; 605 else 606 p_link->line_speed = 0; 607 608 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 609 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 610 611 /* Max bandwidth configuration */ 612 __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 613 614 /* Min bandwidth configuration */ 615 __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 616 qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_link->min_pf_rate); 617 618 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 619 p_link->an_complete = !!(status & 620 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 621 p_link->parallel_detection = !!(status & 622 LINK_STATUS_PARALLEL_DETECTION_USED); 623 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 624 625 p_link->partner_adv_speed |= 626 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 627 QED_LINK_PARTNER_SPEED_1G_FD : 0; 628 p_link->partner_adv_speed |= 629 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 630 QED_LINK_PARTNER_SPEED_1G_HD : 0; 631 p_link->partner_adv_speed |= 632 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 633 QED_LINK_PARTNER_SPEED_10G : 0; 634 p_link->partner_adv_speed |= 635 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 636 QED_LINK_PARTNER_SPEED_20G : 0; 637 p_link->partner_adv_speed |= 638 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 639 QED_LINK_PARTNER_SPEED_40G : 0; 640 p_link->partner_adv_speed |= 641 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 642 QED_LINK_PARTNER_SPEED_50G : 0; 643 p_link->partner_adv_speed |= 644 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 645 QED_LINK_PARTNER_SPEED_100G : 0; 646 647 p_link->partner_tx_flow_ctrl_en = 648 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 649 p_link->partner_rx_flow_ctrl_en = 650 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 651 652 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 653 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 654 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 655 break; 656 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 657 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 658 break; 659 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 660 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 661 break; 662 default: 663 p_link->partner_adv_pause = 0; 664 } 665 666 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 667 668 qed_link_update(p_hwfn); 669 } 670 671 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, 672 struct qed_ptt *p_ptt, 673 bool b_up) 674 { 675 struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 676 struct qed_mcp_mb_params mb_params; 677 union drv_union_data union_data; 678 struct pmm_phy_cfg *phy_cfg; 679 int rc = 0; 680 u32 cmd; 681 682 /* Set the shmem configuration according to params */ 683 phy_cfg = &union_data.drv_phy_cfg; 684 memset(phy_cfg, 0, sizeof(*phy_cfg)); 685 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 686 if (!params->speed.autoneg) 687 phy_cfg->speed = params->speed.forced_speed; 688 phy_cfg->pause |= (params->pause.autoneg) ? PMM_PAUSE_AUTONEG : 0; 689 phy_cfg->pause |= (params->pause.forced_rx) ? PMM_PAUSE_RX : 0; 690 phy_cfg->pause |= (params->pause.forced_tx) ? PMM_PAUSE_TX : 0; 691 phy_cfg->adv_speed = params->speed.advertised_speeds; 692 phy_cfg->loopback_mode = params->loopback_mode; 693 694 p_hwfn->b_drv_link_init = b_up; 695 696 if (b_up) { 697 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 698 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 699 phy_cfg->speed, 700 phy_cfg->pause, 701 phy_cfg->adv_speed, 702 phy_cfg->loopback_mode, 703 phy_cfg->feature_config_flags); 704 } else { 705 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 706 "Resetting link\n"); 707 } 708 709 memset(&mb_params, 0, sizeof(mb_params)); 710 mb_params.cmd = cmd; 711 mb_params.p_data_src = &union_data; 712 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 713 714 /* if mcp fails to respond we must abort */ 715 if (rc) { 716 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 717 return rc; 718 } 719 720 /* Reset the link status if needed */ 721 if (!b_up) 722 qed_mcp_handle_link_change(p_hwfn, p_ptt, true); 723 724 return 0; 725 } 726 727 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 728 struct public_func *p_shmem_info) 729 { 730 struct qed_mcp_function_info *p_info; 731 732 p_info = &p_hwfn->mcp_info->func_info; 733 734 p_info->bandwidth_min = (p_shmem_info->config & 735 FUNC_MF_CFG_MIN_BW_MASK) >> 736 FUNC_MF_CFG_MIN_BW_SHIFT; 737 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 738 DP_INFO(p_hwfn, 739 "bandwidth minimum out of bounds [%02x]. Set to 1\n", 740 p_info->bandwidth_min); 741 p_info->bandwidth_min = 1; 742 } 743 744 p_info->bandwidth_max = (p_shmem_info->config & 745 FUNC_MF_CFG_MAX_BW_MASK) >> 746 FUNC_MF_CFG_MAX_BW_SHIFT; 747 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 748 DP_INFO(p_hwfn, 749 "bandwidth maximum out of bounds [%02x]. Set to 100\n", 750 p_info->bandwidth_max); 751 p_info->bandwidth_max = 100; 752 } 753 } 754 755 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 756 struct qed_ptt *p_ptt, 757 struct public_func *p_data, 758 int pfid) 759 { 760 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 761 PUBLIC_FUNC); 762 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 763 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 764 u32 i, size; 765 766 memset(p_data, 0, sizeof(*p_data)); 767 768 size = min_t(u32, sizeof(*p_data), 769 QED_SECTION_SIZE(mfw_path_offsize)); 770 for (i = 0; i < size / sizeof(u32); i++) 771 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 772 func_addr + (i << 2)); 773 return size; 774 } 775 776 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, 777 struct qed_ptt *p_ptt) 778 { 779 struct qed_mcp_function_info *p_info; 780 struct public_func shmem_info; 781 u32 resp = 0, param = 0; 782 783 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 784 MCP_PF_ID(p_hwfn)); 785 786 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 787 788 p_info = &p_hwfn->mcp_info->func_info; 789 790 qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 791 qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 792 793 /* Acknowledge the MFW */ 794 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 795 ¶m); 796 } 797 798 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 799 struct qed_ptt *p_ptt) 800 { 801 struct qed_mcp_info *info = p_hwfn->mcp_info; 802 int rc = 0; 803 bool found = false; 804 u16 i; 805 806 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 807 808 /* Read Messages from MFW */ 809 qed_mcp_read_mb(p_hwfn, p_ptt); 810 811 /* Compare current messages to old ones */ 812 for (i = 0; i < info->mfw_mb_length; i++) { 813 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 814 continue; 815 816 found = true; 817 818 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 819 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 820 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 821 822 switch (i) { 823 case MFW_DRV_MSG_LINK_CHANGE: 824 qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 825 break; 826 case MFW_DRV_MSG_VF_DISABLED: 827 qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 828 break; 829 case MFW_DRV_MSG_LLDP_DATA_UPDATED: 830 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 831 QED_DCBX_REMOTE_LLDP_MIB); 832 break; 833 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 834 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 835 QED_DCBX_REMOTE_MIB); 836 break; 837 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 838 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 839 QED_DCBX_OPERATIONAL_MIB); 840 break; 841 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 842 qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 843 break; 844 case MFW_DRV_MSG_BW_UPDATE: 845 qed_mcp_update_bw(p_hwfn, p_ptt); 846 break; 847 default: 848 DP_NOTICE(p_hwfn, "Unimplemented MFW message %d\n", i); 849 rc = -EINVAL; 850 } 851 } 852 853 /* ACK everything */ 854 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 855 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 856 857 /* MFW expect answer in BE, so we force write in that format */ 858 qed_wr(p_hwfn, p_ptt, 859 info->mfw_mb_addr + sizeof(u32) + 860 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 861 sizeof(u32) + i * sizeof(u32), 862 (__force u32)val); 863 } 864 865 if (!found) { 866 DP_NOTICE(p_hwfn, 867 "Received an MFW message indication but no new message!\n"); 868 rc = -EINVAL; 869 } 870 871 /* Copy the new mfw messages into the shadow */ 872 memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 873 874 return rc; 875 } 876 877 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 878 struct qed_ptt *p_ptt, 879 u32 *p_mfw_ver, u32 *p_running_bundle_id) 880 { 881 u32 global_offsize; 882 883 if (IS_VF(p_hwfn->cdev)) { 884 if (p_hwfn->vf_iov_info) { 885 struct pfvf_acquire_resp_tlv *p_resp; 886 887 p_resp = &p_hwfn->vf_iov_info->acquire_resp; 888 *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 889 return 0; 890 } else { 891 DP_VERBOSE(p_hwfn, 892 QED_MSG_IOV, 893 "VF requested MFW version prior to ACQUIRE\n"); 894 return -EINVAL; 895 } 896 } 897 898 global_offsize = qed_rd(p_hwfn, p_ptt, 899 SECTION_OFFSIZE_ADDR(p_hwfn-> 900 mcp_info->public_base, 901 PUBLIC_GLOBAL)); 902 *p_mfw_ver = 903 qed_rd(p_hwfn, p_ptt, 904 SECTION_ADDR(global_offsize, 905 0) + offsetof(struct public_global, mfw_ver)); 906 907 if (p_running_bundle_id != NULL) { 908 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 909 SECTION_ADDR(global_offsize, 0) + 910 offsetof(struct public_global, 911 running_bundle_id)); 912 } 913 914 return 0; 915 } 916 917 int qed_mcp_get_media_type(struct qed_dev *cdev, 918 u32 *p_media_type) 919 { 920 struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 921 struct qed_ptt *p_ptt; 922 923 if (IS_VF(cdev)) 924 return -EINVAL; 925 926 if (!qed_mcp_is_init(p_hwfn)) { 927 DP_NOTICE(p_hwfn, "MFW is not initialized !\n"); 928 return -EBUSY; 929 } 930 931 *p_media_type = MEDIA_UNSPECIFIED; 932 933 p_ptt = qed_ptt_acquire(p_hwfn); 934 if (!p_ptt) 935 return -EBUSY; 936 937 *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 938 offsetof(struct public_port, media_type)); 939 940 qed_ptt_release(p_hwfn, p_ptt); 941 942 return 0; 943 } 944 945 static int 946 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 947 struct public_func *p_info, 948 enum qed_pci_personality *p_proto) 949 { 950 int rc = 0; 951 952 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 953 case FUNC_MF_CFG_PROTOCOL_ETHERNET: 954 *p_proto = QED_PCI_ETH; 955 break; 956 default: 957 rc = -EINVAL; 958 } 959 960 return rc; 961 } 962 963 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 964 struct qed_ptt *p_ptt) 965 { 966 struct qed_mcp_function_info *info; 967 struct public_func shmem_info; 968 969 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 970 MCP_PF_ID(p_hwfn)); 971 info = &p_hwfn->mcp_info->func_info; 972 973 info->pause_on_host = (shmem_info.config & 974 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 975 976 if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, 977 &info->protocol)) { 978 DP_ERR(p_hwfn, "Unknown personality %08x\n", 979 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 980 return -EINVAL; 981 } 982 983 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 984 985 if (shmem_info.mac_upper || shmem_info.mac_lower) { 986 info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 987 info->mac[1] = (u8)(shmem_info.mac_upper); 988 info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 989 info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 990 info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 991 info->mac[5] = (u8)(shmem_info.mac_lower); 992 } else { 993 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 994 } 995 996 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper | 997 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32); 998 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper | 999 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32); 1000 1001 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 1002 1003 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 1004 "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x\n", 1005 info->pause_on_host, info->protocol, 1006 info->bandwidth_min, info->bandwidth_max, 1007 info->mac[0], info->mac[1], info->mac[2], 1008 info->mac[3], info->mac[4], info->mac[5], 1009 info->wwn_port, info->wwn_node, info->ovlan); 1010 1011 return 0; 1012 } 1013 1014 struct qed_mcp_link_params 1015 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 1016 { 1017 if (!p_hwfn || !p_hwfn->mcp_info) 1018 return NULL; 1019 return &p_hwfn->mcp_info->link_input; 1020 } 1021 1022 struct qed_mcp_link_state 1023 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 1024 { 1025 if (!p_hwfn || !p_hwfn->mcp_info) 1026 return NULL; 1027 return &p_hwfn->mcp_info->link_output; 1028 } 1029 1030 struct qed_mcp_link_capabilities 1031 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 1032 { 1033 if (!p_hwfn || !p_hwfn->mcp_info) 1034 return NULL; 1035 return &p_hwfn->mcp_info->link_capabilities; 1036 } 1037 1038 int qed_mcp_drain(struct qed_hwfn *p_hwfn, 1039 struct qed_ptt *p_ptt) 1040 { 1041 u32 resp = 0, param = 0; 1042 int rc; 1043 1044 rc = qed_mcp_cmd(p_hwfn, p_ptt, 1045 DRV_MSG_CODE_NIG_DRAIN, 1000, 1046 &resp, ¶m); 1047 1048 /* Wait for the drain to complete before returning */ 1049 msleep(1020); 1050 1051 return rc; 1052 } 1053 1054 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 1055 struct qed_ptt *p_ptt, 1056 u32 *p_flash_size) 1057 { 1058 u32 flash_size; 1059 1060 if (IS_VF(p_hwfn->cdev)) 1061 return -EINVAL; 1062 1063 flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 1064 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 1065 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 1066 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 1067 1068 *p_flash_size = flash_size; 1069 1070 return 0; 1071 } 1072 1073 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 1074 struct qed_ptt *p_ptt, u8 vf_id, u8 num) 1075 { 1076 u32 resp = 0, param = 0, rc_param = 0; 1077 int rc; 1078 1079 /* Only Leader can configure MSIX, and need to take CMT into account */ 1080 if (!IS_LEAD_HWFN(p_hwfn)) 1081 return 0; 1082 num *= p_hwfn->cdev->num_hwfns; 1083 1084 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 1085 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 1086 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 1087 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 1088 1089 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 1090 &resp, &rc_param); 1091 1092 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 1093 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 1094 rc = -EINVAL; 1095 } else { 1096 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 1097 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 1098 num, vf_id); 1099 } 1100 1101 return rc; 1102 } 1103 1104 int 1105 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 1106 struct qed_ptt *p_ptt, 1107 struct qed_mcp_drv_version *p_ver) 1108 { 1109 struct drv_version_stc *p_drv_version; 1110 struct qed_mcp_mb_params mb_params; 1111 union drv_union_data union_data; 1112 __be32 val; 1113 u32 i; 1114 int rc; 1115 1116 p_drv_version = &union_data.drv_version; 1117 p_drv_version->version = p_ver->version; 1118 1119 for (i = 0; i < MCP_DRV_VER_STR_SIZE - 1; i += 4) { 1120 val = cpu_to_be32(p_ver->name[i]); 1121 *(__be32 *)&p_drv_version->name[i * sizeof(u32)] = val; 1122 } 1123 1124 memset(&mb_params, 0, sizeof(mb_params)); 1125 mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 1126 mb_params.p_data_src = &union_data; 1127 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1128 if (rc) 1129 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1130 1131 return rc; 1132 } 1133 1134 int qed_mcp_set_led(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1135 enum qed_led_mode mode) 1136 { 1137 u32 resp = 0, param = 0, drv_mb_param; 1138 int rc; 1139 1140 switch (mode) { 1141 case QED_LED_MODE_ON: 1142 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 1143 break; 1144 case QED_LED_MODE_OFF: 1145 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 1146 break; 1147 case QED_LED_MODE_RESTORE: 1148 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 1149 break; 1150 default: 1151 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 1152 return -EINVAL; 1153 } 1154 1155 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 1156 drv_mb_param, &resp, ¶m); 1157 1158 return rc; 1159 } 1160 1161 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1162 { 1163 u32 drv_mb_param = 0, rsp, param; 1164 int rc = 0; 1165 1166 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 1167 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 1168 1169 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 1170 drv_mb_param, &rsp, ¶m); 1171 1172 if (rc) 1173 return rc; 1174 1175 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 1176 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 1177 rc = -EAGAIN; 1178 1179 return rc; 1180 } 1181 1182 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1183 { 1184 u32 drv_mb_param, rsp, param; 1185 int rc = 0; 1186 1187 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 1188 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 1189 1190 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 1191 drv_mb_param, &rsp, ¶m); 1192 1193 if (rc) 1194 return rc; 1195 1196 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 1197 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 1198 rc = -EAGAIN; 1199 1200 return rc; 1201 } 1202