1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <asm/byteorder.h> 35 #include <linux/delay.h> 36 #include <linux/errno.h> 37 #include <linux/kernel.h> 38 #include <linux/slab.h> 39 #include <linux/spinlock.h> 40 #include <linux/string.h> 41 #include <linux/etherdevice.h> 42 #include "qed.h" 43 #include "qed_cxt.h" 44 #include "qed_dcbx.h" 45 #include "qed_hsi.h" 46 #include "qed_hw.h" 47 #include "qed_mcp.h" 48 #include "qed_reg_addr.h" 49 #include "qed_sriov.h" 50 51 #define QED_MCP_RESP_ITER_US 10 52 53 #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 54 #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 55 56 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 57 qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 58 _val) 59 60 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 61 qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 62 63 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 64 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 65 offsetof(struct public_drv_mb, _field), _val) 66 67 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 68 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 69 offsetof(struct public_drv_mb, _field)) 70 71 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 72 DRV_ID_PDA_COMP_VER_SHIFT) 73 74 #define MCP_BYTES_PER_MBIT_SHIFT 17 75 76 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 77 { 78 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 79 return false; 80 return true; 81 } 82 83 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 84 { 85 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 86 PUBLIC_PORT); 87 u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 88 89 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 90 MFW_PORT(p_hwfn)); 91 DP_VERBOSE(p_hwfn, QED_MSG_SP, 92 "port_addr = 0x%x, port_id 0x%02x\n", 93 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 94 } 95 96 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 97 { 98 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 99 u32 tmp, i; 100 101 if (!p_hwfn->mcp_info->public_base) 102 return; 103 104 for (i = 0; i < length; i++) { 105 tmp = qed_rd(p_hwfn, p_ptt, 106 p_hwfn->mcp_info->mfw_mb_addr + 107 (i << 2) + sizeof(u32)); 108 109 /* The MB data is actually BE; Need to force it to cpu */ 110 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 111 be32_to_cpu((__force __be32)tmp); 112 } 113 } 114 115 struct qed_mcp_cmd_elem { 116 struct list_head list; 117 struct qed_mcp_mb_params *p_mb_params; 118 u16 expected_seq_num; 119 bool b_is_completed; 120 }; 121 122 /* Must be called while cmd_lock is acquired */ 123 static struct qed_mcp_cmd_elem * 124 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 125 struct qed_mcp_mb_params *p_mb_params, 126 u16 expected_seq_num) 127 { 128 struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 129 130 p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 131 if (!p_cmd_elem) 132 goto out; 133 134 p_cmd_elem->p_mb_params = p_mb_params; 135 p_cmd_elem->expected_seq_num = expected_seq_num; 136 list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 137 out: 138 return p_cmd_elem; 139 } 140 141 /* Must be called while cmd_lock is acquired */ 142 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 143 struct qed_mcp_cmd_elem *p_cmd_elem) 144 { 145 list_del(&p_cmd_elem->list); 146 kfree(p_cmd_elem); 147 } 148 149 /* Must be called while cmd_lock is acquired */ 150 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 151 u16 seq_num) 152 { 153 struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 154 155 list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 156 if (p_cmd_elem->expected_seq_num == seq_num) 157 return p_cmd_elem; 158 } 159 160 return NULL; 161 } 162 163 int qed_mcp_free(struct qed_hwfn *p_hwfn) 164 { 165 if (p_hwfn->mcp_info) { 166 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 167 168 kfree(p_hwfn->mcp_info->mfw_mb_cur); 169 kfree(p_hwfn->mcp_info->mfw_mb_shadow); 170 171 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 172 list_for_each_entry_safe(p_cmd_elem, 173 p_tmp, 174 &p_hwfn->mcp_info->cmd_list, list) { 175 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 176 } 177 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 178 } 179 180 kfree(p_hwfn->mcp_info); 181 p_hwfn->mcp_info = NULL; 182 183 return 0; 184 } 185 186 /* Maximum of 1 sec to wait for the SHMEM ready indication */ 187 #define QED_MCP_SHMEM_RDY_MAX_RETRIES 20 188 #define QED_MCP_SHMEM_RDY_ITER_MS 50 189 190 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 191 { 192 struct qed_mcp_info *p_info = p_hwfn->mcp_info; 193 u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES; 194 u8 msec = QED_MCP_SHMEM_RDY_ITER_MS; 195 u32 drv_mb_offsize, mfw_mb_offsize; 196 u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 197 198 p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 199 if (!p_info->public_base) { 200 DP_NOTICE(p_hwfn, 201 "The address of the MCP scratch-pad is not configured\n"); 202 return -EINVAL; 203 } 204 205 p_info->public_base |= GRCBASE_MCP; 206 207 /* Get the MFW MB address and number of supported messages */ 208 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 209 SECTION_OFFSIZE_ADDR(p_info->public_base, 210 PUBLIC_MFW_MB)); 211 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 212 p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, 213 p_info->mfw_mb_addr + 214 offsetof(struct public_mfw_mb, 215 sup_msgs)); 216 217 /* The driver can notify that there was an MCP reset, and might read the 218 * SHMEM values before the MFW has completed initializing them. 219 * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a 220 * data ready indication. 221 */ 222 while (!p_info->mfw_mb_length && --cnt) { 223 msleep(msec); 224 p_info->mfw_mb_length = 225 (u16)qed_rd(p_hwfn, p_ptt, 226 p_info->mfw_mb_addr + 227 offsetof(struct public_mfw_mb, sup_msgs)); 228 } 229 230 if (!cnt) { 231 DP_NOTICE(p_hwfn, 232 "Failed to get the SHMEM ready notification after %d msec\n", 233 QED_MCP_SHMEM_RDY_MAX_RETRIES * msec); 234 return -EBUSY; 235 } 236 237 /* Calculate the driver and MFW mailbox address */ 238 drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 239 SECTION_OFFSIZE_ADDR(p_info->public_base, 240 PUBLIC_DRV_MB)); 241 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 242 DP_VERBOSE(p_hwfn, QED_MSG_SP, 243 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 244 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 245 246 /* Get the current driver mailbox sequence before sending 247 * the first command 248 */ 249 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 250 DRV_MSG_SEQ_NUMBER_MASK; 251 252 /* Get current FW pulse sequence */ 253 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 254 DRV_PULSE_SEQ_MASK; 255 256 p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 257 258 return 0; 259 } 260 261 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 262 { 263 struct qed_mcp_info *p_info; 264 u32 size; 265 266 /* Allocate mcp_info structure */ 267 p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 268 if (!p_hwfn->mcp_info) 269 goto err; 270 p_info = p_hwfn->mcp_info; 271 272 /* Initialize the MFW spinlock */ 273 spin_lock_init(&p_info->cmd_lock); 274 spin_lock_init(&p_info->link_lock); 275 276 INIT_LIST_HEAD(&p_info->cmd_list); 277 278 if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 279 DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 280 /* Do not free mcp_info here, since public_base indicate that 281 * the MCP is not initialized 282 */ 283 return 0; 284 } 285 286 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 287 p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 288 p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 289 if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 290 goto err; 291 292 return 0; 293 294 err: 295 qed_mcp_free(p_hwfn); 296 return -ENOMEM; 297 } 298 299 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 300 struct qed_ptt *p_ptt) 301 { 302 u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 303 304 /* Use MCP history register to check if MCP reset occurred between init 305 * time and now. 306 */ 307 if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 308 DP_VERBOSE(p_hwfn, 309 QED_MSG_SP, 310 "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 311 p_hwfn->mcp_info->mcp_hist, generic_por_0); 312 313 qed_load_mcp_offsets(p_hwfn, p_ptt); 314 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 315 } 316 } 317 318 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 319 { 320 u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0; 321 int rc = 0; 322 323 if (p_hwfn->mcp_info->b_block_cmd) { 324 DP_NOTICE(p_hwfn, 325 "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n"); 326 return -EBUSY; 327 } 328 329 /* Ensure that only a single thread is accessing the mailbox */ 330 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 331 332 org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 333 334 /* Set drv command along with the updated sequence */ 335 qed_mcp_reread_offsets(p_hwfn, p_ptt); 336 seq = ++p_hwfn->mcp_info->drv_mb_seq; 337 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 338 339 do { 340 /* Wait for MFW response */ 341 udelay(delay); 342 /* Give the FW up to 500 second (50*1000*10usec) */ 343 } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 344 MISCS_REG_GENERIC_POR_0)) && 345 (cnt++ < QED_MCP_RESET_RETRIES)); 346 347 if (org_mcp_reset_seq != 348 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 349 DP_VERBOSE(p_hwfn, QED_MSG_SP, 350 "MCP was reset after %d usec\n", cnt * delay); 351 } else { 352 DP_ERR(p_hwfn, "Failed to reset MCP\n"); 353 rc = -EAGAIN; 354 } 355 356 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 357 358 return rc; 359 } 360 361 /* Must be called while cmd_lock is acquired */ 362 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 363 { 364 struct qed_mcp_cmd_elem *p_cmd_elem; 365 366 /* There is at most one pending command at a certain time, and if it 367 * exists - it is placed at the HEAD of the list. 368 */ 369 if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 370 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 371 struct qed_mcp_cmd_elem, list); 372 return !p_cmd_elem->b_is_completed; 373 } 374 375 return false; 376 } 377 378 /* Must be called while cmd_lock is acquired */ 379 static int 380 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 381 { 382 struct qed_mcp_mb_params *p_mb_params; 383 struct qed_mcp_cmd_elem *p_cmd_elem; 384 u32 mcp_resp; 385 u16 seq_num; 386 387 mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 388 seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 389 390 /* Return if no new non-handled response has been received */ 391 if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 392 return -EAGAIN; 393 394 p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 395 if (!p_cmd_elem) { 396 DP_ERR(p_hwfn, 397 "Failed to find a pending mailbox cmd that expects sequence number %d\n", 398 seq_num); 399 return -EINVAL; 400 } 401 402 p_mb_params = p_cmd_elem->p_mb_params; 403 404 /* Get the MFW response along with the sequence number */ 405 p_mb_params->mcp_resp = mcp_resp; 406 407 /* Get the MFW param */ 408 p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 409 410 /* Get the union data */ 411 if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 412 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 413 offsetof(struct public_drv_mb, 414 union_data); 415 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 416 union_data_addr, p_mb_params->data_dst_size); 417 } 418 419 p_cmd_elem->b_is_completed = true; 420 421 return 0; 422 } 423 424 /* Must be called while cmd_lock is acquired */ 425 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 426 struct qed_ptt *p_ptt, 427 struct qed_mcp_mb_params *p_mb_params, 428 u16 seq_num) 429 { 430 union drv_union_data union_data; 431 u32 union_data_addr; 432 433 /* Set the union data */ 434 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 435 offsetof(struct public_drv_mb, union_data); 436 memset(&union_data, 0, sizeof(union_data)); 437 if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 438 memcpy(&union_data, p_mb_params->p_data_src, 439 p_mb_params->data_src_size); 440 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 441 sizeof(union_data)); 442 443 /* Set the drv param */ 444 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 445 446 /* Set the drv command along with the sequence number */ 447 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 448 449 DP_VERBOSE(p_hwfn, QED_MSG_SP, 450 "MFW mailbox: command 0x%08x param 0x%08x\n", 451 (p_mb_params->cmd | seq_num), p_mb_params->param); 452 } 453 454 static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd) 455 { 456 p_hwfn->mcp_info->b_block_cmd = block_cmd; 457 458 DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n", 459 block_cmd ? "Block" : "Unblock"); 460 } 461 462 static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn, 463 struct qed_ptt *p_ptt) 464 { 465 u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2; 466 u32 delay = QED_MCP_RESP_ITER_US; 467 468 cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 469 cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 470 cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 471 udelay(delay); 472 cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 473 udelay(delay); 474 cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 475 476 DP_NOTICE(p_hwfn, 477 "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n", 478 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2); 479 } 480 481 static int 482 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 483 struct qed_ptt *p_ptt, 484 struct qed_mcp_mb_params *p_mb_params, 485 u32 max_retries, u32 usecs) 486 { 487 u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000); 488 struct qed_mcp_cmd_elem *p_cmd_elem; 489 u16 seq_num; 490 int rc = 0; 491 492 /* Wait until the mailbox is non-occupied */ 493 do { 494 /* Exit the loop if there is no pending command, or if the 495 * pending command is completed during this iteration. 496 * The spinlock stays locked until the command is sent. 497 */ 498 499 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 500 501 if (!qed_mcp_has_pending_cmd(p_hwfn)) 502 break; 503 504 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 505 if (!rc) 506 break; 507 else if (rc != -EAGAIN) 508 goto err; 509 510 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 511 512 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 513 msleep(msecs); 514 else 515 udelay(usecs); 516 } while (++cnt < max_retries); 517 518 if (cnt >= max_retries) { 519 DP_NOTICE(p_hwfn, 520 "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 521 p_mb_params->cmd, p_mb_params->param); 522 return -EAGAIN; 523 } 524 525 /* Send the mailbox command */ 526 qed_mcp_reread_offsets(p_hwfn, p_ptt); 527 seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 528 p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 529 if (!p_cmd_elem) { 530 rc = -ENOMEM; 531 goto err; 532 } 533 534 __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 535 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 536 537 /* Wait for the MFW response */ 538 do { 539 /* Exit the loop if the command is already completed, or if the 540 * command is completed during this iteration. 541 * The spinlock stays locked until the list element is removed. 542 */ 543 544 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 545 msleep(msecs); 546 else 547 udelay(usecs); 548 549 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 550 551 if (p_cmd_elem->b_is_completed) 552 break; 553 554 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 555 if (!rc) 556 break; 557 else if (rc != -EAGAIN) 558 goto err; 559 560 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 561 } while (++cnt < max_retries); 562 563 if (cnt >= max_retries) { 564 DP_NOTICE(p_hwfn, 565 "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 566 p_mb_params->cmd, p_mb_params->param); 567 qed_mcp_print_cpu_info(p_hwfn, p_ptt); 568 569 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 570 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 571 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 572 573 if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK)) 574 qed_mcp_cmd_set_blocking(p_hwfn, true); 575 576 return -EAGAIN; 577 } 578 579 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 580 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 581 582 DP_VERBOSE(p_hwfn, 583 QED_MSG_SP, 584 "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 585 p_mb_params->mcp_resp, 586 p_mb_params->mcp_param, 587 (cnt * usecs) / 1000, (cnt * usecs) % 1000); 588 589 /* Clear the sequence number from the MFW response */ 590 p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 591 592 return 0; 593 594 err: 595 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 596 return rc; 597 } 598 599 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 600 struct qed_ptt *p_ptt, 601 struct qed_mcp_mb_params *p_mb_params) 602 { 603 size_t union_data_size = sizeof(union drv_union_data); 604 u32 max_retries = QED_DRV_MB_MAX_RETRIES; 605 u32 usecs = QED_MCP_RESP_ITER_US; 606 607 /* MCP not initialized */ 608 if (!qed_mcp_is_init(p_hwfn)) { 609 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 610 return -EBUSY; 611 } 612 613 if (p_hwfn->mcp_info->b_block_cmd) { 614 DP_NOTICE(p_hwfn, 615 "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n", 616 p_mb_params->cmd, p_mb_params->param); 617 return -EBUSY; 618 } 619 620 if (p_mb_params->data_src_size > union_data_size || 621 p_mb_params->data_dst_size > union_data_size) { 622 DP_ERR(p_hwfn, 623 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 624 p_mb_params->data_src_size, 625 p_mb_params->data_dst_size, union_data_size); 626 return -EINVAL; 627 } 628 629 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) { 630 max_retries = DIV_ROUND_UP(max_retries, 1000); 631 usecs *= 1000; 632 } 633 634 return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 635 usecs); 636 } 637 638 int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 639 struct qed_ptt *p_ptt, 640 u32 cmd, 641 u32 param, 642 u32 *o_mcp_resp, 643 u32 *o_mcp_param) 644 { 645 struct qed_mcp_mb_params mb_params; 646 int rc; 647 648 memset(&mb_params, 0, sizeof(mb_params)); 649 mb_params.cmd = cmd; 650 mb_params.param = param; 651 652 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 653 if (rc) 654 return rc; 655 656 *o_mcp_resp = mb_params.mcp_resp; 657 *o_mcp_param = mb_params.mcp_param; 658 659 return 0; 660 } 661 662 static int 663 qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 664 struct qed_ptt *p_ptt, 665 u32 cmd, 666 u32 param, 667 u32 *o_mcp_resp, 668 u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 669 { 670 struct qed_mcp_mb_params mb_params; 671 int rc; 672 673 memset(&mb_params, 0, sizeof(mb_params)); 674 mb_params.cmd = cmd; 675 mb_params.param = param; 676 mb_params.p_data_src = i_buf; 677 mb_params.data_src_size = (u8)i_txn_size; 678 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 679 if (rc) 680 return rc; 681 682 *o_mcp_resp = mb_params.mcp_resp; 683 *o_mcp_param = mb_params.mcp_param; 684 685 /* nvm_info needs to be updated */ 686 p_hwfn->nvm_info.valid = false; 687 688 return 0; 689 } 690 691 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 692 struct qed_ptt *p_ptt, 693 u32 cmd, 694 u32 param, 695 u32 *o_mcp_resp, 696 u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 697 { 698 struct qed_mcp_mb_params mb_params; 699 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 700 int rc; 701 702 memset(&mb_params, 0, sizeof(mb_params)); 703 mb_params.cmd = cmd; 704 mb_params.param = param; 705 mb_params.p_data_dst = raw_data; 706 707 /* Use the maximal value since the actual one is part of the response */ 708 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 709 710 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 711 if (rc) 712 return rc; 713 714 *o_mcp_resp = mb_params.mcp_resp; 715 *o_mcp_param = mb_params.mcp_param; 716 717 *o_txn_size = *o_mcp_param; 718 memcpy(o_buf, raw_data, *o_txn_size); 719 720 return 0; 721 } 722 723 static bool 724 qed_mcp_can_force_load(u8 drv_role, 725 u8 exist_drv_role, 726 enum qed_override_force_load override_force_load) 727 { 728 bool can_force_load = false; 729 730 switch (override_force_load) { 731 case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 732 can_force_load = true; 733 break; 734 case QED_OVERRIDE_FORCE_LOAD_NEVER: 735 can_force_load = false; 736 break; 737 default: 738 can_force_load = (drv_role == DRV_ROLE_OS && 739 exist_drv_role == DRV_ROLE_PREBOOT) || 740 (drv_role == DRV_ROLE_KDUMP && 741 exist_drv_role == DRV_ROLE_OS); 742 break; 743 } 744 745 return can_force_load; 746 } 747 748 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 749 struct qed_ptt *p_ptt) 750 { 751 u32 resp = 0, param = 0; 752 int rc; 753 754 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 755 &resp, ¶m); 756 if (rc) 757 DP_NOTICE(p_hwfn, 758 "Failed to send cancel load request, rc = %d\n", rc); 759 760 return rc; 761 } 762 763 #define CONFIG_QEDE_BITMAP_IDX BIT(0) 764 #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 765 #define CONFIG_QEDR_BITMAP_IDX BIT(2) 766 #define CONFIG_QEDF_BITMAP_IDX BIT(4) 767 #define CONFIG_QEDI_BITMAP_IDX BIT(5) 768 #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 769 770 static u32 qed_get_config_bitmap(void) 771 { 772 u32 config_bitmap = 0x0; 773 774 if (IS_ENABLED(CONFIG_QEDE)) 775 config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 776 777 if (IS_ENABLED(CONFIG_QED_SRIOV)) 778 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 779 780 if (IS_ENABLED(CONFIG_QED_RDMA)) 781 config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 782 783 if (IS_ENABLED(CONFIG_QED_FCOE)) 784 config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 785 786 if (IS_ENABLED(CONFIG_QED_ISCSI)) 787 config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 788 789 if (IS_ENABLED(CONFIG_QED_LL2)) 790 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 791 792 return config_bitmap; 793 } 794 795 struct qed_load_req_in_params { 796 u8 hsi_ver; 797 #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 798 #define QED_LOAD_REQ_HSI_VER_1 1 799 u32 drv_ver_0; 800 u32 drv_ver_1; 801 u32 fw_ver; 802 u8 drv_role; 803 u8 timeout_val; 804 u8 force_cmd; 805 bool avoid_eng_reset; 806 }; 807 808 struct qed_load_req_out_params { 809 u32 load_code; 810 u32 exist_drv_ver_0; 811 u32 exist_drv_ver_1; 812 u32 exist_fw_ver; 813 u8 exist_drv_role; 814 u8 mfw_hsi_ver; 815 bool drv_exists; 816 }; 817 818 static int 819 __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 820 struct qed_ptt *p_ptt, 821 struct qed_load_req_in_params *p_in_params, 822 struct qed_load_req_out_params *p_out_params) 823 { 824 struct qed_mcp_mb_params mb_params; 825 struct load_req_stc load_req; 826 struct load_rsp_stc load_rsp; 827 u32 hsi_ver; 828 int rc; 829 830 memset(&load_req, 0, sizeof(load_req)); 831 load_req.drv_ver_0 = p_in_params->drv_ver_0; 832 load_req.drv_ver_1 = p_in_params->drv_ver_1; 833 load_req.fw_ver = p_in_params->fw_ver; 834 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 835 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 836 p_in_params->timeout_val); 837 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 838 p_in_params->force_cmd); 839 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 840 p_in_params->avoid_eng_reset); 841 842 hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 843 DRV_ID_MCP_HSI_VER_CURRENT : 844 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 845 846 memset(&mb_params, 0, sizeof(mb_params)); 847 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 848 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 849 mb_params.p_data_src = &load_req; 850 mb_params.data_src_size = sizeof(load_req); 851 mb_params.p_data_dst = &load_rsp; 852 mb_params.data_dst_size = sizeof(load_rsp); 853 mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 854 855 DP_VERBOSE(p_hwfn, QED_MSG_SP, 856 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 857 mb_params.param, 858 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 859 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 860 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 861 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 862 863 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 864 DP_VERBOSE(p_hwfn, QED_MSG_SP, 865 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 866 load_req.drv_ver_0, 867 load_req.drv_ver_1, 868 load_req.fw_ver, 869 load_req.misc0, 870 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 871 QED_MFW_GET_FIELD(load_req.misc0, 872 LOAD_REQ_LOCK_TO), 873 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 874 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 875 } 876 877 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 878 if (rc) { 879 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 880 return rc; 881 } 882 883 DP_VERBOSE(p_hwfn, QED_MSG_SP, 884 "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 885 p_out_params->load_code = mb_params.mcp_resp; 886 887 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 888 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 889 DP_VERBOSE(p_hwfn, 890 QED_MSG_SP, 891 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 892 load_rsp.drv_ver_0, 893 load_rsp.drv_ver_1, 894 load_rsp.fw_ver, 895 load_rsp.misc0, 896 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 897 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 898 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 899 900 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 901 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 902 p_out_params->exist_fw_ver = load_rsp.fw_ver; 903 p_out_params->exist_drv_role = 904 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 905 p_out_params->mfw_hsi_ver = 906 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 907 p_out_params->drv_exists = 908 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 909 LOAD_RSP_FLAGS0_DRV_EXISTS; 910 } 911 912 return 0; 913 } 914 915 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 916 enum qed_drv_role drv_role, 917 u8 *p_mfw_drv_role) 918 { 919 switch (drv_role) { 920 case QED_DRV_ROLE_OS: 921 *p_mfw_drv_role = DRV_ROLE_OS; 922 break; 923 case QED_DRV_ROLE_KDUMP: 924 *p_mfw_drv_role = DRV_ROLE_KDUMP; 925 break; 926 default: 927 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 928 return -EINVAL; 929 } 930 931 return 0; 932 } 933 934 enum qed_load_req_force { 935 QED_LOAD_REQ_FORCE_NONE, 936 QED_LOAD_REQ_FORCE_PF, 937 QED_LOAD_REQ_FORCE_ALL, 938 }; 939 940 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 941 942 enum qed_load_req_force force_cmd, 943 u8 *p_mfw_force_cmd) 944 { 945 switch (force_cmd) { 946 case QED_LOAD_REQ_FORCE_NONE: 947 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 948 break; 949 case QED_LOAD_REQ_FORCE_PF: 950 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 951 break; 952 case QED_LOAD_REQ_FORCE_ALL: 953 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 954 break; 955 } 956 } 957 958 int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 959 struct qed_ptt *p_ptt, 960 struct qed_load_req_params *p_params) 961 { 962 struct qed_load_req_out_params out_params; 963 struct qed_load_req_in_params in_params; 964 u8 mfw_drv_role, mfw_force_cmd; 965 int rc; 966 967 memset(&in_params, 0, sizeof(in_params)); 968 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 969 in_params.drv_ver_0 = QED_VERSION; 970 in_params.drv_ver_1 = qed_get_config_bitmap(); 971 in_params.fw_ver = STORM_FW_VERSION; 972 rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 973 if (rc) 974 return rc; 975 976 in_params.drv_role = mfw_drv_role; 977 in_params.timeout_val = p_params->timeout_val; 978 qed_get_mfw_force_cmd(p_hwfn, 979 QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 980 981 in_params.force_cmd = mfw_force_cmd; 982 in_params.avoid_eng_reset = p_params->avoid_eng_reset; 983 984 memset(&out_params, 0, sizeof(out_params)); 985 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 986 if (rc) 987 return rc; 988 989 /* First handle cases where another load request should/might be sent: 990 * - MFW expects the old interface [HSI version = 1] 991 * - MFW responds that a force load request is required 992 */ 993 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 994 DP_INFO(p_hwfn, 995 "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 996 997 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 998 memset(&out_params, 0, sizeof(out_params)); 999 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 1000 if (rc) 1001 return rc; 1002 } else if (out_params.load_code == 1003 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 1004 if (qed_mcp_can_force_load(in_params.drv_role, 1005 out_params.exist_drv_role, 1006 p_params->override_force_load)) { 1007 DP_INFO(p_hwfn, 1008 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 1009 in_params.drv_role, in_params.fw_ver, 1010 in_params.drv_ver_0, in_params.drv_ver_1, 1011 out_params.exist_drv_role, 1012 out_params.exist_fw_ver, 1013 out_params.exist_drv_ver_0, 1014 out_params.exist_drv_ver_1); 1015 1016 qed_get_mfw_force_cmd(p_hwfn, 1017 QED_LOAD_REQ_FORCE_ALL, 1018 &mfw_force_cmd); 1019 1020 in_params.force_cmd = mfw_force_cmd; 1021 memset(&out_params, 0, sizeof(out_params)); 1022 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 1023 &out_params); 1024 if (rc) 1025 return rc; 1026 } else { 1027 DP_NOTICE(p_hwfn, 1028 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 1029 in_params.drv_role, in_params.fw_ver, 1030 in_params.drv_ver_0, in_params.drv_ver_1, 1031 out_params.exist_drv_role, 1032 out_params.exist_fw_ver, 1033 out_params.exist_drv_ver_0, 1034 out_params.exist_drv_ver_1); 1035 DP_NOTICE(p_hwfn, 1036 "Avoid sending a force load request to prevent disruption of active PFs\n"); 1037 1038 qed_mcp_cancel_load_req(p_hwfn, p_ptt); 1039 return -EBUSY; 1040 } 1041 } 1042 1043 /* Now handle the other types of responses. 1044 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 1045 * expected here after the additional revised load requests were sent. 1046 */ 1047 switch (out_params.load_code) { 1048 case FW_MSG_CODE_DRV_LOAD_ENGINE: 1049 case FW_MSG_CODE_DRV_LOAD_PORT: 1050 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1051 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 1052 out_params.drv_exists) { 1053 /* The role and fw/driver version match, but the PF is 1054 * already loaded and has not been unloaded gracefully. 1055 */ 1056 DP_NOTICE(p_hwfn, 1057 "PF is already loaded\n"); 1058 return -EINVAL; 1059 } 1060 break; 1061 default: 1062 DP_NOTICE(p_hwfn, 1063 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 1064 out_params.load_code); 1065 return -EBUSY; 1066 } 1067 1068 p_params->load_code = out_params.load_code; 1069 1070 return 0; 1071 } 1072 1073 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1074 { 1075 struct qed_mcp_mb_params mb_params; 1076 u32 wol_param; 1077 1078 switch (p_hwfn->cdev->wol_config) { 1079 case QED_OV_WOL_DISABLED: 1080 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 1081 break; 1082 case QED_OV_WOL_ENABLED: 1083 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 1084 break; 1085 default: 1086 DP_NOTICE(p_hwfn, 1087 "Unknown WoL configuration %02x\n", 1088 p_hwfn->cdev->wol_config); 1089 /* Fallthrough */ 1090 case QED_OV_WOL_DEFAULT: 1091 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 1092 } 1093 1094 memset(&mb_params, 0, sizeof(mb_params)); 1095 mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ; 1096 mb_params.param = wol_param; 1097 mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 1098 1099 return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1100 } 1101 1102 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1103 { 1104 struct qed_mcp_mb_params mb_params; 1105 struct mcp_mac wol_mac; 1106 1107 memset(&mb_params, 0, sizeof(mb_params)); 1108 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 1109 1110 /* Set the primary MAC if WoL is enabled */ 1111 if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 1112 u8 *p_mac = p_hwfn->cdev->wol_mac; 1113 1114 memset(&wol_mac, 0, sizeof(wol_mac)); 1115 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 1116 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 1117 p_mac[4] << 8 | p_mac[5]; 1118 1119 DP_VERBOSE(p_hwfn, 1120 (QED_MSG_SP | NETIF_MSG_IFDOWN), 1121 "Setting WoL MAC: %pM --> [%08x,%08x]\n", 1122 p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 1123 1124 mb_params.p_data_src = &wol_mac; 1125 mb_params.data_src_size = sizeof(wol_mac); 1126 } 1127 1128 return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1129 } 1130 1131 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 1132 struct qed_ptt *p_ptt) 1133 { 1134 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1135 PUBLIC_PATH); 1136 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1137 u32 path_addr = SECTION_ADDR(mfw_path_offsize, 1138 QED_PATH_ID(p_hwfn)); 1139 u32 disabled_vfs[VF_MAX_STATIC / 32]; 1140 int i; 1141 1142 DP_VERBOSE(p_hwfn, 1143 QED_MSG_SP, 1144 "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 1145 mfw_path_offsize, path_addr); 1146 1147 for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 1148 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 1149 path_addr + 1150 offsetof(struct public_path, 1151 mcp_vf_disabled) + 1152 sizeof(u32) * i); 1153 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 1154 "FLR-ed VFs [%08x,...,%08x] - %08x\n", 1155 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 1156 } 1157 1158 if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 1159 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 1160 } 1161 1162 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 1163 struct qed_ptt *p_ptt, u32 *vfs_to_ack) 1164 { 1165 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1166 PUBLIC_FUNC); 1167 u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 1168 u32 func_addr = SECTION_ADDR(mfw_func_offsize, 1169 MCP_PF_ID(p_hwfn)); 1170 struct qed_mcp_mb_params mb_params; 1171 int rc; 1172 int i; 1173 1174 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 1175 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 1176 "Acking VFs [%08x,...,%08x] - %08x\n", 1177 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 1178 1179 memset(&mb_params, 0, sizeof(mb_params)); 1180 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 1181 mb_params.p_data_src = vfs_to_ack; 1182 mb_params.data_src_size = VF_MAX_STATIC / 8; 1183 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1184 if (rc) { 1185 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 1186 return -EBUSY; 1187 } 1188 1189 /* Clear the ACK bits */ 1190 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 1191 qed_wr(p_hwfn, p_ptt, 1192 func_addr + 1193 offsetof(struct public_func, drv_ack_vf_disabled) + 1194 i * sizeof(u32), 0); 1195 1196 return rc; 1197 } 1198 1199 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1200 struct qed_ptt *p_ptt) 1201 { 1202 u32 transceiver_state; 1203 1204 transceiver_state = qed_rd(p_hwfn, p_ptt, 1205 p_hwfn->mcp_info->port_addr + 1206 offsetof(struct public_port, 1207 transceiver_data)); 1208 1209 DP_VERBOSE(p_hwfn, 1210 (NETIF_MSG_HW | QED_MSG_SP), 1211 "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1212 transceiver_state, 1213 (u32)(p_hwfn->mcp_info->port_addr + 1214 offsetof(struct public_port, transceiver_data))); 1215 1216 transceiver_state = GET_FIELD(transceiver_state, 1217 ETH_TRANSCEIVER_STATE); 1218 1219 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1220 DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1221 else 1222 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1223 } 1224 1225 static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1226 struct qed_ptt *p_ptt, 1227 struct qed_mcp_link_state *p_link) 1228 { 1229 u32 eee_status, val; 1230 1231 p_link->eee_adv_caps = 0; 1232 p_link->eee_lp_adv_caps = 0; 1233 eee_status = qed_rd(p_hwfn, 1234 p_ptt, 1235 p_hwfn->mcp_info->port_addr + 1236 offsetof(struct public_port, eee_status)); 1237 p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1238 val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1239 if (val & EEE_1G_ADV) 1240 p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1241 if (val & EEE_10G_ADV) 1242 p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1243 val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1244 if (val & EEE_1G_ADV) 1245 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1246 if (val & EEE_10G_ADV) 1247 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1248 } 1249 1250 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 1251 struct qed_ptt *p_ptt, 1252 struct public_func *p_data, int pfid) 1253 { 1254 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1255 PUBLIC_FUNC); 1256 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1257 u32 func_addr; 1258 u32 i, size; 1259 1260 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 1261 memset(p_data, 0, sizeof(*p_data)); 1262 1263 size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 1264 for (i = 0; i < size / sizeof(u32); i++) 1265 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 1266 func_addr + (i << 2)); 1267 return size; 1268 } 1269 1270 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 1271 struct public_func *p_shmem_info) 1272 { 1273 struct qed_mcp_function_info *p_info; 1274 1275 p_info = &p_hwfn->mcp_info->func_info; 1276 1277 p_info->bandwidth_min = QED_MFW_GET_FIELD(p_shmem_info->config, 1278 FUNC_MF_CFG_MIN_BW); 1279 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 1280 DP_INFO(p_hwfn, 1281 "bandwidth minimum out of bounds [%02x]. Set to 1\n", 1282 p_info->bandwidth_min); 1283 p_info->bandwidth_min = 1; 1284 } 1285 1286 p_info->bandwidth_max = QED_MFW_GET_FIELD(p_shmem_info->config, 1287 FUNC_MF_CFG_MAX_BW); 1288 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 1289 DP_INFO(p_hwfn, 1290 "bandwidth maximum out of bounds [%02x]. Set to 100\n", 1291 p_info->bandwidth_max); 1292 p_info->bandwidth_max = 100; 1293 } 1294 } 1295 1296 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 1297 struct qed_ptt *p_ptt, bool b_reset) 1298 { 1299 struct qed_mcp_link_state *p_link; 1300 u8 max_bw, min_bw; 1301 u32 status = 0; 1302 1303 /* Prevent SW/attentions from doing this at the same time */ 1304 spin_lock_bh(&p_hwfn->mcp_info->link_lock); 1305 1306 p_link = &p_hwfn->mcp_info->link_output; 1307 memset(p_link, 0, sizeof(*p_link)); 1308 if (!b_reset) { 1309 status = qed_rd(p_hwfn, p_ptt, 1310 p_hwfn->mcp_info->port_addr + 1311 offsetof(struct public_port, link_status)); 1312 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1313 "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1314 status, 1315 (u32)(p_hwfn->mcp_info->port_addr + 1316 offsetof(struct public_port, link_status))); 1317 } else { 1318 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1319 "Resetting link indications\n"); 1320 goto out; 1321 } 1322 1323 if (p_hwfn->b_drv_link_init) { 1324 /* Link indication with modern MFW arrives as per-PF 1325 * indication. 1326 */ 1327 if (p_hwfn->mcp_info->capabilities & 1328 FW_MB_PARAM_FEATURE_SUPPORT_VLINK) { 1329 struct public_func shmem_info; 1330 1331 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 1332 MCP_PF_ID(p_hwfn)); 1333 p_link->link_up = !!(shmem_info.status & 1334 FUNC_STATUS_VIRTUAL_LINK_UP); 1335 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1336 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1337 "Virtual link_up = %d\n", p_link->link_up); 1338 } else { 1339 p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1340 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1341 "Physical link_up = %d\n", p_link->link_up); 1342 } 1343 } else { 1344 p_link->link_up = false; 1345 } 1346 1347 p_link->full_duplex = true; 1348 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1349 case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1350 p_link->speed = 100000; 1351 break; 1352 case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1353 p_link->speed = 50000; 1354 break; 1355 case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1356 p_link->speed = 40000; 1357 break; 1358 case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1359 p_link->speed = 25000; 1360 break; 1361 case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1362 p_link->speed = 20000; 1363 break; 1364 case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1365 p_link->speed = 10000; 1366 break; 1367 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1368 p_link->full_duplex = false; 1369 /* Fall-through */ 1370 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1371 p_link->speed = 1000; 1372 break; 1373 default: 1374 p_link->speed = 0; 1375 p_link->link_up = 0; 1376 } 1377 1378 if (p_link->link_up && p_link->speed) 1379 p_link->line_speed = p_link->speed; 1380 else 1381 p_link->line_speed = 0; 1382 1383 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1384 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 1385 1386 /* Max bandwidth configuration */ 1387 __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1388 1389 /* Min bandwidth configuration */ 1390 __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 1391 qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 1392 p_link->min_pf_rate); 1393 1394 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1395 p_link->an_complete = !!(status & 1396 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1397 p_link->parallel_detection = !!(status & 1398 LINK_STATUS_PARALLEL_DETECTION_USED); 1399 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1400 1401 p_link->partner_adv_speed |= 1402 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1403 QED_LINK_PARTNER_SPEED_1G_FD : 0; 1404 p_link->partner_adv_speed |= 1405 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1406 QED_LINK_PARTNER_SPEED_1G_HD : 0; 1407 p_link->partner_adv_speed |= 1408 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1409 QED_LINK_PARTNER_SPEED_10G : 0; 1410 p_link->partner_adv_speed |= 1411 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1412 QED_LINK_PARTNER_SPEED_20G : 0; 1413 p_link->partner_adv_speed |= 1414 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1415 QED_LINK_PARTNER_SPEED_25G : 0; 1416 p_link->partner_adv_speed |= 1417 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1418 QED_LINK_PARTNER_SPEED_40G : 0; 1419 p_link->partner_adv_speed |= 1420 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1421 QED_LINK_PARTNER_SPEED_50G : 0; 1422 p_link->partner_adv_speed |= 1423 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1424 QED_LINK_PARTNER_SPEED_100G : 0; 1425 1426 p_link->partner_tx_flow_ctrl_en = 1427 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1428 p_link->partner_rx_flow_ctrl_en = 1429 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1430 1431 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1432 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1433 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1434 break; 1435 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1436 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1437 break; 1438 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1439 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1440 break; 1441 default: 1442 p_link->partner_adv_pause = 0; 1443 } 1444 1445 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1446 1447 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1448 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1449 1450 qed_link_update(p_hwfn, p_ptt); 1451 out: 1452 spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1453 } 1454 1455 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1456 { 1457 struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 1458 struct qed_mcp_mb_params mb_params; 1459 struct eth_phy_cfg phy_cfg; 1460 int rc = 0; 1461 u32 cmd; 1462 1463 /* Set the shmem configuration according to params */ 1464 memset(&phy_cfg, 0, sizeof(phy_cfg)); 1465 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1466 if (!params->speed.autoneg) 1467 phy_cfg.speed = params->speed.forced_speed; 1468 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 1469 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 1470 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 1471 phy_cfg.adv_speed = params->speed.advertised_speeds; 1472 phy_cfg.loopback_mode = params->loopback_mode; 1473 1474 /* There are MFWs that share this capability regardless of whether 1475 * this is feasible or not. And given that at the very least adv_caps 1476 * would be set internally by qed, we want to make sure LFA would 1477 * still work. 1478 */ 1479 if ((p_hwfn->mcp_info->capabilities & 1480 FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1481 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1482 if (params->eee.tx_lpi_enable) 1483 phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1484 if (params->eee.adv_caps & QED_EEE_1G_ADV) 1485 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1486 if (params->eee.adv_caps & QED_EEE_10G_ADV) 1487 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1488 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1489 EEE_TX_TIMER_USEC_OFFSET) & 1490 EEE_TX_TIMER_USEC_MASK; 1491 } 1492 1493 p_hwfn->b_drv_link_init = b_up; 1494 1495 if (b_up) { 1496 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1497 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 1498 phy_cfg.speed, 1499 phy_cfg.pause, 1500 phy_cfg.adv_speed, 1501 phy_cfg.loopback_mode, 1502 phy_cfg.feature_config_flags); 1503 } else { 1504 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1505 "Resetting link\n"); 1506 } 1507 1508 memset(&mb_params, 0, sizeof(mb_params)); 1509 mb_params.cmd = cmd; 1510 mb_params.p_data_src = &phy_cfg; 1511 mb_params.data_src_size = sizeof(phy_cfg); 1512 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1513 1514 /* if mcp fails to respond we must abort */ 1515 if (rc) { 1516 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1517 return rc; 1518 } 1519 1520 /* Mimic link-change attention, done for several reasons: 1521 * - On reset, there's no guarantee MFW would trigger 1522 * an attention. 1523 * - On initialization, older MFWs might not indicate link change 1524 * during LFA, so we'll never get an UP indication. 1525 */ 1526 qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1527 1528 return 0; 1529 } 1530 1531 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 1532 struct qed_ptt *p_ptt, 1533 enum MFW_DRV_MSG_TYPE type) 1534 { 1535 enum qed_mcp_protocol_type stats_type; 1536 union qed_mcp_protocol_stats stats; 1537 struct qed_mcp_mb_params mb_params; 1538 u32 hsi_param; 1539 1540 switch (type) { 1541 case MFW_DRV_MSG_GET_LAN_STATS: 1542 stats_type = QED_MCP_LAN_STATS; 1543 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 1544 break; 1545 case MFW_DRV_MSG_GET_FCOE_STATS: 1546 stats_type = QED_MCP_FCOE_STATS; 1547 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 1548 break; 1549 case MFW_DRV_MSG_GET_ISCSI_STATS: 1550 stats_type = QED_MCP_ISCSI_STATS; 1551 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 1552 break; 1553 case MFW_DRV_MSG_GET_RDMA_STATS: 1554 stats_type = QED_MCP_RDMA_STATS; 1555 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 1556 break; 1557 default: 1558 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 1559 return; 1560 } 1561 1562 qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 1563 1564 memset(&mb_params, 0, sizeof(mb_params)); 1565 mb_params.cmd = DRV_MSG_CODE_GET_STATS; 1566 mb_params.param = hsi_param; 1567 mb_params.p_data_src = &stats; 1568 mb_params.data_src_size = sizeof(stats); 1569 qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1570 } 1571 1572 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1573 { 1574 struct qed_mcp_function_info *p_info; 1575 struct public_func shmem_info; 1576 u32 resp = 0, param = 0; 1577 1578 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1579 1580 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1581 1582 p_info = &p_hwfn->mcp_info->func_info; 1583 1584 qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 1585 qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 1586 1587 /* Acknowledge the MFW */ 1588 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 1589 ¶m); 1590 } 1591 1592 static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1593 { 1594 struct public_func shmem_info; 1595 u32 resp = 0, param = 0; 1596 1597 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1598 1599 p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 1600 FUNC_MF_CFG_OV_STAG_MASK; 1601 p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 1602 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) { 1603 if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) { 1604 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 1605 p_hwfn->hw_info.ovlan); 1606 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1); 1607 1608 /* Configure DB to add external vlan to EDPM packets */ 1609 qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1); 1610 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 1611 p_hwfn->hw_info.ovlan); 1612 } else { 1613 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0); 1614 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0); 1615 qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0); 1616 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0); 1617 } 1618 1619 qed_sp_pf_update_stag(p_hwfn); 1620 } 1621 1622 DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan = %d hw_mode = 0x%x\n", 1623 p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode); 1624 1625 /* Acknowledge the MFW */ 1626 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 1627 &resp, ¶m); 1628 } 1629 1630 void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1631 { 1632 struct public_func shmem_info; 1633 u32 port_cfg, val; 1634 1635 if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1636 return; 1637 1638 memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1639 port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1640 offsetof(struct public_port, oem_cfg_port)); 1641 val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1642 OEM_CFG_CHANNEL_TYPE_OFFSET; 1643 if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1644 DP_NOTICE(p_hwfn, 1645 "Incorrect UFP Channel type %d port_id 0x%02x\n", 1646 val, MFW_PORT(p_hwfn)); 1647 1648 val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1649 if (val == OEM_CFG_SCHED_TYPE_ETS) { 1650 p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1651 } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1652 p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1653 } else { 1654 p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1655 DP_NOTICE(p_hwfn, 1656 "Unknown UFP scheduling mode %d port_id 0x%02x\n", 1657 val, MFW_PORT(p_hwfn)); 1658 } 1659 1660 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1661 val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1662 OEM_CFG_FUNC_TC_OFFSET; 1663 p_hwfn->ufp_info.tc = (u8)val; 1664 val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1665 OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1666 if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1667 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1668 } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1669 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1670 } else { 1671 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1672 DP_NOTICE(p_hwfn, 1673 "Unknown Host priority control %d port_id 0x%02x\n", 1674 val, MFW_PORT(p_hwfn)); 1675 } 1676 1677 DP_NOTICE(p_hwfn, 1678 "UFP shmem config: mode = %d tc = %d pri_type = %d port_id 0x%02x\n", 1679 p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc, 1680 p_hwfn->ufp_info.pri_type, MFW_PORT(p_hwfn)); 1681 } 1682 1683 static int 1684 qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1685 { 1686 qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1687 1688 if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1689 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1690 qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1691 p_hwfn->ufp_info.tc); 1692 1693 qed_qm_reconf(p_hwfn, p_ptt); 1694 } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1695 /* Merge UFP TC with the dcbx TC data */ 1696 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1697 QED_DCBX_OPERATIONAL_MIB); 1698 } else { 1699 DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1700 return -EINVAL; 1701 } 1702 1703 /* update storm FW with negotiation results */ 1704 qed_sp_pf_update_ufp(p_hwfn); 1705 1706 /* update stag pcp value */ 1707 qed_sp_pf_update_stag(p_hwfn); 1708 1709 return 0; 1710 } 1711 1712 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1713 struct qed_ptt *p_ptt) 1714 { 1715 struct qed_mcp_info *info = p_hwfn->mcp_info; 1716 int rc = 0; 1717 bool found = false; 1718 u16 i; 1719 1720 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1721 1722 /* Read Messages from MFW */ 1723 qed_mcp_read_mb(p_hwfn, p_ptt); 1724 1725 /* Compare current messages to old ones */ 1726 for (i = 0; i < info->mfw_mb_length; i++) { 1727 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1728 continue; 1729 1730 found = true; 1731 1732 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1733 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1734 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1735 1736 switch (i) { 1737 case MFW_DRV_MSG_LINK_CHANGE: 1738 qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1739 break; 1740 case MFW_DRV_MSG_VF_DISABLED: 1741 qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 1742 break; 1743 case MFW_DRV_MSG_LLDP_DATA_UPDATED: 1744 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1745 QED_DCBX_REMOTE_LLDP_MIB); 1746 break; 1747 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 1748 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1749 QED_DCBX_REMOTE_MIB); 1750 break; 1751 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 1752 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1753 QED_DCBX_OPERATIONAL_MIB); 1754 break; 1755 case MFW_DRV_MSG_OEM_CFG_UPDATE: 1756 qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 1757 break; 1758 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1759 qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1760 break; 1761 case MFW_DRV_MSG_GET_LAN_STATS: 1762 case MFW_DRV_MSG_GET_FCOE_STATS: 1763 case MFW_DRV_MSG_GET_ISCSI_STATS: 1764 case MFW_DRV_MSG_GET_RDMA_STATS: 1765 qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 1766 break; 1767 case MFW_DRV_MSG_BW_UPDATE: 1768 qed_mcp_update_bw(p_hwfn, p_ptt); 1769 break; 1770 case MFW_DRV_MSG_S_TAG_UPDATE: 1771 qed_mcp_update_stag(p_hwfn, p_ptt); 1772 break; 1773 case MFW_DRV_MSG_GET_TLV_REQ: 1774 qed_mfw_tlv_req(p_hwfn); 1775 break; 1776 default: 1777 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1778 rc = -EINVAL; 1779 } 1780 } 1781 1782 /* ACK everything */ 1783 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1784 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1785 1786 /* MFW expect answer in BE, so we force write in that format */ 1787 qed_wr(p_hwfn, p_ptt, 1788 info->mfw_mb_addr + sizeof(u32) + 1789 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1790 sizeof(u32) + i * sizeof(u32), 1791 (__force u32)val); 1792 } 1793 1794 if (!found) { 1795 DP_NOTICE(p_hwfn, 1796 "Received an MFW message indication but no new message!\n"); 1797 rc = -EINVAL; 1798 } 1799 1800 /* Copy the new mfw messages into the shadow */ 1801 memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1802 1803 return rc; 1804 } 1805 1806 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 1807 struct qed_ptt *p_ptt, 1808 u32 *p_mfw_ver, u32 *p_running_bundle_id) 1809 { 1810 u32 global_offsize; 1811 1812 if (IS_VF(p_hwfn->cdev)) { 1813 if (p_hwfn->vf_iov_info) { 1814 struct pfvf_acquire_resp_tlv *p_resp; 1815 1816 p_resp = &p_hwfn->vf_iov_info->acquire_resp; 1817 *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 1818 return 0; 1819 } else { 1820 DP_VERBOSE(p_hwfn, 1821 QED_MSG_IOV, 1822 "VF requested MFW version prior to ACQUIRE\n"); 1823 return -EINVAL; 1824 } 1825 } 1826 1827 global_offsize = qed_rd(p_hwfn, p_ptt, 1828 SECTION_OFFSIZE_ADDR(p_hwfn-> 1829 mcp_info->public_base, 1830 PUBLIC_GLOBAL)); 1831 *p_mfw_ver = 1832 qed_rd(p_hwfn, p_ptt, 1833 SECTION_ADDR(global_offsize, 1834 0) + offsetof(struct public_global, mfw_ver)); 1835 1836 if (p_running_bundle_id != NULL) { 1837 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 1838 SECTION_ADDR(global_offsize, 0) + 1839 offsetof(struct public_global, 1840 running_bundle_id)); 1841 } 1842 1843 return 0; 1844 } 1845 1846 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 1847 struct qed_ptt *p_ptt, u32 *p_mbi_ver) 1848 { 1849 u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 1850 1851 if (IS_VF(p_hwfn->cdev)) 1852 return -EINVAL; 1853 1854 /* Read the address of the nvm_cfg */ 1855 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1856 if (!nvm_cfg_addr) { 1857 DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1858 return -EINVAL; 1859 } 1860 1861 /* Read the offset of nvm_cfg1 */ 1862 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1863 1864 mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1865 offsetof(struct nvm_cfg1, glob) + 1866 offsetof(struct nvm_cfg1_glob, mbi_version); 1867 *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 1868 mbi_ver_addr) & 1869 (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 1870 NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 1871 NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 1872 1873 return 0; 1874 } 1875 1876 int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, 1877 struct qed_ptt *p_ptt, u32 *p_media_type) 1878 { 1879 *p_media_type = MEDIA_UNSPECIFIED; 1880 1881 if (IS_VF(p_hwfn->cdev)) 1882 return -EINVAL; 1883 1884 if (!qed_mcp_is_init(p_hwfn)) { 1885 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1886 return -EBUSY; 1887 } 1888 1889 if (!p_ptt) { 1890 *p_media_type = MEDIA_UNSPECIFIED; 1891 return -EINVAL; 1892 } 1893 1894 *p_media_type = qed_rd(p_hwfn, p_ptt, 1895 p_hwfn->mcp_info->port_addr + 1896 offsetof(struct public_port, 1897 media_type)); 1898 1899 return 0; 1900 } 1901 1902 int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, 1903 struct qed_ptt *p_ptt, 1904 u32 *p_transceiver_state, 1905 u32 *p_transceiver_type) 1906 { 1907 u32 transceiver_info; 1908 1909 *p_transceiver_type = ETH_TRANSCEIVER_TYPE_NONE; 1910 *p_transceiver_state = ETH_TRANSCEIVER_STATE_UPDATING; 1911 1912 if (IS_VF(p_hwfn->cdev)) 1913 return -EINVAL; 1914 1915 if (!qed_mcp_is_init(p_hwfn)) { 1916 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1917 return -EBUSY; 1918 } 1919 1920 transceiver_info = qed_rd(p_hwfn, p_ptt, 1921 p_hwfn->mcp_info->port_addr + 1922 offsetof(struct public_port, 1923 transceiver_data)); 1924 1925 *p_transceiver_state = (transceiver_info & 1926 ETH_TRANSCEIVER_STATE_MASK) >> 1927 ETH_TRANSCEIVER_STATE_OFFSET; 1928 1929 if (*p_transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1930 *p_transceiver_type = (transceiver_info & 1931 ETH_TRANSCEIVER_TYPE_MASK) >> 1932 ETH_TRANSCEIVER_TYPE_OFFSET; 1933 else 1934 *p_transceiver_type = ETH_TRANSCEIVER_TYPE_UNKNOWN; 1935 1936 return 0; 1937 } 1938 static bool qed_is_transceiver_ready(u32 transceiver_state, 1939 u32 transceiver_type) 1940 { 1941 if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) && 1942 ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) && 1943 (transceiver_type != ETH_TRANSCEIVER_TYPE_NONE)) 1944 return true; 1945 1946 return false; 1947 } 1948 1949 int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, 1950 struct qed_ptt *p_ptt, u32 *p_speed_mask) 1951 { 1952 u32 transceiver_type, transceiver_state; 1953 int ret; 1954 1955 ret = qed_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state, 1956 &transceiver_type); 1957 if (ret) 1958 return ret; 1959 1960 if (qed_is_transceiver_ready(transceiver_state, transceiver_type) == 1961 false) 1962 return -EINVAL; 1963 1964 switch (transceiver_type) { 1965 case ETH_TRANSCEIVER_TYPE_1G_LX: 1966 case ETH_TRANSCEIVER_TYPE_1G_SX: 1967 case ETH_TRANSCEIVER_TYPE_1G_PCC: 1968 case ETH_TRANSCEIVER_TYPE_1G_ACC: 1969 case ETH_TRANSCEIVER_TYPE_1000BASET: 1970 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1971 break; 1972 case ETH_TRANSCEIVER_TYPE_10G_SR: 1973 case ETH_TRANSCEIVER_TYPE_10G_LR: 1974 case ETH_TRANSCEIVER_TYPE_10G_LRM: 1975 case ETH_TRANSCEIVER_TYPE_10G_ER: 1976 case ETH_TRANSCEIVER_TYPE_10G_PCC: 1977 case ETH_TRANSCEIVER_TYPE_10G_ACC: 1978 case ETH_TRANSCEIVER_TYPE_4x10G: 1979 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1980 break; 1981 case ETH_TRANSCEIVER_TYPE_40G_LR4: 1982 case ETH_TRANSCEIVER_TYPE_40G_SR4: 1983 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR: 1984 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR: 1985 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 1986 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1987 break; 1988 case ETH_TRANSCEIVER_TYPE_100G_AOC: 1989 case ETH_TRANSCEIVER_TYPE_100G_SR4: 1990 case ETH_TRANSCEIVER_TYPE_100G_LR4: 1991 case ETH_TRANSCEIVER_TYPE_100G_ER4: 1992 case ETH_TRANSCEIVER_TYPE_100G_ACC: 1993 *p_speed_mask = 1994 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 1995 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 1996 break; 1997 case ETH_TRANSCEIVER_TYPE_25G_SR: 1998 case ETH_TRANSCEIVER_TYPE_25G_LR: 1999 case ETH_TRANSCEIVER_TYPE_25G_AOC: 2000 case ETH_TRANSCEIVER_TYPE_25G_ACC_S: 2001 case ETH_TRANSCEIVER_TYPE_25G_ACC_M: 2002 case ETH_TRANSCEIVER_TYPE_25G_ACC_L: 2003 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2004 break; 2005 case ETH_TRANSCEIVER_TYPE_25G_CA_N: 2006 case ETH_TRANSCEIVER_TYPE_25G_CA_S: 2007 case ETH_TRANSCEIVER_TYPE_25G_CA_L: 2008 case ETH_TRANSCEIVER_TYPE_4x25G_CR: 2009 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2010 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2011 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2012 break; 2013 case ETH_TRANSCEIVER_TYPE_40G_CR4: 2014 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR: 2015 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2016 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2017 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2018 break; 2019 case ETH_TRANSCEIVER_TYPE_100G_CR4: 2020 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR: 2021 *p_speed_mask = 2022 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2023 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G | 2024 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2025 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2026 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G | 2027 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2028 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2029 break; 2030 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR: 2031 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR: 2032 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC: 2033 *p_speed_mask = 2034 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2035 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2036 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2037 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2038 break; 2039 case ETH_TRANSCEIVER_TYPE_XLPPI: 2040 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 2041 break; 2042 case ETH_TRANSCEIVER_TYPE_10G_BASET: 2043 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2044 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2045 break; 2046 default: 2047 DP_INFO(p_hwfn, "Unknown transceiver type 0x%x\n", 2048 transceiver_type); 2049 *p_speed_mask = 0xff; 2050 break; 2051 } 2052 2053 return 0; 2054 } 2055 2056 int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, 2057 struct qed_ptt *p_ptt, u32 *p_board_config) 2058 { 2059 u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr; 2060 2061 if (IS_VF(p_hwfn->cdev)) 2062 return -EINVAL; 2063 2064 if (!qed_mcp_is_init(p_hwfn)) { 2065 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2066 return -EBUSY; 2067 } 2068 if (!p_ptt) { 2069 *p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED; 2070 return -EINVAL; 2071 } 2072 2073 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2074 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2075 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2076 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2077 *p_board_config = qed_rd(p_hwfn, p_ptt, 2078 port_cfg_addr + 2079 offsetof(struct nvm_cfg1_port, 2080 board_cfg)); 2081 2082 return 0; 2083 } 2084 2085 /* Old MFW has a global configuration for all PFs regarding RDMA support */ 2086 static void 2087 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 2088 enum qed_pci_personality *p_proto) 2089 { 2090 /* There wasn't ever a legacy MFW that published iwarp. 2091 * So at this point, this is either plain l2 or RoCE. 2092 */ 2093 if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 2094 *p_proto = QED_PCI_ETH_ROCE; 2095 else 2096 *p_proto = QED_PCI_ETH; 2097 2098 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 2099 "According to Legacy capabilities, L2 personality is %08x\n", 2100 (u32) *p_proto); 2101 } 2102 2103 static int 2104 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 2105 struct qed_ptt *p_ptt, 2106 enum qed_pci_personality *p_proto) 2107 { 2108 u32 resp = 0, param = 0; 2109 int rc; 2110 2111 rc = qed_mcp_cmd(p_hwfn, p_ptt, 2112 DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 2113 if (rc) 2114 return rc; 2115 if (resp != FW_MSG_CODE_OK) { 2116 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 2117 "MFW lacks support for command; Returns %08x\n", 2118 resp); 2119 return -EINVAL; 2120 } 2121 2122 switch (param) { 2123 case FW_MB_PARAM_GET_PF_RDMA_NONE: 2124 *p_proto = QED_PCI_ETH; 2125 break; 2126 case FW_MB_PARAM_GET_PF_RDMA_ROCE: 2127 *p_proto = QED_PCI_ETH_ROCE; 2128 break; 2129 case FW_MB_PARAM_GET_PF_RDMA_IWARP: 2130 *p_proto = QED_PCI_ETH_IWARP; 2131 break; 2132 case FW_MB_PARAM_GET_PF_RDMA_BOTH: 2133 *p_proto = QED_PCI_ETH_RDMA; 2134 break; 2135 default: 2136 DP_NOTICE(p_hwfn, 2137 "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 2138 param); 2139 return -EINVAL; 2140 } 2141 2142 DP_VERBOSE(p_hwfn, 2143 NETIF_MSG_IFUP, 2144 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 2145 (u32) *p_proto, resp, param); 2146 return 0; 2147 } 2148 2149 static int 2150 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 2151 struct public_func *p_info, 2152 struct qed_ptt *p_ptt, 2153 enum qed_pci_personality *p_proto) 2154 { 2155 int rc = 0; 2156 2157 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 2158 case FUNC_MF_CFG_PROTOCOL_ETHERNET: 2159 if (!IS_ENABLED(CONFIG_QED_RDMA)) 2160 *p_proto = QED_PCI_ETH; 2161 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 2162 qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 2163 break; 2164 case FUNC_MF_CFG_PROTOCOL_ISCSI: 2165 *p_proto = QED_PCI_ISCSI; 2166 break; 2167 case FUNC_MF_CFG_PROTOCOL_FCOE: 2168 *p_proto = QED_PCI_FCOE; 2169 break; 2170 case FUNC_MF_CFG_PROTOCOL_ROCE: 2171 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 2172 /* Fallthrough */ 2173 default: 2174 rc = -EINVAL; 2175 } 2176 2177 return rc; 2178 } 2179 2180 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 2181 struct qed_ptt *p_ptt) 2182 { 2183 struct qed_mcp_function_info *info; 2184 struct public_func shmem_info; 2185 2186 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 2187 info = &p_hwfn->mcp_info->func_info; 2188 2189 info->pause_on_host = (shmem_info.config & 2190 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 2191 2192 if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 2193 &info->protocol)) { 2194 DP_ERR(p_hwfn, "Unknown personality %08x\n", 2195 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 2196 return -EINVAL; 2197 } 2198 2199 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 2200 2201 if (shmem_info.mac_upper || shmem_info.mac_lower) { 2202 info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 2203 info->mac[1] = (u8)(shmem_info.mac_upper); 2204 info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 2205 info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 2206 info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 2207 info->mac[5] = (u8)(shmem_info.mac_lower); 2208 2209 /* Store primary MAC for later possible WoL */ 2210 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 2211 } else { 2212 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 2213 } 2214 2215 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 2216 (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 2217 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 2218 (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 2219 2220 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 2221 2222 info->mtu = (u16)shmem_info.mtu_size; 2223 2224 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 2225 p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 2226 if (qed_mcp_is_init(p_hwfn)) { 2227 u32 resp = 0, param = 0; 2228 int rc; 2229 2230 rc = qed_mcp_cmd(p_hwfn, p_ptt, 2231 DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 2232 if (rc) 2233 return rc; 2234 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 2235 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 2236 } 2237 2238 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 2239 "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 2240 info->pause_on_host, info->protocol, 2241 info->bandwidth_min, info->bandwidth_max, 2242 info->mac[0], info->mac[1], info->mac[2], 2243 info->mac[3], info->mac[4], info->mac[5], 2244 info->wwn_port, info->wwn_node, 2245 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 2246 2247 return 0; 2248 } 2249 2250 struct qed_mcp_link_params 2251 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 2252 { 2253 if (!p_hwfn || !p_hwfn->mcp_info) 2254 return NULL; 2255 return &p_hwfn->mcp_info->link_input; 2256 } 2257 2258 struct qed_mcp_link_state 2259 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 2260 { 2261 if (!p_hwfn || !p_hwfn->mcp_info) 2262 return NULL; 2263 return &p_hwfn->mcp_info->link_output; 2264 } 2265 2266 struct qed_mcp_link_capabilities 2267 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 2268 { 2269 if (!p_hwfn || !p_hwfn->mcp_info) 2270 return NULL; 2271 return &p_hwfn->mcp_info->link_capabilities; 2272 } 2273 2274 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2275 { 2276 u32 resp = 0, param = 0; 2277 int rc; 2278 2279 rc = qed_mcp_cmd(p_hwfn, p_ptt, 2280 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 2281 2282 /* Wait for the drain to complete before returning */ 2283 msleep(1020); 2284 2285 return rc; 2286 } 2287 2288 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 2289 struct qed_ptt *p_ptt, u32 *p_flash_size) 2290 { 2291 u32 flash_size; 2292 2293 if (IS_VF(p_hwfn->cdev)) 2294 return -EINVAL; 2295 2296 flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 2297 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 2298 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 2299 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 2300 2301 *p_flash_size = flash_size; 2302 2303 return 0; 2304 } 2305 2306 static int 2307 qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 2308 struct qed_ptt *p_ptt, u8 vf_id, u8 num) 2309 { 2310 u32 resp = 0, param = 0, rc_param = 0; 2311 int rc; 2312 2313 /* Only Leader can configure MSIX, and need to take CMT into account */ 2314 if (!IS_LEAD_HWFN(p_hwfn)) 2315 return 0; 2316 num *= p_hwfn->cdev->num_hwfns; 2317 2318 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 2319 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 2320 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 2321 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 2322 2323 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 2324 &resp, &rc_param); 2325 2326 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 2327 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 2328 rc = -EINVAL; 2329 } else { 2330 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 2331 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 2332 num, vf_id); 2333 } 2334 2335 return rc; 2336 } 2337 2338 static int 2339 qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 2340 struct qed_ptt *p_ptt, u8 num) 2341 { 2342 u32 resp = 0, param = num, rc_param = 0; 2343 int rc; 2344 2345 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 2346 param, &resp, &rc_param); 2347 2348 if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 2349 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 2350 rc = -EINVAL; 2351 } else { 2352 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 2353 "Requested 0x%02x MSI-x interrupts for VFs\n", num); 2354 } 2355 2356 return rc; 2357 } 2358 2359 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 2360 struct qed_ptt *p_ptt, u8 vf_id, u8 num) 2361 { 2362 if (QED_IS_BB(p_hwfn->cdev)) 2363 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 2364 else 2365 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 2366 } 2367 2368 int 2369 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2370 struct qed_ptt *p_ptt, 2371 struct qed_mcp_drv_version *p_ver) 2372 { 2373 struct qed_mcp_mb_params mb_params; 2374 struct drv_version_stc drv_version; 2375 __be32 val; 2376 u32 i; 2377 int rc; 2378 2379 memset(&drv_version, 0, sizeof(drv_version)); 2380 drv_version.version = p_ver->version; 2381 for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 2382 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 2383 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2384 } 2385 2386 memset(&mb_params, 0, sizeof(mb_params)); 2387 mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 2388 mb_params.p_data_src = &drv_version; 2389 mb_params.data_src_size = sizeof(drv_version); 2390 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 2391 if (rc) 2392 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2393 2394 return rc; 2395 } 2396 2397 /* A maximal 100 msec waiting time for the MCP to halt */ 2398 #define QED_MCP_HALT_SLEEP_MS 10 2399 #define QED_MCP_HALT_MAX_RETRIES 10 2400 2401 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2402 { 2403 u32 resp = 0, param = 0, cpu_state, cnt = 0; 2404 int rc; 2405 2406 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 2407 ¶m); 2408 if (rc) { 2409 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2410 return rc; 2411 } 2412 2413 do { 2414 msleep(QED_MCP_HALT_SLEEP_MS); 2415 cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 2416 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) 2417 break; 2418 } while (++cnt < QED_MCP_HALT_MAX_RETRIES); 2419 2420 if (cnt == QED_MCP_HALT_MAX_RETRIES) { 2421 DP_NOTICE(p_hwfn, 2422 "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 2423 qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state); 2424 return -EBUSY; 2425 } 2426 2427 qed_mcp_cmd_set_blocking(p_hwfn, true); 2428 2429 return 0; 2430 } 2431 2432 #define QED_MCP_RESUME_SLEEP_MS 10 2433 2434 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2435 { 2436 u32 cpu_mode, cpu_state; 2437 2438 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 2439 2440 cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 2441 cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT; 2442 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode); 2443 msleep(QED_MCP_RESUME_SLEEP_MS); 2444 cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 2445 2446 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) { 2447 DP_NOTICE(p_hwfn, 2448 "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 2449 cpu_mode, cpu_state); 2450 return -EBUSY; 2451 } 2452 2453 qed_mcp_cmd_set_blocking(p_hwfn, false); 2454 2455 return 0; 2456 } 2457 2458 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 2459 struct qed_ptt *p_ptt, 2460 enum qed_ov_client client) 2461 { 2462 u32 resp = 0, param = 0; 2463 u32 drv_mb_param; 2464 int rc; 2465 2466 switch (client) { 2467 case QED_OV_CLIENT_DRV: 2468 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 2469 break; 2470 case QED_OV_CLIENT_USER: 2471 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 2472 break; 2473 case QED_OV_CLIENT_VENDOR_SPEC: 2474 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 2475 break; 2476 default: 2477 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 2478 return -EINVAL; 2479 } 2480 2481 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 2482 drv_mb_param, &resp, ¶m); 2483 if (rc) 2484 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2485 2486 return rc; 2487 } 2488 2489 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 2490 struct qed_ptt *p_ptt, 2491 enum qed_ov_driver_state drv_state) 2492 { 2493 u32 resp = 0, param = 0; 2494 u32 drv_mb_param; 2495 int rc; 2496 2497 switch (drv_state) { 2498 case QED_OV_DRIVER_STATE_NOT_LOADED: 2499 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 2500 break; 2501 case QED_OV_DRIVER_STATE_DISABLED: 2502 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 2503 break; 2504 case QED_OV_DRIVER_STATE_ACTIVE: 2505 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 2506 break; 2507 default: 2508 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 2509 return -EINVAL; 2510 } 2511 2512 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 2513 drv_mb_param, &resp, ¶m); 2514 if (rc) 2515 DP_ERR(p_hwfn, "Failed to send driver state\n"); 2516 2517 return rc; 2518 } 2519 2520 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 2521 struct qed_ptt *p_ptt, u16 mtu) 2522 { 2523 u32 resp = 0, param = 0; 2524 u32 drv_mb_param; 2525 int rc; 2526 2527 drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 2528 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 2529 drv_mb_param, &resp, ¶m); 2530 if (rc) 2531 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 2532 2533 return rc; 2534 } 2535 2536 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 2537 struct qed_ptt *p_ptt, u8 *mac) 2538 { 2539 struct qed_mcp_mb_params mb_params; 2540 u32 mfw_mac[2]; 2541 int rc; 2542 2543 memset(&mb_params, 0, sizeof(mb_params)); 2544 mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 2545 mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 2546 DRV_MSG_CODE_VMAC_TYPE_SHIFT; 2547 mb_params.param |= MCP_PF_ID(p_hwfn); 2548 2549 /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 2550 * in 32-bit granularity. 2551 * So the MAC has to be set in native order [and not byte order], 2552 * otherwise it would be read incorrectly by MFW after swap. 2553 */ 2554 mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 2555 mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 2556 2557 mb_params.p_data_src = (u8 *)mfw_mac; 2558 mb_params.data_src_size = 8; 2559 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 2560 if (rc) 2561 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 2562 2563 /* Store primary MAC for later possible WoL */ 2564 memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 2565 2566 return rc; 2567 } 2568 2569 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 2570 struct qed_ptt *p_ptt, enum qed_ov_wol wol) 2571 { 2572 u32 resp = 0, param = 0; 2573 u32 drv_mb_param; 2574 int rc; 2575 2576 if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 2577 DP_VERBOSE(p_hwfn, QED_MSG_SP, 2578 "Can't change WoL configuration when WoL isn't supported\n"); 2579 return -EINVAL; 2580 } 2581 2582 switch (wol) { 2583 case QED_OV_WOL_DEFAULT: 2584 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 2585 break; 2586 case QED_OV_WOL_DISABLED: 2587 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 2588 break; 2589 case QED_OV_WOL_ENABLED: 2590 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 2591 break; 2592 default: 2593 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 2594 return -EINVAL; 2595 } 2596 2597 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 2598 drv_mb_param, &resp, ¶m); 2599 if (rc) 2600 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 2601 2602 /* Store the WoL update for a future unload */ 2603 p_hwfn->cdev->wol_config = (u8)wol; 2604 2605 return rc; 2606 } 2607 2608 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 2609 struct qed_ptt *p_ptt, 2610 enum qed_ov_eswitch eswitch) 2611 { 2612 u32 resp = 0, param = 0; 2613 u32 drv_mb_param; 2614 int rc; 2615 2616 switch (eswitch) { 2617 case QED_OV_ESWITCH_NONE: 2618 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 2619 break; 2620 case QED_OV_ESWITCH_VEB: 2621 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 2622 break; 2623 case QED_OV_ESWITCH_VEPA: 2624 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 2625 break; 2626 default: 2627 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 2628 return -EINVAL; 2629 } 2630 2631 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 2632 drv_mb_param, &resp, ¶m); 2633 if (rc) 2634 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 2635 2636 return rc; 2637 } 2638 2639 int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 2640 struct qed_ptt *p_ptt, enum qed_led_mode mode) 2641 { 2642 u32 resp = 0, param = 0, drv_mb_param; 2643 int rc; 2644 2645 switch (mode) { 2646 case QED_LED_MODE_ON: 2647 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 2648 break; 2649 case QED_LED_MODE_OFF: 2650 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 2651 break; 2652 case QED_LED_MODE_RESTORE: 2653 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 2654 break; 2655 default: 2656 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 2657 return -EINVAL; 2658 } 2659 2660 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 2661 drv_mb_param, &resp, ¶m); 2662 2663 return rc; 2664 } 2665 2666 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 2667 struct qed_ptt *p_ptt, u32 mask_parities) 2668 { 2669 u32 resp = 0, param = 0; 2670 int rc; 2671 2672 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 2673 mask_parities, &resp, ¶m); 2674 2675 if (rc) { 2676 DP_ERR(p_hwfn, 2677 "MCP response failure for mask parities, aborting\n"); 2678 } else if (resp != FW_MSG_CODE_OK) { 2679 DP_ERR(p_hwfn, 2680 "MCP did not acknowledge mask parity request. Old MFW?\n"); 2681 rc = -EINVAL; 2682 } 2683 2684 return rc; 2685 } 2686 2687 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 2688 { 2689 u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 2690 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2691 u32 resp = 0, resp_param = 0; 2692 struct qed_ptt *p_ptt; 2693 int rc = 0; 2694 2695 p_ptt = qed_ptt_acquire(p_hwfn); 2696 if (!p_ptt) 2697 return -EBUSY; 2698 2699 while (bytes_left > 0) { 2700 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 2701 2702 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2703 DRV_MSG_CODE_NVM_READ_NVRAM, 2704 addr + offset + 2705 (bytes_to_copy << 2706 DRV_MB_PARAM_NVM_LEN_OFFSET), 2707 &resp, &resp_param, 2708 &read_len, 2709 (u32 *)(p_buf + offset)); 2710 2711 if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 2712 DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 2713 break; 2714 } 2715 2716 /* This can be a lengthy process, and it's possible scheduler 2717 * isn't preemptable. Sleep a bit to prevent CPU hogging. 2718 */ 2719 if (bytes_left % 0x1000 < 2720 (bytes_left - read_len) % 0x1000) 2721 usleep_range(1000, 2000); 2722 2723 offset += read_len; 2724 bytes_left -= read_len; 2725 } 2726 2727 cdev->mcp_nvm_resp = resp; 2728 qed_ptt_release(p_hwfn, p_ptt); 2729 2730 return rc; 2731 } 2732 2733 int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 2734 { 2735 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2736 struct qed_ptt *p_ptt; 2737 2738 p_ptt = qed_ptt_acquire(p_hwfn); 2739 if (!p_ptt) 2740 return -EBUSY; 2741 2742 memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 2743 qed_ptt_release(p_hwfn, p_ptt); 2744 2745 return 0; 2746 } 2747 2748 int qed_mcp_nvm_write(struct qed_dev *cdev, 2749 u32 cmd, u32 addr, u8 *p_buf, u32 len) 2750 { 2751 u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 2752 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2753 struct qed_ptt *p_ptt; 2754 int rc = -EINVAL; 2755 2756 p_ptt = qed_ptt_acquire(p_hwfn); 2757 if (!p_ptt) 2758 return -EBUSY; 2759 2760 switch (cmd) { 2761 case QED_PUT_FILE_BEGIN: 2762 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN; 2763 break; 2764 case QED_PUT_FILE_DATA: 2765 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 2766 break; 2767 case QED_NVM_WRITE_NVRAM: 2768 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 2769 break; 2770 default: 2771 DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 2772 rc = -EINVAL; 2773 goto out; 2774 } 2775 2776 buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 2777 while (buf_idx < len) { 2778 if (cmd == QED_PUT_FILE_BEGIN) 2779 nvm_offset = addr; 2780 else 2781 nvm_offset = ((buf_size << 2782 DRV_MB_PARAM_NVM_LEN_OFFSET) | addr) + 2783 buf_idx; 2784 rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 2785 &resp, ¶m, buf_size, 2786 (u32 *)&p_buf[buf_idx]); 2787 if (rc) { 2788 DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 2789 resp = FW_MSG_CODE_ERROR; 2790 break; 2791 } 2792 2793 if (resp != FW_MSG_CODE_OK && 2794 resp != FW_MSG_CODE_NVM_OK && 2795 resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 2796 DP_NOTICE(cdev, 2797 "nvm write failed, resp = 0x%08x\n", resp); 2798 rc = -EINVAL; 2799 break; 2800 } 2801 2802 /* This can be a lengthy process, and it's possible scheduler 2803 * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 2804 */ 2805 if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 2806 usleep_range(1000, 2000); 2807 2808 /* For MBI upgrade, MFW response includes the next buffer offset 2809 * to be delivered to MFW. 2810 */ 2811 if (param && cmd == QED_PUT_FILE_DATA) { 2812 buf_idx = QED_MFW_GET_FIELD(param, 2813 FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET); 2814 buf_size = QED_MFW_GET_FIELD(param, 2815 FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE); 2816 } else { 2817 buf_idx += buf_size; 2818 buf_size = min_t(u32, (len - buf_idx), 2819 MCP_DRV_NVM_BUF_LEN); 2820 } 2821 } 2822 2823 cdev->mcp_nvm_resp = resp; 2824 out: 2825 qed_ptt_release(p_hwfn, p_ptt); 2826 2827 return rc; 2828 } 2829 2830 int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2831 u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 2832 { 2833 u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 2834 u32 resp, param; 2835 int rc; 2836 2837 nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 2838 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 2839 nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 2840 DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 2841 2842 addr = offset; 2843 offset = 0; 2844 bytes_left = len; 2845 while (bytes_left > 0) { 2846 bytes_to_copy = min_t(u32, bytes_left, 2847 MAX_I2C_TRANSACTION_SIZE); 2848 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 2849 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 2850 nvm_offset |= ((addr + offset) << 2851 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 2852 DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 2853 nvm_offset |= (bytes_to_copy << 2854 DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 2855 DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 2856 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2857 DRV_MSG_CODE_TRANSCEIVER_READ, 2858 nvm_offset, &resp, ¶m, &buf_size, 2859 (u32 *)(p_buf + offset)); 2860 if (rc) { 2861 DP_NOTICE(p_hwfn, 2862 "Failed to send a transceiver read command to the MFW. rc = %d.\n", 2863 rc); 2864 return rc; 2865 } 2866 2867 if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 2868 return -ENODEV; 2869 else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 2870 return -EINVAL; 2871 2872 offset += buf_size; 2873 bytes_left -= buf_size; 2874 } 2875 2876 return 0; 2877 } 2878 2879 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2880 { 2881 u32 drv_mb_param = 0, rsp, param; 2882 int rc = 0; 2883 2884 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 2885 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2886 2887 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2888 drv_mb_param, &rsp, ¶m); 2889 2890 if (rc) 2891 return rc; 2892 2893 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2894 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 2895 rc = -EAGAIN; 2896 2897 return rc; 2898 } 2899 2900 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2901 { 2902 u32 drv_mb_param, rsp, param; 2903 int rc = 0; 2904 2905 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 2906 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2907 2908 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2909 drv_mb_param, &rsp, ¶m); 2910 2911 if (rc) 2912 return rc; 2913 2914 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2915 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 2916 rc = -EAGAIN; 2917 2918 return rc; 2919 } 2920 2921 int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 2922 struct qed_ptt *p_ptt, 2923 u32 *num_images) 2924 { 2925 u32 drv_mb_param = 0, rsp; 2926 int rc = 0; 2927 2928 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 2929 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2930 2931 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2932 drv_mb_param, &rsp, num_images); 2933 if (rc) 2934 return rc; 2935 2936 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 2937 rc = -EINVAL; 2938 2939 return rc; 2940 } 2941 2942 int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 2943 struct qed_ptt *p_ptt, 2944 struct bist_nvm_image_att *p_image_att, 2945 u32 image_index) 2946 { 2947 u32 buf_size = 0, param, resp = 0, resp_param = 0; 2948 int rc; 2949 2950 param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 2951 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 2952 param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 2953 2954 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2955 DRV_MSG_CODE_BIST_TEST, param, 2956 &resp, &resp_param, 2957 &buf_size, 2958 (u32 *)p_image_att); 2959 if (rc) 2960 return rc; 2961 2962 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2963 (p_image_att->return_code != 1)) 2964 rc = -EINVAL; 2965 2966 return rc; 2967 } 2968 2969 int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 2970 { 2971 struct qed_nvm_image_info nvm_info; 2972 struct qed_ptt *p_ptt; 2973 int rc; 2974 u32 i; 2975 2976 if (p_hwfn->nvm_info.valid) 2977 return 0; 2978 2979 p_ptt = qed_ptt_acquire(p_hwfn); 2980 if (!p_ptt) { 2981 DP_ERR(p_hwfn, "failed to acquire ptt\n"); 2982 return -EBUSY; 2983 } 2984 2985 /* Acquire from MFW the amount of available images */ 2986 nvm_info.num_images = 0; 2987 rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 2988 p_ptt, &nvm_info.num_images); 2989 if (rc == -EOPNOTSUPP) { 2990 DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 2991 goto out; 2992 } else if (rc || !nvm_info.num_images) { 2993 DP_ERR(p_hwfn, "Failed getting number of images\n"); 2994 goto err0; 2995 } 2996 2997 nvm_info.image_att = kmalloc_array(nvm_info.num_images, 2998 sizeof(struct bist_nvm_image_att), 2999 GFP_KERNEL); 3000 if (!nvm_info.image_att) { 3001 rc = -ENOMEM; 3002 goto err0; 3003 } 3004 3005 /* Iterate over images and get their attributes */ 3006 for (i = 0; i < nvm_info.num_images; i++) { 3007 rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 3008 &nvm_info.image_att[i], i); 3009 if (rc) { 3010 DP_ERR(p_hwfn, 3011 "Failed getting image index %d attributes\n", i); 3012 goto err1; 3013 } 3014 3015 DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 3016 nvm_info.image_att[i].len); 3017 } 3018 out: 3019 /* Update hwfn's nvm_info */ 3020 if (nvm_info.num_images) { 3021 p_hwfn->nvm_info.num_images = nvm_info.num_images; 3022 kfree(p_hwfn->nvm_info.image_att); 3023 p_hwfn->nvm_info.image_att = nvm_info.image_att; 3024 p_hwfn->nvm_info.valid = true; 3025 } 3026 3027 qed_ptt_release(p_hwfn, p_ptt); 3028 return 0; 3029 3030 err1: 3031 kfree(nvm_info.image_att); 3032 err0: 3033 qed_ptt_release(p_hwfn, p_ptt); 3034 return rc; 3035 } 3036 3037 int 3038 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 3039 enum qed_nvm_images image_id, 3040 struct qed_nvm_image_att *p_image_att) 3041 { 3042 enum nvm_image_type type; 3043 u32 i; 3044 3045 /* Translate image_id into MFW definitions */ 3046 switch (image_id) { 3047 case QED_NVM_IMAGE_ISCSI_CFG: 3048 type = NVM_TYPE_ISCSI_CFG; 3049 break; 3050 case QED_NVM_IMAGE_FCOE_CFG: 3051 type = NVM_TYPE_FCOE_CFG; 3052 break; 3053 case QED_NVM_IMAGE_NVM_CFG1: 3054 type = NVM_TYPE_NVM_CFG1; 3055 break; 3056 case QED_NVM_IMAGE_DEFAULT_CFG: 3057 type = NVM_TYPE_DEFAULT_CFG; 3058 break; 3059 case QED_NVM_IMAGE_NVM_META: 3060 type = NVM_TYPE_META; 3061 break; 3062 default: 3063 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 3064 image_id); 3065 return -EINVAL; 3066 } 3067 3068 qed_mcp_nvm_info_populate(p_hwfn); 3069 for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 3070 if (type == p_hwfn->nvm_info.image_att[i].image_type) 3071 break; 3072 if (i == p_hwfn->nvm_info.num_images) { 3073 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 3074 "Failed to find nvram image of type %08x\n", 3075 image_id); 3076 return -ENOENT; 3077 } 3078 3079 p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 3080 p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 3081 3082 return 0; 3083 } 3084 3085 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 3086 enum qed_nvm_images image_id, 3087 u8 *p_buffer, u32 buffer_len) 3088 { 3089 struct qed_nvm_image_att image_att; 3090 int rc; 3091 3092 memset(p_buffer, 0, buffer_len); 3093 3094 rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 3095 if (rc) 3096 return rc; 3097 3098 /* Validate sizes - both the image's and the supplied buffer's */ 3099 if (image_att.length <= 4) { 3100 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 3101 "Image [%d] is too small - only %d bytes\n", 3102 image_id, image_att.length); 3103 return -EINVAL; 3104 } 3105 3106 if (image_att.length > buffer_len) { 3107 DP_VERBOSE(p_hwfn, 3108 QED_MSG_STORAGE, 3109 "Image [%d] is too big - %08x bytes where only %08x are available\n", 3110 image_id, image_att.length, buffer_len); 3111 return -ENOMEM; 3112 } 3113 3114 return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 3115 p_buffer, image_att.length); 3116 } 3117 3118 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 3119 { 3120 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 3121 3122 switch (res_id) { 3123 case QED_SB: 3124 mfw_res_id = RESOURCE_NUM_SB_E; 3125 break; 3126 case QED_L2_QUEUE: 3127 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 3128 break; 3129 case QED_VPORT: 3130 mfw_res_id = RESOURCE_NUM_VPORT_E; 3131 break; 3132 case QED_RSS_ENG: 3133 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 3134 break; 3135 case QED_PQ: 3136 mfw_res_id = RESOURCE_NUM_PQ_E; 3137 break; 3138 case QED_RL: 3139 mfw_res_id = RESOURCE_NUM_RL_E; 3140 break; 3141 case QED_MAC: 3142 case QED_VLAN: 3143 /* Each VFC resource can accommodate both a MAC and a VLAN */ 3144 mfw_res_id = RESOURCE_VFC_FILTER_E; 3145 break; 3146 case QED_ILT: 3147 mfw_res_id = RESOURCE_ILT_E; 3148 break; 3149 case QED_LL2_QUEUE: 3150 mfw_res_id = RESOURCE_LL2_QUEUE_E; 3151 break; 3152 case QED_RDMA_CNQ_RAM: 3153 case QED_CMDQS_CQS: 3154 /* CNQ/CMDQS are the same resource */ 3155 mfw_res_id = RESOURCE_CQS_E; 3156 break; 3157 case QED_RDMA_STATS_QUEUE: 3158 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 3159 break; 3160 case QED_BDQ: 3161 mfw_res_id = RESOURCE_BDQ_E; 3162 break; 3163 default: 3164 break; 3165 } 3166 3167 return mfw_res_id; 3168 } 3169 3170 #define QED_RESC_ALLOC_VERSION_MAJOR 2 3171 #define QED_RESC_ALLOC_VERSION_MINOR 0 3172 #define QED_RESC_ALLOC_VERSION \ 3173 ((QED_RESC_ALLOC_VERSION_MAJOR << \ 3174 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 3175 (QED_RESC_ALLOC_VERSION_MINOR << \ 3176 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 3177 3178 struct qed_resc_alloc_in_params { 3179 u32 cmd; 3180 enum qed_resources res_id; 3181 u32 resc_max_val; 3182 }; 3183 3184 struct qed_resc_alloc_out_params { 3185 u32 mcp_resp; 3186 u32 mcp_param; 3187 u32 resc_num; 3188 u32 resc_start; 3189 u32 vf_resc_num; 3190 u32 vf_resc_start; 3191 u32 flags; 3192 }; 3193 3194 static int 3195 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 3196 struct qed_ptt *p_ptt, 3197 struct qed_resc_alloc_in_params *p_in_params, 3198 struct qed_resc_alloc_out_params *p_out_params) 3199 { 3200 struct qed_mcp_mb_params mb_params; 3201 struct resource_info mfw_resc_info; 3202 int rc; 3203 3204 memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 3205 3206 mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 3207 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 3208 DP_ERR(p_hwfn, 3209 "Failed to match resource %d [%s] with the MFW resources\n", 3210 p_in_params->res_id, 3211 qed_hw_get_resc_name(p_in_params->res_id)); 3212 return -EINVAL; 3213 } 3214 3215 switch (p_in_params->cmd) { 3216 case DRV_MSG_SET_RESOURCE_VALUE_MSG: 3217 mfw_resc_info.size = p_in_params->resc_max_val; 3218 /* Fallthrough */ 3219 case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 3220 break; 3221 default: 3222 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 3223 p_in_params->cmd); 3224 return -EINVAL; 3225 } 3226 3227 memset(&mb_params, 0, sizeof(mb_params)); 3228 mb_params.cmd = p_in_params->cmd; 3229 mb_params.param = QED_RESC_ALLOC_VERSION; 3230 mb_params.p_data_src = &mfw_resc_info; 3231 mb_params.data_src_size = sizeof(mfw_resc_info); 3232 mb_params.p_data_dst = mb_params.p_data_src; 3233 mb_params.data_dst_size = mb_params.data_src_size; 3234 3235 DP_VERBOSE(p_hwfn, 3236 QED_MSG_SP, 3237 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 3238 p_in_params->cmd, 3239 p_in_params->res_id, 3240 qed_hw_get_resc_name(p_in_params->res_id), 3241 QED_MFW_GET_FIELD(mb_params.param, 3242 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 3243 QED_MFW_GET_FIELD(mb_params.param, 3244 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 3245 p_in_params->resc_max_val); 3246 3247 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 3248 if (rc) 3249 return rc; 3250 3251 p_out_params->mcp_resp = mb_params.mcp_resp; 3252 p_out_params->mcp_param = mb_params.mcp_param; 3253 p_out_params->resc_num = mfw_resc_info.size; 3254 p_out_params->resc_start = mfw_resc_info.offset; 3255 p_out_params->vf_resc_num = mfw_resc_info.vf_size; 3256 p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 3257 p_out_params->flags = mfw_resc_info.flags; 3258 3259 DP_VERBOSE(p_hwfn, 3260 QED_MSG_SP, 3261 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 3262 QED_MFW_GET_FIELD(p_out_params->mcp_param, 3263 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 3264 QED_MFW_GET_FIELD(p_out_params->mcp_param, 3265 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 3266 p_out_params->resc_num, 3267 p_out_params->resc_start, 3268 p_out_params->vf_resc_num, 3269 p_out_params->vf_resc_start, p_out_params->flags); 3270 3271 return 0; 3272 } 3273 3274 int 3275 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 3276 struct qed_ptt *p_ptt, 3277 enum qed_resources res_id, 3278 u32 resc_max_val, u32 *p_mcp_resp) 3279 { 3280 struct qed_resc_alloc_out_params out_params; 3281 struct qed_resc_alloc_in_params in_params; 3282 int rc; 3283 3284 memset(&in_params, 0, sizeof(in_params)); 3285 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 3286 in_params.res_id = res_id; 3287 in_params.resc_max_val = resc_max_val; 3288 memset(&out_params, 0, sizeof(out_params)); 3289 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 3290 &out_params); 3291 if (rc) 3292 return rc; 3293 3294 *p_mcp_resp = out_params.mcp_resp; 3295 3296 return 0; 3297 } 3298 3299 int 3300 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 3301 struct qed_ptt *p_ptt, 3302 enum qed_resources res_id, 3303 u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 3304 { 3305 struct qed_resc_alloc_out_params out_params; 3306 struct qed_resc_alloc_in_params in_params; 3307 int rc; 3308 3309 memset(&in_params, 0, sizeof(in_params)); 3310 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 3311 in_params.res_id = res_id; 3312 memset(&out_params, 0, sizeof(out_params)); 3313 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 3314 &out_params); 3315 if (rc) 3316 return rc; 3317 3318 *p_mcp_resp = out_params.mcp_resp; 3319 3320 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 3321 *p_resc_num = out_params.resc_num; 3322 *p_resc_start = out_params.resc_start; 3323 } 3324 3325 return 0; 3326 } 3327 3328 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3329 { 3330 u32 mcp_resp, mcp_param; 3331 3332 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 3333 &mcp_resp, &mcp_param); 3334 } 3335 3336 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 3337 struct qed_ptt *p_ptt, 3338 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 3339 { 3340 int rc; 3341 3342 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 3343 p_mcp_resp, p_mcp_param); 3344 if (rc) 3345 return rc; 3346 3347 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 3348 DP_INFO(p_hwfn, 3349 "The resource command is unsupported by the MFW\n"); 3350 return -EINVAL; 3351 } 3352 3353 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 3354 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 3355 3356 DP_NOTICE(p_hwfn, 3357 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 3358 param, opcode); 3359 return -EINVAL; 3360 } 3361 3362 return rc; 3363 } 3364 3365 static int 3366 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 3367 struct qed_ptt *p_ptt, 3368 struct qed_resc_lock_params *p_params) 3369 { 3370 u32 param = 0, mcp_resp, mcp_param; 3371 u8 opcode; 3372 int rc; 3373 3374 switch (p_params->timeout) { 3375 case QED_MCP_RESC_LOCK_TO_DEFAULT: 3376 opcode = RESOURCE_OPCODE_REQ; 3377 p_params->timeout = 0; 3378 break; 3379 case QED_MCP_RESC_LOCK_TO_NONE: 3380 opcode = RESOURCE_OPCODE_REQ_WO_AGING; 3381 p_params->timeout = 0; 3382 break; 3383 default: 3384 opcode = RESOURCE_OPCODE_REQ_W_AGING; 3385 break; 3386 } 3387 3388 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 3389 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 3390 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 3391 3392 DP_VERBOSE(p_hwfn, 3393 QED_MSG_SP, 3394 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 3395 param, p_params->timeout, opcode, p_params->resource); 3396 3397 /* Attempt to acquire the resource */ 3398 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 3399 if (rc) 3400 return rc; 3401 3402 /* Analyze the response */ 3403 p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 3404 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 3405 3406 DP_VERBOSE(p_hwfn, 3407 QED_MSG_SP, 3408 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 3409 mcp_param, opcode, p_params->owner); 3410 3411 switch (opcode) { 3412 case RESOURCE_OPCODE_GNT: 3413 p_params->b_granted = true; 3414 break; 3415 case RESOURCE_OPCODE_BUSY: 3416 p_params->b_granted = false; 3417 break; 3418 default: 3419 DP_NOTICE(p_hwfn, 3420 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 3421 mcp_param, opcode); 3422 return -EINVAL; 3423 } 3424 3425 return 0; 3426 } 3427 3428 int 3429 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 3430 struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 3431 { 3432 u32 retry_cnt = 0; 3433 int rc; 3434 3435 do { 3436 /* No need for an interval before the first iteration */ 3437 if (retry_cnt) { 3438 if (p_params->sleep_b4_retry) { 3439 u16 retry_interval_in_ms = 3440 DIV_ROUND_UP(p_params->retry_interval, 3441 1000); 3442 3443 msleep(retry_interval_in_ms); 3444 } else { 3445 udelay(p_params->retry_interval); 3446 } 3447 } 3448 3449 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 3450 if (rc) 3451 return rc; 3452 3453 if (p_params->b_granted) 3454 break; 3455 } while (retry_cnt++ < p_params->retry_num); 3456 3457 return 0; 3458 } 3459 3460 int 3461 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 3462 struct qed_ptt *p_ptt, 3463 struct qed_resc_unlock_params *p_params) 3464 { 3465 u32 param = 0, mcp_resp, mcp_param; 3466 u8 opcode; 3467 int rc; 3468 3469 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 3470 : RESOURCE_OPCODE_RELEASE; 3471 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 3472 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 3473 3474 DP_VERBOSE(p_hwfn, QED_MSG_SP, 3475 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 3476 param, opcode, p_params->resource); 3477 3478 /* Attempt to release the resource */ 3479 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 3480 if (rc) 3481 return rc; 3482 3483 /* Analyze the response */ 3484 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 3485 3486 DP_VERBOSE(p_hwfn, QED_MSG_SP, 3487 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 3488 mcp_param, opcode); 3489 3490 switch (opcode) { 3491 case RESOURCE_OPCODE_RELEASED_PREVIOUS: 3492 DP_INFO(p_hwfn, 3493 "Resource unlock request for an already released resource [%d]\n", 3494 p_params->resource); 3495 /* Fallthrough */ 3496 case RESOURCE_OPCODE_RELEASED: 3497 p_params->b_released = true; 3498 break; 3499 case RESOURCE_OPCODE_WRONG_OWNER: 3500 p_params->b_released = false; 3501 break; 3502 default: 3503 DP_NOTICE(p_hwfn, 3504 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 3505 mcp_param, opcode); 3506 return -EINVAL; 3507 } 3508 3509 return 0; 3510 } 3511 3512 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3513 struct qed_resc_unlock_params *p_unlock, 3514 enum qed_resc_lock 3515 resource, bool b_is_permanent) 3516 { 3517 if (p_lock) { 3518 memset(p_lock, 0, sizeof(*p_lock)); 3519 3520 /* Permanent resources don't require aging, and there's no 3521 * point in trying to acquire them more than once since it's 3522 * unexpected another entity would release them. 3523 */ 3524 if (b_is_permanent) { 3525 p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3526 } else { 3527 p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3528 p_lock->retry_interval = 3529 QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3530 p_lock->sleep_b4_retry = true; 3531 } 3532 3533 p_lock->resource = resource; 3534 } 3535 3536 if (p_unlock) { 3537 memset(p_unlock, 0, sizeof(*p_unlock)); 3538 p_unlock->resource = resource; 3539 } 3540 } 3541 3542 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3543 { 3544 u32 mcp_resp; 3545 int rc; 3546 3547 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3548 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3549 if (!rc) 3550 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3551 "MFW supported features: %08x\n", 3552 p_hwfn->mcp_info->capabilities); 3553 3554 return rc; 3555 } 3556 3557 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3558 { 3559 u32 mcp_resp, mcp_param, features; 3560 3561 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE | 3562 DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK; 3563 3564 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3565 features, &mcp_resp, &mcp_param); 3566 } 3567