11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5fe56b9e6SYuval Mintz */ 6fe56b9e6SYuval Mintz 7fe56b9e6SYuval Mintz #include <linux/types.h> 8fe56b9e6SYuval Mintz #include <asm/byteorder.h> 9fe56b9e6SYuval Mintz #include <linux/delay.h> 10fe56b9e6SYuval Mintz #include <linux/errno.h> 11fe56b9e6SYuval Mintz #include <linux/kernel.h> 12fe56b9e6SYuval Mintz #include <linux/slab.h> 135529bad9STomer Tayar #include <linux/spinlock.h> 14fe56b9e6SYuval Mintz #include <linux/string.h> 150fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 16fe56b9e6SYuval Mintz #include "qed.h" 17cac6f691SSudarsana Reddy Kalluru #include "qed_cxt.h" 1839651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 19fe56b9e6SYuval Mintz #include "qed_hsi.h" 20ee824f4bSOmkar Kulkarni #include "qed_mfw_hsi.h" 21fe56b9e6SYuval Mintz #include "qed_hw.h" 22fe56b9e6SYuval Mintz #include "qed_mcp.h" 23fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 241408cc1fSYuval Mintz #include "qed_sriov.h" 251408cc1fSYuval Mintz 260500a70dSMichal Kalderon #define GRCBASE_MCP 0xe00000 270500a70dSMichal Kalderon 28eaa50fc5STomer Tayar #define QED_MCP_RESP_ITER_US 10 29fe56b9e6SYuval Mintz 30fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 31fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 346c95dd8fSPrabhakar Kushwaha qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + (_offset)), \ 35fe56b9e6SYuval Mintz _val) 36fe56b9e6SYuval Mintz 37fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 386c95dd8fSPrabhakar Kushwaha qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + (_offset))) 39fe56b9e6SYuval Mintz 40fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 41fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 42fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 43fe56b9e6SYuval Mintz 44fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 45fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 46fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 47fe56b9e6SYuval Mintz 48fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 49fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 50fe56b9e6SYuval Mintz 51fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 52fe56b9e6SYuval Mintz 53fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 54fe56b9e6SYuval Mintz { 55fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 56fe56b9e6SYuval Mintz return false; 57fe56b9e6SYuval Mintz return true; 58fe56b9e6SYuval Mintz } 59fe56b9e6SYuval Mintz 601a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 61fe56b9e6SYuval Mintz { 62fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 63fe56b9e6SYuval Mintz PUBLIC_PORT); 64fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 67fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 68fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 69fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 70fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 71fe56b9e6SYuval Mintz } 72fe56b9e6SYuval Mintz 731a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 74fe56b9e6SYuval Mintz { 75fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 76fe56b9e6SYuval Mintz u32 tmp, i; 77fe56b9e6SYuval Mintz 78fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 79fe56b9e6SYuval Mintz return; 80fe56b9e6SYuval Mintz 81fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 82fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 83fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 84fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 85fe56b9e6SYuval Mintz 86fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 87fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 88fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 89fe56b9e6SYuval Mintz } 90fe56b9e6SYuval Mintz } 91fe56b9e6SYuval Mintz 924ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 934ed1eea8STomer Tayar struct list_head list; 944ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 954ed1eea8STomer Tayar u16 expected_seq_num; 964ed1eea8STomer Tayar bool b_is_completed; 974ed1eea8STomer Tayar }; 984ed1eea8STomer Tayar 994ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1004ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1014ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1024ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1034ed1eea8STomer Tayar u16 expected_seq_num) 1044ed1eea8STomer Tayar { 1054ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1064ed1eea8STomer Tayar 1074ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1084ed1eea8STomer Tayar if (!p_cmd_elem) 1094ed1eea8STomer Tayar goto out; 1104ed1eea8STomer Tayar 1114ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1124ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1134ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1144ed1eea8STomer Tayar out: 1154ed1eea8STomer Tayar return p_cmd_elem; 1164ed1eea8STomer Tayar } 1174ed1eea8STomer Tayar 1184ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1194ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1204ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1214ed1eea8STomer Tayar { 1224ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1234ed1eea8STomer Tayar kfree(p_cmd_elem); 1244ed1eea8STomer Tayar } 1254ed1eea8STomer Tayar 1264ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1274ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1284ed1eea8STomer Tayar u16 seq_num) 1294ed1eea8STomer Tayar { 1304ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1314ed1eea8STomer Tayar 1324ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1334ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1344ed1eea8STomer Tayar return p_cmd_elem; 1354ed1eea8STomer Tayar } 1364ed1eea8STomer Tayar 1374ed1eea8STomer Tayar return NULL; 1384ed1eea8STomer Tayar } 1394ed1eea8STomer Tayar 140fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 141fe56b9e6SYuval Mintz { 142fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1434ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1444ed1eea8STomer Tayar 145fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 146fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1474ed1eea8STomer Tayar 1484ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1494ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1504ed1eea8STomer Tayar p_tmp, 1514ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1524ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 153fe56b9e6SYuval Mintz } 1544ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1554ed1eea8STomer Tayar } 1564ed1eea8STomer Tayar 157fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 1583587cb87STomer Tayar p_hwfn->mcp_info = NULL; 159fe56b9e6SYuval Mintz 160fe56b9e6SYuval Mintz return 0; 161fe56b9e6SYuval Mintz } 162fe56b9e6SYuval Mintz 163f00d25f3STomer Tayar /* Maximum of 1 sec to wait for the SHMEM ready indication */ 164f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_MAX_RETRIES 20 165f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_ITER_MS 50 166f00d25f3STomer Tayar 1671a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 168fe56b9e6SYuval Mintz { 169fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 170f00d25f3STomer Tayar u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES; 171f00d25f3STomer Tayar u8 msec = QED_MCP_SHMEM_RDY_ITER_MS; 172fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 173fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 174fe56b9e6SYuval Mintz 175fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 176f00d25f3STomer Tayar if (!p_info->public_base) { 177f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 178f00d25f3STomer Tayar "The address of the MCP scratch-pad is not configured\n"); 179f00d25f3STomer Tayar return -EINVAL; 180f00d25f3STomer Tayar } 181fe56b9e6SYuval Mintz 182fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 183fe56b9e6SYuval Mintz 184f00d25f3STomer Tayar /* Get the MFW MB address and number of supported messages */ 185f00d25f3STomer Tayar mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 186f00d25f3STomer Tayar SECTION_OFFSIZE_ADDR(p_info->public_base, 187f00d25f3STomer Tayar PUBLIC_MFW_MB)); 188f00d25f3STomer Tayar p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 189f00d25f3STomer Tayar p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, 190f00d25f3STomer Tayar p_info->mfw_mb_addr + 191f00d25f3STomer Tayar offsetof(struct public_mfw_mb, 192f00d25f3STomer Tayar sup_msgs)); 193f00d25f3STomer Tayar 194f00d25f3STomer Tayar /* The driver can notify that there was an MCP reset, and might read the 195f00d25f3STomer Tayar * SHMEM values before the MFW has completed initializing them. 196f00d25f3STomer Tayar * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a 197f00d25f3STomer Tayar * data ready indication. 198f00d25f3STomer Tayar */ 199f00d25f3STomer Tayar while (!p_info->mfw_mb_length && --cnt) { 200f00d25f3STomer Tayar msleep(msec); 201f00d25f3STomer Tayar p_info->mfw_mb_length = 202f00d25f3STomer Tayar (u16)qed_rd(p_hwfn, p_ptt, 203f00d25f3STomer Tayar p_info->mfw_mb_addr + 204f00d25f3STomer Tayar offsetof(struct public_mfw_mb, sup_msgs)); 205f00d25f3STomer Tayar } 206f00d25f3STomer Tayar 207f00d25f3STomer Tayar if (!cnt) { 208f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 209f00d25f3STomer Tayar "Failed to get the SHMEM ready notification after %d msec\n", 210f00d25f3STomer Tayar QED_MCP_SHMEM_RDY_MAX_RETRIES * msec); 211f00d25f3STomer Tayar return -EBUSY; 212f00d25f3STomer Tayar } 213f00d25f3STomer Tayar 214fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 215fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 216fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 217fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 218fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 219fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 220fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 221fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 222fe56b9e6SYuval Mintz 223fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 224fe56b9e6SYuval Mintz * the first command 225fe56b9e6SYuval Mintz */ 226fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 227fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 228fe56b9e6SYuval Mintz 229fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 230fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 231fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 232fe56b9e6SYuval Mintz 2334ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 234fe56b9e6SYuval Mintz 235fe56b9e6SYuval Mintz return 0; 236fe56b9e6SYuval Mintz } 237fe56b9e6SYuval Mintz 2381a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 239fe56b9e6SYuval Mintz { 240fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 241fe56b9e6SYuval Mintz u32 size; 242fe56b9e6SYuval Mintz 243fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 24460fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 245fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 246fe56b9e6SYuval Mintz goto err; 247fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 248fe56b9e6SYuval Mintz 2494ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2504ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2514ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2524ed1eea8STomer Tayar 2534ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2544ed1eea8STomer Tayar 255fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 256fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 257fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 258fe56b9e6SYuval Mintz * the MCP is not initialized 259fe56b9e6SYuval Mintz */ 260fe56b9e6SYuval Mintz return 0; 261fe56b9e6SYuval Mintz } 262fe56b9e6SYuval Mintz 263fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 26460fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 26583aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 266eb2a6b80SChristophe Jaillet if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 267fe56b9e6SYuval Mintz goto err; 268fe56b9e6SYuval Mintz 269fe56b9e6SYuval Mintz return 0; 270fe56b9e6SYuval Mintz 271fe56b9e6SYuval Mintz err: 272fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 273fe56b9e6SYuval Mintz return -ENOMEM; 274fe56b9e6SYuval Mintz } 275fe56b9e6SYuval Mintz 2764ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 2774ed1eea8STomer Tayar struct qed_ptt *p_ptt) 2785529bad9STomer Tayar { 2794ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 2805529bad9STomer Tayar 2814ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 2824ed1eea8STomer Tayar * time and now. 2835529bad9STomer Tayar */ 2844ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 2854ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 2864ed1eea8STomer Tayar QED_MSG_SP, 2874ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 2884ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 2895529bad9STomer Tayar 2904ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 2914ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2925529bad9STomer Tayar } 2935529bad9STomer Tayar } 2945529bad9STomer Tayar 2951a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 296fe56b9e6SYuval Mintz { 297eaa50fc5STomer Tayar u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0; 298fe56b9e6SYuval Mintz int rc = 0; 299fe56b9e6SYuval Mintz 300b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 301b310974eSTomer Tayar DP_NOTICE(p_hwfn, 302b310974eSTomer Tayar "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n"); 303b310974eSTomer Tayar return -EBUSY; 304b310974eSTomer Tayar } 305b310974eSTomer Tayar 3064ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 3074ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 3084ed1eea8STomer Tayar 3094ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3105529bad9STomer Tayar 311fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 3124ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 3134ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 3144ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 315fe56b9e6SYuval Mintz 316fe56b9e6SYuval Mintz do { 317fe56b9e6SYuval Mintz /* Wait for MFW response */ 318fe56b9e6SYuval Mintz udelay(delay); 319fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 320fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 321fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 322fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 323fe56b9e6SYuval Mintz 324fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 325fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 326fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 327fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 328fe56b9e6SYuval Mintz } else { 329fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 330fe56b9e6SYuval Mintz rc = -EAGAIN; 331fe56b9e6SYuval Mintz } 332fe56b9e6SYuval Mintz 3334ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3345529bad9STomer Tayar 335fe56b9e6SYuval Mintz return rc; 336fe56b9e6SYuval Mintz } 337fe56b9e6SYuval Mintz 3384ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3394ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 340fe56b9e6SYuval Mintz { 3414ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3424ed1eea8STomer Tayar 3434ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3444ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3454ed1eea8STomer Tayar */ 3464ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3474ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3484ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3494ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3504ed1eea8STomer Tayar } 3514ed1eea8STomer Tayar 3524ed1eea8STomer Tayar return false; 3534ed1eea8STomer Tayar } 3544ed1eea8STomer Tayar 3554ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3564ed1eea8STomer Tayar static int 3574ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3584ed1eea8STomer Tayar { 3594ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3604ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3614ed1eea8STomer Tayar u32 mcp_resp; 3624ed1eea8STomer Tayar u16 seq_num; 3634ed1eea8STomer Tayar 3644ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3654ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3664ed1eea8STomer Tayar 3674ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3684ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3694ed1eea8STomer Tayar return -EAGAIN; 3704ed1eea8STomer Tayar 3714ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3724ed1eea8STomer Tayar if (!p_cmd_elem) { 3734ed1eea8STomer Tayar DP_ERR(p_hwfn, 3744ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 3754ed1eea8STomer Tayar seq_num); 3764ed1eea8STomer Tayar return -EINVAL; 3774ed1eea8STomer Tayar } 3784ed1eea8STomer Tayar 3794ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 3804ed1eea8STomer Tayar 3814ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 3824ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 3834ed1eea8STomer Tayar 3844ed1eea8STomer Tayar /* Get the MFW param */ 3854ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 3864ed1eea8STomer Tayar 3874ed1eea8STomer Tayar /* Get the union data */ 3886c95dd8fSPrabhakar Kushwaha if (p_mb_params->p_data_dst && p_mb_params->data_dst_size) { 3894ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3904ed1eea8STomer Tayar offsetof(struct public_drv_mb, 3914ed1eea8STomer Tayar union_data); 3924ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 3932f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 3944ed1eea8STomer Tayar } 3954ed1eea8STomer Tayar 3964ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 3974ed1eea8STomer Tayar 3984ed1eea8STomer Tayar return 0; 3994ed1eea8STomer Tayar } 4004ed1eea8STomer Tayar 4014ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 4024ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4034ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4044ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4054ed1eea8STomer Tayar u16 seq_num) 4064ed1eea8STomer Tayar { 4074ed1eea8STomer Tayar union drv_union_data union_data; 4084ed1eea8STomer Tayar u32 union_data_addr; 4094ed1eea8STomer Tayar 4104ed1eea8STomer Tayar /* Set the union data */ 4114ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4124ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 4134ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 4146c95dd8fSPrabhakar Kushwaha if (p_mb_params->p_data_src && p_mb_params->data_src_size) 4154ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 4162f67af8cSTomer Tayar p_mb_params->data_src_size); 4174ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4184ed1eea8STomer Tayar sizeof(union_data)); 4194ed1eea8STomer Tayar 4204ed1eea8STomer Tayar /* Set the drv param */ 4214ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4224ed1eea8STomer Tayar 4234ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4244ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4254ed1eea8STomer Tayar 4264ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4274ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4284ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4294ed1eea8STomer Tayar } 4304ed1eea8STomer Tayar 431b310974eSTomer Tayar static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd) 432b310974eSTomer Tayar { 433b310974eSTomer Tayar p_hwfn->mcp_info->b_block_cmd = block_cmd; 434b310974eSTomer Tayar 435b310974eSTomer Tayar DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n", 436b310974eSTomer Tayar block_cmd ? "Block" : "Unblock"); 437b310974eSTomer Tayar } 438b310974eSTomer Tayar 439b310974eSTomer Tayar static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn, 440b310974eSTomer Tayar struct qed_ptt *p_ptt) 441b310974eSTomer Tayar { 442b310974eSTomer Tayar u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2; 443b310974eSTomer Tayar u32 delay = QED_MCP_RESP_ITER_US; 444b310974eSTomer Tayar 445b310974eSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 446b310974eSTomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 447b310974eSTomer Tayar cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 448b310974eSTomer Tayar udelay(delay); 449b310974eSTomer Tayar cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 450b310974eSTomer Tayar udelay(delay); 451b310974eSTomer Tayar cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 452b310974eSTomer Tayar 453b310974eSTomer Tayar DP_NOTICE(p_hwfn, 454b310974eSTomer Tayar "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n", 455b310974eSTomer Tayar cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2); 456b310974eSTomer Tayar } 457b310974eSTomer Tayar 4584ed1eea8STomer Tayar static int 4594ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4604ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4614ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 462eaa50fc5STomer Tayar u32 max_retries, u32 usecs) 4634ed1eea8STomer Tayar { 464eaa50fc5STomer Tayar u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000); 4654ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4664ed1eea8STomer Tayar u16 seq_num; 467fe56b9e6SYuval Mintz int rc = 0; 468fe56b9e6SYuval Mintz 4694ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 470fe56b9e6SYuval Mintz do { 4714ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4724ed1eea8STomer Tayar * pending command is completed during this iteration. 4734ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4744ed1eea8STomer Tayar */ 4754ed1eea8STomer Tayar 4764ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4774ed1eea8STomer Tayar 4784ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 4794ed1eea8STomer Tayar break; 4804ed1eea8STomer Tayar 4814ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 4824ed1eea8STomer Tayar if (!rc) 4834ed1eea8STomer Tayar break; 4844ed1eea8STomer Tayar else if (rc != -EAGAIN) 4854ed1eea8STomer Tayar goto err; 4864ed1eea8STomer Tayar 4874ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 488eaa50fc5STomer Tayar 489eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 490eaa50fc5STomer Tayar msleep(msecs); 491eaa50fc5STomer Tayar else 492eaa50fc5STomer Tayar udelay(usecs); 4934ed1eea8STomer Tayar } while (++cnt < max_retries); 494fe56b9e6SYuval Mintz 4954ed1eea8STomer Tayar if (cnt >= max_retries) { 4964ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 4974ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 4984ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 4994ed1eea8STomer Tayar return -EAGAIN; 500fe56b9e6SYuval Mintz } 5014ed1eea8STomer Tayar 5024ed1eea8STomer Tayar /* Send the mailbox command */ 5034ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 5044ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 5054ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 506c8004600SDan Carpenter if (!p_cmd_elem) { 507c8004600SDan Carpenter rc = -ENOMEM; 5084ed1eea8STomer Tayar goto err; 509c8004600SDan Carpenter } 5104ed1eea8STomer Tayar 5114ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 5124ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5134ed1eea8STomer Tayar 5144ed1eea8STomer Tayar /* Wait for the MFW response */ 5154ed1eea8STomer Tayar do { 5164ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 5174ed1eea8STomer Tayar * command is completed during this iteration. 5184ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 5194ed1eea8STomer Tayar */ 5204ed1eea8STomer Tayar 521eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 522eaa50fc5STomer Tayar msleep(msecs); 523eaa50fc5STomer Tayar else 524eaa50fc5STomer Tayar udelay(usecs); 525eaa50fc5STomer Tayar 5264ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5274ed1eea8STomer Tayar 5284ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 5294ed1eea8STomer Tayar break; 5304ed1eea8STomer Tayar 5314ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5324ed1eea8STomer Tayar if (!rc) 5334ed1eea8STomer Tayar break; 5344ed1eea8STomer Tayar else if (rc != -EAGAIN) 5354ed1eea8STomer Tayar goto err; 5364ed1eea8STomer Tayar 5374ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5384ed1eea8STomer Tayar } while (++cnt < max_retries); 5394ed1eea8STomer Tayar 5404ed1eea8STomer Tayar if (cnt >= max_retries) { 5414ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5424ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 5434ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 544b310974eSTomer Tayar qed_mcp_print_cpu_info(p_hwfn, p_ptt); 5454ed1eea8STomer Tayar 5464ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5474ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5484ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5494ed1eea8STomer Tayar 550b310974eSTomer Tayar if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK)) 551b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 552b310974eSTomer Tayar 5532ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, 5542ec276d5SIgor Russkikh QED_HW_ERR_MFW_RESP_FAIL, NULL); 5554ed1eea8STomer Tayar return -EAGAIN; 5564ed1eea8STomer Tayar } 5574ed1eea8STomer Tayar 5584ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5594ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5604ed1eea8STomer Tayar 5614ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5624ed1eea8STomer Tayar QED_MSG_SP, 5634ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5644ed1eea8STomer Tayar p_mb_params->mcp_resp, 5654ed1eea8STomer Tayar p_mb_params->mcp_param, 566eaa50fc5STomer Tayar (cnt * usecs) / 1000, (cnt * usecs) % 1000); 5674ed1eea8STomer Tayar 5684ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5694ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5704ed1eea8STomer Tayar 5714ed1eea8STomer Tayar return 0; 5724ed1eea8STomer Tayar 5734ed1eea8STomer Tayar err: 5744ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 575fe56b9e6SYuval Mintz return rc; 576fe56b9e6SYuval Mintz } 577fe56b9e6SYuval Mintz 5785529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 579fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 5805529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 581fe56b9e6SYuval Mintz { 5822f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 5834ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 584eaa50fc5STomer Tayar u32 usecs = QED_MCP_RESP_ITER_US; 585fe56b9e6SYuval Mintz 586fe56b9e6SYuval Mintz /* MCP not initialized */ 587fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 588fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 589fe56b9e6SYuval Mintz return -EBUSY; 590fe56b9e6SYuval Mintz } 591fe56b9e6SYuval Mintz 592b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 593b310974eSTomer Tayar DP_NOTICE(p_hwfn, 594b310974eSTomer Tayar "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n", 595b310974eSTomer Tayar p_mb_params->cmd, p_mb_params->param); 596b310974eSTomer Tayar return -EBUSY; 597b310974eSTomer Tayar } 598b310974eSTomer Tayar 5992f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 6002f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 6012f67af8cSTomer Tayar DP_ERR(p_hwfn, 6022f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 6032f67af8cSTomer Tayar p_mb_params->data_src_size, 6042f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 6052f67af8cSTomer Tayar return -EINVAL; 6062f67af8cSTomer Tayar } 6072f67af8cSTomer Tayar 608eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) { 609eaa50fc5STomer Tayar max_retries = DIV_ROUND_UP(max_retries, 1000); 610eaa50fc5STomer Tayar usecs *= 1000; 611eaa50fc5STomer Tayar } 612eaa50fc5STomer Tayar 6134ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 614eaa50fc5STomer Tayar usecs); 615fe56b9e6SYuval Mintz } 616fe56b9e6SYuval Mintz 617*ef10bd49SVenkata Sudheer Kumar Bhavaraju static int _qed_mcp_cmd(struct qed_hwfn *p_hwfn, 6185529bad9STomer Tayar struct qed_ptt *p_ptt, 6195529bad9STomer Tayar u32 cmd, 6205529bad9STomer Tayar u32 param, 6215529bad9STomer Tayar u32 *o_mcp_resp, 622*ef10bd49SVenkata Sudheer Kumar Bhavaraju u32 *o_mcp_param, 623*ef10bd49SVenkata Sudheer Kumar Bhavaraju bool can_sleep) 624fe56b9e6SYuval Mintz { 6255529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 6265529bad9STomer Tayar int rc; 627fe56b9e6SYuval Mintz 6285529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6295529bad9STomer Tayar mb_params.cmd = cmd; 6305529bad9STomer Tayar mb_params.param = param; 631*ef10bd49SVenkata Sudheer Kumar Bhavaraju mb_params.flags = can_sleep ? QED_MB_FLAG_CAN_SLEEP : 0; 63214d39648SMintz, Yuval 6335529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6345529bad9STomer Tayar if (rc) 6355529bad9STomer Tayar return rc; 6365529bad9STomer Tayar 6375529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6385529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 6395529bad9STomer Tayar 6405529bad9STomer Tayar return 0; 641fe56b9e6SYuval Mintz } 642fe56b9e6SYuval Mintz 643*ef10bd49SVenkata Sudheer Kumar Bhavaraju int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 644*ef10bd49SVenkata Sudheer Kumar Bhavaraju struct qed_ptt *p_ptt, 645*ef10bd49SVenkata Sudheer Kumar Bhavaraju u32 cmd, 646*ef10bd49SVenkata Sudheer Kumar Bhavaraju u32 param, 647*ef10bd49SVenkata Sudheer Kumar Bhavaraju u32 *o_mcp_resp, 648*ef10bd49SVenkata Sudheer Kumar Bhavaraju u32 *o_mcp_param) 649*ef10bd49SVenkata Sudheer Kumar Bhavaraju { 650*ef10bd49SVenkata Sudheer Kumar Bhavaraju return (_qed_mcp_cmd(p_hwfn, p_ptt, cmd, param, 651*ef10bd49SVenkata Sudheer Kumar Bhavaraju o_mcp_resp, o_mcp_param, true)); 652*ef10bd49SVenkata Sudheer Kumar Bhavaraju } 653*ef10bd49SVenkata Sudheer Kumar Bhavaraju 654*ef10bd49SVenkata Sudheer Kumar Bhavaraju int qed_mcp_cmd_nosleep(struct qed_hwfn *p_hwfn, 655*ef10bd49SVenkata Sudheer Kumar Bhavaraju struct qed_ptt *p_ptt, 656*ef10bd49SVenkata Sudheer Kumar Bhavaraju u32 cmd, 657*ef10bd49SVenkata Sudheer Kumar Bhavaraju u32 param, 658*ef10bd49SVenkata Sudheer Kumar Bhavaraju u32 *o_mcp_resp, 659*ef10bd49SVenkata Sudheer Kumar Bhavaraju u32 *o_mcp_param) 660*ef10bd49SVenkata Sudheer Kumar Bhavaraju { 661*ef10bd49SVenkata Sudheer Kumar Bhavaraju return (_qed_mcp_cmd(p_hwfn, p_ptt, cmd, param, 662*ef10bd49SVenkata Sudheer Kumar Bhavaraju o_mcp_resp, o_mcp_param, false)); 663*ef10bd49SVenkata Sudheer Kumar Bhavaraju } 664*ef10bd49SVenkata Sudheer Kumar Bhavaraju 665bf774d14SYueHaibing static int 666bf774d14SYueHaibing qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 66762e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 66862e4d438SSudarsana Reddy Kalluru u32 cmd, 66962e4d438SSudarsana Reddy Kalluru u32 param, 67062e4d438SSudarsana Reddy Kalluru u32 *o_mcp_resp, 67162e4d438SSudarsana Reddy Kalluru u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 67262e4d438SSudarsana Reddy Kalluru { 67362e4d438SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 67462e4d438SSudarsana Reddy Kalluru int rc; 67562e4d438SSudarsana Reddy Kalluru 67662e4d438SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 67762e4d438SSudarsana Reddy Kalluru mb_params.cmd = cmd; 67862e4d438SSudarsana Reddy Kalluru mb_params.param = param; 67962e4d438SSudarsana Reddy Kalluru mb_params.p_data_src = i_buf; 68062e4d438SSudarsana Reddy Kalluru mb_params.data_src_size = (u8)i_txn_size; 68162e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 68262e4d438SSudarsana Reddy Kalluru if (rc) 68362e4d438SSudarsana Reddy Kalluru return rc; 68462e4d438SSudarsana Reddy Kalluru 68562e4d438SSudarsana Reddy Kalluru *o_mcp_resp = mb_params.mcp_resp; 68662e4d438SSudarsana Reddy Kalluru *o_mcp_param = mb_params.mcp_param; 68762e4d438SSudarsana Reddy Kalluru 6885e7ba042SDenis Bolotin /* nvm_info needs to be updated */ 6895e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = false; 6905e7ba042SDenis Bolotin 69162e4d438SSudarsana Reddy Kalluru return 0; 69262e4d438SSudarsana Reddy Kalluru } 69362e4d438SSudarsana Reddy Kalluru 6944102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 6954102426fSTomer Tayar struct qed_ptt *p_ptt, 6964102426fSTomer Tayar u32 cmd, 6974102426fSTomer Tayar u32 param, 6984102426fSTomer Tayar u32 *o_mcp_resp, 6996c95dd8fSPrabhakar Kushwaha u32 *o_mcp_param, 7006c95dd8fSPrabhakar Kushwaha u32 *o_txn_size, u32 *o_buf, bool b_can_sleep) 7014102426fSTomer Tayar { 7024102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 7032f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 7044102426fSTomer Tayar int rc; 7054102426fSTomer Tayar 7064102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 7074102426fSTomer Tayar mb_params.cmd = cmd; 7084102426fSTomer Tayar mb_params.param = param; 7092f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 7102f67af8cSTomer Tayar 7112f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 7122f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 7136c95dd8fSPrabhakar Kushwaha if (b_can_sleep) 7146c95dd8fSPrabhakar Kushwaha mb_params.flags = QED_MB_FLAG_CAN_SLEEP; 7152f67af8cSTomer Tayar 7164102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 7174102426fSTomer Tayar if (rc) 7184102426fSTomer Tayar return rc; 7194102426fSTomer Tayar 7204102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 7214102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 7224102426fSTomer Tayar 7234102426fSTomer Tayar *o_txn_size = *o_mcp_param; 7242f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 7254102426fSTomer Tayar 7264102426fSTomer Tayar return 0; 7274102426fSTomer Tayar } 7284102426fSTomer Tayar 7295d24bcf1STomer Tayar static bool 7305d24bcf1STomer Tayar qed_mcp_can_force_load(u8 drv_role, 7315d24bcf1STomer Tayar u8 exist_drv_role, 7325d24bcf1STomer Tayar enum qed_override_force_load override_force_load) 733fe56b9e6SYuval Mintz { 7345d24bcf1STomer Tayar bool can_force_load = false; 7355d24bcf1STomer Tayar 7365d24bcf1STomer Tayar switch (override_force_load) { 7375d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 7385d24bcf1STomer Tayar can_force_load = true; 7395d24bcf1STomer Tayar break; 7405d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_NEVER: 7415d24bcf1STomer Tayar can_force_load = false; 7425d24bcf1STomer Tayar break; 7435d24bcf1STomer Tayar default: 7445d24bcf1STomer Tayar can_force_load = (drv_role == DRV_ROLE_OS && 7455d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_PREBOOT) || 7465d24bcf1STomer Tayar (drv_role == DRV_ROLE_KDUMP && 7475d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_OS); 7485d24bcf1STomer Tayar break; 7495d24bcf1STomer Tayar } 7505d24bcf1STomer Tayar 7515d24bcf1STomer Tayar return can_force_load; 7525d24bcf1STomer Tayar } 7535d24bcf1STomer Tayar 7545d24bcf1STomer Tayar static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 7555d24bcf1STomer Tayar struct qed_ptt *p_ptt) 7565d24bcf1STomer Tayar { 7575d24bcf1STomer Tayar u32 resp = 0, param = 0; 758fe56b9e6SYuval Mintz int rc; 759fe56b9e6SYuval Mintz 7605d24bcf1STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 7615d24bcf1STomer Tayar &resp, ¶m); 7625d24bcf1STomer Tayar if (rc) 7635d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 7645d24bcf1STomer Tayar "Failed to send cancel load request, rc = %d\n", rc); 765fe56b9e6SYuval Mintz 766fe56b9e6SYuval Mintz return rc; 767fe56b9e6SYuval Mintz } 768fe56b9e6SYuval Mintz 7695d24bcf1STomer Tayar #define CONFIG_QEDE_BITMAP_IDX BIT(0) 7705d24bcf1STomer Tayar #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 7715d24bcf1STomer Tayar #define CONFIG_QEDR_BITMAP_IDX BIT(2) 7725d24bcf1STomer Tayar #define CONFIG_QEDF_BITMAP_IDX BIT(4) 7735d24bcf1STomer Tayar #define CONFIG_QEDI_BITMAP_IDX BIT(5) 7745d24bcf1STomer Tayar #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 7755529bad9STomer Tayar 7765d24bcf1STomer Tayar static u32 qed_get_config_bitmap(void) 7775d24bcf1STomer Tayar { 7785d24bcf1STomer Tayar u32 config_bitmap = 0x0; 7795d24bcf1STomer Tayar 7805d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QEDE)) 7815d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 7825d24bcf1STomer Tayar 7835d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_SRIOV)) 7845d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 7855d24bcf1STomer Tayar 7865d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_RDMA)) 7875d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 7885d24bcf1STomer Tayar 7895d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_FCOE)) 7905d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 7915d24bcf1STomer Tayar 7925d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_ISCSI)) 7935d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 7945d24bcf1STomer Tayar 7955d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_LL2)) 7965d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 7975d24bcf1STomer Tayar 7985d24bcf1STomer Tayar return config_bitmap; 7995d24bcf1STomer Tayar } 8005d24bcf1STomer Tayar 8015d24bcf1STomer Tayar struct qed_load_req_in_params { 8025d24bcf1STomer Tayar u8 hsi_ver; 8035d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 8045d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_1 1 8055d24bcf1STomer Tayar u32 drv_ver_0; 8065d24bcf1STomer Tayar u32 drv_ver_1; 8075d24bcf1STomer Tayar u32 fw_ver; 8085d24bcf1STomer Tayar u8 drv_role; 8095d24bcf1STomer Tayar u8 timeout_val; 8105d24bcf1STomer Tayar u8 force_cmd; 8115d24bcf1STomer Tayar bool avoid_eng_reset; 8125d24bcf1STomer Tayar }; 8135d24bcf1STomer Tayar 8145d24bcf1STomer Tayar struct qed_load_req_out_params { 8155d24bcf1STomer Tayar u32 load_code; 8165d24bcf1STomer Tayar u32 exist_drv_ver_0; 8175d24bcf1STomer Tayar u32 exist_drv_ver_1; 8185d24bcf1STomer Tayar u32 exist_fw_ver; 8195d24bcf1STomer Tayar u8 exist_drv_role; 8205d24bcf1STomer Tayar u8 mfw_hsi_ver; 8215d24bcf1STomer Tayar bool drv_exists; 8225d24bcf1STomer Tayar }; 8235d24bcf1STomer Tayar 8245d24bcf1STomer Tayar static int 8255d24bcf1STomer Tayar __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 8265d24bcf1STomer Tayar struct qed_ptt *p_ptt, 8275d24bcf1STomer Tayar struct qed_load_req_in_params *p_in_params, 8285d24bcf1STomer Tayar struct qed_load_req_out_params *p_out_params) 8295d24bcf1STomer Tayar { 8305d24bcf1STomer Tayar struct qed_mcp_mb_params mb_params; 8315d24bcf1STomer Tayar struct load_req_stc load_req; 8325d24bcf1STomer Tayar struct load_rsp_stc load_rsp; 8335d24bcf1STomer Tayar u32 hsi_ver; 8345d24bcf1STomer Tayar int rc; 8355d24bcf1STomer Tayar 8365d24bcf1STomer Tayar memset(&load_req, 0, sizeof(load_req)); 8375d24bcf1STomer Tayar load_req.drv_ver_0 = p_in_params->drv_ver_0; 8385d24bcf1STomer Tayar load_req.drv_ver_1 = p_in_params->drv_ver_1; 8395d24bcf1STomer Tayar load_req.fw_ver = p_in_params->fw_ver; 8405d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 8415d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 8425d24bcf1STomer Tayar p_in_params->timeout_val); 8435d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 8445d24bcf1STomer Tayar p_in_params->force_cmd); 8455d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 8465d24bcf1STomer Tayar p_in_params->avoid_eng_reset); 8475d24bcf1STomer Tayar 8485d24bcf1STomer Tayar hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 8495d24bcf1STomer Tayar DRV_ID_MCP_HSI_VER_CURRENT : 8505d24bcf1STomer Tayar (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 8515d24bcf1STomer Tayar 8525d24bcf1STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 8535d24bcf1STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 8545d24bcf1STomer Tayar mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 8555d24bcf1STomer Tayar mb_params.p_data_src = &load_req; 8565d24bcf1STomer Tayar mb_params.data_src_size = sizeof(load_req); 8575d24bcf1STomer Tayar mb_params.p_data_dst = &load_rsp; 8585d24bcf1STomer Tayar mb_params.data_dst_size = sizeof(load_rsp); 859b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 8605d24bcf1STomer Tayar 8615d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8625d24bcf1STomer Tayar "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 8635d24bcf1STomer Tayar mb_params.param, 8645d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 8655d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 8665d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 8675d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 8685d24bcf1STomer Tayar 8695d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 8705d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8715d24bcf1STomer Tayar "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 8725d24bcf1STomer Tayar load_req.drv_ver_0, 8735d24bcf1STomer Tayar load_req.drv_ver_1, 8745d24bcf1STomer Tayar load_req.fw_ver, 8755d24bcf1STomer Tayar load_req.misc0, 8765d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 8775d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, 8785d24bcf1STomer Tayar LOAD_REQ_LOCK_TO), 8795d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 8805d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 8815d24bcf1STomer Tayar } 8825d24bcf1STomer Tayar 8835d24bcf1STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 8845d24bcf1STomer Tayar if (rc) { 8855d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 8865d24bcf1STomer Tayar return rc; 8875d24bcf1STomer Tayar } 8885d24bcf1STomer Tayar 8895d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8905d24bcf1STomer Tayar "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 8915d24bcf1STomer Tayar p_out_params->load_code = mb_params.mcp_resp; 8925d24bcf1STomer Tayar 8935d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 8945d24bcf1STomer Tayar p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 8955d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, 8965d24bcf1STomer Tayar QED_MSG_SP, 8975d24bcf1STomer Tayar "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 8985d24bcf1STomer Tayar load_rsp.drv_ver_0, 8995d24bcf1STomer Tayar load_rsp.drv_ver_1, 9005d24bcf1STomer Tayar load_rsp.fw_ver, 9015d24bcf1STomer Tayar load_rsp.misc0, 9025d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 9035d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 9045d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 9055d24bcf1STomer Tayar 9065d24bcf1STomer Tayar p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 9075d24bcf1STomer Tayar p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 9085d24bcf1STomer Tayar p_out_params->exist_fw_ver = load_rsp.fw_ver; 9095d24bcf1STomer Tayar p_out_params->exist_drv_role = 9105d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 9115d24bcf1STomer Tayar p_out_params->mfw_hsi_ver = 9125d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 9135d24bcf1STomer Tayar p_out_params->drv_exists = 9145d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 9155d24bcf1STomer Tayar LOAD_RSP_FLAGS0_DRV_EXISTS; 9165d24bcf1STomer Tayar } 9175d24bcf1STomer Tayar 9185d24bcf1STomer Tayar return 0; 9195d24bcf1STomer Tayar } 9205d24bcf1STomer Tayar 9215d24bcf1STomer Tayar static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 9225d24bcf1STomer Tayar enum qed_drv_role drv_role, 9235d24bcf1STomer Tayar u8 *p_mfw_drv_role) 9245d24bcf1STomer Tayar { 9255d24bcf1STomer Tayar switch (drv_role) { 9265d24bcf1STomer Tayar case QED_DRV_ROLE_OS: 9275d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_OS; 9285d24bcf1STomer Tayar break; 9295d24bcf1STomer Tayar case QED_DRV_ROLE_KDUMP: 9305d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_KDUMP; 9315d24bcf1STomer Tayar break; 9325d24bcf1STomer Tayar default: 9335d24bcf1STomer Tayar DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 9345d24bcf1STomer Tayar return -EINVAL; 9355d24bcf1STomer Tayar } 9365d24bcf1STomer Tayar 9375d24bcf1STomer Tayar return 0; 9385d24bcf1STomer Tayar } 9395d24bcf1STomer Tayar 9405d24bcf1STomer Tayar enum qed_load_req_force { 9415d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, 9425d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_PF, 9435d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9445d24bcf1STomer Tayar }; 9455d24bcf1STomer Tayar 9465d24bcf1STomer Tayar static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 9475d24bcf1STomer Tayar enum qed_load_req_force force_cmd, 9485d24bcf1STomer Tayar u8 *p_mfw_force_cmd) 9495d24bcf1STomer Tayar { 9505d24bcf1STomer Tayar switch (force_cmd) { 9515d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_NONE: 9525d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 9535d24bcf1STomer Tayar break; 9545d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_PF: 9555d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 9565d24bcf1STomer Tayar break; 9575d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_ALL: 9585d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 9595d24bcf1STomer Tayar break; 9605d24bcf1STomer Tayar } 9615d24bcf1STomer Tayar } 9625d24bcf1STomer Tayar 9635d24bcf1STomer Tayar int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 9645d24bcf1STomer Tayar struct qed_ptt *p_ptt, 9655d24bcf1STomer Tayar struct qed_load_req_params *p_params) 9665d24bcf1STomer Tayar { 9675d24bcf1STomer Tayar struct qed_load_req_out_params out_params; 9685d24bcf1STomer Tayar struct qed_load_req_in_params in_params; 9695d24bcf1STomer Tayar u8 mfw_drv_role, mfw_force_cmd; 9705d24bcf1STomer Tayar int rc; 9715d24bcf1STomer Tayar 9725d24bcf1STomer Tayar memset(&in_params, 0, sizeof(in_params)); 9735d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 9745d24bcf1STomer Tayar in_params.drv_ver_1 = qed_get_config_bitmap(); 9755d24bcf1STomer Tayar in_params.fw_ver = STORM_FW_VERSION; 9765d24bcf1STomer Tayar rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 9775d24bcf1STomer Tayar if (rc) 9785d24bcf1STomer Tayar return rc; 9795d24bcf1STomer Tayar 9805d24bcf1STomer Tayar in_params.drv_role = mfw_drv_role; 9815d24bcf1STomer Tayar in_params.timeout_val = p_params->timeout_val; 9825d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9835d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 9845d24bcf1STomer Tayar 9855d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9865d24bcf1STomer Tayar in_params.avoid_eng_reset = p_params->avoid_eng_reset; 9875d24bcf1STomer Tayar 9885d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9895d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9905d24bcf1STomer Tayar if (rc) 9915d24bcf1STomer Tayar return rc; 9925d24bcf1STomer Tayar 9935d24bcf1STomer Tayar /* First handle cases where another load request should/might be sent: 9945d24bcf1STomer Tayar * - MFW expects the old interface [HSI version = 1] 9955d24bcf1STomer Tayar * - MFW responds that a force load request is required 996fe56b9e6SYuval Mintz */ 9975d24bcf1STomer Tayar if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 9985d24bcf1STomer Tayar DP_INFO(p_hwfn, 9995d24bcf1STomer Tayar "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 10005d24bcf1STomer Tayar 10015d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 10025d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 10035d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 10045d24bcf1STomer Tayar if (rc) 10055d24bcf1STomer Tayar return rc; 10065d24bcf1STomer Tayar } else if (out_params.load_code == 10075d24bcf1STomer Tayar FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 10085d24bcf1STomer Tayar if (qed_mcp_can_force_load(in_params.drv_role, 10095d24bcf1STomer Tayar out_params.exist_drv_role, 10105d24bcf1STomer Tayar p_params->override_force_load)) { 10115d24bcf1STomer Tayar DP_INFO(p_hwfn, 10125d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 10135d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10145d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10155d24bcf1STomer Tayar out_params.exist_drv_role, 10165d24bcf1STomer Tayar out_params.exist_fw_ver, 10175d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10185d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10195d24bcf1STomer Tayar 10205d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 10215d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 10225d24bcf1STomer Tayar &mfw_force_cmd); 10235d24bcf1STomer Tayar 10245d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 10255d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 10265d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 10275d24bcf1STomer Tayar &out_params); 10285d24bcf1STomer Tayar if (rc) 10295d24bcf1STomer Tayar return rc; 10305d24bcf1STomer Tayar } else { 10315d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10325d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 10335d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10345d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10355d24bcf1STomer Tayar out_params.exist_drv_role, 10365d24bcf1STomer Tayar out_params.exist_fw_ver, 10375d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10385d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10395d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10405d24bcf1STomer Tayar "Avoid sending a force load request to prevent disruption of active PFs\n"); 10415d24bcf1STomer Tayar 10425d24bcf1STomer Tayar qed_mcp_cancel_load_req(p_hwfn, p_ptt); 1043fe56b9e6SYuval Mintz return -EBUSY; 1044fe56b9e6SYuval Mintz } 10455d24bcf1STomer Tayar } 10465d24bcf1STomer Tayar 10475d24bcf1STomer Tayar /* Now handle the other types of responses. 10485d24bcf1STomer Tayar * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 10495d24bcf1STomer Tayar * expected here after the additional revised load requests were sent. 10505d24bcf1STomer Tayar */ 10515d24bcf1STomer Tayar switch (out_params.load_code) { 10525d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_ENGINE: 10535d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_PORT: 10545d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_FUNCTION: 10555d24bcf1STomer Tayar if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 10565d24bcf1STomer Tayar out_params.drv_exists) { 10575d24bcf1STomer Tayar /* The role and fw/driver version match, but the PF is 10585d24bcf1STomer Tayar * already loaded and has not been unloaded gracefully. 10595d24bcf1STomer Tayar */ 10605d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10615d24bcf1STomer Tayar "PF is already loaded\n"); 10625d24bcf1STomer Tayar return -EINVAL; 10635d24bcf1STomer Tayar } 10645d24bcf1STomer Tayar break; 10655d24bcf1STomer Tayar default: 10665d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10675d24bcf1STomer Tayar "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 10685d24bcf1STomer Tayar out_params.load_code); 10695d24bcf1STomer Tayar return -EBUSY; 10705d24bcf1STomer Tayar } 10715d24bcf1STomer Tayar 10725d24bcf1STomer Tayar p_params->load_code = out_params.load_code; 1073fe56b9e6SYuval Mintz 1074fe56b9e6SYuval Mintz return 0; 1075fe56b9e6SYuval Mintz } 1076fe56b9e6SYuval Mintz 1077666db486STomer Tayar int qed_mcp_load_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1078666db486STomer Tayar { 1079666db486STomer Tayar u32 resp = 0, param = 0; 1080666db486STomer Tayar int rc; 1081666db486STomer Tayar 1082666db486STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp, 1083666db486STomer Tayar ¶m); 1084666db486STomer Tayar if (rc) { 1085666db486STomer Tayar DP_NOTICE(p_hwfn, 1086666db486STomer Tayar "Failed to send a LOAD_DONE command, rc = %d\n", rc); 1087666db486STomer Tayar return rc; 1088666db486STomer Tayar } 1089666db486STomer Tayar 1090666db486STomer Tayar /* Check if there is a DID mismatch between nvm-cfg/efuse */ 1091666db486STomer Tayar if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR) 1092666db486STomer Tayar DP_NOTICE(p_hwfn, 1093666db486STomer Tayar "warning: device configuration is not supported on this board type. The device may not function as expected.\n"); 1094666db486STomer Tayar 1095666db486STomer Tayar return 0; 1096666db486STomer Tayar } 1097666db486STomer Tayar 10981226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10991226337aSTomer Tayar { 1100eaa50fc5STomer Tayar struct qed_mcp_mb_params mb_params; 1101eaa50fc5STomer Tayar u32 wol_param; 11021226337aSTomer Tayar 11031226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 11041226337aSTomer Tayar case QED_OV_WOL_DISABLED: 11051226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 11061226337aSTomer Tayar break; 11071226337aSTomer Tayar case QED_OV_WOL_ENABLED: 11081226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 11091226337aSTomer Tayar break; 11101226337aSTomer Tayar default: 11111226337aSTomer Tayar DP_NOTICE(p_hwfn, 11121226337aSTomer Tayar "Unknown WoL configuration %02x\n", 11131226337aSTomer Tayar p_hwfn->cdev->wol_config); 1114df561f66SGustavo A. R. Silva fallthrough; 11151226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 11161226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 11171226337aSTomer Tayar } 11181226337aSTomer Tayar 1119eaa50fc5STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 1120eaa50fc5STomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ; 1121eaa50fc5STomer Tayar mb_params.param = wol_param; 1122b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 1123eaa50fc5STomer Tayar 1124eaa50fc5STomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11251226337aSTomer Tayar } 11261226337aSTomer Tayar 11271226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11281226337aSTomer Tayar { 11291226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 11301226337aSTomer Tayar struct mcp_mac wol_mac; 11311226337aSTomer Tayar 11321226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 11331226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 11341226337aSTomer Tayar 11351226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 11361226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 11371226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 11381226337aSTomer Tayar 11391226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 11401226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 11411226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 11421226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 11431226337aSTomer Tayar 11441226337aSTomer Tayar DP_VERBOSE(p_hwfn, 11451226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 11461226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 11471226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 11481226337aSTomer Tayar 11491226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 11501226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 11511226337aSTomer Tayar } 11521226337aSTomer Tayar 11531226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11541226337aSTomer Tayar } 11551226337aSTomer Tayar 11560b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 11570b55e27dSYuval Mintz struct qed_ptt *p_ptt) 11580b55e27dSYuval Mintz { 11590b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11600b55e27dSYuval Mintz PUBLIC_PATH); 11610b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 11620b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 11630b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 11640b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 11650b55e27dSYuval Mintz int i; 11660b55e27dSYuval Mintz 11670b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 11680b55e27dSYuval Mintz QED_MSG_SP, 11690b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 11700b55e27dSYuval Mintz mfw_path_offsize, path_addr); 11710b55e27dSYuval Mintz 11720b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 11730b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 11740b55e27dSYuval Mintz path_addr + 11750b55e27dSYuval Mintz offsetof(struct public_path, 11760b55e27dSYuval Mintz mcp_vf_disabled) + 11770b55e27dSYuval Mintz sizeof(u32) * i); 11780b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11790b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 11800b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 11810b55e27dSYuval Mintz } 11820b55e27dSYuval Mintz 11830b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 11840b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 11850b55e27dSYuval Mintz } 11860b55e27dSYuval Mintz 11870b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 11880b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 11890b55e27dSYuval Mintz { 11900b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11910b55e27dSYuval Mintz PUBLIC_FUNC); 11920b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 11930b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 11940b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 11950b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 11960b55e27dSYuval Mintz int rc; 11970b55e27dSYuval Mintz int i; 11980b55e27dSYuval Mintz 11990b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 12000b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 12010b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 12020b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 12030b55e27dSYuval Mintz 12040b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 12050b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 12062f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 12072f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 12080b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 12090b55e27dSYuval Mintz if (rc) { 12100b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 12110b55e27dSYuval Mintz return -EBUSY; 12120b55e27dSYuval Mintz } 12130b55e27dSYuval Mintz 12140b55e27dSYuval Mintz /* Clear the ACK bits */ 12150b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 12160b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 12170b55e27dSYuval Mintz func_addr + 12180b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 12190b55e27dSYuval Mintz i * sizeof(u32), 0); 12200b55e27dSYuval Mintz 12210b55e27dSYuval Mintz return rc; 12220b55e27dSYuval Mintz } 12230b55e27dSYuval Mintz 1224334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1225334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 1226334c03b5SZvi Nachmani { 1227334c03b5SZvi Nachmani u32 transceiver_state; 1228334c03b5SZvi Nachmani 1229334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 1230334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 1231334c03b5SZvi Nachmani offsetof(struct public_port, 1232334c03b5SZvi Nachmani transceiver_data)); 1233334c03b5SZvi Nachmani 1234334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 1235334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 1236334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1237334c03b5SZvi Nachmani transceiver_state, 1238334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 12391a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 1240334c03b5SZvi Nachmani 1241334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 1242351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 1243334c03b5SZvi Nachmani 1244351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1245334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1246334c03b5SZvi Nachmani else 1247334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1248334c03b5SZvi Nachmani } 1249334c03b5SZvi Nachmani 1250645874e5SSudarsana Reddy Kalluru static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1251645874e5SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1252645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_state *p_link) 1253645874e5SSudarsana Reddy Kalluru { 1254645874e5SSudarsana Reddy Kalluru u32 eee_status, val; 1255645874e5SSudarsana Reddy Kalluru 1256645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps = 0; 1257645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps = 0; 1258645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, 1259645874e5SSudarsana Reddy Kalluru p_ptt, 1260645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 1261645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 1262645874e5SSudarsana Reddy Kalluru p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1263645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1264645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1265645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1266645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1267645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1268645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1269645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1270645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1271645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1272645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1273645874e5SSudarsana Reddy Kalluru } 1274645874e5SSudarsana Reddy Kalluru 1275e40a826aSSudarsana Reddy Kalluru static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 1276e40a826aSSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1277e40a826aSSudarsana Reddy Kalluru struct public_func *p_data, int pfid) 1278e40a826aSSudarsana Reddy Kalluru { 1279e40a826aSSudarsana Reddy Kalluru u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1280e40a826aSSudarsana Reddy Kalluru PUBLIC_FUNC); 1281e40a826aSSudarsana Reddy Kalluru u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1282e40a826aSSudarsana Reddy Kalluru u32 func_addr; 1283e40a826aSSudarsana Reddy Kalluru u32 i, size; 1284e40a826aSSudarsana Reddy Kalluru 1285e40a826aSSudarsana Reddy Kalluru func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 1286e40a826aSSudarsana Reddy Kalluru memset(p_data, 0, sizeof(*p_data)); 1287e40a826aSSudarsana Reddy Kalluru 1288e40a826aSSudarsana Reddy Kalluru size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 1289e40a826aSSudarsana Reddy Kalluru for (i = 0; i < size / sizeof(u32); i++) 1290e40a826aSSudarsana Reddy Kalluru ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 1291e40a826aSSudarsana Reddy Kalluru func_addr + (i << 2)); 1292e40a826aSSudarsana Reddy Kalluru return size; 1293e40a826aSSudarsana Reddy Kalluru } 1294e40a826aSSudarsana Reddy Kalluru 1295e40a826aSSudarsana Reddy Kalluru static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 1296e40a826aSSudarsana Reddy Kalluru struct public_func *p_shmem_info) 1297e40a826aSSudarsana Reddy Kalluru { 1298e40a826aSSudarsana Reddy Kalluru struct qed_mcp_function_info *p_info; 1299e40a826aSSudarsana Reddy Kalluru 1300e40a826aSSudarsana Reddy Kalluru p_info = &p_hwfn->mcp_info->func_info; 1301e40a826aSSudarsana Reddy Kalluru 1302e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = QED_MFW_GET_FIELD(p_shmem_info->config, 1303e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MIN_BW); 1304e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 1305e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1306e40a826aSSudarsana Reddy Kalluru "bandwidth minimum out of bounds [%02x]. Set to 1\n", 1307e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min); 1308e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = 1; 1309e40a826aSSudarsana Reddy Kalluru } 1310e40a826aSSudarsana Reddy Kalluru 1311e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = QED_MFW_GET_FIELD(p_shmem_info->config, 1312e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MAX_BW); 1313e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 1314e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1315e40a826aSSudarsana Reddy Kalluru "bandwidth maximum out of bounds [%02x]. Set to 100\n", 1316e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max); 1317e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = 100; 1318e40a826aSSudarsana Reddy Kalluru } 1319e40a826aSSudarsana Reddy Kalluru } 1320e40a826aSSudarsana Reddy Kalluru 1321cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 13221a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 1323cc875c2eSYuval Mintz { 1324cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 1325a64b02d5SManish Chopra u8 max_bw, min_bw; 1326cc875c2eSYuval Mintz u32 status = 0; 1327cc875c2eSYuval Mintz 132865ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 132965ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 133065ed2ffdSMintz, Yuval 1331cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 1332cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 1333cc875c2eSYuval Mintz if (!b_reset) { 1334cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 1335cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 1336cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 1337cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1338cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1339cc875c2eSYuval Mintz status, 1340cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 13411a635e48SYuval Mintz offsetof(struct public_port, link_status))); 1342cc875c2eSYuval Mintz } else { 1343cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1344cc875c2eSYuval Mintz "Resetting link indications\n"); 134565ed2ffdSMintz, Yuval goto out; 1346cc875c2eSYuval Mintz } 1347cc875c2eSYuval Mintz 1348e40a826aSSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) { 1349e40a826aSSudarsana Reddy Kalluru /* Link indication with modern MFW arrives as per-PF 1350e40a826aSSudarsana Reddy Kalluru * indication. 1351e40a826aSSudarsana Reddy Kalluru */ 1352e40a826aSSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & 1353e40a826aSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_VLINK) { 1354e40a826aSSudarsana Reddy Kalluru struct public_func shmem_info; 1355e40a826aSSudarsana Reddy Kalluru 1356e40a826aSSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 1357e40a826aSSudarsana Reddy Kalluru MCP_PF_ID(p_hwfn)); 1358e40a826aSSudarsana Reddy Kalluru p_link->link_up = !!(shmem_info.status & 1359e40a826aSSudarsana Reddy Kalluru FUNC_STATUS_VIRTUAL_LINK_UP); 1360e40a826aSSudarsana Reddy Kalluru qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1361e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1362e40a826aSSudarsana Reddy Kalluru "Virtual link_up = %d\n", p_link->link_up); 1363e40a826aSSudarsana Reddy Kalluru } else { 1364cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1365e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1366e40a826aSSudarsana Reddy Kalluru "Physical link_up = %d\n", p_link->link_up); 1367e40a826aSSudarsana Reddy Kalluru } 1368e40a826aSSudarsana Reddy Kalluru } else { 1369fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 1370e40a826aSSudarsana Reddy Kalluru } 1371cc875c2eSYuval Mintz 1372cc875c2eSYuval Mintz p_link->full_duplex = true; 1373cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1374cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1375cc875c2eSYuval Mintz p_link->speed = 100000; 1376cc875c2eSYuval Mintz break; 1377cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1378cc875c2eSYuval Mintz p_link->speed = 50000; 1379cc875c2eSYuval Mintz break; 1380cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1381cc875c2eSYuval Mintz p_link->speed = 40000; 1382cc875c2eSYuval Mintz break; 1383cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1384cc875c2eSYuval Mintz p_link->speed = 25000; 1385cc875c2eSYuval Mintz break; 1386cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1387cc875c2eSYuval Mintz p_link->speed = 20000; 1388cc875c2eSYuval Mintz break; 1389cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1390cc875c2eSYuval Mintz p_link->speed = 10000; 1391cc875c2eSYuval Mintz break; 1392cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1393cc875c2eSYuval Mintz p_link->full_duplex = false; 1394df561f66SGustavo A. R. Silva fallthrough; 1395cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1396cc875c2eSYuval Mintz p_link->speed = 1000; 1397cc875c2eSYuval Mintz break; 1398cc875c2eSYuval Mintz default: 1399cc875c2eSYuval Mintz p_link->speed = 0; 140058874c7bSSudarsana Reddy Kalluru p_link->link_up = 0; 1401cc875c2eSYuval Mintz } 1402cc875c2eSYuval Mintz 14034b01e519SManish Chopra if (p_link->link_up && p_link->speed) 14044b01e519SManish Chopra p_link->line_speed = p_link->speed; 14054b01e519SManish Chopra else 14064b01e519SManish Chopra p_link->line_speed = 0; 14074b01e519SManish Chopra 14084b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1409a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 14104b01e519SManish Chopra 1411a64b02d5SManish Chopra /* Max bandwidth configuration */ 14124b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1413cc875c2eSYuval Mintz 1414a64b02d5SManish Chopra /* Min bandwidth configuration */ 1415a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 14166f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 14176f437d43SMintz, Yuval p_link->min_pf_rate); 1418a64b02d5SManish Chopra 1419cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1420cc875c2eSYuval Mintz p_link->an_complete = !!(status & 1421cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1422cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 1423cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 1424cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1425cc875c2eSYuval Mintz 1426cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1427cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1428cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 1429cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1430cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1431cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 1432cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1433cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1434cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 1435cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1436cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1437cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 1438cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1439054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1440054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 1441054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 1442cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1443cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 1444cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1445cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1446cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 1447cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1448cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1449cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 1450cc875c2eSYuval Mintz 1451cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 1452cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1453cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 1454cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1455cc875c2eSYuval Mintz 1456cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1457cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1458cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1459cc875c2eSYuval Mintz break; 1460cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1461cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1462cc875c2eSYuval Mintz break; 1463cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1464cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1465cc875c2eSYuval Mintz break; 1466cc875c2eSYuval Mintz default: 1467cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 1468cc875c2eSYuval Mintz } 1469cc875c2eSYuval Mintz 1470cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1471cc875c2eSYuval Mintz 1472645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1473645874e5SSudarsana Reddy Kalluru qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1474645874e5SSudarsana Reddy Kalluru 1475ae7e6937SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 1476ae7e6937SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) { 1477ae7e6937SAlexander Lobakin switch (status & LINK_STATUS_FEC_MODE_MASK) { 1478ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_NONE: 1479ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_NONE; 1480ae7e6937SAlexander Lobakin break; 1481ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_FIRECODE_CL74: 1482ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_FIRECODE; 1483ae7e6937SAlexander Lobakin break; 1484ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_RS_CL91: 1485ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_RS; 1486ae7e6937SAlexander Lobakin break; 1487ae7e6937SAlexander Lobakin default: 1488ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_AUTO; 1489ae7e6937SAlexander Lobakin } 1490ae7e6937SAlexander Lobakin } else { 1491ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_UNSUPPORTED; 1492ae7e6937SAlexander Lobakin } 1493ae7e6937SAlexander Lobakin 1494706d0891SRahul Verma qed_link_update(p_hwfn, p_ptt); 149565ed2ffdSMintz, Yuval out: 149665ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1497cc875c2eSYuval Mintz } 1498cc875c2eSYuval Mintz 1499351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1500cc875c2eSYuval Mintz { 1501cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 15025529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 15032f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 1504ae7e6937SAlexander Lobakin u32 cmd, fec_bit = 0; 150599785a87SAlexander Lobakin u32 val, ext_speed; 1506cc875c2eSYuval Mintz int rc = 0; 1507cc875c2eSYuval Mintz 1508cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 15092f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 1510cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1511cc875c2eSYuval Mintz if (!params->speed.autoneg) 15122f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 15132f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 15142f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 15152f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 15162f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 15172f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 15184ad95a93SSudarsana Reddy Kalluru 15194ad95a93SSudarsana Reddy Kalluru /* There are MFWs that share this capability regardless of whether 15204ad95a93SSudarsana Reddy Kalluru * this is feasible or not. And given that at the very least adv_caps 15214ad95a93SSudarsana Reddy Kalluru * would be set internally by qed, we want to make sure LFA would 15224ad95a93SSudarsana Reddy Kalluru * still work. 15234ad95a93SSudarsana Reddy Kalluru */ 15244ad95a93SSudarsana Reddy Kalluru if ((p_hwfn->mcp_info->capabilities & 15254ad95a93SSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1526645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1527645874e5SSudarsana Reddy Kalluru if (params->eee.tx_lpi_enable) 1528645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1529645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_1G_ADV) 1530645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1531645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_10G_ADV) 1532645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1533645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1534645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_OFFSET) & 1535645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_MASK; 1536645874e5SSudarsana Reddy Kalluru } 1537cc875c2eSYuval Mintz 1538ae7e6937SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 1539ae7e6937SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) { 1540ae7e6937SAlexander Lobakin if (params->fec & QED_FEC_MODE_NONE) 1541ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_NONE; 1542ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_FIRECODE) 1543ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_FIRECODE; 1544ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_RS) 1545ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_RS; 1546ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_AUTO) 1547ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_AUTO; 1548ae7e6937SAlexander Lobakin 1549ae7e6937SAlexander Lobakin SET_MFW_FIELD(phy_cfg.fec_mode, FEC_FORCE_MODE, fec_bit); 1550ae7e6937SAlexander Lobakin } 1551ae7e6937SAlexander Lobakin 155299785a87SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 155399785a87SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL) { 155499785a87SAlexander Lobakin ext_speed = 0; 155599785a87SAlexander Lobakin if (params->ext_speed.autoneg) 1556f2a74107SPrabhakar Kushwaha ext_speed |= ETH_EXT_SPEED_NONE; 155799785a87SAlexander Lobakin 155899785a87SAlexander Lobakin val = params->ext_speed.forced_speed; 155999785a87SAlexander Lobakin if (val & QED_EXT_SPEED_1G) 156099785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_1G; 156199785a87SAlexander Lobakin if (val & QED_EXT_SPEED_10G) 156299785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_10G; 156399785a87SAlexander Lobakin if (val & QED_EXT_SPEED_25G) 156499785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_25G; 156599785a87SAlexander Lobakin if (val & QED_EXT_SPEED_40G) 156699785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_40G; 156799785a87SAlexander Lobakin if (val & QED_EXT_SPEED_50G_R) 156899785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_50G_BASE_R; 156999785a87SAlexander Lobakin if (val & QED_EXT_SPEED_50G_R2) 157099785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_50G_BASE_R2; 157199785a87SAlexander Lobakin if (val & QED_EXT_SPEED_100G_R2) 157299785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_100G_BASE_R2; 157399785a87SAlexander Lobakin if (val & QED_EXT_SPEED_100G_R4) 157499785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_100G_BASE_R4; 157599785a87SAlexander Lobakin if (val & QED_EXT_SPEED_100G_P4) 157699785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_100G_BASE_P4; 157799785a87SAlexander Lobakin 157899785a87SAlexander Lobakin SET_MFW_FIELD(phy_cfg.extended_speed, ETH_EXT_SPEED, 157999785a87SAlexander Lobakin ext_speed); 158099785a87SAlexander Lobakin 158199785a87SAlexander Lobakin ext_speed = 0; 158299785a87SAlexander Lobakin 158399785a87SAlexander Lobakin val = params->ext_speed.advertised_speeds; 158499785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_1G) 158599785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_1G; 158699785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_10G) 158799785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_10G; 158899785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_25G) 158999785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_25G; 159099785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_40G) 159199785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_40G; 159299785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_50G_R) 159399785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_50G_BASE_R; 159499785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_50G_R2) 159599785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_50G_BASE_R2; 159699785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_100G_R2) 159799785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_R2; 159899785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_100G_R4) 159999785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_R4; 160099785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_100G_P4) 160199785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_P4; 160299785a87SAlexander Lobakin 160399785a87SAlexander Lobakin phy_cfg.extended_speed |= ext_speed; 160499785a87SAlexander Lobakin 160599785a87SAlexander Lobakin SET_MFW_FIELD(phy_cfg.fec_mode, FEC_EXTENDED_MODE, 160699785a87SAlexander Lobakin params->ext_fec_mode); 160799785a87SAlexander Lobakin } 160899785a87SAlexander Lobakin 1609fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 1610fc916ff2SSudarsana Reddy Kalluru 1611cc875c2eSYuval Mintz if (b_up) { 1612cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 161399785a87SAlexander Lobakin "Configuring Link: Speed 0x%08x, Pause 0x%08x, Adv. Speed 0x%08x, Loopback 0x%08x, FEC 0x%08x, Ext. Speed 0x%08x\n", 1614ae7e6937SAlexander Lobakin phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed, 161599785a87SAlexander Lobakin phy_cfg.loopback_mode, phy_cfg.fec_mode, 161699785a87SAlexander Lobakin phy_cfg.extended_speed); 1617cc875c2eSYuval Mintz } else { 161899785a87SAlexander Lobakin DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, "Resetting link\n"); 1619cc875c2eSYuval Mintz } 1620cc875c2eSYuval Mintz 16215529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 16225529bad9STomer Tayar mb_params.cmd = cmd; 16232f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 16242f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 16255529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1626cc875c2eSYuval Mintz 1627cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 1628cc875c2eSYuval Mintz if (rc) { 1629cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1630cc875c2eSYuval Mintz return rc; 1631cc875c2eSYuval Mintz } 1632cc875c2eSYuval Mintz 163365ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 163465ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 163565ed2ffdSMintz, Yuval * an attention. 163665ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 163765ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 163865ed2ffdSMintz, Yuval */ 163965ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1640cc875c2eSYuval Mintz 1641cc875c2eSYuval Mintz return 0; 1642cc875c2eSYuval Mintz } 1643cc875c2eSYuval Mintz 164464515dc8STomer Tayar u32 qed_get_process_kill_counter(struct qed_hwfn *p_hwfn, 164564515dc8STomer Tayar struct qed_ptt *p_ptt) 164664515dc8STomer Tayar { 164764515dc8STomer Tayar u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt; 164864515dc8STomer Tayar 164964515dc8STomer Tayar if (IS_VF(p_hwfn->cdev)) 165064515dc8STomer Tayar return -EINVAL; 165164515dc8STomer Tayar 165264515dc8STomer Tayar path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 165364515dc8STomer Tayar PUBLIC_PATH); 165464515dc8STomer Tayar path_offsize = qed_rd(p_hwfn, p_ptt, path_offsize_addr); 165564515dc8STomer Tayar path_addr = SECTION_ADDR(path_offsize, QED_PATH_ID(p_hwfn)); 165664515dc8STomer Tayar 165764515dc8STomer Tayar proc_kill_cnt = qed_rd(p_hwfn, p_ptt, 165864515dc8STomer Tayar path_addr + 165964515dc8STomer Tayar offsetof(struct public_path, process_kill)) & 166064515dc8STomer Tayar PROCESS_KILL_COUNTER_MASK; 166164515dc8STomer Tayar 166264515dc8STomer Tayar return proc_kill_cnt; 166364515dc8STomer Tayar } 166464515dc8STomer Tayar 166564515dc8STomer Tayar static void qed_mcp_handle_process_kill(struct qed_hwfn *p_hwfn, 166664515dc8STomer Tayar struct qed_ptt *p_ptt) 166764515dc8STomer Tayar { 166864515dc8STomer Tayar struct qed_dev *cdev = p_hwfn->cdev; 166964515dc8STomer Tayar u32 proc_kill_cnt; 167064515dc8STomer Tayar 167164515dc8STomer Tayar /* Prevent possible attentions/interrupts during the recovery handling 167264515dc8STomer Tayar * and till its load phase, during which they will be re-enabled. 167364515dc8STomer Tayar */ 167464515dc8STomer Tayar qed_int_igu_disable_int(p_hwfn, p_ptt); 167564515dc8STomer Tayar 167664515dc8STomer Tayar DP_NOTICE(p_hwfn, "Received a process kill indication\n"); 167764515dc8STomer Tayar 167864515dc8STomer Tayar /* The following operations should be done once, and thus in CMT mode 167964515dc8STomer Tayar * are carried out by only the first HW function. 168064515dc8STomer Tayar */ 168164515dc8STomer Tayar if (p_hwfn != QED_LEADING_HWFN(cdev)) 168264515dc8STomer Tayar return; 168364515dc8STomer Tayar 168464515dc8STomer Tayar if (cdev->recov_in_prog) { 168564515dc8STomer Tayar DP_NOTICE(p_hwfn, 168664515dc8STomer Tayar "Ignoring the indication since a recovery process is already in progress\n"); 168764515dc8STomer Tayar return; 168864515dc8STomer Tayar } 168964515dc8STomer Tayar 169064515dc8STomer Tayar cdev->recov_in_prog = true; 169164515dc8STomer Tayar 169264515dc8STomer Tayar proc_kill_cnt = qed_get_process_kill_counter(p_hwfn, p_ptt); 169364515dc8STomer Tayar DP_NOTICE(p_hwfn, "Process kill counter: %d\n", proc_kill_cnt); 169464515dc8STomer Tayar 169564515dc8STomer Tayar qed_schedule_recovery_handler(p_hwfn); 169664515dc8STomer Tayar } 169764515dc8STomer Tayar 16986c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 16996c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 17006c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 17016c754246SSudarsana Reddy Kalluru { 17026c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 17036c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 17046c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 17056c754246SSudarsana Reddy Kalluru u32 hsi_param; 17066c754246SSudarsana Reddy Kalluru 17076c754246SSudarsana Reddy Kalluru switch (type) { 17086c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 17096c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 17106c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 17116c754246SSudarsana Reddy Kalluru break; 17126c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 17136c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 17146c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 17156c754246SSudarsana Reddy Kalluru break; 17166c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 17176c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 17186c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 17196c754246SSudarsana Reddy Kalluru break; 17206c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 17216c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 17226c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 17236c754246SSudarsana Reddy Kalluru break; 17246c754246SSudarsana Reddy Kalluru default: 17256c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 17266c754246SSudarsana Reddy Kalluru return; 17276c754246SSudarsana Reddy Kalluru } 17286c754246SSudarsana Reddy Kalluru 17296c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 17306c754246SSudarsana Reddy Kalluru 17316c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 17326c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 17336c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 17342f67af8cSTomer Tayar mb_params.p_data_src = &stats; 17352f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 17366c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 17376c754246SSudarsana Reddy Kalluru } 17386c754246SSudarsana Reddy Kalluru 17391a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 17404b01e519SManish Chopra { 17414b01e519SManish Chopra struct qed_mcp_function_info *p_info; 17424b01e519SManish Chopra struct public_func shmem_info; 17434b01e519SManish Chopra u32 resp = 0, param = 0; 17444b01e519SManish Chopra 17451a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 17464b01e519SManish Chopra 17474b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 17484b01e519SManish Chopra 17494b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 17504b01e519SManish Chopra 1751a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 17524b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 17534b01e519SManish Chopra 17544b01e519SManish Chopra /* Acknowledge the MFW */ 1755*ef10bd49SVenkata Sudheer Kumar Bhavaraju qed_mcp_cmd_nosleep(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 17564b01e519SManish Chopra ¶m); 17574b01e519SManish Chopra } 17584b01e519SManish Chopra 17592a351fd9SMintz, Yuval static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 17602a351fd9SMintz, Yuval { 17612a351fd9SMintz, Yuval struct public_func shmem_info; 17622a351fd9SMintz, Yuval u32 resp = 0, param = 0; 17632a351fd9SMintz, Yuval 17642a351fd9SMintz, Yuval qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 17652a351fd9SMintz, Yuval 17662a351fd9SMintz, Yuval p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 17672a351fd9SMintz, Yuval FUNC_MF_CFG_OV_STAG_MASK; 17682a351fd9SMintz, Yuval p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 17697e3e375cSSudarsana Reddy Kalluru if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) { 17707e3e375cSSudarsana Reddy Kalluru if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) { 17717e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 17727e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 17737e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1); 17747e3e375cSSudarsana Reddy Kalluru 17757e3e375cSSudarsana Reddy Kalluru /* Configure DB to add external vlan to EDPM packets */ 17767e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1); 17777e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 17787e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 17797e3e375cSSudarsana Reddy Kalluru } else { 17807e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0); 17817e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0); 17827e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0); 17837e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0); 17847e3e375cSSudarsana Reddy Kalluru } 17857e3e375cSSudarsana Reddy Kalluru 17862a351fd9SMintz, Yuval qed_sp_pf_update_stag(p_hwfn); 17872a351fd9SMintz, Yuval } 17882a351fd9SMintz, Yuval 17897e3e375cSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan = %d hw_mode = 0x%x\n", 17907e3e375cSSudarsana Reddy Kalluru p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode); 17917e3e375cSSudarsana Reddy Kalluru 17922a351fd9SMintz, Yuval /* Acknowledge the MFW */ 1793*ef10bd49SVenkata Sudheer Kumar Bhavaraju qed_mcp_cmd_nosleep(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 17942a351fd9SMintz, Yuval &resp, ¶m); 17952a351fd9SMintz, Yuval } 17962a351fd9SMintz, Yuval 17973e99c211SIgor Russkikh static void qed_mcp_handle_fan_failure(struct qed_hwfn *p_hwfn, 17983e99c211SIgor Russkikh struct qed_ptt *p_ptt) 17993e99c211SIgor Russkikh { 18003e99c211SIgor Russkikh /* A single notification should be sent to upper driver in CMT mode */ 18013e99c211SIgor Russkikh if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev)) 18023e99c211SIgor Russkikh return; 18033e99c211SIgor Russkikh 18043e99c211SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_FAN_FAIL, 18053e99c211SIgor Russkikh "Fan failure was detected on the network interface card and it's going to be shut down.\n"); 18063e99c211SIgor Russkikh } 18073e99c211SIgor Russkikh 1808ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params { 1809ebf64bf4SIgor Russkikh u32 cmd; 1810ebf64bf4SIgor Russkikh void *p_data_src; 1811ebf64bf4SIgor Russkikh u8 data_src_size; 1812ebf64bf4SIgor Russkikh void *p_data_dst; 1813ebf64bf4SIgor Russkikh u8 data_dst_size; 1814ebf64bf4SIgor Russkikh u32 mcp_resp; 1815ebf64bf4SIgor Russkikh }; 1816ebf64bf4SIgor Russkikh 1817ebf64bf4SIgor Russkikh static int 1818ebf64bf4SIgor Russkikh qed_mcp_mdump_cmd(struct qed_hwfn *p_hwfn, 1819ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt, 1820ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params *p_mdump_cmd_params) 1821ebf64bf4SIgor Russkikh { 1822ebf64bf4SIgor Russkikh struct qed_mcp_mb_params mb_params; 1823ebf64bf4SIgor Russkikh int rc; 1824ebf64bf4SIgor Russkikh 1825ebf64bf4SIgor Russkikh memset(&mb_params, 0, sizeof(mb_params)); 1826ebf64bf4SIgor Russkikh mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD; 1827ebf64bf4SIgor Russkikh mb_params.param = p_mdump_cmd_params->cmd; 1828ebf64bf4SIgor Russkikh mb_params.p_data_src = p_mdump_cmd_params->p_data_src; 1829ebf64bf4SIgor Russkikh mb_params.data_src_size = p_mdump_cmd_params->data_src_size; 1830ebf64bf4SIgor Russkikh mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst; 1831ebf64bf4SIgor Russkikh mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size; 1832ebf64bf4SIgor Russkikh rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1833ebf64bf4SIgor Russkikh if (rc) 1834ebf64bf4SIgor Russkikh return rc; 1835ebf64bf4SIgor Russkikh 1836ebf64bf4SIgor Russkikh p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp; 1837ebf64bf4SIgor Russkikh 1838ebf64bf4SIgor Russkikh if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) { 1839ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1840ebf64bf4SIgor Russkikh "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n", 1841ebf64bf4SIgor Russkikh p_mdump_cmd_params->cmd); 1842ebf64bf4SIgor Russkikh rc = -EOPNOTSUPP; 1843ebf64bf4SIgor Russkikh } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 1844ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1845ebf64bf4SIgor Russkikh "The mdump command is not supported by the MFW\n"); 1846ebf64bf4SIgor Russkikh rc = -EOPNOTSUPP; 1847ebf64bf4SIgor Russkikh } 1848ebf64bf4SIgor Russkikh 1849ebf64bf4SIgor Russkikh return rc; 1850ebf64bf4SIgor Russkikh } 1851ebf64bf4SIgor Russkikh 1852ebf64bf4SIgor Russkikh static int qed_mcp_mdump_ack(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1853ebf64bf4SIgor Russkikh { 1854ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params mdump_cmd_params; 1855ebf64bf4SIgor Russkikh 1856ebf64bf4SIgor Russkikh memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params)); 1857ebf64bf4SIgor Russkikh mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK; 1858ebf64bf4SIgor Russkikh 1859ebf64bf4SIgor Russkikh return qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params); 1860ebf64bf4SIgor Russkikh } 1861ebf64bf4SIgor Russkikh 1862ebf64bf4SIgor Russkikh int 1863ebf64bf4SIgor Russkikh qed_mcp_mdump_get_retain(struct qed_hwfn *p_hwfn, 1864ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt, 1865ebf64bf4SIgor Russkikh struct mdump_retain_data_stc *p_mdump_retain) 1866ebf64bf4SIgor Russkikh { 1867ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params mdump_cmd_params; 1868ebf64bf4SIgor Russkikh int rc; 1869ebf64bf4SIgor Russkikh 1870ebf64bf4SIgor Russkikh memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params)); 1871ebf64bf4SIgor Russkikh mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN; 1872ebf64bf4SIgor Russkikh mdump_cmd_params.p_data_dst = p_mdump_retain; 1873ebf64bf4SIgor Russkikh mdump_cmd_params.data_dst_size = sizeof(*p_mdump_retain); 1874ebf64bf4SIgor Russkikh 1875ebf64bf4SIgor Russkikh rc = qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params); 1876ebf64bf4SIgor Russkikh if (rc) 1877ebf64bf4SIgor Russkikh return rc; 1878ebf64bf4SIgor Russkikh 1879ebf64bf4SIgor Russkikh if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) { 1880ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1881ebf64bf4SIgor Russkikh "Failed to get the mdump retained data [mcp_resp 0x%x]\n", 1882ebf64bf4SIgor Russkikh mdump_cmd_params.mcp_resp); 1883ebf64bf4SIgor Russkikh return -EINVAL; 1884ebf64bf4SIgor Russkikh } 1885ebf64bf4SIgor Russkikh 1886ebf64bf4SIgor Russkikh return 0; 1887ebf64bf4SIgor Russkikh } 1888ebf64bf4SIgor Russkikh 1889ebf64bf4SIgor Russkikh static void qed_mcp_handle_critical_error(struct qed_hwfn *p_hwfn, 1890ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt) 1891ebf64bf4SIgor Russkikh { 1892ebf64bf4SIgor Russkikh struct mdump_retain_data_stc mdump_retain; 1893ebf64bf4SIgor Russkikh int rc; 1894ebf64bf4SIgor Russkikh 1895ebf64bf4SIgor Russkikh /* In CMT mode - no need for more than a single acknowledgment to the 1896ebf64bf4SIgor Russkikh * MFW, and no more than a single notification to the upper driver. 1897ebf64bf4SIgor Russkikh */ 1898ebf64bf4SIgor Russkikh if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev)) 1899ebf64bf4SIgor Russkikh return; 1900ebf64bf4SIgor Russkikh 1901ebf64bf4SIgor Russkikh rc = qed_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain); 1902ebf64bf4SIgor Russkikh if (rc == 0 && mdump_retain.valid) 1903ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1904ebf64bf4SIgor Russkikh "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n", 1905ebf64bf4SIgor Russkikh mdump_retain.epoch, 1906ebf64bf4SIgor Russkikh mdump_retain.pf, mdump_retain.status); 1907ebf64bf4SIgor Russkikh else 1908ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1909ebf64bf4SIgor Russkikh "The MFW notified that a critical error occurred in the device\n"); 1910ebf64bf4SIgor Russkikh 1911ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1912ebf64bf4SIgor Russkikh "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n"); 1913ebf64bf4SIgor Russkikh qed_mcp_mdump_ack(p_hwfn, p_ptt); 1914ebf64bf4SIgor Russkikh 1915ebf64bf4SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_HW_ATTN, NULL); 1916ebf64bf4SIgor Russkikh } 1917ebf64bf4SIgor Russkikh 1918cac6f691SSudarsana Reddy Kalluru void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1919cac6f691SSudarsana Reddy Kalluru { 1920cac6f691SSudarsana Reddy Kalluru struct public_func shmem_info; 1921cac6f691SSudarsana Reddy Kalluru u32 port_cfg, val; 1922cac6f691SSudarsana Reddy Kalluru 1923cac6f691SSudarsana Reddy Kalluru if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1924cac6f691SSudarsana Reddy Kalluru return; 1925cac6f691SSudarsana Reddy Kalluru 1926cac6f691SSudarsana Reddy Kalluru memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1927cac6f691SSudarsana Reddy Kalluru port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1928cac6f691SSudarsana Reddy Kalluru offsetof(struct public_port, oem_cfg_port)); 1929cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1930cac6f691SSudarsana Reddy Kalluru OEM_CFG_CHANNEL_TYPE_OFFSET; 1931cac6f691SSudarsana Reddy Kalluru if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1932ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1933ec036eb9SSudarsana Reddy Kalluru "Incorrect UFP Channel type %d port_id 0x%02x\n", 1934ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1935cac6f691SSudarsana Reddy Kalluru 1936cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1937cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_SCHED_TYPE_ETS) { 1938cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1939cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1940cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1941cac6f691SSudarsana Reddy Kalluru } else { 1942cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1943ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1944ec036eb9SSudarsana Reddy Kalluru "Unknown UFP scheduling mode %d port_id 0x%02x\n", 1945ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1946cac6f691SSudarsana Reddy Kalluru } 1947cac6f691SSudarsana Reddy Kalluru 1948cac6f691SSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1949b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1950b5fabb08SSudarsana Reddy Kalluru OEM_CFG_FUNC_TC_OFFSET; 1951cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.tc = (u8)val; 1952b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1953cac6f691SSudarsana Reddy Kalluru OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1954cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1955cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1956cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1957cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1958cac6f691SSudarsana Reddy Kalluru } else { 1959cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1960ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1961ec036eb9SSudarsana Reddy Kalluru "Unknown Host priority control %d port_id 0x%02x\n", 1962ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1963cac6f691SSudarsana Reddy Kalluru } 1964cac6f691SSudarsana Reddy Kalluru 1965cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1966ec036eb9SSudarsana Reddy Kalluru "UFP shmem config: mode = %d tc = %d pri_type = %d port_id 0x%02x\n", 1967ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc, 1968ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type, MFW_PORT(p_hwfn)); 1969cac6f691SSudarsana Reddy Kalluru } 1970cac6f691SSudarsana Reddy Kalluru 1971cac6f691SSudarsana Reddy Kalluru static int 1972cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1973cac6f691SSudarsana Reddy Kalluru { 1974cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1975cac6f691SSudarsana Reddy Kalluru 1976cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1977cac6f691SSudarsana Reddy Kalluru p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1978c4259ddaSDenis Bolotin qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1979c4259ddaSDenis Bolotin p_hwfn->ufp_info.tc); 1980cac6f691SSudarsana Reddy Kalluru 1981cac6f691SSudarsana Reddy Kalluru qed_qm_reconf(p_hwfn, p_ptt); 1982cac6f691SSudarsana Reddy Kalluru } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1983cac6f691SSudarsana Reddy Kalluru /* Merge UFP TC with the dcbx TC data */ 1984cac6f691SSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1985cac6f691SSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 1986cac6f691SSudarsana Reddy Kalluru } else { 1987cac6f691SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1988cac6f691SSudarsana Reddy Kalluru return -EINVAL; 1989cac6f691SSudarsana Reddy Kalluru } 1990cac6f691SSudarsana Reddy Kalluru 1991cac6f691SSudarsana Reddy Kalluru /* update storm FW with negotiation results */ 1992cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_ufp(p_hwfn); 1993cac6f691SSudarsana Reddy Kalluru 1994cac6f691SSudarsana Reddy Kalluru /* update stag pcp value */ 1995cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_stag(p_hwfn); 1996cac6f691SSudarsana Reddy Kalluru 1997cac6f691SSudarsana Reddy Kalluru return 0; 1998cac6f691SSudarsana Reddy Kalluru } 1999cac6f691SSudarsana Reddy Kalluru 2000cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 2001cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 2002cc875c2eSYuval Mintz { 2003cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 2004cc875c2eSYuval Mintz int rc = 0; 2005cc875c2eSYuval Mintz bool found = false; 2006cc875c2eSYuval Mintz u16 i; 2007cc875c2eSYuval Mintz 2008cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 2009cc875c2eSYuval Mintz 2010cc875c2eSYuval Mintz /* Read Messages from MFW */ 2011cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 2012cc875c2eSYuval Mintz 2013cc875c2eSYuval Mintz /* Compare current messages to old ones */ 2014cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 2015cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 2016cc875c2eSYuval Mintz continue; 2017cc875c2eSYuval Mintz 2018cc875c2eSYuval Mintz found = true; 2019cc875c2eSYuval Mintz 2020cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2021cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 2022cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 2023cc875c2eSYuval Mintz 2024cc875c2eSYuval Mintz switch (i) { 2025cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 2026cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 2027cc875c2eSYuval Mintz break; 20280b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 20290b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 20300b55e27dSYuval Mintz break; 203139651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 203239651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 203339651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 203439651abdSSudarsana Reddy Kalluru break; 203539651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 203639651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 203739651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 203839651abdSSudarsana Reddy Kalluru break; 203939651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 204039651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 204139651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 204239651abdSSudarsana Reddy Kalluru break; 2043cac6f691SSudarsana Reddy Kalluru case MFW_DRV_MSG_OEM_CFG_UPDATE: 2044cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 2045cac6f691SSudarsana Reddy Kalluru break; 2046334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 2047334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 2048334c03b5SZvi Nachmani break; 204964515dc8STomer Tayar case MFW_DRV_MSG_ERROR_RECOVERY: 205064515dc8STomer Tayar qed_mcp_handle_process_kill(p_hwfn, p_ptt); 205164515dc8STomer Tayar break; 20526c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 20536c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 20546c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 20556c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 20566c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 20576c754246SSudarsana Reddy Kalluru break; 20584b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 20594b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 20604b01e519SManish Chopra break; 20612a351fd9SMintz, Yuval case MFW_DRV_MSG_S_TAG_UPDATE: 20622a351fd9SMintz, Yuval qed_mcp_update_stag(p_hwfn, p_ptt); 20632a351fd9SMintz, Yuval break; 20643e99c211SIgor Russkikh case MFW_DRV_MSG_FAILURE_DETECTED: 20653e99c211SIgor Russkikh qed_mcp_handle_fan_failure(p_hwfn, p_ptt); 20663e99c211SIgor Russkikh break; 2067ebf64bf4SIgor Russkikh case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED: 2068ebf64bf4SIgor Russkikh qed_mcp_handle_critical_error(p_hwfn, p_ptt); 2069ebf64bf4SIgor Russkikh break; 207059ccf86fSSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_TLV_REQ: 207159ccf86fSSudarsana Reddy Kalluru qed_mfw_tlv_req(p_hwfn); 20722a351fd9SMintz, Yuval break; 2073cc875c2eSYuval Mintz default: 207439815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 2075cc875c2eSYuval Mintz rc = -EINVAL; 2076cc875c2eSYuval Mintz } 2077cc875c2eSYuval Mintz } 2078cc875c2eSYuval Mintz 2079cc875c2eSYuval Mintz /* ACK everything */ 2080cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 2081cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 2082cc875c2eSYuval Mintz 2083cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 2084cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 2085cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 2086cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 2087cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 2088cc875c2eSYuval Mintz (__force u32)val); 2089cc875c2eSYuval Mintz } 2090cc875c2eSYuval Mintz 2091cc875c2eSYuval Mintz if (!found) { 2092cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 2093cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 2094cc875c2eSYuval Mintz rc = -EINVAL; 2095cc875c2eSYuval Mintz } 2096cc875c2eSYuval Mintz 2097cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 2098cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 2099cc875c2eSYuval Mintz 2100cc875c2eSYuval Mintz return rc; 2101cc875c2eSYuval Mintz } 2102cc875c2eSYuval Mintz 21031408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 21041408cc1fSYuval Mintz struct qed_ptt *p_ptt, 21051408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 2106fe56b9e6SYuval Mintz { 21076c95dd8fSPrabhakar Kushwaha u32 global_offsize, public_base; 2108fe56b9e6SYuval Mintz 21091408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 21101408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 21111408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 21121408cc1fSYuval Mintz 21131408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 21141408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 21151408cc1fSYuval Mintz return 0; 21161408cc1fSYuval Mintz } else { 21171408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 21181408cc1fSYuval Mintz QED_MSG_IOV, 21191408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 21201408cc1fSYuval Mintz return -EINVAL; 21211408cc1fSYuval Mintz } 21221408cc1fSYuval Mintz } 2123fe56b9e6SYuval Mintz 21246c95dd8fSPrabhakar Kushwaha public_base = p_hwfn->mcp_info->public_base; 2125fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 21266c95dd8fSPrabhakar Kushwaha SECTION_OFFSIZE_ADDR(public_base, 2127fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 21281408cc1fSYuval Mintz *p_mfw_ver = 21291408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 21301408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 21311408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 2132fe56b9e6SYuval Mintz 21336c95dd8fSPrabhakar Kushwaha if (p_running_bundle_id) { 21341408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 21351408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 21361408cc1fSYuval Mintz offsetof(struct public_global, 21371408cc1fSYuval Mintz running_bundle_id)); 21381408cc1fSYuval Mintz } 2139fe56b9e6SYuval Mintz 2140fe56b9e6SYuval Mintz return 0; 2141fe56b9e6SYuval Mintz } 2142fe56b9e6SYuval Mintz 2143ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 2144ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver) 2145ae33666aSTomer Tayar { 2146ae33666aSTomer Tayar u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 2147ae33666aSTomer Tayar 2148ae33666aSTomer Tayar if (IS_VF(p_hwfn->cdev)) 2149ae33666aSTomer Tayar return -EINVAL; 2150ae33666aSTomer Tayar 2151ae33666aSTomer Tayar /* Read the address of the nvm_cfg */ 2152ae33666aSTomer Tayar nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2153ae33666aSTomer Tayar if (!nvm_cfg_addr) { 2154ae33666aSTomer Tayar DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 2155ae33666aSTomer Tayar return -EINVAL; 2156ae33666aSTomer Tayar } 2157ae33666aSTomer Tayar 2158ae33666aSTomer Tayar /* Read the offset of nvm_cfg1 */ 2159ae33666aSTomer Tayar nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2160ae33666aSTomer Tayar 2161ae33666aSTomer Tayar mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2162ae33666aSTomer Tayar offsetof(struct nvm_cfg1, glob) + 2163ae33666aSTomer Tayar offsetof(struct nvm_cfg1_glob, mbi_version); 2164ae33666aSTomer Tayar *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 2165ae33666aSTomer Tayar mbi_ver_addr) & 2166ae33666aSTomer Tayar (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 2167ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 2168ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 2169ae33666aSTomer Tayar 2170ae33666aSTomer Tayar return 0; 2171ae33666aSTomer Tayar } 2172ae33666aSTomer Tayar 2173706d0891SRahul Verma int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, 2174706d0891SRahul Verma struct qed_ptt *p_ptt, u32 *p_media_type) 2175cc875c2eSYuval Mintz { 2176c56a8be7SRahul Verma *p_media_type = MEDIA_UNSPECIFIED; 2177c56a8be7SRahul Verma 2178706d0891SRahul Verma if (IS_VF(p_hwfn->cdev)) 21791408cc1fSYuval Mintz return -EINVAL; 21801408cc1fSYuval Mintz 2181cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 2182cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2183cc875c2eSYuval Mintz return -EBUSY; 2184cc875c2eSYuval Mintz } 2185cc875c2eSYuval Mintz 2186706d0891SRahul Verma if (!p_ptt) { 2187cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 2188706d0891SRahul Verma return -EINVAL; 2189706d0891SRahul Verma } 2190cc875c2eSYuval Mintz 2191706d0891SRahul Verma *p_media_type = qed_rd(p_hwfn, p_ptt, 2192706d0891SRahul Verma p_hwfn->mcp_info->port_addr + 2193706d0891SRahul Verma offsetof(struct public_port, 2194706d0891SRahul Verma media_type)); 2195cc875c2eSYuval Mintz 2196cc875c2eSYuval Mintz return 0; 2197cc875c2eSYuval Mintz } 2198cc875c2eSYuval Mintz 2199c56a8be7SRahul Verma int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, 2200c56a8be7SRahul Verma struct qed_ptt *p_ptt, 2201c56a8be7SRahul Verma u32 *p_transceiver_state, 2202c56a8be7SRahul Verma u32 *p_transceiver_type) 2203c56a8be7SRahul Verma { 2204c56a8be7SRahul Verma u32 transceiver_info; 2205c56a8be7SRahul Verma 220668203a67SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_NONE; 220768203a67SRahul Verma *p_transceiver_state = ETH_TRANSCEIVER_STATE_UPDATING; 220868203a67SRahul Verma 2209c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 2210c56a8be7SRahul Verma return -EINVAL; 2211c56a8be7SRahul Verma 2212c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 2213c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2214c56a8be7SRahul Verma return -EBUSY; 2215c56a8be7SRahul Verma } 2216c56a8be7SRahul Verma 2217c56a8be7SRahul Verma transceiver_info = qed_rd(p_hwfn, p_ptt, 2218c56a8be7SRahul Verma p_hwfn->mcp_info->port_addr + 2219c56a8be7SRahul Verma offsetof(struct public_port, 2220c56a8be7SRahul Verma transceiver_data)); 2221c56a8be7SRahul Verma 2222c56a8be7SRahul Verma *p_transceiver_state = (transceiver_info & 2223c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_MASK) >> 2224c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_OFFSET; 2225c56a8be7SRahul Verma 2226c56a8be7SRahul Verma if (*p_transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 2227c56a8be7SRahul Verma *p_transceiver_type = (transceiver_info & 2228c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_MASK) >> 2229c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_OFFSET; 2230c56a8be7SRahul Verma else 2231c56a8be7SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_UNKNOWN; 2232c56a8be7SRahul Verma 2233c56a8be7SRahul Verma return 0; 2234c56a8be7SRahul Verma } 22356c95dd8fSPrabhakar Kushwaha 2236c56a8be7SRahul Verma static bool qed_is_transceiver_ready(u32 transceiver_state, 2237c56a8be7SRahul Verma u32 transceiver_type) 2238c56a8be7SRahul Verma { 2239c56a8be7SRahul Verma if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) && 2240c56a8be7SRahul Verma ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) && 2241c56a8be7SRahul Verma (transceiver_type != ETH_TRANSCEIVER_TYPE_NONE)) 2242c56a8be7SRahul Verma return true; 2243c56a8be7SRahul Verma 2244c56a8be7SRahul Verma return false; 2245c56a8be7SRahul Verma } 2246c56a8be7SRahul Verma 2247c56a8be7SRahul Verma int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, 2248c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_speed_mask) 2249c56a8be7SRahul Verma { 2250c56a8be7SRahul Verma u32 transceiver_type, transceiver_state; 225192619210SArnd Bergmann int ret; 2252c56a8be7SRahul Verma 225392619210SArnd Bergmann ret = qed_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state, 2254c56a8be7SRahul Verma &transceiver_type); 225592619210SArnd Bergmann if (ret) 225692619210SArnd Bergmann return ret; 2257c56a8be7SRahul Verma 2258c56a8be7SRahul Verma if (qed_is_transceiver_ready(transceiver_state, transceiver_type) == 2259c56a8be7SRahul Verma false) 2260c56a8be7SRahul Verma return -EINVAL; 2261c56a8be7SRahul Verma 2262c56a8be7SRahul Verma switch (transceiver_type) { 2263c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_LX: 2264c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_SX: 2265c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_PCC: 2266c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_ACC: 2267c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1000BASET: 2268c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2269c56a8be7SRahul Verma break; 2270c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_SR: 2271c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LR: 2272c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LRM: 2273c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ER: 2274c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_PCC: 2275c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ACC: 2276c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x10G: 2277c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2278c56a8be7SRahul Verma break; 2279c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_LR4: 2280c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_SR4: 2281c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR: 2282c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR: 2283c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2284c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2285c56a8be7SRahul Verma break; 2286c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_AOC: 2287c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_SR4: 2288c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_LR4: 2289c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ER4: 2290c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ACC: 2291c56a8be7SRahul Verma *p_speed_mask = 2292c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2293c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2294c56a8be7SRahul Verma break; 2295c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_SR: 2296c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_LR: 2297c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_AOC: 2298c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_S: 2299c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_M: 2300c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_L: 2301c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2302c56a8be7SRahul Verma break; 2303c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_N: 2304c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_S: 2305c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_L: 2306c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x25G_CR: 2307c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2308c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2309c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2310c56a8be7SRahul Verma break; 23119228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR: 23129228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR: 23139228b7c1SAlexander Lobakin *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 23149228b7c1SAlexander Lobakin NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 23159228b7c1SAlexander Lobakin break; 2316c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_CR4: 2317c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR: 2318c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2319c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2320c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2321c56a8be7SRahul Verma break; 2322c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_CR4: 2323c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR: 2324c56a8be7SRahul Verma *p_speed_mask = 2325c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2326c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G | 2327c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2328c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2329c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G | 2330c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2331c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2332c56a8be7SRahul Verma break; 2333c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR: 2334c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR: 2335c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC: 2336c56a8be7SRahul Verma *p_speed_mask = 2337c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2338c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2339c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2340c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2341c56a8be7SRahul Verma break; 2342c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_XLPPI: 2343c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 2344c56a8be7SRahul Verma break; 2345c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_BASET: 23469228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR: 23479228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR: 2348c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2349c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2350c56a8be7SRahul Verma break; 2351c56a8be7SRahul Verma default: 23521107a674SColin Ian King DP_INFO(p_hwfn, "Unknown transceiver type 0x%x\n", 2353c56a8be7SRahul Verma transceiver_type); 2354c56a8be7SRahul Verma *p_speed_mask = 0xff; 2355c56a8be7SRahul Verma break; 2356c56a8be7SRahul Verma } 2357c56a8be7SRahul Verma 2358c56a8be7SRahul Verma return 0; 2359c56a8be7SRahul Verma } 2360c56a8be7SRahul Verma 2361c56a8be7SRahul Verma int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, 2362c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_board_config) 2363c56a8be7SRahul Verma { 2364c56a8be7SRahul Verma u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr; 2365c56a8be7SRahul Verma 2366c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 2367c56a8be7SRahul Verma return -EINVAL; 2368c56a8be7SRahul Verma 2369c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 2370c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2371c56a8be7SRahul Verma return -EBUSY; 2372c56a8be7SRahul Verma } 2373c56a8be7SRahul Verma if (!p_ptt) { 2374c56a8be7SRahul Verma *p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED; 2375c56a8be7SRahul Verma return -EINVAL; 2376c56a8be7SRahul Verma } 2377c56a8be7SRahul Verma 2378c56a8be7SRahul Verma nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2379c56a8be7SRahul Verma nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2380c56a8be7SRahul Verma port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2381c56a8be7SRahul Verma offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2382c56a8be7SRahul Verma *p_board_config = qed_rd(p_hwfn, p_ptt, 2383c56a8be7SRahul Verma port_cfg_addr + 2384c56a8be7SRahul Verma offsetof(struct nvm_cfg1_port, 2385c56a8be7SRahul Verma board_cfg)); 2386c56a8be7SRahul Verma 2387c56a8be7SRahul Verma return 0; 2388c56a8be7SRahul Verma } 2389c56a8be7SRahul Verma 23906927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 23916927e826SMintz, Yuval static void 23926927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 23936927e826SMintz, Yuval enum qed_pci_personality *p_proto) 23946927e826SMintz, Yuval { 23956927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 23966927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 23976927e826SMintz, Yuval */ 23986927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 23996927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 24006927e826SMintz, Yuval else 24016927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 24026927e826SMintz, Yuval 24036927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 24046927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 24056927e826SMintz, Yuval (u32)*p_proto); 24066927e826SMintz, Yuval } 24076927e826SMintz, Yuval 24086927e826SMintz, Yuval static int 24096927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 24106927e826SMintz, Yuval struct qed_ptt *p_ptt, 24116927e826SMintz, Yuval enum qed_pci_personality *p_proto) 24126927e826SMintz, Yuval { 24136927e826SMintz, Yuval u32 resp = 0, param = 0; 24146927e826SMintz, Yuval int rc; 24156927e826SMintz, Yuval 24166927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 24176927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 24186927e826SMintz, Yuval if (rc) 24196927e826SMintz, Yuval return rc; 24206927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 24216927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 24226927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 24236927e826SMintz, Yuval resp); 24246927e826SMintz, Yuval return -EINVAL; 24256927e826SMintz, Yuval } 24266927e826SMintz, Yuval 24276927e826SMintz, Yuval switch (param) { 24286927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 24296927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 24306927e826SMintz, Yuval break; 24316927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 24326927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 24336927e826SMintz, Yuval break; 24346927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 2435e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_IWARP; 2436e0a8f9deSMichal Kalderon break; 2437e0a8f9deSMichal Kalderon case FW_MB_PARAM_GET_PF_RDMA_BOTH: 2438e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_RDMA; 2439e0a8f9deSMichal Kalderon break; 24406927e826SMintz, Yuval default: 24416927e826SMintz, Yuval DP_NOTICE(p_hwfn, 24426927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 24436927e826SMintz, Yuval param); 24446927e826SMintz, Yuval return -EINVAL; 24456927e826SMintz, Yuval } 24466927e826SMintz, Yuval 24476927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 24486927e826SMintz, Yuval NETIF_MSG_IFUP, 24496927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 24506927e826SMintz, Yuval (u32)*p_proto, resp, param); 24516927e826SMintz, Yuval return 0; 24526927e826SMintz, Yuval } 24536927e826SMintz, Yuval 2454fe56b9e6SYuval Mintz static int 2455fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 2456fe56b9e6SYuval Mintz struct public_func *p_info, 24576927e826SMintz, Yuval struct qed_ptt *p_ptt, 2458fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 2459fe56b9e6SYuval Mintz { 2460fe56b9e6SYuval Mintz int rc = 0; 2461fe56b9e6SYuval Mintz 2462fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 2463fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 24641fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 24651fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 24661fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 24676927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 2468fe56b9e6SYuval Mintz break; 2469c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 2470c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 2471c5ac9319SYuval Mintz break; 24721e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 24731e128c81SArun Easi *p_proto = QED_PCI_FCOE; 24741e128c81SArun Easi break; 2475c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 2476c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 2477df561f66SGustavo A. R. Silva fallthrough; 2478fe56b9e6SYuval Mintz default: 2479fe56b9e6SYuval Mintz rc = -EINVAL; 2480fe56b9e6SYuval Mintz } 2481fe56b9e6SYuval Mintz 2482fe56b9e6SYuval Mintz return rc; 2483fe56b9e6SYuval Mintz } 2484fe56b9e6SYuval Mintz 2485fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 2486fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 2487fe56b9e6SYuval Mintz { 2488fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 2489fe56b9e6SYuval Mintz struct public_func shmem_info; 2490fe56b9e6SYuval Mintz 24911a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 2492fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 2493fe56b9e6SYuval Mintz 2494fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 2495fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 2496fe56b9e6SYuval Mintz 24976927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 24986927e826SMintz, Yuval &info->protocol)) { 2499fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 2500fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 2501fe56b9e6SYuval Mintz return -EINVAL; 2502fe56b9e6SYuval Mintz } 2503fe56b9e6SYuval Mintz 25044b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 2505fe56b9e6SYuval Mintz 2506fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 2507fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 2508fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 2509fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 2510fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 2511fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 2512fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 251314d39648SMintz, Yuval 251414d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 251514d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 2516fe56b9e6SYuval Mintz } else { 2517fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 2518fe56b9e6SYuval Mintz } 2519fe56b9e6SYuval Mintz 252057796759SMintz, Yuval info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 252157796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 252257796759SMintz, Yuval info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 252357796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 2524fe56b9e6SYuval Mintz 2525fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 2526fe56b9e6SYuval Mintz 25270fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 25280fefbfbaSSudarsana Kalluru 252914d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 253014d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 253114d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 253214d39648SMintz, Yuval u32 resp = 0, param = 0; 253314d39648SMintz, Yuval int rc; 253414d39648SMintz, Yuval 253514d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 253614d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 253714d39648SMintz, Yuval if (rc) 253814d39648SMintz, Yuval return rc; 253914d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 254014d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 254114d39648SMintz, Yuval } 254214d39648SMintz, Yuval 2543fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 2544b03c3bacSAndy Shevchenko "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %pM wwn port %llx node %llx ovlan %04x wol %02x\n", 2545fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 2546fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 2547b03c3bacSAndy Shevchenko info->mac, 254814d39648SMintz, Yuval info->wwn_port, info->wwn_node, 254914d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 2550fe56b9e6SYuval Mintz 2551fe56b9e6SYuval Mintz return 0; 2552fe56b9e6SYuval Mintz } 2553fe56b9e6SYuval Mintz 2554cc875c2eSYuval Mintz struct qed_mcp_link_params 2555cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 2556cc875c2eSYuval Mintz { 2557cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2558cc875c2eSYuval Mintz return NULL; 2559cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 2560cc875c2eSYuval Mintz } 2561cc875c2eSYuval Mintz 2562cc875c2eSYuval Mintz struct qed_mcp_link_state 2563cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 2564cc875c2eSYuval Mintz { 2565cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2566cc875c2eSYuval Mintz return NULL; 2567cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 2568cc875c2eSYuval Mintz } 2569cc875c2eSYuval Mintz 2570cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 2571cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 2572cc875c2eSYuval Mintz { 2573cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2574cc875c2eSYuval Mintz return NULL; 2575cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 2576cc875c2eSYuval Mintz } 2577cc875c2eSYuval Mintz 25781a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2579fe56b9e6SYuval Mintz { 2580fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 2581fe56b9e6SYuval Mintz int rc; 2582fe56b9e6SYuval Mintz 2583fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 25841a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 2585fe56b9e6SYuval Mintz 2586fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 25878f60bafeSYuval Mintz msleep(1020); 2588fe56b9e6SYuval Mintz 2589fe56b9e6SYuval Mintz return rc; 2590fe56b9e6SYuval Mintz } 2591fe56b9e6SYuval Mintz 2592cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 25931a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 2594cee4d264SManish Chopra { 2595cee4d264SManish Chopra u32 flash_size; 2596cee4d264SManish Chopra 25971408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 25981408cc1fSYuval Mintz return -EINVAL; 25991408cc1fSYuval Mintz 2600cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 2601cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 2602cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 2603cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 2604cee4d264SManish Chopra 2605cee4d264SManish Chopra *p_flash_size = flash_size; 2606cee4d264SManish Chopra 2607cee4d264SManish Chopra return 0; 2608cee4d264SManish Chopra } 2609cee4d264SManish Chopra 261064515dc8STomer Tayar int qed_start_recovery_process(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 261164515dc8STomer Tayar { 261264515dc8STomer Tayar struct qed_dev *cdev = p_hwfn->cdev; 261364515dc8STomer Tayar 261464515dc8STomer Tayar if (cdev->recov_in_prog) { 261564515dc8STomer Tayar DP_NOTICE(p_hwfn, 261664515dc8STomer Tayar "Avoid triggering a recovery since such a process is already in progress\n"); 261764515dc8STomer Tayar return -EAGAIN; 261864515dc8STomer Tayar } 261964515dc8STomer Tayar 262064515dc8STomer Tayar DP_NOTICE(p_hwfn, "Triggering a recovery process\n"); 262164515dc8STomer Tayar qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1); 262264515dc8STomer Tayar 262364515dc8STomer Tayar return 0; 262464515dc8STomer Tayar } 262564515dc8STomer Tayar 262664515dc8STomer Tayar #define QED_RECOVERY_PROLOG_SLEEP_MS 100 262764515dc8STomer Tayar 262864515dc8STomer Tayar int qed_recovery_prolog(struct qed_dev *cdev) 262964515dc8STomer Tayar { 263064515dc8STomer Tayar struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 263164515dc8STomer Tayar struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 263264515dc8STomer Tayar int rc; 263364515dc8STomer Tayar 263464515dc8STomer Tayar /* Allow ongoing PCIe transactions to complete */ 263564515dc8STomer Tayar msleep(QED_RECOVERY_PROLOG_SLEEP_MS); 263664515dc8STomer Tayar 263764515dc8STomer Tayar /* Clear the PF's internal FID_enable in the PXP */ 263864515dc8STomer Tayar rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false); 263964515dc8STomer Tayar if (rc) 264064515dc8STomer Tayar DP_NOTICE(p_hwfn, 264164515dc8STomer Tayar "qed_pglueb_set_pfid_enable() failed. rc = %d.\n", 264264515dc8STomer Tayar rc); 264364515dc8STomer Tayar 264464515dc8STomer Tayar return rc; 264564515dc8STomer Tayar } 264664515dc8STomer Tayar 264788072fd4SMintz, Yuval static int 264888072fd4SMintz, Yuval qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 26491408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 26501408cc1fSYuval Mintz { 26511408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 26521408cc1fSYuval Mintz int rc; 26531408cc1fSYuval Mintz 26541408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 26551408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 26561408cc1fSYuval Mintz return 0; 26571408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 26581408cc1fSYuval Mintz 26591408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 26601408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 26611408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 26621408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 26631408cc1fSYuval Mintz 26641408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 26651408cc1fSYuval Mintz &resp, &rc_param); 26661408cc1fSYuval Mintz 26671408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 26681408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 26691408cc1fSYuval Mintz rc = -EINVAL; 26701408cc1fSYuval Mintz } else { 26711408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 26721408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 26731408cc1fSYuval Mintz num, vf_id); 26741408cc1fSYuval Mintz } 26751408cc1fSYuval Mintz 26761408cc1fSYuval Mintz return rc; 26771408cc1fSYuval Mintz } 26781408cc1fSYuval Mintz 267988072fd4SMintz, Yuval static int 268088072fd4SMintz, Yuval qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 268188072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 num) 268288072fd4SMintz, Yuval { 268388072fd4SMintz, Yuval u32 resp = 0, param = num, rc_param = 0; 268488072fd4SMintz, Yuval int rc; 268588072fd4SMintz, Yuval 268688072fd4SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 268788072fd4SMintz, Yuval param, &resp, &rc_param); 268888072fd4SMintz, Yuval 268988072fd4SMintz, Yuval if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 269088072fd4SMintz, Yuval DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 269188072fd4SMintz, Yuval rc = -EINVAL; 269288072fd4SMintz, Yuval } else { 269388072fd4SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_IOV, 269488072fd4SMintz, Yuval "Requested 0x%02x MSI-x interrupts for VFs\n", num); 269588072fd4SMintz, Yuval } 269688072fd4SMintz, Yuval 269788072fd4SMintz, Yuval return rc; 269888072fd4SMintz, Yuval } 269988072fd4SMintz, Yuval 270088072fd4SMintz, Yuval int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 270188072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 vf_id, u8 num) 270288072fd4SMintz, Yuval { 270388072fd4SMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 270488072fd4SMintz, Yuval return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 270588072fd4SMintz, Yuval else 270688072fd4SMintz, Yuval return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 270788072fd4SMintz, Yuval } 270888072fd4SMintz, Yuval 2709fe56b9e6SYuval Mintz int 2710fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2711fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2712fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 2713fe56b9e6SYuval Mintz { 27145529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 27152f67af8cSTomer Tayar struct drv_version_stc drv_version; 27165529bad9STomer Tayar __be32 val; 27175529bad9STomer Tayar u32 i; 27185529bad9STomer Tayar int rc; 2719fe56b9e6SYuval Mintz 27202f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 27212f67af8cSTomer Tayar drv_version.version = p_ver->version; 272267a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 272367a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 27242f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2725fe56b9e6SYuval Mintz } 2726fe56b9e6SYuval Mintz 27275529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 27285529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 27292f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 27302f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 27315529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 27325529bad9STomer Tayar if (rc) 2733fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2734fe56b9e6SYuval Mintz 27355529bad9STomer Tayar return rc; 2736fe56b9e6SYuval Mintz } 273791420b83SSudarsana Kalluru 273876271809STomer Tayar /* A maximal 100 msec waiting time for the MCP to halt */ 273976271809STomer Tayar #define QED_MCP_HALT_SLEEP_MS 10 274076271809STomer Tayar #define QED_MCP_HALT_MAX_RETRIES 10 274176271809STomer Tayar 27424102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 27434102426fSTomer Tayar { 274476271809STomer Tayar u32 resp = 0, param = 0, cpu_state, cnt = 0; 27454102426fSTomer Tayar int rc; 27464102426fSTomer Tayar 27474102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 27484102426fSTomer Tayar ¶m); 274976271809STomer Tayar if (rc) { 27504102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 27514102426fSTomer Tayar return rc; 27524102426fSTomer Tayar } 27534102426fSTomer Tayar 275476271809STomer Tayar do { 275576271809STomer Tayar msleep(QED_MCP_HALT_SLEEP_MS); 275676271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 275776271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) 275876271809STomer Tayar break; 275976271809STomer Tayar } while (++cnt < QED_MCP_HALT_MAX_RETRIES); 276076271809STomer Tayar 276176271809STomer Tayar if (cnt == QED_MCP_HALT_MAX_RETRIES) { 276276271809STomer Tayar DP_NOTICE(p_hwfn, 276376271809STomer Tayar "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 276476271809STomer Tayar qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state); 276576271809STomer Tayar return -EBUSY; 276676271809STomer Tayar } 276776271809STomer Tayar 2768b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 2769b310974eSTomer Tayar 277076271809STomer Tayar return 0; 277176271809STomer Tayar } 277276271809STomer Tayar 277376271809STomer Tayar #define QED_MCP_RESUME_SLEEP_MS 10 277476271809STomer Tayar 27754102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 27764102426fSTomer Tayar { 277776271809STomer Tayar u32 cpu_mode, cpu_state; 27784102426fSTomer Tayar 27794102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 27804102426fSTomer Tayar 27814102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 278276271809STomer Tayar cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT; 278376271809STomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode); 278476271809STomer Tayar msleep(QED_MCP_RESUME_SLEEP_MS); 278576271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 27864102426fSTomer Tayar 278776271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) { 278876271809STomer Tayar DP_NOTICE(p_hwfn, 278976271809STomer Tayar "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 279076271809STomer Tayar cpu_mode, cpu_state); 279176271809STomer Tayar return -EBUSY; 279276271809STomer Tayar } 279376271809STomer Tayar 2794b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, false); 2795b310974eSTomer Tayar 279676271809STomer Tayar return 0; 27974102426fSTomer Tayar } 27984102426fSTomer Tayar 27990fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 28000fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 28010fefbfbaSSudarsana Kalluru enum qed_ov_client client) 28020fefbfbaSSudarsana Kalluru { 28030fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 28040fefbfbaSSudarsana Kalluru u32 drv_mb_param; 28050fefbfbaSSudarsana Kalluru int rc; 28060fefbfbaSSudarsana Kalluru 28070fefbfbaSSudarsana Kalluru switch (client) { 28080fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 28090fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 28100fefbfbaSSudarsana Kalluru break; 28110fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 28120fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 28130fefbfbaSSudarsana Kalluru break; 28140fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 28150fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 28160fefbfbaSSudarsana Kalluru break; 28170fefbfbaSSudarsana Kalluru default: 28180fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 28190fefbfbaSSudarsana Kalluru return -EINVAL; 28200fefbfbaSSudarsana Kalluru } 28210fefbfbaSSudarsana Kalluru 28220fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 28230fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 28240fefbfbaSSudarsana Kalluru if (rc) 28250fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 28260fefbfbaSSudarsana Kalluru 28270fefbfbaSSudarsana Kalluru return rc; 28280fefbfbaSSudarsana Kalluru } 28290fefbfbaSSudarsana Kalluru 28300fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 28310fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 28320fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 28330fefbfbaSSudarsana Kalluru { 28340fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 28350fefbfbaSSudarsana Kalluru u32 drv_mb_param; 28360fefbfbaSSudarsana Kalluru int rc; 28370fefbfbaSSudarsana Kalluru 28380fefbfbaSSudarsana Kalluru switch (drv_state) { 28390fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 28400fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 28410fefbfbaSSudarsana Kalluru break; 28420fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 28430fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 28440fefbfbaSSudarsana Kalluru break; 28450fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 28460fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 28470fefbfbaSSudarsana Kalluru break; 28480fefbfbaSSudarsana Kalluru default: 28490fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 28500fefbfbaSSudarsana Kalluru return -EINVAL; 28510fefbfbaSSudarsana Kalluru } 28520fefbfbaSSudarsana Kalluru 28530fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 28540fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 28550fefbfbaSSudarsana Kalluru if (rc) 28560fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 28570fefbfbaSSudarsana Kalluru 28580fefbfbaSSudarsana Kalluru return rc; 28590fefbfbaSSudarsana Kalluru } 28600fefbfbaSSudarsana Kalluru 28610fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 28620fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 28630fefbfbaSSudarsana Kalluru { 28640fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 28650fefbfbaSSudarsana Kalluru u32 drv_mb_param; 28660fefbfbaSSudarsana Kalluru int rc; 28670fefbfbaSSudarsana Kalluru 28680fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 28690fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 28700fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 28710fefbfbaSSudarsana Kalluru if (rc) 28720fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 28730fefbfbaSSudarsana Kalluru 28740fefbfbaSSudarsana Kalluru return rc; 28750fefbfbaSSudarsana Kalluru } 28760fefbfbaSSudarsana Kalluru 28770fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 287876660757SJakub Kicinski struct qed_ptt *p_ptt, const u8 *mac) 28790fefbfbaSSudarsana Kalluru { 28800fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 288117991002SMintz, Yuval u32 mfw_mac[2]; 28820fefbfbaSSudarsana Kalluru int rc; 28830fefbfbaSSudarsana Kalluru 28840fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 28850fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 28860fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 28870fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 28880fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 28892f67af8cSTomer Tayar 289017991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 289117991002SMintz, Yuval * in 32-bit granularity. 289217991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 289317991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 289417991002SMintz, Yuval */ 289517991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 289617991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 289717991002SMintz, Yuval 289817991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 289917991002SMintz, Yuval mb_params.data_src_size = 8; 29000fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 29010fefbfbaSSudarsana Kalluru if (rc) 29020fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 29030fefbfbaSSudarsana Kalluru 290414d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 290514d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 290614d39648SMintz, Yuval 29070fefbfbaSSudarsana Kalluru return rc; 29080fefbfbaSSudarsana Kalluru } 29090fefbfbaSSudarsana Kalluru 29100fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 29110fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 29120fefbfbaSSudarsana Kalluru { 29130fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 29140fefbfbaSSudarsana Kalluru u32 drv_mb_param; 29150fefbfbaSSudarsana Kalluru int rc; 29160fefbfbaSSudarsana Kalluru 291714d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 291814d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 291914d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 292014d39648SMintz, Yuval return -EINVAL; 292114d39648SMintz, Yuval } 292214d39648SMintz, Yuval 29230fefbfbaSSudarsana Kalluru switch (wol) { 29240fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 29250fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 29260fefbfbaSSudarsana Kalluru break; 29270fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 29280fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 29290fefbfbaSSudarsana Kalluru break; 29300fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 29310fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 29320fefbfbaSSudarsana Kalluru break; 29330fefbfbaSSudarsana Kalluru default: 29340fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 29350fefbfbaSSudarsana Kalluru return -EINVAL; 29360fefbfbaSSudarsana Kalluru } 29370fefbfbaSSudarsana Kalluru 29380fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 29390fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 29400fefbfbaSSudarsana Kalluru if (rc) 29410fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 29420fefbfbaSSudarsana Kalluru 294314d39648SMintz, Yuval /* Store the WoL update for a future unload */ 294414d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 294514d39648SMintz, Yuval 29460fefbfbaSSudarsana Kalluru return rc; 29470fefbfbaSSudarsana Kalluru } 29480fefbfbaSSudarsana Kalluru 29490fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 29500fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 29510fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 29520fefbfbaSSudarsana Kalluru { 29530fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 29540fefbfbaSSudarsana Kalluru u32 drv_mb_param; 29550fefbfbaSSudarsana Kalluru int rc; 29560fefbfbaSSudarsana Kalluru 29570fefbfbaSSudarsana Kalluru switch (eswitch) { 29580fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 29590fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 29600fefbfbaSSudarsana Kalluru break; 29610fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 29620fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 29630fefbfbaSSudarsana Kalluru break; 29640fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 29650fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 29660fefbfbaSSudarsana Kalluru break; 29670fefbfbaSSudarsana Kalluru default: 29680fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 29690fefbfbaSSudarsana Kalluru return -EINVAL; 29700fefbfbaSSudarsana Kalluru } 29710fefbfbaSSudarsana Kalluru 29720fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 29730fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 29740fefbfbaSSudarsana Kalluru if (rc) 29750fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 29760fefbfbaSSudarsana Kalluru 29770fefbfbaSSudarsana Kalluru return rc; 29780fefbfbaSSudarsana Kalluru } 29790fefbfbaSSudarsana Kalluru 29801a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 29811a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 298291420b83SSudarsana Kalluru { 298391420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 298491420b83SSudarsana Kalluru int rc; 298591420b83SSudarsana Kalluru 298691420b83SSudarsana Kalluru switch (mode) { 298791420b83SSudarsana Kalluru case QED_LED_MODE_ON: 298891420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 298991420b83SSudarsana Kalluru break; 299091420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 299191420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 299291420b83SSudarsana Kalluru break; 299391420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 299491420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 299591420b83SSudarsana Kalluru break; 299691420b83SSudarsana Kalluru default: 299791420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 299891420b83SSudarsana Kalluru return -EINVAL; 299991420b83SSudarsana Kalluru } 300091420b83SSudarsana Kalluru 300191420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 300291420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 300391420b83SSudarsana Kalluru 300491420b83SSudarsana Kalluru return rc; 300591420b83SSudarsana Kalluru } 300603dc76caSSudarsana Reddy Kalluru 30074102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 30084102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 30094102426fSTomer Tayar { 30104102426fSTomer Tayar u32 resp = 0, param = 0; 30114102426fSTomer Tayar int rc; 30124102426fSTomer Tayar 30134102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 30144102426fSTomer Tayar mask_parities, &resp, ¶m); 30154102426fSTomer Tayar 30164102426fSTomer Tayar if (rc) { 30174102426fSTomer Tayar DP_ERR(p_hwfn, 30184102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 30194102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 30204102426fSTomer Tayar DP_ERR(p_hwfn, 30214102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 30224102426fSTomer Tayar rc = -EINVAL; 30234102426fSTomer Tayar } 30244102426fSTomer Tayar 30254102426fSTomer Tayar return rc; 30264102426fSTomer Tayar } 30274102426fSTomer Tayar 30287a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 30297a4b21b7SMintz, Yuval { 30307a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 30317a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 30327a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 30337a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 30347a4b21b7SMintz, Yuval int rc = 0; 30357a4b21b7SMintz, Yuval 30367a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 30377a4b21b7SMintz, Yuval if (!p_ptt) 30387a4b21b7SMintz, Yuval return -EBUSY; 30397a4b21b7SMintz, Yuval 30407a4b21b7SMintz, Yuval while (bytes_left > 0) { 30417a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 30427a4b21b7SMintz, Yuval 30437a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 30447a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 30457a4b21b7SMintz, Yuval addr + offset + 30467a4b21b7SMintz, Yuval (bytes_to_copy << 3047da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 30487a4b21b7SMintz, Yuval &resp, &resp_param, 30497a4b21b7SMintz, Yuval &read_len, 30506c95dd8fSPrabhakar Kushwaha (u32 *)(p_buf + offset), false); 30517a4b21b7SMintz, Yuval 30527a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 30537a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 30547a4b21b7SMintz, Yuval break; 30557a4b21b7SMintz, Yuval } 30567a4b21b7SMintz, Yuval 30577a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 30586c95dd8fSPrabhakar Kushwaha * isn't preemptible. Sleep a bit to prevent CPU hogging. 30597a4b21b7SMintz, Yuval */ 30607a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 30617a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 30627a4b21b7SMintz, Yuval usleep_range(1000, 2000); 30637a4b21b7SMintz, Yuval 30647a4b21b7SMintz, Yuval offset += read_len; 30657a4b21b7SMintz, Yuval bytes_left -= read_len; 30667a4b21b7SMintz, Yuval } 30677a4b21b7SMintz, Yuval 30687a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 30697a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 30707a4b21b7SMintz, Yuval 30717a4b21b7SMintz, Yuval return rc; 30727a4b21b7SMintz, Yuval } 30737a4b21b7SMintz, Yuval 307462e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 307562e4d438SSudarsana Reddy Kalluru { 307662e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 307762e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 307862e4d438SSudarsana Reddy Kalluru 307962e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 308062e4d438SSudarsana Reddy Kalluru if (!p_ptt) 308162e4d438SSudarsana Reddy Kalluru return -EBUSY; 308262e4d438SSudarsana Reddy Kalluru 308362e4d438SSudarsana Reddy Kalluru memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 308462e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 308562e4d438SSudarsana Reddy Kalluru 308662e4d438SSudarsana Reddy Kalluru return 0; 308762e4d438SSudarsana Reddy Kalluru } 308862e4d438SSudarsana Reddy Kalluru 308962e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 309062e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len) 309162e4d438SSudarsana Reddy Kalluru { 309262e4d438SSudarsana Reddy Kalluru u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 309362e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 309462e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 309562e4d438SSudarsana Reddy Kalluru int rc = -EINVAL; 309662e4d438SSudarsana Reddy Kalluru 309762e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 309862e4d438SSudarsana Reddy Kalluru if (!p_ptt) 309962e4d438SSudarsana Reddy Kalluru return -EBUSY; 310062e4d438SSudarsana Reddy Kalluru 310162e4d438SSudarsana Reddy Kalluru switch (cmd) { 3102057d2b19SSudarsana Reddy Kalluru case QED_PUT_FILE_BEGIN: 3103057d2b19SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN; 3104057d2b19SSudarsana Reddy Kalluru break; 310562e4d438SSudarsana Reddy Kalluru case QED_PUT_FILE_DATA: 310662e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 310762e4d438SSudarsana Reddy Kalluru break; 310862e4d438SSudarsana Reddy Kalluru case QED_NVM_WRITE_NVRAM: 310962e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 311062e4d438SSudarsana Reddy Kalluru break; 311162e4d438SSudarsana Reddy Kalluru default: 311262e4d438SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 311362e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 311462e4d438SSudarsana Reddy Kalluru goto out; 311562e4d438SSudarsana Reddy Kalluru } 311662e4d438SSudarsana Reddy Kalluru 311762e4d438SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 3118057d2b19SSudarsana Reddy Kalluru while (buf_idx < len) { 3119057d2b19SSudarsana Reddy Kalluru if (cmd == QED_PUT_FILE_BEGIN) 3120057d2b19SSudarsana Reddy Kalluru nvm_offset = addr; 3121057d2b19SSudarsana Reddy Kalluru else 3122057d2b19SSudarsana Reddy Kalluru nvm_offset = ((buf_size << 3123057d2b19SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_LEN_OFFSET) | addr) + 3124057d2b19SSudarsana Reddy Kalluru buf_idx; 312562e4d438SSudarsana Reddy Kalluru rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 312662e4d438SSudarsana Reddy Kalluru &resp, ¶m, buf_size, 312762e4d438SSudarsana Reddy Kalluru (u32 *)&p_buf[buf_idx]); 312862e4d438SSudarsana Reddy Kalluru if (rc) { 312962e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 313062e4d438SSudarsana Reddy Kalluru resp = FW_MSG_CODE_ERROR; 313162e4d438SSudarsana Reddy Kalluru break; 313262e4d438SSudarsana Reddy Kalluru } 313362e4d438SSudarsana Reddy Kalluru 313462e4d438SSudarsana Reddy Kalluru if (resp != FW_MSG_CODE_OK && 313562e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_OK && 313662e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 313762e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, 313862e4d438SSudarsana Reddy Kalluru "nvm write failed, resp = 0x%08x\n", resp); 313962e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 314062e4d438SSudarsana Reddy Kalluru break; 314162e4d438SSudarsana Reddy Kalluru } 314262e4d438SSudarsana Reddy Kalluru 314362e4d438SSudarsana Reddy Kalluru /* This can be a lengthy process, and it's possible scheduler 314462e4d438SSudarsana Reddy Kalluru * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 314562e4d438SSudarsana Reddy Kalluru */ 314662e4d438SSudarsana Reddy Kalluru if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 314762e4d438SSudarsana Reddy Kalluru usleep_range(1000, 2000); 314862e4d438SSudarsana Reddy Kalluru 3149057d2b19SSudarsana Reddy Kalluru /* For MBI upgrade, MFW response includes the next buffer offset 3150057d2b19SSudarsana Reddy Kalluru * to be delivered to MFW. 3151057d2b19SSudarsana Reddy Kalluru */ 3152057d2b19SSudarsana Reddy Kalluru if (param && cmd == QED_PUT_FILE_DATA) { 31536c95dd8fSPrabhakar Kushwaha buf_idx = 31546c95dd8fSPrabhakar Kushwaha QED_MFW_GET_FIELD(param, 3155057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET); 31566c95dd8fSPrabhakar Kushwaha buf_size = 31576c95dd8fSPrabhakar Kushwaha QED_MFW_GET_FIELD(param, 3158057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE); 3159057d2b19SSudarsana Reddy Kalluru } else { 316062e4d438SSudarsana Reddy Kalluru buf_idx += buf_size; 3161057d2b19SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), 3162057d2b19SSudarsana Reddy Kalluru MCP_DRV_NVM_BUF_LEN); 3163057d2b19SSudarsana Reddy Kalluru } 316462e4d438SSudarsana Reddy Kalluru } 316562e4d438SSudarsana Reddy Kalluru 316662e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 316762e4d438SSudarsana Reddy Kalluru out: 316862e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 316962e4d438SSudarsana Reddy Kalluru 317062e4d438SSudarsana Reddy Kalluru return rc; 317162e4d438SSudarsana Reddy Kalluru } 317262e4d438SSudarsana Reddy Kalluru 3173b51dab46SSudarsana Reddy Kalluru int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3174b51dab46SSudarsana Reddy Kalluru u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 3175b51dab46SSudarsana Reddy Kalluru { 3176b51dab46SSudarsana Reddy Kalluru u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 3177b51dab46SSudarsana Reddy Kalluru u32 resp, param; 3178b51dab46SSudarsana Reddy Kalluru int rc; 3179b51dab46SSudarsana Reddy Kalluru 3180b51dab46SSudarsana Reddy Kalluru nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 3181b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 3182b51dab46SSudarsana Reddy Kalluru nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 3183b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 3184b51dab46SSudarsana Reddy Kalluru 3185b51dab46SSudarsana Reddy Kalluru addr = offset; 3186b51dab46SSudarsana Reddy Kalluru offset = 0; 3187b51dab46SSudarsana Reddy Kalluru bytes_left = len; 3188b51dab46SSudarsana Reddy Kalluru while (bytes_left > 0) { 3189b51dab46SSudarsana Reddy Kalluru bytes_to_copy = min_t(u32, bytes_left, 3190b51dab46SSudarsana Reddy Kalluru MAX_I2C_TRANSACTION_SIZE); 3191b51dab46SSudarsana Reddy Kalluru nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 3192b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 3193b51dab46SSudarsana Reddy Kalluru nvm_offset |= ((addr + offset) << 3194b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 3195b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 3196b51dab46SSudarsana Reddy Kalluru nvm_offset |= (bytes_to_copy << 3197b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 3198b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 3199b51dab46SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 3200b51dab46SSudarsana Reddy Kalluru DRV_MSG_CODE_TRANSCEIVER_READ, 3201b51dab46SSudarsana Reddy Kalluru nvm_offset, &resp, ¶m, &buf_size, 32026c95dd8fSPrabhakar Kushwaha (u32 *)(p_buf + offset), true); 3203b51dab46SSudarsana Reddy Kalluru if (rc) { 3204b51dab46SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 3205b51dab46SSudarsana Reddy Kalluru "Failed to send a transceiver read command to the MFW. rc = %d.\n", 3206b51dab46SSudarsana Reddy Kalluru rc); 3207b51dab46SSudarsana Reddy Kalluru return rc; 3208b51dab46SSudarsana Reddy Kalluru } 3209b51dab46SSudarsana Reddy Kalluru 3210b51dab46SSudarsana Reddy Kalluru if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 3211b51dab46SSudarsana Reddy Kalluru return -ENODEV; 3212b51dab46SSudarsana Reddy Kalluru else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 3213b51dab46SSudarsana Reddy Kalluru return -EINVAL; 3214b51dab46SSudarsana Reddy Kalluru 3215b51dab46SSudarsana Reddy Kalluru offset += buf_size; 3216b51dab46SSudarsana Reddy Kalluru bytes_left -= buf_size; 3217b51dab46SSudarsana Reddy Kalluru } 3218b51dab46SSudarsana Reddy Kalluru 3219b51dab46SSudarsana Reddy Kalluru return 0; 3220b51dab46SSudarsana Reddy Kalluru } 3221b51dab46SSudarsana Reddy Kalluru 322203dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 322303dc76caSSudarsana Reddy Kalluru { 322403dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 322503dc76caSSudarsana Reddy Kalluru int rc = 0; 322603dc76caSSudarsana Reddy Kalluru 322703dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 322803dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 322903dc76caSSudarsana Reddy Kalluru 323003dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 323103dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 323203dc76caSSudarsana Reddy Kalluru 323303dc76caSSudarsana Reddy Kalluru if (rc) 323403dc76caSSudarsana Reddy Kalluru return rc; 323503dc76caSSudarsana Reddy Kalluru 323603dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 323703dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 323803dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 323903dc76caSSudarsana Reddy Kalluru 324003dc76caSSudarsana Reddy Kalluru return rc; 324103dc76caSSudarsana Reddy Kalluru } 324203dc76caSSudarsana Reddy Kalluru 324303dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 324403dc76caSSudarsana Reddy Kalluru { 324503dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 324603dc76caSSudarsana Reddy Kalluru int rc = 0; 324703dc76caSSudarsana Reddy Kalluru 324803dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 324903dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 325003dc76caSSudarsana Reddy Kalluru 325103dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 325203dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 325303dc76caSSudarsana Reddy Kalluru 325403dc76caSSudarsana Reddy Kalluru if (rc) 325503dc76caSSudarsana Reddy Kalluru return rc; 325603dc76caSSudarsana Reddy Kalluru 325703dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 325803dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 325903dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 326003dc76caSSudarsana Reddy Kalluru 326103dc76caSSudarsana Reddy Kalluru return rc; 326203dc76caSSudarsana Reddy Kalluru } 32637a4b21b7SMintz, Yuval 326443645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 32657a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 32667a4b21b7SMintz, Yuval u32 *num_images) 32677a4b21b7SMintz, Yuval { 32687a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 32697a4b21b7SMintz, Yuval int rc = 0; 32707a4b21b7SMintz, Yuval 32717a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 32727a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 32737a4b21b7SMintz, Yuval 32747a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 32757a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 32767a4b21b7SMintz, Yuval if (rc) 32777a4b21b7SMintz, Yuval return rc; 32787a4b21b7SMintz, Yuval 32797a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 32807a4b21b7SMintz, Yuval rc = -EINVAL; 32817a4b21b7SMintz, Yuval 32827a4b21b7SMintz, Yuval return rc; 32837a4b21b7SMintz, Yuval } 32847a4b21b7SMintz, Yuval 328543645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 32867a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 32877a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 32887a4b21b7SMintz, Yuval u32 image_index) 32897a4b21b7SMintz, Yuval { 32907a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 32917a4b21b7SMintz, Yuval int rc; 32927a4b21b7SMintz, Yuval 32937a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 32947a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 32957a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 32967a4b21b7SMintz, Yuval 32977a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 32987a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 32997a4b21b7SMintz, Yuval &resp, &resp_param, 33007a4b21b7SMintz, Yuval &buf_size, 33016c95dd8fSPrabhakar Kushwaha (u32 *)p_image_att, false); 33027a4b21b7SMintz, Yuval if (rc) 33037a4b21b7SMintz, Yuval return rc; 33047a4b21b7SMintz, Yuval 33057a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 33067a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 33077a4b21b7SMintz, Yuval rc = -EINVAL; 33087a4b21b7SMintz, Yuval 33097a4b21b7SMintz, Yuval return rc; 33107a4b21b7SMintz, Yuval } 33112edbff8dSTomer Tayar 331243645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 331343645ce0SSudarsana Reddy Kalluru { 33145e7ba042SDenis Bolotin struct qed_nvm_image_info nvm_info; 331543645ce0SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 331643645ce0SSudarsana Reddy Kalluru int rc; 331743645ce0SSudarsana Reddy Kalluru u32 i; 331843645ce0SSudarsana Reddy Kalluru 33195e7ba042SDenis Bolotin if (p_hwfn->nvm_info.valid) 33205e7ba042SDenis Bolotin return 0; 33215e7ba042SDenis Bolotin 332243645ce0SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 332343645ce0SSudarsana Reddy Kalluru if (!p_ptt) { 332443645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "failed to acquire ptt\n"); 332543645ce0SSudarsana Reddy Kalluru return -EBUSY; 332643645ce0SSudarsana Reddy Kalluru } 332743645ce0SSudarsana Reddy Kalluru 332843645ce0SSudarsana Reddy Kalluru /* Acquire from MFW the amount of available images */ 33295e7ba042SDenis Bolotin nvm_info.num_images = 0; 333043645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 33315e7ba042SDenis Bolotin p_ptt, &nvm_info.num_images); 333243645ce0SSudarsana Reddy Kalluru if (rc == -EOPNOTSUPP) { 333343645ce0SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 333443645ce0SSudarsana Reddy Kalluru goto out; 33355e7ba042SDenis Bolotin } else if (rc || !nvm_info.num_images) { 333643645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Failed getting number of images\n"); 333743645ce0SSudarsana Reddy Kalluru goto err0; 333843645ce0SSudarsana Reddy Kalluru } 333943645ce0SSudarsana Reddy Kalluru 33405e7ba042SDenis Bolotin nvm_info.image_att = kmalloc_array(nvm_info.num_images, 334143645ce0SSudarsana Reddy Kalluru sizeof(struct bist_nvm_image_att), 334243645ce0SSudarsana Reddy Kalluru GFP_KERNEL); 33435e7ba042SDenis Bolotin if (!nvm_info.image_att) { 334443645ce0SSudarsana Reddy Kalluru rc = -ENOMEM; 334543645ce0SSudarsana Reddy Kalluru goto err0; 334643645ce0SSudarsana Reddy Kalluru } 334743645ce0SSudarsana Reddy Kalluru 334843645ce0SSudarsana Reddy Kalluru /* Iterate over images and get their attributes */ 33495e7ba042SDenis Bolotin for (i = 0; i < nvm_info.num_images; i++) { 335043645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 33515e7ba042SDenis Bolotin &nvm_info.image_att[i], i); 335243645ce0SSudarsana Reddy Kalluru if (rc) { 335343645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, 335443645ce0SSudarsana Reddy Kalluru "Failed getting image index %d attributes\n", i); 335543645ce0SSudarsana Reddy Kalluru goto err1; 335643645ce0SSudarsana Reddy Kalluru } 335743645ce0SSudarsana Reddy Kalluru 335843645ce0SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 33595e7ba042SDenis Bolotin nvm_info.image_att[i].len); 336043645ce0SSudarsana Reddy Kalluru } 336143645ce0SSudarsana Reddy Kalluru out: 33625e7ba042SDenis Bolotin /* Update hwfn's nvm_info */ 33635e7ba042SDenis Bolotin if (nvm_info.num_images) { 33645e7ba042SDenis Bolotin p_hwfn->nvm_info.num_images = nvm_info.num_images; 33655e7ba042SDenis Bolotin kfree(p_hwfn->nvm_info.image_att); 33665e7ba042SDenis Bolotin p_hwfn->nvm_info.image_att = nvm_info.image_att; 33675e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = true; 33685e7ba042SDenis Bolotin } 33695e7ba042SDenis Bolotin 337043645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 337143645ce0SSudarsana Reddy Kalluru return 0; 337243645ce0SSudarsana Reddy Kalluru 337343645ce0SSudarsana Reddy Kalluru err1: 33745e7ba042SDenis Bolotin kfree(nvm_info.image_att); 337543645ce0SSudarsana Reddy Kalluru err0: 337643645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 337743645ce0SSudarsana Reddy Kalluru return rc; 337843645ce0SSudarsana Reddy Kalluru } 337943645ce0SSudarsana Reddy Kalluru 338013cf8aabSSudarsana Reddy Kalluru void qed_mcp_nvm_info_free(struct qed_hwfn *p_hwfn) 338113cf8aabSSudarsana Reddy Kalluru { 338213cf8aabSSudarsana Reddy Kalluru kfree(p_hwfn->nvm_info.image_att); 338313cf8aabSSudarsana Reddy Kalluru p_hwfn->nvm_info.image_att = NULL; 338413cf8aabSSudarsana Reddy Kalluru p_hwfn->nvm_info.valid = false; 338513cf8aabSSudarsana Reddy Kalluru } 338613cf8aabSSudarsana Reddy Kalluru 33871ac4329aSDenis Bolotin int 338820675b37SMintz, Yuval qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 338920675b37SMintz, Yuval enum qed_nvm_images image_id, 339020675b37SMintz, Yuval struct qed_nvm_image_att *p_image_att) 339120675b37SMintz, Yuval { 339220675b37SMintz, Yuval enum nvm_image_type type; 339320e100f5SShai Malin int rc; 339443645ce0SSudarsana Reddy Kalluru u32 i; 339520675b37SMintz, Yuval 339620675b37SMintz, Yuval /* Translate image_id into MFW definitions */ 339720675b37SMintz, Yuval switch (image_id) { 339820675b37SMintz, Yuval case QED_NVM_IMAGE_ISCSI_CFG: 339920675b37SMintz, Yuval type = NVM_TYPE_ISCSI_CFG; 340020675b37SMintz, Yuval break; 340120675b37SMintz, Yuval case QED_NVM_IMAGE_FCOE_CFG: 340220675b37SMintz, Yuval type = NVM_TYPE_FCOE_CFG; 340320675b37SMintz, Yuval break; 34048a52bbabSMichal Kalderon case QED_NVM_IMAGE_MDUMP: 34058a52bbabSMichal Kalderon type = NVM_TYPE_MDUMP; 34068a52bbabSMichal Kalderon break; 34071ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_CFG1: 34081ac4329aSDenis Bolotin type = NVM_TYPE_NVM_CFG1; 34091ac4329aSDenis Bolotin break; 34101ac4329aSDenis Bolotin case QED_NVM_IMAGE_DEFAULT_CFG: 34111ac4329aSDenis Bolotin type = NVM_TYPE_DEFAULT_CFG; 34121ac4329aSDenis Bolotin break; 34131ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_META: 3414f2a74107SPrabhakar Kushwaha type = NVM_TYPE_NVM_META; 34151ac4329aSDenis Bolotin break; 341620675b37SMintz, Yuval default: 341720675b37SMintz, Yuval DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 341820675b37SMintz, Yuval image_id); 341920675b37SMintz, Yuval return -EINVAL; 342020675b37SMintz, Yuval } 342120675b37SMintz, Yuval 342220e100f5SShai Malin rc = qed_mcp_nvm_info_populate(p_hwfn); 342320e100f5SShai Malin if (rc) 342420e100f5SShai Malin return rc; 342520e100f5SShai Malin 342643645ce0SSudarsana Reddy Kalluru for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 342743645ce0SSudarsana Reddy Kalluru if (type == p_hwfn->nvm_info.image_att[i].image_type) 342820675b37SMintz, Yuval break; 342943645ce0SSudarsana Reddy Kalluru if (i == p_hwfn->nvm_info.num_images) { 343020675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 343120675b37SMintz, Yuval "Failed to find nvram image of type %08x\n", 343220675b37SMintz, Yuval image_id); 343343645ce0SSudarsana Reddy Kalluru return -ENOENT; 343420675b37SMintz, Yuval } 343520675b37SMintz, Yuval 343643645ce0SSudarsana Reddy Kalluru p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 343743645ce0SSudarsana Reddy Kalluru p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 343820675b37SMintz, Yuval 343920675b37SMintz, Yuval return 0; 344020675b37SMintz, Yuval } 344120675b37SMintz, Yuval 344220675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 344320675b37SMintz, Yuval enum qed_nvm_images image_id, 344420675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len) 344520675b37SMintz, Yuval { 344620675b37SMintz, Yuval struct qed_nvm_image_att image_att; 344720675b37SMintz, Yuval int rc; 344820675b37SMintz, Yuval 344920675b37SMintz, Yuval memset(p_buffer, 0, buffer_len); 345020675b37SMintz, Yuval 3451b60bfdfeSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 345220675b37SMintz, Yuval if (rc) 345320675b37SMintz, Yuval return rc; 345420675b37SMintz, Yuval 345520675b37SMintz, Yuval /* Validate sizes - both the image's and the supplied buffer's */ 345620675b37SMintz, Yuval if (image_att.length <= 4) { 345720675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 345820675b37SMintz, Yuval "Image [%d] is too small - only %d bytes\n", 345920675b37SMintz, Yuval image_id, image_att.length); 346020675b37SMintz, Yuval return -EINVAL; 346120675b37SMintz, Yuval } 346220675b37SMintz, Yuval 346320675b37SMintz, Yuval if (image_att.length > buffer_len) { 346420675b37SMintz, Yuval DP_VERBOSE(p_hwfn, 346520675b37SMintz, Yuval QED_MSG_STORAGE, 346620675b37SMintz, Yuval "Image [%d] is too big - %08x bytes where only %08x are available\n", 346720675b37SMintz, Yuval image_id, image_att.length, buffer_len); 346820675b37SMintz, Yuval return -ENOMEM; 346920675b37SMintz, Yuval } 347020675b37SMintz, Yuval 347120675b37SMintz, Yuval return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 347220675b37SMintz, Yuval p_buffer, image_att.length); 347320675b37SMintz, Yuval } 347420675b37SMintz, Yuval 34759c8517c4STomer Tayar static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 34769c8517c4STomer Tayar { 34779c8517c4STomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 34789c8517c4STomer Tayar 34799c8517c4STomer Tayar switch (res_id) { 34809c8517c4STomer Tayar case QED_SB: 34819c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 34829c8517c4STomer Tayar break; 34839c8517c4STomer Tayar case QED_L2_QUEUE: 34849c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 34859c8517c4STomer Tayar break; 34869c8517c4STomer Tayar case QED_VPORT: 34879c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 34889c8517c4STomer Tayar break; 34899c8517c4STomer Tayar case QED_RSS_ENG: 34909c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 34919c8517c4STomer Tayar break; 34929c8517c4STomer Tayar case QED_PQ: 34939c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 34949c8517c4STomer Tayar break; 34959c8517c4STomer Tayar case QED_RL: 34969c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 34979c8517c4STomer Tayar break; 34989c8517c4STomer Tayar case QED_MAC: 34999c8517c4STomer Tayar case QED_VLAN: 35009c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 35019c8517c4STomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 35029c8517c4STomer Tayar break; 35039c8517c4STomer Tayar case QED_ILT: 35049c8517c4STomer Tayar mfw_res_id = RESOURCE_ILT_E; 35059c8517c4STomer Tayar break; 3506997af5dfSMichal Kalderon case QED_LL2_RAM_QUEUE: 35079c8517c4STomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 35089c8517c4STomer Tayar break; 3509997af5dfSMichal Kalderon case QED_LL2_CTX_QUEUE: 3510997af5dfSMichal Kalderon mfw_res_id = RESOURCE_LL2_CQS_E; 3511997af5dfSMichal Kalderon break; 35129c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 35139c8517c4STomer Tayar case QED_CMDQS_CQS: 35149c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 35159c8517c4STomer Tayar mfw_res_id = RESOURCE_CQS_E; 35169c8517c4STomer Tayar break; 35179c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 35189c8517c4STomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 35199c8517c4STomer Tayar break; 35209c8517c4STomer Tayar case QED_BDQ: 35219c8517c4STomer Tayar mfw_res_id = RESOURCE_BDQ_E; 35229c8517c4STomer Tayar break; 35239c8517c4STomer Tayar default: 35249c8517c4STomer Tayar break; 35259c8517c4STomer Tayar } 35269c8517c4STomer Tayar 35279c8517c4STomer Tayar return mfw_res_id; 35289c8517c4STomer Tayar } 35299c8517c4STomer Tayar 35309c8517c4STomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 2 35312edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 35322edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 35332edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 35342edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 35352edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 35362edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 35379c8517c4STomer Tayar 35389c8517c4STomer Tayar struct qed_resc_alloc_in_params { 35399c8517c4STomer Tayar u32 cmd; 35409c8517c4STomer Tayar enum qed_resources res_id; 35419c8517c4STomer Tayar u32 resc_max_val; 35429c8517c4STomer Tayar }; 35439c8517c4STomer Tayar 35449c8517c4STomer Tayar struct qed_resc_alloc_out_params { 35459c8517c4STomer Tayar u32 mcp_resp; 35469c8517c4STomer Tayar u32 mcp_param; 35479c8517c4STomer Tayar u32 resc_num; 35489c8517c4STomer Tayar u32 resc_start; 35499c8517c4STomer Tayar u32 vf_resc_num; 35509c8517c4STomer Tayar u32 vf_resc_start; 35519c8517c4STomer Tayar u32 flags; 35529c8517c4STomer Tayar }; 35539c8517c4STomer Tayar 35549c8517c4STomer Tayar static int 35559c8517c4STomer Tayar qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 35562edbff8dSTomer Tayar struct qed_ptt *p_ptt, 35579c8517c4STomer Tayar struct qed_resc_alloc_in_params *p_in_params, 35589c8517c4STomer Tayar struct qed_resc_alloc_out_params *p_out_params) 35592edbff8dSTomer Tayar { 35602edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 35619c8517c4STomer Tayar struct resource_info mfw_resc_info; 35622edbff8dSTomer Tayar int rc; 35632edbff8dSTomer Tayar 35649c8517c4STomer Tayar memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 3565bb480242SMintz, Yuval 35669c8517c4STomer Tayar mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 35679c8517c4STomer Tayar if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 35689c8517c4STomer Tayar DP_ERR(p_hwfn, 35699c8517c4STomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 35709c8517c4STomer Tayar p_in_params->res_id, 35719c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id)); 35729c8517c4STomer Tayar return -EINVAL; 35739c8517c4STomer Tayar } 35749c8517c4STomer Tayar 35759c8517c4STomer Tayar switch (p_in_params->cmd) { 35769c8517c4STomer Tayar case DRV_MSG_SET_RESOURCE_VALUE_MSG: 35779c8517c4STomer Tayar mfw_resc_info.size = p_in_params->resc_max_val; 3578df561f66SGustavo A. R. Silva fallthrough; 35799c8517c4STomer Tayar case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 35809c8517c4STomer Tayar break; 35819c8517c4STomer Tayar default: 35829c8517c4STomer Tayar DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 35839c8517c4STomer Tayar p_in_params->cmd); 35849c8517c4STomer Tayar return -EINVAL; 35859c8517c4STomer Tayar } 35869c8517c4STomer Tayar 35879c8517c4STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 35889c8517c4STomer Tayar mb_params.cmd = p_in_params->cmd; 35899c8517c4STomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 35909c8517c4STomer Tayar mb_params.p_data_src = &mfw_resc_info; 35919c8517c4STomer Tayar mb_params.data_src_size = sizeof(mfw_resc_info); 35929c8517c4STomer Tayar mb_params.p_data_dst = mb_params.p_data_src; 35939c8517c4STomer Tayar mb_params.data_dst_size = mb_params.data_src_size; 35949c8517c4STomer Tayar 35959c8517c4STomer Tayar DP_VERBOSE(p_hwfn, 35969c8517c4STomer Tayar QED_MSG_SP, 35979c8517c4STomer Tayar "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 35989c8517c4STomer Tayar p_in_params->cmd, 35999c8517c4STomer Tayar p_in_params->res_id, 36009c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id), 36019c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 36029c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 36039c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 36049c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 36059c8517c4STomer Tayar p_in_params->resc_max_val); 36069c8517c4STomer Tayar 36072edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 36082edbff8dSTomer Tayar if (rc) 36092edbff8dSTomer Tayar return rc; 36102edbff8dSTomer Tayar 36119c8517c4STomer Tayar p_out_params->mcp_resp = mb_params.mcp_resp; 36129c8517c4STomer Tayar p_out_params->mcp_param = mb_params.mcp_param; 36139c8517c4STomer Tayar p_out_params->resc_num = mfw_resc_info.size; 36149c8517c4STomer Tayar p_out_params->resc_start = mfw_resc_info.offset; 36159c8517c4STomer Tayar p_out_params->vf_resc_num = mfw_resc_info.vf_size; 36169c8517c4STomer Tayar p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 36179c8517c4STomer Tayar p_out_params->flags = mfw_resc_info.flags; 36182edbff8dSTomer Tayar 36192edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 36202edbff8dSTomer Tayar QED_MSG_SP, 36219c8517c4STomer Tayar "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 36229c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 36239c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 36249c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 36259c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 36269c8517c4STomer Tayar p_out_params->resc_num, 36279c8517c4STomer Tayar p_out_params->resc_start, 36289c8517c4STomer Tayar p_out_params->vf_resc_num, 36299c8517c4STomer Tayar p_out_params->vf_resc_start, p_out_params->flags); 36309c8517c4STomer Tayar 36319c8517c4STomer Tayar return 0; 36329c8517c4STomer Tayar } 36339c8517c4STomer Tayar 36349c8517c4STomer Tayar int 36359c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 36369c8517c4STomer Tayar struct qed_ptt *p_ptt, 36379c8517c4STomer Tayar enum qed_resources res_id, 36389c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 36399c8517c4STomer Tayar { 36409c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 36419c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 36429c8517c4STomer Tayar int rc; 36439c8517c4STomer Tayar 36449c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 36459c8517c4STomer Tayar in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 36469c8517c4STomer Tayar in_params.res_id = res_id; 36479c8517c4STomer Tayar in_params.resc_max_val = resc_max_val; 36489c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 36499c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 36509c8517c4STomer Tayar &out_params); 36519c8517c4STomer Tayar if (rc) 36529c8517c4STomer Tayar return rc; 36539c8517c4STomer Tayar 36549c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 36559c8517c4STomer Tayar 36569c8517c4STomer Tayar return 0; 36579c8517c4STomer Tayar } 36589c8517c4STomer Tayar 36599c8517c4STomer Tayar int 36609c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 36619c8517c4STomer Tayar struct qed_ptt *p_ptt, 36629c8517c4STomer Tayar enum qed_resources res_id, 36639c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 36649c8517c4STomer Tayar { 36659c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 36669c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 36679c8517c4STomer Tayar int rc; 36689c8517c4STomer Tayar 36699c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 36709c8517c4STomer Tayar in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 36719c8517c4STomer Tayar in_params.res_id = res_id; 36729c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 36739c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 36749c8517c4STomer Tayar &out_params); 36759c8517c4STomer Tayar if (rc) 36769c8517c4STomer Tayar return rc; 36779c8517c4STomer Tayar 36789c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 36799c8517c4STomer Tayar 36809c8517c4STomer Tayar if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 36819c8517c4STomer Tayar *p_resc_num = out_params.resc_num; 36829c8517c4STomer Tayar *p_resc_start = out_params.resc_start; 36839c8517c4STomer Tayar } 36842edbff8dSTomer Tayar 36852edbff8dSTomer Tayar return 0; 36862edbff8dSTomer Tayar } 368718a69e36SMintz, Yuval 368818a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 368918a69e36SMintz, Yuval { 369018a69e36SMintz, Yuval u32 mcp_resp, mcp_param; 369118a69e36SMintz, Yuval 369218a69e36SMintz, Yuval return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 369318a69e36SMintz, Yuval &mcp_resp, &mcp_param); 369418a69e36SMintz, Yuval } 369595691c9cSTomer Tayar 369695691c9cSTomer Tayar static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 369795691c9cSTomer Tayar struct qed_ptt *p_ptt, 369895691c9cSTomer Tayar u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 369995691c9cSTomer Tayar { 370095691c9cSTomer Tayar int rc; 370195691c9cSTomer Tayar 3702*ef10bd49SVenkata Sudheer Kumar Bhavaraju rc = qed_mcp_cmd_nosleep(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, 3703*ef10bd49SVenkata Sudheer Kumar Bhavaraju param, p_mcp_resp, p_mcp_param); 370495691c9cSTomer Tayar if (rc) 370595691c9cSTomer Tayar return rc; 370695691c9cSTomer Tayar 370795691c9cSTomer Tayar if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 370895691c9cSTomer Tayar DP_INFO(p_hwfn, 370995691c9cSTomer Tayar "The resource command is unsupported by the MFW\n"); 371095691c9cSTomer Tayar return -EINVAL; 371195691c9cSTomer Tayar } 371295691c9cSTomer Tayar 371395691c9cSTomer Tayar if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 371495691c9cSTomer Tayar u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 371595691c9cSTomer Tayar 371695691c9cSTomer Tayar DP_NOTICE(p_hwfn, 371795691c9cSTomer Tayar "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 371895691c9cSTomer Tayar param, opcode); 371995691c9cSTomer Tayar return -EINVAL; 372095691c9cSTomer Tayar } 372195691c9cSTomer Tayar 372295691c9cSTomer Tayar return rc; 372395691c9cSTomer Tayar } 372495691c9cSTomer Tayar 3725bf774d14SYueHaibing static int 372695691c9cSTomer Tayar __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 372795691c9cSTomer Tayar struct qed_ptt *p_ptt, 372895691c9cSTomer Tayar struct qed_resc_lock_params *p_params) 372995691c9cSTomer Tayar { 373095691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 373195691c9cSTomer Tayar u8 opcode; 373295691c9cSTomer Tayar int rc; 373395691c9cSTomer Tayar 373495691c9cSTomer Tayar switch (p_params->timeout) { 373595691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_DEFAULT: 373695691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ; 373795691c9cSTomer Tayar p_params->timeout = 0; 373895691c9cSTomer Tayar break; 373995691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_NONE: 374095691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_WO_AGING; 374195691c9cSTomer Tayar p_params->timeout = 0; 374295691c9cSTomer Tayar break; 374395691c9cSTomer Tayar default: 374495691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_W_AGING; 374595691c9cSTomer Tayar break; 374695691c9cSTomer Tayar } 374795691c9cSTomer Tayar 374895691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 374995691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 375095691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 375195691c9cSTomer Tayar 375295691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 375395691c9cSTomer Tayar QED_MSG_SP, 375495691c9cSTomer Tayar "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 375595691c9cSTomer Tayar param, p_params->timeout, opcode, p_params->resource); 375695691c9cSTomer Tayar 375795691c9cSTomer Tayar /* Attempt to acquire the resource */ 375895691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 375995691c9cSTomer Tayar if (rc) 376095691c9cSTomer Tayar return rc; 376195691c9cSTomer Tayar 376295691c9cSTomer Tayar /* Analyze the response */ 376395691c9cSTomer Tayar p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 376495691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 376595691c9cSTomer Tayar 376695691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 376795691c9cSTomer Tayar QED_MSG_SP, 376895691c9cSTomer Tayar "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 376995691c9cSTomer Tayar mcp_param, opcode, p_params->owner); 377095691c9cSTomer Tayar 377195691c9cSTomer Tayar switch (opcode) { 377295691c9cSTomer Tayar case RESOURCE_OPCODE_GNT: 377395691c9cSTomer Tayar p_params->b_granted = true; 377495691c9cSTomer Tayar break; 377595691c9cSTomer Tayar case RESOURCE_OPCODE_BUSY: 377695691c9cSTomer Tayar p_params->b_granted = false; 377795691c9cSTomer Tayar break; 377895691c9cSTomer Tayar default: 377995691c9cSTomer Tayar DP_NOTICE(p_hwfn, 378095691c9cSTomer Tayar "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 378195691c9cSTomer Tayar mcp_param, opcode); 378295691c9cSTomer Tayar return -EINVAL; 378395691c9cSTomer Tayar } 378495691c9cSTomer Tayar 378595691c9cSTomer Tayar return 0; 378695691c9cSTomer Tayar } 378795691c9cSTomer Tayar 378895691c9cSTomer Tayar int 378995691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 379095691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 379195691c9cSTomer Tayar { 379295691c9cSTomer Tayar u32 retry_cnt = 0; 379395691c9cSTomer Tayar int rc; 379495691c9cSTomer Tayar 379595691c9cSTomer Tayar do { 379695691c9cSTomer Tayar /* No need for an interval before the first iteration */ 379795691c9cSTomer Tayar if (retry_cnt) { 379895691c9cSTomer Tayar if (p_params->sleep_b4_retry) { 379995691c9cSTomer Tayar u16 retry_interval_in_ms = 380095691c9cSTomer Tayar DIV_ROUND_UP(p_params->retry_interval, 380195691c9cSTomer Tayar 1000); 380295691c9cSTomer Tayar 380395691c9cSTomer Tayar msleep(retry_interval_in_ms); 380495691c9cSTomer Tayar } else { 380595691c9cSTomer Tayar udelay(p_params->retry_interval); 380695691c9cSTomer Tayar } 380795691c9cSTomer Tayar } 380895691c9cSTomer Tayar 380995691c9cSTomer Tayar rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 381095691c9cSTomer Tayar if (rc) 381195691c9cSTomer Tayar return rc; 381295691c9cSTomer Tayar 381395691c9cSTomer Tayar if (p_params->b_granted) 381495691c9cSTomer Tayar break; 381595691c9cSTomer Tayar } while (retry_cnt++ < p_params->retry_num); 381695691c9cSTomer Tayar 381795691c9cSTomer Tayar return 0; 381895691c9cSTomer Tayar } 381995691c9cSTomer Tayar 382095691c9cSTomer Tayar int 382195691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 382295691c9cSTomer Tayar struct qed_ptt *p_ptt, 382395691c9cSTomer Tayar struct qed_resc_unlock_params *p_params) 382495691c9cSTomer Tayar { 382595691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 382695691c9cSTomer Tayar u8 opcode; 382795691c9cSTomer Tayar int rc; 382895691c9cSTomer Tayar 382995691c9cSTomer Tayar opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 383095691c9cSTomer Tayar : RESOURCE_OPCODE_RELEASE; 383195691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 383295691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 383395691c9cSTomer Tayar 383495691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 383595691c9cSTomer Tayar "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 383695691c9cSTomer Tayar param, opcode, p_params->resource); 383795691c9cSTomer Tayar 383895691c9cSTomer Tayar /* Attempt to release the resource */ 383995691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 384095691c9cSTomer Tayar if (rc) 384195691c9cSTomer Tayar return rc; 384295691c9cSTomer Tayar 384395691c9cSTomer Tayar /* Analyze the response */ 384495691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 384595691c9cSTomer Tayar 384695691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 384795691c9cSTomer Tayar "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 384895691c9cSTomer Tayar mcp_param, opcode); 384995691c9cSTomer Tayar 385095691c9cSTomer Tayar switch (opcode) { 385195691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED_PREVIOUS: 385295691c9cSTomer Tayar DP_INFO(p_hwfn, 385395691c9cSTomer Tayar "Resource unlock request for an already released resource [%d]\n", 385495691c9cSTomer Tayar p_params->resource); 3855df561f66SGustavo A. R. Silva fallthrough; 385695691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED: 385795691c9cSTomer Tayar p_params->b_released = true; 385895691c9cSTomer Tayar break; 385995691c9cSTomer Tayar case RESOURCE_OPCODE_WRONG_OWNER: 386095691c9cSTomer Tayar p_params->b_released = false; 386195691c9cSTomer Tayar break; 386295691c9cSTomer Tayar default: 386395691c9cSTomer Tayar DP_NOTICE(p_hwfn, 386495691c9cSTomer Tayar "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 386595691c9cSTomer Tayar mcp_param, opcode); 386695691c9cSTomer Tayar return -EINVAL; 386795691c9cSTomer Tayar } 386895691c9cSTomer Tayar 386995691c9cSTomer Tayar return 0; 387095691c9cSTomer Tayar } 3871f470f22cSsudarsana.kalluru@cavium.com 3872f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3873f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 3874f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 3875f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent) 3876f470f22cSsudarsana.kalluru@cavium.com { 3877f470f22cSsudarsana.kalluru@cavium.com if (p_lock) { 3878f470f22cSsudarsana.kalluru@cavium.com memset(p_lock, 0, sizeof(*p_lock)); 3879f470f22cSsudarsana.kalluru@cavium.com 3880f470f22cSsudarsana.kalluru@cavium.com /* Permanent resources don't require aging, and there's no 3881f470f22cSsudarsana.kalluru@cavium.com * point in trying to acquire them more than once since it's 3882f470f22cSsudarsana.kalluru@cavium.com * unexpected another entity would release them. 3883f470f22cSsudarsana.kalluru@cavium.com */ 3884f470f22cSsudarsana.kalluru@cavium.com if (b_is_permanent) { 3885f470f22cSsudarsana.kalluru@cavium.com p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3886f470f22cSsudarsana.kalluru@cavium.com } else { 3887f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3888f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_interval = 3889f470f22cSsudarsana.kalluru@cavium.com QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3890f470f22cSsudarsana.kalluru@cavium.com p_lock->sleep_b4_retry = true; 3891f470f22cSsudarsana.kalluru@cavium.com } 3892f470f22cSsudarsana.kalluru@cavium.com 3893f470f22cSsudarsana.kalluru@cavium.com p_lock->resource = resource; 3894f470f22cSsudarsana.kalluru@cavium.com } 3895f470f22cSsudarsana.kalluru@cavium.com 3896f470f22cSsudarsana.kalluru@cavium.com if (p_unlock) { 3897f470f22cSsudarsana.kalluru@cavium.com memset(p_unlock, 0, sizeof(*p_unlock)); 3898f470f22cSsudarsana.kalluru@cavium.com p_unlock->resource = resource; 3899f470f22cSsudarsana.kalluru@cavium.com } 3900f470f22cSsudarsana.kalluru@cavium.com } 3901645874e5SSudarsana Reddy Kalluru 3902df9c716dSSudarsana Reddy Kalluru bool qed_mcp_is_smart_an_supported(struct qed_hwfn *p_hwfn) 3903df9c716dSSudarsana Reddy Kalluru { 3904df9c716dSSudarsana Reddy Kalluru return !!(p_hwfn->mcp_info->capabilities & 3905df9c716dSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ); 3906df9c716dSSudarsana Reddy Kalluru } 3907df9c716dSSudarsana Reddy Kalluru 3908645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3909645874e5SSudarsana Reddy Kalluru { 3910645874e5SSudarsana Reddy Kalluru u32 mcp_resp; 3911645874e5SSudarsana Reddy Kalluru int rc; 3912645874e5SSudarsana Reddy Kalluru 3913645874e5SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3914645874e5SSudarsana Reddy Kalluru 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3915645874e5SSudarsana Reddy Kalluru if (!rc) 3916645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3917645874e5SSudarsana Reddy Kalluru "MFW supported features: %08x\n", 3918645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->capabilities); 3919645874e5SSudarsana Reddy Kalluru 3920645874e5SSudarsana Reddy Kalluru return rc; 3921645874e5SSudarsana Reddy Kalluru } 3922645874e5SSudarsana Reddy Kalluru 3923645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3924645874e5SSudarsana Reddy Kalluru { 3925645874e5SSudarsana Reddy Kalluru u32 mcp_resp, mcp_param, features; 3926645874e5SSudarsana Reddy Kalluru 3927e40a826aSSudarsana Reddy Kalluru features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE | 3928ae7e6937SAlexander Lobakin DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK | 3929ae7e6937SAlexander Lobakin DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL; 3930645874e5SSudarsana Reddy Kalluru 3931645874e5SSudarsana Reddy Kalluru return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3932645874e5SSudarsana Reddy Kalluru features, &mcp_resp, &mcp_param); 3933645874e5SSudarsana Reddy Kalluru } 393479284adeSMichal Kalderon 393579284adeSMichal Kalderon int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 393679284adeSMichal Kalderon { 393779284adeSMichal Kalderon struct qed_mcp_mb_params mb_params = {0}; 393879284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 393979284adeSMichal Kalderon u8 fir_valid, l2_valid; 394079284adeSMichal Kalderon int rc; 394179284adeSMichal Kalderon 394279284adeSMichal Kalderon mb_params.cmd = DRV_MSG_CODE_GET_ENGINE_CONFIG; 394379284adeSMichal Kalderon rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 394479284adeSMichal Kalderon if (rc) 394579284adeSMichal Kalderon return rc; 394679284adeSMichal Kalderon 394779284adeSMichal Kalderon if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 394879284adeSMichal Kalderon DP_INFO(p_hwfn, 394979284adeSMichal Kalderon "The get_engine_config command is unsupported by the MFW\n"); 395079284adeSMichal Kalderon return -EOPNOTSUPP; 395179284adeSMichal Kalderon } 395279284adeSMichal Kalderon 395379284adeSMichal Kalderon fir_valid = QED_MFW_GET_FIELD(mb_params.mcp_param, 395479284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID); 395579284adeSMichal Kalderon if (fir_valid) 395679284adeSMichal Kalderon cdev->fir_affin = 395779284adeSMichal Kalderon QED_MFW_GET_FIELD(mb_params.mcp_param, 395879284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE); 395979284adeSMichal Kalderon 396079284adeSMichal Kalderon l2_valid = QED_MFW_GET_FIELD(mb_params.mcp_param, 396179284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID); 396279284adeSMichal Kalderon if (l2_valid) 396379284adeSMichal Kalderon cdev->l2_affin_hint = 396479284adeSMichal Kalderon QED_MFW_GET_FIELD(mb_params.mcp_param, 396579284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE); 396679284adeSMichal Kalderon 396779284adeSMichal Kalderon DP_INFO(p_hwfn, 396879284adeSMichal Kalderon "Engine affinity config: FIR={valid %hhd, value %hhd}, L2_hint={valid %hhd, value %hhd}\n", 396979284adeSMichal Kalderon fir_valid, cdev->fir_affin, l2_valid, cdev->l2_affin_hint); 397079284adeSMichal Kalderon 397179284adeSMichal Kalderon return 0; 397279284adeSMichal Kalderon } 397379284adeSMichal Kalderon 397479284adeSMichal Kalderon int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 397579284adeSMichal Kalderon { 397679284adeSMichal Kalderon struct qed_mcp_mb_params mb_params = {0}; 397779284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 397879284adeSMichal Kalderon int rc; 397979284adeSMichal Kalderon 398079284adeSMichal Kalderon mb_params.cmd = DRV_MSG_CODE_GET_PPFID_BITMAP; 398179284adeSMichal Kalderon rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 398279284adeSMichal Kalderon if (rc) 398379284adeSMichal Kalderon return rc; 398479284adeSMichal Kalderon 398579284adeSMichal Kalderon if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 398679284adeSMichal Kalderon DP_INFO(p_hwfn, 398779284adeSMichal Kalderon "The get_ppfid_bitmap command is unsupported by the MFW\n"); 398879284adeSMichal Kalderon return -EOPNOTSUPP; 398979284adeSMichal Kalderon } 399079284adeSMichal Kalderon 399179284adeSMichal Kalderon cdev->ppfid_bitmap = QED_MFW_GET_FIELD(mb_params.mcp_param, 399279284adeSMichal Kalderon FW_MB_PARAM_PPFID_BITMAP); 399379284adeSMichal Kalderon 399479284adeSMichal Kalderon DP_VERBOSE(p_hwfn, QED_MSG_SP, "PPFID bitmap 0x%hhx\n", 399579284adeSMichal Kalderon cdev->ppfid_bitmap); 399679284adeSMichal Kalderon 399779284adeSMichal Kalderon return 0; 399879284adeSMichal Kalderon } 399938eabdf0SSudarsana Reddy Kalluru 40002d4c8495SSudarsana Reddy Kalluru int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 40012d4c8495SSudarsana Reddy Kalluru u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 40022d4c8495SSudarsana Reddy Kalluru u32 *p_len) 40032d4c8495SSudarsana Reddy Kalluru { 40042d4c8495SSudarsana Reddy Kalluru u32 mb_param = 0, resp, param; 40052d4c8495SSudarsana Reddy Kalluru int rc; 40062d4c8495SSudarsana Reddy Kalluru 40072d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id); 40082d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_INIT) 40092d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 40102d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1); 40112d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_FREE) 40122d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 40132d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1); 40142d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) { 40152d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 40162d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1); 40172d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 40182d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID, 40192d4c8495SSudarsana Reddy Kalluru entity_id); 40202d4c8495SSudarsana Reddy Kalluru } 40212d4c8495SSudarsana Reddy Kalluru 40222d4c8495SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 40232d4c8495SSudarsana Reddy Kalluru DRV_MSG_CODE_GET_NVM_CFG_OPTION, 40246c95dd8fSPrabhakar Kushwaha mb_param, &resp, ¶m, p_len, 40256c95dd8fSPrabhakar Kushwaha (u32 *)p_buf, false); 40262d4c8495SSudarsana Reddy Kalluru 40272d4c8495SSudarsana Reddy Kalluru return rc; 40282d4c8495SSudarsana Reddy Kalluru } 40292d4c8495SSudarsana Reddy Kalluru 403038eabdf0SSudarsana Reddy Kalluru int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 403138eabdf0SSudarsana Reddy Kalluru u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 403238eabdf0SSudarsana Reddy Kalluru u32 len) 403338eabdf0SSudarsana Reddy Kalluru { 403438eabdf0SSudarsana Reddy Kalluru u32 mb_param = 0, resp, param; 403538eabdf0SSudarsana Reddy Kalluru 403638eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id); 403738eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ALL) 403838eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 403938eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ALL, 1); 404038eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_INIT) 404138eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 404238eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1); 404338eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_COMMIT) 404438eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 404538eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT, 1); 404638eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_FREE) 404738eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 404838eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1); 404938eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) { 405038eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 405138eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1); 405238eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 405338eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID, 405438eabdf0SSudarsana Reddy Kalluru entity_id); 405538eabdf0SSudarsana Reddy Kalluru } 405638eabdf0SSudarsana Reddy Kalluru 405738eabdf0SSudarsana Reddy Kalluru return qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, 405838eabdf0SSudarsana Reddy Kalluru DRV_MSG_CODE_SET_NVM_CFG_OPTION, 405938eabdf0SSudarsana Reddy Kalluru mb_param, &resp, ¶m, len, (u32 *)p_buf); 406038eabdf0SSudarsana Reddy Kalluru } 4061d8d6c5a7SIgor Russkikh 4062d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_SIZE MCP_DRV_NVM_BUF_LEN 4063d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_HEADER_SIZE sizeof(u32) 4064d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE \ 4065d8d6c5a7SIgor Russkikh (QED_MCP_DBG_DATA_MAX_SIZE - QED_MCP_DBG_DATA_MAX_HEADER_SIZE) 4066d8d6c5a7SIgor Russkikh 4067d8d6c5a7SIgor Russkikh static int 4068d8d6c5a7SIgor Russkikh __qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn, 4069d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, u8 *p_buf, u8 size) 4070d8d6c5a7SIgor Russkikh { 4071d8d6c5a7SIgor Russkikh struct qed_mcp_mb_params mb_params; 4072d8d6c5a7SIgor Russkikh int rc; 4073d8d6c5a7SIgor Russkikh 4074d8d6c5a7SIgor Russkikh if (size > QED_MCP_DBG_DATA_MAX_SIZE) { 4075d8d6c5a7SIgor Russkikh DP_ERR(p_hwfn, 4076d8d6c5a7SIgor Russkikh "Debug data size is %d while it should not exceed %d\n", 4077d8d6c5a7SIgor Russkikh size, QED_MCP_DBG_DATA_MAX_SIZE); 4078d8d6c5a7SIgor Russkikh return -EINVAL; 4079d8d6c5a7SIgor Russkikh } 4080d8d6c5a7SIgor Russkikh 4081d8d6c5a7SIgor Russkikh memset(&mb_params, 0, sizeof(mb_params)); 4082d8d6c5a7SIgor Russkikh mb_params.cmd = DRV_MSG_CODE_DEBUG_DATA_SEND; 4083d8d6c5a7SIgor Russkikh SET_MFW_FIELD(mb_params.param, DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE, size); 4084d8d6c5a7SIgor Russkikh mb_params.p_data_src = p_buf; 4085d8d6c5a7SIgor Russkikh mb_params.data_src_size = size; 4086d8d6c5a7SIgor Russkikh rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 4087d8d6c5a7SIgor Russkikh if (rc) 4088d8d6c5a7SIgor Russkikh return rc; 4089d8d6c5a7SIgor Russkikh 4090d8d6c5a7SIgor Russkikh if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 4091d8d6c5a7SIgor Russkikh DP_INFO(p_hwfn, 4092d8d6c5a7SIgor Russkikh "The DEBUG_DATA_SEND command is unsupported by the MFW\n"); 4093d8d6c5a7SIgor Russkikh return -EOPNOTSUPP; 4094d8d6c5a7SIgor Russkikh } else if (mb_params.mcp_resp == (u32)FW_MSG_CODE_DEBUG_NOT_ENABLED) { 4095d8d6c5a7SIgor Russkikh DP_INFO(p_hwfn, "The DEBUG_DATA_SEND command is not enabled\n"); 4096d8d6c5a7SIgor Russkikh return -EBUSY; 4097d8d6c5a7SIgor Russkikh } else if (mb_params.mcp_resp != (u32)FW_MSG_CODE_DEBUG_DATA_SEND_OK) { 4098d8d6c5a7SIgor Russkikh DP_NOTICE(p_hwfn, 4099d8d6c5a7SIgor Russkikh "Failed to send debug data to the MFW [resp 0x%08x]\n", 4100d8d6c5a7SIgor Russkikh mb_params.mcp_resp); 4101d8d6c5a7SIgor Russkikh return -EINVAL; 4102d8d6c5a7SIgor Russkikh } 4103d8d6c5a7SIgor Russkikh 4104d8d6c5a7SIgor Russkikh return 0; 4105d8d6c5a7SIgor Russkikh } 4106d8d6c5a7SIgor Russkikh 4107d8d6c5a7SIgor Russkikh enum qed_mcp_dbg_data_type { 4108d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_TYPE_RAW, 4109d8d6c5a7SIgor Russkikh }; 4110d8d6c5a7SIgor Russkikh 4111d8d6c5a7SIgor Russkikh /* Header format: [31:28] PFID, [27:20] flags, [19:12] type, [11:0] S/N */ 4112d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_SN_OFFSET 0 4113d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_SN_MASK 0x00000fff 4114d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_TYPE_OFFSET 12 4115d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_TYPE_MASK 0x000ff000 4116d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_OFFSET 20 4117d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_MASK 0x0ff00000 4118d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_PF_OFFSET 28 4119d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_PF_MASK 0xf0000000 4120d8d6c5a7SIgor Russkikh 4121d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_FIRST 0x1 4122d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_LAST 0x2 4123d8d6c5a7SIgor Russkikh 4124d8d6c5a7SIgor Russkikh static int 4125d8d6c5a7SIgor Russkikh qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn, 4126d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, 4127d8d6c5a7SIgor Russkikh enum qed_mcp_dbg_data_type type, u8 *p_buf, u32 size) 4128d8d6c5a7SIgor Russkikh { 4129d8d6c5a7SIgor Russkikh u8 raw_data[QED_MCP_DBG_DATA_MAX_SIZE], *p_tmp_buf = p_buf; 4130d8d6c5a7SIgor Russkikh u32 tmp_size = size, *p_header, *p_payload; 4131d8d6c5a7SIgor Russkikh u8 flags = 0; 4132d8d6c5a7SIgor Russkikh u16 seq; 4133d8d6c5a7SIgor Russkikh int rc; 4134d8d6c5a7SIgor Russkikh 4135d8d6c5a7SIgor Russkikh p_header = (u32 *)raw_data; 4136d8d6c5a7SIgor Russkikh p_payload = (u32 *)(raw_data + QED_MCP_DBG_DATA_MAX_HEADER_SIZE); 4137d8d6c5a7SIgor Russkikh 4138d8d6c5a7SIgor Russkikh seq = (u16)atomic_inc_return(&p_hwfn->mcp_info->dbg_data_seq); 4139d8d6c5a7SIgor Russkikh 4140d8d6c5a7SIgor Russkikh /* First chunk is marked as 'first' */ 4141d8d6c5a7SIgor Russkikh flags |= QED_MCP_DBG_DATA_HDR_FLAGS_FIRST; 4142d8d6c5a7SIgor Russkikh 4143d8d6c5a7SIgor Russkikh *p_header = 0; 4144d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_SN, seq); 4145d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_TYPE, type); 4146d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags); 4147d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_PF, p_hwfn->abs_pf_id); 4148d8d6c5a7SIgor Russkikh 4149d8d6c5a7SIgor Russkikh while (tmp_size > QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE) { 4150d8d6c5a7SIgor Russkikh memcpy(p_payload, p_tmp_buf, QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE); 4151d8d6c5a7SIgor Russkikh rc = __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data, 4152d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_MAX_SIZE); 4153d8d6c5a7SIgor Russkikh if (rc) 4154d8d6c5a7SIgor Russkikh return rc; 4155d8d6c5a7SIgor Russkikh 4156d8d6c5a7SIgor Russkikh /* Clear the 'first' marking after sending the first chunk */ 4157d8d6c5a7SIgor Russkikh if (p_tmp_buf == p_buf) { 4158d8d6c5a7SIgor Russkikh flags &= ~QED_MCP_DBG_DATA_HDR_FLAGS_FIRST; 4159d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, 4160d8d6c5a7SIgor Russkikh flags); 4161d8d6c5a7SIgor Russkikh } 4162d8d6c5a7SIgor Russkikh 4163d8d6c5a7SIgor Russkikh p_tmp_buf += QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE; 4164d8d6c5a7SIgor Russkikh tmp_size -= QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE; 4165d8d6c5a7SIgor Russkikh } 4166d8d6c5a7SIgor Russkikh 4167d8d6c5a7SIgor Russkikh /* Last chunk is marked as 'last' */ 4168d8d6c5a7SIgor Russkikh flags |= QED_MCP_DBG_DATA_HDR_FLAGS_LAST; 4169d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags); 4170d8d6c5a7SIgor Russkikh memcpy(p_payload, p_tmp_buf, tmp_size); 4171d8d6c5a7SIgor Russkikh 4172d8d6c5a7SIgor Russkikh /* Casting the left size to u8 is ok since at this point it is <= 32 */ 4173d8d6c5a7SIgor Russkikh return __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data, 4174d8d6c5a7SIgor Russkikh (u8)(QED_MCP_DBG_DATA_MAX_HEADER_SIZE + 4175d8d6c5a7SIgor Russkikh tmp_size)); 4176d8d6c5a7SIgor Russkikh } 4177d8d6c5a7SIgor Russkikh 4178d8d6c5a7SIgor Russkikh int 4179d8d6c5a7SIgor Russkikh qed_mcp_send_raw_debug_data(struct qed_hwfn *p_hwfn, 4180d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, u8 *p_buf, u32 size) 4181d8d6c5a7SIgor Russkikh { 4182d8d6c5a7SIgor Russkikh return qed_mcp_send_debug_data(p_hwfn, p_ptt, 4183d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_TYPE_RAW, p_buf, size); 4184d8d6c5a7SIgor Russkikh } 4185823163baSManish Chopra 4186823163baSManish Chopra bool qed_mcp_is_esl_supported(struct qed_hwfn *p_hwfn) 4187823163baSManish Chopra { 4188823163baSManish Chopra return !!(p_hwfn->mcp_info->capabilities & 4189823163baSManish Chopra FW_MB_PARAM_FEATURE_SUPPORT_ENHANCED_SYS_LCK); 4190823163baSManish Chopra } 4191823163baSManish Chopra 4192823163baSManish Chopra int qed_mcp_get_esl_status(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool *active) 4193823163baSManish Chopra { 4194823163baSManish Chopra u32 resp = 0, param = 0; 4195823163baSManish Chopra int rc; 4196823163baSManish Chopra 4197823163baSManish Chopra rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MANAGEMENT_STATUS, 0, &resp, ¶m); 4198823163baSManish Chopra if (rc) { 4199823163baSManish Chopra DP_NOTICE(p_hwfn, "Failed to send ESL command, rc = %d\n", rc); 4200823163baSManish Chopra return rc; 4201823163baSManish Chopra } 4202823163baSManish Chopra 4203823163baSManish Chopra *active = !!(param & FW_MB_PARAM_MANAGEMENT_STATUS_LOCKDOWN_ENABLED); 4204823163baSManish Chopra 4205823163baSManish Chopra return 0; 4206823163baSManish Chopra } 4207