1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/delay.h> 36fe56b9e6SYuval Mintz #include <linux/errno.h> 37fe56b9e6SYuval Mintz #include <linux/kernel.h> 38fe56b9e6SYuval Mintz #include <linux/slab.h> 395529bad9STomer Tayar #include <linux/spinlock.h> 40fe56b9e6SYuval Mintz #include <linux/string.h> 410fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 42fe56b9e6SYuval Mintz #include "qed.h" 43cac6f691SSudarsana Reddy Kalluru #include "qed_cxt.h" 4439651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 45fe56b9e6SYuval Mintz #include "qed_hsi.h" 46fe56b9e6SYuval Mintz #include "qed_hw.h" 47fe56b9e6SYuval Mintz #include "qed_mcp.h" 48fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 491408cc1fSYuval Mintz #include "qed_sriov.h" 501408cc1fSYuval Mintz 51eaa50fc5STomer Tayar #define QED_MCP_RESP_ITER_US 10 52fe56b9e6SYuval Mintz 53fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 54fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 57fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 58fe56b9e6SYuval Mintz _val) 59fe56b9e6SYuval Mintz 60fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 61fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 62fe56b9e6SYuval Mintz 63fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 64fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 65fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 66fe56b9e6SYuval Mintz 67fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 68fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 69fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 70fe56b9e6SYuval Mintz 71fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 72fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 73fe56b9e6SYuval Mintz 74fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 77fe56b9e6SYuval Mintz { 78fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 79fe56b9e6SYuval Mintz return false; 80fe56b9e6SYuval Mintz return true; 81fe56b9e6SYuval Mintz } 82fe56b9e6SYuval Mintz 831a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 84fe56b9e6SYuval Mintz { 85fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 86fe56b9e6SYuval Mintz PUBLIC_PORT); 87fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 88fe56b9e6SYuval Mintz 89fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 90fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 91fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 92fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 93fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 94fe56b9e6SYuval Mintz } 95fe56b9e6SYuval Mintz 961a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 97fe56b9e6SYuval Mintz { 98fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 99fe56b9e6SYuval Mintz u32 tmp, i; 100fe56b9e6SYuval Mintz 101fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 102fe56b9e6SYuval Mintz return; 103fe56b9e6SYuval Mintz 104fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 105fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 106fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 107fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 108fe56b9e6SYuval Mintz 109fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 110fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 111fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 112fe56b9e6SYuval Mintz } 113fe56b9e6SYuval Mintz } 114fe56b9e6SYuval Mintz 1154ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 1164ed1eea8STomer Tayar struct list_head list; 1174ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 1184ed1eea8STomer Tayar u16 expected_seq_num; 1194ed1eea8STomer Tayar bool b_is_completed; 1204ed1eea8STomer Tayar }; 1214ed1eea8STomer Tayar 1224ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1234ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1244ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1254ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1264ed1eea8STomer Tayar u16 expected_seq_num) 1274ed1eea8STomer Tayar { 1284ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1294ed1eea8STomer Tayar 1304ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1314ed1eea8STomer Tayar if (!p_cmd_elem) 1324ed1eea8STomer Tayar goto out; 1334ed1eea8STomer Tayar 1344ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1354ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1364ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1374ed1eea8STomer Tayar out: 1384ed1eea8STomer Tayar return p_cmd_elem; 1394ed1eea8STomer Tayar } 1404ed1eea8STomer Tayar 1414ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1424ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1434ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1444ed1eea8STomer Tayar { 1454ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1464ed1eea8STomer Tayar kfree(p_cmd_elem); 1474ed1eea8STomer Tayar } 1484ed1eea8STomer Tayar 1494ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1504ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1514ed1eea8STomer Tayar u16 seq_num) 1524ed1eea8STomer Tayar { 1534ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1544ed1eea8STomer Tayar 1554ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1564ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1574ed1eea8STomer Tayar return p_cmd_elem; 1584ed1eea8STomer Tayar } 1594ed1eea8STomer Tayar 1604ed1eea8STomer Tayar return NULL; 1614ed1eea8STomer Tayar } 1624ed1eea8STomer Tayar 163fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 164fe56b9e6SYuval Mintz { 165fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1664ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1674ed1eea8STomer Tayar 168fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 169fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1704ed1eea8STomer Tayar 1714ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1724ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1734ed1eea8STomer Tayar p_tmp, 1744ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1754ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 176fe56b9e6SYuval Mintz } 1774ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1784ed1eea8STomer Tayar } 1794ed1eea8STomer Tayar 180fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 1813587cb87STomer Tayar p_hwfn->mcp_info = NULL; 182fe56b9e6SYuval Mintz 183fe56b9e6SYuval Mintz return 0; 184fe56b9e6SYuval Mintz } 185fe56b9e6SYuval Mintz 186f00d25f3STomer Tayar /* Maximum of 1 sec to wait for the SHMEM ready indication */ 187f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_MAX_RETRIES 20 188f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_ITER_MS 50 189f00d25f3STomer Tayar 1901a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 191fe56b9e6SYuval Mintz { 192fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 193f00d25f3STomer Tayar u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES; 194f00d25f3STomer Tayar u8 msec = QED_MCP_SHMEM_RDY_ITER_MS; 195fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 196fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 197fe56b9e6SYuval Mintz 198fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 199f00d25f3STomer Tayar if (!p_info->public_base) { 200f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 201f00d25f3STomer Tayar "The address of the MCP scratch-pad is not configured\n"); 202f00d25f3STomer Tayar return -EINVAL; 203f00d25f3STomer Tayar } 204fe56b9e6SYuval Mintz 205fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 206fe56b9e6SYuval Mintz 207f00d25f3STomer Tayar /* Get the MFW MB address and number of supported messages */ 208f00d25f3STomer Tayar mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 209f00d25f3STomer Tayar SECTION_OFFSIZE_ADDR(p_info->public_base, 210f00d25f3STomer Tayar PUBLIC_MFW_MB)); 211f00d25f3STomer Tayar p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 212f00d25f3STomer Tayar p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, 213f00d25f3STomer Tayar p_info->mfw_mb_addr + 214f00d25f3STomer Tayar offsetof(struct public_mfw_mb, 215f00d25f3STomer Tayar sup_msgs)); 216f00d25f3STomer Tayar 217f00d25f3STomer Tayar /* The driver can notify that there was an MCP reset, and might read the 218f00d25f3STomer Tayar * SHMEM values before the MFW has completed initializing them. 219f00d25f3STomer Tayar * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a 220f00d25f3STomer Tayar * data ready indication. 221f00d25f3STomer Tayar */ 222f00d25f3STomer Tayar while (!p_info->mfw_mb_length && --cnt) { 223f00d25f3STomer Tayar msleep(msec); 224f00d25f3STomer Tayar p_info->mfw_mb_length = 225f00d25f3STomer Tayar (u16)qed_rd(p_hwfn, p_ptt, 226f00d25f3STomer Tayar p_info->mfw_mb_addr + 227f00d25f3STomer Tayar offsetof(struct public_mfw_mb, sup_msgs)); 228f00d25f3STomer Tayar } 229f00d25f3STomer Tayar 230f00d25f3STomer Tayar if (!cnt) { 231f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 232f00d25f3STomer Tayar "Failed to get the SHMEM ready notification after %d msec\n", 233f00d25f3STomer Tayar QED_MCP_SHMEM_RDY_MAX_RETRIES * msec); 234f00d25f3STomer Tayar return -EBUSY; 235f00d25f3STomer Tayar } 236f00d25f3STomer Tayar 237fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 238fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 239fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 240fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 241fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 242fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 243fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 244fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 245fe56b9e6SYuval Mintz 246fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 247fe56b9e6SYuval Mintz * the first command 248fe56b9e6SYuval Mintz */ 249fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 250fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 251fe56b9e6SYuval Mintz 252fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 253fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 254fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 255fe56b9e6SYuval Mintz 2564ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 257fe56b9e6SYuval Mintz 258fe56b9e6SYuval Mintz return 0; 259fe56b9e6SYuval Mintz } 260fe56b9e6SYuval Mintz 2611a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 262fe56b9e6SYuval Mintz { 263fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 264fe56b9e6SYuval Mintz u32 size; 265fe56b9e6SYuval Mintz 266fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 26760fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 268fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 269fe56b9e6SYuval Mintz goto err; 270fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 271fe56b9e6SYuval Mintz 2724ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2734ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2744ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2754ed1eea8STomer Tayar 2764ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2774ed1eea8STomer Tayar 278fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 279fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 280fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 281fe56b9e6SYuval Mintz * the MCP is not initialized 282fe56b9e6SYuval Mintz */ 283fe56b9e6SYuval Mintz return 0; 284fe56b9e6SYuval Mintz } 285fe56b9e6SYuval Mintz 286fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 28760fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 28883aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 289eb2a6b80SChristophe Jaillet if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 290fe56b9e6SYuval Mintz goto err; 291fe56b9e6SYuval Mintz 292fe56b9e6SYuval Mintz return 0; 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz err: 295fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 296fe56b9e6SYuval Mintz return -ENOMEM; 297fe56b9e6SYuval Mintz } 298fe56b9e6SYuval Mintz 2994ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 3004ed1eea8STomer Tayar struct qed_ptt *p_ptt) 3015529bad9STomer Tayar { 3024ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3035529bad9STomer Tayar 3044ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 3054ed1eea8STomer Tayar * time and now. 3065529bad9STomer Tayar */ 3074ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 3084ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 3094ed1eea8STomer Tayar QED_MSG_SP, 3104ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 3114ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 3125529bad9STomer Tayar 3134ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 3144ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 3155529bad9STomer Tayar } 3165529bad9STomer Tayar } 3175529bad9STomer Tayar 3181a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 319fe56b9e6SYuval Mintz { 320eaa50fc5STomer Tayar u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0; 321fe56b9e6SYuval Mintz int rc = 0; 322fe56b9e6SYuval Mintz 3234ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 3244ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 3254ed1eea8STomer Tayar 3264ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3275529bad9STomer Tayar 328fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 3294ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 3304ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 3314ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 332fe56b9e6SYuval Mintz 333fe56b9e6SYuval Mintz do { 334fe56b9e6SYuval Mintz /* Wait for MFW response */ 335fe56b9e6SYuval Mintz udelay(delay); 336fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 337fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 338fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 339fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 340fe56b9e6SYuval Mintz 341fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 342fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 343fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 344fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 345fe56b9e6SYuval Mintz } else { 346fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 347fe56b9e6SYuval Mintz rc = -EAGAIN; 348fe56b9e6SYuval Mintz } 349fe56b9e6SYuval Mintz 3504ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3515529bad9STomer Tayar 352fe56b9e6SYuval Mintz return rc; 353fe56b9e6SYuval Mintz } 354fe56b9e6SYuval Mintz 3554ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3564ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 357fe56b9e6SYuval Mintz { 3584ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3594ed1eea8STomer Tayar 3604ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3614ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3624ed1eea8STomer Tayar */ 3634ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3644ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3654ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3664ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3674ed1eea8STomer Tayar } 3684ed1eea8STomer Tayar 3694ed1eea8STomer Tayar return false; 3704ed1eea8STomer Tayar } 3714ed1eea8STomer Tayar 3724ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3734ed1eea8STomer Tayar static int 3744ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3754ed1eea8STomer Tayar { 3764ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3774ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3784ed1eea8STomer Tayar u32 mcp_resp; 3794ed1eea8STomer Tayar u16 seq_num; 3804ed1eea8STomer Tayar 3814ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3824ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3834ed1eea8STomer Tayar 3844ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3854ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3864ed1eea8STomer Tayar return -EAGAIN; 3874ed1eea8STomer Tayar 3884ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3894ed1eea8STomer Tayar if (!p_cmd_elem) { 3904ed1eea8STomer Tayar DP_ERR(p_hwfn, 3914ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 3924ed1eea8STomer Tayar seq_num); 3934ed1eea8STomer Tayar return -EINVAL; 3944ed1eea8STomer Tayar } 3954ed1eea8STomer Tayar 3964ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 3974ed1eea8STomer Tayar 3984ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 3994ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 4004ed1eea8STomer Tayar 4014ed1eea8STomer Tayar /* Get the MFW param */ 4024ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 4034ed1eea8STomer Tayar 4044ed1eea8STomer Tayar /* Get the union data */ 4052f67af8cSTomer Tayar if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 4064ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4074ed1eea8STomer Tayar offsetof(struct public_drv_mb, 4084ed1eea8STomer Tayar union_data); 4094ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 4102f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 4114ed1eea8STomer Tayar } 4124ed1eea8STomer Tayar 4134ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 4144ed1eea8STomer Tayar 4154ed1eea8STomer Tayar return 0; 4164ed1eea8STomer Tayar } 4174ed1eea8STomer Tayar 4184ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 4194ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4204ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4214ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4224ed1eea8STomer Tayar u16 seq_num) 4234ed1eea8STomer Tayar { 4244ed1eea8STomer Tayar union drv_union_data union_data; 4254ed1eea8STomer Tayar u32 union_data_addr; 4264ed1eea8STomer Tayar 4274ed1eea8STomer Tayar /* Set the union data */ 4284ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4294ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 4304ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 4312f67af8cSTomer Tayar if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 4324ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 4332f67af8cSTomer Tayar p_mb_params->data_src_size); 4344ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4354ed1eea8STomer Tayar sizeof(union_data)); 4364ed1eea8STomer Tayar 4374ed1eea8STomer Tayar /* Set the drv param */ 4384ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4394ed1eea8STomer Tayar 4404ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4414ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4424ed1eea8STomer Tayar 4434ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4444ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4454ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4464ed1eea8STomer Tayar } 4474ed1eea8STomer Tayar 4484ed1eea8STomer Tayar static int 4494ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4504ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4514ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 452eaa50fc5STomer Tayar u32 max_retries, u32 usecs) 4534ed1eea8STomer Tayar { 454eaa50fc5STomer Tayar u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000); 4554ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4564ed1eea8STomer Tayar u16 seq_num; 457fe56b9e6SYuval Mintz int rc = 0; 458fe56b9e6SYuval Mintz 4594ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 460fe56b9e6SYuval Mintz do { 4614ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4624ed1eea8STomer Tayar * pending command is completed during this iteration. 4634ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4644ed1eea8STomer Tayar */ 4654ed1eea8STomer Tayar 4664ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4674ed1eea8STomer Tayar 4684ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 4694ed1eea8STomer Tayar break; 4704ed1eea8STomer Tayar 4714ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 4724ed1eea8STomer Tayar if (!rc) 4734ed1eea8STomer Tayar break; 4744ed1eea8STomer Tayar else if (rc != -EAGAIN) 4754ed1eea8STomer Tayar goto err; 4764ed1eea8STomer Tayar 4774ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 478eaa50fc5STomer Tayar 479eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 480eaa50fc5STomer Tayar msleep(msecs); 481eaa50fc5STomer Tayar else 482eaa50fc5STomer Tayar udelay(usecs); 4834ed1eea8STomer Tayar } while (++cnt < max_retries); 484fe56b9e6SYuval Mintz 4854ed1eea8STomer Tayar if (cnt >= max_retries) { 4864ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 4874ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 4884ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 4894ed1eea8STomer Tayar return -EAGAIN; 490fe56b9e6SYuval Mintz } 4914ed1eea8STomer Tayar 4924ed1eea8STomer Tayar /* Send the mailbox command */ 4934ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 4944ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 4954ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 496c8004600SDan Carpenter if (!p_cmd_elem) { 497c8004600SDan Carpenter rc = -ENOMEM; 4984ed1eea8STomer Tayar goto err; 499c8004600SDan Carpenter } 5004ed1eea8STomer Tayar 5014ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 5024ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5034ed1eea8STomer Tayar 5044ed1eea8STomer Tayar /* Wait for the MFW response */ 5054ed1eea8STomer Tayar do { 5064ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 5074ed1eea8STomer Tayar * command is completed during this iteration. 5084ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 5094ed1eea8STomer Tayar */ 5104ed1eea8STomer Tayar 511eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 512eaa50fc5STomer Tayar msleep(msecs); 513eaa50fc5STomer Tayar else 514eaa50fc5STomer Tayar udelay(usecs); 515eaa50fc5STomer Tayar 5164ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5174ed1eea8STomer Tayar 5184ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 5194ed1eea8STomer Tayar break; 5204ed1eea8STomer Tayar 5214ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5224ed1eea8STomer Tayar if (!rc) 5234ed1eea8STomer Tayar break; 5244ed1eea8STomer Tayar else if (rc != -EAGAIN) 5254ed1eea8STomer Tayar goto err; 5264ed1eea8STomer Tayar 5274ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5284ed1eea8STomer Tayar } while (++cnt < max_retries); 5294ed1eea8STomer Tayar 5304ed1eea8STomer Tayar if (cnt >= max_retries) { 5314ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5324ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 5334ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 5344ed1eea8STomer Tayar 5354ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5364ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5374ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5384ed1eea8STomer Tayar 5394ed1eea8STomer Tayar return -EAGAIN; 5404ed1eea8STomer Tayar } 5414ed1eea8STomer Tayar 5424ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5434ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5444ed1eea8STomer Tayar 5454ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5464ed1eea8STomer Tayar QED_MSG_SP, 5474ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5484ed1eea8STomer Tayar p_mb_params->mcp_resp, 5494ed1eea8STomer Tayar p_mb_params->mcp_param, 550eaa50fc5STomer Tayar (cnt * usecs) / 1000, (cnt * usecs) % 1000); 5514ed1eea8STomer Tayar 5524ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5534ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5544ed1eea8STomer Tayar 5554ed1eea8STomer Tayar return 0; 5564ed1eea8STomer Tayar 5574ed1eea8STomer Tayar err: 5584ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 559fe56b9e6SYuval Mintz return rc; 560fe56b9e6SYuval Mintz } 561fe56b9e6SYuval Mintz 5625529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 563fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 5645529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 565fe56b9e6SYuval Mintz { 5662f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 5674ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 568eaa50fc5STomer Tayar u32 usecs = QED_MCP_RESP_ITER_US; 569fe56b9e6SYuval Mintz 570fe56b9e6SYuval Mintz /* MCP not initialized */ 571fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 572fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 573fe56b9e6SYuval Mintz return -EBUSY; 574fe56b9e6SYuval Mintz } 575fe56b9e6SYuval Mintz 5762f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 5772f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 5782f67af8cSTomer Tayar DP_ERR(p_hwfn, 5792f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 5802f67af8cSTomer Tayar p_mb_params->data_src_size, 5812f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 5822f67af8cSTomer Tayar return -EINVAL; 5832f67af8cSTomer Tayar } 5842f67af8cSTomer Tayar 585eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) { 586eaa50fc5STomer Tayar max_retries = DIV_ROUND_UP(max_retries, 1000); 587eaa50fc5STomer Tayar usecs *= 1000; 588eaa50fc5STomer Tayar } 589eaa50fc5STomer Tayar 5904ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 591eaa50fc5STomer Tayar usecs); 592fe56b9e6SYuval Mintz } 593fe56b9e6SYuval Mintz 5945529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 5955529bad9STomer Tayar struct qed_ptt *p_ptt, 5965529bad9STomer Tayar u32 cmd, 5975529bad9STomer Tayar u32 param, 5985529bad9STomer Tayar u32 *o_mcp_resp, 5995529bad9STomer Tayar u32 *o_mcp_param) 600fe56b9e6SYuval Mintz { 6015529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 6025529bad9STomer Tayar int rc; 603fe56b9e6SYuval Mintz 6045529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6055529bad9STomer Tayar mb_params.cmd = cmd; 6065529bad9STomer Tayar mb_params.param = param; 60714d39648SMintz, Yuval 6085529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6095529bad9STomer Tayar if (rc) 6105529bad9STomer Tayar return rc; 6115529bad9STomer Tayar 6125529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6135529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 6145529bad9STomer Tayar 6155529bad9STomer Tayar return 0; 616fe56b9e6SYuval Mintz } 617fe56b9e6SYuval Mintz 618bf774d14SYueHaibing static int 619bf774d14SYueHaibing qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 62062e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 62162e4d438SSudarsana Reddy Kalluru u32 cmd, 62262e4d438SSudarsana Reddy Kalluru u32 param, 62362e4d438SSudarsana Reddy Kalluru u32 *o_mcp_resp, 62462e4d438SSudarsana Reddy Kalluru u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 62562e4d438SSudarsana Reddy Kalluru { 62662e4d438SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 62762e4d438SSudarsana Reddy Kalluru int rc; 62862e4d438SSudarsana Reddy Kalluru 62962e4d438SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 63062e4d438SSudarsana Reddy Kalluru mb_params.cmd = cmd; 63162e4d438SSudarsana Reddy Kalluru mb_params.param = param; 63262e4d438SSudarsana Reddy Kalluru mb_params.p_data_src = i_buf; 63362e4d438SSudarsana Reddy Kalluru mb_params.data_src_size = (u8)i_txn_size; 63462e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 63562e4d438SSudarsana Reddy Kalluru if (rc) 63662e4d438SSudarsana Reddy Kalluru return rc; 63762e4d438SSudarsana Reddy Kalluru 63862e4d438SSudarsana Reddy Kalluru *o_mcp_resp = mb_params.mcp_resp; 63962e4d438SSudarsana Reddy Kalluru *o_mcp_param = mb_params.mcp_param; 64062e4d438SSudarsana Reddy Kalluru 6415e7ba042SDenis Bolotin /* nvm_info needs to be updated */ 6425e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = false; 6435e7ba042SDenis Bolotin 64462e4d438SSudarsana Reddy Kalluru return 0; 64562e4d438SSudarsana Reddy Kalluru } 64662e4d438SSudarsana Reddy Kalluru 6474102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 6484102426fSTomer Tayar struct qed_ptt *p_ptt, 6494102426fSTomer Tayar u32 cmd, 6504102426fSTomer Tayar u32 param, 6514102426fSTomer Tayar u32 *o_mcp_resp, 6524102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 6534102426fSTomer Tayar { 6544102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 6552f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 6564102426fSTomer Tayar int rc; 6574102426fSTomer Tayar 6584102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6594102426fSTomer Tayar mb_params.cmd = cmd; 6604102426fSTomer Tayar mb_params.param = param; 6612f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 6622f67af8cSTomer Tayar 6632f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 6642f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 6652f67af8cSTomer Tayar 6664102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6674102426fSTomer Tayar if (rc) 6684102426fSTomer Tayar return rc; 6694102426fSTomer Tayar 6704102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6714102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 6724102426fSTomer Tayar 6734102426fSTomer Tayar *o_txn_size = *o_mcp_param; 6742f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 6754102426fSTomer Tayar 6764102426fSTomer Tayar return 0; 6774102426fSTomer Tayar } 6784102426fSTomer Tayar 6795d24bcf1STomer Tayar static bool 6805d24bcf1STomer Tayar qed_mcp_can_force_load(u8 drv_role, 6815d24bcf1STomer Tayar u8 exist_drv_role, 6825d24bcf1STomer Tayar enum qed_override_force_load override_force_load) 683fe56b9e6SYuval Mintz { 6845d24bcf1STomer Tayar bool can_force_load = false; 6855d24bcf1STomer Tayar 6865d24bcf1STomer Tayar switch (override_force_load) { 6875d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 6885d24bcf1STomer Tayar can_force_load = true; 6895d24bcf1STomer Tayar break; 6905d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_NEVER: 6915d24bcf1STomer Tayar can_force_load = false; 6925d24bcf1STomer Tayar break; 6935d24bcf1STomer Tayar default: 6945d24bcf1STomer Tayar can_force_load = (drv_role == DRV_ROLE_OS && 6955d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_PREBOOT) || 6965d24bcf1STomer Tayar (drv_role == DRV_ROLE_KDUMP && 6975d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_OS); 6985d24bcf1STomer Tayar break; 6995d24bcf1STomer Tayar } 7005d24bcf1STomer Tayar 7015d24bcf1STomer Tayar return can_force_load; 7025d24bcf1STomer Tayar } 7035d24bcf1STomer Tayar 7045d24bcf1STomer Tayar static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 7055d24bcf1STomer Tayar struct qed_ptt *p_ptt) 7065d24bcf1STomer Tayar { 7075d24bcf1STomer Tayar u32 resp = 0, param = 0; 708fe56b9e6SYuval Mintz int rc; 709fe56b9e6SYuval Mintz 7105d24bcf1STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 7115d24bcf1STomer Tayar &resp, ¶m); 7125d24bcf1STomer Tayar if (rc) 7135d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 7145d24bcf1STomer Tayar "Failed to send cancel load request, rc = %d\n", rc); 715fe56b9e6SYuval Mintz 716fe56b9e6SYuval Mintz return rc; 717fe56b9e6SYuval Mintz } 718fe56b9e6SYuval Mintz 7195d24bcf1STomer Tayar #define CONFIG_QEDE_BITMAP_IDX BIT(0) 7205d24bcf1STomer Tayar #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 7215d24bcf1STomer Tayar #define CONFIG_QEDR_BITMAP_IDX BIT(2) 7225d24bcf1STomer Tayar #define CONFIG_QEDF_BITMAP_IDX BIT(4) 7235d24bcf1STomer Tayar #define CONFIG_QEDI_BITMAP_IDX BIT(5) 7245d24bcf1STomer Tayar #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 7255529bad9STomer Tayar 7265d24bcf1STomer Tayar static u32 qed_get_config_bitmap(void) 7275d24bcf1STomer Tayar { 7285d24bcf1STomer Tayar u32 config_bitmap = 0x0; 7295d24bcf1STomer Tayar 7305d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QEDE)) 7315d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 7325d24bcf1STomer Tayar 7335d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_SRIOV)) 7345d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 7355d24bcf1STomer Tayar 7365d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_RDMA)) 7375d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 7385d24bcf1STomer Tayar 7395d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_FCOE)) 7405d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 7415d24bcf1STomer Tayar 7425d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_ISCSI)) 7435d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 7445d24bcf1STomer Tayar 7455d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_LL2)) 7465d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 7475d24bcf1STomer Tayar 7485d24bcf1STomer Tayar return config_bitmap; 7495d24bcf1STomer Tayar } 7505d24bcf1STomer Tayar 7515d24bcf1STomer Tayar struct qed_load_req_in_params { 7525d24bcf1STomer Tayar u8 hsi_ver; 7535d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 7545d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_1 1 7555d24bcf1STomer Tayar u32 drv_ver_0; 7565d24bcf1STomer Tayar u32 drv_ver_1; 7575d24bcf1STomer Tayar u32 fw_ver; 7585d24bcf1STomer Tayar u8 drv_role; 7595d24bcf1STomer Tayar u8 timeout_val; 7605d24bcf1STomer Tayar u8 force_cmd; 7615d24bcf1STomer Tayar bool avoid_eng_reset; 7625d24bcf1STomer Tayar }; 7635d24bcf1STomer Tayar 7645d24bcf1STomer Tayar struct qed_load_req_out_params { 7655d24bcf1STomer Tayar u32 load_code; 7665d24bcf1STomer Tayar u32 exist_drv_ver_0; 7675d24bcf1STomer Tayar u32 exist_drv_ver_1; 7685d24bcf1STomer Tayar u32 exist_fw_ver; 7695d24bcf1STomer Tayar u8 exist_drv_role; 7705d24bcf1STomer Tayar u8 mfw_hsi_ver; 7715d24bcf1STomer Tayar bool drv_exists; 7725d24bcf1STomer Tayar }; 7735d24bcf1STomer Tayar 7745d24bcf1STomer Tayar static int 7755d24bcf1STomer Tayar __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 7765d24bcf1STomer Tayar struct qed_ptt *p_ptt, 7775d24bcf1STomer Tayar struct qed_load_req_in_params *p_in_params, 7785d24bcf1STomer Tayar struct qed_load_req_out_params *p_out_params) 7795d24bcf1STomer Tayar { 7805d24bcf1STomer Tayar struct qed_mcp_mb_params mb_params; 7815d24bcf1STomer Tayar struct load_req_stc load_req; 7825d24bcf1STomer Tayar struct load_rsp_stc load_rsp; 7835d24bcf1STomer Tayar u32 hsi_ver; 7845d24bcf1STomer Tayar int rc; 7855d24bcf1STomer Tayar 7865d24bcf1STomer Tayar memset(&load_req, 0, sizeof(load_req)); 7875d24bcf1STomer Tayar load_req.drv_ver_0 = p_in_params->drv_ver_0; 7885d24bcf1STomer Tayar load_req.drv_ver_1 = p_in_params->drv_ver_1; 7895d24bcf1STomer Tayar load_req.fw_ver = p_in_params->fw_ver; 7905d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 7915d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 7925d24bcf1STomer Tayar p_in_params->timeout_val); 7935d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 7945d24bcf1STomer Tayar p_in_params->force_cmd); 7955d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 7965d24bcf1STomer Tayar p_in_params->avoid_eng_reset); 7975d24bcf1STomer Tayar 7985d24bcf1STomer Tayar hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 7995d24bcf1STomer Tayar DRV_ID_MCP_HSI_VER_CURRENT : 8005d24bcf1STomer Tayar (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 8015d24bcf1STomer Tayar 8025d24bcf1STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 8035d24bcf1STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 8045d24bcf1STomer Tayar mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 8055d24bcf1STomer Tayar mb_params.p_data_src = &load_req; 8065d24bcf1STomer Tayar mb_params.data_src_size = sizeof(load_req); 8075d24bcf1STomer Tayar mb_params.p_data_dst = &load_rsp; 8085d24bcf1STomer Tayar mb_params.data_dst_size = sizeof(load_rsp); 809eaa50fc5STomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP; 8105d24bcf1STomer Tayar 8115d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8125d24bcf1STomer Tayar "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 8135d24bcf1STomer Tayar mb_params.param, 8145d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 8155d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 8165d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 8175d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 8185d24bcf1STomer Tayar 8195d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 8205d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8215d24bcf1STomer Tayar "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 8225d24bcf1STomer Tayar load_req.drv_ver_0, 8235d24bcf1STomer Tayar load_req.drv_ver_1, 8245d24bcf1STomer Tayar load_req.fw_ver, 8255d24bcf1STomer Tayar load_req.misc0, 8265d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 8275d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, 8285d24bcf1STomer Tayar LOAD_REQ_LOCK_TO), 8295d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 8305d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 8315d24bcf1STomer Tayar } 8325d24bcf1STomer Tayar 8335d24bcf1STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 8345d24bcf1STomer Tayar if (rc) { 8355d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 8365d24bcf1STomer Tayar return rc; 8375d24bcf1STomer Tayar } 8385d24bcf1STomer Tayar 8395d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8405d24bcf1STomer Tayar "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 8415d24bcf1STomer Tayar p_out_params->load_code = mb_params.mcp_resp; 8425d24bcf1STomer Tayar 8435d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 8445d24bcf1STomer Tayar p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 8455d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, 8465d24bcf1STomer Tayar QED_MSG_SP, 8475d24bcf1STomer Tayar "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 8485d24bcf1STomer Tayar load_rsp.drv_ver_0, 8495d24bcf1STomer Tayar load_rsp.drv_ver_1, 8505d24bcf1STomer Tayar load_rsp.fw_ver, 8515d24bcf1STomer Tayar load_rsp.misc0, 8525d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 8535d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 8545d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 8555d24bcf1STomer Tayar 8565d24bcf1STomer Tayar p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 8575d24bcf1STomer Tayar p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 8585d24bcf1STomer Tayar p_out_params->exist_fw_ver = load_rsp.fw_ver; 8595d24bcf1STomer Tayar p_out_params->exist_drv_role = 8605d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 8615d24bcf1STomer Tayar p_out_params->mfw_hsi_ver = 8625d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 8635d24bcf1STomer Tayar p_out_params->drv_exists = 8645d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 8655d24bcf1STomer Tayar LOAD_RSP_FLAGS0_DRV_EXISTS; 8665d24bcf1STomer Tayar } 8675d24bcf1STomer Tayar 8685d24bcf1STomer Tayar return 0; 8695d24bcf1STomer Tayar } 8705d24bcf1STomer Tayar 8715d24bcf1STomer Tayar static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 8725d24bcf1STomer Tayar enum qed_drv_role drv_role, 8735d24bcf1STomer Tayar u8 *p_mfw_drv_role) 8745d24bcf1STomer Tayar { 8755d24bcf1STomer Tayar switch (drv_role) { 8765d24bcf1STomer Tayar case QED_DRV_ROLE_OS: 8775d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_OS; 8785d24bcf1STomer Tayar break; 8795d24bcf1STomer Tayar case QED_DRV_ROLE_KDUMP: 8805d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_KDUMP; 8815d24bcf1STomer Tayar break; 8825d24bcf1STomer Tayar default: 8835d24bcf1STomer Tayar DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 8845d24bcf1STomer Tayar return -EINVAL; 8855d24bcf1STomer Tayar } 8865d24bcf1STomer Tayar 8875d24bcf1STomer Tayar return 0; 8885d24bcf1STomer Tayar } 8895d24bcf1STomer Tayar 8905d24bcf1STomer Tayar enum qed_load_req_force { 8915d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, 8925d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_PF, 8935d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 8945d24bcf1STomer Tayar }; 8955d24bcf1STomer Tayar 8965d24bcf1STomer Tayar static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 8975d24bcf1STomer Tayar 8985d24bcf1STomer Tayar enum qed_load_req_force force_cmd, 8995d24bcf1STomer Tayar u8 *p_mfw_force_cmd) 9005d24bcf1STomer Tayar { 9015d24bcf1STomer Tayar switch (force_cmd) { 9025d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_NONE: 9035d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 9045d24bcf1STomer Tayar break; 9055d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_PF: 9065d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 9075d24bcf1STomer Tayar break; 9085d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_ALL: 9095d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 9105d24bcf1STomer Tayar break; 9115d24bcf1STomer Tayar } 9125d24bcf1STomer Tayar } 9135d24bcf1STomer Tayar 9145d24bcf1STomer Tayar int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 9155d24bcf1STomer Tayar struct qed_ptt *p_ptt, 9165d24bcf1STomer Tayar struct qed_load_req_params *p_params) 9175d24bcf1STomer Tayar { 9185d24bcf1STomer Tayar struct qed_load_req_out_params out_params; 9195d24bcf1STomer Tayar struct qed_load_req_in_params in_params; 9205d24bcf1STomer Tayar u8 mfw_drv_role, mfw_force_cmd; 9215d24bcf1STomer Tayar int rc; 9225d24bcf1STomer Tayar 9235d24bcf1STomer Tayar memset(&in_params, 0, sizeof(in_params)); 9245d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 9255d24bcf1STomer Tayar in_params.drv_ver_0 = QED_VERSION; 9265d24bcf1STomer Tayar in_params.drv_ver_1 = qed_get_config_bitmap(); 9275d24bcf1STomer Tayar in_params.fw_ver = STORM_FW_VERSION; 9285d24bcf1STomer Tayar rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 9295d24bcf1STomer Tayar if (rc) 9305d24bcf1STomer Tayar return rc; 9315d24bcf1STomer Tayar 9325d24bcf1STomer Tayar in_params.drv_role = mfw_drv_role; 9335d24bcf1STomer Tayar in_params.timeout_val = p_params->timeout_val; 9345d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9355d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 9365d24bcf1STomer Tayar 9375d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9385d24bcf1STomer Tayar in_params.avoid_eng_reset = p_params->avoid_eng_reset; 9395d24bcf1STomer Tayar 9405d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9415d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9425d24bcf1STomer Tayar if (rc) 9435d24bcf1STomer Tayar return rc; 9445d24bcf1STomer Tayar 9455d24bcf1STomer Tayar /* First handle cases where another load request should/might be sent: 9465d24bcf1STomer Tayar * - MFW expects the old interface [HSI version = 1] 9475d24bcf1STomer Tayar * - MFW responds that a force load request is required 948fe56b9e6SYuval Mintz */ 9495d24bcf1STomer Tayar if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 9505d24bcf1STomer Tayar DP_INFO(p_hwfn, 9515d24bcf1STomer Tayar "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 9525d24bcf1STomer Tayar 9535d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 9545d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9555d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9565d24bcf1STomer Tayar if (rc) 9575d24bcf1STomer Tayar return rc; 9585d24bcf1STomer Tayar } else if (out_params.load_code == 9595d24bcf1STomer Tayar FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 9605d24bcf1STomer Tayar if (qed_mcp_can_force_load(in_params.drv_role, 9615d24bcf1STomer Tayar out_params.exist_drv_role, 9625d24bcf1STomer Tayar p_params->override_force_load)) { 9635d24bcf1STomer Tayar DP_INFO(p_hwfn, 9645d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 9655d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 9665d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 9675d24bcf1STomer Tayar out_params.exist_drv_role, 9685d24bcf1STomer Tayar out_params.exist_fw_ver, 9695d24bcf1STomer Tayar out_params.exist_drv_ver_0, 9705d24bcf1STomer Tayar out_params.exist_drv_ver_1); 9715d24bcf1STomer Tayar 9725d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9735d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9745d24bcf1STomer Tayar &mfw_force_cmd); 9755d24bcf1STomer Tayar 9765d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9775d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9785d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 9795d24bcf1STomer Tayar &out_params); 9805d24bcf1STomer Tayar if (rc) 9815d24bcf1STomer Tayar return rc; 9825d24bcf1STomer Tayar } else { 9835d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 9845d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 9855d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 9865d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 9875d24bcf1STomer Tayar out_params.exist_drv_role, 9885d24bcf1STomer Tayar out_params.exist_fw_ver, 9895d24bcf1STomer Tayar out_params.exist_drv_ver_0, 9905d24bcf1STomer Tayar out_params.exist_drv_ver_1); 9915d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 9925d24bcf1STomer Tayar "Avoid sending a force load request to prevent disruption of active PFs\n"); 9935d24bcf1STomer Tayar 9945d24bcf1STomer Tayar qed_mcp_cancel_load_req(p_hwfn, p_ptt); 995fe56b9e6SYuval Mintz return -EBUSY; 996fe56b9e6SYuval Mintz } 9975d24bcf1STomer Tayar } 9985d24bcf1STomer Tayar 9995d24bcf1STomer Tayar /* Now handle the other types of responses. 10005d24bcf1STomer Tayar * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 10015d24bcf1STomer Tayar * expected here after the additional revised load requests were sent. 10025d24bcf1STomer Tayar */ 10035d24bcf1STomer Tayar switch (out_params.load_code) { 10045d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_ENGINE: 10055d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_PORT: 10065d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_FUNCTION: 10075d24bcf1STomer Tayar if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 10085d24bcf1STomer Tayar out_params.drv_exists) { 10095d24bcf1STomer Tayar /* The role and fw/driver version match, but the PF is 10105d24bcf1STomer Tayar * already loaded and has not been unloaded gracefully. 10115d24bcf1STomer Tayar */ 10125d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10135d24bcf1STomer Tayar "PF is already loaded\n"); 10145d24bcf1STomer Tayar return -EINVAL; 10155d24bcf1STomer Tayar } 10165d24bcf1STomer Tayar break; 10175d24bcf1STomer Tayar default: 10185d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10195d24bcf1STomer Tayar "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 10205d24bcf1STomer Tayar out_params.load_code); 10215d24bcf1STomer Tayar return -EBUSY; 10225d24bcf1STomer Tayar } 10235d24bcf1STomer Tayar 10245d24bcf1STomer Tayar p_params->load_code = out_params.load_code; 1025fe56b9e6SYuval Mintz 1026fe56b9e6SYuval Mintz return 0; 1027fe56b9e6SYuval Mintz } 1028fe56b9e6SYuval Mintz 10291226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10301226337aSTomer Tayar { 1031eaa50fc5STomer Tayar struct qed_mcp_mb_params mb_params; 1032eaa50fc5STomer Tayar u32 wol_param; 10331226337aSTomer Tayar 10341226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 10351226337aSTomer Tayar case QED_OV_WOL_DISABLED: 10361226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 10371226337aSTomer Tayar break; 10381226337aSTomer Tayar case QED_OV_WOL_ENABLED: 10391226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 10401226337aSTomer Tayar break; 10411226337aSTomer Tayar default: 10421226337aSTomer Tayar DP_NOTICE(p_hwfn, 10431226337aSTomer Tayar "Unknown WoL configuration %02x\n", 10441226337aSTomer Tayar p_hwfn->cdev->wol_config); 10451226337aSTomer Tayar /* Fallthrough */ 10461226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 10471226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 10481226337aSTomer Tayar } 10491226337aSTomer Tayar 1050eaa50fc5STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 1051eaa50fc5STomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ; 1052eaa50fc5STomer Tayar mb_params.param = wol_param; 1053eaa50fc5STomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP; 1054eaa50fc5STomer Tayar 1055eaa50fc5STomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 10561226337aSTomer Tayar } 10571226337aSTomer Tayar 10581226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10591226337aSTomer Tayar { 10601226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 10611226337aSTomer Tayar struct mcp_mac wol_mac; 10621226337aSTomer Tayar 10631226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 10641226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 10651226337aSTomer Tayar 10661226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 10671226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 10681226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 10691226337aSTomer Tayar 10701226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 10711226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 10721226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 10731226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 10741226337aSTomer Tayar 10751226337aSTomer Tayar DP_VERBOSE(p_hwfn, 10761226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 10771226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 10781226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 10791226337aSTomer Tayar 10801226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 10811226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 10821226337aSTomer Tayar } 10831226337aSTomer Tayar 10841226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 10851226337aSTomer Tayar } 10861226337aSTomer Tayar 10870b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 10880b55e27dSYuval Mintz struct qed_ptt *p_ptt) 10890b55e27dSYuval Mintz { 10900b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 10910b55e27dSYuval Mintz PUBLIC_PATH); 10920b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 10930b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 10940b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 10950b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 10960b55e27dSYuval Mintz int i; 10970b55e27dSYuval Mintz 10980b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 10990b55e27dSYuval Mintz QED_MSG_SP, 11000b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 11010b55e27dSYuval Mintz mfw_path_offsize, path_addr); 11020b55e27dSYuval Mintz 11030b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 11040b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 11050b55e27dSYuval Mintz path_addr + 11060b55e27dSYuval Mintz offsetof(struct public_path, 11070b55e27dSYuval Mintz mcp_vf_disabled) + 11080b55e27dSYuval Mintz sizeof(u32) * i); 11090b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11100b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 11110b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 11120b55e27dSYuval Mintz } 11130b55e27dSYuval Mintz 11140b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 11150b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 11160b55e27dSYuval Mintz } 11170b55e27dSYuval Mintz 11180b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 11190b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 11200b55e27dSYuval Mintz { 11210b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11220b55e27dSYuval Mintz PUBLIC_FUNC); 11230b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 11240b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 11250b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 11260b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 11270b55e27dSYuval Mintz int rc; 11280b55e27dSYuval Mintz int i; 11290b55e27dSYuval Mintz 11300b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11310b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11320b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 11330b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 11340b55e27dSYuval Mintz 11350b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 11360b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 11372f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 11382f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 11390b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11400b55e27dSYuval Mintz if (rc) { 11410b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 11420b55e27dSYuval Mintz return -EBUSY; 11430b55e27dSYuval Mintz } 11440b55e27dSYuval Mintz 11450b55e27dSYuval Mintz /* Clear the ACK bits */ 11460b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11470b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 11480b55e27dSYuval Mintz func_addr + 11490b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 11500b55e27dSYuval Mintz i * sizeof(u32), 0); 11510b55e27dSYuval Mintz 11520b55e27dSYuval Mintz return rc; 11530b55e27dSYuval Mintz } 11540b55e27dSYuval Mintz 1155334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1156334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 1157334c03b5SZvi Nachmani { 1158334c03b5SZvi Nachmani u32 transceiver_state; 1159334c03b5SZvi Nachmani 1160334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 1161334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 1162334c03b5SZvi Nachmani offsetof(struct public_port, 1163334c03b5SZvi Nachmani transceiver_data)); 1164334c03b5SZvi Nachmani 1165334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 1166334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 1167334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1168334c03b5SZvi Nachmani transceiver_state, 1169334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 11701a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 1171334c03b5SZvi Nachmani 1172334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 1173351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 1174334c03b5SZvi Nachmani 1175351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1176334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1177334c03b5SZvi Nachmani else 1178334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1179334c03b5SZvi Nachmani } 1180334c03b5SZvi Nachmani 1181645874e5SSudarsana Reddy Kalluru static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1182645874e5SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1183645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_state *p_link) 1184645874e5SSudarsana Reddy Kalluru { 1185645874e5SSudarsana Reddy Kalluru u32 eee_status, val; 1186645874e5SSudarsana Reddy Kalluru 1187645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps = 0; 1188645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps = 0; 1189645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, 1190645874e5SSudarsana Reddy Kalluru p_ptt, 1191645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 1192645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 1193645874e5SSudarsana Reddy Kalluru p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1194645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1195645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1196645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1197645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1198645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1199645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1200645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1201645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1202645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1203645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1204645874e5SSudarsana Reddy Kalluru } 1205645874e5SSudarsana Reddy Kalluru 1206cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 12071a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 1208cc875c2eSYuval Mintz { 1209cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 1210a64b02d5SManish Chopra u8 max_bw, min_bw; 1211cc875c2eSYuval Mintz u32 status = 0; 1212cc875c2eSYuval Mintz 121365ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 121465ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 121565ed2ffdSMintz, Yuval 1216cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 1217cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 1218cc875c2eSYuval Mintz if (!b_reset) { 1219cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 1220cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 1221cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 1222cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1223cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1224cc875c2eSYuval Mintz status, 1225cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 12261a635e48SYuval Mintz offsetof(struct public_port, link_status))); 1227cc875c2eSYuval Mintz } else { 1228cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1229cc875c2eSYuval Mintz "Resetting link indications\n"); 123065ed2ffdSMintz, Yuval goto out; 1231cc875c2eSYuval Mintz } 1232cc875c2eSYuval Mintz 1233fc916ff2SSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) 1234cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1235fc916ff2SSudarsana Reddy Kalluru else 1236fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 1237cc875c2eSYuval Mintz 1238cc875c2eSYuval Mintz p_link->full_duplex = true; 1239cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1240cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1241cc875c2eSYuval Mintz p_link->speed = 100000; 1242cc875c2eSYuval Mintz break; 1243cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1244cc875c2eSYuval Mintz p_link->speed = 50000; 1245cc875c2eSYuval Mintz break; 1246cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1247cc875c2eSYuval Mintz p_link->speed = 40000; 1248cc875c2eSYuval Mintz break; 1249cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1250cc875c2eSYuval Mintz p_link->speed = 25000; 1251cc875c2eSYuval Mintz break; 1252cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1253cc875c2eSYuval Mintz p_link->speed = 20000; 1254cc875c2eSYuval Mintz break; 1255cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1256cc875c2eSYuval Mintz p_link->speed = 10000; 1257cc875c2eSYuval Mintz break; 1258cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1259cc875c2eSYuval Mintz p_link->full_duplex = false; 1260cc875c2eSYuval Mintz /* Fall-through */ 1261cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1262cc875c2eSYuval Mintz p_link->speed = 1000; 1263cc875c2eSYuval Mintz break; 1264cc875c2eSYuval Mintz default: 1265cc875c2eSYuval Mintz p_link->speed = 0; 126658874c7bSSudarsana Reddy Kalluru p_link->link_up = 0; 1267cc875c2eSYuval Mintz } 1268cc875c2eSYuval Mintz 12694b01e519SManish Chopra if (p_link->link_up && p_link->speed) 12704b01e519SManish Chopra p_link->line_speed = p_link->speed; 12714b01e519SManish Chopra else 12724b01e519SManish Chopra p_link->line_speed = 0; 12734b01e519SManish Chopra 12744b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1275a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 12764b01e519SManish Chopra 1277a64b02d5SManish Chopra /* Max bandwidth configuration */ 12784b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1279cc875c2eSYuval Mintz 1280a64b02d5SManish Chopra /* Min bandwidth configuration */ 1281a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 12826f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 12836f437d43SMintz, Yuval p_link->min_pf_rate); 1284a64b02d5SManish Chopra 1285cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1286cc875c2eSYuval Mintz p_link->an_complete = !!(status & 1287cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1288cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 1289cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 1290cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1291cc875c2eSYuval Mintz 1292cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1293cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1294cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 1295cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1296cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1297cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 1298cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1299cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1300cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 1301cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1302cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1303cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 1304cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1305054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1306054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 1307054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 1308cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1309cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 1310cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1311cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1312cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 1313cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1314cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1315cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 1316cc875c2eSYuval Mintz 1317cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 1318cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1319cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 1320cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1321cc875c2eSYuval Mintz 1322cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1323cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1324cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1325cc875c2eSYuval Mintz break; 1326cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1327cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1328cc875c2eSYuval Mintz break; 1329cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1330cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1331cc875c2eSYuval Mintz break; 1332cc875c2eSYuval Mintz default: 1333cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 1334cc875c2eSYuval Mintz } 1335cc875c2eSYuval Mintz 1336cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1337cc875c2eSYuval Mintz 1338645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1339645874e5SSudarsana Reddy Kalluru qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1340645874e5SSudarsana Reddy Kalluru 1341cc875c2eSYuval Mintz qed_link_update(p_hwfn); 134265ed2ffdSMintz, Yuval out: 134365ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1344cc875c2eSYuval Mintz } 1345cc875c2eSYuval Mintz 1346351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1347cc875c2eSYuval Mintz { 1348cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 13495529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 13502f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 1351cc875c2eSYuval Mintz int rc = 0; 13525529bad9STomer Tayar u32 cmd; 1353cc875c2eSYuval Mintz 1354cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 13552f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 1356cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1357cc875c2eSYuval Mintz if (!params->speed.autoneg) 13582f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 13592f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 13602f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 13612f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 13622f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 13632f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 13644ad95a93SSudarsana Reddy Kalluru 13654ad95a93SSudarsana Reddy Kalluru /* There are MFWs that share this capability regardless of whether 13664ad95a93SSudarsana Reddy Kalluru * this is feasible or not. And given that at the very least adv_caps 13674ad95a93SSudarsana Reddy Kalluru * would be set internally by qed, we want to make sure LFA would 13684ad95a93SSudarsana Reddy Kalluru * still work. 13694ad95a93SSudarsana Reddy Kalluru */ 13704ad95a93SSudarsana Reddy Kalluru if ((p_hwfn->mcp_info->capabilities & 13714ad95a93SSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1372645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1373645874e5SSudarsana Reddy Kalluru if (params->eee.tx_lpi_enable) 1374645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1375645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_1G_ADV) 1376645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1377645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_10G_ADV) 1378645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1379645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1380645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_OFFSET) & 1381645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_MASK; 1382645874e5SSudarsana Reddy Kalluru } 1383cc875c2eSYuval Mintz 1384fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 1385fc916ff2SSudarsana Reddy Kalluru 1386cc875c2eSYuval Mintz if (b_up) { 1387cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1388cc875c2eSYuval Mintz "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 13892f67af8cSTomer Tayar phy_cfg.speed, 13902f67af8cSTomer Tayar phy_cfg.pause, 13912f67af8cSTomer Tayar phy_cfg.adv_speed, 13922f67af8cSTomer Tayar phy_cfg.loopback_mode, 13932f67af8cSTomer Tayar phy_cfg.feature_config_flags); 1394cc875c2eSYuval Mintz } else { 1395cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1396cc875c2eSYuval Mintz "Resetting link\n"); 1397cc875c2eSYuval Mintz } 1398cc875c2eSYuval Mintz 13995529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 14005529bad9STomer Tayar mb_params.cmd = cmd; 14012f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 14022f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 14035529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1404cc875c2eSYuval Mintz 1405cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 1406cc875c2eSYuval Mintz if (rc) { 1407cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1408cc875c2eSYuval Mintz return rc; 1409cc875c2eSYuval Mintz } 1410cc875c2eSYuval Mintz 141165ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 141265ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 141365ed2ffdSMintz, Yuval * an attention. 141465ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 141565ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 141665ed2ffdSMintz, Yuval */ 141765ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1418cc875c2eSYuval Mintz 1419cc875c2eSYuval Mintz return 0; 1420cc875c2eSYuval Mintz } 1421cc875c2eSYuval Mintz 14226c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 14236c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 14246c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 14256c754246SSudarsana Reddy Kalluru { 14266c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 14276c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 14286c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 14296c754246SSudarsana Reddy Kalluru u32 hsi_param; 14306c754246SSudarsana Reddy Kalluru 14316c754246SSudarsana Reddy Kalluru switch (type) { 14326c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 14336c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 14346c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 14356c754246SSudarsana Reddy Kalluru break; 14366c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 14376c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 14386c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 14396c754246SSudarsana Reddy Kalluru break; 14406c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 14416c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 14426c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 14436c754246SSudarsana Reddy Kalluru break; 14446c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 14456c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 14466c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 14476c754246SSudarsana Reddy Kalluru break; 14486c754246SSudarsana Reddy Kalluru default: 14496c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 14506c754246SSudarsana Reddy Kalluru return; 14516c754246SSudarsana Reddy Kalluru } 14526c754246SSudarsana Reddy Kalluru 14536c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 14546c754246SSudarsana Reddy Kalluru 14556c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 14566c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 14576c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 14582f67af8cSTomer Tayar mb_params.p_data_src = &stats; 14592f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 14606c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 14616c754246SSudarsana Reddy Kalluru } 14626c754246SSudarsana Reddy Kalluru 14634b01e519SManish Chopra static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 14644b01e519SManish Chopra struct public_func *p_shmem_info) 14654b01e519SManish Chopra { 14664b01e519SManish Chopra struct qed_mcp_function_info *p_info; 14674b01e519SManish Chopra 14684b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 14694b01e519SManish Chopra 14704b01e519SManish Chopra p_info->bandwidth_min = (p_shmem_info->config & 14714b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_MASK) >> 14724b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_SHIFT; 14734b01e519SManish Chopra if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 14744b01e519SManish Chopra DP_INFO(p_hwfn, 14754b01e519SManish Chopra "bandwidth minimum out of bounds [%02x]. Set to 1\n", 14764b01e519SManish Chopra p_info->bandwidth_min); 14774b01e519SManish Chopra p_info->bandwidth_min = 1; 14784b01e519SManish Chopra } 14794b01e519SManish Chopra 14804b01e519SManish Chopra p_info->bandwidth_max = (p_shmem_info->config & 14814b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_MASK) >> 14824b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_SHIFT; 14834b01e519SManish Chopra if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 14844b01e519SManish Chopra DP_INFO(p_hwfn, 14854b01e519SManish Chopra "bandwidth maximum out of bounds [%02x]. Set to 100\n", 14864b01e519SManish Chopra p_info->bandwidth_max); 14874b01e519SManish Chopra p_info->bandwidth_max = 100; 14884b01e519SManish Chopra } 14894b01e519SManish Chopra } 14904b01e519SManish Chopra 14914b01e519SManish Chopra static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 14924b01e519SManish Chopra struct qed_ptt *p_ptt, 14931a635e48SYuval Mintz struct public_func *p_data, int pfid) 14944b01e519SManish Chopra { 14954b01e519SManish Chopra u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 14964b01e519SManish Chopra PUBLIC_FUNC); 14974b01e519SManish Chopra u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 14984b01e519SManish Chopra u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 14994b01e519SManish Chopra u32 i, size; 15004b01e519SManish Chopra 15014b01e519SManish Chopra memset(p_data, 0, sizeof(*p_data)); 15024b01e519SManish Chopra 15031a635e48SYuval Mintz size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 15044b01e519SManish Chopra for (i = 0; i < size / sizeof(u32); i++) 15054b01e519SManish Chopra ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 15064b01e519SManish Chopra func_addr + (i << 2)); 15074b01e519SManish Chopra return size; 15084b01e519SManish Chopra } 15094b01e519SManish Chopra 15101a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 15114b01e519SManish Chopra { 15124b01e519SManish Chopra struct qed_mcp_function_info *p_info; 15134b01e519SManish Chopra struct public_func shmem_info; 15144b01e519SManish Chopra u32 resp = 0, param = 0; 15154b01e519SManish Chopra 15161a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 15174b01e519SManish Chopra 15184b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 15194b01e519SManish Chopra 15204b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 15214b01e519SManish Chopra 1522a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 15234b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 15244b01e519SManish Chopra 15254b01e519SManish Chopra /* Acknowledge the MFW */ 15264b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 15274b01e519SManish Chopra ¶m); 15284b01e519SManish Chopra } 15294b01e519SManish Chopra 15302a351fd9SMintz, Yuval static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 15312a351fd9SMintz, Yuval { 15322a351fd9SMintz, Yuval struct public_func shmem_info; 15332a351fd9SMintz, Yuval u32 resp = 0, param = 0; 15342a351fd9SMintz, Yuval 15352a351fd9SMintz, Yuval qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 15362a351fd9SMintz, Yuval 15372a351fd9SMintz, Yuval p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 15382a351fd9SMintz, Yuval FUNC_MF_CFG_OV_STAG_MASK; 15392a351fd9SMintz, Yuval p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 15402a351fd9SMintz, Yuval if ((p_hwfn->hw_info.hw_mode & BIT(MODE_MF_SD)) && 15412a351fd9SMintz, Yuval (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET)) { 15422a351fd9SMintz, Yuval qed_wr(p_hwfn, p_ptt, 15432a351fd9SMintz, Yuval NIG_REG_LLH_FUNC_TAG_VALUE, p_hwfn->hw_info.ovlan); 15442a351fd9SMintz, Yuval qed_sp_pf_update_stag(p_hwfn); 15452a351fd9SMintz, Yuval } 15462a351fd9SMintz, Yuval 15472a351fd9SMintz, Yuval /* Acknowledge the MFW */ 15482a351fd9SMintz, Yuval qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 15492a351fd9SMintz, Yuval &resp, ¶m); 15502a351fd9SMintz, Yuval } 15512a351fd9SMintz, Yuval 1552cac6f691SSudarsana Reddy Kalluru void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1553cac6f691SSudarsana Reddy Kalluru { 1554cac6f691SSudarsana Reddy Kalluru struct public_func shmem_info; 1555cac6f691SSudarsana Reddy Kalluru u32 port_cfg, val; 1556cac6f691SSudarsana Reddy Kalluru 1557cac6f691SSudarsana Reddy Kalluru if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1558cac6f691SSudarsana Reddy Kalluru return; 1559cac6f691SSudarsana Reddy Kalluru 1560cac6f691SSudarsana Reddy Kalluru memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1561cac6f691SSudarsana Reddy Kalluru port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1562cac6f691SSudarsana Reddy Kalluru offsetof(struct public_port, oem_cfg_port)); 1563cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1564cac6f691SSudarsana Reddy Kalluru OEM_CFG_CHANNEL_TYPE_OFFSET; 1565cac6f691SSudarsana Reddy Kalluru if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1566cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Incorrect UFP Channel type %d\n", val); 1567cac6f691SSudarsana Reddy Kalluru 1568cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1569cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_SCHED_TYPE_ETS) { 1570cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1571cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1572cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1573cac6f691SSudarsana Reddy Kalluru } else { 1574cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1575cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Unknown UFP scheduling mode %d\n", val); 1576cac6f691SSudarsana Reddy Kalluru } 1577cac6f691SSudarsana Reddy Kalluru 1578cac6f691SSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1579b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1580b5fabb08SSudarsana Reddy Kalluru OEM_CFG_FUNC_TC_OFFSET; 1581cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.tc = (u8)val; 1582b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1583cac6f691SSudarsana Reddy Kalluru OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1584cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1585cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1586cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1587cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1588cac6f691SSudarsana Reddy Kalluru } else { 1589cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1590cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Unknown Host priority control %d\n", val); 1591cac6f691SSudarsana Reddy Kalluru } 1592cac6f691SSudarsana Reddy Kalluru 1593cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1594cac6f691SSudarsana Reddy Kalluru "UFP shmem config: mode = %d tc = %d pri_type = %d\n", 1595cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode, 1596cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.tc, p_hwfn->ufp_info.pri_type); 1597cac6f691SSudarsana Reddy Kalluru } 1598cac6f691SSudarsana Reddy Kalluru 1599cac6f691SSudarsana Reddy Kalluru static int 1600cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1601cac6f691SSudarsana Reddy Kalluru { 1602cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1603cac6f691SSudarsana Reddy Kalluru 1604cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1605cac6f691SSudarsana Reddy Kalluru p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1606c4259ddaSDenis Bolotin qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1607c4259ddaSDenis Bolotin p_hwfn->ufp_info.tc); 1608cac6f691SSudarsana Reddy Kalluru 1609cac6f691SSudarsana Reddy Kalluru qed_qm_reconf(p_hwfn, p_ptt); 1610cac6f691SSudarsana Reddy Kalluru } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1611cac6f691SSudarsana Reddy Kalluru /* Merge UFP TC with the dcbx TC data */ 1612cac6f691SSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1613cac6f691SSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 1614cac6f691SSudarsana Reddy Kalluru } else { 1615cac6f691SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1616cac6f691SSudarsana Reddy Kalluru return -EINVAL; 1617cac6f691SSudarsana Reddy Kalluru } 1618cac6f691SSudarsana Reddy Kalluru 1619cac6f691SSudarsana Reddy Kalluru /* update storm FW with negotiation results */ 1620cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_ufp(p_hwfn); 1621cac6f691SSudarsana Reddy Kalluru 1622cac6f691SSudarsana Reddy Kalluru /* update stag pcp value */ 1623cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_stag(p_hwfn); 1624cac6f691SSudarsana Reddy Kalluru 1625cac6f691SSudarsana Reddy Kalluru return 0; 1626cac6f691SSudarsana Reddy Kalluru } 1627cac6f691SSudarsana Reddy Kalluru 1628cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1629cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1630cc875c2eSYuval Mintz { 1631cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 1632cc875c2eSYuval Mintz int rc = 0; 1633cc875c2eSYuval Mintz bool found = false; 1634cc875c2eSYuval Mintz u16 i; 1635cc875c2eSYuval Mintz 1636cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1637cc875c2eSYuval Mintz 1638cc875c2eSYuval Mintz /* Read Messages from MFW */ 1639cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 1640cc875c2eSYuval Mintz 1641cc875c2eSYuval Mintz /* Compare current messages to old ones */ 1642cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 1643cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1644cc875c2eSYuval Mintz continue; 1645cc875c2eSYuval Mintz 1646cc875c2eSYuval Mintz found = true; 1647cc875c2eSYuval Mintz 1648cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1649cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1650cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1651cc875c2eSYuval Mintz 1652cc875c2eSYuval Mintz switch (i) { 1653cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 1654cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1655cc875c2eSYuval Mintz break; 16560b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 16570b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 16580b55e27dSYuval Mintz break; 165939651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 166039651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 166139651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 166239651abdSSudarsana Reddy Kalluru break; 166339651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 166439651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 166539651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 166639651abdSSudarsana Reddy Kalluru break; 166739651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 166839651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 166939651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 167039651abdSSudarsana Reddy Kalluru break; 1671cac6f691SSudarsana Reddy Kalluru case MFW_DRV_MSG_OEM_CFG_UPDATE: 1672cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 1673cac6f691SSudarsana Reddy Kalluru break; 1674334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1675334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1676334c03b5SZvi Nachmani break; 16776c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 16786c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 16796c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 16806c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 16816c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 16826c754246SSudarsana Reddy Kalluru break; 16834b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 16844b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 16854b01e519SManish Chopra break; 16862a351fd9SMintz, Yuval case MFW_DRV_MSG_S_TAG_UPDATE: 16872a351fd9SMintz, Yuval qed_mcp_update_stag(p_hwfn, p_ptt); 16882a351fd9SMintz, Yuval break; 168959ccf86fSSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_TLV_REQ: 169059ccf86fSSudarsana Reddy Kalluru qed_mfw_tlv_req(p_hwfn); 16912a351fd9SMintz, Yuval break; 1692cc875c2eSYuval Mintz default: 169339815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1694cc875c2eSYuval Mintz rc = -EINVAL; 1695cc875c2eSYuval Mintz } 1696cc875c2eSYuval Mintz } 1697cc875c2eSYuval Mintz 1698cc875c2eSYuval Mintz /* ACK everything */ 1699cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1700cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1701cc875c2eSYuval Mintz 1702cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 1703cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 1704cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 1705cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1706cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 1707cc875c2eSYuval Mintz (__force u32)val); 1708cc875c2eSYuval Mintz } 1709cc875c2eSYuval Mintz 1710cc875c2eSYuval Mintz if (!found) { 1711cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 1712cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 1713cc875c2eSYuval Mintz rc = -EINVAL; 1714cc875c2eSYuval Mintz } 1715cc875c2eSYuval Mintz 1716cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 1717cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1718cc875c2eSYuval Mintz 1719cc875c2eSYuval Mintz return rc; 1720cc875c2eSYuval Mintz } 1721cc875c2eSYuval Mintz 17221408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 17231408cc1fSYuval Mintz struct qed_ptt *p_ptt, 17241408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 1725fe56b9e6SYuval Mintz { 1726fe56b9e6SYuval Mintz u32 global_offsize; 1727fe56b9e6SYuval Mintz 17281408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 17291408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 17301408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 17311408cc1fSYuval Mintz 17321408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 17331408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 17341408cc1fSYuval Mintz return 0; 17351408cc1fSYuval Mintz } else { 17361408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 17371408cc1fSYuval Mintz QED_MSG_IOV, 17381408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 17391408cc1fSYuval Mintz return -EINVAL; 17401408cc1fSYuval Mintz } 17411408cc1fSYuval Mintz } 1742fe56b9e6SYuval Mintz 1743fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 17441408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 17451408cc1fSYuval Mintz mcp_info->public_base, 1746fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 17471408cc1fSYuval Mintz *p_mfw_ver = 17481408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 17491408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 17501408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 1751fe56b9e6SYuval Mintz 17521408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 17531408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 17541408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 17551408cc1fSYuval Mintz offsetof(struct public_global, 17561408cc1fSYuval Mintz running_bundle_id)); 17571408cc1fSYuval Mintz } 1758fe56b9e6SYuval Mintz 1759fe56b9e6SYuval Mintz return 0; 1760fe56b9e6SYuval Mintz } 1761fe56b9e6SYuval Mintz 1762ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 1763ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver) 1764ae33666aSTomer Tayar { 1765ae33666aSTomer Tayar u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 1766ae33666aSTomer Tayar 1767ae33666aSTomer Tayar if (IS_VF(p_hwfn->cdev)) 1768ae33666aSTomer Tayar return -EINVAL; 1769ae33666aSTomer Tayar 1770ae33666aSTomer Tayar /* Read the address of the nvm_cfg */ 1771ae33666aSTomer Tayar nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1772ae33666aSTomer Tayar if (!nvm_cfg_addr) { 1773ae33666aSTomer Tayar DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1774ae33666aSTomer Tayar return -EINVAL; 1775ae33666aSTomer Tayar } 1776ae33666aSTomer Tayar 1777ae33666aSTomer Tayar /* Read the offset of nvm_cfg1 */ 1778ae33666aSTomer Tayar nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1779ae33666aSTomer Tayar 1780ae33666aSTomer Tayar mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1781ae33666aSTomer Tayar offsetof(struct nvm_cfg1, glob) + 1782ae33666aSTomer Tayar offsetof(struct nvm_cfg1_glob, mbi_version); 1783ae33666aSTomer Tayar *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 1784ae33666aSTomer Tayar mbi_ver_addr) & 1785ae33666aSTomer Tayar (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 1786ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 1787ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 1788ae33666aSTomer Tayar 1789ae33666aSTomer Tayar return 0; 1790ae33666aSTomer Tayar } 1791ae33666aSTomer Tayar 17921a635e48SYuval Mintz int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) 1793cc875c2eSYuval Mintz { 1794cc875c2eSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 1795cc875c2eSYuval Mintz struct qed_ptt *p_ptt; 1796cc875c2eSYuval Mintz 17971408cc1fSYuval Mintz if (IS_VF(cdev)) 17981408cc1fSYuval Mintz return -EINVAL; 17991408cc1fSYuval Mintz 1800cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 1801cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1802cc875c2eSYuval Mintz return -EBUSY; 1803cc875c2eSYuval Mintz } 1804cc875c2eSYuval Mintz 1805cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 1806cc875c2eSYuval Mintz 1807cc875c2eSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 1808cc875c2eSYuval Mintz if (!p_ptt) 1809cc875c2eSYuval Mintz return -EBUSY; 1810cc875c2eSYuval Mintz 1811cc875c2eSYuval Mintz *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1812cc875c2eSYuval Mintz offsetof(struct public_port, media_type)); 1813cc875c2eSYuval Mintz 1814cc875c2eSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 1815cc875c2eSYuval Mintz 1816cc875c2eSYuval Mintz return 0; 1817cc875c2eSYuval Mintz } 1818cc875c2eSYuval Mintz 18196927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 18206927e826SMintz, Yuval static void 18216927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 18226927e826SMintz, Yuval enum qed_pci_personality *p_proto) 18236927e826SMintz, Yuval { 18246927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 18256927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 18266927e826SMintz, Yuval */ 18276927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 18286927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 18296927e826SMintz, Yuval else 18306927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 18316927e826SMintz, Yuval 18326927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 18336927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 18346927e826SMintz, Yuval (u32) *p_proto); 18356927e826SMintz, Yuval } 18366927e826SMintz, Yuval 18376927e826SMintz, Yuval static int 18386927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 18396927e826SMintz, Yuval struct qed_ptt *p_ptt, 18406927e826SMintz, Yuval enum qed_pci_personality *p_proto) 18416927e826SMintz, Yuval { 18426927e826SMintz, Yuval u32 resp = 0, param = 0; 18436927e826SMintz, Yuval int rc; 18446927e826SMintz, Yuval 18456927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 18466927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 18476927e826SMintz, Yuval if (rc) 18486927e826SMintz, Yuval return rc; 18496927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 18506927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 18516927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 18526927e826SMintz, Yuval resp); 18536927e826SMintz, Yuval return -EINVAL; 18546927e826SMintz, Yuval } 18556927e826SMintz, Yuval 18566927e826SMintz, Yuval switch (param) { 18576927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 18586927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 18596927e826SMintz, Yuval break; 18606927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 18616927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 18626927e826SMintz, Yuval break; 18636927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 1864e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_IWARP; 1865e0a8f9deSMichal Kalderon break; 1866e0a8f9deSMichal Kalderon case FW_MB_PARAM_GET_PF_RDMA_BOTH: 1867e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_RDMA; 1868e0a8f9deSMichal Kalderon break; 18696927e826SMintz, Yuval default: 18706927e826SMintz, Yuval DP_NOTICE(p_hwfn, 18716927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 18726927e826SMintz, Yuval param); 18736927e826SMintz, Yuval return -EINVAL; 18746927e826SMintz, Yuval } 18756927e826SMintz, Yuval 18766927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 18776927e826SMintz, Yuval NETIF_MSG_IFUP, 18786927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 18796927e826SMintz, Yuval (u32) *p_proto, resp, param); 18806927e826SMintz, Yuval return 0; 18816927e826SMintz, Yuval } 18826927e826SMintz, Yuval 1883fe56b9e6SYuval Mintz static int 1884fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 1885fe56b9e6SYuval Mintz struct public_func *p_info, 18866927e826SMintz, Yuval struct qed_ptt *p_ptt, 1887fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 1888fe56b9e6SYuval Mintz { 1889fe56b9e6SYuval Mintz int rc = 0; 1890fe56b9e6SYuval Mintz 1891fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 1892fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 18931fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 18941fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 18951fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 18966927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 1897fe56b9e6SYuval Mintz break; 1898c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 1899c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 1900c5ac9319SYuval Mintz break; 19011e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 19021e128c81SArun Easi *p_proto = QED_PCI_FCOE; 19031e128c81SArun Easi break; 1904c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 1905c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 19066927e826SMintz, Yuval /* Fallthrough */ 1907fe56b9e6SYuval Mintz default: 1908fe56b9e6SYuval Mintz rc = -EINVAL; 1909fe56b9e6SYuval Mintz } 1910fe56b9e6SYuval Mintz 1911fe56b9e6SYuval Mintz return rc; 1912fe56b9e6SYuval Mintz } 1913fe56b9e6SYuval Mintz 1914fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 1915fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 1916fe56b9e6SYuval Mintz { 1917fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 1918fe56b9e6SYuval Mintz struct public_func shmem_info; 1919fe56b9e6SYuval Mintz 19201a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1921fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 1922fe56b9e6SYuval Mintz 1923fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 1924fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 1925fe56b9e6SYuval Mintz 19266927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 19276927e826SMintz, Yuval &info->protocol)) { 1928fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 1929fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 1930fe56b9e6SYuval Mintz return -EINVAL; 1931fe56b9e6SYuval Mintz } 1932fe56b9e6SYuval Mintz 19334b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1934fe56b9e6SYuval Mintz 1935fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 1936fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 1937fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 1938fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 1939fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 1940fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 1941fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 194214d39648SMintz, Yuval 194314d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 194414d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 1945fe56b9e6SYuval Mintz } else { 1946fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 1947fe56b9e6SYuval Mintz } 1948fe56b9e6SYuval Mintz 194957796759SMintz, Yuval info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 195057796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 195157796759SMintz, Yuval info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 195257796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 1953fe56b9e6SYuval Mintz 1954fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 1955fe56b9e6SYuval Mintz 19560fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 19570fefbfbaSSudarsana Kalluru 195814d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 195914d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 196014d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 196114d39648SMintz, Yuval u32 resp = 0, param = 0; 196214d39648SMintz, Yuval int rc; 196314d39648SMintz, Yuval 196414d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 196514d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 196614d39648SMintz, Yuval if (rc) 196714d39648SMintz, Yuval return rc; 196814d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 196914d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 197014d39648SMintz, Yuval } 197114d39648SMintz, Yuval 1972fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 197314d39648SMintz, Yuval "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 1974fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 1975fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 1976fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 1977fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 197814d39648SMintz, Yuval info->wwn_port, info->wwn_node, 197914d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 1980fe56b9e6SYuval Mintz 1981fe56b9e6SYuval Mintz return 0; 1982fe56b9e6SYuval Mintz } 1983fe56b9e6SYuval Mintz 1984cc875c2eSYuval Mintz struct qed_mcp_link_params 1985cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 1986cc875c2eSYuval Mintz { 1987cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1988cc875c2eSYuval Mintz return NULL; 1989cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 1990cc875c2eSYuval Mintz } 1991cc875c2eSYuval Mintz 1992cc875c2eSYuval Mintz struct qed_mcp_link_state 1993cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 1994cc875c2eSYuval Mintz { 1995cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1996cc875c2eSYuval Mintz return NULL; 1997cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 1998cc875c2eSYuval Mintz } 1999cc875c2eSYuval Mintz 2000cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 2001cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 2002cc875c2eSYuval Mintz { 2003cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2004cc875c2eSYuval Mintz return NULL; 2005cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 2006cc875c2eSYuval Mintz } 2007cc875c2eSYuval Mintz 20081a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2009fe56b9e6SYuval Mintz { 2010fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 2011fe56b9e6SYuval Mintz int rc; 2012fe56b9e6SYuval Mintz 2013fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 20141a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 2015fe56b9e6SYuval Mintz 2016fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 20178f60bafeSYuval Mintz msleep(1020); 2018fe56b9e6SYuval Mintz 2019fe56b9e6SYuval Mintz return rc; 2020fe56b9e6SYuval Mintz } 2021fe56b9e6SYuval Mintz 2022cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 20231a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 2024cee4d264SManish Chopra { 2025cee4d264SManish Chopra u32 flash_size; 2026cee4d264SManish Chopra 20271408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 20281408cc1fSYuval Mintz return -EINVAL; 20291408cc1fSYuval Mintz 2030cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 2031cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 2032cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 2033cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 2034cee4d264SManish Chopra 2035cee4d264SManish Chopra *p_flash_size = flash_size; 2036cee4d264SManish Chopra 2037cee4d264SManish Chopra return 0; 2038cee4d264SManish Chopra } 2039cee4d264SManish Chopra 204088072fd4SMintz, Yuval static int 204188072fd4SMintz, Yuval qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 20421408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 20431408cc1fSYuval Mintz { 20441408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 20451408cc1fSYuval Mintz int rc; 20461408cc1fSYuval Mintz 20471408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 20481408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 20491408cc1fSYuval Mintz return 0; 20501408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 20511408cc1fSYuval Mintz 20521408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 20531408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 20541408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 20551408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 20561408cc1fSYuval Mintz 20571408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 20581408cc1fSYuval Mintz &resp, &rc_param); 20591408cc1fSYuval Mintz 20601408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 20611408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 20621408cc1fSYuval Mintz rc = -EINVAL; 20631408cc1fSYuval Mintz } else { 20641408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 20651408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 20661408cc1fSYuval Mintz num, vf_id); 20671408cc1fSYuval Mintz } 20681408cc1fSYuval Mintz 20691408cc1fSYuval Mintz return rc; 20701408cc1fSYuval Mintz } 20711408cc1fSYuval Mintz 207288072fd4SMintz, Yuval static int 207388072fd4SMintz, Yuval qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 207488072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 num) 207588072fd4SMintz, Yuval { 207688072fd4SMintz, Yuval u32 resp = 0, param = num, rc_param = 0; 207788072fd4SMintz, Yuval int rc; 207888072fd4SMintz, Yuval 207988072fd4SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 208088072fd4SMintz, Yuval param, &resp, &rc_param); 208188072fd4SMintz, Yuval 208288072fd4SMintz, Yuval if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 208388072fd4SMintz, Yuval DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 208488072fd4SMintz, Yuval rc = -EINVAL; 208588072fd4SMintz, Yuval } else { 208688072fd4SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_IOV, 208788072fd4SMintz, Yuval "Requested 0x%02x MSI-x interrupts for VFs\n", num); 208888072fd4SMintz, Yuval } 208988072fd4SMintz, Yuval 209088072fd4SMintz, Yuval return rc; 209188072fd4SMintz, Yuval } 209288072fd4SMintz, Yuval 209388072fd4SMintz, Yuval int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 209488072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 vf_id, u8 num) 209588072fd4SMintz, Yuval { 209688072fd4SMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 209788072fd4SMintz, Yuval return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 209888072fd4SMintz, Yuval else 209988072fd4SMintz, Yuval return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 210088072fd4SMintz, Yuval } 210188072fd4SMintz, Yuval 2102fe56b9e6SYuval Mintz int 2103fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2104fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2105fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 2106fe56b9e6SYuval Mintz { 21075529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 21082f67af8cSTomer Tayar struct drv_version_stc drv_version; 21095529bad9STomer Tayar __be32 val; 21105529bad9STomer Tayar u32 i; 21115529bad9STomer Tayar int rc; 2112fe56b9e6SYuval Mintz 21132f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 21142f67af8cSTomer Tayar drv_version.version = p_ver->version; 211567a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 211667a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 21172f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2118fe56b9e6SYuval Mintz } 2119fe56b9e6SYuval Mintz 21205529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 21215529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 21222f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 21232f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 21245529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 21255529bad9STomer Tayar if (rc) 2126fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2127fe56b9e6SYuval Mintz 21285529bad9STomer Tayar return rc; 2129fe56b9e6SYuval Mintz } 213091420b83SSudarsana Kalluru 213176271809STomer Tayar /* A maximal 100 msec waiting time for the MCP to halt */ 213276271809STomer Tayar #define QED_MCP_HALT_SLEEP_MS 10 213376271809STomer Tayar #define QED_MCP_HALT_MAX_RETRIES 10 213476271809STomer Tayar 21354102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 21364102426fSTomer Tayar { 213776271809STomer Tayar u32 resp = 0, param = 0, cpu_state, cnt = 0; 21384102426fSTomer Tayar int rc; 21394102426fSTomer Tayar 21404102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 21414102426fSTomer Tayar ¶m); 214276271809STomer Tayar if (rc) { 21434102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 21444102426fSTomer Tayar return rc; 21454102426fSTomer Tayar } 21464102426fSTomer Tayar 214776271809STomer Tayar do { 214876271809STomer Tayar msleep(QED_MCP_HALT_SLEEP_MS); 214976271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 215076271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) 215176271809STomer Tayar break; 215276271809STomer Tayar } while (++cnt < QED_MCP_HALT_MAX_RETRIES); 215376271809STomer Tayar 215476271809STomer Tayar if (cnt == QED_MCP_HALT_MAX_RETRIES) { 215576271809STomer Tayar DP_NOTICE(p_hwfn, 215676271809STomer Tayar "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 215776271809STomer Tayar qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state); 215876271809STomer Tayar return -EBUSY; 215976271809STomer Tayar } 216076271809STomer Tayar 216176271809STomer Tayar return 0; 216276271809STomer Tayar } 216376271809STomer Tayar 216476271809STomer Tayar #define QED_MCP_RESUME_SLEEP_MS 10 216576271809STomer Tayar 21664102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 21674102426fSTomer Tayar { 216876271809STomer Tayar u32 cpu_mode, cpu_state; 21694102426fSTomer Tayar 21704102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 21714102426fSTomer Tayar 21724102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 217376271809STomer Tayar cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT; 217476271809STomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode); 217576271809STomer Tayar msleep(QED_MCP_RESUME_SLEEP_MS); 217676271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 21774102426fSTomer Tayar 217876271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) { 217976271809STomer Tayar DP_NOTICE(p_hwfn, 218076271809STomer Tayar "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 218176271809STomer Tayar cpu_mode, cpu_state); 218276271809STomer Tayar return -EBUSY; 218376271809STomer Tayar } 218476271809STomer Tayar 218576271809STomer Tayar return 0; 21864102426fSTomer Tayar } 21874102426fSTomer Tayar 21880fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 21890fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 21900fefbfbaSSudarsana Kalluru enum qed_ov_client client) 21910fefbfbaSSudarsana Kalluru { 21920fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 21930fefbfbaSSudarsana Kalluru u32 drv_mb_param; 21940fefbfbaSSudarsana Kalluru int rc; 21950fefbfbaSSudarsana Kalluru 21960fefbfbaSSudarsana Kalluru switch (client) { 21970fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 21980fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 21990fefbfbaSSudarsana Kalluru break; 22000fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 22010fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 22020fefbfbaSSudarsana Kalluru break; 22030fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 22040fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 22050fefbfbaSSudarsana Kalluru break; 22060fefbfbaSSudarsana Kalluru default: 22070fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 22080fefbfbaSSudarsana Kalluru return -EINVAL; 22090fefbfbaSSudarsana Kalluru } 22100fefbfbaSSudarsana Kalluru 22110fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 22120fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 22130fefbfbaSSudarsana Kalluru if (rc) 22140fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 22150fefbfbaSSudarsana Kalluru 22160fefbfbaSSudarsana Kalluru return rc; 22170fefbfbaSSudarsana Kalluru } 22180fefbfbaSSudarsana Kalluru 22190fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 22200fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 22210fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 22220fefbfbaSSudarsana Kalluru { 22230fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 22240fefbfbaSSudarsana Kalluru u32 drv_mb_param; 22250fefbfbaSSudarsana Kalluru int rc; 22260fefbfbaSSudarsana Kalluru 22270fefbfbaSSudarsana Kalluru switch (drv_state) { 22280fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 22290fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 22300fefbfbaSSudarsana Kalluru break; 22310fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 22320fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 22330fefbfbaSSudarsana Kalluru break; 22340fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 22350fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 22360fefbfbaSSudarsana Kalluru break; 22370fefbfbaSSudarsana Kalluru default: 22380fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 22390fefbfbaSSudarsana Kalluru return -EINVAL; 22400fefbfbaSSudarsana Kalluru } 22410fefbfbaSSudarsana Kalluru 22420fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 22430fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 22440fefbfbaSSudarsana Kalluru if (rc) 22450fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 22460fefbfbaSSudarsana Kalluru 22470fefbfbaSSudarsana Kalluru return rc; 22480fefbfbaSSudarsana Kalluru } 22490fefbfbaSSudarsana Kalluru 22500fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 22510fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 22520fefbfbaSSudarsana Kalluru { 22530fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 22540fefbfbaSSudarsana Kalluru u32 drv_mb_param; 22550fefbfbaSSudarsana Kalluru int rc; 22560fefbfbaSSudarsana Kalluru 22570fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 22580fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 22590fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 22600fefbfbaSSudarsana Kalluru if (rc) 22610fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 22620fefbfbaSSudarsana Kalluru 22630fefbfbaSSudarsana Kalluru return rc; 22640fefbfbaSSudarsana Kalluru } 22650fefbfbaSSudarsana Kalluru 22660fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 22670fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 22680fefbfbaSSudarsana Kalluru { 22690fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 227017991002SMintz, Yuval u32 mfw_mac[2]; 22710fefbfbaSSudarsana Kalluru int rc; 22720fefbfbaSSudarsana Kalluru 22730fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 22740fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 22750fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 22760fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 22770fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 22782f67af8cSTomer Tayar 227917991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 228017991002SMintz, Yuval * in 32-bit granularity. 228117991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 228217991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 228317991002SMintz, Yuval */ 228417991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 228517991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 228617991002SMintz, Yuval 228717991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 228817991002SMintz, Yuval mb_params.data_src_size = 8; 22890fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 22900fefbfbaSSudarsana Kalluru if (rc) 22910fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 22920fefbfbaSSudarsana Kalluru 229314d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 229414d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 229514d39648SMintz, Yuval 22960fefbfbaSSudarsana Kalluru return rc; 22970fefbfbaSSudarsana Kalluru } 22980fefbfbaSSudarsana Kalluru 22990fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 23000fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 23010fefbfbaSSudarsana Kalluru { 23020fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 23030fefbfbaSSudarsana Kalluru u32 drv_mb_param; 23040fefbfbaSSudarsana Kalluru int rc; 23050fefbfbaSSudarsana Kalluru 230614d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 230714d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 230814d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 230914d39648SMintz, Yuval return -EINVAL; 231014d39648SMintz, Yuval } 231114d39648SMintz, Yuval 23120fefbfbaSSudarsana Kalluru switch (wol) { 23130fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 23140fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 23150fefbfbaSSudarsana Kalluru break; 23160fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 23170fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 23180fefbfbaSSudarsana Kalluru break; 23190fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 23200fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 23210fefbfbaSSudarsana Kalluru break; 23220fefbfbaSSudarsana Kalluru default: 23230fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 23240fefbfbaSSudarsana Kalluru return -EINVAL; 23250fefbfbaSSudarsana Kalluru } 23260fefbfbaSSudarsana Kalluru 23270fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 23280fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 23290fefbfbaSSudarsana Kalluru if (rc) 23300fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 23310fefbfbaSSudarsana Kalluru 233214d39648SMintz, Yuval /* Store the WoL update for a future unload */ 233314d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 233414d39648SMintz, Yuval 23350fefbfbaSSudarsana Kalluru return rc; 23360fefbfbaSSudarsana Kalluru } 23370fefbfbaSSudarsana Kalluru 23380fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 23390fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 23400fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 23410fefbfbaSSudarsana Kalluru { 23420fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 23430fefbfbaSSudarsana Kalluru u32 drv_mb_param; 23440fefbfbaSSudarsana Kalluru int rc; 23450fefbfbaSSudarsana Kalluru 23460fefbfbaSSudarsana Kalluru switch (eswitch) { 23470fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 23480fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 23490fefbfbaSSudarsana Kalluru break; 23500fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 23510fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 23520fefbfbaSSudarsana Kalluru break; 23530fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 23540fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 23550fefbfbaSSudarsana Kalluru break; 23560fefbfbaSSudarsana Kalluru default: 23570fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 23580fefbfbaSSudarsana Kalluru return -EINVAL; 23590fefbfbaSSudarsana Kalluru } 23600fefbfbaSSudarsana Kalluru 23610fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 23620fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 23630fefbfbaSSudarsana Kalluru if (rc) 23640fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 23650fefbfbaSSudarsana Kalluru 23660fefbfbaSSudarsana Kalluru return rc; 23670fefbfbaSSudarsana Kalluru } 23680fefbfbaSSudarsana Kalluru 23691a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 23701a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 237191420b83SSudarsana Kalluru { 237291420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 237391420b83SSudarsana Kalluru int rc; 237491420b83SSudarsana Kalluru 237591420b83SSudarsana Kalluru switch (mode) { 237691420b83SSudarsana Kalluru case QED_LED_MODE_ON: 237791420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 237891420b83SSudarsana Kalluru break; 237991420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 238091420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 238191420b83SSudarsana Kalluru break; 238291420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 238391420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 238491420b83SSudarsana Kalluru break; 238591420b83SSudarsana Kalluru default: 238691420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 238791420b83SSudarsana Kalluru return -EINVAL; 238891420b83SSudarsana Kalluru } 238991420b83SSudarsana Kalluru 239091420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 239191420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 239291420b83SSudarsana Kalluru 239391420b83SSudarsana Kalluru return rc; 239491420b83SSudarsana Kalluru } 239503dc76caSSudarsana Reddy Kalluru 23964102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 23974102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 23984102426fSTomer Tayar { 23994102426fSTomer Tayar u32 resp = 0, param = 0; 24004102426fSTomer Tayar int rc; 24014102426fSTomer Tayar 24024102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 24034102426fSTomer Tayar mask_parities, &resp, ¶m); 24044102426fSTomer Tayar 24054102426fSTomer Tayar if (rc) { 24064102426fSTomer Tayar DP_ERR(p_hwfn, 24074102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 24084102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 24094102426fSTomer Tayar DP_ERR(p_hwfn, 24104102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 24114102426fSTomer Tayar rc = -EINVAL; 24124102426fSTomer Tayar } 24134102426fSTomer Tayar 24144102426fSTomer Tayar return rc; 24154102426fSTomer Tayar } 24164102426fSTomer Tayar 24177a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 24187a4b21b7SMintz, Yuval { 24197a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 24207a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 24217a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 24227a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 24237a4b21b7SMintz, Yuval int rc = 0; 24247a4b21b7SMintz, Yuval 24257a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 24267a4b21b7SMintz, Yuval if (!p_ptt) 24277a4b21b7SMintz, Yuval return -EBUSY; 24287a4b21b7SMintz, Yuval 24297a4b21b7SMintz, Yuval while (bytes_left > 0) { 24307a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 24317a4b21b7SMintz, Yuval 24327a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 24337a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 24347a4b21b7SMintz, Yuval addr + offset + 24357a4b21b7SMintz, Yuval (bytes_to_copy << 2436da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 24377a4b21b7SMintz, Yuval &resp, &resp_param, 24387a4b21b7SMintz, Yuval &read_len, 24397a4b21b7SMintz, Yuval (u32 *)(p_buf + offset)); 24407a4b21b7SMintz, Yuval 24417a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 24427a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 24437a4b21b7SMintz, Yuval break; 24447a4b21b7SMintz, Yuval } 24457a4b21b7SMintz, Yuval 24467a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 24477a4b21b7SMintz, Yuval * isn't preemptable. Sleep a bit to prevent CPU hogging. 24487a4b21b7SMintz, Yuval */ 24497a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 24507a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 24517a4b21b7SMintz, Yuval usleep_range(1000, 2000); 24527a4b21b7SMintz, Yuval 24537a4b21b7SMintz, Yuval offset += read_len; 24547a4b21b7SMintz, Yuval bytes_left -= read_len; 24557a4b21b7SMintz, Yuval } 24567a4b21b7SMintz, Yuval 24577a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 24587a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 24597a4b21b7SMintz, Yuval 24607a4b21b7SMintz, Yuval return rc; 24617a4b21b7SMintz, Yuval } 24627a4b21b7SMintz, Yuval 246362e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 246462e4d438SSudarsana Reddy Kalluru { 246562e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 246662e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 246762e4d438SSudarsana Reddy Kalluru 246862e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 246962e4d438SSudarsana Reddy Kalluru if (!p_ptt) 247062e4d438SSudarsana Reddy Kalluru return -EBUSY; 247162e4d438SSudarsana Reddy Kalluru 247262e4d438SSudarsana Reddy Kalluru memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 247362e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 247462e4d438SSudarsana Reddy Kalluru 247562e4d438SSudarsana Reddy Kalluru return 0; 247662e4d438SSudarsana Reddy Kalluru } 247762e4d438SSudarsana Reddy Kalluru 247862e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr) 247962e4d438SSudarsana Reddy Kalluru { 248062e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 248162e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 248262e4d438SSudarsana Reddy Kalluru u32 resp, param; 248362e4d438SSudarsana Reddy Kalluru int rc; 248462e4d438SSudarsana Reddy Kalluru 248562e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 248662e4d438SSudarsana Reddy Kalluru if (!p_ptt) 248762e4d438SSudarsana Reddy Kalluru return -EBUSY; 248862e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr, 248962e4d438SSudarsana Reddy Kalluru &resp, ¶m); 249062e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 249162e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 249262e4d438SSudarsana Reddy Kalluru 249362e4d438SSudarsana Reddy Kalluru return rc; 249462e4d438SSudarsana Reddy Kalluru } 249562e4d438SSudarsana Reddy Kalluru 249662e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 249762e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len) 249862e4d438SSudarsana Reddy Kalluru { 249962e4d438SSudarsana Reddy Kalluru u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 250062e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 250162e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 250262e4d438SSudarsana Reddy Kalluru int rc = -EINVAL; 250362e4d438SSudarsana Reddy Kalluru 250462e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 250562e4d438SSudarsana Reddy Kalluru if (!p_ptt) 250662e4d438SSudarsana Reddy Kalluru return -EBUSY; 250762e4d438SSudarsana Reddy Kalluru 250862e4d438SSudarsana Reddy Kalluru switch (cmd) { 250962e4d438SSudarsana Reddy Kalluru case QED_PUT_FILE_DATA: 251062e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 251162e4d438SSudarsana Reddy Kalluru break; 251262e4d438SSudarsana Reddy Kalluru case QED_NVM_WRITE_NVRAM: 251362e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 251462e4d438SSudarsana Reddy Kalluru break; 251562e4d438SSudarsana Reddy Kalluru default: 251662e4d438SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 251762e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 251862e4d438SSudarsana Reddy Kalluru goto out; 251962e4d438SSudarsana Reddy Kalluru } 252062e4d438SSudarsana Reddy Kalluru 252162e4d438SSudarsana Reddy Kalluru while (buf_idx < len) { 252262e4d438SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 252362e4d438SSudarsana Reddy Kalluru nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) | 252462e4d438SSudarsana Reddy Kalluru addr) + buf_idx; 252562e4d438SSudarsana Reddy Kalluru rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 252662e4d438SSudarsana Reddy Kalluru &resp, ¶m, buf_size, 252762e4d438SSudarsana Reddy Kalluru (u32 *)&p_buf[buf_idx]); 252862e4d438SSudarsana Reddy Kalluru if (rc) { 252962e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 253062e4d438SSudarsana Reddy Kalluru resp = FW_MSG_CODE_ERROR; 253162e4d438SSudarsana Reddy Kalluru break; 253262e4d438SSudarsana Reddy Kalluru } 253362e4d438SSudarsana Reddy Kalluru 253462e4d438SSudarsana Reddy Kalluru if (resp != FW_MSG_CODE_OK && 253562e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_OK && 253662e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 253762e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, 253862e4d438SSudarsana Reddy Kalluru "nvm write failed, resp = 0x%08x\n", resp); 253962e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 254062e4d438SSudarsana Reddy Kalluru break; 254162e4d438SSudarsana Reddy Kalluru } 254262e4d438SSudarsana Reddy Kalluru 254362e4d438SSudarsana Reddy Kalluru /* This can be a lengthy process, and it's possible scheduler 254462e4d438SSudarsana Reddy Kalluru * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 254562e4d438SSudarsana Reddy Kalluru */ 254662e4d438SSudarsana Reddy Kalluru if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 254762e4d438SSudarsana Reddy Kalluru usleep_range(1000, 2000); 254862e4d438SSudarsana Reddy Kalluru 254962e4d438SSudarsana Reddy Kalluru buf_idx += buf_size; 255062e4d438SSudarsana Reddy Kalluru } 255162e4d438SSudarsana Reddy Kalluru 255262e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 255362e4d438SSudarsana Reddy Kalluru out: 255462e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 255562e4d438SSudarsana Reddy Kalluru 255662e4d438SSudarsana Reddy Kalluru return rc; 255762e4d438SSudarsana Reddy Kalluru } 255862e4d438SSudarsana Reddy Kalluru 2559b51dab46SSudarsana Reddy Kalluru int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2560b51dab46SSudarsana Reddy Kalluru u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 2561b51dab46SSudarsana Reddy Kalluru { 2562b51dab46SSudarsana Reddy Kalluru u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 2563b51dab46SSudarsana Reddy Kalluru u32 resp, param; 2564b51dab46SSudarsana Reddy Kalluru int rc; 2565b51dab46SSudarsana Reddy Kalluru 2566b51dab46SSudarsana Reddy Kalluru nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 2567b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 2568b51dab46SSudarsana Reddy Kalluru nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 2569b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 2570b51dab46SSudarsana Reddy Kalluru 2571b51dab46SSudarsana Reddy Kalluru addr = offset; 2572b51dab46SSudarsana Reddy Kalluru offset = 0; 2573b51dab46SSudarsana Reddy Kalluru bytes_left = len; 2574b51dab46SSudarsana Reddy Kalluru while (bytes_left > 0) { 2575b51dab46SSudarsana Reddy Kalluru bytes_to_copy = min_t(u32, bytes_left, 2576b51dab46SSudarsana Reddy Kalluru MAX_I2C_TRANSACTION_SIZE); 2577b51dab46SSudarsana Reddy Kalluru nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 2578b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 2579b51dab46SSudarsana Reddy Kalluru nvm_offset |= ((addr + offset) << 2580b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 2581b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 2582b51dab46SSudarsana Reddy Kalluru nvm_offset |= (bytes_to_copy << 2583b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 2584b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 2585b51dab46SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2586b51dab46SSudarsana Reddy Kalluru DRV_MSG_CODE_TRANSCEIVER_READ, 2587b51dab46SSudarsana Reddy Kalluru nvm_offset, &resp, ¶m, &buf_size, 2588b51dab46SSudarsana Reddy Kalluru (u32 *)(p_buf + offset)); 2589b51dab46SSudarsana Reddy Kalluru if (rc) { 2590b51dab46SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 2591b51dab46SSudarsana Reddy Kalluru "Failed to send a transceiver read command to the MFW. rc = %d.\n", 2592b51dab46SSudarsana Reddy Kalluru rc); 2593b51dab46SSudarsana Reddy Kalluru return rc; 2594b51dab46SSudarsana Reddy Kalluru } 2595b51dab46SSudarsana Reddy Kalluru 2596b51dab46SSudarsana Reddy Kalluru if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 2597b51dab46SSudarsana Reddy Kalluru return -ENODEV; 2598b51dab46SSudarsana Reddy Kalluru else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 2599b51dab46SSudarsana Reddy Kalluru return -EINVAL; 2600b51dab46SSudarsana Reddy Kalluru 2601b51dab46SSudarsana Reddy Kalluru offset += buf_size; 2602b51dab46SSudarsana Reddy Kalluru bytes_left -= buf_size; 2603b51dab46SSudarsana Reddy Kalluru } 2604b51dab46SSudarsana Reddy Kalluru 2605b51dab46SSudarsana Reddy Kalluru return 0; 2606b51dab46SSudarsana Reddy Kalluru } 2607b51dab46SSudarsana Reddy Kalluru 260803dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 260903dc76caSSudarsana Reddy Kalluru { 261003dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 261103dc76caSSudarsana Reddy Kalluru int rc = 0; 261203dc76caSSudarsana Reddy Kalluru 261303dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 261403dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 261503dc76caSSudarsana Reddy Kalluru 261603dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 261703dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 261803dc76caSSudarsana Reddy Kalluru 261903dc76caSSudarsana Reddy Kalluru if (rc) 262003dc76caSSudarsana Reddy Kalluru return rc; 262103dc76caSSudarsana Reddy Kalluru 262203dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 262303dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 262403dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 262503dc76caSSudarsana Reddy Kalluru 262603dc76caSSudarsana Reddy Kalluru return rc; 262703dc76caSSudarsana Reddy Kalluru } 262803dc76caSSudarsana Reddy Kalluru 262903dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 263003dc76caSSudarsana Reddy Kalluru { 263103dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 263203dc76caSSudarsana Reddy Kalluru int rc = 0; 263303dc76caSSudarsana Reddy Kalluru 263403dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 263503dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 263603dc76caSSudarsana Reddy Kalluru 263703dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 263803dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 263903dc76caSSudarsana Reddy Kalluru 264003dc76caSSudarsana Reddy Kalluru if (rc) 264103dc76caSSudarsana Reddy Kalluru return rc; 264203dc76caSSudarsana Reddy Kalluru 264303dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 264403dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 264503dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 264603dc76caSSudarsana Reddy Kalluru 264703dc76caSSudarsana Reddy Kalluru return rc; 264803dc76caSSudarsana Reddy Kalluru } 26497a4b21b7SMintz, Yuval 265043645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 26517a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 26527a4b21b7SMintz, Yuval u32 *num_images) 26537a4b21b7SMintz, Yuval { 26547a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 26557a4b21b7SMintz, Yuval int rc = 0; 26567a4b21b7SMintz, Yuval 26577a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 26587a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 26597a4b21b7SMintz, Yuval 26607a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 26617a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 26627a4b21b7SMintz, Yuval if (rc) 26637a4b21b7SMintz, Yuval return rc; 26647a4b21b7SMintz, Yuval 26657a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 26667a4b21b7SMintz, Yuval rc = -EINVAL; 26677a4b21b7SMintz, Yuval 26687a4b21b7SMintz, Yuval return rc; 26697a4b21b7SMintz, Yuval } 26707a4b21b7SMintz, Yuval 267143645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 26727a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 26737a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 26747a4b21b7SMintz, Yuval u32 image_index) 26757a4b21b7SMintz, Yuval { 26767a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 26777a4b21b7SMintz, Yuval int rc; 26787a4b21b7SMintz, Yuval 26797a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 26807a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 26817a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 26827a4b21b7SMintz, Yuval 26837a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 26847a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 26857a4b21b7SMintz, Yuval &resp, &resp_param, 26867a4b21b7SMintz, Yuval &buf_size, 26877a4b21b7SMintz, Yuval (u32 *)p_image_att); 26887a4b21b7SMintz, Yuval if (rc) 26897a4b21b7SMintz, Yuval return rc; 26907a4b21b7SMintz, Yuval 26917a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 26927a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 26937a4b21b7SMintz, Yuval rc = -EINVAL; 26947a4b21b7SMintz, Yuval 26957a4b21b7SMintz, Yuval return rc; 26967a4b21b7SMintz, Yuval } 26972edbff8dSTomer Tayar 269843645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 269943645ce0SSudarsana Reddy Kalluru { 27005e7ba042SDenis Bolotin struct qed_nvm_image_info nvm_info; 270143645ce0SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 270243645ce0SSudarsana Reddy Kalluru int rc; 270343645ce0SSudarsana Reddy Kalluru u32 i; 270443645ce0SSudarsana Reddy Kalluru 27055e7ba042SDenis Bolotin if (p_hwfn->nvm_info.valid) 27065e7ba042SDenis Bolotin return 0; 27075e7ba042SDenis Bolotin 270843645ce0SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 270943645ce0SSudarsana Reddy Kalluru if (!p_ptt) { 271043645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "failed to acquire ptt\n"); 271143645ce0SSudarsana Reddy Kalluru return -EBUSY; 271243645ce0SSudarsana Reddy Kalluru } 271343645ce0SSudarsana Reddy Kalluru 271443645ce0SSudarsana Reddy Kalluru /* Acquire from MFW the amount of available images */ 27155e7ba042SDenis Bolotin nvm_info.num_images = 0; 271643645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 27175e7ba042SDenis Bolotin p_ptt, &nvm_info.num_images); 271843645ce0SSudarsana Reddy Kalluru if (rc == -EOPNOTSUPP) { 271943645ce0SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 272043645ce0SSudarsana Reddy Kalluru goto out; 27215e7ba042SDenis Bolotin } else if (rc || !nvm_info.num_images) { 272243645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Failed getting number of images\n"); 272343645ce0SSudarsana Reddy Kalluru goto err0; 272443645ce0SSudarsana Reddy Kalluru } 272543645ce0SSudarsana Reddy Kalluru 27265e7ba042SDenis Bolotin nvm_info.image_att = kmalloc_array(nvm_info.num_images, 272743645ce0SSudarsana Reddy Kalluru sizeof(struct bist_nvm_image_att), 272843645ce0SSudarsana Reddy Kalluru GFP_KERNEL); 27295e7ba042SDenis Bolotin if (!nvm_info.image_att) { 273043645ce0SSudarsana Reddy Kalluru rc = -ENOMEM; 273143645ce0SSudarsana Reddy Kalluru goto err0; 273243645ce0SSudarsana Reddy Kalluru } 273343645ce0SSudarsana Reddy Kalluru 273443645ce0SSudarsana Reddy Kalluru /* Iterate over images and get their attributes */ 27355e7ba042SDenis Bolotin for (i = 0; i < nvm_info.num_images; i++) { 273643645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 27375e7ba042SDenis Bolotin &nvm_info.image_att[i], i); 273843645ce0SSudarsana Reddy Kalluru if (rc) { 273943645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, 274043645ce0SSudarsana Reddy Kalluru "Failed getting image index %d attributes\n", i); 274143645ce0SSudarsana Reddy Kalluru goto err1; 274243645ce0SSudarsana Reddy Kalluru } 274343645ce0SSudarsana Reddy Kalluru 274443645ce0SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 27455e7ba042SDenis Bolotin nvm_info.image_att[i].len); 274643645ce0SSudarsana Reddy Kalluru } 274743645ce0SSudarsana Reddy Kalluru out: 27485e7ba042SDenis Bolotin /* Update hwfn's nvm_info */ 27495e7ba042SDenis Bolotin if (nvm_info.num_images) { 27505e7ba042SDenis Bolotin p_hwfn->nvm_info.num_images = nvm_info.num_images; 27515e7ba042SDenis Bolotin kfree(p_hwfn->nvm_info.image_att); 27525e7ba042SDenis Bolotin p_hwfn->nvm_info.image_att = nvm_info.image_att; 27535e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = true; 27545e7ba042SDenis Bolotin } 27555e7ba042SDenis Bolotin 275643645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 275743645ce0SSudarsana Reddy Kalluru return 0; 275843645ce0SSudarsana Reddy Kalluru 275943645ce0SSudarsana Reddy Kalluru err1: 27605e7ba042SDenis Bolotin kfree(nvm_info.image_att); 276143645ce0SSudarsana Reddy Kalluru err0: 276243645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 276343645ce0SSudarsana Reddy Kalluru return rc; 276443645ce0SSudarsana Reddy Kalluru } 276543645ce0SSudarsana Reddy Kalluru 27661ac4329aSDenis Bolotin int 276720675b37SMintz, Yuval qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 276820675b37SMintz, Yuval enum qed_nvm_images image_id, 276920675b37SMintz, Yuval struct qed_nvm_image_att *p_image_att) 277020675b37SMintz, Yuval { 277120675b37SMintz, Yuval enum nvm_image_type type; 277243645ce0SSudarsana Reddy Kalluru u32 i; 277320675b37SMintz, Yuval 277420675b37SMintz, Yuval /* Translate image_id into MFW definitions */ 277520675b37SMintz, Yuval switch (image_id) { 277620675b37SMintz, Yuval case QED_NVM_IMAGE_ISCSI_CFG: 277720675b37SMintz, Yuval type = NVM_TYPE_ISCSI_CFG; 277820675b37SMintz, Yuval break; 277920675b37SMintz, Yuval case QED_NVM_IMAGE_FCOE_CFG: 278020675b37SMintz, Yuval type = NVM_TYPE_FCOE_CFG; 278120675b37SMintz, Yuval break; 27821ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_CFG1: 27831ac4329aSDenis Bolotin type = NVM_TYPE_NVM_CFG1; 27841ac4329aSDenis Bolotin break; 27851ac4329aSDenis Bolotin case QED_NVM_IMAGE_DEFAULT_CFG: 27861ac4329aSDenis Bolotin type = NVM_TYPE_DEFAULT_CFG; 27871ac4329aSDenis Bolotin break; 27881ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_META: 27891ac4329aSDenis Bolotin type = NVM_TYPE_META; 27901ac4329aSDenis Bolotin break; 279120675b37SMintz, Yuval default: 279220675b37SMintz, Yuval DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 279320675b37SMintz, Yuval image_id); 279420675b37SMintz, Yuval return -EINVAL; 279520675b37SMintz, Yuval } 279620675b37SMintz, Yuval 27975e7ba042SDenis Bolotin qed_mcp_nvm_info_populate(p_hwfn); 279843645ce0SSudarsana Reddy Kalluru for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 279943645ce0SSudarsana Reddy Kalluru if (type == p_hwfn->nvm_info.image_att[i].image_type) 280020675b37SMintz, Yuval break; 280143645ce0SSudarsana Reddy Kalluru if (i == p_hwfn->nvm_info.num_images) { 280220675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 280320675b37SMintz, Yuval "Failed to find nvram image of type %08x\n", 280420675b37SMintz, Yuval image_id); 280543645ce0SSudarsana Reddy Kalluru return -ENOENT; 280620675b37SMintz, Yuval } 280720675b37SMintz, Yuval 280843645ce0SSudarsana Reddy Kalluru p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 280943645ce0SSudarsana Reddy Kalluru p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 281020675b37SMintz, Yuval 281120675b37SMintz, Yuval return 0; 281220675b37SMintz, Yuval } 281320675b37SMintz, Yuval 281420675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 281520675b37SMintz, Yuval enum qed_nvm_images image_id, 281620675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len) 281720675b37SMintz, Yuval { 281820675b37SMintz, Yuval struct qed_nvm_image_att image_att; 281920675b37SMintz, Yuval int rc; 282020675b37SMintz, Yuval 282120675b37SMintz, Yuval memset(p_buffer, 0, buffer_len); 282220675b37SMintz, Yuval 2823b60bfdfeSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 282420675b37SMintz, Yuval if (rc) 282520675b37SMintz, Yuval return rc; 282620675b37SMintz, Yuval 282720675b37SMintz, Yuval /* Validate sizes - both the image's and the supplied buffer's */ 282820675b37SMintz, Yuval if (image_att.length <= 4) { 282920675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 283020675b37SMintz, Yuval "Image [%d] is too small - only %d bytes\n", 283120675b37SMintz, Yuval image_id, image_att.length); 283220675b37SMintz, Yuval return -EINVAL; 283320675b37SMintz, Yuval } 283420675b37SMintz, Yuval 283520675b37SMintz, Yuval if (image_att.length > buffer_len) { 283620675b37SMintz, Yuval DP_VERBOSE(p_hwfn, 283720675b37SMintz, Yuval QED_MSG_STORAGE, 283820675b37SMintz, Yuval "Image [%d] is too big - %08x bytes where only %08x are available\n", 283920675b37SMintz, Yuval image_id, image_att.length, buffer_len); 284020675b37SMintz, Yuval return -ENOMEM; 284120675b37SMintz, Yuval } 284220675b37SMintz, Yuval 284320675b37SMintz, Yuval return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 284420675b37SMintz, Yuval p_buffer, image_att.length); 284520675b37SMintz, Yuval } 284620675b37SMintz, Yuval 28479c8517c4STomer Tayar static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 28489c8517c4STomer Tayar { 28499c8517c4STomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 28509c8517c4STomer Tayar 28519c8517c4STomer Tayar switch (res_id) { 28529c8517c4STomer Tayar case QED_SB: 28539c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 28549c8517c4STomer Tayar break; 28559c8517c4STomer Tayar case QED_L2_QUEUE: 28569c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 28579c8517c4STomer Tayar break; 28589c8517c4STomer Tayar case QED_VPORT: 28599c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 28609c8517c4STomer Tayar break; 28619c8517c4STomer Tayar case QED_RSS_ENG: 28629c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 28639c8517c4STomer Tayar break; 28649c8517c4STomer Tayar case QED_PQ: 28659c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 28669c8517c4STomer Tayar break; 28679c8517c4STomer Tayar case QED_RL: 28689c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 28699c8517c4STomer Tayar break; 28709c8517c4STomer Tayar case QED_MAC: 28719c8517c4STomer Tayar case QED_VLAN: 28729c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 28739c8517c4STomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 28749c8517c4STomer Tayar break; 28759c8517c4STomer Tayar case QED_ILT: 28769c8517c4STomer Tayar mfw_res_id = RESOURCE_ILT_E; 28779c8517c4STomer Tayar break; 28789c8517c4STomer Tayar case QED_LL2_QUEUE: 28799c8517c4STomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 28809c8517c4STomer Tayar break; 28819c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 28829c8517c4STomer Tayar case QED_CMDQS_CQS: 28839c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 28849c8517c4STomer Tayar mfw_res_id = RESOURCE_CQS_E; 28859c8517c4STomer Tayar break; 28869c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 28879c8517c4STomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 28889c8517c4STomer Tayar break; 28899c8517c4STomer Tayar case QED_BDQ: 28909c8517c4STomer Tayar mfw_res_id = RESOURCE_BDQ_E; 28919c8517c4STomer Tayar break; 28929c8517c4STomer Tayar default: 28939c8517c4STomer Tayar break; 28949c8517c4STomer Tayar } 28959c8517c4STomer Tayar 28969c8517c4STomer Tayar return mfw_res_id; 28979c8517c4STomer Tayar } 28989c8517c4STomer Tayar 28999c8517c4STomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 2 29002edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 29012edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 29022edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 29032edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 29042edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 29052edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 29069c8517c4STomer Tayar 29079c8517c4STomer Tayar struct qed_resc_alloc_in_params { 29089c8517c4STomer Tayar u32 cmd; 29099c8517c4STomer Tayar enum qed_resources res_id; 29109c8517c4STomer Tayar u32 resc_max_val; 29119c8517c4STomer Tayar }; 29129c8517c4STomer Tayar 29139c8517c4STomer Tayar struct qed_resc_alloc_out_params { 29149c8517c4STomer Tayar u32 mcp_resp; 29159c8517c4STomer Tayar u32 mcp_param; 29169c8517c4STomer Tayar u32 resc_num; 29179c8517c4STomer Tayar u32 resc_start; 29189c8517c4STomer Tayar u32 vf_resc_num; 29199c8517c4STomer Tayar u32 vf_resc_start; 29209c8517c4STomer Tayar u32 flags; 29219c8517c4STomer Tayar }; 29229c8517c4STomer Tayar 29239c8517c4STomer Tayar static int 29249c8517c4STomer Tayar qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 29252edbff8dSTomer Tayar struct qed_ptt *p_ptt, 29269c8517c4STomer Tayar struct qed_resc_alloc_in_params *p_in_params, 29279c8517c4STomer Tayar struct qed_resc_alloc_out_params *p_out_params) 29282edbff8dSTomer Tayar { 29292edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 29309c8517c4STomer Tayar struct resource_info mfw_resc_info; 29312edbff8dSTomer Tayar int rc; 29322edbff8dSTomer Tayar 29339c8517c4STomer Tayar memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 2934bb480242SMintz, Yuval 29359c8517c4STomer Tayar mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 29369c8517c4STomer Tayar if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 29379c8517c4STomer Tayar DP_ERR(p_hwfn, 29389c8517c4STomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 29399c8517c4STomer Tayar p_in_params->res_id, 29409c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id)); 29419c8517c4STomer Tayar return -EINVAL; 29429c8517c4STomer Tayar } 29439c8517c4STomer Tayar 29449c8517c4STomer Tayar switch (p_in_params->cmd) { 29459c8517c4STomer Tayar case DRV_MSG_SET_RESOURCE_VALUE_MSG: 29469c8517c4STomer Tayar mfw_resc_info.size = p_in_params->resc_max_val; 29479c8517c4STomer Tayar /* Fallthrough */ 29489c8517c4STomer Tayar case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 29499c8517c4STomer Tayar break; 29509c8517c4STomer Tayar default: 29519c8517c4STomer Tayar DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 29529c8517c4STomer Tayar p_in_params->cmd); 29539c8517c4STomer Tayar return -EINVAL; 29549c8517c4STomer Tayar } 29559c8517c4STomer Tayar 29569c8517c4STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 29579c8517c4STomer Tayar mb_params.cmd = p_in_params->cmd; 29589c8517c4STomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 29599c8517c4STomer Tayar mb_params.p_data_src = &mfw_resc_info; 29609c8517c4STomer Tayar mb_params.data_src_size = sizeof(mfw_resc_info); 29619c8517c4STomer Tayar mb_params.p_data_dst = mb_params.p_data_src; 29629c8517c4STomer Tayar mb_params.data_dst_size = mb_params.data_src_size; 29639c8517c4STomer Tayar 29649c8517c4STomer Tayar DP_VERBOSE(p_hwfn, 29659c8517c4STomer Tayar QED_MSG_SP, 29669c8517c4STomer Tayar "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 29679c8517c4STomer Tayar p_in_params->cmd, 29689c8517c4STomer Tayar p_in_params->res_id, 29699c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id), 29709c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 29719c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 29729c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 29739c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 29749c8517c4STomer Tayar p_in_params->resc_max_val); 29759c8517c4STomer Tayar 29762edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 29772edbff8dSTomer Tayar if (rc) 29782edbff8dSTomer Tayar return rc; 29792edbff8dSTomer Tayar 29809c8517c4STomer Tayar p_out_params->mcp_resp = mb_params.mcp_resp; 29819c8517c4STomer Tayar p_out_params->mcp_param = mb_params.mcp_param; 29829c8517c4STomer Tayar p_out_params->resc_num = mfw_resc_info.size; 29839c8517c4STomer Tayar p_out_params->resc_start = mfw_resc_info.offset; 29849c8517c4STomer Tayar p_out_params->vf_resc_num = mfw_resc_info.vf_size; 29859c8517c4STomer Tayar p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 29869c8517c4STomer Tayar p_out_params->flags = mfw_resc_info.flags; 29872edbff8dSTomer Tayar 29882edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 29892edbff8dSTomer Tayar QED_MSG_SP, 29909c8517c4STomer Tayar "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 29919c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 29929c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 29939c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 29949c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 29959c8517c4STomer Tayar p_out_params->resc_num, 29969c8517c4STomer Tayar p_out_params->resc_start, 29979c8517c4STomer Tayar p_out_params->vf_resc_num, 29989c8517c4STomer Tayar p_out_params->vf_resc_start, p_out_params->flags); 29999c8517c4STomer Tayar 30009c8517c4STomer Tayar return 0; 30019c8517c4STomer Tayar } 30029c8517c4STomer Tayar 30039c8517c4STomer Tayar int 30049c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 30059c8517c4STomer Tayar struct qed_ptt *p_ptt, 30069c8517c4STomer Tayar enum qed_resources res_id, 30079c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 30089c8517c4STomer Tayar { 30099c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 30109c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 30119c8517c4STomer Tayar int rc; 30129c8517c4STomer Tayar 30139c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 30149c8517c4STomer Tayar in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 30159c8517c4STomer Tayar in_params.res_id = res_id; 30169c8517c4STomer Tayar in_params.resc_max_val = resc_max_val; 30179c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 30189c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 30199c8517c4STomer Tayar &out_params); 30209c8517c4STomer Tayar if (rc) 30219c8517c4STomer Tayar return rc; 30229c8517c4STomer Tayar 30239c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 30249c8517c4STomer Tayar 30259c8517c4STomer Tayar return 0; 30269c8517c4STomer Tayar } 30279c8517c4STomer Tayar 30289c8517c4STomer Tayar int 30299c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 30309c8517c4STomer Tayar struct qed_ptt *p_ptt, 30319c8517c4STomer Tayar enum qed_resources res_id, 30329c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 30339c8517c4STomer Tayar { 30349c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 30359c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 30369c8517c4STomer Tayar int rc; 30379c8517c4STomer Tayar 30389c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 30399c8517c4STomer Tayar in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 30409c8517c4STomer Tayar in_params.res_id = res_id; 30419c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 30429c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 30439c8517c4STomer Tayar &out_params); 30449c8517c4STomer Tayar if (rc) 30459c8517c4STomer Tayar return rc; 30469c8517c4STomer Tayar 30479c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 30489c8517c4STomer Tayar 30499c8517c4STomer Tayar if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 30509c8517c4STomer Tayar *p_resc_num = out_params.resc_num; 30519c8517c4STomer Tayar *p_resc_start = out_params.resc_start; 30529c8517c4STomer Tayar } 30532edbff8dSTomer Tayar 30542edbff8dSTomer Tayar return 0; 30552edbff8dSTomer Tayar } 305618a69e36SMintz, Yuval 305718a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 305818a69e36SMintz, Yuval { 305918a69e36SMintz, Yuval u32 mcp_resp, mcp_param; 306018a69e36SMintz, Yuval 306118a69e36SMintz, Yuval return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 306218a69e36SMintz, Yuval &mcp_resp, &mcp_param); 306318a69e36SMintz, Yuval } 306495691c9cSTomer Tayar 306595691c9cSTomer Tayar static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 306695691c9cSTomer Tayar struct qed_ptt *p_ptt, 306795691c9cSTomer Tayar u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 306895691c9cSTomer Tayar { 306995691c9cSTomer Tayar int rc; 307095691c9cSTomer Tayar 307195691c9cSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 307295691c9cSTomer Tayar p_mcp_resp, p_mcp_param); 307395691c9cSTomer Tayar if (rc) 307495691c9cSTomer Tayar return rc; 307595691c9cSTomer Tayar 307695691c9cSTomer Tayar if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 307795691c9cSTomer Tayar DP_INFO(p_hwfn, 307895691c9cSTomer Tayar "The resource command is unsupported by the MFW\n"); 307995691c9cSTomer Tayar return -EINVAL; 308095691c9cSTomer Tayar } 308195691c9cSTomer Tayar 308295691c9cSTomer Tayar if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 308395691c9cSTomer Tayar u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 308495691c9cSTomer Tayar 308595691c9cSTomer Tayar DP_NOTICE(p_hwfn, 308695691c9cSTomer Tayar "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 308795691c9cSTomer Tayar param, opcode); 308895691c9cSTomer Tayar return -EINVAL; 308995691c9cSTomer Tayar } 309095691c9cSTomer Tayar 309195691c9cSTomer Tayar return rc; 309295691c9cSTomer Tayar } 309395691c9cSTomer Tayar 3094bf774d14SYueHaibing static int 309595691c9cSTomer Tayar __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 309695691c9cSTomer Tayar struct qed_ptt *p_ptt, 309795691c9cSTomer Tayar struct qed_resc_lock_params *p_params) 309895691c9cSTomer Tayar { 309995691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 310095691c9cSTomer Tayar u8 opcode; 310195691c9cSTomer Tayar int rc; 310295691c9cSTomer Tayar 310395691c9cSTomer Tayar switch (p_params->timeout) { 310495691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_DEFAULT: 310595691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ; 310695691c9cSTomer Tayar p_params->timeout = 0; 310795691c9cSTomer Tayar break; 310895691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_NONE: 310995691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_WO_AGING; 311095691c9cSTomer Tayar p_params->timeout = 0; 311195691c9cSTomer Tayar break; 311295691c9cSTomer Tayar default: 311395691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_W_AGING; 311495691c9cSTomer Tayar break; 311595691c9cSTomer Tayar } 311695691c9cSTomer Tayar 311795691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 311895691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 311995691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 312095691c9cSTomer Tayar 312195691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 312295691c9cSTomer Tayar QED_MSG_SP, 312395691c9cSTomer Tayar "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 312495691c9cSTomer Tayar param, p_params->timeout, opcode, p_params->resource); 312595691c9cSTomer Tayar 312695691c9cSTomer Tayar /* Attempt to acquire the resource */ 312795691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 312895691c9cSTomer Tayar if (rc) 312995691c9cSTomer Tayar return rc; 313095691c9cSTomer Tayar 313195691c9cSTomer Tayar /* Analyze the response */ 313295691c9cSTomer Tayar p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 313395691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 313495691c9cSTomer Tayar 313595691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 313695691c9cSTomer Tayar QED_MSG_SP, 313795691c9cSTomer Tayar "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 313895691c9cSTomer Tayar mcp_param, opcode, p_params->owner); 313995691c9cSTomer Tayar 314095691c9cSTomer Tayar switch (opcode) { 314195691c9cSTomer Tayar case RESOURCE_OPCODE_GNT: 314295691c9cSTomer Tayar p_params->b_granted = true; 314395691c9cSTomer Tayar break; 314495691c9cSTomer Tayar case RESOURCE_OPCODE_BUSY: 314595691c9cSTomer Tayar p_params->b_granted = false; 314695691c9cSTomer Tayar break; 314795691c9cSTomer Tayar default: 314895691c9cSTomer Tayar DP_NOTICE(p_hwfn, 314995691c9cSTomer Tayar "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 315095691c9cSTomer Tayar mcp_param, opcode); 315195691c9cSTomer Tayar return -EINVAL; 315295691c9cSTomer Tayar } 315395691c9cSTomer Tayar 315495691c9cSTomer Tayar return 0; 315595691c9cSTomer Tayar } 315695691c9cSTomer Tayar 315795691c9cSTomer Tayar int 315895691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 315995691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 316095691c9cSTomer Tayar { 316195691c9cSTomer Tayar u32 retry_cnt = 0; 316295691c9cSTomer Tayar int rc; 316395691c9cSTomer Tayar 316495691c9cSTomer Tayar do { 316595691c9cSTomer Tayar /* No need for an interval before the first iteration */ 316695691c9cSTomer Tayar if (retry_cnt) { 316795691c9cSTomer Tayar if (p_params->sleep_b4_retry) { 316895691c9cSTomer Tayar u16 retry_interval_in_ms = 316995691c9cSTomer Tayar DIV_ROUND_UP(p_params->retry_interval, 317095691c9cSTomer Tayar 1000); 317195691c9cSTomer Tayar 317295691c9cSTomer Tayar msleep(retry_interval_in_ms); 317395691c9cSTomer Tayar } else { 317495691c9cSTomer Tayar udelay(p_params->retry_interval); 317595691c9cSTomer Tayar } 317695691c9cSTomer Tayar } 317795691c9cSTomer Tayar 317895691c9cSTomer Tayar rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 317995691c9cSTomer Tayar if (rc) 318095691c9cSTomer Tayar return rc; 318195691c9cSTomer Tayar 318295691c9cSTomer Tayar if (p_params->b_granted) 318395691c9cSTomer Tayar break; 318495691c9cSTomer Tayar } while (retry_cnt++ < p_params->retry_num); 318595691c9cSTomer Tayar 318695691c9cSTomer Tayar return 0; 318795691c9cSTomer Tayar } 318895691c9cSTomer Tayar 318995691c9cSTomer Tayar int 319095691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 319195691c9cSTomer Tayar struct qed_ptt *p_ptt, 319295691c9cSTomer Tayar struct qed_resc_unlock_params *p_params) 319395691c9cSTomer Tayar { 319495691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 319595691c9cSTomer Tayar u8 opcode; 319695691c9cSTomer Tayar int rc; 319795691c9cSTomer Tayar 319895691c9cSTomer Tayar opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 319995691c9cSTomer Tayar : RESOURCE_OPCODE_RELEASE; 320095691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 320195691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 320295691c9cSTomer Tayar 320395691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 320495691c9cSTomer Tayar "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 320595691c9cSTomer Tayar param, opcode, p_params->resource); 320695691c9cSTomer Tayar 320795691c9cSTomer Tayar /* Attempt to release the resource */ 320895691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 320995691c9cSTomer Tayar if (rc) 321095691c9cSTomer Tayar return rc; 321195691c9cSTomer Tayar 321295691c9cSTomer Tayar /* Analyze the response */ 321395691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 321495691c9cSTomer Tayar 321595691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 321695691c9cSTomer Tayar "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 321795691c9cSTomer Tayar mcp_param, opcode); 321895691c9cSTomer Tayar 321995691c9cSTomer Tayar switch (opcode) { 322095691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED_PREVIOUS: 322195691c9cSTomer Tayar DP_INFO(p_hwfn, 322295691c9cSTomer Tayar "Resource unlock request for an already released resource [%d]\n", 322395691c9cSTomer Tayar p_params->resource); 322495691c9cSTomer Tayar /* Fallthrough */ 322595691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED: 322695691c9cSTomer Tayar p_params->b_released = true; 322795691c9cSTomer Tayar break; 322895691c9cSTomer Tayar case RESOURCE_OPCODE_WRONG_OWNER: 322995691c9cSTomer Tayar p_params->b_released = false; 323095691c9cSTomer Tayar break; 323195691c9cSTomer Tayar default: 323295691c9cSTomer Tayar DP_NOTICE(p_hwfn, 323395691c9cSTomer Tayar "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 323495691c9cSTomer Tayar mcp_param, opcode); 323595691c9cSTomer Tayar return -EINVAL; 323695691c9cSTomer Tayar } 323795691c9cSTomer Tayar 323895691c9cSTomer Tayar return 0; 323995691c9cSTomer Tayar } 3240f470f22cSsudarsana.kalluru@cavium.com 3241f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3242f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 3243f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 3244f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent) 3245f470f22cSsudarsana.kalluru@cavium.com { 3246f470f22cSsudarsana.kalluru@cavium.com if (p_lock) { 3247f470f22cSsudarsana.kalluru@cavium.com memset(p_lock, 0, sizeof(*p_lock)); 3248f470f22cSsudarsana.kalluru@cavium.com 3249f470f22cSsudarsana.kalluru@cavium.com /* Permanent resources don't require aging, and there's no 3250f470f22cSsudarsana.kalluru@cavium.com * point in trying to acquire them more than once since it's 3251f470f22cSsudarsana.kalluru@cavium.com * unexpected another entity would release them. 3252f470f22cSsudarsana.kalluru@cavium.com */ 3253f470f22cSsudarsana.kalluru@cavium.com if (b_is_permanent) { 3254f470f22cSsudarsana.kalluru@cavium.com p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3255f470f22cSsudarsana.kalluru@cavium.com } else { 3256f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3257f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_interval = 3258f470f22cSsudarsana.kalluru@cavium.com QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3259f470f22cSsudarsana.kalluru@cavium.com p_lock->sleep_b4_retry = true; 3260f470f22cSsudarsana.kalluru@cavium.com } 3261f470f22cSsudarsana.kalluru@cavium.com 3262f470f22cSsudarsana.kalluru@cavium.com p_lock->resource = resource; 3263f470f22cSsudarsana.kalluru@cavium.com } 3264f470f22cSsudarsana.kalluru@cavium.com 3265f470f22cSsudarsana.kalluru@cavium.com if (p_unlock) { 3266f470f22cSsudarsana.kalluru@cavium.com memset(p_unlock, 0, sizeof(*p_unlock)); 3267f470f22cSsudarsana.kalluru@cavium.com p_unlock->resource = resource; 3268f470f22cSsudarsana.kalluru@cavium.com } 3269f470f22cSsudarsana.kalluru@cavium.com } 3270645874e5SSudarsana Reddy Kalluru 3271645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3272645874e5SSudarsana Reddy Kalluru { 3273645874e5SSudarsana Reddy Kalluru u32 mcp_resp; 3274645874e5SSudarsana Reddy Kalluru int rc; 3275645874e5SSudarsana Reddy Kalluru 3276645874e5SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3277645874e5SSudarsana Reddy Kalluru 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3278645874e5SSudarsana Reddy Kalluru if (!rc) 3279645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3280645874e5SSudarsana Reddy Kalluru "MFW supported features: %08x\n", 3281645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->capabilities); 3282645874e5SSudarsana Reddy Kalluru 3283645874e5SSudarsana Reddy Kalluru return rc; 3284645874e5SSudarsana Reddy Kalluru } 3285645874e5SSudarsana Reddy Kalluru 3286645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3287645874e5SSudarsana Reddy Kalluru { 3288645874e5SSudarsana Reddy Kalluru u32 mcp_resp, mcp_param, features; 3289645874e5SSudarsana Reddy Kalluru 3290645874e5SSudarsana Reddy Kalluru features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE; 3291645874e5SSudarsana Reddy Kalluru 3292645874e5SSudarsana Reddy Kalluru return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3293645874e5SSudarsana Reddy Kalluru features, &mcp_resp, &mcp_param); 3294645874e5SSudarsana Reddy Kalluru } 3295