11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5fe56b9e6SYuval Mintz */ 6fe56b9e6SYuval Mintz 7fe56b9e6SYuval Mintz #include <linux/types.h> 8fe56b9e6SYuval Mintz #include <asm/byteorder.h> 9fe56b9e6SYuval Mintz #include <linux/delay.h> 10fe56b9e6SYuval Mintz #include <linux/errno.h> 11fe56b9e6SYuval Mintz #include <linux/kernel.h> 12fe56b9e6SYuval Mintz #include <linux/slab.h> 135529bad9STomer Tayar #include <linux/spinlock.h> 14fe56b9e6SYuval Mintz #include <linux/string.h> 150fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 16fe56b9e6SYuval Mintz #include "qed.h" 17cac6f691SSudarsana Reddy Kalluru #include "qed_cxt.h" 1839651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 19fe56b9e6SYuval Mintz #include "qed_hsi.h" 20fe56b9e6SYuval Mintz #include "qed_hw.h" 21fe56b9e6SYuval Mintz #include "qed_mcp.h" 22fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 231408cc1fSYuval Mintz #include "qed_sriov.h" 241408cc1fSYuval Mintz 250500a70dSMichal Kalderon #define GRCBASE_MCP 0xe00000 260500a70dSMichal Kalderon 27eaa50fc5STomer Tayar #define QED_MCP_RESP_ITER_US 10 28fe56b9e6SYuval Mintz 29fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 30fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 31fe56b9e6SYuval Mintz 32fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 33fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 34fe56b9e6SYuval Mintz _val) 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 37fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 38fe56b9e6SYuval Mintz 39fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 40fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 41fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 42fe56b9e6SYuval Mintz 43fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 44fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 45fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 46fe56b9e6SYuval Mintz 47fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 48fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 49fe56b9e6SYuval Mintz 50fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 51fe56b9e6SYuval Mintz 52fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 53fe56b9e6SYuval Mintz { 54fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 55fe56b9e6SYuval Mintz return false; 56fe56b9e6SYuval Mintz return true; 57fe56b9e6SYuval Mintz } 58fe56b9e6SYuval Mintz 591a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 60fe56b9e6SYuval Mintz { 61fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 62fe56b9e6SYuval Mintz PUBLIC_PORT); 63fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 64fe56b9e6SYuval Mintz 65fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 66fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 67fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 68fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 69fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 70fe56b9e6SYuval Mintz } 71fe56b9e6SYuval Mintz 721a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 73fe56b9e6SYuval Mintz { 74fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 75fe56b9e6SYuval Mintz u32 tmp, i; 76fe56b9e6SYuval Mintz 77fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 78fe56b9e6SYuval Mintz return; 79fe56b9e6SYuval Mintz 80fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 81fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 82fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 83fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 84fe56b9e6SYuval Mintz 85fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 86fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 87fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 88fe56b9e6SYuval Mintz } 89fe56b9e6SYuval Mintz } 90fe56b9e6SYuval Mintz 914ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 924ed1eea8STomer Tayar struct list_head list; 934ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 944ed1eea8STomer Tayar u16 expected_seq_num; 954ed1eea8STomer Tayar bool b_is_completed; 964ed1eea8STomer Tayar }; 974ed1eea8STomer Tayar 984ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 994ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1004ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1014ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1024ed1eea8STomer Tayar u16 expected_seq_num) 1034ed1eea8STomer Tayar { 1044ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1054ed1eea8STomer Tayar 1064ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1074ed1eea8STomer Tayar if (!p_cmd_elem) 1084ed1eea8STomer Tayar goto out; 1094ed1eea8STomer Tayar 1104ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1114ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1124ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1134ed1eea8STomer Tayar out: 1144ed1eea8STomer Tayar return p_cmd_elem; 1154ed1eea8STomer Tayar } 1164ed1eea8STomer Tayar 1174ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1184ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1194ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1204ed1eea8STomer Tayar { 1214ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1224ed1eea8STomer Tayar kfree(p_cmd_elem); 1234ed1eea8STomer Tayar } 1244ed1eea8STomer Tayar 1254ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1264ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1274ed1eea8STomer Tayar u16 seq_num) 1284ed1eea8STomer Tayar { 1294ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1304ed1eea8STomer Tayar 1314ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1324ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1334ed1eea8STomer Tayar return p_cmd_elem; 1344ed1eea8STomer Tayar } 1354ed1eea8STomer Tayar 1364ed1eea8STomer Tayar return NULL; 1374ed1eea8STomer Tayar } 1384ed1eea8STomer Tayar 139fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 140fe56b9e6SYuval Mintz { 141fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1424ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1434ed1eea8STomer Tayar 144fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 145fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1464ed1eea8STomer Tayar 1474ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1484ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1494ed1eea8STomer Tayar p_tmp, 1504ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1514ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 152fe56b9e6SYuval Mintz } 1534ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1544ed1eea8STomer Tayar } 1554ed1eea8STomer Tayar 156fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 1573587cb87STomer Tayar p_hwfn->mcp_info = NULL; 158fe56b9e6SYuval Mintz 159fe56b9e6SYuval Mintz return 0; 160fe56b9e6SYuval Mintz } 161fe56b9e6SYuval Mintz 162f00d25f3STomer Tayar /* Maximum of 1 sec to wait for the SHMEM ready indication */ 163f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_MAX_RETRIES 20 164f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_ITER_MS 50 165f00d25f3STomer Tayar 1661a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 167fe56b9e6SYuval Mintz { 168fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 169f00d25f3STomer Tayar u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES; 170f00d25f3STomer Tayar u8 msec = QED_MCP_SHMEM_RDY_ITER_MS; 171fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 172fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 173fe56b9e6SYuval Mintz 174fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 175f00d25f3STomer Tayar if (!p_info->public_base) { 176f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 177f00d25f3STomer Tayar "The address of the MCP scratch-pad is not configured\n"); 178f00d25f3STomer Tayar return -EINVAL; 179f00d25f3STomer Tayar } 180fe56b9e6SYuval Mintz 181fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 182fe56b9e6SYuval Mintz 183f00d25f3STomer Tayar /* Get the MFW MB address and number of supported messages */ 184f00d25f3STomer Tayar mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 185f00d25f3STomer Tayar SECTION_OFFSIZE_ADDR(p_info->public_base, 186f00d25f3STomer Tayar PUBLIC_MFW_MB)); 187f00d25f3STomer Tayar p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 188f00d25f3STomer Tayar p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, 189f00d25f3STomer Tayar p_info->mfw_mb_addr + 190f00d25f3STomer Tayar offsetof(struct public_mfw_mb, 191f00d25f3STomer Tayar sup_msgs)); 192f00d25f3STomer Tayar 193f00d25f3STomer Tayar /* The driver can notify that there was an MCP reset, and might read the 194f00d25f3STomer Tayar * SHMEM values before the MFW has completed initializing them. 195f00d25f3STomer Tayar * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a 196f00d25f3STomer Tayar * data ready indication. 197f00d25f3STomer Tayar */ 198f00d25f3STomer Tayar while (!p_info->mfw_mb_length && --cnt) { 199f00d25f3STomer Tayar msleep(msec); 200f00d25f3STomer Tayar p_info->mfw_mb_length = 201f00d25f3STomer Tayar (u16)qed_rd(p_hwfn, p_ptt, 202f00d25f3STomer Tayar p_info->mfw_mb_addr + 203f00d25f3STomer Tayar offsetof(struct public_mfw_mb, sup_msgs)); 204f00d25f3STomer Tayar } 205f00d25f3STomer Tayar 206f00d25f3STomer Tayar if (!cnt) { 207f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 208f00d25f3STomer Tayar "Failed to get the SHMEM ready notification after %d msec\n", 209f00d25f3STomer Tayar QED_MCP_SHMEM_RDY_MAX_RETRIES * msec); 210f00d25f3STomer Tayar return -EBUSY; 211f00d25f3STomer Tayar } 212f00d25f3STomer Tayar 213fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 214fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 215fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 216fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 217fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 218fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 219fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 220fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 221fe56b9e6SYuval Mintz 222fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 223fe56b9e6SYuval Mintz * the first command 224fe56b9e6SYuval Mintz */ 225fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 226fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 227fe56b9e6SYuval Mintz 228fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 229fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 230fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 231fe56b9e6SYuval Mintz 2324ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 233fe56b9e6SYuval Mintz 234fe56b9e6SYuval Mintz return 0; 235fe56b9e6SYuval Mintz } 236fe56b9e6SYuval Mintz 2371a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 238fe56b9e6SYuval Mintz { 239fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 240fe56b9e6SYuval Mintz u32 size; 241fe56b9e6SYuval Mintz 242fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 24360fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 244fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 245fe56b9e6SYuval Mintz goto err; 246fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 247fe56b9e6SYuval Mintz 2484ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2494ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2504ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2514ed1eea8STomer Tayar 2524ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2534ed1eea8STomer Tayar 254fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 255fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 256fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 257fe56b9e6SYuval Mintz * the MCP is not initialized 258fe56b9e6SYuval Mintz */ 259fe56b9e6SYuval Mintz return 0; 260fe56b9e6SYuval Mintz } 261fe56b9e6SYuval Mintz 262fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 26360fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 26483aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 265eb2a6b80SChristophe Jaillet if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 266fe56b9e6SYuval Mintz goto err; 267fe56b9e6SYuval Mintz 268fe56b9e6SYuval Mintz return 0; 269fe56b9e6SYuval Mintz 270fe56b9e6SYuval Mintz err: 271fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 272fe56b9e6SYuval Mintz return -ENOMEM; 273fe56b9e6SYuval Mintz } 274fe56b9e6SYuval Mintz 2754ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 2764ed1eea8STomer Tayar struct qed_ptt *p_ptt) 2775529bad9STomer Tayar { 2784ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 2795529bad9STomer Tayar 2804ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 2814ed1eea8STomer Tayar * time and now. 2825529bad9STomer Tayar */ 2834ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 2844ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 2854ed1eea8STomer Tayar QED_MSG_SP, 2864ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 2874ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 2885529bad9STomer Tayar 2894ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 2904ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2915529bad9STomer Tayar } 2925529bad9STomer Tayar } 2935529bad9STomer Tayar 2941a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 295fe56b9e6SYuval Mintz { 296eaa50fc5STomer Tayar u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0; 297fe56b9e6SYuval Mintz int rc = 0; 298fe56b9e6SYuval Mintz 299b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 300b310974eSTomer Tayar DP_NOTICE(p_hwfn, 301b310974eSTomer Tayar "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n"); 302b310974eSTomer Tayar return -EBUSY; 303b310974eSTomer Tayar } 304b310974eSTomer Tayar 3054ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 3064ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 3074ed1eea8STomer Tayar 3084ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3095529bad9STomer Tayar 310fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 3114ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 3124ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 3134ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 314fe56b9e6SYuval Mintz 315fe56b9e6SYuval Mintz do { 316fe56b9e6SYuval Mintz /* Wait for MFW response */ 317fe56b9e6SYuval Mintz udelay(delay); 318fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 319fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 320fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 321fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 322fe56b9e6SYuval Mintz 323fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 324fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 325fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 326fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 327fe56b9e6SYuval Mintz } else { 328fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 329fe56b9e6SYuval Mintz rc = -EAGAIN; 330fe56b9e6SYuval Mintz } 331fe56b9e6SYuval Mintz 3324ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3335529bad9STomer Tayar 334fe56b9e6SYuval Mintz return rc; 335fe56b9e6SYuval Mintz } 336fe56b9e6SYuval Mintz 3374ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3384ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 339fe56b9e6SYuval Mintz { 3404ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3414ed1eea8STomer Tayar 3424ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3434ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3444ed1eea8STomer Tayar */ 3454ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3464ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3474ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3484ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3494ed1eea8STomer Tayar } 3504ed1eea8STomer Tayar 3514ed1eea8STomer Tayar return false; 3524ed1eea8STomer Tayar } 3534ed1eea8STomer Tayar 3544ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3554ed1eea8STomer Tayar static int 3564ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3574ed1eea8STomer Tayar { 3584ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3594ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3604ed1eea8STomer Tayar u32 mcp_resp; 3614ed1eea8STomer Tayar u16 seq_num; 3624ed1eea8STomer Tayar 3634ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3644ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3654ed1eea8STomer Tayar 3664ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3674ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3684ed1eea8STomer Tayar return -EAGAIN; 3694ed1eea8STomer Tayar 3704ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3714ed1eea8STomer Tayar if (!p_cmd_elem) { 3724ed1eea8STomer Tayar DP_ERR(p_hwfn, 3734ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 3744ed1eea8STomer Tayar seq_num); 3754ed1eea8STomer Tayar return -EINVAL; 3764ed1eea8STomer Tayar } 3774ed1eea8STomer Tayar 3784ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 3794ed1eea8STomer Tayar 3804ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 3814ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 3824ed1eea8STomer Tayar 3834ed1eea8STomer Tayar /* Get the MFW param */ 3844ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 3854ed1eea8STomer Tayar 3864ed1eea8STomer Tayar /* Get the union data */ 3872f67af8cSTomer Tayar if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 3884ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3894ed1eea8STomer Tayar offsetof(struct public_drv_mb, 3904ed1eea8STomer Tayar union_data); 3914ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 3922f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 3934ed1eea8STomer Tayar } 3944ed1eea8STomer Tayar 3954ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 3964ed1eea8STomer Tayar 3974ed1eea8STomer Tayar return 0; 3984ed1eea8STomer Tayar } 3994ed1eea8STomer Tayar 4004ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 4014ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4024ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4034ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4044ed1eea8STomer Tayar u16 seq_num) 4054ed1eea8STomer Tayar { 4064ed1eea8STomer Tayar union drv_union_data union_data; 4074ed1eea8STomer Tayar u32 union_data_addr; 4084ed1eea8STomer Tayar 4094ed1eea8STomer Tayar /* Set the union data */ 4104ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4114ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 4124ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 4132f67af8cSTomer Tayar if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 4144ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 4152f67af8cSTomer Tayar p_mb_params->data_src_size); 4164ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4174ed1eea8STomer Tayar sizeof(union_data)); 4184ed1eea8STomer Tayar 4194ed1eea8STomer Tayar /* Set the drv param */ 4204ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4214ed1eea8STomer Tayar 4224ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4234ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4244ed1eea8STomer Tayar 4254ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4264ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4274ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4284ed1eea8STomer Tayar } 4294ed1eea8STomer Tayar 430b310974eSTomer Tayar static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd) 431b310974eSTomer Tayar { 432b310974eSTomer Tayar p_hwfn->mcp_info->b_block_cmd = block_cmd; 433b310974eSTomer Tayar 434b310974eSTomer Tayar DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n", 435b310974eSTomer Tayar block_cmd ? "Block" : "Unblock"); 436b310974eSTomer Tayar } 437b310974eSTomer Tayar 438b310974eSTomer Tayar static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn, 439b310974eSTomer Tayar struct qed_ptt *p_ptt) 440b310974eSTomer Tayar { 441b310974eSTomer Tayar u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2; 442b310974eSTomer Tayar u32 delay = QED_MCP_RESP_ITER_US; 443b310974eSTomer Tayar 444b310974eSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 445b310974eSTomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 446b310974eSTomer Tayar cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 447b310974eSTomer Tayar udelay(delay); 448b310974eSTomer Tayar cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 449b310974eSTomer Tayar udelay(delay); 450b310974eSTomer Tayar cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 451b310974eSTomer Tayar 452b310974eSTomer Tayar DP_NOTICE(p_hwfn, 453b310974eSTomer Tayar "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n", 454b310974eSTomer Tayar cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2); 455b310974eSTomer Tayar } 456b310974eSTomer Tayar 4574ed1eea8STomer Tayar static int 4584ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4594ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4604ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 461eaa50fc5STomer Tayar u32 max_retries, u32 usecs) 4624ed1eea8STomer Tayar { 463eaa50fc5STomer Tayar u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000); 4644ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4654ed1eea8STomer Tayar u16 seq_num; 466fe56b9e6SYuval Mintz int rc = 0; 467fe56b9e6SYuval Mintz 4684ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 469fe56b9e6SYuval Mintz do { 4704ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4714ed1eea8STomer Tayar * pending command is completed during this iteration. 4724ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4734ed1eea8STomer Tayar */ 4744ed1eea8STomer Tayar 4754ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4764ed1eea8STomer Tayar 4774ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 4784ed1eea8STomer Tayar break; 4794ed1eea8STomer Tayar 4804ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 4814ed1eea8STomer Tayar if (!rc) 4824ed1eea8STomer Tayar break; 4834ed1eea8STomer Tayar else if (rc != -EAGAIN) 4844ed1eea8STomer Tayar goto err; 4854ed1eea8STomer Tayar 4864ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 487eaa50fc5STomer Tayar 488eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 489eaa50fc5STomer Tayar msleep(msecs); 490eaa50fc5STomer Tayar else 491eaa50fc5STomer Tayar udelay(usecs); 4924ed1eea8STomer Tayar } while (++cnt < max_retries); 493fe56b9e6SYuval Mintz 4944ed1eea8STomer Tayar if (cnt >= max_retries) { 4954ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 4964ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 4974ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 4984ed1eea8STomer Tayar return -EAGAIN; 499fe56b9e6SYuval Mintz } 5004ed1eea8STomer Tayar 5014ed1eea8STomer Tayar /* Send the mailbox command */ 5024ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 5034ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 5044ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 505c8004600SDan Carpenter if (!p_cmd_elem) { 506c8004600SDan Carpenter rc = -ENOMEM; 5074ed1eea8STomer Tayar goto err; 508c8004600SDan Carpenter } 5094ed1eea8STomer Tayar 5104ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 5114ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5124ed1eea8STomer Tayar 5134ed1eea8STomer Tayar /* Wait for the MFW response */ 5144ed1eea8STomer Tayar do { 5154ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 5164ed1eea8STomer Tayar * command is completed during this iteration. 5174ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 5184ed1eea8STomer Tayar */ 5194ed1eea8STomer Tayar 520eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 521eaa50fc5STomer Tayar msleep(msecs); 522eaa50fc5STomer Tayar else 523eaa50fc5STomer Tayar udelay(usecs); 524eaa50fc5STomer Tayar 5254ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5264ed1eea8STomer Tayar 5274ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 5284ed1eea8STomer Tayar break; 5294ed1eea8STomer Tayar 5304ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5314ed1eea8STomer Tayar if (!rc) 5324ed1eea8STomer Tayar break; 5334ed1eea8STomer Tayar else if (rc != -EAGAIN) 5344ed1eea8STomer Tayar goto err; 5354ed1eea8STomer Tayar 5364ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5374ed1eea8STomer Tayar } while (++cnt < max_retries); 5384ed1eea8STomer Tayar 5394ed1eea8STomer Tayar if (cnt >= max_retries) { 5404ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5414ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 5424ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 543b310974eSTomer Tayar qed_mcp_print_cpu_info(p_hwfn, p_ptt); 5444ed1eea8STomer Tayar 5454ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5464ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5474ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5484ed1eea8STomer Tayar 549b310974eSTomer Tayar if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK)) 550b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 551b310974eSTomer Tayar 5522ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, 5532ec276d5SIgor Russkikh QED_HW_ERR_MFW_RESP_FAIL, NULL); 5544ed1eea8STomer Tayar return -EAGAIN; 5554ed1eea8STomer Tayar } 5564ed1eea8STomer Tayar 5574ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5584ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5594ed1eea8STomer Tayar 5604ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5614ed1eea8STomer Tayar QED_MSG_SP, 5624ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5634ed1eea8STomer Tayar p_mb_params->mcp_resp, 5644ed1eea8STomer Tayar p_mb_params->mcp_param, 565eaa50fc5STomer Tayar (cnt * usecs) / 1000, (cnt * usecs) % 1000); 5664ed1eea8STomer Tayar 5674ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5684ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5694ed1eea8STomer Tayar 5704ed1eea8STomer Tayar return 0; 5714ed1eea8STomer Tayar 5724ed1eea8STomer Tayar err: 5734ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 574fe56b9e6SYuval Mintz return rc; 575fe56b9e6SYuval Mintz } 576fe56b9e6SYuval Mintz 5775529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 578fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 5795529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 580fe56b9e6SYuval Mintz { 5812f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 5824ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 583eaa50fc5STomer Tayar u32 usecs = QED_MCP_RESP_ITER_US; 584fe56b9e6SYuval Mintz 585fe56b9e6SYuval Mintz /* MCP not initialized */ 586fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 587fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 588fe56b9e6SYuval Mintz return -EBUSY; 589fe56b9e6SYuval Mintz } 590fe56b9e6SYuval Mintz 591b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 592b310974eSTomer Tayar DP_NOTICE(p_hwfn, 593b310974eSTomer Tayar "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n", 594b310974eSTomer Tayar p_mb_params->cmd, p_mb_params->param); 595b310974eSTomer Tayar return -EBUSY; 596b310974eSTomer Tayar } 597b310974eSTomer Tayar 5982f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 5992f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 6002f67af8cSTomer Tayar DP_ERR(p_hwfn, 6012f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 6022f67af8cSTomer Tayar p_mb_params->data_src_size, 6032f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 6042f67af8cSTomer Tayar return -EINVAL; 6052f67af8cSTomer Tayar } 6062f67af8cSTomer Tayar 607eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) { 608eaa50fc5STomer Tayar max_retries = DIV_ROUND_UP(max_retries, 1000); 609eaa50fc5STomer Tayar usecs *= 1000; 610eaa50fc5STomer Tayar } 611eaa50fc5STomer Tayar 6124ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 613eaa50fc5STomer Tayar usecs); 614fe56b9e6SYuval Mintz } 615fe56b9e6SYuval Mintz 6165529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 6175529bad9STomer Tayar struct qed_ptt *p_ptt, 6185529bad9STomer Tayar u32 cmd, 6195529bad9STomer Tayar u32 param, 6205529bad9STomer Tayar u32 *o_mcp_resp, 6215529bad9STomer Tayar u32 *o_mcp_param) 622fe56b9e6SYuval Mintz { 6235529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 6245529bad9STomer Tayar int rc; 625fe56b9e6SYuval Mintz 6265529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6275529bad9STomer Tayar mb_params.cmd = cmd; 6285529bad9STomer Tayar mb_params.param = param; 62914d39648SMintz, Yuval 6305529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6315529bad9STomer Tayar if (rc) 6325529bad9STomer Tayar return rc; 6335529bad9STomer Tayar 6345529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6355529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 6365529bad9STomer Tayar 6375529bad9STomer Tayar return 0; 638fe56b9e6SYuval Mintz } 639fe56b9e6SYuval Mintz 640bf774d14SYueHaibing static int 641bf774d14SYueHaibing qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 64262e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 64362e4d438SSudarsana Reddy Kalluru u32 cmd, 64462e4d438SSudarsana Reddy Kalluru u32 param, 64562e4d438SSudarsana Reddy Kalluru u32 *o_mcp_resp, 64662e4d438SSudarsana Reddy Kalluru u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 64762e4d438SSudarsana Reddy Kalluru { 64862e4d438SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 64962e4d438SSudarsana Reddy Kalluru int rc; 65062e4d438SSudarsana Reddy Kalluru 65162e4d438SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 65262e4d438SSudarsana Reddy Kalluru mb_params.cmd = cmd; 65362e4d438SSudarsana Reddy Kalluru mb_params.param = param; 65462e4d438SSudarsana Reddy Kalluru mb_params.p_data_src = i_buf; 65562e4d438SSudarsana Reddy Kalluru mb_params.data_src_size = (u8)i_txn_size; 65662e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 65762e4d438SSudarsana Reddy Kalluru if (rc) 65862e4d438SSudarsana Reddy Kalluru return rc; 65962e4d438SSudarsana Reddy Kalluru 66062e4d438SSudarsana Reddy Kalluru *o_mcp_resp = mb_params.mcp_resp; 66162e4d438SSudarsana Reddy Kalluru *o_mcp_param = mb_params.mcp_param; 66262e4d438SSudarsana Reddy Kalluru 6635e7ba042SDenis Bolotin /* nvm_info needs to be updated */ 6645e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = false; 6655e7ba042SDenis Bolotin 66662e4d438SSudarsana Reddy Kalluru return 0; 66762e4d438SSudarsana Reddy Kalluru } 66862e4d438SSudarsana Reddy Kalluru 6694102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 6704102426fSTomer Tayar struct qed_ptt *p_ptt, 6714102426fSTomer Tayar u32 cmd, 6724102426fSTomer Tayar u32 param, 6734102426fSTomer Tayar u32 *o_mcp_resp, 6744102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 6754102426fSTomer Tayar { 6764102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 6772f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 6784102426fSTomer Tayar int rc; 6794102426fSTomer Tayar 6804102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6814102426fSTomer Tayar mb_params.cmd = cmd; 6824102426fSTomer Tayar mb_params.param = param; 6832f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 6842f67af8cSTomer Tayar 6852f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 6862f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 6872f67af8cSTomer Tayar 6884102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6894102426fSTomer Tayar if (rc) 6904102426fSTomer Tayar return rc; 6914102426fSTomer Tayar 6924102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6934102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 6944102426fSTomer Tayar 6954102426fSTomer Tayar *o_txn_size = *o_mcp_param; 6962f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 6974102426fSTomer Tayar 6984102426fSTomer Tayar return 0; 6994102426fSTomer Tayar } 7004102426fSTomer Tayar 7015d24bcf1STomer Tayar static bool 7025d24bcf1STomer Tayar qed_mcp_can_force_load(u8 drv_role, 7035d24bcf1STomer Tayar u8 exist_drv_role, 7045d24bcf1STomer Tayar enum qed_override_force_load override_force_load) 705fe56b9e6SYuval Mintz { 7065d24bcf1STomer Tayar bool can_force_load = false; 7075d24bcf1STomer Tayar 7085d24bcf1STomer Tayar switch (override_force_load) { 7095d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 7105d24bcf1STomer Tayar can_force_load = true; 7115d24bcf1STomer Tayar break; 7125d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_NEVER: 7135d24bcf1STomer Tayar can_force_load = false; 7145d24bcf1STomer Tayar break; 7155d24bcf1STomer Tayar default: 7165d24bcf1STomer Tayar can_force_load = (drv_role == DRV_ROLE_OS && 7175d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_PREBOOT) || 7185d24bcf1STomer Tayar (drv_role == DRV_ROLE_KDUMP && 7195d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_OS); 7205d24bcf1STomer Tayar break; 7215d24bcf1STomer Tayar } 7225d24bcf1STomer Tayar 7235d24bcf1STomer Tayar return can_force_load; 7245d24bcf1STomer Tayar } 7255d24bcf1STomer Tayar 7265d24bcf1STomer Tayar static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 7275d24bcf1STomer Tayar struct qed_ptt *p_ptt) 7285d24bcf1STomer Tayar { 7295d24bcf1STomer Tayar u32 resp = 0, param = 0; 730fe56b9e6SYuval Mintz int rc; 731fe56b9e6SYuval Mintz 7325d24bcf1STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 7335d24bcf1STomer Tayar &resp, ¶m); 7345d24bcf1STomer Tayar if (rc) 7355d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 7365d24bcf1STomer Tayar "Failed to send cancel load request, rc = %d\n", rc); 737fe56b9e6SYuval Mintz 738fe56b9e6SYuval Mintz return rc; 739fe56b9e6SYuval Mintz } 740fe56b9e6SYuval Mintz 7415d24bcf1STomer Tayar #define CONFIG_QEDE_BITMAP_IDX BIT(0) 7425d24bcf1STomer Tayar #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 7435d24bcf1STomer Tayar #define CONFIG_QEDR_BITMAP_IDX BIT(2) 7445d24bcf1STomer Tayar #define CONFIG_QEDF_BITMAP_IDX BIT(4) 7455d24bcf1STomer Tayar #define CONFIG_QEDI_BITMAP_IDX BIT(5) 7465d24bcf1STomer Tayar #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 7475529bad9STomer Tayar 7485d24bcf1STomer Tayar static u32 qed_get_config_bitmap(void) 7495d24bcf1STomer Tayar { 7505d24bcf1STomer Tayar u32 config_bitmap = 0x0; 7515d24bcf1STomer Tayar 7525d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QEDE)) 7535d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 7545d24bcf1STomer Tayar 7555d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_SRIOV)) 7565d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 7575d24bcf1STomer Tayar 7585d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_RDMA)) 7595d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 7605d24bcf1STomer Tayar 7615d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_FCOE)) 7625d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 7635d24bcf1STomer Tayar 7645d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_ISCSI)) 7655d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 7665d24bcf1STomer Tayar 7675d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_LL2)) 7685d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 7695d24bcf1STomer Tayar 7705d24bcf1STomer Tayar return config_bitmap; 7715d24bcf1STomer Tayar } 7725d24bcf1STomer Tayar 7735d24bcf1STomer Tayar struct qed_load_req_in_params { 7745d24bcf1STomer Tayar u8 hsi_ver; 7755d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 7765d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_1 1 7775d24bcf1STomer Tayar u32 drv_ver_0; 7785d24bcf1STomer Tayar u32 drv_ver_1; 7795d24bcf1STomer Tayar u32 fw_ver; 7805d24bcf1STomer Tayar u8 drv_role; 7815d24bcf1STomer Tayar u8 timeout_val; 7825d24bcf1STomer Tayar u8 force_cmd; 7835d24bcf1STomer Tayar bool avoid_eng_reset; 7845d24bcf1STomer Tayar }; 7855d24bcf1STomer Tayar 7865d24bcf1STomer Tayar struct qed_load_req_out_params { 7875d24bcf1STomer Tayar u32 load_code; 7885d24bcf1STomer Tayar u32 exist_drv_ver_0; 7895d24bcf1STomer Tayar u32 exist_drv_ver_1; 7905d24bcf1STomer Tayar u32 exist_fw_ver; 7915d24bcf1STomer Tayar u8 exist_drv_role; 7925d24bcf1STomer Tayar u8 mfw_hsi_ver; 7935d24bcf1STomer Tayar bool drv_exists; 7945d24bcf1STomer Tayar }; 7955d24bcf1STomer Tayar 7965d24bcf1STomer Tayar static int 7975d24bcf1STomer Tayar __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 7985d24bcf1STomer Tayar struct qed_ptt *p_ptt, 7995d24bcf1STomer Tayar struct qed_load_req_in_params *p_in_params, 8005d24bcf1STomer Tayar struct qed_load_req_out_params *p_out_params) 8015d24bcf1STomer Tayar { 8025d24bcf1STomer Tayar struct qed_mcp_mb_params mb_params; 8035d24bcf1STomer Tayar struct load_req_stc load_req; 8045d24bcf1STomer Tayar struct load_rsp_stc load_rsp; 8055d24bcf1STomer Tayar u32 hsi_ver; 8065d24bcf1STomer Tayar int rc; 8075d24bcf1STomer Tayar 8085d24bcf1STomer Tayar memset(&load_req, 0, sizeof(load_req)); 8095d24bcf1STomer Tayar load_req.drv_ver_0 = p_in_params->drv_ver_0; 8105d24bcf1STomer Tayar load_req.drv_ver_1 = p_in_params->drv_ver_1; 8115d24bcf1STomer Tayar load_req.fw_ver = p_in_params->fw_ver; 8125d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 8135d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 8145d24bcf1STomer Tayar p_in_params->timeout_val); 8155d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 8165d24bcf1STomer Tayar p_in_params->force_cmd); 8175d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 8185d24bcf1STomer Tayar p_in_params->avoid_eng_reset); 8195d24bcf1STomer Tayar 8205d24bcf1STomer Tayar hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 8215d24bcf1STomer Tayar DRV_ID_MCP_HSI_VER_CURRENT : 8225d24bcf1STomer Tayar (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 8235d24bcf1STomer Tayar 8245d24bcf1STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 8255d24bcf1STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 8265d24bcf1STomer Tayar mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 8275d24bcf1STomer Tayar mb_params.p_data_src = &load_req; 8285d24bcf1STomer Tayar mb_params.data_src_size = sizeof(load_req); 8295d24bcf1STomer Tayar mb_params.p_data_dst = &load_rsp; 8305d24bcf1STomer Tayar mb_params.data_dst_size = sizeof(load_rsp); 831b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 8325d24bcf1STomer Tayar 8335d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8345d24bcf1STomer Tayar "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 8355d24bcf1STomer Tayar mb_params.param, 8365d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 8375d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 8385d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 8395d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 8405d24bcf1STomer Tayar 8415d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 8425d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8435d24bcf1STomer Tayar "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 8445d24bcf1STomer Tayar load_req.drv_ver_0, 8455d24bcf1STomer Tayar load_req.drv_ver_1, 8465d24bcf1STomer Tayar load_req.fw_ver, 8475d24bcf1STomer Tayar load_req.misc0, 8485d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 8495d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, 8505d24bcf1STomer Tayar LOAD_REQ_LOCK_TO), 8515d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 8525d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 8535d24bcf1STomer Tayar } 8545d24bcf1STomer Tayar 8555d24bcf1STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 8565d24bcf1STomer Tayar if (rc) { 8575d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 8585d24bcf1STomer Tayar return rc; 8595d24bcf1STomer Tayar } 8605d24bcf1STomer Tayar 8615d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8625d24bcf1STomer Tayar "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 8635d24bcf1STomer Tayar p_out_params->load_code = mb_params.mcp_resp; 8645d24bcf1STomer Tayar 8655d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 8665d24bcf1STomer Tayar p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 8675d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, 8685d24bcf1STomer Tayar QED_MSG_SP, 8695d24bcf1STomer Tayar "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 8705d24bcf1STomer Tayar load_rsp.drv_ver_0, 8715d24bcf1STomer Tayar load_rsp.drv_ver_1, 8725d24bcf1STomer Tayar load_rsp.fw_ver, 8735d24bcf1STomer Tayar load_rsp.misc0, 8745d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 8755d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 8765d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 8775d24bcf1STomer Tayar 8785d24bcf1STomer Tayar p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 8795d24bcf1STomer Tayar p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 8805d24bcf1STomer Tayar p_out_params->exist_fw_ver = load_rsp.fw_ver; 8815d24bcf1STomer Tayar p_out_params->exist_drv_role = 8825d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 8835d24bcf1STomer Tayar p_out_params->mfw_hsi_ver = 8845d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 8855d24bcf1STomer Tayar p_out_params->drv_exists = 8865d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 8875d24bcf1STomer Tayar LOAD_RSP_FLAGS0_DRV_EXISTS; 8885d24bcf1STomer Tayar } 8895d24bcf1STomer Tayar 8905d24bcf1STomer Tayar return 0; 8915d24bcf1STomer Tayar } 8925d24bcf1STomer Tayar 8935d24bcf1STomer Tayar static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 8945d24bcf1STomer Tayar enum qed_drv_role drv_role, 8955d24bcf1STomer Tayar u8 *p_mfw_drv_role) 8965d24bcf1STomer Tayar { 8975d24bcf1STomer Tayar switch (drv_role) { 8985d24bcf1STomer Tayar case QED_DRV_ROLE_OS: 8995d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_OS; 9005d24bcf1STomer Tayar break; 9015d24bcf1STomer Tayar case QED_DRV_ROLE_KDUMP: 9025d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_KDUMP; 9035d24bcf1STomer Tayar break; 9045d24bcf1STomer Tayar default: 9055d24bcf1STomer Tayar DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 9065d24bcf1STomer Tayar return -EINVAL; 9075d24bcf1STomer Tayar } 9085d24bcf1STomer Tayar 9095d24bcf1STomer Tayar return 0; 9105d24bcf1STomer Tayar } 9115d24bcf1STomer Tayar 9125d24bcf1STomer Tayar enum qed_load_req_force { 9135d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, 9145d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_PF, 9155d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9165d24bcf1STomer Tayar }; 9175d24bcf1STomer Tayar 9185d24bcf1STomer Tayar static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 9195d24bcf1STomer Tayar 9205d24bcf1STomer Tayar enum qed_load_req_force force_cmd, 9215d24bcf1STomer Tayar u8 *p_mfw_force_cmd) 9225d24bcf1STomer Tayar { 9235d24bcf1STomer Tayar switch (force_cmd) { 9245d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_NONE: 9255d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 9265d24bcf1STomer Tayar break; 9275d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_PF: 9285d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 9295d24bcf1STomer Tayar break; 9305d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_ALL: 9315d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 9325d24bcf1STomer Tayar break; 9335d24bcf1STomer Tayar } 9345d24bcf1STomer Tayar } 9355d24bcf1STomer Tayar 9365d24bcf1STomer Tayar int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 9375d24bcf1STomer Tayar struct qed_ptt *p_ptt, 9385d24bcf1STomer Tayar struct qed_load_req_params *p_params) 9395d24bcf1STomer Tayar { 9405d24bcf1STomer Tayar struct qed_load_req_out_params out_params; 9415d24bcf1STomer Tayar struct qed_load_req_in_params in_params; 9425d24bcf1STomer Tayar u8 mfw_drv_role, mfw_force_cmd; 9435d24bcf1STomer Tayar int rc; 9445d24bcf1STomer Tayar 9455d24bcf1STomer Tayar memset(&in_params, 0, sizeof(in_params)); 9465d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 9475d24bcf1STomer Tayar in_params.drv_ver_0 = QED_VERSION; 9485d24bcf1STomer Tayar in_params.drv_ver_1 = qed_get_config_bitmap(); 9495d24bcf1STomer Tayar in_params.fw_ver = STORM_FW_VERSION; 9505d24bcf1STomer Tayar rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 9515d24bcf1STomer Tayar if (rc) 9525d24bcf1STomer Tayar return rc; 9535d24bcf1STomer Tayar 9545d24bcf1STomer Tayar in_params.drv_role = mfw_drv_role; 9555d24bcf1STomer Tayar in_params.timeout_val = p_params->timeout_val; 9565d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9575d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 9585d24bcf1STomer Tayar 9595d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9605d24bcf1STomer Tayar in_params.avoid_eng_reset = p_params->avoid_eng_reset; 9615d24bcf1STomer Tayar 9625d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9635d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9645d24bcf1STomer Tayar if (rc) 9655d24bcf1STomer Tayar return rc; 9665d24bcf1STomer Tayar 9675d24bcf1STomer Tayar /* First handle cases where another load request should/might be sent: 9685d24bcf1STomer Tayar * - MFW expects the old interface [HSI version = 1] 9695d24bcf1STomer Tayar * - MFW responds that a force load request is required 970fe56b9e6SYuval Mintz */ 9715d24bcf1STomer Tayar if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 9725d24bcf1STomer Tayar DP_INFO(p_hwfn, 9735d24bcf1STomer Tayar "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 9745d24bcf1STomer Tayar 9755d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 9765d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9775d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9785d24bcf1STomer Tayar if (rc) 9795d24bcf1STomer Tayar return rc; 9805d24bcf1STomer Tayar } else if (out_params.load_code == 9815d24bcf1STomer Tayar FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 9825d24bcf1STomer Tayar if (qed_mcp_can_force_load(in_params.drv_role, 9835d24bcf1STomer Tayar out_params.exist_drv_role, 9845d24bcf1STomer Tayar p_params->override_force_load)) { 9855d24bcf1STomer Tayar DP_INFO(p_hwfn, 9865d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 9875d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 9885d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 9895d24bcf1STomer Tayar out_params.exist_drv_role, 9905d24bcf1STomer Tayar out_params.exist_fw_ver, 9915d24bcf1STomer Tayar out_params.exist_drv_ver_0, 9925d24bcf1STomer Tayar out_params.exist_drv_ver_1); 9935d24bcf1STomer Tayar 9945d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9955d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9965d24bcf1STomer Tayar &mfw_force_cmd); 9975d24bcf1STomer Tayar 9985d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9995d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 10005d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 10015d24bcf1STomer Tayar &out_params); 10025d24bcf1STomer Tayar if (rc) 10035d24bcf1STomer Tayar return rc; 10045d24bcf1STomer Tayar } else { 10055d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10065d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 10075d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10085d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10095d24bcf1STomer Tayar out_params.exist_drv_role, 10105d24bcf1STomer Tayar out_params.exist_fw_ver, 10115d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10125d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10135d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10145d24bcf1STomer Tayar "Avoid sending a force load request to prevent disruption of active PFs\n"); 10155d24bcf1STomer Tayar 10165d24bcf1STomer Tayar qed_mcp_cancel_load_req(p_hwfn, p_ptt); 1017fe56b9e6SYuval Mintz return -EBUSY; 1018fe56b9e6SYuval Mintz } 10195d24bcf1STomer Tayar } 10205d24bcf1STomer Tayar 10215d24bcf1STomer Tayar /* Now handle the other types of responses. 10225d24bcf1STomer Tayar * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 10235d24bcf1STomer Tayar * expected here after the additional revised load requests were sent. 10245d24bcf1STomer Tayar */ 10255d24bcf1STomer Tayar switch (out_params.load_code) { 10265d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_ENGINE: 10275d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_PORT: 10285d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_FUNCTION: 10295d24bcf1STomer Tayar if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 10305d24bcf1STomer Tayar out_params.drv_exists) { 10315d24bcf1STomer Tayar /* The role and fw/driver version match, but the PF is 10325d24bcf1STomer Tayar * already loaded and has not been unloaded gracefully. 10335d24bcf1STomer Tayar */ 10345d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10355d24bcf1STomer Tayar "PF is already loaded\n"); 10365d24bcf1STomer Tayar return -EINVAL; 10375d24bcf1STomer Tayar } 10385d24bcf1STomer Tayar break; 10395d24bcf1STomer Tayar default: 10405d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10415d24bcf1STomer Tayar "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 10425d24bcf1STomer Tayar out_params.load_code); 10435d24bcf1STomer Tayar return -EBUSY; 10445d24bcf1STomer Tayar } 10455d24bcf1STomer Tayar 10465d24bcf1STomer Tayar p_params->load_code = out_params.load_code; 1047fe56b9e6SYuval Mintz 1048fe56b9e6SYuval Mintz return 0; 1049fe56b9e6SYuval Mintz } 1050fe56b9e6SYuval Mintz 1051666db486STomer Tayar int qed_mcp_load_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1052666db486STomer Tayar { 1053666db486STomer Tayar u32 resp = 0, param = 0; 1054666db486STomer Tayar int rc; 1055666db486STomer Tayar 1056666db486STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp, 1057666db486STomer Tayar ¶m); 1058666db486STomer Tayar if (rc) { 1059666db486STomer Tayar DP_NOTICE(p_hwfn, 1060666db486STomer Tayar "Failed to send a LOAD_DONE command, rc = %d\n", rc); 1061666db486STomer Tayar return rc; 1062666db486STomer Tayar } 1063666db486STomer Tayar 1064666db486STomer Tayar /* Check if there is a DID mismatch between nvm-cfg/efuse */ 1065666db486STomer Tayar if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR) 1066666db486STomer Tayar DP_NOTICE(p_hwfn, 1067666db486STomer Tayar "warning: device configuration is not supported on this board type. The device may not function as expected.\n"); 1068666db486STomer Tayar 1069666db486STomer Tayar return 0; 1070666db486STomer Tayar } 1071666db486STomer Tayar 10721226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10731226337aSTomer Tayar { 1074eaa50fc5STomer Tayar struct qed_mcp_mb_params mb_params; 1075eaa50fc5STomer Tayar u32 wol_param; 10761226337aSTomer Tayar 10771226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 10781226337aSTomer Tayar case QED_OV_WOL_DISABLED: 10791226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 10801226337aSTomer Tayar break; 10811226337aSTomer Tayar case QED_OV_WOL_ENABLED: 10821226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 10831226337aSTomer Tayar break; 10841226337aSTomer Tayar default: 10851226337aSTomer Tayar DP_NOTICE(p_hwfn, 10861226337aSTomer Tayar "Unknown WoL configuration %02x\n", 10871226337aSTomer Tayar p_hwfn->cdev->wol_config); 1088df561f66SGustavo A. R. Silva fallthrough; 10891226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 10901226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 10911226337aSTomer Tayar } 10921226337aSTomer Tayar 1093eaa50fc5STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 1094eaa50fc5STomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ; 1095eaa50fc5STomer Tayar mb_params.param = wol_param; 1096b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 1097eaa50fc5STomer Tayar 1098eaa50fc5STomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 10991226337aSTomer Tayar } 11001226337aSTomer Tayar 11011226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11021226337aSTomer Tayar { 11031226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 11041226337aSTomer Tayar struct mcp_mac wol_mac; 11051226337aSTomer Tayar 11061226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 11071226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 11081226337aSTomer Tayar 11091226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 11101226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 11111226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 11121226337aSTomer Tayar 11131226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 11141226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 11151226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 11161226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 11171226337aSTomer Tayar 11181226337aSTomer Tayar DP_VERBOSE(p_hwfn, 11191226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 11201226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 11211226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 11221226337aSTomer Tayar 11231226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 11241226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 11251226337aSTomer Tayar } 11261226337aSTomer Tayar 11271226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11281226337aSTomer Tayar } 11291226337aSTomer Tayar 11300b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 11310b55e27dSYuval Mintz struct qed_ptt *p_ptt) 11320b55e27dSYuval Mintz { 11330b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11340b55e27dSYuval Mintz PUBLIC_PATH); 11350b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 11360b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 11370b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 11380b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 11390b55e27dSYuval Mintz int i; 11400b55e27dSYuval Mintz 11410b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 11420b55e27dSYuval Mintz QED_MSG_SP, 11430b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 11440b55e27dSYuval Mintz mfw_path_offsize, path_addr); 11450b55e27dSYuval Mintz 11460b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 11470b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 11480b55e27dSYuval Mintz path_addr + 11490b55e27dSYuval Mintz offsetof(struct public_path, 11500b55e27dSYuval Mintz mcp_vf_disabled) + 11510b55e27dSYuval Mintz sizeof(u32) * i); 11520b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11530b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 11540b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 11550b55e27dSYuval Mintz } 11560b55e27dSYuval Mintz 11570b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 11580b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 11590b55e27dSYuval Mintz } 11600b55e27dSYuval Mintz 11610b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 11620b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 11630b55e27dSYuval Mintz { 11640b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11650b55e27dSYuval Mintz PUBLIC_FUNC); 11660b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 11670b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 11680b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 11690b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 11700b55e27dSYuval Mintz int rc; 11710b55e27dSYuval Mintz int i; 11720b55e27dSYuval Mintz 11730b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11740b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11750b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 11760b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 11770b55e27dSYuval Mintz 11780b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 11790b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 11802f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 11812f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 11820b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11830b55e27dSYuval Mintz if (rc) { 11840b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 11850b55e27dSYuval Mintz return -EBUSY; 11860b55e27dSYuval Mintz } 11870b55e27dSYuval Mintz 11880b55e27dSYuval Mintz /* Clear the ACK bits */ 11890b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11900b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 11910b55e27dSYuval Mintz func_addr + 11920b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 11930b55e27dSYuval Mintz i * sizeof(u32), 0); 11940b55e27dSYuval Mintz 11950b55e27dSYuval Mintz return rc; 11960b55e27dSYuval Mintz } 11970b55e27dSYuval Mintz 1198334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1199334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 1200334c03b5SZvi Nachmani { 1201334c03b5SZvi Nachmani u32 transceiver_state; 1202334c03b5SZvi Nachmani 1203334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 1204334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 1205334c03b5SZvi Nachmani offsetof(struct public_port, 1206334c03b5SZvi Nachmani transceiver_data)); 1207334c03b5SZvi Nachmani 1208334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 1209334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 1210334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1211334c03b5SZvi Nachmani transceiver_state, 1212334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 12131a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 1214334c03b5SZvi Nachmani 1215334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 1216351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 1217334c03b5SZvi Nachmani 1218351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1219334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1220334c03b5SZvi Nachmani else 1221334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1222334c03b5SZvi Nachmani } 1223334c03b5SZvi Nachmani 1224645874e5SSudarsana Reddy Kalluru static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1225645874e5SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1226645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_state *p_link) 1227645874e5SSudarsana Reddy Kalluru { 1228645874e5SSudarsana Reddy Kalluru u32 eee_status, val; 1229645874e5SSudarsana Reddy Kalluru 1230645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps = 0; 1231645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps = 0; 1232645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, 1233645874e5SSudarsana Reddy Kalluru p_ptt, 1234645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 1235645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 1236645874e5SSudarsana Reddy Kalluru p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1237645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1238645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1239645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1240645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1241645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1242645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1243645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1244645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1245645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1246645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1247645874e5SSudarsana Reddy Kalluru } 1248645874e5SSudarsana Reddy Kalluru 1249e40a826aSSudarsana Reddy Kalluru static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 1250e40a826aSSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1251e40a826aSSudarsana Reddy Kalluru struct public_func *p_data, int pfid) 1252e40a826aSSudarsana Reddy Kalluru { 1253e40a826aSSudarsana Reddy Kalluru u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1254e40a826aSSudarsana Reddy Kalluru PUBLIC_FUNC); 1255e40a826aSSudarsana Reddy Kalluru u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1256e40a826aSSudarsana Reddy Kalluru u32 func_addr; 1257e40a826aSSudarsana Reddy Kalluru u32 i, size; 1258e40a826aSSudarsana Reddy Kalluru 1259e40a826aSSudarsana Reddy Kalluru func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 1260e40a826aSSudarsana Reddy Kalluru memset(p_data, 0, sizeof(*p_data)); 1261e40a826aSSudarsana Reddy Kalluru 1262e40a826aSSudarsana Reddy Kalluru size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 1263e40a826aSSudarsana Reddy Kalluru for (i = 0; i < size / sizeof(u32); i++) 1264e40a826aSSudarsana Reddy Kalluru ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 1265e40a826aSSudarsana Reddy Kalluru func_addr + (i << 2)); 1266e40a826aSSudarsana Reddy Kalluru return size; 1267e40a826aSSudarsana Reddy Kalluru } 1268e40a826aSSudarsana Reddy Kalluru 1269e40a826aSSudarsana Reddy Kalluru static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 1270e40a826aSSudarsana Reddy Kalluru struct public_func *p_shmem_info) 1271e40a826aSSudarsana Reddy Kalluru { 1272e40a826aSSudarsana Reddy Kalluru struct qed_mcp_function_info *p_info; 1273e40a826aSSudarsana Reddy Kalluru 1274e40a826aSSudarsana Reddy Kalluru p_info = &p_hwfn->mcp_info->func_info; 1275e40a826aSSudarsana Reddy Kalluru 1276e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = QED_MFW_GET_FIELD(p_shmem_info->config, 1277e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MIN_BW); 1278e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 1279e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1280e40a826aSSudarsana Reddy Kalluru "bandwidth minimum out of bounds [%02x]. Set to 1\n", 1281e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min); 1282e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = 1; 1283e40a826aSSudarsana Reddy Kalluru } 1284e40a826aSSudarsana Reddy Kalluru 1285e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = QED_MFW_GET_FIELD(p_shmem_info->config, 1286e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MAX_BW); 1287e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 1288e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1289e40a826aSSudarsana Reddy Kalluru "bandwidth maximum out of bounds [%02x]. Set to 100\n", 1290e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max); 1291e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = 100; 1292e40a826aSSudarsana Reddy Kalluru } 1293e40a826aSSudarsana Reddy Kalluru } 1294e40a826aSSudarsana Reddy Kalluru 1295cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 12961a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 1297cc875c2eSYuval Mintz { 1298cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 1299a64b02d5SManish Chopra u8 max_bw, min_bw; 1300cc875c2eSYuval Mintz u32 status = 0; 1301cc875c2eSYuval Mintz 130265ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 130365ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 130465ed2ffdSMintz, Yuval 1305cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 1306cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 1307cc875c2eSYuval Mintz if (!b_reset) { 1308cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 1309cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 1310cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 1311cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1312cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1313cc875c2eSYuval Mintz status, 1314cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 13151a635e48SYuval Mintz offsetof(struct public_port, link_status))); 1316cc875c2eSYuval Mintz } else { 1317cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1318cc875c2eSYuval Mintz "Resetting link indications\n"); 131965ed2ffdSMintz, Yuval goto out; 1320cc875c2eSYuval Mintz } 1321cc875c2eSYuval Mintz 1322e40a826aSSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) { 1323e40a826aSSudarsana Reddy Kalluru /* Link indication with modern MFW arrives as per-PF 1324e40a826aSSudarsana Reddy Kalluru * indication. 1325e40a826aSSudarsana Reddy Kalluru */ 1326e40a826aSSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & 1327e40a826aSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_VLINK) { 1328e40a826aSSudarsana Reddy Kalluru struct public_func shmem_info; 1329e40a826aSSudarsana Reddy Kalluru 1330e40a826aSSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 1331e40a826aSSudarsana Reddy Kalluru MCP_PF_ID(p_hwfn)); 1332e40a826aSSudarsana Reddy Kalluru p_link->link_up = !!(shmem_info.status & 1333e40a826aSSudarsana Reddy Kalluru FUNC_STATUS_VIRTUAL_LINK_UP); 1334e40a826aSSudarsana Reddy Kalluru qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1335e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1336e40a826aSSudarsana Reddy Kalluru "Virtual link_up = %d\n", p_link->link_up); 1337e40a826aSSudarsana Reddy Kalluru } else { 1338cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1339e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1340e40a826aSSudarsana Reddy Kalluru "Physical link_up = %d\n", p_link->link_up); 1341e40a826aSSudarsana Reddy Kalluru } 1342e40a826aSSudarsana Reddy Kalluru } else { 1343fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 1344e40a826aSSudarsana Reddy Kalluru } 1345cc875c2eSYuval Mintz 1346cc875c2eSYuval Mintz p_link->full_duplex = true; 1347cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1348cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1349cc875c2eSYuval Mintz p_link->speed = 100000; 1350cc875c2eSYuval Mintz break; 1351cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1352cc875c2eSYuval Mintz p_link->speed = 50000; 1353cc875c2eSYuval Mintz break; 1354cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1355cc875c2eSYuval Mintz p_link->speed = 40000; 1356cc875c2eSYuval Mintz break; 1357cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1358cc875c2eSYuval Mintz p_link->speed = 25000; 1359cc875c2eSYuval Mintz break; 1360cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1361cc875c2eSYuval Mintz p_link->speed = 20000; 1362cc875c2eSYuval Mintz break; 1363cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1364cc875c2eSYuval Mintz p_link->speed = 10000; 1365cc875c2eSYuval Mintz break; 1366cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1367cc875c2eSYuval Mintz p_link->full_duplex = false; 1368df561f66SGustavo A. R. Silva fallthrough; 1369cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1370cc875c2eSYuval Mintz p_link->speed = 1000; 1371cc875c2eSYuval Mintz break; 1372cc875c2eSYuval Mintz default: 1373cc875c2eSYuval Mintz p_link->speed = 0; 137458874c7bSSudarsana Reddy Kalluru p_link->link_up = 0; 1375cc875c2eSYuval Mintz } 1376cc875c2eSYuval Mintz 13774b01e519SManish Chopra if (p_link->link_up && p_link->speed) 13784b01e519SManish Chopra p_link->line_speed = p_link->speed; 13794b01e519SManish Chopra else 13804b01e519SManish Chopra p_link->line_speed = 0; 13814b01e519SManish Chopra 13824b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1383a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 13844b01e519SManish Chopra 1385a64b02d5SManish Chopra /* Max bandwidth configuration */ 13864b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1387cc875c2eSYuval Mintz 1388a64b02d5SManish Chopra /* Min bandwidth configuration */ 1389a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 13906f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 13916f437d43SMintz, Yuval p_link->min_pf_rate); 1392a64b02d5SManish Chopra 1393cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1394cc875c2eSYuval Mintz p_link->an_complete = !!(status & 1395cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1396cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 1397cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 1398cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1399cc875c2eSYuval Mintz 1400cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1401cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1402cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 1403cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1404cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1405cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 1406cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1407cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1408cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 1409cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1410cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1411cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 1412cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1413054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1414054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 1415054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 1416cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1417cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 1418cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1419cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1420cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 1421cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1422cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1423cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 1424cc875c2eSYuval Mintz 1425cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 1426cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1427cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 1428cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1429cc875c2eSYuval Mintz 1430cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1431cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1432cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1433cc875c2eSYuval Mintz break; 1434cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1435cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1436cc875c2eSYuval Mintz break; 1437cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1438cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1439cc875c2eSYuval Mintz break; 1440cc875c2eSYuval Mintz default: 1441cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 1442cc875c2eSYuval Mintz } 1443cc875c2eSYuval Mintz 1444cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1445cc875c2eSYuval Mintz 1446645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1447645874e5SSudarsana Reddy Kalluru qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1448645874e5SSudarsana Reddy Kalluru 1449ae7e6937SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 1450ae7e6937SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) { 1451ae7e6937SAlexander Lobakin switch (status & LINK_STATUS_FEC_MODE_MASK) { 1452ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_NONE: 1453ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_NONE; 1454ae7e6937SAlexander Lobakin break; 1455ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_FIRECODE_CL74: 1456ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_FIRECODE; 1457ae7e6937SAlexander Lobakin break; 1458ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_RS_CL91: 1459ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_RS; 1460ae7e6937SAlexander Lobakin break; 1461ae7e6937SAlexander Lobakin default: 1462ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_AUTO; 1463ae7e6937SAlexander Lobakin } 1464ae7e6937SAlexander Lobakin } else { 1465ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_UNSUPPORTED; 1466ae7e6937SAlexander Lobakin } 1467ae7e6937SAlexander Lobakin 1468706d0891SRahul Verma qed_link_update(p_hwfn, p_ptt); 146965ed2ffdSMintz, Yuval out: 147065ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1471cc875c2eSYuval Mintz } 1472cc875c2eSYuval Mintz 1473351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1474cc875c2eSYuval Mintz { 1475cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 14765529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 14772f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 1478ae7e6937SAlexander Lobakin u32 cmd, fec_bit = 0; 147999785a87SAlexander Lobakin u32 val, ext_speed; 1480cc875c2eSYuval Mintz int rc = 0; 1481cc875c2eSYuval Mintz 1482cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 14832f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 1484cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1485cc875c2eSYuval Mintz if (!params->speed.autoneg) 14862f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 14872f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 14882f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 14892f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 14902f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 14912f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 14924ad95a93SSudarsana Reddy Kalluru 14934ad95a93SSudarsana Reddy Kalluru /* There are MFWs that share this capability regardless of whether 14944ad95a93SSudarsana Reddy Kalluru * this is feasible or not. And given that at the very least adv_caps 14954ad95a93SSudarsana Reddy Kalluru * would be set internally by qed, we want to make sure LFA would 14964ad95a93SSudarsana Reddy Kalluru * still work. 14974ad95a93SSudarsana Reddy Kalluru */ 14984ad95a93SSudarsana Reddy Kalluru if ((p_hwfn->mcp_info->capabilities & 14994ad95a93SSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1500645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1501645874e5SSudarsana Reddy Kalluru if (params->eee.tx_lpi_enable) 1502645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1503645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_1G_ADV) 1504645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1505645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_10G_ADV) 1506645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1507645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1508645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_OFFSET) & 1509645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_MASK; 1510645874e5SSudarsana Reddy Kalluru } 1511cc875c2eSYuval Mintz 1512ae7e6937SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 1513ae7e6937SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) { 1514ae7e6937SAlexander Lobakin if (params->fec & QED_FEC_MODE_NONE) 1515ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_NONE; 1516ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_FIRECODE) 1517ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_FIRECODE; 1518ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_RS) 1519ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_RS; 1520ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_AUTO) 1521ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_AUTO; 1522ae7e6937SAlexander Lobakin 1523ae7e6937SAlexander Lobakin SET_MFW_FIELD(phy_cfg.fec_mode, FEC_FORCE_MODE, fec_bit); 1524ae7e6937SAlexander Lobakin } 1525ae7e6937SAlexander Lobakin 152699785a87SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 152799785a87SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL) { 152899785a87SAlexander Lobakin ext_speed = 0; 152999785a87SAlexander Lobakin if (params->ext_speed.autoneg) 153099785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_AN; 153199785a87SAlexander Lobakin 153299785a87SAlexander Lobakin val = params->ext_speed.forced_speed; 153399785a87SAlexander Lobakin if (val & QED_EXT_SPEED_1G) 153499785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_1G; 153599785a87SAlexander Lobakin if (val & QED_EXT_SPEED_10G) 153699785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_10G; 153799785a87SAlexander Lobakin if (val & QED_EXT_SPEED_20G) 153899785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_20G; 153999785a87SAlexander Lobakin if (val & QED_EXT_SPEED_25G) 154099785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_25G; 154199785a87SAlexander Lobakin if (val & QED_EXT_SPEED_40G) 154299785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_40G; 154399785a87SAlexander Lobakin if (val & QED_EXT_SPEED_50G_R) 154499785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_50G_BASE_R; 154599785a87SAlexander Lobakin if (val & QED_EXT_SPEED_50G_R2) 154699785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_50G_BASE_R2; 154799785a87SAlexander Lobakin if (val & QED_EXT_SPEED_100G_R2) 154899785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_100G_BASE_R2; 154999785a87SAlexander Lobakin if (val & QED_EXT_SPEED_100G_R4) 155099785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_100G_BASE_R4; 155199785a87SAlexander Lobakin if (val & QED_EXT_SPEED_100G_P4) 155299785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_100G_BASE_P4; 155399785a87SAlexander Lobakin 155499785a87SAlexander Lobakin SET_MFW_FIELD(phy_cfg.extended_speed, ETH_EXT_SPEED, 155599785a87SAlexander Lobakin ext_speed); 155699785a87SAlexander Lobakin 155799785a87SAlexander Lobakin ext_speed = 0; 155899785a87SAlexander Lobakin 155999785a87SAlexander Lobakin val = params->ext_speed.advertised_speeds; 156099785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_1G) 156199785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_1G; 156299785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_10G) 156399785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_10G; 156499785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_20G) 156599785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_20G; 156699785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_25G) 156799785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_25G; 156899785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_40G) 156999785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_40G; 157099785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_50G_R) 157199785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_50G_BASE_R; 157299785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_50G_R2) 157399785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_50G_BASE_R2; 157499785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_100G_R2) 157599785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_R2; 157699785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_100G_R4) 157799785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_R4; 157899785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_100G_P4) 157999785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_P4; 158099785a87SAlexander Lobakin 158199785a87SAlexander Lobakin phy_cfg.extended_speed |= ext_speed; 158299785a87SAlexander Lobakin 158399785a87SAlexander Lobakin SET_MFW_FIELD(phy_cfg.fec_mode, FEC_EXTENDED_MODE, 158499785a87SAlexander Lobakin params->ext_fec_mode); 158599785a87SAlexander Lobakin } 158699785a87SAlexander Lobakin 1587fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 1588fc916ff2SSudarsana Reddy Kalluru 1589cc875c2eSYuval Mintz if (b_up) { 1590cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 159199785a87SAlexander Lobakin "Configuring Link: Speed 0x%08x, Pause 0x%08x, Adv. Speed 0x%08x, Loopback 0x%08x, FEC 0x%08x, Ext. Speed 0x%08x\n", 1592ae7e6937SAlexander Lobakin phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed, 159399785a87SAlexander Lobakin phy_cfg.loopback_mode, phy_cfg.fec_mode, 159499785a87SAlexander Lobakin phy_cfg.extended_speed); 1595cc875c2eSYuval Mintz } else { 159699785a87SAlexander Lobakin DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, "Resetting link\n"); 1597cc875c2eSYuval Mintz } 1598cc875c2eSYuval Mintz 15995529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 16005529bad9STomer Tayar mb_params.cmd = cmd; 16012f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 16022f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 16035529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1604cc875c2eSYuval Mintz 1605cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 1606cc875c2eSYuval Mintz if (rc) { 1607cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1608cc875c2eSYuval Mintz return rc; 1609cc875c2eSYuval Mintz } 1610cc875c2eSYuval Mintz 161165ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 161265ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 161365ed2ffdSMintz, Yuval * an attention. 161465ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 161565ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 161665ed2ffdSMintz, Yuval */ 161765ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1618cc875c2eSYuval Mintz 1619cc875c2eSYuval Mintz return 0; 1620cc875c2eSYuval Mintz } 1621cc875c2eSYuval Mintz 162264515dc8STomer Tayar u32 qed_get_process_kill_counter(struct qed_hwfn *p_hwfn, 162364515dc8STomer Tayar struct qed_ptt *p_ptt) 162464515dc8STomer Tayar { 162564515dc8STomer Tayar u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt; 162664515dc8STomer Tayar 162764515dc8STomer Tayar if (IS_VF(p_hwfn->cdev)) 162864515dc8STomer Tayar return -EINVAL; 162964515dc8STomer Tayar 163064515dc8STomer Tayar path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 163164515dc8STomer Tayar PUBLIC_PATH); 163264515dc8STomer Tayar path_offsize = qed_rd(p_hwfn, p_ptt, path_offsize_addr); 163364515dc8STomer Tayar path_addr = SECTION_ADDR(path_offsize, QED_PATH_ID(p_hwfn)); 163464515dc8STomer Tayar 163564515dc8STomer Tayar proc_kill_cnt = qed_rd(p_hwfn, p_ptt, 163664515dc8STomer Tayar path_addr + 163764515dc8STomer Tayar offsetof(struct public_path, process_kill)) & 163864515dc8STomer Tayar PROCESS_KILL_COUNTER_MASK; 163964515dc8STomer Tayar 164064515dc8STomer Tayar return proc_kill_cnt; 164164515dc8STomer Tayar } 164264515dc8STomer Tayar 164364515dc8STomer Tayar static void qed_mcp_handle_process_kill(struct qed_hwfn *p_hwfn, 164464515dc8STomer Tayar struct qed_ptt *p_ptt) 164564515dc8STomer Tayar { 164664515dc8STomer Tayar struct qed_dev *cdev = p_hwfn->cdev; 164764515dc8STomer Tayar u32 proc_kill_cnt; 164864515dc8STomer Tayar 164964515dc8STomer Tayar /* Prevent possible attentions/interrupts during the recovery handling 165064515dc8STomer Tayar * and till its load phase, during which they will be re-enabled. 165164515dc8STomer Tayar */ 165264515dc8STomer Tayar qed_int_igu_disable_int(p_hwfn, p_ptt); 165364515dc8STomer Tayar 165464515dc8STomer Tayar DP_NOTICE(p_hwfn, "Received a process kill indication\n"); 165564515dc8STomer Tayar 165664515dc8STomer Tayar /* The following operations should be done once, and thus in CMT mode 165764515dc8STomer Tayar * are carried out by only the first HW function. 165864515dc8STomer Tayar */ 165964515dc8STomer Tayar if (p_hwfn != QED_LEADING_HWFN(cdev)) 166064515dc8STomer Tayar return; 166164515dc8STomer Tayar 166264515dc8STomer Tayar if (cdev->recov_in_prog) { 166364515dc8STomer Tayar DP_NOTICE(p_hwfn, 166464515dc8STomer Tayar "Ignoring the indication since a recovery process is already in progress\n"); 166564515dc8STomer Tayar return; 166664515dc8STomer Tayar } 166764515dc8STomer Tayar 166864515dc8STomer Tayar cdev->recov_in_prog = true; 166964515dc8STomer Tayar 167064515dc8STomer Tayar proc_kill_cnt = qed_get_process_kill_counter(p_hwfn, p_ptt); 167164515dc8STomer Tayar DP_NOTICE(p_hwfn, "Process kill counter: %d\n", proc_kill_cnt); 167264515dc8STomer Tayar 167364515dc8STomer Tayar qed_schedule_recovery_handler(p_hwfn); 167464515dc8STomer Tayar } 167564515dc8STomer Tayar 16766c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 16776c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 16786c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 16796c754246SSudarsana Reddy Kalluru { 16806c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 16816c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 16826c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 16836c754246SSudarsana Reddy Kalluru u32 hsi_param; 16846c754246SSudarsana Reddy Kalluru 16856c754246SSudarsana Reddy Kalluru switch (type) { 16866c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 16876c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 16886c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 16896c754246SSudarsana Reddy Kalluru break; 16906c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 16916c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 16926c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 16936c754246SSudarsana Reddy Kalluru break; 16946c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 16956c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 16966c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 16976c754246SSudarsana Reddy Kalluru break; 16986c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 16996c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 17006c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 17016c754246SSudarsana Reddy Kalluru break; 17026c754246SSudarsana Reddy Kalluru default: 17036c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 17046c754246SSudarsana Reddy Kalluru return; 17056c754246SSudarsana Reddy Kalluru } 17066c754246SSudarsana Reddy Kalluru 17076c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 17086c754246SSudarsana Reddy Kalluru 17096c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 17106c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 17116c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 17122f67af8cSTomer Tayar mb_params.p_data_src = &stats; 17132f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 17146c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 17156c754246SSudarsana Reddy Kalluru } 17166c754246SSudarsana Reddy Kalluru 17171a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 17184b01e519SManish Chopra { 17194b01e519SManish Chopra struct qed_mcp_function_info *p_info; 17204b01e519SManish Chopra struct public_func shmem_info; 17214b01e519SManish Chopra u32 resp = 0, param = 0; 17224b01e519SManish Chopra 17231a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 17244b01e519SManish Chopra 17254b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 17264b01e519SManish Chopra 17274b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 17284b01e519SManish Chopra 1729a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 17304b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 17314b01e519SManish Chopra 17324b01e519SManish Chopra /* Acknowledge the MFW */ 17334b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 17344b01e519SManish Chopra ¶m); 17354b01e519SManish Chopra } 17364b01e519SManish Chopra 17372a351fd9SMintz, Yuval static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 17382a351fd9SMintz, Yuval { 17392a351fd9SMintz, Yuval struct public_func shmem_info; 17402a351fd9SMintz, Yuval u32 resp = 0, param = 0; 17412a351fd9SMintz, Yuval 17422a351fd9SMintz, Yuval qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 17432a351fd9SMintz, Yuval 17442a351fd9SMintz, Yuval p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 17452a351fd9SMintz, Yuval FUNC_MF_CFG_OV_STAG_MASK; 17462a351fd9SMintz, Yuval p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 17477e3e375cSSudarsana Reddy Kalluru if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) { 17487e3e375cSSudarsana Reddy Kalluru if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) { 17497e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 17507e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 17517e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1); 17527e3e375cSSudarsana Reddy Kalluru 17537e3e375cSSudarsana Reddy Kalluru /* Configure DB to add external vlan to EDPM packets */ 17547e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1); 17557e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 17567e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 17577e3e375cSSudarsana Reddy Kalluru } else { 17587e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0); 17597e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0); 17607e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0); 17617e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0); 17627e3e375cSSudarsana Reddy Kalluru } 17637e3e375cSSudarsana Reddy Kalluru 17642a351fd9SMintz, Yuval qed_sp_pf_update_stag(p_hwfn); 17652a351fd9SMintz, Yuval } 17662a351fd9SMintz, Yuval 17677e3e375cSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan = %d hw_mode = 0x%x\n", 17687e3e375cSSudarsana Reddy Kalluru p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode); 17697e3e375cSSudarsana Reddy Kalluru 17702a351fd9SMintz, Yuval /* Acknowledge the MFW */ 17712a351fd9SMintz, Yuval qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 17722a351fd9SMintz, Yuval &resp, ¶m); 17732a351fd9SMintz, Yuval } 17742a351fd9SMintz, Yuval 17753e99c211SIgor Russkikh static void qed_mcp_handle_fan_failure(struct qed_hwfn *p_hwfn, 17763e99c211SIgor Russkikh struct qed_ptt *p_ptt) 17773e99c211SIgor Russkikh { 17783e99c211SIgor Russkikh /* A single notification should be sent to upper driver in CMT mode */ 17793e99c211SIgor Russkikh if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev)) 17803e99c211SIgor Russkikh return; 17813e99c211SIgor Russkikh 17823e99c211SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_FAN_FAIL, 17833e99c211SIgor Russkikh "Fan failure was detected on the network interface card and it's going to be shut down.\n"); 17843e99c211SIgor Russkikh } 17853e99c211SIgor Russkikh 1786ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params { 1787ebf64bf4SIgor Russkikh u32 cmd; 1788ebf64bf4SIgor Russkikh void *p_data_src; 1789ebf64bf4SIgor Russkikh u8 data_src_size; 1790ebf64bf4SIgor Russkikh void *p_data_dst; 1791ebf64bf4SIgor Russkikh u8 data_dst_size; 1792ebf64bf4SIgor Russkikh u32 mcp_resp; 1793ebf64bf4SIgor Russkikh }; 1794ebf64bf4SIgor Russkikh 1795ebf64bf4SIgor Russkikh static int 1796ebf64bf4SIgor Russkikh qed_mcp_mdump_cmd(struct qed_hwfn *p_hwfn, 1797ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt, 1798ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params *p_mdump_cmd_params) 1799ebf64bf4SIgor Russkikh { 1800ebf64bf4SIgor Russkikh struct qed_mcp_mb_params mb_params; 1801ebf64bf4SIgor Russkikh int rc; 1802ebf64bf4SIgor Russkikh 1803ebf64bf4SIgor Russkikh memset(&mb_params, 0, sizeof(mb_params)); 1804ebf64bf4SIgor Russkikh mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD; 1805ebf64bf4SIgor Russkikh mb_params.param = p_mdump_cmd_params->cmd; 1806ebf64bf4SIgor Russkikh mb_params.p_data_src = p_mdump_cmd_params->p_data_src; 1807ebf64bf4SIgor Russkikh mb_params.data_src_size = p_mdump_cmd_params->data_src_size; 1808ebf64bf4SIgor Russkikh mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst; 1809ebf64bf4SIgor Russkikh mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size; 1810ebf64bf4SIgor Russkikh rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1811ebf64bf4SIgor Russkikh if (rc) 1812ebf64bf4SIgor Russkikh return rc; 1813ebf64bf4SIgor Russkikh 1814ebf64bf4SIgor Russkikh p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp; 1815ebf64bf4SIgor Russkikh 1816ebf64bf4SIgor Russkikh if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) { 1817ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1818ebf64bf4SIgor Russkikh "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n", 1819ebf64bf4SIgor Russkikh p_mdump_cmd_params->cmd); 1820ebf64bf4SIgor Russkikh rc = -EOPNOTSUPP; 1821ebf64bf4SIgor Russkikh } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 1822ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1823ebf64bf4SIgor Russkikh "The mdump command is not supported by the MFW\n"); 1824ebf64bf4SIgor Russkikh rc = -EOPNOTSUPP; 1825ebf64bf4SIgor Russkikh } 1826ebf64bf4SIgor Russkikh 1827ebf64bf4SIgor Russkikh return rc; 1828ebf64bf4SIgor Russkikh } 1829ebf64bf4SIgor Russkikh 1830ebf64bf4SIgor Russkikh static int qed_mcp_mdump_ack(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1831ebf64bf4SIgor Russkikh { 1832ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params mdump_cmd_params; 1833ebf64bf4SIgor Russkikh 1834ebf64bf4SIgor Russkikh memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params)); 1835ebf64bf4SIgor Russkikh mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK; 1836ebf64bf4SIgor Russkikh 1837ebf64bf4SIgor Russkikh return qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params); 1838ebf64bf4SIgor Russkikh } 1839ebf64bf4SIgor Russkikh 1840ebf64bf4SIgor Russkikh int 1841ebf64bf4SIgor Russkikh qed_mcp_mdump_get_retain(struct qed_hwfn *p_hwfn, 1842ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt, 1843ebf64bf4SIgor Russkikh struct mdump_retain_data_stc *p_mdump_retain) 1844ebf64bf4SIgor Russkikh { 1845ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params mdump_cmd_params; 1846ebf64bf4SIgor Russkikh int rc; 1847ebf64bf4SIgor Russkikh 1848ebf64bf4SIgor Russkikh memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params)); 1849ebf64bf4SIgor Russkikh mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN; 1850ebf64bf4SIgor Russkikh mdump_cmd_params.p_data_dst = p_mdump_retain; 1851ebf64bf4SIgor Russkikh mdump_cmd_params.data_dst_size = sizeof(*p_mdump_retain); 1852ebf64bf4SIgor Russkikh 1853ebf64bf4SIgor Russkikh rc = qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params); 1854ebf64bf4SIgor Russkikh if (rc) 1855ebf64bf4SIgor Russkikh return rc; 1856ebf64bf4SIgor Russkikh 1857ebf64bf4SIgor Russkikh if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) { 1858ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1859ebf64bf4SIgor Russkikh "Failed to get the mdump retained data [mcp_resp 0x%x]\n", 1860ebf64bf4SIgor Russkikh mdump_cmd_params.mcp_resp); 1861ebf64bf4SIgor Russkikh return -EINVAL; 1862ebf64bf4SIgor Russkikh } 1863ebf64bf4SIgor Russkikh 1864ebf64bf4SIgor Russkikh return 0; 1865ebf64bf4SIgor Russkikh } 1866ebf64bf4SIgor Russkikh 1867ebf64bf4SIgor Russkikh static void qed_mcp_handle_critical_error(struct qed_hwfn *p_hwfn, 1868ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt) 1869ebf64bf4SIgor Russkikh { 1870ebf64bf4SIgor Russkikh struct mdump_retain_data_stc mdump_retain; 1871ebf64bf4SIgor Russkikh int rc; 1872ebf64bf4SIgor Russkikh 1873ebf64bf4SIgor Russkikh /* In CMT mode - no need for more than a single acknowledgment to the 1874ebf64bf4SIgor Russkikh * MFW, and no more than a single notification to the upper driver. 1875ebf64bf4SIgor Russkikh */ 1876ebf64bf4SIgor Russkikh if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev)) 1877ebf64bf4SIgor Russkikh return; 1878ebf64bf4SIgor Russkikh 1879ebf64bf4SIgor Russkikh rc = qed_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain); 1880ebf64bf4SIgor Russkikh if (rc == 0 && mdump_retain.valid) 1881ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1882ebf64bf4SIgor Russkikh "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n", 1883ebf64bf4SIgor Russkikh mdump_retain.epoch, 1884ebf64bf4SIgor Russkikh mdump_retain.pf, mdump_retain.status); 1885ebf64bf4SIgor Russkikh else 1886ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1887ebf64bf4SIgor Russkikh "The MFW notified that a critical error occurred in the device\n"); 1888ebf64bf4SIgor Russkikh 1889ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1890ebf64bf4SIgor Russkikh "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n"); 1891ebf64bf4SIgor Russkikh qed_mcp_mdump_ack(p_hwfn, p_ptt); 1892ebf64bf4SIgor Russkikh 1893ebf64bf4SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_HW_ATTN, NULL); 1894ebf64bf4SIgor Russkikh } 1895ebf64bf4SIgor Russkikh 1896cac6f691SSudarsana Reddy Kalluru void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1897cac6f691SSudarsana Reddy Kalluru { 1898cac6f691SSudarsana Reddy Kalluru struct public_func shmem_info; 1899cac6f691SSudarsana Reddy Kalluru u32 port_cfg, val; 1900cac6f691SSudarsana Reddy Kalluru 1901cac6f691SSudarsana Reddy Kalluru if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1902cac6f691SSudarsana Reddy Kalluru return; 1903cac6f691SSudarsana Reddy Kalluru 1904cac6f691SSudarsana Reddy Kalluru memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1905cac6f691SSudarsana Reddy Kalluru port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1906cac6f691SSudarsana Reddy Kalluru offsetof(struct public_port, oem_cfg_port)); 1907cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1908cac6f691SSudarsana Reddy Kalluru OEM_CFG_CHANNEL_TYPE_OFFSET; 1909cac6f691SSudarsana Reddy Kalluru if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1910ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1911ec036eb9SSudarsana Reddy Kalluru "Incorrect UFP Channel type %d port_id 0x%02x\n", 1912ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1913cac6f691SSudarsana Reddy Kalluru 1914cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1915cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_SCHED_TYPE_ETS) { 1916cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1917cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1918cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1919cac6f691SSudarsana Reddy Kalluru } else { 1920cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1921ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1922ec036eb9SSudarsana Reddy Kalluru "Unknown UFP scheduling mode %d port_id 0x%02x\n", 1923ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1924cac6f691SSudarsana Reddy Kalluru } 1925cac6f691SSudarsana Reddy Kalluru 1926cac6f691SSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1927b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1928b5fabb08SSudarsana Reddy Kalluru OEM_CFG_FUNC_TC_OFFSET; 1929cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.tc = (u8)val; 1930b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1931cac6f691SSudarsana Reddy Kalluru OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1932cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1933cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1934cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1935cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1936cac6f691SSudarsana Reddy Kalluru } else { 1937cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1938ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1939ec036eb9SSudarsana Reddy Kalluru "Unknown Host priority control %d port_id 0x%02x\n", 1940ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1941cac6f691SSudarsana Reddy Kalluru } 1942cac6f691SSudarsana Reddy Kalluru 1943cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1944ec036eb9SSudarsana Reddy Kalluru "UFP shmem config: mode = %d tc = %d pri_type = %d port_id 0x%02x\n", 1945ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc, 1946ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type, MFW_PORT(p_hwfn)); 1947cac6f691SSudarsana Reddy Kalluru } 1948cac6f691SSudarsana Reddy Kalluru 1949cac6f691SSudarsana Reddy Kalluru static int 1950cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1951cac6f691SSudarsana Reddy Kalluru { 1952cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1953cac6f691SSudarsana Reddy Kalluru 1954cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1955cac6f691SSudarsana Reddy Kalluru p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1956c4259ddaSDenis Bolotin qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1957c4259ddaSDenis Bolotin p_hwfn->ufp_info.tc); 1958cac6f691SSudarsana Reddy Kalluru 1959cac6f691SSudarsana Reddy Kalluru qed_qm_reconf(p_hwfn, p_ptt); 1960cac6f691SSudarsana Reddy Kalluru } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1961cac6f691SSudarsana Reddy Kalluru /* Merge UFP TC with the dcbx TC data */ 1962cac6f691SSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1963cac6f691SSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 1964cac6f691SSudarsana Reddy Kalluru } else { 1965cac6f691SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1966cac6f691SSudarsana Reddy Kalluru return -EINVAL; 1967cac6f691SSudarsana Reddy Kalluru } 1968cac6f691SSudarsana Reddy Kalluru 1969cac6f691SSudarsana Reddy Kalluru /* update storm FW with negotiation results */ 1970cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_ufp(p_hwfn); 1971cac6f691SSudarsana Reddy Kalluru 1972cac6f691SSudarsana Reddy Kalluru /* update stag pcp value */ 1973cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_stag(p_hwfn); 1974cac6f691SSudarsana Reddy Kalluru 1975cac6f691SSudarsana Reddy Kalluru return 0; 1976cac6f691SSudarsana Reddy Kalluru } 1977cac6f691SSudarsana Reddy Kalluru 1978cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1979cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1980cc875c2eSYuval Mintz { 1981cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 1982cc875c2eSYuval Mintz int rc = 0; 1983cc875c2eSYuval Mintz bool found = false; 1984cc875c2eSYuval Mintz u16 i; 1985cc875c2eSYuval Mintz 1986cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1987cc875c2eSYuval Mintz 1988cc875c2eSYuval Mintz /* Read Messages from MFW */ 1989cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 1990cc875c2eSYuval Mintz 1991cc875c2eSYuval Mintz /* Compare current messages to old ones */ 1992cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 1993cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1994cc875c2eSYuval Mintz continue; 1995cc875c2eSYuval Mintz 1996cc875c2eSYuval Mintz found = true; 1997cc875c2eSYuval Mintz 1998cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1999cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 2000cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 2001cc875c2eSYuval Mintz 2002cc875c2eSYuval Mintz switch (i) { 2003cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 2004cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 2005cc875c2eSYuval Mintz break; 20060b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 20070b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 20080b55e27dSYuval Mintz break; 200939651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 201039651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 201139651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 201239651abdSSudarsana Reddy Kalluru break; 201339651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 201439651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 201539651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 201639651abdSSudarsana Reddy Kalluru break; 201739651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 201839651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 201939651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 202039651abdSSudarsana Reddy Kalluru break; 2021cac6f691SSudarsana Reddy Kalluru case MFW_DRV_MSG_OEM_CFG_UPDATE: 2022cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 2023cac6f691SSudarsana Reddy Kalluru break; 2024334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 2025334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 2026334c03b5SZvi Nachmani break; 202764515dc8STomer Tayar case MFW_DRV_MSG_ERROR_RECOVERY: 202864515dc8STomer Tayar qed_mcp_handle_process_kill(p_hwfn, p_ptt); 202964515dc8STomer Tayar break; 20306c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 20316c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 20326c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 20336c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 20346c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 20356c754246SSudarsana Reddy Kalluru break; 20364b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 20374b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 20384b01e519SManish Chopra break; 20392a351fd9SMintz, Yuval case MFW_DRV_MSG_S_TAG_UPDATE: 20402a351fd9SMintz, Yuval qed_mcp_update_stag(p_hwfn, p_ptt); 20412a351fd9SMintz, Yuval break; 20423e99c211SIgor Russkikh case MFW_DRV_MSG_FAILURE_DETECTED: 20433e99c211SIgor Russkikh qed_mcp_handle_fan_failure(p_hwfn, p_ptt); 20443e99c211SIgor Russkikh break; 2045ebf64bf4SIgor Russkikh case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED: 2046ebf64bf4SIgor Russkikh qed_mcp_handle_critical_error(p_hwfn, p_ptt); 2047ebf64bf4SIgor Russkikh break; 204859ccf86fSSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_TLV_REQ: 204959ccf86fSSudarsana Reddy Kalluru qed_mfw_tlv_req(p_hwfn); 20502a351fd9SMintz, Yuval break; 2051cc875c2eSYuval Mintz default: 205239815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 2053cc875c2eSYuval Mintz rc = -EINVAL; 2054cc875c2eSYuval Mintz } 2055cc875c2eSYuval Mintz } 2056cc875c2eSYuval Mintz 2057cc875c2eSYuval Mintz /* ACK everything */ 2058cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 2059cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 2060cc875c2eSYuval Mintz 2061cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 2062cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 2063cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 2064cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 2065cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 2066cc875c2eSYuval Mintz (__force u32)val); 2067cc875c2eSYuval Mintz } 2068cc875c2eSYuval Mintz 2069cc875c2eSYuval Mintz if (!found) { 2070cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 2071cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 2072cc875c2eSYuval Mintz rc = -EINVAL; 2073cc875c2eSYuval Mintz } 2074cc875c2eSYuval Mintz 2075cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 2076cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 2077cc875c2eSYuval Mintz 2078cc875c2eSYuval Mintz return rc; 2079cc875c2eSYuval Mintz } 2080cc875c2eSYuval Mintz 20811408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 20821408cc1fSYuval Mintz struct qed_ptt *p_ptt, 20831408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 2084fe56b9e6SYuval Mintz { 2085fe56b9e6SYuval Mintz u32 global_offsize; 2086fe56b9e6SYuval Mintz 20871408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 20881408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 20891408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 20901408cc1fSYuval Mintz 20911408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 20921408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 20931408cc1fSYuval Mintz return 0; 20941408cc1fSYuval Mintz } else { 20951408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 20961408cc1fSYuval Mintz QED_MSG_IOV, 20971408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 20981408cc1fSYuval Mintz return -EINVAL; 20991408cc1fSYuval Mintz } 21001408cc1fSYuval Mintz } 2101fe56b9e6SYuval Mintz 2102fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 21031408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 21041408cc1fSYuval Mintz mcp_info->public_base, 2105fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 21061408cc1fSYuval Mintz *p_mfw_ver = 21071408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 21081408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 21091408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 2110fe56b9e6SYuval Mintz 21111408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 21121408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 21131408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 21141408cc1fSYuval Mintz offsetof(struct public_global, 21151408cc1fSYuval Mintz running_bundle_id)); 21161408cc1fSYuval Mintz } 2117fe56b9e6SYuval Mintz 2118fe56b9e6SYuval Mintz return 0; 2119fe56b9e6SYuval Mintz } 2120fe56b9e6SYuval Mintz 2121ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 2122ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver) 2123ae33666aSTomer Tayar { 2124ae33666aSTomer Tayar u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 2125ae33666aSTomer Tayar 2126ae33666aSTomer Tayar if (IS_VF(p_hwfn->cdev)) 2127ae33666aSTomer Tayar return -EINVAL; 2128ae33666aSTomer Tayar 2129ae33666aSTomer Tayar /* Read the address of the nvm_cfg */ 2130ae33666aSTomer Tayar nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2131ae33666aSTomer Tayar if (!nvm_cfg_addr) { 2132ae33666aSTomer Tayar DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 2133ae33666aSTomer Tayar return -EINVAL; 2134ae33666aSTomer Tayar } 2135ae33666aSTomer Tayar 2136ae33666aSTomer Tayar /* Read the offset of nvm_cfg1 */ 2137ae33666aSTomer Tayar nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2138ae33666aSTomer Tayar 2139ae33666aSTomer Tayar mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2140ae33666aSTomer Tayar offsetof(struct nvm_cfg1, glob) + 2141ae33666aSTomer Tayar offsetof(struct nvm_cfg1_glob, mbi_version); 2142ae33666aSTomer Tayar *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 2143ae33666aSTomer Tayar mbi_ver_addr) & 2144ae33666aSTomer Tayar (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 2145ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 2146ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 2147ae33666aSTomer Tayar 2148ae33666aSTomer Tayar return 0; 2149ae33666aSTomer Tayar } 2150ae33666aSTomer Tayar 2151706d0891SRahul Verma int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, 2152706d0891SRahul Verma struct qed_ptt *p_ptt, u32 *p_media_type) 2153cc875c2eSYuval Mintz { 2154c56a8be7SRahul Verma *p_media_type = MEDIA_UNSPECIFIED; 2155c56a8be7SRahul Verma 2156706d0891SRahul Verma if (IS_VF(p_hwfn->cdev)) 21571408cc1fSYuval Mintz return -EINVAL; 21581408cc1fSYuval Mintz 2159cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 2160cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2161cc875c2eSYuval Mintz return -EBUSY; 2162cc875c2eSYuval Mintz } 2163cc875c2eSYuval Mintz 2164706d0891SRahul Verma if (!p_ptt) { 2165cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 2166706d0891SRahul Verma return -EINVAL; 2167706d0891SRahul Verma } 2168cc875c2eSYuval Mintz 2169706d0891SRahul Verma *p_media_type = qed_rd(p_hwfn, p_ptt, 2170706d0891SRahul Verma p_hwfn->mcp_info->port_addr + 2171706d0891SRahul Verma offsetof(struct public_port, 2172706d0891SRahul Verma media_type)); 2173cc875c2eSYuval Mintz 2174cc875c2eSYuval Mintz return 0; 2175cc875c2eSYuval Mintz } 2176cc875c2eSYuval Mintz 2177c56a8be7SRahul Verma int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, 2178c56a8be7SRahul Verma struct qed_ptt *p_ptt, 2179c56a8be7SRahul Verma u32 *p_transceiver_state, 2180c56a8be7SRahul Verma u32 *p_transceiver_type) 2181c56a8be7SRahul Verma { 2182c56a8be7SRahul Verma u32 transceiver_info; 2183c56a8be7SRahul Verma 218468203a67SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_NONE; 218568203a67SRahul Verma *p_transceiver_state = ETH_TRANSCEIVER_STATE_UPDATING; 218668203a67SRahul Verma 2187c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 2188c56a8be7SRahul Verma return -EINVAL; 2189c56a8be7SRahul Verma 2190c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 2191c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2192c56a8be7SRahul Verma return -EBUSY; 2193c56a8be7SRahul Verma } 2194c56a8be7SRahul Verma 2195c56a8be7SRahul Verma transceiver_info = qed_rd(p_hwfn, p_ptt, 2196c56a8be7SRahul Verma p_hwfn->mcp_info->port_addr + 2197c56a8be7SRahul Verma offsetof(struct public_port, 2198c56a8be7SRahul Verma transceiver_data)); 2199c56a8be7SRahul Verma 2200c56a8be7SRahul Verma *p_transceiver_state = (transceiver_info & 2201c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_MASK) >> 2202c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_OFFSET; 2203c56a8be7SRahul Verma 2204c56a8be7SRahul Verma if (*p_transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 2205c56a8be7SRahul Verma *p_transceiver_type = (transceiver_info & 2206c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_MASK) >> 2207c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_OFFSET; 2208c56a8be7SRahul Verma else 2209c56a8be7SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_UNKNOWN; 2210c56a8be7SRahul Verma 2211c56a8be7SRahul Verma return 0; 2212c56a8be7SRahul Verma } 2213c56a8be7SRahul Verma static bool qed_is_transceiver_ready(u32 transceiver_state, 2214c56a8be7SRahul Verma u32 transceiver_type) 2215c56a8be7SRahul Verma { 2216c56a8be7SRahul Verma if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) && 2217c56a8be7SRahul Verma ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) && 2218c56a8be7SRahul Verma (transceiver_type != ETH_TRANSCEIVER_TYPE_NONE)) 2219c56a8be7SRahul Verma return true; 2220c56a8be7SRahul Verma 2221c56a8be7SRahul Verma return false; 2222c56a8be7SRahul Verma } 2223c56a8be7SRahul Verma 2224c56a8be7SRahul Verma int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, 2225c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_speed_mask) 2226c56a8be7SRahul Verma { 2227c56a8be7SRahul Verma u32 transceiver_type, transceiver_state; 222892619210SArnd Bergmann int ret; 2229c56a8be7SRahul Verma 223092619210SArnd Bergmann ret = qed_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state, 2231c56a8be7SRahul Verma &transceiver_type); 223292619210SArnd Bergmann if (ret) 223392619210SArnd Bergmann return ret; 2234c56a8be7SRahul Verma 2235c56a8be7SRahul Verma if (qed_is_transceiver_ready(transceiver_state, transceiver_type) == 2236c56a8be7SRahul Verma false) 2237c56a8be7SRahul Verma return -EINVAL; 2238c56a8be7SRahul Verma 2239c56a8be7SRahul Verma switch (transceiver_type) { 2240c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_LX: 2241c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_SX: 2242c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_PCC: 2243c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_ACC: 2244c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1000BASET: 2245c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2246c56a8be7SRahul Verma break; 2247c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_SR: 2248c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LR: 2249c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LRM: 2250c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ER: 2251c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_PCC: 2252c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ACC: 2253c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x10G: 2254c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2255c56a8be7SRahul Verma break; 2256c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_LR4: 2257c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_SR4: 2258c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR: 2259c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR: 2260c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2261c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2262c56a8be7SRahul Verma break; 2263c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_AOC: 2264c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_SR4: 2265c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_LR4: 2266c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ER4: 2267c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ACC: 2268c56a8be7SRahul Verma *p_speed_mask = 2269c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2270c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2271c56a8be7SRahul Verma break; 2272c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_SR: 2273c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_LR: 2274c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_AOC: 2275c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_S: 2276c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_M: 2277c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_L: 2278c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2279c56a8be7SRahul Verma break; 2280c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_N: 2281c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_S: 2282c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_L: 2283c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x25G_CR: 2284c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2285c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2286c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2287c56a8be7SRahul Verma break; 22889228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR: 22899228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR: 22909228b7c1SAlexander Lobakin *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 22919228b7c1SAlexander Lobakin NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 22929228b7c1SAlexander Lobakin break; 2293c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_CR4: 2294c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR: 2295c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2296c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2297c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2298c56a8be7SRahul Verma break; 2299c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_CR4: 2300c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR: 2301c56a8be7SRahul Verma *p_speed_mask = 2302c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2303c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G | 2304c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2305c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2306c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G | 2307c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2308c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2309c56a8be7SRahul Verma break; 2310c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR: 2311c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR: 2312c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC: 2313c56a8be7SRahul Verma *p_speed_mask = 2314c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2315c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2316c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2317c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2318c56a8be7SRahul Verma break; 2319c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_XLPPI: 2320c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 2321c56a8be7SRahul Verma break; 2322c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_BASET: 23239228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR: 23249228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR: 2325c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2326c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2327c56a8be7SRahul Verma break; 2328c56a8be7SRahul Verma default: 23291107a674SColin Ian King DP_INFO(p_hwfn, "Unknown transceiver type 0x%x\n", 2330c56a8be7SRahul Verma transceiver_type); 2331c56a8be7SRahul Verma *p_speed_mask = 0xff; 2332c56a8be7SRahul Verma break; 2333c56a8be7SRahul Verma } 2334c56a8be7SRahul Verma 2335c56a8be7SRahul Verma return 0; 2336c56a8be7SRahul Verma } 2337c56a8be7SRahul Verma 2338c56a8be7SRahul Verma int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, 2339c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_board_config) 2340c56a8be7SRahul Verma { 2341c56a8be7SRahul Verma u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr; 2342c56a8be7SRahul Verma 2343c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 2344c56a8be7SRahul Verma return -EINVAL; 2345c56a8be7SRahul Verma 2346c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 2347c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2348c56a8be7SRahul Verma return -EBUSY; 2349c56a8be7SRahul Verma } 2350c56a8be7SRahul Verma if (!p_ptt) { 2351c56a8be7SRahul Verma *p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED; 2352c56a8be7SRahul Verma return -EINVAL; 2353c56a8be7SRahul Verma } 2354c56a8be7SRahul Verma 2355c56a8be7SRahul Verma nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2356c56a8be7SRahul Verma nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2357c56a8be7SRahul Verma port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2358c56a8be7SRahul Verma offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2359c56a8be7SRahul Verma *p_board_config = qed_rd(p_hwfn, p_ptt, 2360c56a8be7SRahul Verma port_cfg_addr + 2361c56a8be7SRahul Verma offsetof(struct nvm_cfg1_port, 2362c56a8be7SRahul Verma board_cfg)); 2363c56a8be7SRahul Verma 2364c56a8be7SRahul Verma return 0; 2365c56a8be7SRahul Verma } 2366c56a8be7SRahul Verma 23676927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 23686927e826SMintz, Yuval static void 23696927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 23706927e826SMintz, Yuval enum qed_pci_personality *p_proto) 23716927e826SMintz, Yuval { 23726927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 23736927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 23746927e826SMintz, Yuval */ 23756927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 23766927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 23776927e826SMintz, Yuval else 23786927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 23796927e826SMintz, Yuval 23806927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 23816927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 23826927e826SMintz, Yuval (u32) *p_proto); 23836927e826SMintz, Yuval } 23846927e826SMintz, Yuval 23856927e826SMintz, Yuval static int 23866927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 23876927e826SMintz, Yuval struct qed_ptt *p_ptt, 23886927e826SMintz, Yuval enum qed_pci_personality *p_proto) 23896927e826SMintz, Yuval { 23906927e826SMintz, Yuval u32 resp = 0, param = 0; 23916927e826SMintz, Yuval int rc; 23926927e826SMintz, Yuval 23936927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 23946927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 23956927e826SMintz, Yuval if (rc) 23966927e826SMintz, Yuval return rc; 23976927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 23986927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 23996927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 24006927e826SMintz, Yuval resp); 24016927e826SMintz, Yuval return -EINVAL; 24026927e826SMintz, Yuval } 24036927e826SMintz, Yuval 24046927e826SMintz, Yuval switch (param) { 24056927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 24066927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 24076927e826SMintz, Yuval break; 24086927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 24096927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 24106927e826SMintz, Yuval break; 24116927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 2412e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_IWARP; 2413e0a8f9deSMichal Kalderon break; 2414e0a8f9deSMichal Kalderon case FW_MB_PARAM_GET_PF_RDMA_BOTH: 2415e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_RDMA; 2416e0a8f9deSMichal Kalderon break; 24176927e826SMintz, Yuval default: 24186927e826SMintz, Yuval DP_NOTICE(p_hwfn, 24196927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 24206927e826SMintz, Yuval param); 24216927e826SMintz, Yuval return -EINVAL; 24226927e826SMintz, Yuval } 24236927e826SMintz, Yuval 24246927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 24256927e826SMintz, Yuval NETIF_MSG_IFUP, 24266927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 24276927e826SMintz, Yuval (u32) *p_proto, resp, param); 24286927e826SMintz, Yuval return 0; 24296927e826SMintz, Yuval } 24306927e826SMintz, Yuval 2431fe56b9e6SYuval Mintz static int 2432fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 2433fe56b9e6SYuval Mintz struct public_func *p_info, 24346927e826SMintz, Yuval struct qed_ptt *p_ptt, 2435fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 2436fe56b9e6SYuval Mintz { 2437fe56b9e6SYuval Mintz int rc = 0; 2438fe56b9e6SYuval Mintz 2439fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 2440fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 24411fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 24421fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 24431fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 24446927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 2445fe56b9e6SYuval Mintz break; 2446c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 2447c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 2448c5ac9319SYuval Mintz break; 24491e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 24501e128c81SArun Easi *p_proto = QED_PCI_FCOE; 24511e128c81SArun Easi break; 2452c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 2453c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 2454df561f66SGustavo A. R. Silva fallthrough; 2455fe56b9e6SYuval Mintz default: 2456fe56b9e6SYuval Mintz rc = -EINVAL; 2457fe56b9e6SYuval Mintz } 2458fe56b9e6SYuval Mintz 2459fe56b9e6SYuval Mintz return rc; 2460fe56b9e6SYuval Mintz } 2461fe56b9e6SYuval Mintz 2462fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 2463fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 2464fe56b9e6SYuval Mintz { 2465fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 2466fe56b9e6SYuval Mintz struct public_func shmem_info; 2467fe56b9e6SYuval Mintz 24681a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 2469fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 2470fe56b9e6SYuval Mintz 2471fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 2472fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 2473fe56b9e6SYuval Mintz 24746927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 24756927e826SMintz, Yuval &info->protocol)) { 2476fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 2477fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 2478fe56b9e6SYuval Mintz return -EINVAL; 2479fe56b9e6SYuval Mintz } 2480fe56b9e6SYuval Mintz 24814b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 2482fe56b9e6SYuval Mintz 2483fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 2484fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 2485fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 2486fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 2487fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 2488fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 2489fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 249014d39648SMintz, Yuval 249114d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 249214d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 2493fe56b9e6SYuval Mintz } else { 2494fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 2495fe56b9e6SYuval Mintz } 2496fe56b9e6SYuval Mintz 249757796759SMintz, Yuval info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 249857796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 249957796759SMintz, Yuval info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 250057796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 2501fe56b9e6SYuval Mintz 2502fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 2503fe56b9e6SYuval Mintz 25040fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 25050fefbfbaSSudarsana Kalluru 250614d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 250714d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 250814d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 250914d39648SMintz, Yuval u32 resp = 0, param = 0; 251014d39648SMintz, Yuval int rc; 251114d39648SMintz, Yuval 251214d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 251314d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 251414d39648SMintz, Yuval if (rc) 251514d39648SMintz, Yuval return rc; 251614d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 251714d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 251814d39648SMintz, Yuval } 251914d39648SMintz, Yuval 2520fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 2521b03c3bacSAndy Shevchenko "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %pM wwn port %llx node %llx ovlan %04x wol %02x\n", 2522fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 2523fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 2524b03c3bacSAndy Shevchenko info->mac, 252514d39648SMintz, Yuval info->wwn_port, info->wwn_node, 252614d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 2527fe56b9e6SYuval Mintz 2528fe56b9e6SYuval Mintz return 0; 2529fe56b9e6SYuval Mintz } 2530fe56b9e6SYuval Mintz 2531cc875c2eSYuval Mintz struct qed_mcp_link_params 2532cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 2533cc875c2eSYuval Mintz { 2534cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2535cc875c2eSYuval Mintz return NULL; 2536cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 2537cc875c2eSYuval Mintz } 2538cc875c2eSYuval Mintz 2539cc875c2eSYuval Mintz struct qed_mcp_link_state 2540cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 2541cc875c2eSYuval Mintz { 2542cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2543cc875c2eSYuval Mintz return NULL; 2544cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 2545cc875c2eSYuval Mintz } 2546cc875c2eSYuval Mintz 2547cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 2548cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 2549cc875c2eSYuval Mintz { 2550cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2551cc875c2eSYuval Mintz return NULL; 2552cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 2553cc875c2eSYuval Mintz } 2554cc875c2eSYuval Mintz 25551a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2556fe56b9e6SYuval Mintz { 2557fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 2558fe56b9e6SYuval Mintz int rc; 2559fe56b9e6SYuval Mintz 2560fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 25611a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 2562fe56b9e6SYuval Mintz 2563fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 25648f60bafeSYuval Mintz msleep(1020); 2565fe56b9e6SYuval Mintz 2566fe56b9e6SYuval Mintz return rc; 2567fe56b9e6SYuval Mintz } 2568fe56b9e6SYuval Mintz 2569cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 25701a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 2571cee4d264SManish Chopra { 2572cee4d264SManish Chopra u32 flash_size; 2573cee4d264SManish Chopra 25741408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 25751408cc1fSYuval Mintz return -EINVAL; 25761408cc1fSYuval Mintz 2577cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 2578cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 2579cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 2580cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 2581cee4d264SManish Chopra 2582cee4d264SManish Chopra *p_flash_size = flash_size; 2583cee4d264SManish Chopra 2584cee4d264SManish Chopra return 0; 2585cee4d264SManish Chopra } 2586cee4d264SManish Chopra 258764515dc8STomer Tayar int qed_start_recovery_process(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 258864515dc8STomer Tayar { 258964515dc8STomer Tayar struct qed_dev *cdev = p_hwfn->cdev; 259064515dc8STomer Tayar 259164515dc8STomer Tayar if (cdev->recov_in_prog) { 259264515dc8STomer Tayar DP_NOTICE(p_hwfn, 259364515dc8STomer Tayar "Avoid triggering a recovery since such a process is already in progress\n"); 259464515dc8STomer Tayar return -EAGAIN; 259564515dc8STomer Tayar } 259664515dc8STomer Tayar 259764515dc8STomer Tayar DP_NOTICE(p_hwfn, "Triggering a recovery process\n"); 259864515dc8STomer Tayar qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1); 259964515dc8STomer Tayar 260064515dc8STomer Tayar return 0; 260164515dc8STomer Tayar } 260264515dc8STomer Tayar 260364515dc8STomer Tayar #define QED_RECOVERY_PROLOG_SLEEP_MS 100 260464515dc8STomer Tayar 260564515dc8STomer Tayar int qed_recovery_prolog(struct qed_dev *cdev) 260664515dc8STomer Tayar { 260764515dc8STomer Tayar struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 260864515dc8STomer Tayar struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 260964515dc8STomer Tayar int rc; 261064515dc8STomer Tayar 261164515dc8STomer Tayar /* Allow ongoing PCIe transactions to complete */ 261264515dc8STomer Tayar msleep(QED_RECOVERY_PROLOG_SLEEP_MS); 261364515dc8STomer Tayar 261464515dc8STomer Tayar /* Clear the PF's internal FID_enable in the PXP */ 261564515dc8STomer Tayar rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false); 261664515dc8STomer Tayar if (rc) 261764515dc8STomer Tayar DP_NOTICE(p_hwfn, 261864515dc8STomer Tayar "qed_pglueb_set_pfid_enable() failed. rc = %d.\n", 261964515dc8STomer Tayar rc); 262064515dc8STomer Tayar 262164515dc8STomer Tayar return rc; 262264515dc8STomer Tayar } 262364515dc8STomer Tayar 262488072fd4SMintz, Yuval static int 262588072fd4SMintz, Yuval qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 26261408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 26271408cc1fSYuval Mintz { 26281408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 26291408cc1fSYuval Mintz int rc; 26301408cc1fSYuval Mintz 26311408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 26321408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 26331408cc1fSYuval Mintz return 0; 26341408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 26351408cc1fSYuval Mintz 26361408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 26371408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 26381408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 26391408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 26401408cc1fSYuval Mintz 26411408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 26421408cc1fSYuval Mintz &resp, &rc_param); 26431408cc1fSYuval Mintz 26441408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 26451408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 26461408cc1fSYuval Mintz rc = -EINVAL; 26471408cc1fSYuval Mintz } else { 26481408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 26491408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 26501408cc1fSYuval Mintz num, vf_id); 26511408cc1fSYuval Mintz } 26521408cc1fSYuval Mintz 26531408cc1fSYuval Mintz return rc; 26541408cc1fSYuval Mintz } 26551408cc1fSYuval Mintz 265688072fd4SMintz, Yuval static int 265788072fd4SMintz, Yuval qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 265888072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 num) 265988072fd4SMintz, Yuval { 266088072fd4SMintz, Yuval u32 resp = 0, param = num, rc_param = 0; 266188072fd4SMintz, Yuval int rc; 266288072fd4SMintz, Yuval 266388072fd4SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 266488072fd4SMintz, Yuval param, &resp, &rc_param); 266588072fd4SMintz, Yuval 266688072fd4SMintz, Yuval if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 266788072fd4SMintz, Yuval DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 266888072fd4SMintz, Yuval rc = -EINVAL; 266988072fd4SMintz, Yuval } else { 267088072fd4SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_IOV, 267188072fd4SMintz, Yuval "Requested 0x%02x MSI-x interrupts for VFs\n", num); 267288072fd4SMintz, Yuval } 267388072fd4SMintz, Yuval 267488072fd4SMintz, Yuval return rc; 267588072fd4SMintz, Yuval } 267688072fd4SMintz, Yuval 267788072fd4SMintz, Yuval int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 267888072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 vf_id, u8 num) 267988072fd4SMintz, Yuval { 268088072fd4SMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 268188072fd4SMintz, Yuval return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 268288072fd4SMintz, Yuval else 268388072fd4SMintz, Yuval return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 268488072fd4SMintz, Yuval } 268588072fd4SMintz, Yuval 2686fe56b9e6SYuval Mintz int 2687fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2688fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2689fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 2690fe56b9e6SYuval Mintz { 26915529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 26922f67af8cSTomer Tayar struct drv_version_stc drv_version; 26935529bad9STomer Tayar __be32 val; 26945529bad9STomer Tayar u32 i; 26955529bad9STomer Tayar int rc; 2696fe56b9e6SYuval Mintz 26972f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 26982f67af8cSTomer Tayar drv_version.version = p_ver->version; 269967a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 270067a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 27012f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2702fe56b9e6SYuval Mintz } 2703fe56b9e6SYuval Mintz 27045529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 27055529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 27062f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 27072f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 27085529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 27095529bad9STomer Tayar if (rc) 2710fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2711fe56b9e6SYuval Mintz 27125529bad9STomer Tayar return rc; 2713fe56b9e6SYuval Mintz } 271491420b83SSudarsana Kalluru 271576271809STomer Tayar /* A maximal 100 msec waiting time for the MCP to halt */ 271676271809STomer Tayar #define QED_MCP_HALT_SLEEP_MS 10 271776271809STomer Tayar #define QED_MCP_HALT_MAX_RETRIES 10 271876271809STomer Tayar 27194102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 27204102426fSTomer Tayar { 272176271809STomer Tayar u32 resp = 0, param = 0, cpu_state, cnt = 0; 27224102426fSTomer Tayar int rc; 27234102426fSTomer Tayar 27244102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 27254102426fSTomer Tayar ¶m); 272676271809STomer Tayar if (rc) { 27274102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 27284102426fSTomer Tayar return rc; 27294102426fSTomer Tayar } 27304102426fSTomer Tayar 273176271809STomer Tayar do { 273276271809STomer Tayar msleep(QED_MCP_HALT_SLEEP_MS); 273376271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 273476271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) 273576271809STomer Tayar break; 273676271809STomer Tayar } while (++cnt < QED_MCP_HALT_MAX_RETRIES); 273776271809STomer Tayar 273876271809STomer Tayar if (cnt == QED_MCP_HALT_MAX_RETRIES) { 273976271809STomer Tayar DP_NOTICE(p_hwfn, 274076271809STomer Tayar "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 274176271809STomer Tayar qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state); 274276271809STomer Tayar return -EBUSY; 274376271809STomer Tayar } 274476271809STomer Tayar 2745b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 2746b310974eSTomer Tayar 274776271809STomer Tayar return 0; 274876271809STomer Tayar } 274976271809STomer Tayar 275076271809STomer Tayar #define QED_MCP_RESUME_SLEEP_MS 10 275176271809STomer Tayar 27524102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 27534102426fSTomer Tayar { 275476271809STomer Tayar u32 cpu_mode, cpu_state; 27554102426fSTomer Tayar 27564102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 27574102426fSTomer Tayar 27584102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 275976271809STomer Tayar cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT; 276076271809STomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode); 276176271809STomer Tayar msleep(QED_MCP_RESUME_SLEEP_MS); 276276271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 27634102426fSTomer Tayar 276476271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) { 276576271809STomer Tayar DP_NOTICE(p_hwfn, 276676271809STomer Tayar "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 276776271809STomer Tayar cpu_mode, cpu_state); 276876271809STomer Tayar return -EBUSY; 276976271809STomer Tayar } 277076271809STomer Tayar 2771b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, false); 2772b310974eSTomer Tayar 277376271809STomer Tayar return 0; 27744102426fSTomer Tayar } 27754102426fSTomer Tayar 27760fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 27770fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 27780fefbfbaSSudarsana Kalluru enum qed_ov_client client) 27790fefbfbaSSudarsana Kalluru { 27800fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 27810fefbfbaSSudarsana Kalluru u32 drv_mb_param; 27820fefbfbaSSudarsana Kalluru int rc; 27830fefbfbaSSudarsana Kalluru 27840fefbfbaSSudarsana Kalluru switch (client) { 27850fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 27860fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 27870fefbfbaSSudarsana Kalluru break; 27880fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 27890fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 27900fefbfbaSSudarsana Kalluru break; 27910fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 27920fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 27930fefbfbaSSudarsana Kalluru break; 27940fefbfbaSSudarsana Kalluru default: 27950fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 27960fefbfbaSSudarsana Kalluru return -EINVAL; 27970fefbfbaSSudarsana Kalluru } 27980fefbfbaSSudarsana Kalluru 27990fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 28000fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 28010fefbfbaSSudarsana Kalluru if (rc) 28020fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 28030fefbfbaSSudarsana Kalluru 28040fefbfbaSSudarsana Kalluru return rc; 28050fefbfbaSSudarsana Kalluru } 28060fefbfbaSSudarsana Kalluru 28070fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 28080fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 28090fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 28100fefbfbaSSudarsana Kalluru { 28110fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 28120fefbfbaSSudarsana Kalluru u32 drv_mb_param; 28130fefbfbaSSudarsana Kalluru int rc; 28140fefbfbaSSudarsana Kalluru 28150fefbfbaSSudarsana Kalluru switch (drv_state) { 28160fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 28170fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 28180fefbfbaSSudarsana Kalluru break; 28190fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 28200fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 28210fefbfbaSSudarsana Kalluru break; 28220fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 28230fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 28240fefbfbaSSudarsana Kalluru break; 28250fefbfbaSSudarsana Kalluru default: 28260fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 28270fefbfbaSSudarsana Kalluru return -EINVAL; 28280fefbfbaSSudarsana Kalluru } 28290fefbfbaSSudarsana Kalluru 28300fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 28310fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 28320fefbfbaSSudarsana Kalluru if (rc) 28330fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 28340fefbfbaSSudarsana Kalluru 28350fefbfbaSSudarsana Kalluru return rc; 28360fefbfbaSSudarsana Kalluru } 28370fefbfbaSSudarsana Kalluru 28380fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 28390fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 28400fefbfbaSSudarsana Kalluru { 28410fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 28420fefbfbaSSudarsana Kalluru u32 drv_mb_param; 28430fefbfbaSSudarsana Kalluru int rc; 28440fefbfbaSSudarsana Kalluru 28450fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 28460fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 28470fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 28480fefbfbaSSudarsana Kalluru if (rc) 28490fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 28500fefbfbaSSudarsana Kalluru 28510fefbfbaSSudarsana Kalluru return rc; 28520fefbfbaSSudarsana Kalluru } 28530fefbfbaSSudarsana Kalluru 28540fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 28550fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 28560fefbfbaSSudarsana Kalluru { 28570fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 285817991002SMintz, Yuval u32 mfw_mac[2]; 28590fefbfbaSSudarsana Kalluru int rc; 28600fefbfbaSSudarsana Kalluru 28610fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 28620fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 28630fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 28640fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 28650fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 28662f67af8cSTomer Tayar 286717991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 286817991002SMintz, Yuval * in 32-bit granularity. 286917991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 287017991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 287117991002SMintz, Yuval */ 287217991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 287317991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 287417991002SMintz, Yuval 287517991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 287617991002SMintz, Yuval mb_params.data_src_size = 8; 28770fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 28780fefbfbaSSudarsana Kalluru if (rc) 28790fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 28800fefbfbaSSudarsana Kalluru 288114d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 288214d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 288314d39648SMintz, Yuval 28840fefbfbaSSudarsana Kalluru return rc; 28850fefbfbaSSudarsana Kalluru } 28860fefbfbaSSudarsana Kalluru 28870fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 28880fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 28890fefbfbaSSudarsana Kalluru { 28900fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 28910fefbfbaSSudarsana Kalluru u32 drv_mb_param; 28920fefbfbaSSudarsana Kalluru int rc; 28930fefbfbaSSudarsana Kalluru 289414d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 289514d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 289614d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 289714d39648SMintz, Yuval return -EINVAL; 289814d39648SMintz, Yuval } 289914d39648SMintz, Yuval 29000fefbfbaSSudarsana Kalluru switch (wol) { 29010fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 29020fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 29030fefbfbaSSudarsana Kalluru break; 29040fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 29050fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 29060fefbfbaSSudarsana Kalluru break; 29070fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 29080fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 29090fefbfbaSSudarsana Kalluru break; 29100fefbfbaSSudarsana Kalluru default: 29110fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 29120fefbfbaSSudarsana Kalluru return -EINVAL; 29130fefbfbaSSudarsana Kalluru } 29140fefbfbaSSudarsana Kalluru 29150fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 29160fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 29170fefbfbaSSudarsana Kalluru if (rc) 29180fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 29190fefbfbaSSudarsana Kalluru 292014d39648SMintz, Yuval /* Store the WoL update for a future unload */ 292114d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 292214d39648SMintz, Yuval 29230fefbfbaSSudarsana Kalluru return rc; 29240fefbfbaSSudarsana Kalluru } 29250fefbfbaSSudarsana Kalluru 29260fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 29270fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 29280fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 29290fefbfbaSSudarsana Kalluru { 29300fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 29310fefbfbaSSudarsana Kalluru u32 drv_mb_param; 29320fefbfbaSSudarsana Kalluru int rc; 29330fefbfbaSSudarsana Kalluru 29340fefbfbaSSudarsana Kalluru switch (eswitch) { 29350fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 29360fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 29370fefbfbaSSudarsana Kalluru break; 29380fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 29390fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 29400fefbfbaSSudarsana Kalluru break; 29410fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 29420fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 29430fefbfbaSSudarsana Kalluru break; 29440fefbfbaSSudarsana Kalluru default: 29450fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 29460fefbfbaSSudarsana Kalluru return -EINVAL; 29470fefbfbaSSudarsana Kalluru } 29480fefbfbaSSudarsana Kalluru 29490fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 29500fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 29510fefbfbaSSudarsana Kalluru if (rc) 29520fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 29530fefbfbaSSudarsana Kalluru 29540fefbfbaSSudarsana Kalluru return rc; 29550fefbfbaSSudarsana Kalluru } 29560fefbfbaSSudarsana Kalluru 29571a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 29581a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 295991420b83SSudarsana Kalluru { 296091420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 296191420b83SSudarsana Kalluru int rc; 296291420b83SSudarsana Kalluru 296391420b83SSudarsana Kalluru switch (mode) { 296491420b83SSudarsana Kalluru case QED_LED_MODE_ON: 296591420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 296691420b83SSudarsana Kalluru break; 296791420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 296891420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 296991420b83SSudarsana Kalluru break; 297091420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 297191420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 297291420b83SSudarsana Kalluru break; 297391420b83SSudarsana Kalluru default: 297491420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 297591420b83SSudarsana Kalluru return -EINVAL; 297691420b83SSudarsana Kalluru } 297791420b83SSudarsana Kalluru 297891420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 297991420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 298091420b83SSudarsana Kalluru 298191420b83SSudarsana Kalluru return rc; 298291420b83SSudarsana Kalluru } 298303dc76caSSudarsana Reddy Kalluru 29844102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 29854102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 29864102426fSTomer Tayar { 29874102426fSTomer Tayar u32 resp = 0, param = 0; 29884102426fSTomer Tayar int rc; 29894102426fSTomer Tayar 29904102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 29914102426fSTomer Tayar mask_parities, &resp, ¶m); 29924102426fSTomer Tayar 29934102426fSTomer Tayar if (rc) { 29944102426fSTomer Tayar DP_ERR(p_hwfn, 29954102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 29964102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 29974102426fSTomer Tayar DP_ERR(p_hwfn, 29984102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 29994102426fSTomer Tayar rc = -EINVAL; 30004102426fSTomer Tayar } 30014102426fSTomer Tayar 30024102426fSTomer Tayar return rc; 30034102426fSTomer Tayar } 30044102426fSTomer Tayar 30057a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 30067a4b21b7SMintz, Yuval { 30077a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 30087a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 30097a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 30107a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 30117a4b21b7SMintz, Yuval int rc = 0; 30127a4b21b7SMintz, Yuval 30137a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 30147a4b21b7SMintz, Yuval if (!p_ptt) 30157a4b21b7SMintz, Yuval return -EBUSY; 30167a4b21b7SMintz, Yuval 30177a4b21b7SMintz, Yuval while (bytes_left > 0) { 30187a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 30197a4b21b7SMintz, Yuval 30207a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 30217a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 30227a4b21b7SMintz, Yuval addr + offset + 30237a4b21b7SMintz, Yuval (bytes_to_copy << 3024da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 30257a4b21b7SMintz, Yuval &resp, &resp_param, 30267a4b21b7SMintz, Yuval &read_len, 30277a4b21b7SMintz, Yuval (u32 *)(p_buf + offset)); 30287a4b21b7SMintz, Yuval 30297a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 30307a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 30317a4b21b7SMintz, Yuval break; 30327a4b21b7SMintz, Yuval } 30337a4b21b7SMintz, Yuval 30347a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 30357a4b21b7SMintz, Yuval * isn't preemptable. Sleep a bit to prevent CPU hogging. 30367a4b21b7SMintz, Yuval */ 30377a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 30387a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 30397a4b21b7SMintz, Yuval usleep_range(1000, 2000); 30407a4b21b7SMintz, Yuval 30417a4b21b7SMintz, Yuval offset += read_len; 30427a4b21b7SMintz, Yuval bytes_left -= read_len; 30437a4b21b7SMintz, Yuval } 30447a4b21b7SMintz, Yuval 30457a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 30467a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 30477a4b21b7SMintz, Yuval 30487a4b21b7SMintz, Yuval return rc; 30497a4b21b7SMintz, Yuval } 30507a4b21b7SMintz, Yuval 305162e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 305262e4d438SSudarsana Reddy Kalluru { 305362e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 305462e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 305562e4d438SSudarsana Reddy Kalluru 305662e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 305762e4d438SSudarsana Reddy Kalluru if (!p_ptt) 305862e4d438SSudarsana Reddy Kalluru return -EBUSY; 305962e4d438SSudarsana Reddy Kalluru 306062e4d438SSudarsana Reddy Kalluru memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 306162e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 306262e4d438SSudarsana Reddy Kalluru 306362e4d438SSudarsana Reddy Kalluru return 0; 306462e4d438SSudarsana Reddy Kalluru } 306562e4d438SSudarsana Reddy Kalluru 306662e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 306762e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len) 306862e4d438SSudarsana Reddy Kalluru { 306962e4d438SSudarsana Reddy Kalluru u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 307062e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 307162e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 307262e4d438SSudarsana Reddy Kalluru int rc = -EINVAL; 307362e4d438SSudarsana Reddy Kalluru 307462e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 307562e4d438SSudarsana Reddy Kalluru if (!p_ptt) 307662e4d438SSudarsana Reddy Kalluru return -EBUSY; 307762e4d438SSudarsana Reddy Kalluru 307862e4d438SSudarsana Reddy Kalluru switch (cmd) { 3079057d2b19SSudarsana Reddy Kalluru case QED_PUT_FILE_BEGIN: 3080057d2b19SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN; 3081057d2b19SSudarsana Reddy Kalluru break; 308262e4d438SSudarsana Reddy Kalluru case QED_PUT_FILE_DATA: 308362e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 308462e4d438SSudarsana Reddy Kalluru break; 308562e4d438SSudarsana Reddy Kalluru case QED_NVM_WRITE_NVRAM: 308662e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 308762e4d438SSudarsana Reddy Kalluru break; 308862e4d438SSudarsana Reddy Kalluru default: 308962e4d438SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 309062e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 309162e4d438SSudarsana Reddy Kalluru goto out; 309262e4d438SSudarsana Reddy Kalluru } 309362e4d438SSudarsana Reddy Kalluru 309462e4d438SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 3095057d2b19SSudarsana Reddy Kalluru while (buf_idx < len) { 3096057d2b19SSudarsana Reddy Kalluru if (cmd == QED_PUT_FILE_BEGIN) 3097057d2b19SSudarsana Reddy Kalluru nvm_offset = addr; 3098057d2b19SSudarsana Reddy Kalluru else 3099057d2b19SSudarsana Reddy Kalluru nvm_offset = ((buf_size << 3100057d2b19SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_LEN_OFFSET) | addr) + 3101057d2b19SSudarsana Reddy Kalluru buf_idx; 310262e4d438SSudarsana Reddy Kalluru rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 310362e4d438SSudarsana Reddy Kalluru &resp, ¶m, buf_size, 310462e4d438SSudarsana Reddy Kalluru (u32 *)&p_buf[buf_idx]); 310562e4d438SSudarsana Reddy Kalluru if (rc) { 310662e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 310762e4d438SSudarsana Reddy Kalluru resp = FW_MSG_CODE_ERROR; 310862e4d438SSudarsana Reddy Kalluru break; 310962e4d438SSudarsana Reddy Kalluru } 311062e4d438SSudarsana Reddy Kalluru 311162e4d438SSudarsana Reddy Kalluru if (resp != FW_MSG_CODE_OK && 311262e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_OK && 311362e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 311462e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, 311562e4d438SSudarsana Reddy Kalluru "nvm write failed, resp = 0x%08x\n", resp); 311662e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 311762e4d438SSudarsana Reddy Kalluru break; 311862e4d438SSudarsana Reddy Kalluru } 311962e4d438SSudarsana Reddy Kalluru 312062e4d438SSudarsana Reddy Kalluru /* This can be a lengthy process, and it's possible scheduler 312162e4d438SSudarsana Reddy Kalluru * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 312262e4d438SSudarsana Reddy Kalluru */ 312362e4d438SSudarsana Reddy Kalluru if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 312462e4d438SSudarsana Reddy Kalluru usleep_range(1000, 2000); 312562e4d438SSudarsana Reddy Kalluru 3126057d2b19SSudarsana Reddy Kalluru /* For MBI upgrade, MFW response includes the next buffer offset 3127057d2b19SSudarsana Reddy Kalluru * to be delivered to MFW. 3128057d2b19SSudarsana Reddy Kalluru */ 3129057d2b19SSudarsana Reddy Kalluru if (param && cmd == QED_PUT_FILE_DATA) { 3130057d2b19SSudarsana Reddy Kalluru buf_idx = QED_MFW_GET_FIELD(param, 3131057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET); 3132057d2b19SSudarsana Reddy Kalluru buf_size = QED_MFW_GET_FIELD(param, 3133057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE); 3134057d2b19SSudarsana Reddy Kalluru } else { 313562e4d438SSudarsana Reddy Kalluru buf_idx += buf_size; 3136057d2b19SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), 3137057d2b19SSudarsana Reddy Kalluru MCP_DRV_NVM_BUF_LEN); 3138057d2b19SSudarsana Reddy Kalluru } 313962e4d438SSudarsana Reddy Kalluru } 314062e4d438SSudarsana Reddy Kalluru 314162e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 314262e4d438SSudarsana Reddy Kalluru out: 314362e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 314462e4d438SSudarsana Reddy Kalluru 314562e4d438SSudarsana Reddy Kalluru return rc; 314662e4d438SSudarsana Reddy Kalluru } 314762e4d438SSudarsana Reddy Kalluru 3148b51dab46SSudarsana Reddy Kalluru int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3149b51dab46SSudarsana Reddy Kalluru u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 3150b51dab46SSudarsana Reddy Kalluru { 3151b51dab46SSudarsana Reddy Kalluru u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 3152b51dab46SSudarsana Reddy Kalluru u32 resp, param; 3153b51dab46SSudarsana Reddy Kalluru int rc; 3154b51dab46SSudarsana Reddy Kalluru 3155b51dab46SSudarsana Reddy Kalluru nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 3156b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 3157b51dab46SSudarsana Reddy Kalluru nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 3158b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 3159b51dab46SSudarsana Reddy Kalluru 3160b51dab46SSudarsana Reddy Kalluru addr = offset; 3161b51dab46SSudarsana Reddy Kalluru offset = 0; 3162b51dab46SSudarsana Reddy Kalluru bytes_left = len; 3163b51dab46SSudarsana Reddy Kalluru while (bytes_left > 0) { 3164b51dab46SSudarsana Reddy Kalluru bytes_to_copy = min_t(u32, bytes_left, 3165b51dab46SSudarsana Reddy Kalluru MAX_I2C_TRANSACTION_SIZE); 3166b51dab46SSudarsana Reddy Kalluru nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 3167b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 3168b51dab46SSudarsana Reddy Kalluru nvm_offset |= ((addr + offset) << 3169b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 3170b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 3171b51dab46SSudarsana Reddy Kalluru nvm_offset |= (bytes_to_copy << 3172b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 3173b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 3174b51dab46SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 3175b51dab46SSudarsana Reddy Kalluru DRV_MSG_CODE_TRANSCEIVER_READ, 3176b51dab46SSudarsana Reddy Kalluru nvm_offset, &resp, ¶m, &buf_size, 3177b51dab46SSudarsana Reddy Kalluru (u32 *)(p_buf + offset)); 3178b51dab46SSudarsana Reddy Kalluru if (rc) { 3179b51dab46SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 3180b51dab46SSudarsana Reddy Kalluru "Failed to send a transceiver read command to the MFW. rc = %d.\n", 3181b51dab46SSudarsana Reddy Kalluru rc); 3182b51dab46SSudarsana Reddy Kalluru return rc; 3183b51dab46SSudarsana Reddy Kalluru } 3184b51dab46SSudarsana Reddy Kalluru 3185b51dab46SSudarsana Reddy Kalluru if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 3186b51dab46SSudarsana Reddy Kalluru return -ENODEV; 3187b51dab46SSudarsana Reddy Kalluru else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 3188b51dab46SSudarsana Reddy Kalluru return -EINVAL; 3189b51dab46SSudarsana Reddy Kalluru 3190b51dab46SSudarsana Reddy Kalluru offset += buf_size; 3191b51dab46SSudarsana Reddy Kalluru bytes_left -= buf_size; 3192b51dab46SSudarsana Reddy Kalluru } 3193b51dab46SSudarsana Reddy Kalluru 3194b51dab46SSudarsana Reddy Kalluru return 0; 3195b51dab46SSudarsana Reddy Kalluru } 3196b51dab46SSudarsana Reddy Kalluru 319703dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 319803dc76caSSudarsana Reddy Kalluru { 319903dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 320003dc76caSSudarsana Reddy Kalluru int rc = 0; 320103dc76caSSudarsana Reddy Kalluru 320203dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 320303dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 320403dc76caSSudarsana Reddy Kalluru 320503dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 320603dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 320703dc76caSSudarsana Reddy Kalluru 320803dc76caSSudarsana Reddy Kalluru if (rc) 320903dc76caSSudarsana Reddy Kalluru return rc; 321003dc76caSSudarsana Reddy Kalluru 321103dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 321203dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 321303dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 321403dc76caSSudarsana Reddy Kalluru 321503dc76caSSudarsana Reddy Kalluru return rc; 321603dc76caSSudarsana Reddy Kalluru } 321703dc76caSSudarsana Reddy Kalluru 321803dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 321903dc76caSSudarsana Reddy Kalluru { 322003dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 322103dc76caSSudarsana Reddy Kalluru int rc = 0; 322203dc76caSSudarsana Reddy Kalluru 322303dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 322403dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 322503dc76caSSudarsana Reddy Kalluru 322603dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 322703dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 322803dc76caSSudarsana Reddy Kalluru 322903dc76caSSudarsana Reddy Kalluru if (rc) 323003dc76caSSudarsana Reddy Kalluru return rc; 323103dc76caSSudarsana Reddy Kalluru 323203dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 323303dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 323403dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 323503dc76caSSudarsana Reddy Kalluru 323603dc76caSSudarsana Reddy Kalluru return rc; 323703dc76caSSudarsana Reddy Kalluru } 32387a4b21b7SMintz, Yuval 323943645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 32407a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 32417a4b21b7SMintz, Yuval u32 *num_images) 32427a4b21b7SMintz, Yuval { 32437a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 32447a4b21b7SMintz, Yuval int rc = 0; 32457a4b21b7SMintz, Yuval 32467a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 32477a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 32487a4b21b7SMintz, Yuval 32497a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 32507a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 32517a4b21b7SMintz, Yuval if (rc) 32527a4b21b7SMintz, Yuval return rc; 32537a4b21b7SMintz, Yuval 32547a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 32557a4b21b7SMintz, Yuval rc = -EINVAL; 32567a4b21b7SMintz, Yuval 32577a4b21b7SMintz, Yuval return rc; 32587a4b21b7SMintz, Yuval } 32597a4b21b7SMintz, Yuval 326043645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 32617a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 32627a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 32637a4b21b7SMintz, Yuval u32 image_index) 32647a4b21b7SMintz, Yuval { 32657a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 32667a4b21b7SMintz, Yuval int rc; 32677a4b21b7SMintz, Yuval 32687a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 32697a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 32707a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 32717a4b21b7SMintz, Yuval 32727a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 32737a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 32747a4b21b7SMintz, Yuval &resp, &resp_param, 32757a4b21b7SMintz, Yuval &buf_size, 32767a4b21b7SMintz, Yuval (u32 *)p_image_att); 32777a4b21b7SMintz, Yuval if (rc) 32787a4b21b7SMintz, Yuval return rc; 32797a4b21b7SMintz, Yuval 32807a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 32817a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 32827a4b21b7SMintz, Yuval rc = -EINVAL; 32837a4b21b7SMintz, Yuval 32847a4b21b7SMintz, Yuval return rc; 32857a4b21b7SMintz, Yuval } 32862edbff8dSTomer Tayar 328743645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 328843645ce0SSudarsana Reddy Kalluru { 32895e7ba042SDenis Bolotin struct qed_nvm_image_info nvm_info; 329043645ce0SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 329143645ce0SSudarsana Reddy Kalluru int rc; 329243645ce0SSudarsana Reddy Kalluru u32 i; 329343645ce0SSudarsana Reddy Kalluru 32945e7ba042SDenis Bolotin if (p_hwfn->nvm_info.valid) 32955e7ba042SDenis Bolotin return 0; 32965e7ba042SDenis Bolotin 329743645ce0SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 329843645ce0SSudarsana Reddy Kalluru if (!p_ptt) { 329943645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "failed to acquire ptt\n"); 330043645ce0SSudarsana Reddy Kalluru return -EBUSY; 330143645ce0SSudarsana Reddy Kalluru } 330243645ce0SSudarsana Reddy Kalluru 330343645ce0SSudarsana Reddy Kalluru /* Acquire from MFW the amount of available images */ 33045e7ba042SDenis Bolotin nvm_info.num_images = 0; 330543645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 33065e7ba042SDenis Bolotin p_ptt, &nvm_info.num_images); 330743645ce0SSudarsana Reddy Kalluru if (rc == -EOPNOTSUPP) { 330843645ce0SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 330943645ce0SSudarsana Reddy Kalluru goto out; 33105e7ba042SDenis Bolotin } else if (rc || !nvm_info.num_images) { 331143645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Failed getting number of images\n"); 331243645ce0SSudarsana Reddy Kalluru goto err0; 331343645ce0SSudarsana Reddy Kalluru } 331443645ce0SSudarsana Reddy Kalluru 33155e7ba042SDenis Bolotin nvm_info.image_att = kmalloc_array(nvm_info.num_images, 331643645ce0SSudarsana Reddy Kalluru sizeof(struct bist_nvm_image_att), 331743645ce0SSudarsana Reddy Kalluru GFP_KERNEL); 33185e7ba042SDenis Bolotin if (!nvm_info.image_att) { 331943645ce0SSudarsana Reddy Kalluru rc = -ENOMEM; 332043645ce0SSudarsana Reddy Kalluru goto err0; 332143645ce0SSudarsana Reddy Kalluru } 332243645ce0SSudarsana Reddy Kalluru 332343645ce0SSudarsana Reddy Kalluru /* Iterate over images and get their attributes */ 33245e7ba042SDenis Bolotin for (i = 0; i < nvm_info.num_images; i++) { 332543645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 33265e7ba042SDenis Bolotin &nvm_info.image_att[i], i); 332743645ce0SSudarsana Reddy Kalluru if (rc) { 332843645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, 332943645ce0SSudarsana Reddy Kalluru "Failed getting image index %d attributes\n", i); 333043645ce0SSudarsana Reddy Kalluru goto err1; 333143645ce0SSudarsana Reddy Kalluru } 333243645ce0SSudarsana Reddy Kalluru 333343645ce0SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 33345e7ba042SDenis Bolotin nvm_info.image_att[i].len); 333543645ce0SSudarsana Reddy Kalluru } 333643645ce0SSudarsana Reddy Kalluru out: 33375e7ba042SDenis Bolotin /* Update hwfn's nvm_info */ 33385e7ba042SDenis Bolotin if (nvm_info.num_images) { 33395e7ba042SDenis Bolotin p_hwfn->nvm_info.num_images = nvm_info.num_images; 33405e7ba042SDenis Bolotin kfree(p_hwfn->nvm_info.image_att); 33415e7ba042SDenis Bolotin p_hwfn->nvm_info.image_att = nvm_info.image_att; 33425e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = true; 33435e7ba042SDenis Bolotin } 33445e7ba042SDenis Bolotin 334543645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 334643645ce0SSudarsana Reddy Kalluru return 0; 334743645ce0SSudarsana Reddy Kalluru 334843645ce0SSudarsana Reddy Kalluru err1: 33495e7ba042SDenis Bolotin kfree(nvm_info.image_att); 335043645ce0SSudarsana Reddy Kalluru err0: 335143645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 335243645ce0SSudarsana Reddy Kalluru return rc; 335343645ce0SSudarsana Reddy Kalluru } 335443645ce0SSudarsana Reddy Kalluru 335513cf8aabSSudarsana Reddy Kalluru void qed_mcp_nvm_info_free(struct qed_hwfn *p_hwfn) 335613cf8aabSSudarsana Reddy Kalluru { 335713cf8aabSSudarsana Reddy Kalluru kfree(p_hwfn->nvm_info.image_att); 335813cf8aabSSudarsana Reddy Kalluru p_hwfn->nvm_info.image_att = NULL; 335913cf8aabSSudarsana Reddy Kalluru p_hwfn->nvm_info.valid = false; 336013cf8aabSSudarsana Reddy Kalluru } 336113cf8aabSSudarsana Reddy Kalluru 33621ac4329aSDenis Bolotin int 336320675b37SMintz, Yuval qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 336420675b37SMintz, Yuval enum qed_nvm_images image_id, 336520675b37SMintz, Yuval struct qed_nvm_image_att *p_image_att) 336620675b37SMintz, Yuval { 336720675b37SMintz, Yuval enum nvm_image_type type; 336843645ce0SSudarsana Reddy Kalluru u32 i; 336920675b37SMintz, Yuval 337020675b37SMintz, Yuval /* Translate image_id into MFW definitions */ 337120675b37SMintz, Yuval switch (image_id) { 337220675b37SMintz, Yuval case QED_NVM_IMAGE_ISCSI_CFG: 337320675b37SMintz, Yuval type = NVM_TYPE_ISCSI_CFG; 337420675b37SMintz, Yuval break; 337520675b37SMintz, Yuval case QED_NVM_IMAGE_FCOE_CFG: 337620675b37SMintz, Yuval type = NVM_TYPE_FCOE_CFG; 337720675b37SMintz, Yuval break; 33788a52bbabSMichal Kalderon case QED_NVM_IMAGE_MDUMP: 33798a52bbabSMichal Kalderon type = NVM_TYPE_MDUMP; 33808a52bbabSMichal Kalderon break; 33811ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_CFG1: 33821ac4329aSDenis Bolotin type = NVM_TYPE_NVM_CFG1; 33831ac4329aSDenis Bolotin break; 33841ac4329aSDenis Bolotin case QED_NVM_IMAGE_DEFAULT_CFG: 33851ac4329aSDenis Bolotin type = NVM_TYPE_DEFAULT_CFG; 33861ac4329aSDenis Bolotin break; 33871ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_META: 33881ac4329aSDenis Bolotin type = NVM_TYPE_META; 33891ac4329aSDenis Bolotin break; 339020675b37SMintz, Yuval default: 339120675b37SMintz, Yuval DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 339220675b37SMintz, Yuval image_id); 339320675b37SMintz, Yuval return -EINVAL; 339420675b37SMintz, Yuval } 339520675b37SMintz, Yuval 33965e7ba042SDenis Bolotin qed_mcp_nvm_info_populate(p_hwfn); 339743645ce0SSudarsana Reddy Kalluru for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 339843645ce0SSudarsana Reddy Kalluru if (type == p_hwfn->nvm_info.image_att[i].image_type) 339920675b37SMintz, Yuval break; 340043645ce0SSudarsana Reddy Kalluru if (i == p_hwfn->nvm_info.num_images) { 340120675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 340220675b37SMintz, Yuval "Failed to find nvram image of type %08x\n", 340320675b37SMintz, Yuval image_id); 340443645ce0SSudarsana Reddy Kalluru return -ENOENT; 340520675b37SMintz, Yuval } 340620675b37SMintz, Yuval 340743645ce0SSudarsana Reddy Kalluru p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 340843645ce0SSudarsana Reddy Kalluru p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 340920675b37SMintz, Yuval 341020675b37SMintz, Yuval return 0; 341120675b37SMintz, Yuval } 341220675b37SMintz, Yuval 341320675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 341420675b37SMintz, Yuval enum qed_nvm_images image_id, 341520675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len) 341620675b37SMintz, Yuval { 341720675b37SMintz, Yuval struct qed_nvm_image_att image_att; 341820675b37SMintz, Yuval int rc; 341920675b37SMintz, Yuval 342020675b37SMintz, Yuval memset(p_buffer, 0, buffer_len); 342120675b37SMintz, Yuval 3422b60bfdfeSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 342320675b37SMintz, Yuval if (rc) 342420675b37SMintz, Yuval return rc; 342520675b37SMintz, Yuval 342620675b37SMintz, Yuval /* Validate sizes - both the image's and the supplied buffer's */ 342720675b37SMintz, Yuval if (image_att.length <= 4) { 342820675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 342920675b37SMintz, Yuval "Image [%d] is too small - only %d bytes\n", 343020675b37SMintz, Yuval image_id, image_att.length); 343120675b37SMintz, Yuval return -EINVAL; 343220675b37SMintz, Yuval } 343320675b37SMintz, Yuval 343420675b37SMintz, Yuval if (image_att.length > buffer_len) { 343520675b37SMintz, Yuval DP_VERBOSE(p_hwfn, 343620675b37SMintz, Yuval QED_MSG_STORAGE, 343720675b37SMintz, Yuval "Image [%d] is too big - %08x bytes where only %08x are available\n", 343820675b37SMintz, Yuval image_id, image_att.length, buffer_len); 343920675b37SMintz, Yuval return -ENOMEM; 344020675b37SMintz, Yuval } 344120675b37SMintz, Yuval 344220675b37SMintz, Yuval return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 344320675b37SMintz, Yuval p_buffer, image_att.length); 344420675b37SMintz, Yuval } 344520675b37SMintz, Yuval 34469c8517c4STomer Tayar static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 34479c8517c4STomer Tayar { 34489c8517c4STomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 34499c8517c4STomer Tayar 34509c8517c4STomer Tayar switch (res_id) { 34519c8517c4STomer Tayar case QED_SB: 34529c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 34539c8517c4STomer Tayar break; 34549c8517c4STomer Tayar case QED_L2_QUEUE: 34559c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 34569c8517c4STomer Tayar break; 34579c8517c4STomer Tayar case QED_VPORT: 34589c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 34599c8517c4STomer Tayar break; 34609c8517c4STomer Tayar case QED_RSS_ENG: 34619c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 34629c8517c4STomer Tayar break; 34639c8517c4STomer Tayar case QED_PQ: 34649c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 34659c8517c4STomer Tayar break; 34669c8517c4STomer Tayar case QED_RL: 34679c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 34689c8517c4STomer Tayar break; 34699c8517c4STomer Tayar case QED_MAC: 34709c8517c4STomer Tayar case QED_VLAN: 34719c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 34729c8517c4STomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 34739c8517c4STomer Tayar break; 34749c8517c4STomer Tayar case QED_ILT: 34759c8517c4STomer Tayar mfw_res_id = RESOURCE_ILT_E; 34769c8517c4STomer Tayar break; 3477997af5dfSMichal Kalderon case QED_LL2_RAM_QUEUE: 34789c8517c4STomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 34799c8517c4STomer Tayar break; 3480997af5dfSMichal Kalderon case QED_LL2_CTX_QUEUE: 3481997af5dfSMichal Kalderon mfw_res_id = RESOURCE_LL2_CQS_E; 3482997af5dfSMichal Kalderon break; 34839c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 34849c8517c4STomer Tayar case QED_CMDQS_CQS: 34859c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 34869c8517c4STomer Tayar mfw_res_id = RESOURCE_CQS_E; 34879c8517c4STomer Tayar break; 34889c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 34899c8517c4STomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 34909c8517c4STomer Tayar break; 34919c8517c4STomer Tayar case QED_BDQ: 34929c8517c4STomer Tayar mfw_res_id = RESOURCE_BDQ_E; 34939c8517c4STomer Tayar break; 34949c8517c4STomer Tayar default: 34959c8517c4STomer Tayar break; 34969c8517c4STomer Tayar } 34979c8517c4STomer Tayar 34989c8517c4STomer Tayar return mfw_res_id; 34999c8517c4STomer Tayar } 35009c8517c4STomer Tayar 35019c8517c4STomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 2 35022edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 35032edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 35042edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 35052edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 35062edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 35072edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 35089c8517c4STomer Tayar 35099c8517c4STomer Tayar struct qed_resc_alloc_in_params { 35109c8517c4STomer Tayar u32 cmd; 35119c8517c4STomer Tayar enum qed_resources res_id; 35129c8517c4STomer Tayar u32 resc_max_val; 35139c8517c4STomer Tayar }; 35149c8517c4STomer Tayar 35159c8517c4STomer Tayar struct qed_resc_alloc_out_params { 35169c8517c4STomer Tayar u32 mcp_resp; 35179c8517c4STomer Tayar u32 mcp_param; 35189c8517c4STomer Tayar u32 resc_num; 35199c8517c4STomer Tayar u32 resc_start; 35209c8517c4STomer Tayar u32 vf_resc_num; 35219c8517c4STomer Tayar u32 vf_resc_start; 35229c8517c4STomer Tayar u32 flags; 35239c8517c4STomer Tayar }; 35249c8517c4STomer Tayar 35259c8517c4STomer Tayar static int 35269c8517c4STomer Tayar qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 35272edbff8dSTomer Tayar struct qed_ptt *p_ptt, 35289c8517c4STomer Tayar struct qed_resc_alloc_in_params *p_in_params, 35299c8517c4STomer Tayar struct qed_resc_alloc_out_params *p_out_params) 35302edbff8dSTomer Tayar { 35312edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 35329c8517c4STomer Tayar struct resource_info mfw_resc_info; 35332edbff8dSTomer Tayar int rc; 35342edbff8dSTomer Tayar 35359c8517c4STomer Tayar memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 3536bb480242SMintz, Yuval 35379c8517c4STomer Tayar mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 35389c8517c4STomer Tayar if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 35399c8517c4STomer Tayar DP_ERR(p_hwfn, 35409c8517c4STomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 35419c8517c4STomer Tayar p_in_params->res_id, 35429c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id)); 35439c8517c4STomer Tayar return -EINVAL; 35449c8517c4STomer Tayar } 35459c8517c4STomer Tayar 35469c8517c4STomer Tayar switch (p_in_params->cmd) { 35479c8517c4STomer Tayar case DRV_MSG_SET_RESOURCE_VALUE_MSG: 35489c8517c4STomer Tayar mfw_resc_info.size = p_in_params->resc_max_val; 3549df561f66SGustavo A. R. Silva fallthrough; 35509c8517c4STomer Tayar case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 35519c8517c4STomer Tayar break; 35529c8517c4STomer Tayar default: 35539c8517c4STomer Tayar DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 35549c8517c4STomer Tayar p_in_params->cmd); 35559c8517c4STomer Tayar return -EINVAL; 35569c8517c4STomer Tayar } 35579c8517c4STomer Tayar 35589c8517c4STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 35599c8517c4STomer Tayar mb_params.cmd = p_in_params->cmd; 35609c8517c4STomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 35619c8517c4STomer Tayar mb_params.p_data_src = &mfw_resc_info; 35629c8517c4STomer Tayar mb_params.data_src_size = sizeof(mfw_resc_info); 35639c8517c4STomer Tayar mb_params.p_data_dst = mb_params.p_data_src; 35649c8517c4STomer Tayar mb_params.data_dst_size = mb_params.data_src_size; 35659c8517c4STomer Tayar 35669c8517c4STomer Tayar DP_VERBOSE(p_hwfn, 35679c8517c4STomer Tayar QED_MSG_SP, 35689c8517c4STomer Tayar "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 35699c8517c4STomer Tayar p_in_params->cmd, 35709c8517c4STomer Tayar p_in_params->res_id, 35719c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id), 35729c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 35739c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 35749c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 35759c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 35769c8517c4STomer Tayar p_in_params->resc_max_val); 35779c8517c4STomer Tayar 35782edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 35792edbff8dSTomer Tayar if (rc) 35802edbff8dSTomer Tayar return rc; 35812edbff8dSTomer Tayar 35829c8517c4STomer Tayar p_out_params->mcp_resp = mb_params.mcp_resp; 35839c8517c4STomer Tayar p_out_params->mcp_param = mb_params.mcp_param; 35849c8517c4STomer Tayar p_out_params->resc_num = mfw_resc_info.size; 35859c8517c4STomer Tayar p_out_params->resc_start = mfw_resc_info.offset; 35869c8517c4STomer Tayar p_out_params->vf_resc_num = mfw_resc_info.vf_size; 35879c8517c4STomer Tayar p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 35889c8517c4STomer Tayar p_out_params->flags = mfw_resc_info.flags; 35892edbff8dSTomer Tayar 35902edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 35912edbff8dSTomer Tayar QED_MSG_SP, 35929c8517c4STomer Tayar "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 35939c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 35949c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 35959c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 35969c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 35979c8517c4STomer Tayar p_out_params->resc_num, 35989c8517c4STomer Tayar p_out_params->resc_start, 35999c8517c4STomer Tayar p_out_params->vf_resc_num, 36009c8517c4STomer Tayar p_out_params->vf_resc_start, p_out_params->flags); 36019c8517c4STomer Tayar 36029c8517c4STomer Tayar return 0; 36039c8517c4STomer Tayar } 36049c8517c4STomer Tayar 36059c8517c4STomer Tayar int 36069c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 36079c8517c4STomer Tayar struct qed_ptt *p_ptt, 36089c8517c4STomer Tayar enum qed_resources res_id, 36099c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 36109c8517c4STomer Tayar { 36119c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 36129c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 36139c8517c4STomer Tayar int rc; 36149c8517c4STomer Tayar 36159c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 36169c8517c4STomer Tayar in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 36179c8517c4STomer Tayar in_params.res_id = res_id; 36189c8517c4STomer Tayar in_params.resc_max_val = resc_max_val; 36199c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 36209c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 36219c8517c4STomer Tayar &out_params); 36229c8517c4STomer Tayar if (rc) 36239c8517c4STomer Tayar return rc; 36249c8517c4STomer Tayar 36259c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 36269c8517c4STomer Tayar 36279c8517c4STomer Tayar return 0; 36289c8517c4STomer Tayar } 36299c8517c4STomer Tayar 36309c8517c4STomer Tayar int 36319c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 36329c8517c4STomer Tayar struct qed_ptt *p_ptt, 36339c8517c4STomer Tayar enum qed_resources res_id, 36349c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 36359c8517c4STomer Tayar { 36369c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 36379c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 36389c8517c4STomer Tayar int rc; 36399c8517c4STomer Tayar 36409c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 36419c8517c4STomer Tayar in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 36429c8517c4STomer Tayar in_params.res_id = res_id; 36439c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 36449c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 36459c8517c4STomer Tayar &out_params); 36469c8517c4STomer Tayar if (rc) 36479c8517c4STomer Tayar return rc; 36489c8517c4STomer Tayar 36499c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 36509c8517c4STomer Tayar 36519c8517c4STomer Tayar if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 36529c8517c4STomer Tayar *p_resc_num = out_params.resc_num; 36539c8517c4STomer Tayar *p_resc_start = out_params.resc_start; 36549c8517c4STomer Tayar } 36552edbff8dSTomer Tayar 36562edbff8dSTomer Tayar return 0; 36572edbff8dSTomer Tayar } 365818a69e36SMintz, Yuval 365918a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 366018a69e36SMintz, Yuval { 366118a69e36SMintz, Yuval u32 mcp_resp, mcp_param; 366218a69e36SMintz, Yuval 366318a69e36SMintz, Yuval return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 366418a69e36SMintz, Yuval &mcp_resp, &mcp_param); 366518a69e36SMintz, Yuval } 366695691c9cSTomer Tayar 366795691c9cSTomer Tayar static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 366895691c9cSTomer Tayar struct qed_ptt *p_ptt, 366995691c9cSTomer Tayar u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 367095691c9cSTomer Tayar { 367195691c9cSTomer Tayar int rc; 367295691c9cSTomer Tayar 367395691c9cSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 367495691c9cSTomer Tayar p_mcp_resp, p_mcp_param); 367595691c9cSTomer Tayar if (rc) 367695691c9cSTomer Tayar return rc; 367795691c9cSTomer Tayar 367895691c9cSTomer Tayar if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 367995691c9cSTomer Tayar DP_INFO(p_hwfn, 368095691c9cSTomer Tayar "The resource command is unsupported by the MFW\n"); 368195691c9cSTomer Tayar return -EINVAL; 368295691c9cSTomer Tayar } 368395691c9cSTomer Tayar 368495691c9cSTomer Tayar if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 368595691c9cSTomer Tayar u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 368695691c9cSTomer Tayar 368795691c9cSTomer Tayar DP_NOTICE(p_hwfn, 368895691c9cSTomer Tayar "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 368995691c9cSTomer Tayar param, opcode); 369095691c9cSTomer Tayar return -EINVAL; 369195691c9cSTomer Tayar } 369295691c9cSTomer Tayar 369395691c9cSTomer Tayar return rc; 369495691c9cSTomer Tayar } 369595691c9cSTomer Tayar 3696bf774d14SYueHaibing static int 369795691c9cSTomer Tayar __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 369895691c9cSTomer Tayar struct qed_ptt *p_ptt, 369995691c9cSTomer Tayar struct qed_resc_lock_params *p_params) 370095691c9cSTomer Tayar { 370195691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 370295691c9cSTomer Tayar u8 opcode; 370395691c9cSTomer Tayar int rc; 370495691c9cSTomer Tayar 370595691c9cSTomer Tayar switch (p_params->timeout) { 370695691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_DEFAULT: 370795691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ; 370895691c9cSTomer Tayar p_params->timeout = 0; 370995691c9cSTomer Tayar break; 371095691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_NONE: 371195691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_WO_AGING; 371295691c9cSTomer Tayar p_params->timeout = 0; 371395691c9cSTomer Tayar break; 371495691c9cSTomer Tayar default: 371595691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_W_AGING; 371695691c9cSTomer Tayar break; 371795691c9cSTomer Tayar } 371895691c9cSTomer Tayar 371995691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 372095691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 372195691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 372295691c9cSTomer Tayar 372395691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 372495691c9cSTomer Tayar QED_MSG_SP, 372595691c9cSTomer Tayar "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 372695691c9cSTomer Tayar param, p_params->timeout, opcode, p_params->resource); 372795691c9cSTomer Tayar 372895691c9cSTomer Tayar /* Attempt to acquire the resource */ 372995691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 373095691c9cSTomer Tayar if (rc) 373195691c9cSTomer Tayar return rc; 373295691c9cSTomer Tayar 373395691c9cSTomer Tayar /* Analyze the response */ 373495691c9cSTomer Tayar p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 373595691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 373695691c9cSTomer Tayar 373795691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 373895691c9cSTomer Tayar QED_MSG_SP, 373995691c9cSTomer Tayar "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 374095691c9cSTomer Tayar mcp_param, opcode, p_params->owner); 374195691c9cSTomer Tayar 374295691c9cSTomer Tayar switch (opcode) { 374395691c9cSTomer Tayar case RESOURCE_OPCODE_GNT: 374495691c9cSTomer Tayar p_params->b_granted = true; 374595691c9cSTomer Tayar break; 374695691c9cSTomer Tayar case RESOURCE_OPCODE_BUSY: 374795691c9cSTomer Tayar p_params->b_granted = false; 374895691c9cSTomer Tayar break; 374995691c9cSTomer Tayar default: 375095691c9cSTomer Tayar DP_NOTICE(p_hwfn, 375195691c9cSTomer Tayar "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 375295691c9cSTomer Tayar mcp_param, opcode); 375395691c9cSTomer Tayar return -EINVAL; 375495691c9cSTomer Tayar } 375595691c9cSTomer Tayar 375695691c9cSTomer Tayar return 0; 375795691c9cSTomer Tayar } 375895691c9cSTomer Tayar 375995691c9cSTomer Tayar int 376095691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 376195691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 376295691c9cSTomer Tayar { 376395691c9cSTomer Tayar u32 retry_cnt = 0; 376495691c9cSTomer Tayar int rc; 376595691c9cSTomer Tayar 376695691c9cSTomer Tayar do { 376795691c9cSTomer Tayar /* No need for an interval before the first iteration */ 376895691c9cSTomer Tayar if (retry_cnt) { 376995691c9cSTomer Tayar if (p_params->sleep_b4_retry) { 377095691c9cSTomer Tayar u16 retry_interval_in_ms = 377195691c9cSTomer Tayar DIV_ROUND_UP(p_params->retry_interval, 377295691c9cSTomer Tayar 1000); 377395691c9cSTomer Tayar 377495691c9cSTomer Tayar msleep(retry_interval_in_ms); 377595691c9cSTomer Tayar } else { 377695691c9cSTomer Tayar udelay(p_params->retry_interval); 377795691c9cSTomer Tayar } 377895691c9cSTomer Tayar } 377995691c9cSTomer Tayar 378095691c9cSTomer Tayar rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 378195691c9cSTomer Tayar if (rc) 378295691c9cSTomer Tayar return rc; 378395691c9cSTomer Tayar 378495691c9cSTomer Tayar if (p_params->b_granted) 378595691c9cSTomer Tayar break; 378695691c9cSTomer Tayar } while (retry_cnt++ < p_params->retry_num); 378795691c9cSTomer Tayar 378895691c9cSTomer Tayar return 0; 378995691c9cSTomer Tayar } 379095691c9cSTomer Tayar 379195691c9cSTomer Tayar int 379295691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 379395691c9cSTomer Tayar struct qed_ptt *p_ptt, 379495691c9cSTomer Tayar struct qed_resc_unlock_params *p_params) 379595691c9cSTomer Tayar { 379695691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 379795691c9cSTomer Tayar u8 opcode; 379895691c9cSTomer Tayar int rc; 379995691c9cSTomer Tayar 380095691c9cSTomer Tayar opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 380195691c9cSTomer Tayar : RESOURCE_OPCODE_RELEASE; 380295691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 380395691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 380495691c9cSTomer Tayar 380595691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 380695691c9cSTomer Tayar "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 380795691c9cSTomer Tayar param, opcode, p_params->resource); 380895691c9cSTomer Tayar 380995691c9cSTomer Tayar /* Attempt to release the resource */ 381095691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 381195691c9cSTomer Tayar if (rc) 381295691c9cSTomer Tayar return rc; 381395691c9cSTomer Tayar 381495691c9cSTomer Tayar /* Analyze the response */ 381595691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 381695691c9cSTomer Tayar 381795691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 381895691c9cSTomer Tayar "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 381995691c9cSTomer Tayar mcp_param, opcode); 382095691c9cSTomer Tayar 382195691c9cSTomer Tayar switch (opcode) { 382295691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED_PREVIOUS: 382395691c9cSTomer Tayar DP_INFO(p_hwfn, 382495691c9cSTomer Tayar "Resource unlock request for an already released resource [%d]\n", 382595691c9cSTomer Tayar p_params->resource); 3826df561f66SGustavo A. R. Silva fallthrough; 382795691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED: 382895691c9cSTomer Tayar p_params->b_released = true; 382995691c9cSTomer Tayar break; 383095691c9cSTomer Tayar case RESOURCE_OPCODE_WRONG_OWNER: 383195691c9cSTomer Tayar p_params->b_released = false; 383295691c9cSTomer Tayar break; 383395691c9cSTomer Tayar default: 383495691c9cSTomer Tayar DP_NOTICE(p_hwfn, 383595691c9cSTomer Tayar "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 383695691c9cSTomer Tayar mcp_param, opcode); 383795691c9cSTomer Tayar return -EINVAL; 383895691c9cSTomer Tayar } 383995691c9cSTomer Tayar 384095691c9cSTomer Tayar return 0; 384195691c9cSTomer Tayar } 3842f470f22cSsudarsana.kalluru@cavium.com 3843f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3844f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 3845f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 3846f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent) 3847f470f22cSsudarsana.kalluru@cavium.com { 3848f470f22cSsudarsana.kalluru@cavium.com if (p_lock) { 3849f470f22cSsudarsana.kalluru@cavium.com memset(p_lock, 0, sizeof(*p_lock)); 3850f470f22cSsudarsana.kalluru@cavium.com 3851f470f22cSsudarsana.kalluru@cavium.com /* Permanent resources don't require aging, and there's no 3852f470f22cSsudarsana.kalluru@cavium.com * point in trying to acquire them more than once since it's 3853f470f22cSsudarsana.kalluru@cavium.com * unexpected another entity would release them. 3854f470f22cSsudarsana.kalluru@cavium.com */ 3855f470f22cSsudarsana.kalluru@cavium.com if (b_is_permanent) { 3856f470f22cSsudarsana.kalluru@cavium.com p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3857f470f22cSsudarsana.kalluru@cavium.com } else { 3858f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3859f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_interval = 3860f470f22cSsudarsana.kalluru@cavium.com QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3861f470f22cSsudarsana.kalluru@cavium.com p_lock->sleep_b4_retry = true; 3862f470f22cSsudarsana.kalluru@cavium.com } 3863f470f22cSsudarsana.kalluru@cavium.com 3864f470f22cSsudarsana.kalluru@cavium.com p_lock->resource = resource; 3865f470f22cSsudarsana.kalluru@cavium.com } 3866f470f22cSsudarsana.kalluru@cavium.com 3867f470f22cSsudarsana.kalluru@cavium.com if (p_unlock) { 3868f470f22cSsudarsana.kalluru@cavium.com memset(p_unlock, 0, sizeof(*p_unlock)); 3869f470f22cSsudarsana.kalluru@cavium.com p_unlock->resource = resource; 3870f470f22cSsudarsana.kalluru@cavium.com } 3871f470f22cSsudarsana.kalluru@cavium.com } 3872645874e5SSudarsana Reddy Kalluru 3873df9c716dSSudarsana Reddy Kalluru bool qed_mcp_is_smart_an_supported(struct qed_hwfn *p_hwfn) 3874df9c716dSSudarsana Reddy Kalluru { 3875df9c716dSSudarsana Reddy Kalluru return !!(p_hwfn->mcp_info->capabilities & 3876df9c716dSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ); 3877df9c716dSSudarsana Reddy Kalluru } 3878df9c716dSSudarsana Reddy Kalluru 3879645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3880645874e5SSudarsana Reddy Kalluru { 3881645874e5SSudarsana Reddy Kalluru u32 mcp_resp; 3882645874e5SSudarsana Reddy Kalluru int rc; 3883645874e5SSudarsana Reddy Kalluru 3884645874e5SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3885645874e5SSudarsana Reddy Kalluru 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3886645874e5SSudarsana Reddy Kalluru if (!rc) 3887645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3888645874e5SSudarsana Reddy Kalluru "MFW supported features: %08x\n", 3889645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->capabilities); 3890645874e5SSudarsana Reddy Kalluru 3891645874e5SSudarsana Reddy Kalluru return rc; 3892645874e5SSudarsana Reddy Kalluru } 3893645874e5SSudarsana Reddy Kalluru 3894645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3895645874e5SSudarsana Reddy Kalluru { 3896645874e5SSudarsana Reddy Kalluru u32 mcp_resp, mcp_param, features; 3897645874e5SSudarsana Reddy Kalluru 3898e40a826aSSudarsana Reddy Kalluru features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE | 3899ae7e6937SAlexander Lobakin DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK | 3900ae7e6937SAlexander Lobakin DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL; 3901645874e5SSudarsana Reddy Kalluru 390299785a87SAlexander Lobakin if (QED_IS_E5(p_hwfn->cdev)) 390399785a87SAlexander Lobakin features |= 390499785a87SAlexander Lobakin DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EXT_SPEED_FEC_CONTROL; 390599785a87SAlexander Lobakin 3906645874e5SSudarsana Reddy Kalluru return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3907645874e5SSudarsana Reddy Kalluru features, &mcp_resp, &mcp_param); 3908645874e5SSudarsana Reddy Kalluru } 390979284adeSMichal Kalderon 391079284adeSMichal Kalderon int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 391179284adeSMichal Kalderon { 391279284adeSMichal Kalderon struct qed_mcp_mb_params mb_params = {0}; 391379284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 391479284adeSMichal Kalderon u8 fir_valid, l2_valid; 391579284adeSMichal Kalderon int rc; 391679284adeSMichal Kalderon 391779284adeSMichal Kalderon mb_params.cmd = DRV_MSG_CODE_GET_ENGINE_CONFIG; 391879284adeSMichal Kalderon rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 391979284adeSMichal Kalderon if (rc) 392079284adeSMichal Kalderon return rc; 392179284adeSMichal Kalderon 392279284adeSMichal Kalderon if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 392379284adeSMichal Kalderon DP_INFO(p_hwfn, 392479284adeSMichal Kalderon "The get_engine_config command is unsupported by the MFW\n"); 392579284adeSMichal Kalderon return -EOPNOTSUPP; 392679284adeSMichal Kalderon } 392779284adeSMichal Kalderon 392879284adeSMichal Kalderon fir_valid = QED_MFW_GET_FIELD(mb_params.mcp_param, 392979284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID); 393079284adeSMichal Kalderon if (fir_valid) 393179284adeSMichal Kalderon cdev->fir_affin = 393279284adeSMichal Kalderon QED_MFW_GET_FIELD(mb_params.mcp_param, 393379284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE); 393479284adeSMichal Kalderon 393579284adeSMichal Kalderon l2_valid = QED_MFW_GET_FIELD(mb_params.mcp_param, 393679284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID); 393779284adeSMichal Kalderon if (l2_valid) 393879284adeSMichal Kalderon cdev->l2_affin_hint = 393979284adeSMichal Kalderon QED_MFW_GET_FIELD(mb_params.mcp_param, 394079284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE); 394179284adeSMichal Kalderon 394279284adeSMichal Kalderon DP_INFO(p_hwfn, 394379284adeSMichal Kalderon "Engine affinity config: FIR={valid %hhd, value %hhd}, L2_hint={valid %hhd, value %hhd}\n", 394479284adeSMichal Kalderon fir_valid, cdev->fir_affin, l2_valid, cdev->l2_affin_hint); 394579284adeSMichal Kalderon 394679284adeSMichal Kalderon return 0; 394779284adeSMichal Kalderon } 394879284adeSMichal Kalderon 394979284adeSMichal Kalderon int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 395079284adeSMichal Kalderon { 395179284adeSMichal Kalderon struct qed_mcp_mb_params mb_params = {0}; 395279284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 395379284adeSMichal Kalderon int rc; 395479284adeSMichal Kalderon 395579284adeSMichal Kalderon mb_params.cmd = DRV_MSG_CODE_GET_PPFID_BITMAP; 395679284adeSMichal Kalderon rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 395779284adeSMichal Kalderon if (rc) 395879284adeSMichal Kalderon return rc; 395979284adeSMichal Kalderon 396079284adeSMichal Kalderon if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 396179284adeSMichal Kalderon DP_INFO(p_hwfn, 396279284adeSMichal Kalderon "The get_ppfid_bitmap command is unsupported by the MFW\n"); 396379284adeSMichal Kalderon return -EOPNOTSUPP; 396479284adeSMichal Kalderon } 396579284adeSMichal Kalderon 396679284adeSMichal Kalderon cdev->ppfid_bitmap = QED_MFW_GET_FIELD(mb_params.mcp_param, 396779284adeSMichal Kalderon FW_MB_PARAM_PPFID_BITMAP); 396879284adeSMichal Kalderon 396979284adeSMichal Kalderon DP_VERBOSE(p_hwfn, QED_MSG_SP, "PPFID bitmap 0x%hhx\n", 397079284adeSMichal Kalderon cdev->ppfid_bitmap); 397179284adeSMichal Kalderon 397279284adeSMichal Kalderon return 0; 397379284adeSMichal Kalderon } 397438eabdf0SSudarsana Reddy Kalluru 39752d4c8495SSudarsana Reddy Kalluru int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 39762d4c8495SSudarsana Reddy Kalluru u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 39772d4c8495SSudarsana Reddy Kalluru u32 *p_len) 39782d4c8495SSudarsana Reddy Kalluru { 39792d4c8495SSudarsana Reddy Kalluru u32 mb_param = 0, resp, param; 39802d4c8495SSudarsana Reddy Kalluru int rc; 39812d4c8495SSudarsana Reddy Kalluru 39822d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id); 39832d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_INIT) 39842d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39852d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1); 39862d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_FREE) 39872d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39882d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1); 39892d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) { 39902d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39912d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1); 39922d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39932d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID, 39942d4c8495SSudarsana Reddy Kalluru entity_id); 39952d4c8495SSudarsana Reddy Kalluru } 39962d4c8495SSudarsana Reddy Kalluru 39972d4c8495SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 39982d4c8495SSudarsana Reddy Kalluru DRV_MSG_CODE_GET_NVM_CFG_OPTION, 39992d4c8495SSudarsana Reddy Kalluru mb_param, &resp, ¶m, p_len, (u32 *)p_buf); 40002d4c8495SSudarsana Reddy Kalluru 40012d4c8495SSudarsana Reddy Kalluru return rc; 40022d4c8495SSudarsana Reddy Kalluru } 40032d4c8495SSudarsana Reddy Kalluru 400438eabdf0SSudarsana Reddy Kalluru int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 400538eabdf0SSudarsana Reddy Kalluru u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 400638eabdf0SSudarsana Reddy Kalluru u32 len) 400738eabdf0SSudarsana Reddy Kalluru { 400838eabdf0SSudarsana Reddy Kalluru u32 mb_param = 0, resp, param; 400938eabdf0SSudarsana Reddy Kalluru 401038eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id); 401138eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ALL) 401238eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 401338eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ALL, 1); 401438eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_INIT) 401538eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 401638eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1); 401738eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_COMMIT) 401838eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 401938eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT, 1); 402038eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_FREE) 402138eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 402238eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1); 402338eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) { 402438eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 402538eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1); 402638eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 402738eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID, 402838eabdf0SSudarsana Reddy Kalluru entity_id); 402938eabdf0SSudarsana Reddy Kalluru } 403038eabdf0SSudarsana Reddy Kalluru 403138eabdf0SSudarsana Reddy Kalluru return qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, 403238eabdf0SSudarsana Reddy Kalluru DRV_MSG_CODE_SET_NVM_CFG_OPTION, 403338eabdf0SSudarsana Reddy Kalluru mb_param, &resp, ¶m, len, (u32 *)p_buf); 403438eabdf0SSudarsana Reddy Kalluru } 4035d8d6c5a7SIgor Russkikh 4036d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_SIZE MCP_DRV_NVM_BUF_LEN 4037d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_HEADER_SIZE sizeof(u32) 4038d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE \ 4039d8d6c5a7SIgor Russkikh (QED_MCP_DBG_DATA_MAX_SIZE - QED_MCP_DBG_DATA_MAX_HEADER_SIZE) 4040d8d6c5a7SIgor Russkikh 4041d8d6c5a7SIgor Russkikh static int 4042d8d6c5a7SIgor Russkikh __qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn, 4043d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, u8 *p_buf, u8 size) 4044d8d6c5a7SIgor Russkikh { 4045d8d6c5a7SIgor Russkikh struct qed_mcp_mb_params mb_params; 4046d8d6c5a7SIgor Russkikh int rc; 4047d8d6c5a7SIgor Russkikh 4048d8d6c5a7SIgor Russkikh if (size > QED_MCP_DBG_DATA_MAX_SIZE) { 4049d8d6c5a7SIgor Russkikh DP_ERR(p_hwfn, 4050d8d6c5a7SIgor Russkikh "Debug data size is %d while it should not exceed %d\n", 4051d8d6c5a7SIgor Russkikh size, QED_MCP_DBG_DATA_MAX_SIZE); 4052d8d6c5a7SIgor Russkikh return -EINVAL; 4053d8d6c5a7SIgor Russkikh } 4054d8d6c5a7SIgor Russkikh 4055d8d6c5a7SIgor Russkikh memset(&mb_params, 0, sizeof(mb_params)); 4056d8d6c5a7SIgor Russkikh mb_params.cmd = DRV_MSG_CODE_DEBUG_DATA_SEND; 4057d8d6c5a7SIgor Russkikh SET_MFW_FIELD(mb_params.param, DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE, size); 4058d8d6c5a7SIgor Russkikh mb_params.p_data_src = p_buf; 4059d8d6c5a7SIgor Russkikh mb_params.data_src_size = size; 4060d8d6c5a7SIgor Russkikh rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 4061d8d6c5a7SIgor Russkikh if (rc) 4062d8d6c5a7SIgor Russkikh return rc; 4063d8d6c5a7SIgor Russkikh 4064d8d6c5a7SIgor Russkikh if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 4065d8d6c5a7SIgor Russkikh DP_INFO(p_hwfn, 4066d8d6c5a7SIgor Russkikh "The DEBUG_DATA_SEND command is unsupported by the MFW\n"); 4067d8d6c5a7SIgor Russkikh return -EOPNOTSUPP; 4068d8d6c5a7SIgor Russkikh } else if (mb_params.mcp_resp == (u32)FW_MSG_CODE_DEBUG_NOT_ENABLED) { 4069d8d6c5a7SIgor Russkikh DP_INFO(p_hwfn, "The DEBUG_DATA_SEND command is not enabled\n"); 4070d8d6c5a7SIgor Russkikh return -EBUSY; 4071d8d6c5a7SIgor Russkikh } else if (mb_params.mcp_resp != (u32)FW_MSG_CODE_DEBUG_DATA_SEND_OK) { 4072d8d6c5a7SIgor Russkikh DP_NOTICE(p_hwfn, 4073d8d6c5a7SIgor Russkikh "Failed to send debug data to the MFW [resp 0x%08x]\n", 4074d8d6c5a7SIgor Russkikh mb_params.mcp_resp); 4075d8d6c5a7SIgor Russkikh return -EINVAL; 4076d8d6c5a7SIgor Russkikh } 4077d8d6c5a7SIgor Russkikh 4078d8d6c5a7SIgor Russkikh return 0; 4079d8d6c5a7SIgor Russkikh } 4080d8d6c5a7SIgor Russkikh 4081d8d6c5a7SIgor Russkikh enum qed_mcp_dbg_data_type { 4082d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_TYPE_RAW, 4083d8d6c5a7SIgor Russkikh }; 4084d8d6c5a7SIgor Russkikh 4085d8d6c5a7SIgor Russkikh /* Header format: [31:28] PFID, [27:20] flags, [19:12] type, [11:0] S/N */ 4086d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_SN_OFFSET 0 4087d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_SN_MASK 0x00000fff 4088d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_TYPE_OFFSET 12 4089d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_TYPE_MASK 0x000ff000 4090d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_OFFSET 20 4091d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_MASK 0x0ff00000 4092d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_PF_OFFSET 28 4093d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_PF_MASK 0xf0000000 4094d8d6c5a7SIgor Russkikh 4095d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_FIRST 0x1 4096d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_LAST 0x2 4097d8d6c5a7SIgor Russkikh 4098d8d6c5a7SIgor Russkikh static int 4099d8d6c5a7SIgor Russkikh qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn, 4100d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, 4101d8d6c5a7SIgor Russkikh enum qed_mcp_dbg_data_type type, u8 *p_buf, u32 size) 4102d8d6c5a7SIgor Russkikh { 4103d8d6c5a7SIgor Russkikh u8 raw_data[QED_MCP_DBG_DATA_MAX_SIZE], *p_tmp_buf = p_buf; 4104d8d6c5a7SIgor Russkikh u32 tmp_size = size, *p_header, *p_payload; 4105d8d6c5a7SIgor Russkikh u8 flags = 0; 4106d8d6c5a7SIgor Russkikh u16 seq; 4107d8d6c5a7SIgor Russkikh int rc; 4108d8d6c5a7SIgor Russkikh 4109d8d6c5a7SIgor Russkikh p_header = (u32 *)raw_data; 4110d8d6c5a7SIgor Russkikh p_payload = (u32 *)(raw_data + QED_MCP_DBG_DATA_MAX_HEADER_SIZE); 4111d8d6c5a7SIgor Russkikh 4112d8d6c5a7SIgor Russkikh seq = (u16)atomic_inc_return(&p_hwfn->mcp_info->dbg_data_seq); 4113d8d6c5a7SIgor Russkikh 4114d8d6c5a7SIgor Russkikh /* First chunk is marked as 'first' */ 4115d8d6c5a7SIgor Russkikh flags |= QED_MCP_DBG_DATA_HDR_FLAGS_FIRST; 4116d8d6c5a7SIgor Russkikh 4117d8d6c5a7SIgor Russkikh *p_header = 0; 4118d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_SN, seq); 4119d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_TYPE, type); 4120d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags); 4121d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_PF, p_hwfn->abs_pf_id); 4122d8d6c5a7SIgor Russkikh 4123d8d6c5a7SIgor Russkikh while (tmp_size > QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE) { 4124d8d6c5a7SIgor Russkikh memcpy(p_payload, p_tmp_buf, QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE); 4125d8d6c5a7SIgor Russkikh rc = __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data, 4126d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_MAX_SIZE); 4127d8d6c5a7SIgor Russkikh if (rc) 4128d8d6c5a7SIgor Russkikh return rc; 4129d8d6c5a7SIgor Russkikh 4130d8d6c5a7SIgor Russkikh /* Clear the 'first' marking after sending the first chunk */ 4131d8d6c5a7SIgor Russkikh if (p_tmp_buf == p_buf) { 4132d8d6c5a7SIgor Russkikh flags &= ~QED_MCP_DBG_DATA_HDR_FLAGS_FIRST; 4133d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, 4134d8d6c5a7SIgor Russkikh flags); 4135d8d6c5a7SIgor Russkikh } 4136d8d6c5a7SIgor Russkikh 4137d8d6c5a7SIgor Russkikh p_tmp_buf += QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE; 4138d8d6c5a7SIgor Russkikh tmp_size -= QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE; 4139d8d6c5a7SIgor Russkikh } 4140d8d6c5a7SIgor Russkikh 4141d8d6c5a7SIgor Russkikh /* Last chunk is marked as 'last' */ 4142d8d6c5a7SIgor Russkikh flags |= QED_MCP_DBG_DATA_HDR_FLAGS_LAST; 4143d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags); 4144d8d6c5a7SIgor Russkikh memcpy(p_payload, p_tmp_buf, tmp_size); 4145d8d6c5a7SIgor Russkikh 4146d8d6c5a7SIgor Russkikh /* Casting the left size to u8 is ok since at this point it is <= 32 */ 4147d8d6c5a7SIgor Russkikh return __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data, 4148d8d6c5a7SIgor Russkikh (u8)(QED_MCP_DBG_DATA_MAX_HEADER_SIZE + 4149d8d6c5a7SIgor Russkikh tmp_size)); 4150d8d6c5a7SIgor Russkikh } 4151d8d6c5a7SIgor Russkikh 4152d8d6c5a7SIgor Russkikh int 4153d8d6c5a7SIgor Russkikh qed_mcp_send_raw_debug_data(struct qed_hwfn *p_hwfn, 4154d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, u8 *p_buf, u32 size) 4155d8d6c5a7SIgor Russkikh { 4156d8d6c5a7SIgor Russkikh return qed_mcp_send_debug_data(p_hwfn, p_ptt, 4157d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_TYPE_RAW, p_buf, size); 4158d8d6c5a7SIgor Russkikh } 4159