1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/delay.h> 36fe56b9e6SYuval Mintz #include <linux/errno.h> 37fe56b9e6SYuval Mintz #include <linux/kernel.h> 38fe56b9e6SYuval Mintz #include <linux/slab.h> 395529bad9STomer Tayar #include <linux/spinlock.h> 40fe56b9e6SYuval Mintz #include <linux/string.h> 410fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 42fe56b9e6SYuval Mintz #include "qed.h" 43cac6f691SSudarsana Reddy Kalluru #include "qed_cxt.h" 4439651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 45fe56b9e6SYuval Mintz #include "qed_hsi.h" 46fe56b9e6SYuval Mintz #include "qed_hw.h" 47fe56b9e6SYuval Mintz #include "qed_mcp.h" 48fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 491408cc1fSYuval Mintz #include "qed_sriov.h" 501408cc1fSYuval Mintz 51eaa50fc5STomer Tayar #define QED_MCP_RESP_ITER_US 10 52fe56b9e6SYuval Mintz 53fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 54fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 57fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 58fe56b9e6SYuval Mintz _val) 59fe56b9e6SYuval Mintz 60fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 61fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 62fe56b9e6SYuval Mintz 63fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 64fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 65fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 66fe56b9e6SYuval Mintz 67fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 68fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 69fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 70fe56b9e6SYuval Mintz 71fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 72fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 73fe56b9e6SYuval Mintz 74fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 77fe56b9e6SYuval Mintz { 78fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 79fe56b9e6SYuval Mintz return false; 80fe56b9e6SYuval Mintz return true; 81fe56b9e6SYuval Mintz } 82fe56b9e6SYuval Mintz 831a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 84fe56b9e6SYuval Mintz { 85fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 86fe56b9e6SYuval Mintz PUBLIC_PORT); 87fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 88fe56b9e6SYuval Mintz 89fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 90fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 91fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 92fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 93fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 94fe56b9e6SYuval Mintz } 95fe56b9e6SYuval Mintz 961a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 97fe56b9e6SYuval Mintz { 98fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 99fe56b9e6SYuval Mintz u32 tmp, i; 100fe56b9e6SYuval Mintz 101fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 102fe56b9e6SYuval Mintz return; 103fe56b9e6SYuval Mintz 104fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 105fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 106fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 107fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 108fe56b9e6SYuval Mintz 109fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 110fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 111fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 112fe56b9e6SYuval Mintz } 113fe56b9e6SYuval Mintz } 114fe56b9e6SYuval Mintz 1154ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 1164ed1eea8STomer Tayar struct list_head list; 1174ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 1184ed1eea8STomer Tayar u16 expected_seq_num; 1194ed1eea8STomer Tayar bool b_is_completed; 1204ed1eea8STomer Tayar }; 1214ed1eea8STomer Tayar 1224ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1234ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1244ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1254ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1264ed1eea8STomer Tayar u16 expected_seq_num) 1274ed1eea8STomer Tayar { 1284ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1294ed1eea8STomer Tayar 1304ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1314ed1eea8STomer Tayar if (!p_cmd_elem) 1324ed1eea8STomer Tayar goto out; 1334ed1eea8STomer Tayar 1344ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1354ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1364ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1374ed1eea8STomer Tayar out: 1384ed1eea8STomer Tayar return p_cmd_elem; 1394ed1eea8STomer Tayar } 1404ed1eea8STomer Tayar 1414ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1424ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1434ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1444ed1eea8STomer Tayar { 1454ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1464ed1eea8STomer Tayar kfree(p_cmd_elem); 1474ed1eea8STomer Tayar } 1484ed1eea8STomer Tayar 1494ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1504ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1514ed1eea8STomer Tayar u16 seq_num) 1524ed1eea8STomer Tayar { 1534ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1544ed1eea8STomer Tayar 1554ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1564ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1574ed1eea8STomer Tayar return p_cmd_elem; 1584ed1eea8STomer Tayar } 1594ed1eea8STomer Tayar 1604ed1eea8STomer Tayar return NULL; 1614ed1eea8STomer Tayar } 1624ed1eea8STomer Tayar 163fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 164fe56b9e6SYuval Mintz { 165fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1664ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1674ed1eea8STomer Tayar 168fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 169fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1704ed1eea8STomer Tayar 1714ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1724ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1734ed1eea8STomer Tayar p_tmp, 1744ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1754ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 176fe56b9e6SYuval Mintz } 1774ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1784ed1eea8STomer Tayar } 1794ed1eea8STomer Tayar 180fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 1813587cb87STomer Tayar p_hwfn->mcp_info = NULL; 182fe56b9e6SYuval Mintz 183fe56b9e6SYuval Mintz return 0; 184fe56b9e6SYuval Mintz } 185fe56b9e6SYuval Mintz 186f00d25f3STomer Tayar /* Maximum of 1 sec to wait for the SHMEM ready indication */ 187f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_MAX_RETRIES 20 188f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_ITER_MS 50 189f00d25f3STomer Tayar 1901a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 191fe56b9e6SYuval Mintz { 192fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 193f00d25f3STomer Tayar u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES; 194f00d25f3STomer Tayar u8 msec = QED_MCP_SHMEM_RDY_ITER_MS; 195fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 196fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 197fe56b9e6SYuval Mintz 198fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 199f00d25f3STomer Tayar if (!p_info->public_base) { 200f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 201f00d25f3STomer Tayar "The address of the MCP scratch-pad is not configured\n"); 202f00d25f3STomer Tayar return -EINVAL; 203f00d25f3STomer Tayar } 204fe56b9e6SYuval Mintz 205fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 206fe56b9e6SYuval Mintz 207f00d25f3STomer Tayar /* Get the MFW MB address and number of supported messages */ 208f00d25f3STomer Tayar mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 209f00d25f3STomer Tayar SECTION_OFFSIZE_ADDR(p_info->public_base, 210f00d25f3STomer Tayar PUBLIC_MFW_MB)); 211f00d25f3STomer Tayar p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 212f00d25f3STomer Tayar p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, 213f00d25f3STomer Tayar p_info->mfw_mb_addr + 214f00d25f3STomer Tayar offsetof(struct public_mfw_mb, 215f00d25f3STomer Tayar sup_msgs)); 216f00d25f3STomer Tayar 217f00d25f3STomer Tayar /* The driver can notify that there was an MCP reset, and might read the 218f00d25f3STomer Tayar * SHMEM values before the MFW has completed initializing them. 219f00d25f3STomer Tayar * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a 220f00d25f3STomer Tayar * data ready indication. 221f00d25f3STomer Tayar */ 222f00d25f3STomer Tayar while (!p_info->mfw_mb_length && --cnt) { 223f00d25f3STomer Tayar msleep(msec); 224f00d25f3STomer Tayar p_info->mfw_mb_length = 225f00d25f3STomer Tayar (u16)qed_rd(p_hwfn, p_ptt, 226f00d25f3STomer Tayar p_info->mfw_mb_addr + 227f00d25f3STomer Tayar offsetof(struct public_mfw_mb, sup_msgs)); 228f00d25f3STomer Tayar } 229f00d25f3STomer Tayar 230f00d25f3STomer Tayar if (!cnt) { 231f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 232f00d25f3STomer Tayar "Failed to get the SHMEM ready notification after %d msec\n", 233f00d25f3STomer Tayar QED_MCP_SHMEM_RDY_MAX_RETRIES * msec); 234f00d25f3STomer Tayar return -EBUSY; 235f00d25f3STomer Tayar } 236f00d25f3STomer Tayar 237fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 238fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 239fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 240fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 241fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 242fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 243fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 244fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 245fe56b9e6SYuval Mintz 246fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 247fe56b9e6SYuval Mintz * the first command 248fe56b9e6SYuval Mintz */ 249fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 250fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 251fe56b9e6SYuval Mintz 252fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 253fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 254fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 255fe56b9e6SYuval Mintz 2564ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 257fe56b9e6SYuval Mintz 258fe56b9e6SYuval Mintz return 0; 259fe56b9e6SYuval Mintz } 260fe56b9e6SYuval Mintz 2611a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 262fe56b9e6SYuval Mintz { 263fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 264fe56b9e6SYuval Mintz u32 size; 265fe56b9e6SYuval Mintz 266fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 26760fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 268fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 269fe56b9e6SYuval Mintz goto err; 270fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 271fe56b9e6SYuval Mintz 2724ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2734ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2744ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2754ed1eea8STomer Tayar 2764ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2774ed1eea8STomer Tayar 278fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 279fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 280fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 281fe56b9e6SYuval Mintz * the MCP is not initialized 282fe56b9e6SYuval Mintz */ 283fe56b9e6SYuval Mintz return 0; 284fe56b9e6SYuval Mintz } 285fe56b9e6SYuval Mintz 286fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 28760fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 28883aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 289eb2a6b80SChristophe Jaillet if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 290fe56b9e6SYuval Mintz goto err; 291fe56b9e6SYuval Mintz 292fe56b9e6SYuval Mintz return 0; 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz err: 295fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 296fe56b9e6SYuval Mintz return -ENOMEM; 297fe56b9e6SYuval Mintz } 298fe56b9e6SYuval Mintz 2994ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 3004ed1eea8STomer Tayar struct qed_ptt *p_ptt) 3015529bad9STomer Tayar { 3024ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3035529bad9STomer Tayar 3044ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 3054ed1eea8STomer Tayar * time and now. 3065529bad9STomer Tayar */ 3074ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 3084ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 3094ed1eea8STomer Tayar QED_MSG_SP, 3104ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 3114ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 3125529bad9STomer Tayar 3134ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 3144ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 3155529bad9STomer Tayar } 3165529bad9STomer Tayar } 3175529bad9STomer Tayar 3181a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 319fe56b9e6SYuval Mintz { 320eaa50fc5STomer Tayar u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0; 321fe56b9e6SYuval Mintz int rc = 0; 322fe56b9e6SYuval Mintz 323b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 324b310974eSTomer Tayar DP_NOTICE(p_hwfn, 325b310974eSTomer Tayar "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n"); 326b310974eSTomer Tayar return -EBUSY; 327b310974eSTomer Tayar } 328b310974eSTomer Tayar 3294ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 3304ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 3314ed1eea8STomer Tayar 3324ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3335529bad9STomer Tayar 334fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 3354ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 3364ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 3374ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 338fe56b9e6SYuval Mintz 339fe56b9e6SYuval Mintz do { 340fe56b9e6SYuval Mintz /* Wait for MFW response */ 341fe56b9e6SYuval Mintz udelay(delay); 342fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 343fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 344fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 345fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 346fe56b9e6SYuval Mintz 347fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 348fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 349fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 350fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 351fe56b9e6SYuval Mintz } else { 352fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 353fe56b9e6SYuval Mintz rc = -EAGAIN; 354fe56b9e6SYuval Mintz } 355fe56b9e6SYuval Mintz 3564ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3575529bad9STomer Tayar 358fe56b9e6SYuval Mintz return rc; 359fe56b9e6SYuval Mintz } 360fe56b9e6SYuval Mintz 3614ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3624ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 363fe56b9e6SYuval Mintz { 3644ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3654ed1eea8STomer Tayar 3664ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3674ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3684ed1eea8STomer Tayar */ 3694ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3704ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3714ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3724ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3734ed1eea8STomer Tayar } 3744ed1eea8STomer Tayar 3754ed1eea8STomer Tayar return false; 3764ed1eea8STomer Tayar } 3774ed1eea8STomer Tayar 3784ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3794ed1eea8STomer Tayar static int 3804ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3814ed1eea8STomer Tayar { 3824ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3834ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3844ed1eea8STomer Tayar u32 mcp_resp; 3854ed1eea8STomer Tayar u16 seq_num; 3864ed1eea8STomer Tayar 3874ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3884ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3894ed1eea8STomer Tayar 3904ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3914ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3924ed1eea8STomer Tayar return -EAGAIN; 3934ed1eea8STomer Tayar 3944ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3954ed1eea8STomer Tayar if (!p_cmd_elem) { 3964ed1eea8STomer Tayar DP_ERR(p_hwfn, 3974ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 3984ed1eea8STomer Tayar seq_num); 3994ed1eea8STomer Tayar return -EINVAL; 4004ed1eea8STomer Tayar } 4014ed1eea8STomer Tayar 4024ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 4034ed1eea8STomer Tayar 4044ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 4054ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 4064ed1eea8STomer Tayar 4074ed1eea8STomer Tayar /* Get the MFW param */ 4084ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 4094ed1eea8STomer Tayar 4104ed1eea8STomer Tayar /* Get the union data */ 4112f67af8cSTomer Tayar if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 4124ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4134ed1eea8STomer Tayar offsetof(struct public_drv_mb, 4144ed1eea8STomer Tayar union_data); 4154ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 4162f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 4174ed1eea8STomer Tayar } 4184ed1eea8STomer Tayar 4194ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 4204ed1eea8STomer Tayar 4214ed1eea8STomer Tayar return 0; 4224ed1eea8STomer Tayar } 4234ed1eea8STomer Tayar 4244ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 4254ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4264ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4274ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4284ed1eea8STomer Tayar u16 seq_num) 4294ed1eea8STomer Tayar { 4304ed1eea8STomer Tayar union drv_union_data union_data; 4314ed1eea8STomer Tayar u32 union_data_addr; 4324ed1eea8STomer Tayar 4334ed1eea8STomer Tayar /* Set the union data */ 4344ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4354ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 4364ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 4372f67af8cSTomer Tayar if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 4384ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 4392f67af8cSTomer Tayar p_mb_params->data_src_size); 4404ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4414ed1eea8STomer Tayar sizeof(union_data)); 4424ed1eea8STomer Tayar 4434ed1eea8STomer Tayar /* Set the drv param */ 4444ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4454ed1eea8STomer Tayar 4464ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4474ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4484ed1eea8STomer Tayar 4494ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4504ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4514ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4524ed1eea8STomer Tayar } 4534ed1eea8STomer Tayar 454b310974eSTomer Tayar static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd) 455b310974eSTomer Tayar { 456b310974eSTomer Tayar p_hwfn->mcp_info->b_block_cmd = block_cmd; 457b310974eSTomer Tayar 458b310974eSTomer Tayar DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n", 459b310974eSTomer Tayar block_cmd ? "Block" : "Unblock"); 460b310974eSTomer Tayar } 461b310974eSTomer Tayar 462b310974eSTomer Tayar static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn, 463b310974eSTomer Tayar struct qed_ptt *p_ptt) 464b310974eSTomer Tayar { 465b310974eSTomer Tayar u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2; 466b310974eSTomer Tayar u32 delay = QED_MCP_RESP_ITER_US; 467b310974eSTomer Tayar 468b310974eSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 469b310974eSTomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 470b310974eSTomer Tayar cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 471b310974eSTomer Tayar udelay(delay); 472b310974eSTomer Tayar cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 473b310974eSTomer Tayar udelay(delay); 474b310974eSTomer Tayar cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 475b310974eSTomer Tayar 476b310974eSTomer Tayar DP_NOTICE(p_hwfn, 477b310974eSTomer Tayar "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n", 478b310974eSTomer Tayar cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2); 479b310974eSTomer Tayar } 480b310974eSTomer Tayar 4814ed1eea8STomer Tayar static int 4824ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4834ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4844ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 485eaa50fc5STomer Tayar u32 max_retries, u32 usecs) 4864ed1eea8STomer Tayar { 487eaa50fc5STomer Tayar u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000); 4884ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4894ed1eea8STomer Tayar u16 seq_num; 490fe56b9e6SYuval Mintz int rc = 0; 491fe56b9e6SYuval Mintz 4924ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 493fe56b9e6SYuval Mintz do { 4944ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4954ed1eea8STomer Tayar * pending command is completed during this iteration. 4964ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4974ed1eea8STomer Tayar */ 4984ed1eea8STomer Tayar 4994ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5004ed1eea8STomer Tayar 5014ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 5024ed1eea8STomer Tayar break; 5034ed1eea8STomer Tayar 5044ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5054ed1eea8STomer Tayar if (!rc) 5064ed1eea8STomer Tayar break; 5074ed1eea8STomer Tayar else if (rc != -EAGAIN) 5084ed1eea8STomer Tayar goto err; 5094ed1eea8STomer Tayar 5104ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 511eaa50fc5STomer Tayar 512eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 513eaa50fc5STomer Tayar msleep(msecs); 514eaa50fc5STomer Tayar else 515eaa50fc5STomer Tayar udelay(usecs); 5164ed1eea8STomer Tayar } while (++cnt < max_retries); 517fe56b9e6SYuval Mintz 5184ed1eea8STomer Tayar if (cnt >= max_retries) { 5194ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5204ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 5214ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 5224ed1eea8STomer Tayar return -EAGAIN; 523fe56b9e6SYuval Mintz } 5244ed1eea8STomer Tayar 5254ed1eea8STomer Tayar /* Send the mailbox command */ 5264ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 5274ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 5284ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 529c8004600SDan Carpenter if (!p_cmd_elem) { 530c8004600SDan Carpenter rc = -ENOMEM; 5314ed1eea8STomer Tayar goto err; 532c8004600SDan Carpenter } 5334ed1eea8STomer Tayar 5344ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 5354ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5364ed1eea8STomer Tayar 5374ed1eea8STomer Tayar /* Wait for the MFW response */ 5384ed1eea8STomer Tayar do { 5394ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 5404ed1eea8STomer Tayar * command is completed during this iteration. 5414ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 5424ed1eea8STomer Tayar */ 5434ed1eea8STomer Tayar 544eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 545eaa50fc5STomer Tayar msleep(msecs); 546eaa50fc5STomer Tayar else 547eaa50fc5STomer Tayar udelay(usecs); 548eaa50fc5STomer Tayar 5494ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5504ed1eea8STomer Tayar 5514ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 5524ed1eea8STomer Tayar break; 5534ed1eea8STomer Tayar 5544ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5554ed1eea8STomer Tayar if (!rc) 5564ed1eea8STomer Tayar break; 5574ed1eea8STomer Tayar else if (rc != -EAGAIN) 5584ed1eea8STomer Tayar goto err; 5594ed1eea8STomer Tayar 5604ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5614ed1eea8STomer Tayar } while (++cnt < max_retries); 5624ed1eea8STomer Tayar 5634ed1eea8STomer Tayar if (cnt >= max_retries) { 5644ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5654ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 5664ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 567b310974eSTomer Tayar qed_mcp_print_cpu_info(p_hwfn, p_ptt); 5684ed1eea8STomer Tayar 5694ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5704ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5714ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5724ed1eea8STomer Tayar 573b310974eSTomer Tayar if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK)) 574b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 575b310974eSTomer Tayar 5764ed1eea8STomer Tayar return -EAGAIN; 5774ed1eea8STomer Tayar } 5784ed1eea8STomer Tayar 5794ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5804ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5814ed1eea8STomer Tayar 5824ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5834ed1eea8STomer Tayar QED_MSG_SP, 5844ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5854ed1eea8STomer Tayar p_mb_params->mcp_resp, 5864ed1eea8STomer Tayar p_mb_params->mcp_param, 587eaa50fc5STomer Tayar (cnt * usecs) / 1000, (cnt * usecs) % 1000); 5884ed1eea8STomer Tayar 5894ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5904ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5914ed1eea8STomer Tayar 5924ed1eea8STomer Tayar return 0; 5934ed1eea8STomer Tayar 5944ed1eea8STomer Tayar err: 5954ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 596fe56b9e6SYuval Mintz return rc; 597fe56b9e6SYuval Mintz } 598fe56b9e6SYuval Mintz 5995529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 600fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 6015529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 602fe56b9e6SYuval Mintz { 6032f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 6044ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 605eaa50fc5STomer Tayar u32 usecs = QED_MCP_RESP_ITER_US; 606fe56b9e6SYuval Mintz 607fe56b9e6SYuval Mintz /* MCP not initialized */ 608fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 609fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 610fe56b9e6SYuval Mintz return -EBUSY; 611fe56b9e6SYuval Mintz } 612fe56b9e6SYuval Mintz 613b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 614b310974eSTomer Tayar DP_NOTICE(p_hwfn, 615b310974eSTomer Tayar "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n", 616b310974eSTomer Tayar p_mb_params->cmd, p_mb_params->param); 617b310974eSTomer Tayar return -EBUSY; 618b310974eSTomer Tayar } 619b310974eSTomer Tayar 6202f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 6212f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 6222f67af8cSTomer Tayar DP_ERR(p_hwfn, 6232f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 6242f67af8cSTomer Tayar p_mb_params->data_src_size, 6252f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 6262f67af8cSTomer Tayar return -EINVAL; 6272f67af8cSTomer Tayar } 6282f67af8cSTomer Tayar 629eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) { 630eaa50fc5STomer Tayar max_retries = DIV_ROUND_UP(max_retries, 1000); 631eaa50fc5STomer Tayar usecs *= 1000; 632eaa50fc5STomer Tayar } 633eaa50fc5STomer Tayar 6344ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 635eaa50fc5STomer Tayar usecs); 636fe56b9e6SYuval Mintz } 637fe56b9e6SYuval Mintz 6385529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 6395529bad9STomer Tayar struct qed_ptt *p_ptt, 6405529bad9STomer Tayar u32 cmd, 6415529bad9STomer Tayar u32 param, 6425529bad9STomer Tayar u32 *o_mcp_resp, 6435529bad9STomer Tayar u32 *o_mcp_param) 644fe56b9e6SYuval Mintz { 6455529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 6465529bad9STomer Tayar int rc; 647fe56b9e6SYuval Mintz 6485529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6495529bad9STomer Tayar mb_params.cmd = cmd; 6505529bad9STomer Tayar mb_params.param = param; 65114d39648SMintz, Yuval 6525529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6535529bad9STomer Tayar if (rc) 6545529bad9STomer Tayar return rc; 6555529bad9STomer Tayar 6565529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6575529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 6585529bad9STomer Tayar 6595529bad9STomer Tayar return 0; 660fe56b9e6SYuval Mintz } 661fe56b9e6SYuval Mintz 662bf774d14SYueHaibing static int 663bf774d14SYueHaibing qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 66462e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 66562e4d438SSudarsana Reddy Kalluru u32 cmd, 66662e4d438SSudarsana Reddy Kalluru u32 param, 66762e4d438SSudarsana Reddy Kalluru u32 *o_mcp_resp, 66862e4d438SSudarsana Reddy Kalluru u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 66962e4d438SSudarsana Reddy Kalluru { 67062e4d438SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 67162e4d438SSudarsana Reddy Kalluru int rc; 67262e4d438SSudarsana Reddy Kalluru 67362e4d438SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 67462e4d438SSudarsana Reddy Kalluru mb_params.cmd = cmd; 67562e4d438SSudarsana Reddy Kalluru mb_params.param = param; 67662e4d438SSudarsana Reddy Kalluru mb_params.p_data_src = i_buf; 67762e4d438SSudarsana Reddy Kalluru mb_params.data_src_size = (u8)i_txn_size; 67862e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 67962e4d438SSudarsana Reddy Kalluru if (rc) 68062e4d438SSudarsana Reddy Kalluru return rc; 68162e4d438SSudarsana Reddy Kalluru 68262e4d438SSudarsana Reddy Kalluru *o_mcp_resp = mb_params.mcp_resp; 68362e4d438SSudarsana Reddy Kalluru *o_mcp_param = mb_params.mcp_param; 68462e4d438SSudarsana Reddy Kalluru 6855e7ba042SDenis Bolotin /* nvm_info needs to be updated */ 6865e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = false; 6875e7ba042SDenis Bolotin 68862e4d438SSudarsana Reddy Kalluru return 0; 68962e4d438SSudarsana Reddy Kalluru } 69062e4d438SSudarsana Reddy Kalluru 6914102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 6924102426fSTomer Tayar struct qed_ptt *p_ptt, 6934102426fSTomer Tayar u32 cmd, 6944102426fSTomer Tayar u32 param, 6954102426fSTomer Tayar u32 *o_mcp_resp, 6964102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 6974102426fSTomer Tayar { 6984102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 6992f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 7004102426fSTomer Tayar int rc; 7014102426fSTomer Tayar 7024102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 7034102426fSTomer Tayar mb_params.cmd = cmd; 7044102426fSTomer Tayar mb_params.param = param; 7052f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 7062f67af8cSTomer Tayar 7072f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 7082f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 7092f67af8cSTomer Tayar 7104102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 7114102426fSTomer Tayar if (rc) 7124102426fSTomer Tayar return rc; 7134102426fSTomer Tayar 7144102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 7154102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 7164102426fSTomer Tayar 7174102426fSTomer Tayar *o_txn_size = *o_mcp_param; 7182f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 7194102426fSTomer Tayar 7204102426fSTomer Tayar return 0; 7214102426fSTomer Tayar } 7224102426fSTomer Tayar 7235d24bcf1STomer Tayar static bool 7245d24bcf1STomer Tayar qed_mcp_can_force_load(u8 drv_role, 7255d24bcf1STomer Tayar u8 exist_drv_role, 7265d24bcf1STomer Tayar enum qed_override_force_load override_force_load) 727fe56b9e6SYuval Mintz { 7285d24bcf1STomer Tayar bool can_force_load = false; 7295d24bcf1STomer Tayar 7305d24bcf1STomer Tayar switch (override_force_load) { 7315d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 7325d24bcf1STomer Tayar can_force_load = true; 7335d24bcf1STomer Tayar break; 7345d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_NEVER: 7355d24bcf1STomer Tayar can_force_load = false; 7365d24bcf1STomer Tayar break; 7375d24bcf1STomer Tayar default: 7385d24bcf1STomer Tayar can_force_load = (drv_role == DRV_ROLE_OS && 7395d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_PREBOOT) || 7405d24bcf1STomer Tayar (drv_role == DRV_ROLE_KDUMP && 7415d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_OS); 7425d24bcf1STomer Tayar break; 7435d24bcf1STomer Tayar } 7445d24bcf1STomer Tayar 7455d24bcf1STomer Tayar return can_force_load; 7465d24bcf1STomer Tayar } 7475d24bcf1STomer Tayar 7485d24bcf1STomer Tayar static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 7495d24bcf1STomer Tayar struct qed_ptt *p_ptt) 7505d24bcf1STomer Tayar { 7515d24bcf1STomer Tayar u32 resp = 0, param = 0; 752fe56b9e6SYuval Mintz int rc; 753fe56b9e6SYuval Mintz 7545d24bcf1STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 7555d24bcf1STomer Tayar &resp, ¶m); 7565d24bcf1STomer Tayar if (rc) 7575d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 7585d24bcf1STomer Tayar "Failed to send cancel load request, rc = %d\n", rc); 759fe56b9e6SYuval Mintz 760fe56b9e6SYuval Mintz return rc; 761fe56b9e6SYuval Mintz } 762fe56b9e6SYuval Mintz 7635d24bcf1STomer Tayar #define CONFIG_QEDE_BITMAP_IDX BIT(0) 7645d24bcf1STomer Tayar #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 7655d24bcf1STomer Tayar #define CONFIG_QEDR_BITMAP_IDX BIT(2) 7665d24bcf1STomer Tayar #define CONFIG_QEDF_BITMAP_IDX BIT(4) 7675d24bcf1STomer Tayar #define CONFIG_QEDI_BITMAP_IDX BIT(5) 7685d24bcf1STomer Tayar #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 7695529bad9STomer Tayar 7705d24bcf1STomer Tayar static u32 qed_get_config_bitmap(void) 7715d24bcf1STomer Tayar { 7725d24bcf1STomer Tayar u32 config_bitmap = 0x0; 7735d24bcf1STomer Tayar 7745d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QEDE)) 7755d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 7765d24bcf1STomer Tayar 7775d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_SRIOV)) 7785d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 7795d24bcf1STomer Tayar 7805d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_RDMA)) 7815d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 7825d24bcf1STomer Tayar 7835d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_FCOE)) 7845d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 7855d24bcf1STomer Tayar 7865d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_ISCSI)) 7875d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 7885d24bcf1STomer Tayar 7895d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_LL2)) 7905d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 7915d24bcf1STomer Tayar 7925d24bcf1STomer Tayar return config_bitmap; 7935d24bcf1STomer Tayar } 7945d24bcf1STomer Tayar 7955d24bcf1STomer Tayar struct qed_load_req_in_params { 7965d24bcf1STomer Tayar u8 hsi_ver; 7975d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 7985d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_1 1 7995d24bcf1STomer Tayar u32 drv_ver_0; 8005d24bcf1STomer Tayar u32 drv_ver_1; 8015d24bcf1STomer Tayar u32 fw_ver; 8025d24bcf1STomer Tayar u8 drv_role; 8035d24bcf1STomer Tayar u8 timeout_val; 8045d24bcf1STomer Tayar u8 force_cmd; 8055d24bcf1STomer Tayar bool avoid_eng_reset; 8065d24bcf1STomer Tayar }; 8075d24bcf1STomer Tayar 8085d24bcf1STomer Tayar struct qed_load_req_out_params { 8095d24bcf1STomer Tayar u32 load_code; 8105d24bcf1STomer Tayar u32 exist_drv_ver_0; 8115d24bcf1STomer Tayar u32 exist_drv_ver_1; 8125d24bcf1STomer Tayar u32 exist_fw_ver; 8135d24bcf1STomer Tayar u8 exist_drv_role; 8145d24bcf1STomer Tayar u8 mfw_hsi_ver; 8155d24bcf1STomer Tayar bool drv_exists; 8165d24bcf1STomer Tayar }; 8175d24bcf1STomer Tayar 8185d24bcf1STomer Tayar static int 8195d24bcf1STomer Tayar __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 8205d24bcf1STomer Tayar struct qed_ptt *p_ptt, 8215d24bcf1STomer Tayar struct qed_load_req_in_params *p_in_params, 8225d24bcf1STomer Tayar struct qed_load_req_out_params *p_out_params) 8235d24bcf1STomer Tayar { 8245d24bcf1STomer Tayar struct qed_mcp_mb_params mb_params; 8255d24bcf1STomer Tayar struct load_req_stc load_req; 8265d24bcf1STomer Tayar struct load_rsp_stc load_rsp; 8275d24bcf1STomer Tayar u32 hsi_ver; 8285d24bcf1STomer Tayar int rc; 8295d24bcf1STomer Tayar 8305d24bcf1STomer Tayar memset(&load_req, 0, sizeof(load_req)); 8315d24bcf1STomer Tayar load_req.drv_ver_0 = p_in_params->drv_ver_0; 8325d24bcf1STomer Tayar load_req.drv_ver_1 = p_in_params->drv_ver_1; 8335d24bcf1STomer Tayar load_req.fw_ver = p_in_params->fw_ver; 8345d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 8355d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 8365d24bcf1STomer Tayar p_in_params->timeout_val); 8375d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 8385d24bcf1STomer Tayar p_in_params->force_cmd); 8395d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 8405d24bcf1STomer Tayar p_in_params->avoid_eng_reset); 8415d24bcf1STomer Tayar 8425d24bcf1STomer Tayar hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 8435d24bcf1STomer Tayar DRV_ID_MCP_HSI_VER_CURRENT : 8445d24bcf1STomer Tayar (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 8455d24bcf1STomer Tayar 8465d24bcf1STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 8475d24bcf1STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 8485d24bcf1STomer Tayar mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 8495d24bcf1STomer Tayar mb_params.p_data_src = &load_req; 8505d24bcf1STomer Tayar mb_params.data_src_size = sizeof(load_req); 8515d24bcf1STomer Tayar mb_params.p_data_dst = &load_rsp; 8525d24bcf1STomer Tayar mb_params.data_dst_size = sizeof(load_rsp); 853b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 8545d24bcf1STomer Tayar 8555d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8565d24bcf1STomer Tayar "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 8575d24bcf1STomer Tayar mb_params.param, 8585d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 8595d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 8605d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 8615d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 8625d24bcf1STomer Tayar 8635d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 8645d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8655d24bcf1STomer Tayar "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 8665d24bcf1STomer Tayar load_req.drv_ver_0, 8675d24bcf1STomer Tayar load_req.drv_ver_1, 8685d24bcf1STomer Tayar load_req.fw_ver, 8695d24bcf1STomer Tayar load_req.misc0, 8705d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 8715d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, 8725d24bcf1STomer Tayar LOAD_REQ_LOCK_TO), 8735d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 8745d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 8755d24bcf1STomer Tayar } 8765d24bcf1STomer Tayar 8775d24bcf1STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 8785d24bcf1STomer Tayar if (rc) { 8795d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 8805d24bcf1STomer Tayar return rc; 8815d24bcf1STomer Tayar } 8825d24bcf1STomer Tayar 8835d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8845d24bcf1STomer Tayar "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 8855d24bcf1STomer Tayar p_out_params->load_code = mb_params.mcp_resp; 8865d24bcf1STomer Tayar 8875d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 8885d24bcf1STomer Tayar p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 8895d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, 8905d24bcf1STomer Tayar QED_MSG_SP, 8915d24bcf1STomer Tayar "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 8925d24bcf1STomer Tayar load_rsp.drv_ver_0, 8935d24bcf1STomer Tayar load_rsp.drv_ver_1, 8945d24bcf1STomer Tayar load_rsp.fw_ver, 8955d24bcf1STomer Tayar load_rsp.misc0, 8965d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 8975d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 8985d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 8995d24bcf1STomer Tayar 9005d24bcf1STomer Tayar p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 9015d24bcf1STomer Tayar p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 9025d24bcf1STomer Tayar p_out_params->exist_fw_ver = load_rsp.fw_ver; 9035d24bcf1STomer Tayar p_out_params->exist_drv_role = 9045d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 9055d24bcf1STomer Tayar p_out_params->mfw_hsi_ver = 9065d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 9075d24bcf1STomer Tayar p_out_params->drv_exists = 9085d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 9095d24bcf1STomer Tayar LOAD_RSP_FLAGS0_DRV_EXISTS; 9105d24bcf1STomer Tayar } 9115d24bcf1STomer Tayar 9125d24bcf1STomer Tayar return 0; 9135d24bcf1STomer Tayar } 9145d24bcf1STomer Tayar 9155d24bcf1STomer Tayar static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 9165d24bcf1STomer Tayar enum qed_drv_role drv_role, 9175d24bcf1STomer Tayar u8 *p_mfw_drv_role) 9185d24bcf1STomer Tayar { 9195d24bcf1STomer Tayar switch (drv_role) { 9205d24bcf1STomer Tayar case QED_DRV_ROLE_OS: 9215d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_OS; 9225d24bcf1STomer Tayar break; 9235d24bcf1STomer Tayar case QED_DRV_ROLE_KDUMP: 9245d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_KDUMP; 9255d24bcf1STomer Tayar break; 9265d24bcf1STomer Tayar default: 9275d24bcf1STomer Tayar DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 9285d24bcf1STomer Tayar return -EINVAL; 9295d24bcf1STomer Tayar } 9305d24bcf1STomer Tayar 9315d24bcf1STomer Tayar return 0; 9325d24bcf1STomer Tayar } 9335d24bcf1STomer Tayar 9345d24bcf1STomer Tayar enum qed_load_req_force { 9355d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, 9365d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_PF, 9375d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9385d24bcf1STomer Tayar }; 9395d24bcf1STomer Tayar 9405d24bcf1STomer Tayar static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 9415d24bcf1STomer Tayar 9425d24bcf1STomer Tayar enum qed_load_req_force force_cmd, 9435d24bcf1STomer Tayar u8 *p_mfw_force_cmd) 9445d24bcf1STomer Tayar { 9455d24bcf1STomer Tayar switch (force_cmd) { 9465d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_NONE: 9475d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 9485d24bcf1STomer Tayar break; 9495d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_PF: 9505d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 9515d24bcf1STomer Tayar break; 9525d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_ALL: 9535d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 9545d24bcf1STomer Tayar break; 9555d24bcf1STomer Tayar } 9565d24bcf1STomer Tayar } 9575d24bcf1STomer Tayar 9585d24bcf1STomer Tayar int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 9595d24bcf1STomer Tayar struct qed_ptt *p_ptt, 9605d24bcf1STomer Tayar struct qed_load_req_params *p_params) 9615d24bcf1STomer Tayar { 9625d24bcf1STomer Tayar struct qed_load_req_out_params out_params; 9635d24bcf1STomer Tayar struct qed_load_req_in_params in_params; 9645d24bcf1STomer Tayar u8 mfw_drv_role, mfw_force_cmd; 9655d24bcf1STomer Tayar int rc; 9665d24bcf1STomer Tayar 9675d24bcf1STomer Tayar memset(&in_params, 0, sizeof(in_params)); 9685d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 9695d24bcf1STomer Tayar in_params.drv_ver_0 = QED_VERSION; 9705d24bcf1STomer Tayar in_params.drv_ver_1 = qed_get_config_bitmap(); 9715d24bcf1STomer Tayar in_params.fw_ver = STORM_FW_VERSION; 9725d24bcf1STomer Tayar rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 9735d24bcf1STomer Tayar if (rc) 9745d24bcf1STomer Tayar return rc; 9755d24bcf1STomer Tayar 9765d24bcf1STomer Tayar in_params.drv_role = mfw_drv_role; 9775d24bcf1STomer Tayar in_params.timeout_val = p_params->timeout_val; 9785d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9795d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 9805d24bcf1STomer Tayar 9815d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9825d24bcf1STomer Tayar in_params.avoid_eng_reset = p_params->avoid_eng_reset; 9835d24bcf1STomer Tayar 9845d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9855d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9865d24bcf1STomer Tayar if (rc) 9875d24bcf1STomer Tayar return rc; 9885d24bcf1STomer Tayar 9895d24bcf1STomer Tayar /* First handle cases where another load request should/might be sent: 9905d24bcf1STomer Tayar * - MFW expects the old interface [HSI version = 1] 9915d24bcf1STomer Tayar * - MFW responds that a force load request is required 992fe56b9e6SYuval Mintz */ 9935d24bcf1STomer Tayar if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 9945d24bcf1STomer Tayar DP_INFO(p_hwfn, 9955d24bcf1STomer Tayar "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 9965d24bcf1STomer Tayar 9975d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 9985d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9995d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 10005d24bcf1STomer Tayar if (rc) 10015d24bcf1STomer Tayar return rc; 10025d24bcf1STomer Tayar } else if (out_params.load_code == 10035d24bcf1STomer Tayar FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 10045d24bcf1STomer Tayar if (qed_mcp_can_force_load(in_params.drv_role, 10055d24bcf1STomer Tayar out_params.exist_drv_role, 10065d24bcf1STomer Tayar p_params->override_force_load)) { 10075d24bcf1STomer Tayar DP_INFO(p_hwfn, 10085d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 10095d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10105d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10115d24bcf1STomer Tayar out_params.exist_drv_role, 10125d24bcf1STomer Tayar out_params.exist_fw_ver, 10135d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10145d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10155d24bcf1STomer Tayar 10165d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 10175d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 10185d24bcf1STomer Tayar &mfw_force_cmd); 10195d24bcf1STomer Tayar 10205d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 10215d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 10225d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 10235d24bcf1STomer Tayar &out_params); 10245d24bcf1STomer Tayar if (rc) 10255d24bcf1STomer Tayar return rc; 10265d24bcf1STomer Tayar } else { 10275d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10285d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 10295d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10305d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10315d24bcf1STomer Tayar out_params.exist_drv_role, 10325d24bcf1STomer Tayar out_params.exist_fw_ver, 10335d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10345d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10355d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10365d24bcf1STomer Tayar "Avoid sending a force load request to prevent disruption of active PFs\n"); 10375d24bcf1STomer Tayar 10385d24bcf1STomer Tayar qed_mcp_cancel_load_req(p_hwfn, p_ptt); 1039fe56b9e6SYuval Mintz return -EBUSY; 1040fe56b9e6SYuval Mintz } 10415d24bcf1STomer Tayar } 10425d24bcf1STomer Tayar 10435d24bcf1STomer Tayar /* Now handle the other types of responses. 10445d24bcf1STomer Tayar * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 10455d24bcf1STomer Tayar * expected here after the additional revised load requests were sent. 10465d24bcf1STomer Tayar */ 10475d24bcf1STomer Tayar switch (out_params.load_code) { 10485d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_ENGINE: 10495d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_PORT: 10505d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_FUNCTION: 10515d24bcf1STomer Tayar if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 10525d24bcf1STomer Tayar out_params.drv_exists) { 10535d24bcf1STomer Tayar /* The role and fw/driver version match, but the PF is 10545d24bcf1STomer Tayar * already loaded and has not been unloaded gracefully. 10555d24bcf1STomer Tayar */ 10565d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10575d24bcf1STomer Tayar "PF is already loaded\n"); 10585d24bcf1STomer Tayar return -EINVAL; 10595d24bcf1STomer Tayar } 10605d24bcf1STomer Tayar break; 10615d24bcf1STomer Tayar default: 10625d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10635d24bcf1STomer Tayar "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 10645d24bcf1STomer Tayar out_params.load_code); 10655d24bcf1STomer Tayar return -EBUSY; 10665d24bcf1STomer Tayar } 10675d24bcf1STomer Tayar 10685d24bcf1STomer Tayar p_params->load_code = out_params.load_code; 1069fe56b9e6SYuval Mintz 1070fe56b9e6SYuval Mintz return 0; 1071fe56b9e6SYuval Mintz } 1072fe56b9e6SYuval Mintz 10731226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10741226337aSTomer Tayar { 1075eaa50fc5STomer Tayar struct qed_mcp_mb_params mb_params; 1076eaa50fc5STomer Tayar u32 wol_param; 10771226337aSTomer Tayar 10781226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 10791226337aSTomer Tayar case QED_OV_WOL_DISABLED: 10801226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 10811226337aSTomer Tayar break; 10821226337aSTomer Tayar case QED_OV_WOL_ENABLED: 10831226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 10841226337aSTomer Tayar break; 10851226337aSTomer Tayar default: 10861226337aSTomer Tayar DP_NOTICE(p_hwfn, 10871226337aSTomer Tayar "Unknown WoL configuration %02x\n", 10881226337aSTomer Tayar p_hwfn->cdev->wol_config); 10891226337aSTomer Tayar /* Fallthrough */ 10901226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 10911226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 10921226337aSTomer Tayar } 10931226337aSTomer Tayar 1094eaa50fc5STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 1095eaa50fc5STomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ; 1096eaa50fc5STomer Tayar mb_params.param = wol_param; 1097b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 1098eaa50fc5STomer Tayar 1099eaa50fc5STomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11001226337aSTomer Tayar } 11011226337aSTomer Tayar 11021226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11031226337aSTomer Tayar { 11041226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 11051226337aSTomer Tayar struct mcp_mac wol_mac; 11061226337aSTomer Tayar 11071226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 11081226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 11091226337aSTomer Tayar 11101226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 11111226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 11121226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 11131226337aSTomer Tayar 11141226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 11151226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 11161226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 11171226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 11181226337aSTomer Tayar 11191226337aSTomer Tayar DP_VERBOSE(p_hwfn, 11201226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 11211226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 11221226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 11231226337aSTomer Tayar 11241226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 11251226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 11261226337aSTomer Tayar } 11271226337aSTomer Tayar 11281226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11291226337aSTomer Tayar } 11301226337aSTomer Tayar 11310b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 11320b55e27dSYuval Mintz struct qed_ptt *p_ptt) 11330b55e27dSYuval Mintz { 11340b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11350b55e27dSYuval Mintz PUBLIC_PATH); 11360b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 11370b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 11380b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 11390b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 11400b55e27dSYuval Mintz int i; 11410b55e27dSYuval Mintz 11420b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 11430b55e27dSYuval Mintz QED_MSG_SP, 11440b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 11450b55e27dSYuval Mintz mfw_path_offsize, path_addr); 11460b55e27dSYuval Mintz 11470b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 11480b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 11490b55e27dSYuval Mintz path_addr + 11500b55e27dSYuval Mintz offsetof(struct public_path, 11510b55e27dSYuval Mintz mcp_vf_disabled) + 11520b55e27dSYuval Mintz sizeof(u32) * i); 11530b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11540b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 11550b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 11560b55e27dSYuval Mintz } 11570b55e27dSYuval Mintz 11580b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 11590b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 11600b55e27dSYuval Mintz } 11610b55e27dSYuval Mintz 11620b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 11630b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 11640b55e27dSYuval Mintz { 11650b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11660b55e27dSYuval Mintz PUBLIC_FUNC); 11670b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 11680b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 11690b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 11700b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 11710b55e27dSYuval Mintz int rc; 11720b55e27dSYuval Mintz int i; 11730b55e27dSYuval Mintz 11740b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11750b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11760b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 11770b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 11780b55e27dSYuval Mintz 11790b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 11800b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 11812f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 11822f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 11830b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11840b55e27dSYuval Mintz if (rc) { 11850b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 11860b55e27dSYuval Mintz return -EBUSY; 11870b55e27dSYuval Mintz } 11880b55e27dSYuval Mintz 11890b55e27dSYuval Mintz /* Clear the ACK bits */ 11900b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11910b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 11920b55e27dSYuval Mintz func_addr + 11930b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 11940b55e27dSYuval Mintz i * sizeof(u32), 0); 11950b55e27dSYuval Mintz 11960b55e27dSYuval Mintz return rc; 11970b55e27dSYuval Mintz } 11980b55e27dSYuval Mintz 1199334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1200334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 1201334c03b5SZvi Nachmani { 1202334c03b5SZvi Nachmani u32 transceiver_state; 1203334c03b5SZvi Nachmani 1204334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 1205334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 1206334c03b5SZvi Nachmani offsetof(struct public_port, 1207334c03b5SZvi Nachmani transceiver_data)); 1208334c03b5SZvi Nachmani 1209334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 1210334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 1211334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1212334c03b5SZvi Nachmani transceiver_state, 1213334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 12141a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 1215334c03b5SZvi Nachmani 1216334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 1217351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 1218334c03b5SZvi Nachmani 1219351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1220334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1221334c03b5SZvi Nachmani else 1222334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1223334c03b5SZvi Nachmani } 1224334c03b5SZvi Nachmani 1225645874e5SSudarsana Reddy Kalluru static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1226645874e5SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1227645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_state *p_link) 1228645874e5SSudarsana Reddy Kalluru { 1229645874e5SSudarsana Reddy Kalluru u32 eee_status, val; 1230645874e5SSudarsana Reddy Kalluru 1231645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps = 0; 1232645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps = 0; 1233645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, 1234645874e5SSudarsana Reddy Kalluru p_ptt, 1235645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 1236645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 1237645874e5SSudarsana Reddy Kalluru p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1238645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1239645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1240645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1241645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1242645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1243645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1244645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1245645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1246645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1247645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1248645874e5SSudarsana Reddy Kalluru } 1249645874e5SSudarsana Reddy Kalluru 1250cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 12511a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 1252cc875c2eSYuval Mintz { 1253cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 1254a64b02d5SManish Chopra u8 max_bw, min_bw; 1255cc875c2eSYuval Mintz u32 status = 0; 1256cc875c2eSYuval Mintz 125765ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 125865ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 125965ed2ffdSMintz, Yuval 1260cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 1261cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 1262cc875c2eSYuval Mintz if (!b_reset) { 1263cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 1264cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 1265cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 1266cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1267cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1268cc875c2eSYuval Mintz status, 1269cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 12701a635e48SYuval Mintz offsetof(struct public_port, link_status))); 1271cc875c2eSYuval Mintz } else { 1272cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1273cc875c2eSYuval Mintz "Resetting link indications\n"); 127465ed2ffdSMintz, Yuval goto out; 1275cc875c2eSYuval Mintz } 1276cc875c2eSYuval Mintz 1277fc916ff2SSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) 1278cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1279fc916ff2SSudarsana Reddy Kalluru else 1280fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 1281cc875c2eSYuval Mintz 1282cc875c2eSYuval Mintz p_link->full_duplex = true; 1283cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1284cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1285cc875c2eSYuval Mintz p_link->speed = 100000; 1286cc875c2eSYuval Mintz break; 1287cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1288cc875c2eSYuval Mintz p_link->speed = 50000; 1289cc875c2eSYuval Mintz break; 1290cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1291cc875c2eSYuval Mintz p_link->speed = 40000; 1292cc875c2eSYuval Mintz break; 1293cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1294cc875c2eSYuval Mintz p_link->speed = 25000; 1295cc875c2eSYuval Mintz break; 1296cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1297cc875c2eSYuval Mintz p_link->speed = 20000; 1298cc875c2eSYuval Mintz break; 1299cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1300cc875c2eSYuval Mintz p_link->speed = 10000; 1301cc875c2eSYuval Mintz break; 1302cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1303cc875c2eSYuval Mintz p_link->full_duplex = false; 1304cc875c2eSYuval Mintz /* Fall-through */ 1305cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1306cc875c2eSYuval Mintz p_link->speed = 1000; 1307cc875c2eSYuval Mintz break; 1308cc875c2eSYuval Mintz default: 1309cc875c2eSYuval Mintz p_link->speed = 0; 131058874c7bSSudarsana Reddy Kalluru p_link->link_up = 0; 1311cc875c2eSYuval Mintz } 1312cc875c2eSYuval Mintz 13134b01e519SManish Chopra if (p_link->link_up && p_link->speed) 13144b01e519SManish Chopra p_link->line_speed = p_link->speed; 13154b01e519SManish Chopra else 13164b01e519SManish Chopra p_link->line_speed = 0; 13174b01e519SManish Chopra 13184b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1319a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 13204b01e519SManish Chopra 1321a64b02d5SManish Chopra /* Max bandwidth configuration */ 13224b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1323cc875c2eSYuval Mintz 1324a64b02d5SManish Chopra /* Min bandwidth configuration */ 1325a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 13266f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 13276f437d43SMintz, Yuval p_link->min_pf_rate); 1328a64b02d5SManish Chopra 1329cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1330cc875c2eSYuval Mintz p_link->an_complete = !!(status & 1331cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1332cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 1333cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 1334cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1335cc875c2eSYuval Mintz 1336cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1337cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1338cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 1339cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1340cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1341cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 1342cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1343cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1344cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 1345cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1346cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1347cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 1348cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1349054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1350054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 1351054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 1352cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1353cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 1354cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1355cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1356cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 1357cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1358cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1359cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 1360cc875c2eSYuval Mintz 1361cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 1362cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1363cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 1364cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1365cc875c2eSYuval Mintz 1366cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1367cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1368cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1369cc875c2eSYuval Mintz break; 1370cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1371cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1372cc875c2eSYuval Mintz break; 1373cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1374cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1375cc875c2eSYuval Mintz break; 1376cc875c2eSYuval Mintz default: 1377cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 1378cc875c2eSYuval Mintz } 1379cc875c2eSYuval Mintz 1380cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1381cc875c2eSYuval Mintz 1382645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1383645874e5SSudarsana Reddy Kalluru qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1384645874e5SSudarsana Reddy Kalluru 1385cc875c2eSYuval Mintz qed_link_update(p_hwfn); 138665ed2ffdSMintz, Yuval out: 138765ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1388cc875c2eSYuval Mintz } 1389cc875c2eSYuval Mintz 1390351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1391cc875c2eSYuval Mintz { 1392cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 13935529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 13942f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 1395cc875c2eSYuval Mintz int rc = 0; 13965529bad9STomer Tayar u32 cmd; 1397cc875c2eSYuval Mintz 1398cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 13992f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 1400cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1401cc875c2eSYuval Mintz if (!params->speed.autoneg) 14022f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 14032f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 14042f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 14052f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 14062f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 14072f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 14084ad95a93SSudarsana Reddy Kalluru 14094ad95a93SSudarsana Reddy Kalluru /* There are MFWs that share this capability regardless of whether 14104ad95a93SSudarsana Reddy Kalluru * this is feasible or not. And given that at the very least adv_caps 14114ad95a93SSudarsana Reddy Kalluru * would be set internally by qed, we want to make sure LFA would 14124ad95a93SSudarsana Reddy Kalluru * still work. 14134ad95a93SSudarsana Reddy Kalluru */ 14144ad95a93SSudarsana Reddy Kalluru if ((p_hwfn->mcp_info->capabilities & 14154ad95a93SSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1416645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1417645874e5SSudarsana Reddy Kalluru if (params->eee.tx_lpi_enable) 1418645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1419645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_1G_ADV) 1420645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1421645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_10G_ADV) 1422645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1423645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1424645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_OFFSET) & 1425645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_MASK; 1426645874e5SSudarsana Reddy Kalluru } 1427cc875c2eSYuval Mintz 1428fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 1429fc916ff2SSudarsana Reddy Kalluru 1430cc875c2eSYuval Mintz if (b_up) { 1431cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1432cc875c2eSYuval Mintz "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 14332f67af8cSTomer Tayar phy_cfg.speed, 14342f67af8cSTomer Tayar phy_cfg.pause, 14352f67af8cSTomer Tayar phy_cfg.adv_speed, 14362f67af8cSTomer Tayar phy_cfg.loopback_mode, 14372f67af8cSTomer Tayar phy_cfg.feature_config_flags); 1438cc875c2eSYuval Mintz } else { 1439cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1440cc875c2eSYuval Mintz "Resetting link\n"); 1441cc875c2eSYuval Mintz } 1442cc875c2eSYuval Mintz 14435529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 14445529bad9STomer Tayar mb_params.cmd = cmd; 14452f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 14462f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 14475529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1448cc875c2eSYuval Mintz 1449cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 1450cc875c2eSYuval Mintz if (rc) { 1451cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1452cc875c2eSYuval Mintz return rc; 1453cc875c2eSYuval Mintz } 1454cc875c2eSYuval Mintz 145565ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 145665ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 145765ed2ffdSMintz, Yuval * an attention. 145865ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 145965ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 146065ed2ffdSMintz, Yuval */ 146165ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1462cc875c2eSYuval Mintz 1463cc875c2eSYuval Mintz return 0; 1464cc875c2eSYuval Mintz } 1465cc875c2eSYuval Mintz 14666c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 14676c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 14686c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 14696c754246SSudarsana Reddy Kalluru { 14706c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 14716c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 14726c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 14736c754246SSudarsana Reddy Kalluru u32 hsi_param; 14746c754246SSudarsana Reddy Kalluru 14756c754246SSudarsana Reddy Kalluru switch (type) { 14766c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 14776c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 14786c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 14796c754246SSudarsana Reddy Kalluru break; 14806c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 14816c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 14826c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 14836c754246SSudarsana Reddy Kalluru break; 14846c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 14856c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 14866c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 14876c754246SSudarsana Reddy Kalluru break; 14886c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 14896c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 14906c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 14916c754246SSudarsana Reddy Kalluru break; 14926c754246SSudarsana Reddy Kalluru default: 14936c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 14946c754246SSudarsana Reddy Kalluru return; 14956c754246SSudarsana Reddy Kalluru } 14966c754246SSudarsana Reddy Kalluru 14976c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 14986c754246SSudarsana Reddy Kalluru 14996c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 15006c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 15016c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 15022f67af8cSTomer Tayar mb_params.p_data_src = &stats; 15032f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 15046c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 15056c754246SSudarsana Reddy Kalluru } 15066c754246SSudarsana Reddy Kalluru 15074b01e519SManish Chopra static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 15084b01e519SManish Chopra struct public_func *p_shmem_info) 15094b01e519SManish Chopra { 15104b01e519SManish Chopra struct qed_mcp_function_info *p_info; 15114b01e519SManish Chopra 15124b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 15134b01e519SManish Chopra 15144b01e519SManish Chopra p_info->bandwidth_min = (p_shmem_info->config & 15154b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_MASK) >> 15164b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_SHIFT; 15174b01e519SManish Chopra if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 15184b01e519SManish Chopra DP_INFO(p_hwfn, 15194b01e519SManish Chopra "bandwidth minimum out of bounds [%02x]. Set to 1\n", 15204b01e519SManish Chopra p_info->bandwidth_min); 15214b01e519SManish Chopra p_info->bandwidth_min = 1; 15224b01e519SManish Chopra } 15234b01e519SManish Chopra 15244b01e519SManish Chopra p_info->bandwidth_max = (p_shmem_info->config & 15254b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_MASK) >> 15264b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_SHIFT; 15274b01e519SManish Chopra if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 15284b01e519SManish Chopra DP_INFO(p_hwfn, 15294b01e519SManish Chopra "bandwidth maximum out of bounds [%02x]. Set to 100\n", 15304b01e519SManish Chopra p_info->bandwidth_max); 15314b01e519SManish Chopra p_info->bandwidth_max = 100; 15324b01e519SManish Chopra } 15334b01e519SManish Chopra } 15344b01e519SManish Chopra 15354b01e519SManish Chopra static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 15364b01e519SManish Chopra struct qed_ptt *p_ptt, 15371a635e48SYuval Mintz struct public_func *p_data, int pfid) 15384b01e519SManish Chopra { 15394b01e519SManish Chopra u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 15404b01e519SManish Chopra PUBLIC_FUNC); 15414b01e519SManish Chopra u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 15424b01e519SManish Chopra u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 15434b01e519SManish Chopra u32 i, size; 15444b01e519SManish Chopra 15454b01e519SManish Chopra memset(p_data, 0, sizeof(*p_data)); 15464b01e519SManish Chopra 15471a635e48SYuval Mintz size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 15484b01e519SManish Chopra for (i = 0; i < size / sizeof(u32); i++) 15494b01e519SManish Chopra ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 15504b01e519SManish Chopra func_addr + (i << 2)); 15514b01e519SManish Chopra return size; 15524b01e519SManish Chopra } 15534b01e519SManish Chopra 15541a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 15554b01e519SManish Chopra { 15564b01e519SManish Chopra struct qed_mcp_function_info *p_info; 15574b01e519SManish Chopra struct public_func shmem_info; 15584b01e519SManish Chopra u32 resp = 0, param = 0; 15594b01e519SManish Chopra 15601a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 15614b01e519SManish Chopra 15624b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 15634b01e519SManish Chopra 15644b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 15654b01e519SManish Chopra 1566a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 15674b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 15684b01e519SManish Chopra 15694b01e519SManish Chopra /* Acknowledge the MFW */ 15704b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 15714b01e519SManish Chopra ¶m); 15724b01e519SManish Chopra } 15734b01e519SManish Chopra 15742a351fd9SMintz, Yuval static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 15752a351fd9SMintz, Yuval { 15762a351fd9SMintz, Yuval struct public_func shmem_info; 15772a351fd9SMintz, Yuval u32 resp = 0, param = 0; 15782a351fd9SMintz, Yuval 15792a351fd9SMintz, Yuval qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 15802a351fd9SMintz, Yuval 15812a351fd9SMintz, Yuval p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 15822a351fd9SMintz, Yuval FUNC_MF_CFG_OV_STAG_MASK; 15832a351fd9SMintz, Yuval p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 15842a351fd9SMintz, Yuval if ((p_hwfn->hw_info.hw_mode & BIT(MODE_MF_SD)) && 15852a351fd9SMintz, Yuval (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET)) { 15862a351fd9SMintz, Yuval qed_wr(p_hwfn, p_ptt, 15872a351fd9SMintz, Yuval NIG_REG_LLH_FUNC_TAG_VALUE, p_hwfn->hw_info.ovlan); 15882a351fd9SMintz, Yuval qed_sp_pf_update_stag(p_hwfn); 15892a351fd9SMintz, Yuval } 15902a351fd9SMintz, Yuval 15912a351fd9SMintz, Yuval /* Acknowledge the MFW */ 15922a351fd9SMintz, Yuval qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 15932a351fd9SMintz, Yuval &resp, ¶m); 15942a351fd9SMintz, Yuval } 15952a351fd9SMintz, Yuval 1596cac6f691SSudarsana Reddy Kalluru void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1597cac6f691SSudarsana Reddy Kalluru { 1598cac6f691SSudarsana Reddy Kalluru struct public_func shmem_info; 1599cac6f691SSudarsana Reddy Kalluru u32 port_cfg, val; 1600cac6f691SSudarsana Reddy Kalluru 1601cac6f691SSudarsana Reddy Kalluru if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1602cac6f691SSudarsana Reddy Kalluru return; 1603cac6f691SSudarsana Reddy Kalluru 1604cac6f691SSudarsana Reddy Kalluru memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1605cac6f691SSudarsana Reddy Kalluru port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1606cac6f691SSudarsana Reddy Kalluru offsetof(struct public_port, oem_cfg_port)); 1607cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1608cac6f691SSudarsana Reddy Kalluru OEM_CFG_CHANNEL_TYPE_OFFSET; 1609cac6f691SSudarsana Reddy Kalluru if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1610cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Incorrect UFP Channel type %d\n", val); 1611cac6f691SSudarsana Reddy Kalluru 1612cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1613cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_SCHED_TYPE_ETS) { 1614cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1615cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1616cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1617cac6f691SSudarsana Reddy Kalluru } else { 1618cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1619cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Unknown UFP scheduling mode %d\n", val); 1620cac6f691SSudarsana Reddy Kalluru } 1621cac6f691SSudarsana Reddy Kalluru 1622cac6f691SSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1623b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1624b5fabb08SSudarsana Reddy Kalluru OEM_CFG_FUNC_TC_OFFSET; 1625cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.tc = (u8)val; 1626b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1627cac6f691SSudarsana Reddy Kalluru OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1628cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1629cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1630cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1631cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1632cac6f691SSudarsana Reddy Kalluru } else { 1633cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1634cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Unknown Host priority control %d\n", val); 1635cac6f691SSudarsana Reddy Kalluru } 1636cac6f691SSudarsana Reddy Kalluru 1637cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1638cac6f691SSudarsana Reddy Kalluru "UFP shmem config: mode = %d tc = %d pri_type = %d\n", 1639cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode, 1640cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.tc, p_hwfn->ufp_info.pri_type); 1641cac6f691SSudarsana Reddy Kalluru } 1642cac6f691SSudarsana Reddy Kalluru 1643cac6f691SSudarsana Reddy Kalluru static int 1644cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1645cac6f691SSudarsana Reddy Kalluru { 1646cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1647cac6f691SSudarsana Reddy Kalluru 1648cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1649cac6f691SSudarsana Reddy Kalluru p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1650c4259ddaSDenis Bolotin qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1651c4259ddaSDenis Bolotin p_hwfn->ufp_info.tc); 1652cac6f691SSudarsana Reddy Kalluru 1653cac6f691SSudarsana Reddy Kalluru qed_qm_reconf(p_hwfn, p_ptt); 1654cac6f691SSudarsana Reddy Kalluru } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1655cac6f691SSudarsana Reddy Kalluru /* Merge UFP TC with the dcbx TC data */ 1656cac6f691SSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1657cac6f691SSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 1658cac6f691SSudarsana Reddy Kalluru } else { 1659cac6f691SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1660cac6f691SSudarsana Reddy Kalluru return -EINVAL; 1661cac6f691SSudarsana Reddy Kalluru } 1662cac6f691SSudarsana Reddy Kalluru 1663cac6f691SSudarsana Reddy Kalluru /* update storm FW with negotiation results */ 1664cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_ufp(p_hwfn); 1665cac6f691SSudarsana Reddy Kalluru 1666cac6f691SSudarsana Reddy Kalluru /* update stag pcp value */ 1667cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_stag(p_hwfn); 1668cac6f691SSudarsana Reddy Kalluru 1669cac6f691SSudarsana Reddy Kalluru return 0; 1670cac6f691SSudarsana Reddy Kalluru } 1671cac6f691SSudarsana Reddy Kalluru 1672cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1673cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1674cc875c2eSYuval Mintz { 1675cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 1676cc875c2eSYuval Mintz int rc = 0; 1677cc875c2eSYuval Mintz bool found = false; 1678cc875c2eSYuval Mintz u16 i; 1679cc875c2eSYuval Mintz 1680cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1681cc875c2eSYuval Mintz 1682cc875c2eSYuval Mintz /* Read Messages from MFW */ 1683cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 1684cc875c2eSYuval Mintz 1685cc875c2eSYuval Mintz /* Compare current messages to old ones */ 1686cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 1687cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1688cc875c2eSYuval Mintz continue; 1689cc875c2eSYuval Mintz 1690cc875c2eSYuval Mintz found = true; 1691cc875c2eSYuval Mintz 1692cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1693cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1694cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1695cc875c2eSYuval Mintz 1696cc875c2eSYuval Mintz switch (i) { 1697cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 1698cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1699cc875c2eSYuval Mintz break; 17000b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 17010b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 17020b55e27dSYuval Mintz break; 170339651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 170439651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 170539651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 170639651abdSSudarsana Reddy Kalluru break; 170739651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 170839651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 170939651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 171039651abdSSudarsana Reddy Kalluru break; 171139651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 171239651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 171339651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 171439651abdSSudarsana Reddy Kalluru break; 1715cac6f691SSudarsana Reddy Kalluru case MFW_DRV_MSG_OEM_CFG_UPDATE: 1716cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 1717cac6f691SSudarsana Reddy Kalluru break; 1718334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1719334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1720334c03b5SZvi Nachmani break; 17216c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 17226c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 17236c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 17246c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 17256c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 17266c754246SSudarsana Reddy Kalluru break; 17274b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 17284b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 17294b01e519SManish Chopra break; 17302a351fd9SMintz, Yuval case MFW_DRV_MSG_S_TAG_UPDATE: 17312a351fd9SMintz, Yuval qed_mcp_update_stag(p_hwfn, p_ptt); 17322a351fd9SMintz, Yuval break; 173359ccf86fSSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_TLV_REQ: 173459ccf86fSSudarsana Reddy Kalluru qed_mfw_tlv_req(p_hwfn); 17352a351fd9SMintz, Yuval break; 1736cc875c2eSYuval Mintz default: 173739815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1738cc875c2eSYuval Mintz rc = -EINVAL; 1739cc875c2eSYuval Mintz } 1740cc875c2eSYuval Mintz } 1741cc875c2eSYuval Mintz 1742cc875c2eSYuval Mintz /* ACK everything */ 1743cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1744cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1745cc875c2eSYuval Mintz 1746cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 1747cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 1748cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 1749cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1750cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 1751cc875c2eSYuval Mintz (__force u32)val); 1752cc875c2eSYuval Mintz } 1753cc875c2eSYuval Mintz 1754cc875c2eSYuval Mintz if (!found) { 1755cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 1756cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 1757cc875c2eSYuval Mintz rc = -EINVAL; 1758cc875c2eSYuval Mintz } 1759cc875c2eSYuval Mintz 1760cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 1761cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1762cc875c2eSYuval Mintz 1763cc875c2eSYuval Mintz return rc; 1764cc875c2eSYuval Mintz } 1765cc875c2eSYuval Mintz 17661408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 17671408cc1fSYuval Mintz struct qed_ptt *p_ptt, 17681408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 1769fe56b9e6SYuval Mintz { 1770fe56b9e6SYuval Mintz u32 global_offsize; 1771fe56b9e6SYuval Mintz 17721408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 17731408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 17741408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 17751408cc1fSYuval Mintz 17761408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 17771408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 17781408cc1fSYuval Mintz return 0; 17791408cc1fSYuval Mintz } else { 17801408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 17811408cc1fSYuval Mintz QED_MSG_IOV, 17821408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 17831408cc1fSYuval Mintz return -EINVAL; 17841408cc1fSYuval Mintz } 17851408cc1fSYuval Mintz } 1786fe56b9e6SYuval Mintz 1787fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 17881408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 17891408cc1fSYuval Mintz mcp_info->public_base, 1790fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 17911408cc1fSYuval Mintz *p_mfw_ver = 17921408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 17931408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 17941408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 1795fe56b9e6SYuval Mintz 17961408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 17971408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 17981408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 17991408cc1fSYuval Mintz offsetof(struct public_global, 18001408cc1fSYuval Mintz running_bundle_id)); 18011408cc1fSYuval Mintz } 1802fe56b9e6SYuval Mintz 1803fe56b9e6SYuval Mintz return 0; 1804fe56b9e6SYuval Mintz } 1805fe56b9e6SYuval Mintz 1806ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 1807ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver) 1808ae33666aSTomer Tayar { 1809ae33666aSTomer Tayar u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 1810ae33666aSTomer Tayar 1811ae33666aSTomer Tayar if (IS_VF(p_hwfn->cdev)) 1812ae33666aSTomer Tayar return -EINVAL; 1813ae33666aSTomer Tayar 1814ae33666aSTomer Tayar /* Read the address of the nvm_cfg */ 1815ae33666aSTomer Tayar nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1816ae33666aSTomer Tayar if (!nvm_cfg_addr) { 1817ae33666aSTomer Tayar DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1818ae33666aSTomer Tayar return -EINVAL; 1819ae33666aSTomer Tayar } 1820ae33666aSTomer Tayar 1821ae33666aSTomer Tayar /* Read the offset of nvm_cfg1 */ 1822ae33666aSTomer Tayar nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1823ae33666aSTomer Tayar 1824ae33666aSTomer Tayar mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1825ae33666aSTomer Tayar offsetof(struct nvm_cfg1, glob) + 1826ae33666aSTomer Tayar offsetof(struct nvm_cfg1_glob, mbi_version); 1827ae33666aSTomer Tayar *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 1828ae33666aSTomer Tayar mbi_ver_addr) & 1829ae33666aSTomer Tayar (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 1830ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 1831ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 1832ae33666aSTomer Tayar 1833ae33666aSTomer Tayar return 0; 1834ae33666aSTomer Tayar } 1835ae33666aSTomer Tayar 18361a635e48SYuval Mintz int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) 1837cc875c2eSYuval Mintz { 1838cc875c2eSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 1839cc875c2eSYuval Mintz struct qed_ptt *p_ptt; 1840cc875c2eSYuval Mintz 18411408cc1fSYuval Mintz if (IS_VF(cdev)) 18421408cc1fSYuval Mintz return -EINVAL; 18431408cc1fSYuval Mintz 1844cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 1845cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1846cc875c2eSYuval Mintz return -EBUSY; 1847cc875c2eSYuval Mintz } 1848cc875c2eSYuval Mintz 1849cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 1850cc875c2eSYuval Mintz 1851cc875c2eSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 1852cc875c2eSYuval Mintz if (!p_ptt) 1853cc875c2eSYuval Mintz return -EBUSY; 1854cc875c2eSYuval Mintz 1855cc875c2eSYuval Mintz *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1856cc875c2eSYuval Mintz offsetof(struct public_port, media_type)); 1857cc875c2eSYuval Mintz 1858cc875c2eSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 1859cc875c2eSYuval Mintz 1860cc875c2eSYuval Mintz return 0; 1861cc875c2eSYuval Mintz } 1862cc875c2eSYuval Mintz 18636927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 18646927e826SMintz, Yuval static void 18656927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 18666927e826SMintz, Yuval enum qed_pci_personality *p_proto) 18676927e826SMintz, Yuval { 18686927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 18696927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 18706927e826SMintz, Yuval */ 18716927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 18726927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 18736927e826SMintz, Yuval else 18746927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 18756927e826SMintz, Yuval 18766927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 18776927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 18786927e826SMintz, Yuval (u32) *p_proto); 18796927e826SMintz, Yuval } 18806927e826SMintz, Yuval 18816927e826SMintz, Yuval static int 18826927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 18836927e826SMintz, Yuval struct qed_ptt *p_ptt, 18846927e826SMintz, Yuval enum qed_pci_personality *p_proto) 18856927e826SMintz, Yuval { 18866927e826SMintz, Yuval u32 resp = 0, param = 0; 18876927e826SMintz, Yuval int rc; 18886927e826SMintz, Yuval 18896927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 18906927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 18916927e826SMintz, Yuval if (rc) 18926927e826SMintz, Yuval return rc; 18936927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 18946927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 18956927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 18966927e826SMintz, Yuval resp); 18976927e826SMintz, Yuval return -EINVAL; 18986927e826SMintz, Yuval } 18996927e826SMintz, Yuval 19006927e826SMintz, Yuval switch (param) { 19016927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 19026927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 19036927e826SMintz, Yuval break; 19046927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 19056927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 19066927e826SMintz, Yuval break; 19076927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 1908e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_IWARP; 1909e0a8f9deSMichal Kalderon break; 1910e0a8f9deSMichal Kalderon case FW_MB_PARAM_GET_PF_RDMA_BOTH: 1911e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_RDMA; 1912e0a8f9deSMichal Kalderon break; 19136927e826SMintz, Yuval default: 19146927e826SMintz, Yuval DP_NOTICE(p_hwfn, 19156927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 19166927e826SMintz, Yuval param); 19176927e826SMintz, Yuval return -EINVAL; 19186927e826SMintz, Yuval } 19196927e826SMintz, Yuval 19206927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 19216927e826SMintz, Yuval NETIF_MSG_IFUP, 19226927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 19236927e826SMintz, Yuval (u32) *p_proto, resp, param); 19246927e826SMintz, Yuval return 0; 19256927e826SMintz, Yuval } 19266927e826SMintz, Yuval 1927fe56b9e6SYuval Mintz static int 1928fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 1929fe56b9e6SYuval Mintz struct public_func *p_info, 19306927e826SMintz, Yuval struct qed_ptt *p_ptt, 1931fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 1932fe56b9e6SYuval Mintz { 1933fe56b9e6SYuval Mintz int rc = 0; 1934fe56b9e6SYuval Mintz 1935fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 1936fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 19371fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 19381fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 19391fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 19406927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 1941fe56b9e6SYuval Mintz break; 1942c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 1943c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 1944c5ac9319SYuval Mintz break; 19451e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 19461e128c81SArun Easi *p_proto = QED_PCI_FCOE; 19471e128c81SArun Easi break; 1948c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 1949c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 19506927e826SMintz, Yuval /* Fallthrough */ 1951fe56b9e6SYuval Mintz default: 1952fe56b9e6SYuval Mintz rc = -EINVAL; 1953fe56b9e6SYuval Mintz } 1954fe56b9e6SYuval Mintz 1955fe56b9e6SYuval Mintz return rc; 1956fe56b9e6SYuval Mintz } 1957fe56b9e6SYuval Mintz 1958fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 1959fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 1960fe56b9e6SYuval Mintz { 1961fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 1962fe56b9e6SYuval Mintz struct public_func shmem_info; 1963fe56b9e6SYuval Mintz 19641a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1965fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 1966fe56b9e6SYuval Mintz 1967fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 1968fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 1969fe56b9e6SYuval Mintz 19706927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 19716927e826SMintz, Yuval &info->protocol)) { 1972fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 1973fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 1974fe56b9e6SYuval Mintz return -EINVAL; 1975fe56b9e6SYuval Mintz } 1976fe56b9e6SYuval Mintz 19774b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1978fe56b9e6SYuval Mintz 1979fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 1980fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 1981fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 1982fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 1983fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 1984fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 1985fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 198614d39648SMintz, Yuval 198714d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 198814d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 1989fe56b9e6SYuval Mintz } else { 1990fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 1991fe56b9e6SYuval Mintz } 1992fe56b9e6SYuval Mintz 199357796759SMintz, Yuval info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 199457796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 199557796759SMintz, Yuval info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 199657796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 1997fe56b9e6SYuval Mintz 1998fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 1999fe56b9e6SYuval Mintz 20000fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 20010fefbfbaSSudarsana Kalluru 200214d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 200314d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 200414d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 200514d39648SMintz, Yuval u32 resp = 0, param = 0; 200614d39648SMintz, Yuval int rc; 200714d39648SMintz, Yuval 200814d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 200914d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 201014d39648SMintz, Yuval if (rc) 201114d39648SMintz, Yuval return rc; 201214d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 201314d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 201414d39648SMintz, Yuval } 201514d39648SMintz, Yuval 2016fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 201714d39648SMintz, Yuval "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 2018fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 2019fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 2020fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 2021fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 202214d39648SMintz, Yuval info->wwn_port, info->wwn_node, 202314d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 2024fe56b9e6SYuval Mintz 2025fe56b9e6SYuval Mintz return 0; 2026fe56b9e6SYuval Mintz } 2027fe56b9e6SYuval Mintz 2028cc875c2eSYuval Mintz struct qed_mcp_link_params 2029cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 2030cc875c2eSYuval Mintz { 2031cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2032cc875c2eSYuval Mintz return NULL; 2033cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 2034cc875c2eSYuval Mintz } 2035cc875c2eSYuval Mintz 2036cc875c2eSYuval Mintz struct qed_mcp_link_state 2037cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 2038cc875c2eSYuval Mintz { 2039cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2040cc875c2eSYuval Mintz return NULL; 2041cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 2042cc875c2eSYuval Mintz } 2043cc875c2eSYuval Mintz 2044cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 2045cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 2046cc875c2eSYuval Mintz { 2047cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2048cc875c2eSYuval Mintz return NULL; 2049cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 2050cc875c2eSYuval Mintz } 2051cc875c2eSYuval Mintz 20521a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2053fe56b9e6SYuval Mintz { 2054fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 2055fe56b9e6SYuval Mintz int rc; 2056fe56b9e6SYuval Mintz 2057fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 20581a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 2059fe56b9e6SYuval Mintz 2060fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 20618f60bafeSYuval Mintz msleep(1020); 2062fe56b9e6SYuval Mintz 2063fe56b9e6SYuval Mintz return rc; 2064fe56b9e6SYuval Mintz } 2065fe56b9e6SYuval Mintz 2066cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 20671a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 2068cee4d264SManish Chopra { 2069cee4d264SManish Chopra u32 flash_size; 2070cee4d264SManish Chopra 20711408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 20721408cc1fSYuval Mintz return -EINVAL; 20731408cc1fSYuval Mintz 2074cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 2075cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 2076cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 2077cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 2078cee4d264SManish Chopra 2079cee4d264SManish Chopra *p_flash_size = flash_size; 2080cee4d264SManish Chopra 2081cee4d264SManish Chopra return 0; 2082cee4d264SManish Chopra } 2083cee4d264SManish Chopra 208488072fd4SMintz, Yuval static int 208588072fd4SMintz, Yuval qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 20861408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 20871408cc1fSYuval Mintz { 20881408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 20891408cc1fSYuval Mintz int rc; 20901408cc1fSYuval Mintz 20911408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 20921408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 20931408cc1fSYuval Mintz return 0; 20941408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 20951408cc1fSYuval Mintz 20961408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 20971408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 20981408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 20991408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 21001408cc1fSYuval Mintz 21011408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 21021408cc1fSYuval Mintz &resp, &rc_param); 21031408cc1fSYuval Mintz 21041408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 21051408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 21061408cc1fSYuval Mintz rc = -EINVAL; 21071408cc1fSYuval Mintz } else { 21081408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 21091408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 21101408cc1fSYuval Mintz num, vf_id); 21111408cc1fSYuval Mintz } 21121408cc1fSYuval Mintz 21131408cc1fSYuval Mintz return rc; 21141408cc1fSYuval Mintz } 21151408cc1fSYuval Mintz 211688072fd4SMintz, Yuval static int 211788072fd4SMintz, Yuval qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 211888072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 num) 211988072fd4SMintz, Yuval { 212088072fd4SMintz, Yuval u32 resp = 0, param = num, rc_param = 0; 212188072fd4SMintz, Yuval int rc; 212288072fd4SMintz, Yuval 212388072fd4SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 212488072fd4SMintz, Yuval param, &resp, &rc_param); 212588072fd4SMintz, Yuval 212688072fd4SMintz, Yuval if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 212788072fd4SMintz, Yuval DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 212888072fd4SMintz, Yuval rc = -EINVAL; 212988072fd4SMintz, Yuval } else { 213088072fd4SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_IOV, 213188072fd4SMintz, Yuval "Requested 0x%02x MSI-x interrupts for VFs\n", num); 213288072fd4SMintz, Yuval } 213388072fd4SMintz, Yuval 213488072fd4SMintz, Yuval return rc; 213588072fd4SMintz, Yuval } 213688072fd4SMintz, Yuval 213788072fd4SMintz, Yuval int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 213888072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 vf_id, u8 num) 213988072fd4SMintz, Yuval { 214088072fd4SMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 214188072fd4SMintz, Yuval return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 214288072fd4SMintz, Yuval else 214388072fd4SMintz, Yuval return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 214488072fd4SMintz, Yuval } 214588072fd4SMintz, Yuval 2146fe56b9e6SYuval Mintz int 2147fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2148fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2149fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 2150fe56b9e6SYuval Mintz { 21515529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 21522f67af8cSTomer Tayar struct drv_version_stc drv_version; 21535529bad9STomer Tayar __be32 val; 21545529bad9STomer Tayar u32 i; 21555529bad9STomer Tayar int rc; 2156fe56b9e6SYuval Mintz 21572f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 21582f67af8cSTomer Tayar drv_version.version = p_ver->version; 215967a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 216067a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 21612f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2162fe56b9e6SYuval Mintz } 2163fe56b9e6SYuval Mintz 21645529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 21655529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 21662f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 21672f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 21685529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 21695529bad9STomer Tayar if (rc) 2170fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2171fe56b9e6SYuval Mintz 21725529bad9STomer Tayar return rc; 2173fe56b9e6SYuval Mintz } 217491420b83SSudarsana Kalluru 217576271809STomer Tayar /* A maximal 100 msec waiting time for the MCP to halt */ 217676271809STomer Tayar #define QED_MCP_HALT_SLEEP_MS 10 217776271809STomer Tayar #define QED_MCP_HALT_MAX_RETRIES 10 217876271809STomer Tayar 21794102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 21804102426fSTomer Tayar { 218176271809STomer Tayar u32 resp = 0, param = 0, cpu_state, cnt = 0; 21824102426fSTomer Tayar int rc; 21834102426fSTomer Tayar 21844102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 21854102426fSTomer Tayar ¶m); 218676271809STomer Tayar if (rc) { 21874102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 21884102426fSTomer Tayar return rc; 21894102426fSTomer Tayar } 21904102426fSTomer Tayar 219176271809STomer Tayar do { 219276271809STomer Tayar msleep(QED_MCP_HALT_SLEEP_MS); 219376271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 219476271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) 219576271809STomer Tayar break; 219676271809STomer Tayar } while (++cnt < QED_MCP_HALT_MAX_RETRIES); 219776271809STomer Tayar 219876271809STomer Tayar if (cnt == QED_MCP_HALT_MAX_RETRIES) { 219976271809STomer Tayar DP_NOTICE(p_hwfn, 220076271809STomer Tayar "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 220176271809STomer Tayar qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state); 220276271809STomer Tayar return -EBUSY; 220376271809STomer Tayar } 220476271809STomer Tayar 2205b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 2206b310974eSTomer Tayar 220776271809STomer Tayar return 0; 220876271809STomer Tayar } 220976271809STomer Tayar 221076271809STomer Tayar #define QED_MCP_RESUME_SLEEP_MS 10 221176271809STomer Tayar 22124102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 22134102426fSTomer Tayar { 221476271809STomer Tayar u32 cpu_mode, cpu_state; 22154102426fSTomer Tayar 22164102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 22174102426fSTomer Tayar 22184102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 221976271809STomer Tayar cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT; 222076271809STomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode); 222176271809STomer Tayar msleep(QED_MCP_RESUME_SLEEP_MS); 222276271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 22234102426fSTomer Tayar 222476271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) { 222576271809STomer Tayar DP_NOTICE(p_hwfn, 222676271809STomer Tayar "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 222776271809STomer Tayar cpu_mode, cpu_state); 222876271809STomer Tayar return -EBUSY; 222976271809STomer Tayar } 223076271809STomer Tayar 2231b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, false); 2232b310974eSTomer Tayar 223376271809STomer Tayar return 0; 22344102426fSTomer Tayar } 22354102426fSTomer Tayar 22360fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 22370fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 22380fefbfbaSSudarsana Kalluru enum qed_ov_client client) 22390fefbfbaSSudarsana Kalluru { 22400fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 22410fefbfbaSSudarsana Kalluru u32 drv_mb_param; 22420fefbfbaSSudarsana Kalluru int rc; 22430fefbfbaSSudarsana Kalluru 22440fefbfbaSSudarsana Kalluru switch (client) { 22450fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 22460fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 22470fefbfbaSSudarsana Kalluru break; 22480fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 22490fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 22500fefbfbaSSudarsana Kalluru break; 22510fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 22520fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 22530fefbfbaSSudarsana Kalluru break; 22540fefbfbaSSudarsana Kalluru default: 22550fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 22560fefbfbaSSudarsana Kalluru return -EINVAL; 22570fefbfbaSSudarsana Kalluru } 22580fefbfbaSSudarsana Kalluru 22590fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 22600fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 22610fefbfbaSSudarsana Kalluru if (rc) 22620fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 22630fefbfbaSSudarsana Kalluru 22640fefbfbaSSudarsana Kalluru return rc; 22650fefbfbaSSudarsana Kalluru } 22660fefbfbaSSudarsana Kalluru 22670fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 22680fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 22690fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 22700fefbfbaSSudarsana Kalluru { 22710fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 22720fefbfbaSSudarsana Kalluru u32 drv_mb_param; 22730fefbfbaSSudarsana Kalluru int rc; 22740fefbfbaSSudarsana Kalluru 22750fefbfbaSSudarsana Kalluru switch (drv_state) { 22760fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 22770fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 22780fefbfbaSSudarsana Kalluru break; 22790fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 22800fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 22810fefbfbaSSudarsana Kalluru break; 22820fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 22830fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 22840fefbfbaSSudarsana Kalluru break; 22850fefbfbaSSudarsana Kalluru default: 22860fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 22870fefbfbaSSudarsana Kalluru return -EINVAL; 22880fefbfbaSSudarsana Kalluru } 22890fefbfbaSSudarsana Kalluru 22900fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 22910fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 22920fefbfbaSSudarsana Kalluru if (rc) 22930fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 22940fefbfbaSSudarsana Kalluru 22950fefbfbaSSudarsana Kalluru return rc; 22960fefbfbaSSudarsana Kalluru } 22970fefbfbaSSudarsana Kalluru 22980fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 22990fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 23000fefbfbaSSudarsana Kalluru { 23010fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 23020fefbfbaSSudarsana Kalluru u32 drv_mb_param; 23030fefbfbaSSudarsana Kalluru int rc; 23040fefbfbaSSudarsana Kalluru 23050fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 23060fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 23070fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 23080fefbfbaSSudarsana Kalluru if (rc) 23090fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 23100fefbfbaSSudarsana Kalluru 23110fefbfbaSSudarsana Kalluru return rc; 23120fefbfbaSSudarsana Kalluru } 23130fefbfbaSSudarsana Kalluru 23140fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 23150fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 23160fefbfbaSSudarsana Kalluru { 23170fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 231817991002SMintz, Yuval u32 mfw_mac[2]; 23190fefbfbaSSudarsana Kalluru int rc; 23200fefbfbaSSudarsana Kalluru 23210fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 23220fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 23230fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 23240fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 23250fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 23262f67af8cSTomer Tayar 232717991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 232817991002SMintz, Yuval * in 32-bit granularity. 232917991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 233017991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 233117991002SMintz, Yuval */ 233217991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 233317991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 233417991002SMintz, Yuval 233517991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 233617991002SMintz, Yuval mb_params.data_src_size = 8; 23370fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 23380fefbfbaSSudarsana Kalluru if (rc) 23390fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 23400fefbfbaSSudarsana Kalluru 234114d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 234214d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 234314d39648SMintz, Yuval 23440fefbfbaSSudarsana Kalluru return rc; 23450fefbfbaSSudarsana Kalluru } 23460fefbfbaSSudarsana Kalluru 23470fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 23480fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 23490fefbfbaSSudarsana Kalluru { 23500fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 23510fefbfbaSSudarsana Kalluru u32 drv_mb_param; 23520fefbfbaSSudarsana Kalluru int rc; 23530fefbfbaSSudarsana Kalluru 235414d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 235514d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 235614d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 235714d39648SMintz, Yuval return -EINVAL; 235814d39648SMintz, Yuval } 235914d39648SMintz, Yuval 23600fefbfbaSSudarsana Kalluru switch (wol) { 23610fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 23620fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 23630fefbfbaSSudarsana Kalluru break; 23640fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 23650fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 23660fefbfbaSSudarsana Kalluru break; 23670fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 23680fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 23690fefbfbaSSudarsana Kalluru break; 23700fefbfbaSSudarsana Kalluru default: 23710fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 23720fefbfbaSSudarsana Kalluru return -EINVAL; 23730fefbfbaSSudarsana Kalluru } 23740fefbfbaSSudarsana Kalluru 23750fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 23760fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 23770fefbfbaSSudarsana Kalluru if (rc) 23780fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 23790fefbfbaSSudarsana Kalluru 238014d39648SMintz, Yuval /* Store the WoL update for a future unload */ 238114d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 238214d39648SMintz, Yuval 23830fefbfbaSSudarsana Kalluru return rc; 23840fefbfbaSSudarsana Kalluru } 23850fefbfbaSSudarsana Kalluru 23860fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 23870fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 23880fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 23890fefbfbaSSudarsana Kalluru { 23900fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 23910fefbfbaSSudarsana Kalluru u32 drv_mb_param; 23920fefbfbaSSudarsana Kalluru int rc; 23930fefbfbaSSudarsana Kalluru 23940fefbfbaSSudarsana Kalluru switch (eswitch) { 23950fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 23960fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 23970fefbfbaSSudarsana Kalluru break; 23980fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 23990fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 24000fefbfbaSSudarsana Kalluru break; 24010fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 24020fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 24030fefbfbaSSudarsana Kalluru break; 24040fefbfbaSSudarsana Kalluru default: 24050fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 24060fefbfbaSSudarsana Kalluru return -EINVAL; 24070fefbfbaSSudarsana Kalluru } 24080fefbfbaSSudarsana Kalluru 24090fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 24100fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 24110fefbfbaSSudarsana Kalluru if (rc) 24120fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 24130fefbfbaSSudarsana Kalluru 24140fefbfbaSSudarsana Kalluru return rc; 24150fefbfbaSSudarsana Kalluru } 24160fefbfbaSSudarsana Kalluru 24171a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 24181a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 241991420b83SSudarsana Kalluru { 242091420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 242191420b83SSudarsana Kalluru int rc; 242291420b83SSudarsana Kalluru 242391420b83SSudarsana Kalluru switch (mode) { 242491420b83SSudarsana Kalluru case QED_LED_MODE_ON: 242591420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 242691420b83SSudarsana Kalluru break; 242791420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 242891420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 242991420b83SSudarsana Kalluru break; 243091420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 243191420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 243291420b83SSudarsana Kalluru break; 243391420b83SSudarsana Kalluru default: 243491420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 243591420b83SSudarsana Kalluru return -EINVAL; 243691420b83SSudarsana Kalluru } 243791420b83SSudarsana Kalluru 243891420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 243991420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 244091420b83SSudarsana Kalluru 244191420b83SSudarsana Kalluru return rc; 244291420b83SSudarsana Kalluru } 244303dc76caSSudarsana Reddy Kalluru 24444102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 24454102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 24464102426fSTomer Tayar { 24474102426fSTomer Tayar u32 resp = 0, param = 0; 24484102426fSTomer Tayar int rc; 24494102426fSTomer Tayar 24504102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 24514102426fSTomer Tayar mask_parities, &resp, ¶m); 24524102426fSTomer Tayar 24534102426fSTomer Tayar if (rc) { 24544102426fSTomer Tayar DP_ERR(p_hwfn, 24554102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 24564102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 24574102426fSTomer Tayar DP_ERR(p_hwfn, 24584102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 24594102426fSTomer Tayar rc = -EINVAL; 24604102426fSTomer Tayar } 24614102426fSTomer Tayar 24624102426fSTomer Tayar return rc; 24634102426fSTomer Tayar } 24644102426fSTomer Tayar 24657a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 24667a4b21b7SMintz, Yuval { 24677a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 24687a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 24697a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 24707a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 24717a4b21b7SMintz, Yuval int rc = 0; 24727a4b21b7SMintz, Yuval 24737a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 24747a4b21b7SMintz, Yuval if (!p_ptt) 24757a4b21b7SMintz, Yuval return -EBUSY; 24767a4b21b7SMintz, Yuval 24777a4b21b7SMintz, Yuval while (bytes_left > 0) { 24787a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 24797a4b21b7SMintz, Yuval 24807a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 24817a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 24827a4b21b7SMintz, Yuval addr + offset + 24837a4b21b7SMintz, Yuval (bytes_to_copy << 2484da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 24857a4b21b7SMintz, Yuval &resp, &resp_param, 24867a4b21b7SMintz, Yuval &read_len, 24877a4b21b7SMintz, Yuval (u32 *)(p_buf + offset)); 24887a4b21b7SMintz, Yuval 24897a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 24907a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 24917a4b21b7SMintz, Yuval break; 24927a4b21b7SMintz, Yuval } 24937a4b21b7SMintz, Yuval 24947a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 24957a4b21b7SMintz, Yuval * isn't preemptable. Sleep a bit to prevent CPU hogging. 24967a4b21b7SMintz, Yuval */ 24977a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 24987a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 24997a4b21b7SMintz, Yuval usleep_range(1000, 2000); 25007a4b21b7SMintz, Yuval 25017a4b21b7SMintz, Yuval offset += read_len; 25027a4b21b7SMintz, Yuval bytes_left -= read_len; 25037a4b21b7SMintz, Yuval } 25047a4b21b7SMintz, Yuval 25057a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 25067a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 25077a4b21b7SMintz, Yuval 25087a4b21b7SMintz, Yuval return rc; 25097a4b21b7SMintz, Yuval } 25107a4b21b7SMintz, Yuval 251162e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 251262e4d438SSudarsana Reddy Kalluru { 251362e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 251462e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 251562e4d438SSudarsana Reddy Kalluru 251662e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 251762e4d438SSudarsana Reddy Kalluru if (!p_ptt) 251862e4d438SSudarsana Reddy Kalluru return -EBUSY; 251962e4d438SSudarsana Reddy Kalluru 252062e4d438SSudarsana Reddy Kalluru memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 252162e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 252262e4d438SSudarsana Reddy Kalluru 252362e4d438SSudarsana Reddy Kalluru return 0; 252462e4d438SSudarsana Reddy Kalluru } 252562e4d438SSudarsana Reddy Kalluru 252662e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr) 252762e4d438SSudarsana Reddy Kalluru { 252862e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 252962e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 253062e4d438SSudarsana Reddy Kalluru u32 resp, param; 253162e4d438SSudarsana Reddy Kalluru int rc; 253262e4d438SSudarsana Reddy Kalluru 253362e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 253462e4d438SSudarsana Reddy Kalluru if (!p_ptt) 253562e4d438SSudarsana Reddy Kalluru return -EBUSY; 253662e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr, 253762e4d438SSudarsana Reddy Kalluru &resp, ¶m); 253862e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 253962e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 254062e4d438SSudarsana Reddy Kalluru 254162e4d438SSudarsana Reddy Kalluru return rc; 254262e4d438SSudarsana Reddy Kalluru } 254362e4d438SSudarsana Reddy Kalluru 254462e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 254562e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len) 254662e4d438SSudarsana Reddy Kalluru { 254762e4d438SSudarsana Reddy Kalluru u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 254862e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 254962e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 255062e4d438SSudarsana Reddy Kalluru int rc = -EINVAL; 255162e4d438SSudarsana Reddy Kalluru 255262e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 255362e4d438SSudarsana Reddy Kalluru if (!p_ptt) 255462e4d438SSudarsana Reddy Kalluru return -EBUSY; 255562e4d438SSudarsana Reddy Kalluru 255662e4d438SSudarsana Reddy Kalluru switch (cmd) { 255762e4d438SSudarsana Reddy Kalluru case QED_PUT_FILE_DATA: 255862e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 255962e4d438SSudarsana Reddy Kalluru break; 256062e4d438SSudarsana Reddy Kalluru case QED_NVM_WRITE_NVRAM: 256162e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 256262e4d438SSudarsana Reddy Kalluru break; 256362e4d438SSudarsana Reddy Kalluru default: 256462e4d438SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 256562e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 256662e4d438SSudarsana Reddy Kalluru goto out; 256762e4d438SSudarsana Reddy Kalluru } 256862e4d438SSudarsana Reddy Kalluru 256962e4d438SSudarsana Reddy Kalluru while (buf_idx < len) { 257062e4d438SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 257162e4d438SSudarsana Reddy Kalluru nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) | 257262e4d438SSudarsana Reddy Kalluru addr) + buf_idx; 257362e4d438SSudarsana Reddy Kalluru rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 257462e4d438SSudarsana Reddy Kalluru &resp, ¶m, buf_size, 257562e4d438SSudarsana Reddy Kalluru (u32 *)&p_buf[buf_idx]); 257662e4d438SSudarsana Reddy Kalluru if (rc) { 257762e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 257862e4d438SSudarsana Reddy Kalluru resp = FW_MSG_CODE_ERROR; 257962e4d438SSudarsana Reddy Kalluru break; 258062e4d438SSudarsana Reddy Kalluru } 258162e4d438SSudarsana Reddy Kalluru 258262e4d438SSudarsana Reddy Kalluru if (resp != FW_MSG_CODE_OK && 258362e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_OK && 258462e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 258562e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, 258662e4d438SSudarsana Reddy Kalluru "nvm write failed, resp = 0x%08x\n", resp); 258762e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 258862e4d438SSudarsana Reddy Kalluru break; 258962e4d438SSudarsana Reddy Kalluru } 259062e4d438SSudarsana Reddy Kalluru 259162e4d438SSudarsana Reddy Kalluru /* This can be a lengthy process, and it's possible scheduler 259262e4d438SSudarsana Reddy Kalluru * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 259362e4d438SSudarsana Reddy Kalluru */ 259462e4d438SSudarsana Reddy Kalluru if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 259562e4d438SSudarsana Reddy Kalluru usleep_range(1000, 2000); 259662e4d438SSudarsana Reddy Kalluru 259762e4d438SSudarsana Reddy Kalluru buf_idx += buf_size; 259862e4d438SSudarsana Reddy Kalluru } 259962e4d438SSudarsana Reddy Kalluru 260062e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 260162e4d438SSudarsana Reddy Kalluru out: 260262e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 260362e4d438SSudarsana Reddy Kalluru 260462e4d438SSudarsana Reddy Kalluru return rc; 260562e4d438SSudarsana Reddy Kalluru } 260662e4d438SSudarsana Reddy Kalluru 2607b51dab46SSudarsana Reddy Kalluru int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2608b51dab46SSudarsana Reddy Kalluru u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 2609b51dab46SSudarsana Reddy Kalluru { 2610b51dab46SSudarsana Reddy Kalluru u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 2611b51dab46SSudarsana Reddy Kalluru u32 resp, param; 2612b51dab46SSudarsana Reddy Kalluru int rc; 2613b51dab46SSudarsana Reddy Kalluru 2614b51dab46SSudarsana Reddy Kalluru nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 2615b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 2616b51dab46SSudarsana Reddy Kalluru nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 2617b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 2618b51dab46SSudarsana Reddy Kalluru 2619b51dab46SSudarsana Reddy Kalluru addr = offset; 2620b51dab46SSudarsana Reddy Kalluru offset = 0; 2621b51dab46SSudarsana Reddy Kalluru bytes_left = len; 2622b51dab46SSudarsana Reddy Kalluru while (bytes_left > 0) { 2623b51dab46SSudarsana Reddy Kalluru bytes_to_copy = min_t(u32, bytes_left, 2624b51dab46SSudarsana Reddy Kalluru MAX_I2C_TRANSACTION_SIZE); 2625b51dab46SSudarsana Reddy Kalluru nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 2626b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 2627b51dab46SSudarsana Reddy Kalluru nvm_offset |= ((addr + offset) << 2628b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 2629b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 2630b51dab46SSudarsana Reddy Kalluru nvm_offset |= (bytes_to_copy << 2631b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 2632b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 2633b51dab46SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2634b51dab46SSudarsana Reddy Kalluru DRV_MSG_CODE_TRANSCEIVER_READ, 2635b51dab46SSudarsana Reddy Kalluru nvm_offset, &resp, ¶m, &buf_size, 2636b51dab46SSudarsana Reddy Kalluru (u32 *)(p_buf + offset)); 2637b51dab46SSudarsana Reddy Kalluru if (rc) { 2638b51dab46SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 2639b51dab46SSudarsana Reddy Kalluru "Failed to send a transceiver read command to the MFW. rc = %d.\n", 2640b51dab46SSudarsana Reddy Kalluru rc); 2641b51dab46SSudarsana Reddy Kalluru return rc; 2642b51dab46SSudarsana Reddy Kalluru } 2643b51dab46SSudarsana Reddy Kalluru 2644b51dab46SSudarsana Reddy Kalluru if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 2645b51dab46SSudarsana Reddy Kalluru return -ENODEV; 2646b51dab46SSudarsana Reddy Kalluru else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 2647b51dab46SSudarsana Reddy Kalluru return -EINVAL; 2648b51dab46SSudarsana Reddy Kalluru 2649b51dab46SSudarsana Reddy Kalluru offset += buf_size; 2650b51dab46SSudarsana Reddy Kalluru bytes_left -= buf_size; 2651b51dab46SSudarsana Reddy Kalluru } 2652b51dab46SSudarsana Reddy Kalluru 2653b51dab46SSudarsana Reddy Kalluru return 0; 2654b51dab46SSudarsana Reddy Kalluru } 2655b51dab46SSudarsana Reddy Kalluru 265603dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 265703dc76caSSudarsana Reddy Kalluru { 265803dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 265903dc76caSSudarsana Reddy Kalluru int rc = 0; 266003dc76caSSudarsana Reddy Kalluru 266103dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 266203dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 266303dc76caSSudarsana Reddy Kalluru 266403dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 266503dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 266603dc76caSSudarsana Reddy Kalluru 266703dc76caSSudarsana Reddy Kalluru if (rc) 266803dc76caSSudarsana Reddy Kalluru return rc; 266903dc76caSSudarsana Reddy Kalluru 267003dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 267103dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 267203dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 267303dc76caSSudarsana Reddy Kalluru 267403dc76caSSudarsana Reddy Kalluru return rc; 267503dc76caSSudarsana Reddy Kalluru } 267603dc76caSSudarsana Reddy Kalluru 267703dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 267803dc76caSSudarsana Reddy Kalluru { 267903dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 268003dc76caSSudarsana Reddy Kalluru int rc = 0; 268103dc76caSSudarsana Reddy Kalluru 268203dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 268303dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 268403dc76caSSudarsana Reddy Kalluru 268503dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 268603dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 268703dc76caSSudarsana Reddy Kalluru 268803dc76caSSudarsana Reddy Kalluru if (rc) 268903dc76caSSudarsana Reddy Kalluru return rc; 269003dc76caSSudarsana Reddy Kalluru 269103dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 269203dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 269303dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 269403dc76caSSudarsana Reddy Kalluru 269503dc76caSSudarsana Reddy Kalluru return rc; 269603dc76caSSudarsana Reddy Kalluru } 26977a4b21b7SMintz, Yuval 269843645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 26997a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 27007a4b21b7SMintz, Yuval u32 *num_images) 27017a4b21b7SMintz, Yuval { 27027a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 27037a4b21b7SMintz, Yuval int rc = 0; 27047a4b21b7SMintz, Yuval 27057a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 27067a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 27077a4b21b7SMintz, Yuval 27087a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 27097a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 27107a4b21b7SMintz, Yuval if (rc) 27117a4b21b7SMintz, Yuval return rc; 27127a4b21b7SMintz, Yuval 27137a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 27147a4b21b7SMintz, Yuval rc = -EINVAL; 27157a4b21b7SMintz, Yuval 27167a4b21b7SMintz, Yuval return rc; 27177a4b21b7SMintz, Yuval } 27187a4b21b7SMintz, Yuval 271943645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 27207a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 27217a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 27227a4b21b7SMintz, Yuval u32 image_index) 27237a4b21b7SMintz, Yuval { 27247a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 27257a4b21b7SMintz, Yuval int rc; 27267a4b21b7SMintz, Yuval 27277a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 27287a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 27297a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 27307a4b21b7SMintz, Yuval 27317a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 27327a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 27337a4b21b7SMintz, Yuval &resp, &resp_param, 27347a4b21b7SMintz, Yuval &buf_size, 27357a4b21b7SMintz, Yuval (u32 *)p_image_att); 27367a4b21b7SMintz, Yuval if (rc) 27377a4b21b7SMintz, Yuval return rc; 27387a4b21b7SMintz, Yuval 27397a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 27407a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 27417a4b21b7SMintz, Yuval rc = -EINVAL; 27427a4b21b7SMintz, Yuval 27437a4b21b7SMintz, Yuval return rc; 27447a4b21b7SMintz, Yuval } 27452edbff8dSTomer Tayar 274643645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 274743645ce0SSudarsana Reddy Kalluru { 27485e7ba042SDenis Bolotin struct qed_nvm_image_info nvm_info; 274943645ce0SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 275043645ce0SSudarsana Reddy Kalluru int rc; 275143645ce0SSudarsana Reddy Kalluru u32 i; 275243645ce0SSudarsana Reddy Kalluru 27535e7ba042SDenis Bolotin if (p_hwfn->nvm_info.valid) 27545e7ba042SDenis Bolotin return 0; 27555e7ba042SDenis Bolotin 275643645ce0SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 275743645ce0SSudarsana Reddy Kalluru if (!p_ptt) { 275843645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "failed to acquire ptt\n"); 275943645ce0SSudarsana Reddy Kalluru return -EBUSY; 276043645ce0SSudarsana Reddy Kalluru } 276143645ce0SSudarsana Reddy Kalluru 276243645ce0SSudarsana Reddy Kalluru /* Acquire from MFW the amount of available images */ 27635e7ba042SDenis Bolotin nvm_info.num_images = 0; 276443645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 27655e7ba042SDenis Bolotin p_ptt, &nvm_info.num_images); 276643645ce0SSudarsana Reddy Kalluru if (rc == -EOPNOTSUPP) { 276743645ce0SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 276843645ce0SSudarsana Reddy Kalluru goto out; 27695e7ba042SDenis Bolotin } else if (rc || !nvm_info.num_images) { 277043645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Failed getting number of images\n"); 277143645ce0SSudarsana Reddy Kalluru goto err0; 277243645ce0SSudarsana Reddy Kalluru } 277343645ce0SSudarsana Reddy Kalluru 27745e7ba042SDenis Bolotin nvm_info.image_att = kmalloc_array(nvm_info.num_images, 277543645ce0SSudarsana Reddy Kalluru sizeof(struct bist_nvm_image_att), 277643645ce0SSudarsana Reddy Kalluru GFP_KERNEL); 27775e7ba042SDenis Bolotin if (!nvm_info.image_att) { 277843645ce0SSudarsana Reddy Kalluru rc = -ENOMEM; 277943645ce0SSudarsana Reddy Kalluru goto err0; 278043645ce0SSudarsana Reddy Kalluru } 278143645ce0SSudarsana Reddy Kalluru 278243645ce0SSudarsana Reddy Kalluru /* Iterate over images and get their attributes */ 27835e7ba042SDenis Bolotin for (i = 0; i < nvm_info.num_images; i++) { 278443645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 27855e7ba042SDenis Bolotin &nvm_info.image_att[i], i); 278643645ce0SSudarsana Reddy Kalluru if (rc) { 278743645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, 278843645ce0SSudarsana Reddy Kalluru "Failed getting image index %d attributes\n", i); 278943645ce0SSudarsana Reddy Kalluru goto err1; 279043645ce0SSudarsana Reddy Kalluru } 279143645ce0SSudarsana Reddy Kalluru 279243645ce0SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 27935e7ba042SDenis Bolotin nvm_info.image_att[i].len); 279443645ce0SSudarsana Reddy Kalluru } 279543645ce0SSudarsana Reddy Kalluru out: 27965e7ba042SDenis Bolotin /* Update hwfn's nvm_info */ 27975e7ba042SDenis Bolotin if (nvm_info.num_images) { 27985e7ba042SDenis Bolotin p_hwfn->nvm_info.num_images = nvm_info.num_images; 27995e7ba042SDenis Bolotin kfree(p_hwfn->nvm_info.image_att); 28005e7ba042SDenis Bolotin p_hwfn->nvm_info.image_att = nvm_info.image_att; 28015e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = true; 28025e7ba042SDenis Bolotin } 28035e7ba042SDenis Bolotin 280443645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 280543645ce0SSudarsana Reddy Kalluru return 0; 280643645ce0SSudarsana Reddy Kalluru 280743645ce0SSudarsana Reddy Kalluru err1: 28085e7ba042SDenis Bolotin kfree(nvm_info.image_att); 280943645ce0SSudarsana Reddy Kalluru err0: 281043645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 281143645ce0SSudarsana Reddy Kalluru return rc; 281243645ce0SSudarsana Reddy Kalluru } 281343645ce0SSudarsana Reddy Kalluru 28141ac4329aSDenis Bolotin int 281520675b37SMintz, Yuval qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 281620675b37SMintz, Yuval enum qed_nvm_images image_id, 281720675b37SMintz, Yuval struct qed_nvm_image_att *p_image_att) 281820675b37SMintz, Yuval { 281920675b37SMintz, Yuval enum nvm_image_type type; 282043645ce0SSudarsana Reddy Kalluru u32 i; 282120675b37SMintz, Yuval 282220675b37SMintz, Yuval /* Translate image_id into MFW definitions */ 282320675b37SMintz, Yuval switch (image_id) { 282420675b37SMintz, Yuval case QED_NVM_IMAGE_ISCSI_CFG: 282520675b37SMintz, Yuval type = NVM_TYPE_ISCSI_CFG; 282620675b37SMintz, Yuval break; 282720675b37SMintz, Yuval case QED_NVM_IMAGE_FCOE_CFG: 282820675b37SMintz, Yuval type = NVM_TYPE_FCOE_CFG; 282920675b37SMintz, Yuval break; 28301ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_CFG1: 28311ac4329aSDenis Bolotin type = NVM_TYPE_NVM_CFG1; 28321ac4329aSDenis Bolotin break; 28331ac4329aSDenis Bolotin case QED_NVM_IMAGE_DEFAULT_CFG: 28341ac4329aSDenis Bolotin type = NVM_TYPE_DEFAULT_CFG; 28351ac4329aSDenis Bolotin break; 28361ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_META: 28371ac4329aSDenis Bolotin type = NVM_TYPE_META; 28381ac4329aSDenis Bolotin break; 283920675b37SMintz, Yuval default: 284020675b37SMintz, Yuval DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 284120675b37SMintz, Yuval image_id); 284220675b37SMintz, Yuval return -EINVAL; 284320675b37SMintz, Yuval } 284420675b37SMintz, Yuval 28455e7ba042SDenis Bolotin qed_mcp_nvm_info_populate(p_hwfn); 284643645ce0SSudarsana Reddy Kalluru for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 284743645ce0SSudarsana Reddy Kalluru if (type == p_hwfn->nvm_info.image_att[i].image_type) 284820675b37SMintz, Yuval break; 284943645ce0SSudarsana Reddy Kalluru if (i == p_hwfn->nvm_info.num_images) { 285020675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 285120675b37SMintz, Yuval "Failed to find nvram image of type %08x\n", 285220675b37SMintz, Yuval image_id); 285343645ce0SSudarsana Reddy Kalluru return -ENOENT; 285420675b37SMintz, Yuval } 285520675b37SMintz, Yuval 285643645ce0SSudarsana Reddy Kalluru p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 285743645ce0SSudarsana Reddy Kalluru p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 285820675b37SMintz, Yuval 285920675b37SMintz, Yuval return 0; 286020675b37SMintz, Yuval } 286120675b37SMintz, Yuval 286220675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 286320675b37SMintz, Yuval enum qed_nvm_images image_id, 286420675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len) 286520675b37SMintz, Yuval { 286620675b37SMintz, Yuval struct qed_nvm_image_att image_att; 286720675b37SMintz, Yuval int rc; 286820675b37SMintz, Yuval 286920675b37SMintz, Yuval memset(p_buffer, 0, buffer_len); 287020675b37SMintz, Yuval 2871b60bfdfeSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 287220675b37SMintz, Yuval if (rc) 287320675b37SMintz, Yuval return rc; 287420675b37SMintz, Yuval 287520675b37SMintz, Yuval /* Validate sizes - both the image's and the supplied buffer's */ 287620675b37SMintz, Yuval if (image_att.length <= 4) { 287720675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 287820675b37SMintz, Yuval "Image [%d] is too small - only %d bytes\n", 287920675b37SMintz, Yuval image_id, image_att.length); 288020675b37SMintz, Yuval return -EINVAL; 288120675b37SMintz, Yuval } 288220675b37SMintz, Yuval 288320675b37SMintz, Yuval if (image_att.length > buffer_len) { 288420675b37SMintz, Yuval DP_VERBOSE(p_hwfn, 288520675b37SMintz, Yuval QED_MSG_STORAGE, 288620675b37SMintz, Yuval "Image [%d] is too big - %08x bytes where only %08x are available\n", 288720675b37SMintz, Yuval image_id, image_att.length, buffer_len); 288820675b37SMintz, Yuval return -ENOMEM; 288920675b37SMintz, Yuval } 289020675b37SMintz, Yuval 289120675b37SMintz, Yuval return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 289220675b37SMintz, Yuval p_buffer, image_att.length); 289320675b37SMintz, Yuval } 289420675b37SMintz, Yuval 28959c8517c4STomer Tayar static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 28969c8517c4STomer Tayar { 28979c8517c4STomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 28989c8517c4STomer Tayar 28999c8517c4STomer Tayar switch (res_id) { 29009c8517c4STomer Tayar case QED_SB: 29019c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 29029c8517c4STomer Tayar break; 29039c8517c4STomer Tayar case QED_L2_QUEUE: 29049c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 29059c8517c4STomer Tayar break; 29069c8517c4STomer Tayar case QED_VPORT: 29079c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 29089c8517c4STomer Tayar break; 29099c8517c4STomer Tayar case QED_RSS_ENG: 29109c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 29119c8517c4STomer Tayar break; 29129c8517c4STomer Tayar case QED_PQ: 29139c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 29149c8517c4STomer Tayar break; 29159c8517c4STomer Tayar case QED_RL: 29169c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 29179c8517c4STomer Tayar break; 29189c8517c4STomer Tayar case QED_MAC: 29199c8517c4STomer Tayar case QED_VLAN: 29209c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 29219c8517c4STomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 29229c8517c4STomer Tayar break; 29239c8517c4STomer Tayar case QED_ILT: 29249c8517c4STomer Tayar mfw_res_id = RESOURCE_ILT_E; 29259c8517c4STomer Tayar break; 29269c8517c4STomer Tayar case QED_LL2_QUEUE: 29279c8517c4STomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 29289c8517c4STomer Tayar break; 29299c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 29309c8517c4STomer Tayar case QED_CMDQS_CQS: 29319c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 29329c8517c4STomer Tayar mfw_res_id = RESOURCE_CQS_E; 29339c8517c4STomer Tayar break; 29349c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 29359c8517c4STomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 29369c8517c4STomer Tayar break; 29379c8517c4STomer Tayar case QED_BDQ: 29389c8517c4STomer Tayar mfw_res_id = RESOURCE_BDQ_E; 29399c8517c4STomer Tayar break; 29409c8517c4STomer Tayar default: 29419c8517c4STomer Tayar break; 29429c8517c4STomer Tayar } 29439c8517c4STomer Tayar 29449c8517c4STomer Tayar return mfw_res_id; 29459c8517c4STomer Tayar } 29469c8517c4STomer Tayar 29479c8517c4STomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 2 29482edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 29492edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 29502edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 29512edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 29522edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 29532edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 29549c8517c4STomer Tayar 29559c8517c4STomer Tayar struct qed_resc_alloc_in_params { 29569c8517c4STomer Tayar u32 cmd; 29579c8517c4STomer Tayar enum qed_resources res_id; 29589c8517c4STomer Tayar u32 resc_max_val; 29599c8517c4STomer Tayar }; 29609c8517c4STomer Tayar 29619c8517c4STomer Tayar struct qed_resc_alloc_out_params { 29629c8517c4STomer Tayar u32 mcp_resp; 29639c8517c4STomer Tayar u32 mcp_param; 29649c8517c4STomer Tayar u32 resc_num; 29659c8517c4STomer Tayar u32 resc_start; 29669c8517c4STomer Tayar u32 vf_resc_num; 29679c8517c4STomer Tayar u32 vf_resc_start; 29689c8517c4STomer Tayar u32 flags; 29699c8517c4STomer Tayar }; 29709c8517c4STomer Tayar 29719c8517c4STomer Tayar static int 29729c8517c4STomer Tayar qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 29732edbff8dSTomer Tayar struct qed_ptt *p_ptt, 29749c8517c4STomer Tayar struct qed_resc_alloc_in_params *p_in_params, 29759c8517c4STomer Tayar struct qed_resc_alloc_out_params *p_out_params) 29762edbff8dSTomer Tayar { 29772edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 29789c8517c4STomer Tayar struct resource_info mfw_resc_info; 29792edbff8dSTomer Tayar int rc; 29802edbff8dSTomer Tayar 29819c8517c4STomer Tayar memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 2982bb480242SMintz, Yuval 29839c8517c4STomer Tayar mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 29849c8517c4STomer Tayar if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 29859c8517c4STomer Tayar DP_ERR(p_hwfn, 29869c8517c4STomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 29879c8517c4STomer Tayar p_in_params->res_id, 29889c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id)); 29899c8517c4STomer Tayar return -EINVAL; 29909c8517c4STomer Tayar } 29919c8517c4STomer Tayar 29929c8517c4STomer Tayar switch (p_in_params->cmd) { 29939c8517c4STomer Tayar case DRV_MSG_SET_RESOURCE_VALUE_MSG: 29949c8517c4STomer Tayar mfw_resc_info.size = p_in_params->resc_max_val; 29959c8517c4STomer Tayar /* Fallthrough */ 29969c8517c4STomer Tayar case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 29979c8517c4STomer Tayar break; 29989c8517c4STomer Tayar default: 29999c8517c4STomer Tayar DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 30009c8517c4STomer Tayar p_in_params->cmd); 30019c8517c4STomer Tayar return -EINVAL; 30029c8517c4STomer Tayar } 30039c8517c4STomer Tayar 30049c8517c4STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 30059c8517c4STomer Tayar mb_params.cmd = p_in_params->cmd; 30069c8517c4STomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 30079c8517c4STomer Tayar mb_params.p_data_src = &mfw_resc_info; 30089c8517c4STomer Tayar mb_params.data_src_size = sizeof(mfw_resc_info); 30099c8517c4STomer Tayar mb_params.p_data_dst = mb_params.p_data_src; 30109c8517c4STomer Tayar mb_params.data_dst_size = mb_params.data_src_size; 30119c8517c4STomer Tayar 30129c8517c4STomer Tayar DP_VERBOSE(p_hwfn, 30139c8517c4STomer Tayar QED_MSG_SP, 30149c8517c4STomer Tayar "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 30159c8517c4STomer Tayar p_in_params->cmd, 30169c8517c4STomer Tayar p_in_params->res_id, 30179c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id), 30189c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 30199c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 30209c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 30219c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 30229c8517c4STomer Tayar p_in_params->resc_max_val); 30239c8517c4STomer Tayar 30242edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 30252edbff8dSTomer Tayar if (rc) 30262edbff8dSTomer Tayar return rc; 30272edbff8dSTomer Tayar 30289c8517c4STomer Tayar p_out_params->mcp_resp = mb_params.mcp_resp; 30299c8517c4STomer Tayar p_out_params->mcp_param = mb_params.mcp_param; 30309c8517c4STomer Tayar p_out_params->resc_num = mfw_resc_info.size; 30319c8517c4STomer Tayar p_out_params->resc_start = mfw_resc_info.offset; 30329c8517c4STomer Tayar p_out_params->vf_resc_num = mfw_resc_info.vf_size; 30339c8517c4STomer Tayar p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 30349c8517c4STomer Tayar p_out_params->flags = mfw_resc_info.flags; 30352edbff8dSTomer Tayar 30362edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 30372edbff8dSTomer Tayar QED_MSG_SP, 30389c8517c4STomer Tayar "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 30399c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 30409c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 30419c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 30429c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 30439c8517c4STomer Tayar p_out_params->resc_num, 30449c8517c4STomer Tayar p_out_params->resc_start, 30459c8517c4STomer Tayar p_out_params->vf_resc_num, 30469c8517c4STomer Tayar p_out_params->vf_resc_start, p_out_params->flags); 30479c8517c4STomer Tayar 30489c8517c4STomer Tayar return 0; 30499c8517c4STomer Tayar } 30509c8517c4STomer Tayar 30519c8517c4STomer Tayar int 30529c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 30539c8517c4STomer Tayar struct qed_ptt *p_ptt, 30549c8517c4STomer Tayar enum qed_resources res_id, 30559c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 30569c8517c4STomer Tayar { 30579c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 30589c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 30599c8517c4STomer Tayar int rc; 30609c8517c4STomer Tayar 30619c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 30629c8517c4STomer Tayar in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 30639c8517c4STomer Tayar in_params.res_id = res_id; 30649c8517c4STomer Tayar in_params.resc_max_val = resc_max_val; 30659c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 30669c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 30679c8517c4STomer Tayar &out_params); 30689c8517c4STomer Tayar if (rc) 30699c8517c4STomer Tayar return rc; 30709c8517c4STomer Tayar 30719c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 30729c8517c4STomer Tayar 30739c8517c4STomer Tayar return 0; 30749c8517c4STomer Tayar } 30759c8517c4STomer Tayar 30769c8517c4STomer Tayar int 30779c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 30789c8517c4STomer Tayar struct qed_ptt *p_ptt, 30799c8517c4STomer Tayar enum qed_resources res_id, 30809c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 30819c8517c4STomer Tayar { 30829c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 30839c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 30849c8517c4STomer Tayar int rc; 30859c8517c4STomer Tayar 30869c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 30879c8517c4STomer Tayar in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 30889c8517c4STomer Tayar in_params.res_id = res_id; 30899c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 30909c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 30919c8517c4STomer Tayar &out_params); 30929c8517c4STomer Tayar if (rc) 30939c8517c4STomer Tayar return rc; 30949c8517c4STomer Tayar 30959c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 30969c8517c4STomer Tayar 30979c8517c4STomer Tayar if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 30989c8517c4STomer Tayar *p_resc_num = out_params.resc_num; 30999c8517c4STomer Tayar *p_resc_start = out_params.resc_start; 31009c8517c4STomer Tayar } 31012edbff8dSTomer Tayar 31022edbff8dSTomer Tayar return 0; 31032edbff8dSTomer Tayar } 310418a69e36SMintz, Yuval 310518a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 310618a69e36SMintz, Yuval { 310718a69e36SMintz, Yuval u32 mcp_resp, mcp_param; 310818a69e36SMintz, Yuval 310918a69e36SMintz, Yuval return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 311018a69e36SMintz, Yuval &mcp_resp, &mcp_param); 311118a69e36SMintz, Yuval } 311295691c9cSTomer Tayar 311395691c9cSTomer Tayar static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 311495691c9cSTomer Tayar struct qed_ptt *p_ptt, 311595691c9cSTomer Tayar u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 311695691c9cSTomer Tayar { 311795691c9cSTomer Tayar int rc; 311895691c9cSTomer Tayar 311995691c9cSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 312095691c9cSTomer Tayar p_mcp_resp, p_mcp_param); 312195691c9cSTomer Tayar if (rc) 312295691c9cSTomer Tayar return rc; 312395691c9cSTomer Tayar 312495691c9cSTomer Tayar if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 312595691c9cSTomer Tayar DP_INFO(p_hwfn, 312695691c9cSTomer Tayar "The resource command is unsupported by the MFW\n"); 312795691c9cSTomer Tayar return -EINVAL; 312895691c9cSTomer Tayar } 312995691c9cSTomer Tayar 313095691c9cSTomer Tayar if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 313195691c9cSTomer Tayar u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 313295691c9cSTomer Tayar 313395691c9cSTomer Tayar DP_NOTICE(p_hwfn, 313495691c9cSTomer Tayar "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 313595691c9cSTomer Tayar param, opcode); 313695691c9cSTomer Tayar return -EINVAL; 313795691c9cSTomer Tayar } 313895691c9cSTomer Tayar 313995691c9cSTomer Tayar return rc; 314095691c9cSTomer Tayar } 314195691c9cSTomer Tayar 3142bf774d14SYueHaibing static int 314395691c9cSTomer Tayar __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 314495691c9cSTomer Tayar struct qed_ptt *p_ptt, 314595691c9cSTomer Tayar struct qed_resc_lock_params *p_params) 314695691c9cSTomer Tayar { 314795691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 314895691c9cSTomer Tayar u8 opcode; 314995691c9cSTomer Tayar int rc; 315095691c9cSTomer Tayar 315195691c9cSTomer Tayar switch (p_params->timeout) { 315295691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_DEFAULT: 315395691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ; 315495691c9cSTomer Tayar p_params->timeout = 0; 315595691c9cSTomer Tayar break; 315695691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_NONE: 315795691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_WO_AGING; 315895691c9cSTomer Tayar p_params->timeout = 0; 315995691c9cSTomer Tayar break; 316095691c9cSTomer Tayar default: 316195691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_W_AGING; 316295691c9cSTomer Tayar break; 316395691c9cSTomer Tayar } 316495691c9cSTomer Tayar 316595691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 316695691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 316795691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 316895691c9cSTomer Tayar 316995691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 317095691c9cSTomer Tayar QED_MSG_SP, 317195691c9cSTomer Tayar "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 317295691c9cSTomer Tayar param, p_params->timeout, opcode, p_params->resource); 317395691c9cSTomer Tayar 317495691c9cSTomer Tayar /* Attempt to acquire the resource */ 317595691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 317695691c9cSTomer Tayar if (rc) 317795691c9cSTomer Tayar return rc; 317895691c9cSTomer Tayar 317995691c9cSTomer Tayar /* Analyze the response */ 318095691c9cSTomer Tayar p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 318195691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 318295691c9cSTomer Tayar 318395691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 318495691c9cSTomer Tayar QED_MSG_SP, 318595691c9cSTomer Tayar "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 318695691c9cSTomer Tayar mcp_param, opcode, p_params->owner); 318795691c9cSTomer Tayar 318895691c9cSTomer Tayar switch (opcode) { 318995691c9cSTomer Tayar case RESOURCE_OPCODE_GNT: 319095691c9cSTomer Tayar p_params->b_granted = true; 319195691c9cSTomer Tayar break; 319295691c9cSTomer Tayar case RESOURCE_OPCODE_BUSY: 319395691c9cSTomer Tayar p_params->b_granted = false; 319495691c9cSTomer Tayar break; 319595691c9cSTomer Tayar default: 319695691c9cSTomer Tayar DP_NOTICE(p_hwfn, 319795691c9cSTomer Tayar "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 319895691c9cSTomer Tayar mcp_param, opcode); 319995691c9cSTomer Tayar return -EINVAL; 320095691c9cSTomer Tayar } 320195691c9cSTomer Tayar 320295691c9cSTomer Tayar return 0; 320395691c9cSTomer Tayar } 320495691c9cSTomer Tayar 320595691c9cSTomer Tayar int 320695691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 320795691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 320895691c9cSTomer Tayar { 320995691c9cSTomer Tayar u32 retry_cnt = 0; 321095691c9cSTomer Tayar int rc; 321195691c9cSTomer Tayar 321295691c9cSTomer Tayar do { 321395691c9cSTomer Tayar /* No need for an interval before the first iteration */ 321495691c9cSTomer Tayar if (retry_cnt) { 321595691c9cSTomer Tayar if (p_params->sleep_b4_retry) { 321695691c9cSTomer Tayar u16 retry_interval_in_ms = 321795691c9cSTomer Tayar DIV_ROUND_UP(p_params->retry_interval, 321895691c9cSTomer Tayar 1000); 321995691c9cSTomer Tayar 322095691c9cSTomer Tayar msleep(retry_interval_in_ms); 322195691c9cSTomer Tayar } else { 322295691c9cSTomer Tayar udelay(p_params->retry_interval); 322395691c9cSTomer Tayar } 322495691c9cSTomer Tayar } 322595691c9cSTomer Tayar 322695691c9cSTomer Tayar rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 322795691c9cSTomer Tayar if (rc) 322895691c9cSTomer Tayar return rc; 322995691c9cSTomer Tayar 323095691c9cSTomer Tayar if (p_params->b_granted) 323195691c9cSTomer Tayar break; 323295691c9cSTomer Tayar } while (retry_cnt++ < p_params->retry_num); 323395691c9cSTomer Tayar 323495691c9cSTomer Tayar return 0; 323595691c9cSTomer Tayar } 323695691c9cSTomer Tayar 323795691c9cSTomer Tayar int 323895691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 323995691c9cSTomer Tayar struct qed_ptt *p_ptt, 324095691c9cSTomer Tayar struct qed_resc_unlock_params *p_params) 324195691c9cSTomer Tayar { 324295691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 324395691c9cSTomer Tayar u8 opcode; 324495691c9cSTomer Tayar int rc; 324595691c9cSTomer Tayar 324695691c9cSTomer Tayar opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 324795691c9cSTomer Tayar : RESOURCE_OPCODE_RELEASE; 324895691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 324995691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 325095691c9cSTomer Tayar 325195691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 325295691c9cSTomer Tayar "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 325395691c9cSTomer Tayar param, opcode, p_params->resource); 325495691c9cSTomer Tayar 325595691c9cSTomer Tayar /* Attempt to release the resource */ 325695691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 325795691c9cSTomer Tayar if (rc) 325895691c9cSTomer Tayar return rc; 325995691c9cSTomer Tayar 326095691c9cSTomer Tayar /* Analyze the response */ 326195691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 326295691c9cSTomer Tayar 326395691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 326495691c9cSTomer Tayar "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 326595691c9cSTomer Tayar mcp_param, opcode); 326695691c9cSTomer Tayar 326795691c9cSTomer Tayar switch (opcode) { 326895691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED_PREVIOUS: 326995691c9cSTomer Tayar DP_INFO(p_hwfn, 327095691c9cSTomer Tayar "Resource unlock request for an already released resource [%d]\n", 327195691c9cSTomer Tayar p_params->resource); 327295691c9cSTomer Tayar /* Fallthrough */ 327395691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED: 327495691c9cSTomer Tayar p_params->b_released = true; 327595691c9cSTomer Tayar break; 327695691c9cSTomer Tayar case RESOURCE_OPCODE_WRONG_OWNER: 327795691c9cSTomer Tayar p_params->b_released = false; 327895691c9cSTomer Tayar break; 327995691c9cSTomer Tayar default: 328095691c9cSTomer Tayar DP_NOTICE(p_hwfn, 328195691c9cSTomer Tayar "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 328295691c9cSTomer Tayar mcp_param, opcode); 328395691c9cSTomer Tayar return -EINVAL; 328495691c9cSTomer Tayar } 328595691c9cSTomer Tayar 328695691c9cSTomer Tayar return 0; 328795691c9cSTomer Tayar } 3288f470f22cSsudarsana.kalluru@cavium.com 3289f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3290f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 3291f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 3292f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent) 3293f470f22cSsudarsana.kalluru@cavium.com { 3294f470f22cSsudarsana.kalluru@cavium.com if (p_lock) { 3295f470f22cSsudarsana.kalluru@cavium.com memset(p_lock, 0, sizeof(*p_lock)); 3296f470f22cSsudarsana.kalluru@cavium.com 3297f470f22cSsudarsana.kalluru@cavium.com /* Permanent resources don't require aging, and there's no 3298f470f22cSsudarsana.kalluru@cavium.com * point in trying to acquire them more than once since it's 3299f470f22cSsudarsana.kalluru@cavium.com * unexpected another entity would release them. 3300f470f22cSsudarsana.kalluru@cavium.com */ 3301f470f22cSsudarsana.kalluru@cavium.com if (b_is_permanent) { 3302f470f22cSsudarsana.kalluru@cavium.com p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3303f470f22cSsudarsana.kalluru@cavium.com } else { 3304f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3305f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_interval = 3306f470f22cSsudarsana.kalluru@cavium.com QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3307f470f22cSsudarsana.kalluru@cavium.com p_lock->sleep_b4_retry = true; 3308f470f22cSsudarsana.kalluru@cavium.com } 3309f470f22cSsudarsana.kalluru@cavium.com 3310f470f22cSsudarsana.kalluru@cavium.com p_lock->resource = resource; 3311f470f22cSsudarsana.kalluru@cavium.com } 3312f470f22cSsudarsana.kalluru@cavium.com 3313f470f22cSsudarsana.kalluru@cavium.com if (p_unlock) { 3314f470f22cSsudarsana.kalluru@cavium.com memset(p_unlock, 0, sizeof(*p_unlock)); 3315f470f22cSsudarsana.kalluru@cavium.com p_unlock->resource = resource; 3316f470f22cSsudarsana.kalluru@cavium.com } 3317f470f22cSsudarsana.kalluru@cavium.com } 3318645874e5SSudarsana Reddy Kalluru 3319645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3320645874e5SSudarsana Reddy Kalluru { 3321645874e5SSudarsana Reddy Kalluru u32 mcp_resp; 3322645874e5SSudarsana Reddy Kalluru int rc; 3323645874e5SSudarsana Reddy Kalluru 3324645874e5SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3325645874e5SSudarsana Reddy Kalluru 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3326645874e5SSudarsana Reddy Kalluru if (!rc) 3327645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3328645874e5SSudarsana Reddy Kalluru "MFW supported features: %08x\n", 3329645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->capabilities); 3330645874e5SSudarsana Reddy Kalluru 3331645874e5SSudarsana Reddy Kalluru return rc; 3332645874e5SSudarsana Reddy Kalluru } 3333645874e5SSudarsana Reddy Kalluru 3334645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3335645874e5SSudarsana Reddy Kalluru { 3336645874e5SSudarsana Reddy Kalluru u32 mcp_resp, mcp_param, features; 3337645874e5SSudarsana Reddy Kalluru 3338645874e5SSudarsana Reddy Kalluru features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE; 3339645874e5SSudarsana Reddy Kalluru 3340645874e5SSudarsana Reddy Kalluru return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3341645874e5SSudarsana Reddy Kalluru features, &mcp_resp, &mcp_param); 3342645874e5SSudarsana Reddy Kalluru } 3343