11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5fe56b9e6SYuval Mintz */ 6fe56b9e6SYuval Mintz 7fe56b9e6SYuval Mintz #include <linux/types.h> 8fe56b9e6SYuval Mintz #include <asm/byteorder.h> 9fe56b9e6SYuval Mintz #include <linux/delay.h> 10fe56b9e6SYuval Mintz #include <linux/errno.h> 11fe56b9e6SYuval Mintz #include <linux/kernel.h> 12fe56b9e6SYuval Mintz #include <linux/slab.h> 135529bad9STomer Tayar #include <linux/spinlock.h> 14fe56b9e6SYuval Mintz #include <linux/string.h> 150fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 16fe56b9e6SYuval Mintz #include "qed.h" 17cac6f691SSudarsana Reddy Kalluru #include "qed_cxt.h" 1839651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 19fe56b9e6SYuval Mintz #include "qed_hsi.h" 20fe56b9e6SYuval Mintz #include "qed_hw.h" 21fe56b9e6SYuval Mintz #include "qed_mcp.h" 22fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 231408cc1fSYuval Mintz #include "qed_sriov.h" 241408cc1fSYuval Mintz 250500a70dSMichal Kalderon #define GRCBASE_MCP 0xe00000 260500a70dSMichal Kalderon 27eaa50fc5STomer Tayar #define QED_MCP_RESP_ITER_US 10 28fe56b9e6SYuval Mintz 29fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 30fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 31fe56b9e6SYuval Mintz 32fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 33fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 34fe56b9e6SYuval Mintz _val) 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 37fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 38fe56b9e6SYuval Mintz 39fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 40fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 41fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 42fe56b9e6SYuval Mintz 43fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 44fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 45fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 46fe56b9e6SYuval Mintz 47fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 48fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 49fe56b9e6SYuval Mintz 50fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 51fe56b9e6SYuval Mintz 52fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 53fe56b9e6SYuval Mintz { 54fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 55fe56b9e6SYuval Mintz return false; 56fe56b9e6SYuval Mintz return true; 57fe56b9e6SYuval Mintz } 58fe56b9e6SYuval Mintz 591a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 60fe56b9e6SYuval Mintz { 61fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 62fe56b9e6SYuval Mintz PUBLIC_PORT); 63fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 64fe56b9e6SYuval Mintz 65fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 66fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 67fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 68fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 69fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 70fe56b9e6SYuval Mintz } 71fe56b9e6SYuval Mintz 721a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 73fe56b9e6SYuval Mintz { 74fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 75fe56b9e6SYuval Mintz u32 tmp, i; 76fe56b9e6SYuval Mintz 77fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 78fe56b9e6SYuval Mintz return; 79fe56b9e6SYuval Mintz 80fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 81fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 82fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 83fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 84fe56b9e6SYuval Mintz 85fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 86fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 87fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 88fe56b9e6SYuval Mintz } 89fe56b9e6SYuval Mintz } 90fe56b9e6SYuval Mintz 914ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 924ed1eea8STomer Tayar struct list_head list; 934ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 944ed1eea8STomer Tayar u16 expected_seq_num; 954ed1eea8STomer Tayar bool b_is_completed; 964ed1eea8STomer Tayar }; 974ed1eea8STomer Tayar 984ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 994ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1004ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1014ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1024ed1eea8STomer Tayar u16 expected_seq_num) 1034ed1eea8STomer Tayar { 1044ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1054ed1eea8STomer Tayar 1064ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1074ed1eea8STomer Tayar if (!p_cmd_elem) 1084ed1eea8STomer Tayar goto out; 1094ed1eea8STomer Tayar 1104ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1114ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1124ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1134ed1eea8STomer Tayar out: 1144ed1eea8STomer Tayar return p_cmd_elem; 1154ed1eea8STomer Tayar } 1164ed1eea8STomer Tayar 1174ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1184ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1194ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1204ed1eea8STomer Tayar { 1214ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1224ed1eea8STomer Tayar kfree(p_cmd_elem); 1234ed1eea8STomer Tayar } 1244ed1eea8STomer Tayar 1254ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1264ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1274ed1eea8STomer Tayar u16 seq_num) 1284ed1eea8STomer Tayar { 1294ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1304ed1eea8STomer Tayar 1314ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1324ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1334ed1eea8STomer Tayar return p_cmd_elem; 1344ed1eea8STomer Tayar } 1354ed1eea8STomer Tayar 1364ed1eea8STomer Tayar return NULL; 1374ed1eea8STomer Tayar } 1384ed1eea8STomer Tayar 139fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 140fe56b9e6SYuval Mintz { 141fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1424ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1434ed1eea8STomer Tayar 144fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 145fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1464ed1eea8STomer Tayar 1474ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1484ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1494ed1eea8STomer Tayar p_tmp, 1504ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1514ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 152fe56b9e6SYuval Mintz } 1534ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1544ed1eea8STomer Tayar } 1554ed1eea8STomer Tayar 156fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 1573587cb87STomer Tayar p_hwfn->mcp_info = NULL; 158fe56b9e6SYuval Mintz 159fe56b9e6SYuval Mintz return 0; 160fe56b9e6SYuval Mintz } 161fe56b9e6SYuval Mintz 162f00d25f3STomer Tayar /* Maximum of 1 sec to wait for the SHMEM ready indication */ 163f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_MAX_RETRIES 20 164f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_ITER_MS 50 165f00d25f3STomer Tayar 1661a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 167fe56b9e6SYuval Mintz { 168fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 169f00d25f3STomer Tayar u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES; 170f00d25f3STomer Tayar u8 msec = QED_MCP_SHMEM_RDY_ITER_MS; 171fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 172fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 173fe56b9e6SYuval Mintz 174fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 175f00d25f3STomer Tayar if (!p_info->public_base) { 176f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 177f00d25f3STomer Tayar "The address of the MCP scratch-pad is not configured\n"); 178f00d25f3STomer Tayar return -EINVAL; 179f00d25f3STomer Tayar } 180fe56b9e6SYuval Mintz 181fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 182fe56b9e6SYuval Mintz 183f00d25f3STomer Tayar /* Get the MFW MB address and number of supported messages */ 184f00d25f3STomer Tayar mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 185f00d25f3STomer Tayar SECTION_OFFSIZE_ADDR(p_info->public_base, 186f00d25f3STomer Tayar PUBLIC_MFW_MB)); 187f00d25f3STomer Tayar p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 188f00d25f3STomer Tayar p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, 189f00d25f3STomer Tayar p_info->mfw_mb_addr + 190f00d25f3STomer Tayar offsetof(struct public_mfw_mb, 191f00d25f3STomer Tayar sup_msgs)); 192f00d25f3STomer Tayar 193f00d25f3STomer Tayar /* The driver can notify that there was an MCP reset, and might read the 194f00d25f3STomer Tayar * SHMEM values before the MFW has completed initializing them. 195f00d25f3STomer Tayar * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a 196f00d25f3STomer Tayar * data ready indication. 197f00d25f3STomer Tayar */ 198f00d25f3STomer Tayar while (!p_info->mfw_mb_length && --cnt) { 199f00d25f3STomer Tayar msleep(msec); 200f00d25f3STomer Tayar p_info->mfw_mb_length = 201f00d25f3STomer Tayar (u16)qed_rd(p_hwfn, p_ptt, 202f00d25f3STomer Tayar p_info->mfw_mb_addr + 203f00d25f3STomer Tayar offsetof(struct public_mfw_mb, sup_msgs)); 204f00d25f3STomer Tayar } 205f00d25f3STomer Tayar 206f00d25f3STomer Tayar if (!cnt) { 207f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 208f00d25f3STomer Tayar "Failed to get the SHMEM ready notification after %d msec\n", 209f00d25f3STomer Tayar QED_MCP_SHMEM_RDY_MAX_RETRIES * msec); 210f00d25f3STomer Tayar return -EBUSY; 211f00d25f3STomer Tayar } 212f00d25f3STomer Tayar 213fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 214fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 215fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 216fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 217fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 218fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 219fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 220fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 221fe56b9e6SYuval Mintz 222fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 223fe56b9e6SYuval Mintz * the first command 224fe56b9e6SYuval Mintz */ 225fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 226fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 227fe56b9e6SYuval Mintz 228fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 229fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 230fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 231fe56b9e6SYuval Mintz 2324ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 233fe56b9e6SYuval Mintz 234fe56b9e6SYuval Mintz return 0; 235fe56b9e6SYuval Mintz } 236fe56b9e6SYuval Mintz 2371a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 238fe56b9e6SYuval Mintz { 239fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 240fe56b9e6SYuval Mintz u32 size; 241fe56b9e6SYuval Mintz 242fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 24360fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 244fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 245fe56b9e6SYuval Mintz goto err; 246fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 247fe56b9e6SYuval Mintz 2484ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2494ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2504ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2514ed1eea8STomer Tayar 2524ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2534ed1eea8STomer Tayar 254fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 255fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 256fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 257fe56b9e6SYuval Mintz * the MCP is not initialized 258fe56b9e6SYuval Mintz */ 259fe56b9e6SYuval Mintz return 0; 260fe56b9e6SYuval Mintz } 261fe56b9e6SYuval Mintz 262fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 26360fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 26483aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 265eb2a6b80SChristophe Jaillet if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 266fe56b9e6SYuval Mintz goto err; 267fe56b9e6SYuval Mintz 268fe56b9e6SYuval Mintz return 0; 269fe56b9e6SYuval Mintz 270fe56b9e6SYuval Mintz err: 271fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 272fe56b9e6SYuval Mintz return -ENOMEM; 273fe56b9e6SYuval Mintz } 274fe56b9e6SYuval Mintz 2754ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 2764ed1eea8STomer Tayar struct qed_ptt *p_ptt) 2775529bad9STomer Tayar { 2784ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 2795529bad9STomer Tayar 2804ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 2814ed1eea8STomer Tayar * time and now. 2825529bad9STomer Tayar */ 2834ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 2844ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 2854ed1eea8STomer Tayar QED_MSG_SP, 2864ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 2874ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 2885529bad9STomer Tayar 2894ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 2904ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2915529bad9STomer Tayar } 2925529bad9STomer Tayar } 2935529bad9STomer Tayar 2941a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 295fe56b9e6SYuval Mintz { 296eaa50fc5STomer Tayar u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0; 297fe56b9e6SYuval Mintz int rc = 0; 298fe56b9e6SYuval Mintz 299b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 300b310974eSTomer Tayar DP_NOTICE(p_hwfn, 301b310974eSTomer Tayar "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n"); 302b310974eSTomer Tayar return -EBUSY; 303b310974eSTomer Tayar } 304b310974eSTomer Tayar 3054ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 3064ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 3074ed1eea8STomer Tayar 3084ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3095529bad9STomer Tayar 310fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 3114ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 3124ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 3134ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 314fe56b9e6SYuval Mintz 315fe56b9e6SYuval Mintz do { 316fe56b9e6SYuval Mintz /* Wait for MFW response */ 317fe56b9e6SYuval Mintz udelay(delay); 318fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 319fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 320fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 321fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 322fe56b9e6SYuval Mintz 323fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 324fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 325fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 326fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 327fe56b9e6SYuval Mintz } else { 328fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 329fe56b9e6SYuval Mintz rc = -EAGAIN; 330fe56b9e6SYuval Mintz } 331fe56b9e6SYuval Mintz 3324ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3335529bad9STomer Tayar 334fe56b9e6SYuval Mintz return rc; 335fe56b9e6SYuval Mintz } 336fe56b9e6SYuval Mintz 3374ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3384ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 339fe56b9e6SYuval Mintz { 3404ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3414ed1eea8STomer Tayar 3424ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3434ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3444ed1eea8STomer Tayar */ 3454ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3464ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3474ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3484ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3494ed1eea8STomer Tayar } 3504ed1eea8STomer Tayar 3514ed1eea8STomer Tayar return false; 3524ed1eea8STomer Tayar } 3534ed1eea8STomer Tayar 3544ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3554ed1eea8STomer Tayar static int 3564ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3574ed1eea8STomer Tayar { 3584ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3594ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3604ed1eea8STomer Tayar u32 mcp_resp; 3614ed1eea8STomer Tayar u16 seq_num; 3624ed1eea8STomer Tayar 3634ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3644ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3654ed1eea8STomer Tayar 3664ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3674ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3684ed1eea8STomer Tayar return -EAGAIN; 3694ed1eea8STomer Tayar 3704ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3714ed1eea8STomer Tayar if (!p_cmd_elem) { 3724ed1eea8STomer Tayar DP_ERR(p_hwfn, 3734ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 3744ed1eea8STomer Tayar seq_num); 3754ed1eea8STomer Tayar return -EINVAL; 3764ed1eea8STomer Tayar } 3774ed1eea8STomer Tayar 3784ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 3794ed1eea8STomer Tayar 3804ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 3814ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 3824ed1eea8STomer Tayar 3834ed1eea8STomer Tayar /* Get the MFW param */ 3844ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 3854ed1eea8STomer Tayar 3864ed1eea8STomer Tayar /* Get the union data */ 3872f67af8cSTomer Tayar if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 3884ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3894ed1eea8STomer Tayar offsetof(struct public_drv_mb, 3904ed1eea8STomer Tayar union_data); 3914ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 3922f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 3934ed1eea8STomer Tayar } 3944ed1eea8STomer Tayar 3954ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 3964ed1eea8STomer Tayar 3974ed1eea8STomer Tayar return 0; 3984ed1eea8STomer Tayar } 3994ed1eea8STomer Tayar 4004ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 4014ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4024ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4034ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4044ed1eea8STomer Tayar u16 seq_num) 4054ed1eea8STomer Tayar { 4064ed1eea8STomer Tayar union drv_union_data union_data; 4074ed1eea8STomer Tayar u32 union_data_addr; 4084ed1eea8STomer Tayar 4094ed1eea8STomer Tayar /* Set the union data */ 4104ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4114ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 4124ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 4132f67af8cSTomer Tayar if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 4144ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 4152f67af8cSTomer Tayar p_mb_params->data_src_size); 4164ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4174ed1eea8STomer Tayar sizeof(union_data)); 4184ed1eea8STomer Tayar 4194ed1eea8STomer Tayar /* Set the drv param */ 4204ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4214ed1eea8STomer Tayar 4224ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4234ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4244ed1eea8STomer Tayar 4254ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4264ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4274ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4284ed1eea8STomer Tayar } 4294ed1eea8STomer Tayar 430b310974eSTomer Tayar static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd) 431b310974eSTomer Tayar { 432b310974eSTomer Tayar p_hwfn->mcp_info->b_block_cmd = block_cmd; 433b310974eSTomer Tayar 434b310974eSTomer Tayar DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n", 435b310974eSTomer Tayar block_cmd ? "Block" : "Unblock"); 436b310974eSTomer Tayar } 437b310974eSTomer Tayar 438b310974eSTomer Tayar static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn, 439b310974eSTomer Tayar struct qed_ptt *p_ptt) 440b310974eSTomer Tayar { 441b310974eSTomer Tayar u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2; 442b310974eSTomer Tayar u32 delay = QED_MCP_RESP_ITER_US; 443b310974eSTomer Tayar 444b310974eSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 445b310974eSTomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 446b310974eSTomer Tayar cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 447b310974eSTomer Tayar udelay(delay); 448b310974eSTomer Tayar cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 449b310974eSTomer Tayar udelay(delay); 450b310974eSTomer Tayar cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 451b310974eSTomer Tayar 452b310974eSTomer Tayar DP_NOTICE(p_hwfn, 453b310974eSTomer Tayar "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n", 454b310974eSTomer Tayar cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2); 455b310974eSTomer Tayar } 456b310974eSTomer Tayar 4574ed1eea8STomer Tayar static int 4584ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4594ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4604ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 461eaa50fc5STomer Tayar u32 max_retries, u32 usecs) 4624ed1eea8STomer Tayar { 463eaa50fc5STomer Tayar u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000); 4644ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4654ed1eea8STomer Tayar u16 seq_num; 466fe56b9e6SYuval Mintz int rc = 0; 467fe56b9e6SYuval Mintz 4684ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 469fe56b9e6SYuval Mintz do { 4704ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4714ed1eea8STomer Tayar * pending command is completed during this iteration. 4724ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4734ed1eea8STomer Tayar */ 4744ed1eea8STomer Tayar 4754ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4764ed1eea8STomer Tayar 4774ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 4784ed1eea8STomer Tayar break; 4794ed1eea8STomer Tayar 4804ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 4814ed1eea8STomer Tayar if (!rc) 4824ed1eea8STomer Tayar break; 4834ed1eea8STomer Tayar else if (rc != -EAGAIN) 4844ed1eea8STomer Tayar goto err; 4854ed1eea8STomer Tayar 4864ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 487eaa50fc5STomer Tayar 488eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 489eaa50fc5STomer Tayar msleep(msecs); 490eaa50fc5STomer Tayar else 491eaa50fc5STomer Tayar udelay(usecs); 4924ed1eea8STomer Tayar } while (++cnt < max_retries); 493fe56b9e6SYuval Mintz 4944ed1eea8STomer Tayar if (cnt >= max_retries) { 4954ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 4964ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 4974ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 4984ed1eea8STomer Tayar return -EAGAIN; 499fe56b9e6SYuval Mintz } 5004ed1eea8STomer Tayar 5014ed1eea8STomer Tayar /* Send the mailbox command */ 5024ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 5034ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 5044ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 505c8004600SDan Carpenter if (!p_cmd_elem) { 506c8004600SDan Carpenter rc = -ENOMEM; 5074ed1eea8STomer Tayar goto err; 508c8004600SDan Carpenter } 5094ed1eea8STomer Tayar 5104ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 5114ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5124ed1eea8STomer Tayar 5134ed1eea8STomer Tayar /* Wait for the MFW response */ 5144ed1eea8STomer Tayar do { 5154ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 5164ed1eea8STomer Tayar * command is completed during this iteration. 5174ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 5184ed1eea8STomer Tayar */ 5194ed1eea8STomer Tayar 520eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 521eaa50fc5STomer Tayar msleep(msecs); 522eaa50fc5STomer Tayar else 523eaa50fc5STomer Tayar udelay(usecs); 524eaa50fc5STomer Tayar 5254ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5264ed1eea8STomer Tayar 5274ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 5284ed1eea8STomer Tayar break; 5294ed1eea8STomer Tayar 5304ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5314ed1eea8STomer Tayar if (!rc) 5324ed1eea8STomer Tayar break; 5334ed1eea8STomer Tayar else if (rc != -EAGAIN) 5344ed1eea8STomer Tayar goto err; 5354ed1eea8STomer Tayar 5364ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5374ed1eea8STomer Tayar } while (++cnt < max_retries); 5384ed1eea8STomer Tayar 5394ed1eea8STomer Tayar if (cnt >= max_retries) { 5404ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5414ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 5424ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 543b310974eSTomer Tayar qed_mcp_print_cpu_info(p_hwfn, p_ptt); 5444ed1eea8STomer Tayar 5454ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5464ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5474ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5484ed1eea8STomer Tayar 549b310974eSTomer Tayar if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK)) 550b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 551b310974eSTomer Tayar 5522ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, 5532ec276d5SIgor Russkikh QED_HW_ERR_MFW_RESP_FAIL, NULL); 5544ed1eea8STomer Tayar return -EAGAIN; 5554ed1eea8STomer Tayar } 5564ed1eea8STomer Tayar 5574ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5584ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5594ed1eea8STomer Tayar 5604ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5614ed1eea8STomer Tayar QED_MSG_SP, 5624ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5634ed1eea8STomer Tayar p_mb_params->mcp_resp, 5644ed1eea8STomer Tayar p_mb_params->mcp_param, 565eaa50fc5STomer Tayar (cnt * usecs) / 1000, (cnt * usecs) % 1000); 5664ed1eea8STomer Tayar 5674ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5684ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5694ed1eea8STomer Tayar 5704ed1eea8STomer Tayar return 0; 5714ed1eea8STomer Tayar 5724ed1eea8STomer Tayar err: 5734ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 574fe56b9e6SYuval Mintz return rc; 575fe56b9e6SYuval Mintz } 576fe56b9e6SYuval Mintz 5775529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 578fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 5795529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 580fe56b9e6SYuval Mintz { 5812f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 5824ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 583eaa50fc5STomer Tayar u32 usecs = QED_MCP_RESP_ITER_US; 584fe56b9e6SYuval Mintz 585fe56b9e6SYuval Mintz /* MCP not initialized */ 586fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 587fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 588fe56b9e6SYuval Mintz return -EBUSY; 589fe56b9e6SYuval Mintz } 590fe56b9e6SYuval Mintz 591b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 592b310974eSTomer Tayar DP_NOTICE(p_hwfn, 593b310974eSTomer Tayar "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n", 594b310974eSTomer Tayar p_mb_params->cmd, p_mb_params->param); 595b310974eSTomer Tayar return -EBUSY; 596b310974eSTomer Tayar } 597b310974eSTomer Tayar 5982f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 5992f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 6002f67af8cSTomer Tayar DP_ERR(p_hwfn, 6012f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 6022f67af8cSTomer Tayar p_mb_params->data_src_size, 6032f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 6042f67af8cSTomer Tayar return -EINVAL; 6052f67af8cSTomer Tayar } 6062f67af8cSTomer Tayar 607eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) { 608eaa50fc5STomer Tayar max_retries = DIV_ROUND_UP(max_retries, 1000); 609eaa50fc5STomer Tayar usecs *= 1000; 610eaa50fc5STomer Tayar } 611eaa50fc5STomer Tayar 6124ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 613eaa50fc5STomer Tayar usecs); 614fe56b9e6SYuval Mintz } 615fe56b9e6SYuval Mintz 6165529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 6175529bad9STomer Tayar struct qed_ptt *p_ptt, 6185529bad9STomer Tayar u32 cmd, 6195529bad9STomer Tayar u32 param, 6205529bad9STomer Tayar u32 *o_mcp_resp, 6215529bad9STomer Tayar u32 *o_mcp_param) 622fe56b9e6SYuval Mintz { 6235529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 6245529bad9STomer Tayar int rc; 625fe56b9e6SYuval Mintz 6265529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6275529bad9STomer Tayar mb_params.cmd = cmd; 6285529bad9STomer Tayar mb_params.param = param; 62914d39648SMintz, Yuval 6305529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6315529bad9STomer Tayar if (rc) 6325529bad9STomer Tayar return rc; 6335529bad9STomer Tayar 6345529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6355529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 6365529bad9STomer Tayar 6375529bad9STomer Tayar return 0; 638fe56b9e6SYuval Mintz } 639fe56b9e6SYuval Mintz 640bf774d14SYueHaibing static int 641bf774d14SYueHaibing qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 64262e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 64362e4d438SSudarsana Reddy Kalluru u32 cmd, 64462e4d438SSudarsana Reddy Kalluru u32 param, 64562e4d438SSudarsana Reddy Kalluru u32 *o_mcp_resp, 64662e4d438SSudarsana Reddy Kalluru u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 64762e4d438SSudarsana Reddy Kalluru { 64862e4d438SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 64962e4d438SSudarsana Reddy Kalluru int rc; 65062e4d438SSudarsana Reddy Kalluru 65162e4d438SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 65262e4d438SSudarsana Reddy Kalluru mb_params.cmd = cmd; 65362e4d438SSudarsana Reddy Kalluru mb_params.param = param; 65462e4d438SSudarsana Reddy Kalluru mb_params.p_data_src = i_buf; 65562e4d438SSudarsana Reddy Kalluru mb_params.data_src_size = (u8)i_txn_size; 65662e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 65762e4d438SSudarsana Reddy Kalluru if (rc) 65862e4d438SSudarsana Reddy Kalluru return rc; 65962e4d438SSudarsana Reddy Kalluru 66062e4d438SSudarsana Reddy Kalluru *o_mcp_resp = mb_params.mcp_resp; 66162e4d438SSudarsana Reddy Kalluru *o_mcp_param = mb_params.mcp_param; 66262e4d438SSudarsana Reddy Kalluru 6635e7ba042SDenis Bolotin /* nvm_info needs to be updated */ 6645e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = false; 6655e7ba042SDenis Bolotin 66662e4d438SSudarsana Reddy Kalluru return 0; 66762e4d438SSudarsana Reddy Kalluru } 66862e4d438SSudarsana Reddy Kalluru 6694102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 6704102426fSTomer Tayar struct qed_ptt *p_ptt, 6714102426fSTomer Tayar u32 cmd, 6724102426fSTomer Tayar u32 param, 6734102426fSTomer Tayar u32 *o_mcp_resp, 6744102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 6754102426fSTomer Tayar { 6764102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 6772f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 6784102426fSTomer Tayar int rc; 6794102426fSTomer Tayar 6804102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6814102426fSTomer Tayar mb_params.cmd = cmd; 6824102426fSTomer Tayar mb_params.param = param; 6832f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 6842f67af8cSTomer Tayar 6852f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 6862f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 6872f67af8cSTomer Tayar 6884102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6894102426fSTomer Tayar if (rc) 6904102426fSTomer Tayar return rc; 6914102426fSTomer Tayar 6924102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6934102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 6944102426fSTomer Tayar 6954102426fSTomer Tayar *o_txn_size = *o_mcp_param; 6962f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 6974102426fSTomer Tayar 6984102426fSTomer Tayar return 0; 6994102426fSTomer Tayar } 7004102426fSTomer Tayar 7015d24bcf1STomer Tayar static bool 7025d24bcf1STomer Tayar qed_mcp_can_force_load(u8 drv_role, 7035d24bcf1STomer Tayar u8 exist_drv_role, 7045d24bcf1STomer Tayar enum qed_override_force_load override_force_load) 705fe56b9e6SYuval Mintz { 7065d24bcf1STomer Tayar bool can_force_load = false; 7075d24bcf1STomer Tayar 7085d24bcf1STomer Tayar switch (override_force_load) { 7095d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 7105d24bcf1STomer Tayar can_force_load = true; 7115d24bcf1STomer Tayar break; 7125d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_NEVER: 7135d24bcf1STomer Tayar can_force_load = false; 7145d24bcf1STomer Tayar break; 7155d24bcf1STomer Tayar default: 7165d24bcf1STomer Tayar can_force_load = (drv_role == DRV_ROLE_OS && 7175d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_PREBOOT) || 7185d24bcf1STomer Tayar (drv_role == DRV_ROLE_KDUMP && 7195d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_OS); 7205d24bcf1STomer Tayar break; 7215d24bcf1STomer Tayar } 7225d24bcf1STomer Tayar 7235d24bcf1STomer Tayar return can_force_load; 7245d24bcf1STomer Tayar } 7255d24bcf1STomer Tayar 7265d24bcf1STomer Tayar static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 7275d24bcf1STomer Tayar struct qed_ptt *p_ptt) 7285d24bcf1STomer Tayar { 7295d24bcf1STomer Tayar u32 resp = 0, param = 0; 730fe56b9e6SYuval Mintz int rc; 731fe56b9e6SYuval Mintz 7325d24bcf1STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 7335d24bcf1STomer Tayar &resp, ¶m); 7345d24bcf1STomer Tayar if (rc) 7355d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 7365d24bcf1STomer Tayar "Failed to send cancel load request, rc = %d\n", rc); 737fe56b9e6SYuval Mintz 738fe56b9e6SYuval Mintz return rc; 739fe56b9e6SYuval Mintz } 740fe56b9e6SYuval Mintz 7415d24bcf1STomer Tayar #define CONFIG_QEDE_BITMAP_IDX BIT(0) 7425d24bcf1STomer Tayar #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 7435d24bcf1STomer Tayar #define CONFIG_QEDR_BITMAP_IDX BIT(2) 7445d24bcf1STomer Tayar #define CONFIG_QEDF_BITMAP_IDX BIT(4) 7455d24bcf1STomer Tayar #define CONFIG_QEDI_BITMAP_IDX BIT(5) 7465d24bcf1STomer Tayar #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 7475529bad9STomer Tayar 7485d24bcf1STomer Tayar static u32 qed_get_config_bitmap(void) 7495d24bcf1STomer Tayar { 7505d24bcf1STomer Tayar u32 config_bitmap = 0x0; 7515d24bcf1STomer Tayar 7525d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QEDE)) 7535d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 7545d24bcf1STomer Tayar 7555d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_SRIOV)) 7565d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 7575d24bcf1STomer Tayar 7585d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_RDMA)) 7595d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 7605d24bcf1STomer Tayar 7615d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_FCOE)) 7625d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 7635d24bcf1STomer Tayar 7645d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_ISCSI)) 7655d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 7665d24bcf1STomer Tayar 7675d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_LL2)) 7685d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 7695d24bcf1STomer Tayar 7705d24bcf1STomer Tayar return config_bitmap; 7715d24bcf1STomer Tayar } 7725d24bcf1STomer Tayar 7735d24bcf1STomer Tayar struct qed_load_req_in_params { 7745d24bcf1STomer Tayar u8 hsi_ver; 7755d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 7765d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_1 1 7775d24bcf1STomer Tayar u32 drv_ver_0; 7785d24bcf1STomer Tayar u32 drv_ver_1; 7795d24bcf1STomer Tayar u32 fw_ver; 7805d24bcf1STomer Tayar u8 drv_role; 7815d24bcf1STomer Tayar u8 timeout_val; 7825d24bcf1STomer Tayar u8 force_cmd; 7835d24bcf1STomer Tayar bool avoid_eng_reset; 7845d24bcf1STomer Tayar }; 7855d24bcf1STomer Tayar 7865d24bcf1STomer Tayar struct qed_load_req_out_params { 7875d24bcf1STomer Tayar u32 load_code; 7885d24bcf1STomer Tayar u32 exist_drv_ver_0; 7895d24bcf1STomer Tayar u32 exist_drv_ver_1; 7905d24bcf1STomer Tayar u32 exist_fw_ver; 7915d24bcf1STomer Tayar u8 exist_drv_role; 7925d24bcf1STomer Tayar u8 mfw_hsi_ver; 7935d24bcf1STomer Tayar bool drv_exists; 7945d24bcf1STomer Tayar }; 7955d24bcf1STomer Tayar 7965d24bcf1STomer Tayar static int 7975d24bcf1STomer Tayar __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 7985d24bcf1STomer Tayar struct qed_ptt *p_ptt, 7995d24bcf1STomer Tayar struct qed_load_req_in_params *p_in_params, 8005d24bcf1STomer Tayar struct qed_load_req_out_params *p_out_params) 8015d24bcf1STomer Tayar { 8025d24bcf1STomer Tayar struct qed_mcp_mb_params mb_params; 8035d24bcf1STomer Tayar struct load_req_stc load_req; 8045d24bcf1STomer Tayar struct load_rsp_stc load_rsp; 8055d24bcf1STomer Tayar u32 hsi_ver; 8065d24bcf1STomer Tayar int rc; 8075d24bcf1STomer Tayar 8085d24bcf1STomer Tayar memset(&load_req, 0, sizeof(load_req)); 8095d24bcf1STomer Tayar load_req.drv_ver_0 = p_in_params->drv_ver_0; 8105d24bcf1STomer Tayar load_req.drv_ver_1 = p_in_params->drv_ver_1; 8115d24bcf1STomer Tayar load_req.fw_ver = p_in_params->fw_ver; 8125d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 8135d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 8145d24bcf1STomer Tayar p_in_params->timeout_val); 8155d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 8165d24bcf1STomer Tayar p_in_params->force_cmd); 8175d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 8185d24bcf1STomer Tayar p_in_params->avoid_eng_reset); 8195d24bcf1STomer Tayar 8205d24bcf1STomer Tayar hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 8215d24bcf1STomer Tayar DRV_ID_MCP_HSI_VER_CURRENT : 8225d24bcf1STomer Tayar (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 8235d24bcf1STomer Tayar 8245d24bcf1STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 8255d24bcf1STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 8265d24bcf1STomer Tayar mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 8275d24bcf1STomer Tayar mb_params.p_data_src = &load_req; 8285d24bcf1STomer Tayar mb_params.data_src_size = sizeof(load_req); 8295d24bcf1STomer Tayar mb_params.p_data_dst = &load_rsp; 8305d24bcf1STomer Tayar mb_params.data_dst_size = sizeof(load_rsp); 831b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 8325d24bcf1STomer Tayar 8335d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8345d24bcf1STomer Tayar "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 8355d24bcf1STomer Tayar mb_params.param, 8365d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 8375d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 8385d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 8395d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 8405d24bcf1STomer Tayar 8415d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 8425d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8435d24bcf1STomer Tayar "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 8445d24bcf1STomer Tayar load_req.drv_ver_0, 8455d24bcf1STomer Tayar load_req.drv_ver_1, 8465d24bcf1STomer Tayar load_req.fw_ver, 8475d24bcf1STomer Tayar load_req.misc0, 8485d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 8495d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, 8505d24bcf1STomer Tayar LOAD_REQ_LOCK_TO), 8515d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 8525d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 8535d24bcf1STomer Tayar } 8545d24bcf1STomer Tayar 8555d24bcf1STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 8565d24bcf1STomer Tayar if (rc) { 8575d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 8585d24bcf1STomer Tayar return rc; 8595d24bcf1STomer Tayar } 8605d24bcf1STomer Tayar 8615d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8625d24bcf1STomer Tayar "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 8635d24bcf1STomer Tayar p_out_params->load_code = mb_params.mcp_resp; 8645d24bcf1STomer Tayar 8655d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 8665d24bcf1STomer Tayar p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 8675d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, 8685d24bcf1STomer Tayar QED_MSG_SP, 8695d24bcf1STomer Tayar "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 8705d24bcf1STomer Tayar load_rsp.drv_ver_0, 8715d24bcf1STomer Tayar load_rsp.drv_ver_1, 8725d24bcf1STomer Tayar load_rsp.fw_ver, 8735d24bcf1STomer Tayar load_rsp.misc0, 8745d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 8755d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 8765d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 8775d24bcf1STomer Tayar 8785d24bcf1STomer Tayar p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 8795d24bcf1STomer Tayar p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 8805d24bcf1STomer Tayar p_out_params->exist_fw_ver = load_rsp.fw_ver; 8815d24bcf1STomer Tayar p_out_params->exist_drv_role = 8825d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 8835d24bcf1STomer Tayar p_out_params->mfw_hsi_ver = 8845d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 8855d24bcf1STomer Tayar p_out_params->drv_exists = 8865d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 8875d24bcf1STomer Tayar LOAD_RSP_FLAGS0_DRV_EXISTS; 8885d24bcf1STomer Tayar } 8895d24bcf1STomer Tayar 8905d24bcf1STomer Tayar return 0; 8915d24bcf1STomer Tayar } 8925d24bcf1STomer Tayar 8935d24bcf1STomer Tayar static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 8945d24bcf1STomer Tayar enum qed_drv_role drv_role, 8955d24bcf1STomer Tayar u8 *p_mfw_drv_role) 8965d24bcf1STomer Tayar { 8975d24bcf1STomer Tayar switch (drv_role) { 8985d24bcf1STomer Tayar case QED_DRV_ROLE_OS: 8995d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_OS; 9005d24bcf1STomer Tayar break; 9015d24bcf1STomer Tayar case QED_DRV_ROLE_KDUMP: 9025d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_KDUMP; 9035d24bcf1STomer Tayar break; 9045d24bcf1STomer Tayar default: 9055d24bcf1STomer Tayar DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 9065d24bcf1STomer Tayar return -EINVAL; 9075d24bcf1STomer Tayar } 9085d24bcf1STomer Tayar 9095d24bcf1STomer Tayar return 0; 9105d24bcf1STomer Tayar } 9115d24bcf1STomer Tayar 9125d24bcf1STomer Tayar enum qed_load_req_force { 9135d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, 9145d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_PF, 9155d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9165d24bcf1STomer Tayar }; 9175d24bcf1STomer Tayar 9185d24bcf1STomer Tayar static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 9195d24bcf1STomer Tayar 9205d24bcf1STomer Tayar enum qed_load_req_force force_cmd, 9215d24bcf1STomer Tayar u8 *p_mfw_force_cmd) 9225d24bcf1STomer Tayar { 9235d24bcf1STomer Tayar switch (force_cmd) { 9245d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_NONE: 9255d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 9265d24bcf1STomer Tayar break; 9275d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_PF: 9285d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 9295d24bcf1STomer Tayar break; 9305d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_ALL: 9315d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 9325d24bcf1STomer Tayar break; 9335d24bcf1STomer Tayar } 9345d24bcf1STomer Tayar } 9355d24bcf1STomer Tayar 9365d24bcf1STomer Tayar int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 9375d24bcf1STomer Tayar struct qed_ptt *p_ptt, 9385d24bcf1STomer Tayar struct qed_load_req_params *p_params) 9395d24bcf1STomer Tayar { 9405d24bcf1STomer Tayar struct qed_load_req_out_params out_params; 9415d24bcf1STomer Tayar struct qed_load_req_in_params in_params; 9425d24bcf1STomer Tayar u8 mfw_drv_role, mfw_force_cmd; 9435d24bcf1STomer Tayar int rc; 9445d24bcf1STomer Tayar 9455d24bcf1STomer Tayar memset(&in_params, 0, sizeof(in_params)); 9465d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 9475d24bcf1STomer Tayar in_params.drv_ver_0 = QED_VERSION; 9485d24bcf1STomer Tayar in_params.drv_ver_1 = qed_get_config_bitmap(); 9495d24bcf1STomer Tayar in_params.fw_ver = STORM_FW_VERSION; 9505d24bcf1STomer Tayar rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 9515d24bcf1STomer Tayar if (rc) 9525d24bcf1STomer Tayar return rc; 9535d24bcf1STomer Tayar 9545d24bcf1STomer Tayar in_params.drv_role = mfw_drv_role; 9555d24bcf1STomer Tayar in_params.timeout_val = p_params->timeout_val; 9565d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9575d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 9585d24bcf1STomer Tayar 9595d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9605d24bcf1STomer Tayar in_params.avoid_eng_reset = p_params->avoid_eng_reset; 9615d24bcf1STomer Tayar 9625d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9635d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9645d24bcf1STomer Tayar if (rc) 9655d24bcf1STomer Tayar return rc; 9665d24bcf1STomer Tayar 9675d24bcf1STomer Tayar /* First handle cases where another load request should/might be sent: 9685d24bcf1STomer Tayar * - MFW expects the old interface [HSI version = 1] 9695d24bcf1STomer Tayar * - MFW responds that a force load request is required 970fe56b9e6SYuval Mintz */ 9715d24bcf1STomer Tayar if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 9725d24bcf1STomer Tayar DP_INFO(p_hwfn, 9735d24bcf1STomer Tayar "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 9745d24bcf1STomer Tayar 9755d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 9765d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9775d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9785d24bcf1STomer Tayar if (rc) 9795d24bcf1STomer Tayar return rc; 9805d24bcf1STomer Tayar } else if (out_params.load_code == 9815d24bcf1STomer Tayar FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 9825d24bcf1STomer Tayar if (qed_mcp_can_force_load(in_params.drv_role, 9835d24bcf1STomer Tayar out_params.exist_drv_role, 9845d24bcf1STomer Tayar p_params->override_force_load)) { 9855d24bcf1STomer Tayar DP_INFO(p_hwfn, 9865d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 9875d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 9885d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 9895d24bcf1STomer Tayar out_params.exist_drv_role, 9905d24bcf1STomer Tayar out_params.exist_fw_ver, 9915d24bcf1STomer Tayar out_params.exist_drv_ver_0, 9925d24bcf1STomer Tayar out_params.exist_drv_ver_1); 9935d24bcf1STomer Tayar 9945d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9955d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9965d24bcf1STomer Tayar &mfw_force_cmd); 9975d24bcf1STomer Tayar 9985d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9995d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 10005d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 10015d24bcf1STomer Tayar &out_params); 10025d24bcf1STomer Tayar if (rc) 10035d24bcf1STomer Tayar return rc; 10045d24bcf1STomer Tayar } else { 10055d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10065d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 10075d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10085d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10095d24bcf1STomer Tayar out_params.exist_drv_role, 10105d24bcf1STomer Tayar out_params.exist_fw_ver, 10115d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10125d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10135d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10145d24bcf1STomer Tayar "Avoid sending a force load request to prevent disruption of active PFs\n"); 10155d24bcf1STomer Tayar 10165d24bcf1STomer Tayar qed_mcp_cancel_load_req(p_hwfn, p_ptt); 1017fe56b9e6SYuval Mintz return -EBUSY; 1018fe56b9e6SYuval Mintz } 10195d24bcf1STomer Tayar } 10205d24bcf1STomer Tayar 10215d24bcf1STomer Tayar /* Now handle the other types of responses. 10225d24bcf1STomer Tayar * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 10235d24bcf1STomer Tayar * expected here after the additional revised load requests were sent. 10245d24bcf1STomer Tayar */ 10255d24bcf1STomer Tayar switch (out_params.load_code) { 10265d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_ENGINE: 10275d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_PORT: 10285d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_FUNCTION: 10295d24bcf1STomer Tayar if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 10305d24bcf1STomer Tayar out_params.drv_exists) { 10315d24bcf1STomer Tayar /* The role and fw/driver version match, but the PF is 10325d24bcf1STomer Tayar * already loaded and has not been unloaded gracefully. 10335d24bcf1STomer Tayar */ 10345d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10355d24bcf1STomer Tayar "PF is already loaded\n"); 10365d24bcf1STomer Tayar return -EINVAL; 10375d24bcf1STomer Tayar } 10385d24bcf1STomer Tayar break; 10395d24bcf1STomer Tayar default: 10405d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10415d24bcf1STomer Tayar "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 10425d24bcf1STomer Tayar out_params.load_code); 10435d24bcf1STomer Tayar return -EBUSY; 10445d24bcf1STomer Tayar } 10455d24bcf1STomer Tayar 10465d24bcf1STomer Tayar p_params->load_code = out_params.load_code; 1047fe56b9e6SYuval Mintz 1048fe56b9e6SYuval Mintz return 0; 1049fe56b9e6SYuval Mintz } 1050fe56b9e6SYuval Mintz 1051666db486STomer Tayar int qed_mcp_load_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1052666db486STomer Tayar { 1053666db486STomer Tayar u32 resp = 0, param = 0; 1054666db486STomer Tayar int rc; 1055666db486STomer Tayar 1056666db486STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp, 1057666db486STomer Tayar ¶m); 1058666db486STomer Tayar if (rc) { 1059666db486STomer Tayar DP_NOTICE(p_hwfn, 1060666db486STomer Tayar "Failed to send a LOAD_DONE command, rc = %d\n", rc); 1061666db486STomer Tayar return rc; 1062666db486STomer Tayar } 1063666db486STomer Tayar 1064666db486STomer Tayar /* Check if there is a DID mismatch between nvm-cfg/efuse */ 1065666db486STomer Tayar if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR) 1066666db486STomer Tayar DP_NOTICE(p_hwfn, 1067666db486STomer Tayar "warning: device configuration is not supported on this board type. The device may not function as expected.\n"); 1068666db486STomer Tayar 1069666db486STomer Tayar return 0; 1070666db486STomer Tayar } 1071666db486STomer Tayar 10721226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10731226337aSTomer Tayar { 1074eaa50fc5STomer Tayar struct qed_mcp_mb_params mb_params; 1075eaa50fc5STomer Tayar u32 wol_param; 10761226337aSTomer Tayar 10771226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 10781226337aSTomer Tayar case QED_OV_WOL_DISABLED: 10791226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 10801226337aSTomer Tayar break; 10811226337aSTomer Tayar case QED_OV_WOL_ENABLED: 10821226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 10831226337aSTomer Tayar break; 10841226337aSTomer Tayar default: 10851226337aSTomer Tayar DP_NOTICE(p_hwfn, 10861226337aSTomer Tayar "Unknown WoL configuration %02x\n", 10871226337aSTomer Tayar p_hwfn->cdev->wol_config); 10881226337aSTomer Tayar /* Fallthrough */ 10891226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 10901226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 10911226337aSTomer Tayar } 10921226337aSTomer Tayar 1093eaa50fc5STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 1094eaa50fc5STomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ; 1095eaa50fc5STomer Tayar mb_params.param = wol_param; 1096b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 1097eaa50fc5STomer Tayar 1098eaa50fc5STomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 10991226337aSTomer Tayar } 11001226337aSTomer Tayar 11011226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11021226337aSTomer Tayar { 11031226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 11041226337aSTomer Tayar struct mcp_mac wol_mac; 11051226337aSTomer Tayar 11061226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 11071226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 11081226337aSTomer Tayar 11091226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 11101226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 11111226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 11121226337aSTomer Tayar 11131226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 11141226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 11151226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 11161226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 11171226337aSTomer Tayar 11181226337aSTomer Tayar DP_VERBOSE(p_hwfn, 11191226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 11201226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 11211226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 11221226337aSTomer Tayar 11231226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 11241226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 11251226337aSTomer Tayar } 11261226337aSTomer Tayar 11271226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11281226337aSTomer Tayar } 11291226337aSTomer Tayar 11300b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 11310b55e27dSYuval Mintz struct qed_ptt *p_ptt) 11320b55e27dSYuval Mintz { 11330b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11340b55e27dSYuval Mintz PUBLIC_PATH); 11350b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 11360b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 11370b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 11380b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 11390b55e27dSYuval Mintz int i; 11400b55e27dSYuval Mintz 11410b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 11420b55e27dSYuval Mintz QED_MSG_SP, 11430b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 11440b55e27dSYuval Mintz mfw_path_offsize, path_addr); 11450b55e27dSYuval Mintz 11460b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 11470b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 11480b55e27dSYuval Mintz path_addr + 11490b55e27dSYuval Mintz offsetof(struct public_path, 11500b55e27dSYuval Mintz mcp_vf_disabled) + 11510b55e27dSYuval Mintz sizeof(u32) * i); 11520b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11530b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 11540b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 11550b55e27dSYuval Mintz } 11560b55e27dSYuval Mintz 11570b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 11580b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 11590b55e27dSYuval Mintz } 11600b55e27dSYuval Mintz 11610b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 11620b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 11630b55e27dSYuval Mintz { 11640b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11650b55e27dSYuval Mintz PUBLIC_FUNC); 11660b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 11670b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 11680b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 11690b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 11700b55e27dSYuval Mintz int rc; 11710b55e27dSYuval Mintz int i; 11720b55e27dSYuval Mintz 11730b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11740b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11750b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 11760b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 11770b55e27dSYuval Mintz 11780b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 11790b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 11802f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 11812f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 11820b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11830b55e27dSYuval Mintz if (rc) { 11840b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 11850b55e27dSYuval Mintz return -EBUSY; 11860b55e27dSYuval Mintz } 11870b55e27dSYuval Mintz 11880b55e27dSYuval Mintz /* Clear the ACK bits */ 11890b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11900b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 11910b55e27dSYuval Mintz func_addr + 11920b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 11930b55e27dSYuval Mintz i * sizeof(u32), 0); 11940b55e27dSYuval Mintz 11950b55e27dSYuval Mintz return rc; 11960b55e27dSYuval Mintz } 11970b55e27dSYuval Mintz 1198334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1199334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 1200334c03b5SZvi Nachmani { 1201334c03b5SZvi Nachmani u32 transceiver_state; 1202334c03b5SZvi Nachmani 1203334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 1204334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 1205334c03b5SZvi Nachmani offsetof(struct public_port, 1206334c03b5SZvi Nachmani transceiver_data)); 1207334c03b5SZvi Nachmani 1208334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 1209334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 1210334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1211334c03b5SZvi Nachmani transceiver_state, 1212334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 12131a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 1214334c03b5SZvi Nachmani 1215334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 1216351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 1217334c03b5SZvi Nachmani 1218351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1219334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1220334c03b5SZvi Nachmani else 1221334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1222334c03b5SZvi Nachmani } 1223334c03b5SZvi Nachmani 1224645874e5SSudarsana Reddy Kalluru static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1225645874e5SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1226645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_state *p_link) 1227645874e5SSudarsana Reddy Kalluru { 1228645874e5SSudarsana Reddy Kalluru u32 eee_status, val; 1229645874e5SSudarsana Reddy Kalluru 1230645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps = 0; 1231645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps = 0; 1232645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, 1233645874e5SSudarsana Reddy Kalluru p_ptt, 1234645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 1235645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 1236645874e5SSudarsana Reddy Kalluru p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1237645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1238645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1239645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1240645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1241645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1242645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1243645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1244645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1245645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1246645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1247645874e5SSudarsana Reddy Kalluru } 1248645874e5SSudarsana Reddy Kalluru 1249e40a826aSSudarsana Reddy Kalluru static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 1250e40a826aSSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1251e40a826aSSudarsana Reddy Kalluru struct public_func *p_data, int pfid) 1252e40a826aSSudarsana Reddy Kalluru { 1253e40a826aSSudarsana Reddy Kalluru u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1254e40a826aSSudarsana Reddy Kalluru PUBLIC_FUNC); 1255e40a826aSSudarsana Reddy Kalluru u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1256e40a826aSSudarsana Reddy Kalluru u32 func_addr; 1257e40a826aSSudarsana Reddy Kalluru u32 i, size; 1258e40a826aSSudarsana Reddy Kalluru 1259e40a826aSSudarsana Reddy Kalluru func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 1260e40a826aSSudarsana Reddy Kalluru memset(p_data, 0, sizeof(*p_data)); 1261e40a826aSSudarsana Reddy Kalluru 1262e40a826aSSudarsana Reddy Kalluru size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 1263e40a826aSSudarsana Reddy Kalluru for (i = 0; i < size / sizeof(u32); i++) 1264e40a826aSSudarsana Reddy Kalluru ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 1265e40a826aSSudarsana Reddy Kalluru func_addr + (i << 2)); 1266e40a826aSSudarsana Reddy Kalluru return size; 1267e40a826aSSudarsana Reddy Kalluru } 1268e40a826aSSudarsana Reddy Kalluru 1269e40a826aSSudarsana Reddy Kalluru static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 1270e40a826aSSudarsana Reddy Kalluru struct public_func *p_shmem_info) 1271e40a826aSSudarsana Reddy Kalluru { 1272e40a826aSSudarsana Reddy Kalluru struct qed_mcp_function_info *p_info; 1273e40a826aSSudarsana Reddy Kalluru 1274e40a826aSSudarsana Reddy Kalluru p_info = &p_hwfn->mcp_info->func_info; 1275e40a826aSSudarsana Reddy Kalluru 1276e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = QED_MFW_GET_FIELD(p_shmem_info->config, 1277e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MIN_BW); 1278e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 1279e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1280e40a826aSSudarsana Reddy Kalluru "bandwidth minimum out of bounds [%02x]. Set to 1\n", 1281e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min); 1282e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = 1; 1283e40a826aSSudarsana Reddy Kalluru } 1284e40a826aSSudarsana Reddy Kalluru 1285e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = QED_MFW_GET_FIELD(p_shmem_info->config, 1286e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MAX_BW); 1287e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 1288e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1289e40a826aSSudarsana Reddy Kalluru "bandwidth maximum out of bounds [%02x]. Set to 100\n", 1290e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max); 1291e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = 100; 1292e40a826aSSudarsana Reddy Kalluru } 1293e40a826aSSudarsana Reddy Kalluru } 1294e40a826aSSudarsana Reddy Kalluru 1295cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 12961a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 1297cc875c2eSYuval Mintz { 1298cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 1299a64b02d5SManish Chopra u8 max_bw, min_bw; 1300cc875c2eSYuval Mintz u32 status = 0; 1301cc875c2eSYuval Mintz 130265ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 130365ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 130465ed2ffdSMintz, Yuval 1305cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 1306cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 1307cc875c2eSYuval Mintz if (!b_reset) { 1308cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 1309cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 1310cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 1311cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1312cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1313cc875c2eSYuval Mintz status, 1314cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 13151a635e48SYuval Mintz offsetof(struct public_port, link_status))); 1316cc875c2eSYuval Mintz } else { 1317cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1318cc875c2eSYuval Mintz "Resetting link indications\n"); 131965ed2ffdSMintz, Yuval goto out; 1320cc875c2eSYuval Mintz } 1321cc875c2eSYuval Mintz 1322e40a826aSSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) { 1323e40a826aSSudarsana Reddy Kalluru /* Link indication with modern MFW arrives as per-PF 1324e40a826aSSudarsana Reddy Kalluru * indication. 1325e40a826aSSudarsana Reddy Kalluru */ 1326e40a826aSSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & 1327e40a826aSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_VLINK) { 1328e40a826aSSudarsana Reddy Kalluru struct public_func shmem_info; 1329e40a826aSSudarsana Reddy Kalluru 1330e40a826aSSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 1331e40a826aSSudarsana Reddy Kalluru MCP_PF_ID(p_hwfn)); 1332e40a826aSSudarsana Reddy Kalluru p_link->link_up = !!(shmem_info.status & 1333e40a826aSSudarsana Reddy Kalluru FUNC_STATUS_VIRTUAL_LINK_UP); 1334e40a826aSSudarsana Reddy Kalluru qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1335e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1336e40a826aSSudarsana Reddy Kalluru "Virtual link_up = %d\n", p_link->link_up); 1337e40a826aSSudarsana Reddy Kalluru } else { 1338cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1339e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1340e40a826aSSudarsana Reddy Kalluru "Physical link_up = %d\n", p_link->link_up); 1341e40a826aSSudarsana Reddy Kalluru } 1342e40a826aSSudarsana Reddy Kalluru } else { 1343fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 1344e40a826aSSudarsana Reddy Kalluru } 1345cc875c2eSYuval Mintz 1346cc875c2eSYuval Mintz p_link->full_duplex = true; 1347cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1348cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1349cc875c2eSYuval Mintz p_link->speed = 100000; 1350cc875c2eSYuval Mintz break; 1351cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1352cc875c2eSYuval Mintz p_link->speed = 50000; 1353cc875c2eSYuval Mintz break; 1354cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1355cc875c2eSYuval Mintz p_link->speed = 40000; 1356cc875c2eSYuval Mintz break; 1357cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1358cc875c2eSYuval Mintz p_link->speed = 25000; 1359cc875c2eSYuval Mintz break; 1360cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1361cc875c2eSYuval Mintz p_link->speed = 20000; 1362cc875c2eSYuval Mintz break; 1363cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1364cc875c2eSYuval Mintz p_link->speed = 10000; 1365cc875c2eSYuval Mintz break; 1366cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1367cc875c2eSYuval Mintz p_link->full_duplex = false; 1368cc875c2eSYuval Mintz /* Fall-through */ 1369cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1370cc875c2eSYuval Mintz p_link->speed = 1000; 1371cc875c2eSYuval Mintz break; 1372cc875c2eSYuval Mintz default: 1373cc875c2eSYuval Mintz p_link->speed = 0; 137458874c7bSSudarsana Reddy Kalluru p_link->link_up = 0; 1375cc875c2eSYuval Mintz } 1376cc875c2eSYuval Mintz 13774b01e519SManish Chopra if (p_link->link_up && p_link->speed) 13784b01e519SManish Chopra p_link->line_speed = p_link->speed; 13794b01e519SManish Chopra else 13804b01e519SManish Chopra p_link->line_speed = 0; 13814b01e519SManish Chopra 13824b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1383a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 13844b01e519SManish Chopra 1385a64b02d5SManish Chopra /* Max bandwidth configuration */ 13864b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1387cc875c2eSYuval Mintz 1388a64b02d5SManish Chopra /* Min bandwidth configuration */ 1389a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 13906f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 13916f437d43SMintz, Yuval p_link->min_pf_rate); 1392a64b02d5SManish Chopra 1393cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1394cc875c2eSYuval Mintz p_link->an_complete = !!(status & 1395cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1396cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 1397cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 1398cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1399cc875c2eSYuval Mintz 1400cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1401cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1402cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 1403cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1404cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1405cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 1406cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1407cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1408cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 1409cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1410cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1411cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 1412cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1413054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1414054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 1415054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 1416cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1417cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 1418cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1419cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1420cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 1421cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1422cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1423cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 1424cc875c2eSYuval Mintz 1425cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 1426cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1427cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 1428cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1429cc875c2eSYuval Mintz 1430cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1431cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1432cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1433cc875c2eSYuval Mintz break; 1434cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1435cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1436cc875c2eSYuval Mintz break; 1437cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1438cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1439cc875c2eSYuval Mintz break; 1440cc875c2eSYuval Mintz default: 1441cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 1442cc875c2eSYuval Mintz } 1443cc875c2eSYuval Mintz 1444cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1445cc875c2eSYuval Mintz 1446645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1447645874e5SSudarsana Reddy Kalluru qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1448645874e5SSudarsana Reddy Kalluru 1449ae7e6937SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 1450ae7e6937SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) { 1451ae7e6937SAlexander Lobakin switch (status & LINK_STATUS_FEC_MODE_MASK) { 1452ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_NONE: 1453ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_NONE; 1454ae7e6937SAlexander Lobakin break; 1455ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_FIRECODE_CL74: 1456ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_FIRECODE; 1457ae7e6937SAlexander Lobakin break; 1458ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_RS_CL91: 1459ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_RS; 1460ae7e6937SAlexander Lobakin break; 1461ae7e6937SAlexander Lobakin default: 1462ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_AUTO; 1463ae7e6937SAlexander Lobakin } 1464ae7e6937SAlexander Lobakin } else { 1465ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_UNSUPPORTED; 1466ae7e6937SAlexander Lobakin } 1467ae7e6937SAlexander Lobakin 1468706d0891SRahul Verma qed_link_update(p_hwfn, p_ptt); 146965ed2ffdSMintz, Yuval out: 147065ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1471cc875c2eSYuval Mintz } 1472cc875c2eSYuval Mintz 1473351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1474cc875c2eSYuval Mintz { 1475cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 14765529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 14772f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 1478ae7e6937SAlexander Lobakin u32 cmd, fec_bit = 0; 1479cc875c2eSYuval Mintz int rc = 0; 1480cc875c2eSYuval Mintz 1481cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 14822f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 1483cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1484cc875c2eSYuval Mintz if (!params->speed.autoneg) 14852f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 14862f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 14872f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 14882f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 14892f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 14902f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 14914ad95a93SSudarsana Reddy Kalluru 14924ad95a93SSudarsana Reddy Kalluru /* There are MFWs that share this capability regardless of whether 14934ad95a93SSudarsana Reddy Kalluru * this is feasible or not. And given that at the very least adv_caps 14944ad95a93SSudarsana Reddy Kalluru * would be set internally by qed, we want to make sure LFA would 14954ad95a93SSudarsana Reddy Kalluru * still work. 14964ad95a93SSudarsana Reddy Kalluru */ 14974ad95a93SSudarsana Reddy Kalluru if ((p_hwfn->mcp_info->capabilities & 14984ad95a93SSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1499645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1500645874e5SSudarsana Reddy Kalluru if (params->eee.tx_lpi_enable) 1501645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1502645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_1G_ADV) 1503645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1504645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_10G_ADV) 1505645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1506645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1507645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_OFFSET) & 1508645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_MASK; 1509645874e5SSudarsana Reddy Kalluru } 1510cc875c2eSYuval Mintz 1511ae7e6937SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 1512ae7e6937SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) { 1513ae7e6937SAlexander Lobakin if (params->fec & QED_FEC_MODE_NONE) 1514ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_NONE; 1515ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_FIRECODE) 1516ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_FIRECODE; 1517ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_RS) 1518ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_RS; 1519ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_AUTO) 1520ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_AUTO; 1521ae7e6937SAlexander Lobakin 1522ae7e6937SAlexander Lobakin SET_MFW_FIELD(phy_cfg.fec_mode, FEC_FORCE_MODE, fec_bit); 1523ae7e6937SAlexander Lobakin } 1524ae7e6937SAlexander Lobakin 1525fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 1526fc916ff2SSudarsana Reddy Kalluru 1527cc875c2eSYuval Mintz if (b_up) { 1528cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1529ae7e6937SAlexander Lobakin "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, FEC 0x%08x\n", 1530ae7e6937SAlexander Lobakin phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed, 1531ae7e6937SAlexander Lobakin phy_cfg.loopback_mode, phy_cfg.fec_mode); 1532cc875c2eSYuval Mintz } else { 1533cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1534cc875c2eSYuval Mintz "Resetting link\n"); 1535cc875c2eSYuval Mintz } 1536cc875c2eSYuval Mintz 15375529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 15385529bad9STomer Tayar mb_params.cmd = cmd; 15392f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 15402f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 15415529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1542cc875c2eSYuval Mintz 1543cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 1544cc875c2eSYuval Mintz if (rc) { 1545cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1546cc875c2eSYuval Mintz return rc; 1547cc875c2eSYuval Mintz } 1548cc875c2eSYuval Mintz 154965ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 155065ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 155165ed2ffdSMintz, Yuval * an attention. 155265ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 155365ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 155465ed2ffdSMintz, Yuval */ 155565ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1556cc875c2eSYuval Mintz 1557cc875c2eSYuval Mintz return 0; 1558cc875c2eSYuval Mintz } 1559cc875c2eSYuval Mintz 156064515dc8STomer Tayar u32 qed_get_process_kill_counter(struct qed_hwfn *p_hwfn, 156164515dc8STomer Tayar struct qed_ptt *p_ptt) 156264515dc8STomer Tayar { 156364515dc8STomer Tayar u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt; 156464515dc8STomer Tayar 156564515dc8STomer Tayar if (IS_VF(p_hwfn->cdev)) 156664515dc8STomer Tayar return -EINVAL; 156764515dc8STomer Tayar 156864515dc8STomer Tayar path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 156964515dc8STomer Tayar PUBLIC_PATH); 157064515dc8STomer Tayar path_offsize = qed_rd(p_hwfn, p_ptt, path_offsize_addr); 157164515dc8STomer Tayar path_addr = SECTION_ADDR(path_offsize, QED_PATH_ID(p_hwfn)); 157264515dc8STomer Tayar 157364515dc8STomer Tayar proc_kill_cnt = qed_rd(p_hwfn, p_ptt, 157464515dc8STomer Tayar path_addr + 157564515dc8STomer Tayar offsetof(struct public_path, process_kill)) & 157664515dc8STomer Tayar PROCESS_KILL_COUNTER_MASK; 157764515dc8STomer Tayar 157864515dc8STomer Tayar return proc_kill_cnt; 157964515dc8STomer Tayar } 158064515dc8STomer Tayar 158164515dc8STomer Tayar static void qed_mcp_handle_process_kill(struct qed_hwfn *p_hwfn, 158264515dc8STomer Tayar struct qed_ptt *p_ptt) 158364515dc8STomer Tayar { 158464515dc8STomer Tayar struct qed_dev *cdev = p_hwfn->cdev; 158564515dc8STomer Tayar u32 proc_kill_cnt; 158664515dc8STomer Tayar 158764515dc8STomer Tayar /* Prevent possible attentions/interrupts during the recovery handling 158864515dc8STomer Tayar * and till its load phase, during which they will be re-enabled. 158964515dc8STomer Tayar */ 159064515dc8STomer Tayar qed_int_igu_disable_int(p_hwfn, p_ptt); 159164515dc8STomer Tayar 159264515dc8STomer Tayar DP_NOTICE(p_hwfn, "Received a process kill indication\n"); 159364515dc8STomer Tayar 159464515dc8STomer Tayar /* The following operations should be done once, and thus in CMT mode 159564515dc8STomer Tayar * are carried out by only the first HW function. 159664515dc8STomer Tayar */ 159764515dc8STomer Tayar if (p_hwfn != QED_LEADING_HWFN(cdev)) 159864515dc8STomer Tayar return; 159964515dc8STomer Tayar 160064515dc8STomer Tayar if (cdev->recov_in_prog) { 160164515dc8STomer Tayar DP_NOTICE(p_hwfn, 160264515dc8STomer Tayar "Ignoring the indication since a recovery process is already in progress\n"); 160364515dc8STomer Tayar return; 160464515dc8STomer Tayar } 160564515dc8STomer Tayar 160664515dc8STomer Tayar cdev->recov_in_prog = true; 160764515dc8STomer Tayar 160864515dc8STomer Tayar proc_kill_cnt = qed_get_process_kill_counter(p_hwfn, p_ptt); 160964515dc8STomer Tayar DP_NOTICE(p_hwfn, "Process kill counter: %d\n", proc_kill_cnt); 161064515dc8STomer Tayar 161164515dc8STomer Tayar qed_schedule_recovery_handler(p_hwfn); 161264515dc8STomer Tayar } 161364515dc8STomer Tayar 16146c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 16156c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 16166c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 16176c754246SSudarsana Reddy Kalluru { 16186c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 16196c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 16206c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 16216c754246SSudarsana Reddy Kalluru u32 hsi_param; 16226c754246SSudarsana Reddy Kalluru 16236c754246SSudarsana Reddy Kalluru switch (type) { 16246c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 16256c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 16266c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 16276c754246SSudarsana Reddy Kalluru break; 16286c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 16296c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 16306c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 16316c754246SSudarsana Reddy Kalluru break; 16326c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 16336c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 16346c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 16356c754246SSudarsana Reddy Kalluru break; 16366c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 16376c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 16386c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 16396c754246SSudarsana Reddy Kalluru break; 16406c754246SSudarsana Reddy Kalluru default: 16416c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 16426c754246SSudarsana Reddy Kalluru return; 16436c754246SSudarsana Reddy Kalluru } 16446c754246SSudarsana Reddy Kalluru 16456c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 16466c754246SSudarsana Reddy Kalluru 16476c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 16486c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 16496c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 16502f67af8cSTomer Tayar mb_params.p_data_src = &stats; 16512f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 16526c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 16536c754246SSudarsana Reddy Kalluru } 16546c754246SSudarsana Reddy Kalluru 16551a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 16564b01e519SManish Chopra { 16574b01e519SManish Chopra struct qed_mcp_function_info *p_info; 16584b01e519SManish Chopra struct public_func shmem_info; 16594b01e519SManish Chopra u32 resp = 0, param = 0; 16604b01e519SManish Chopra 16611a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 16624b01e519SManish Chopra 16634b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 16644b01e519SManish Chopra 16654b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 16664b01e519SManish Chopra 1667a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 16684b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 16694b01e519SManish Chopra 16704b01e519SManish Chopra /* Acknowledge the MFW */ 16714b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 16724b01e519SManish Chopra ¶m); 16734b01e519SManish Chopra } 16744b01e519SManish Chopra 16752a351fd9SMintz, Yuval static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 16762a351fd9SMintz, Yuval { 16772a351fd9SMintz, Yuval struct public_func shmem_info; 16782a351fd9SMintz, Yuval u32 resp = 0, param = 0; 16792a351fd9SMintz, Yuval 16802a351fd9SMintz, Yuval qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 16812a351fd9SMintz, Yuval 16822a351fd9SMintz, Yuval p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 16832a351fd9SMintz, Yuval FUNC_MF_CFG_OV_STAG_MASK; 16842a351fd9SMintz, Yuval p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 16857e3e375cSSudarsana Reddy Kalluru if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) { 16867e3e375cSSudarsana Reddy Kalluru if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) { 16877e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 16887e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 16897e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1); 16907e3e375cSSudarsana Reddy Kalluru 16917e3e375cSSudarsana Reddy Kalluru /* Configure DB to add external vlan to EDPM packets */ 16927e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1); 16937e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 16947e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 16957e3e375cSSudarsana Reddy Kalluru } else { 16967e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0); 16977e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0); 16987e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0); 16997e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0); 17007e3e375cSSudarsana Reddy Kalluru } 17017e3e375cSSudarsana Reddy Kalluru 17022a351fd9SMintz, Yuval qed_sp_pf_update_stag(p_hwfn); 17032a351fd9SMintz, Yuval } 17042a351fd9SMintz, Yuval 17057e3e375cSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan = %d hw_mode = 0x%x\n", 17067e3e375cSSudarsana Reddy Kalluru p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode); 17077e3e375cSSudarsana Reddy Kalluru 17082a351fd9SMintz, Yuval /* Acknowledge the MFW */ 17092a351fd9SMintz, Yuval qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 17102a351fd9SMintz, Yuval &resp, ¶m); 17112a351fd9SMintz, Yuval } 17122a351fd9SMintz, Yuval 17133e99c211SIgor Russkikh static void qed_mcp_handle_fan_failure(struct qed_hwfn *p_hwfn, 17143e99c211SIgor Russkikh struct qed_ptt *p_ptt) 17153e99c211SIgor Russkikh { 17163e99c211SIgor Russkikh /* A single notification should be sent to upper driver in CMT mode */ 17173e99c211SIgor Russkikh if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev)) 17183e99c211SIgor Russkikh return; 17193e99c211SIgor Russkikh 17203e99c211SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_FAN_FAIL, 17213e99c211SIgor Russkikh "Fan failure was detected on the network interface card and it's going to be shut down.\n"); 17223e99c211SIgor Russkikh } 17233e99c211SIgor Russkikh 1724ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params { 1725ebf64bf4SIgor Russkikh u32 cmd; 1726ebf64bf4SIgor Russkikh void *p_data_src; 1727ebf64bf4SIgor Russkikh u8 data_src_size; 1728ebf64bf4SIgor Russkikh void *p_data_dst; 1729ebf64bf4SIgor Russkikh u8 data_dst_size; 1730ebf64bf4SIgor Russkikh u32 mcp_resp; 1731ebf64bf4SIgor Russkikh }; 1732ebf64bf4SIgor Russkikh 1733ebf64bf4SIgor Russkikh static int 1734ebf64bf4SIgor Russkikh qed_mcp_mdump_cmd(struct qed_hwfn *p_hwfn, 1735ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt, 1736ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params *p_mdump_cmd_params) 1737ebf64bf4SIgor Russkikh { 1738ebf64bf4SIgor Russkikh struct qed_mcp_mb_params mb_params; 1739ebf64bf4SIgor Russkikh int rc; 1740ebf64bf4SIgor Russkikh 1741ebf64bf4SIgor Russkikh memset(&mb_params, 0, sizeof(mb_params)); 1742ebf64bf4SIgor Russkikh mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD; 1743ebf64bf4SIgor Russkikh mb_params.param = p_mdump_cmd_params->cmd; 1744ebf64bf4SIgor Russkikh mb_params.p_data_src = p_mdump_cmd_params->p_data_src; 1745ebf64bf4SIgor Russkikh mb_params.data_src_size = p_mdump_cmd_params->data_src_size; 1746ebf64bf4SIgor Russkikh mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst; 1747ebf64bf4SIgor Russkikh mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size; 1748ebf64bf4SIgor Russkikh rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1749ebf64bf4SIgor Russkikh if (rc) 1750ebf64bf4SIgor Russkikh return rc; 1751ebf64bf4SIgor Russkikh 1752ebf64bf4SIgor Russkikh p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp; 1753ebf64bf4SIgor Russkikh 1754ebf64bf4SIgor Russkikh if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) { 1755ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1756ebf64bf4SIgor Russkikh "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n", 1757ebf64bf4SIgor Russkikh p_mdump_cmd_params->cmd); 1758ebf64bf4SIgor Russkikh rc = -EOPNOTSUPP; 1759ebf64bf4SIgor Russkikh } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 1760ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1761ebf64bf4SIgor Russkikh "The mdump command is not supported by the MFW\n"); 1762ebf64bf4SIgor Russkikh rc = -EOPNOTSUPP; 1763ebf64bf4SIgor Russkikh } 1764ebf64bf4SIgor Russkikh 1765ebf64bf4SIgor Russkikh return rc; 1766ebf64bf4SIgor Russkikh } 1767ebf64bf4SIgor Russkikh 1768ebf64bf4SIgor Russkikh static int qed_mcp_mdump_ack(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1769ebf64bf4SIgor Russkikh { 1770ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params mdump_cmd_params; 1771ebf64bf4SIgor Russkikh 1772ebf64bf4SIgor Russkikh memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params)); 1773ebf64bf4SIgor Russkikh mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK; 1774ebf64bf4SIgor Russkikh 1775ebf64bf4SIgor Russkikh return qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params); 1776ebf64bf4SIgor Russkikh } 1777ebf64bf4SIgor Russkikh 1778ebf64bf4SIgor Russkikh int 1779ebf64bf4SIgor Russkikh qed_mcp_mdump_get_retain(struct qed_hwfn *p_hwfn, 1780ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt, 1781ebf64bf4SIgor Russkikh struct mdump_retain_data_stc *p_mdump_retain) 1782ebf64bf4SIgor Russkikh { 1783ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params mdump_cmd_params; 1784ebf64bf4SIgor Russkikh int rc; 1785ebf64bf4SIgor Russkikh 1786ebf64bf4SIgor Russkikh memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params)); 1787ebf64bf4SIgor Russkikh mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN; 1788ebf64bf4SIgor Russkikh mdump_cmd_params.p_data_dst = p_mdump_retain; 1789ebf64bf4SIgor Russkikh mdump_cmd_params.data_dst_size = sizeof(*p_mdump_retain); 1790ebf64bf4SIgor Russkikh 1791ebf64bf4SIgor Russkikh rc = qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params); 1792ebf64bf4SIgor Russkikh if (rc) 1793ebf64bf4SIgor Russkikh return rc; 1794ebf64bf4SIgor Russkikh 1795ebf64bf4SIgor Russkikh if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) { 1796ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1797ebf64bf4SIgor Russkikh "Failed to get the mdump retained data [mcp_resp 0x%x]\n", 1798ebf64bf4SIgor Russkikh mdump_cmd_params.mcp_resp); 1799ebf64bf4SIgor Russkikh return -EINVAL; 1800ebf64bf4SIgor Russkikh } 1801ebf64bf4SIgor Russkikh 1802ebf64bf4SIgor Russkikh return 0; 1803ebf64bf4SIgor Russkikh } 1804ebf64bf4SIgor Russkikh 1805ebf64bf4SIgor Russkikh static void qed_mcp_handle_critical_error(struct qed_hwfn *p_hwfn, 1806ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt) 1807ebf64bf4SIgor Russkikh { 1808ebf64bf4SIgor Russkikh struct mdump_retain_data_stc mdump_retain; 1809ebf64bf4SIgor Russkikh int rc; 1810ebf64bf4SIgor Russkikh 1811ebf64bf4SIgor Russkikh /* In CMT mode - no need for more than a single acknowledgment to the 1812ebf64bf4SIgor Russkikh * MFW, and no more than a single notification to the upper driver. 1813ebf64bf4SIgor Russkikh */ 1814ebf64bf4SIgor Russkikh if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev)) 1815ebf64bf4SIgor Russkikh return; 1816ebf64bf4SIgor Russkikh 1817ebf64bf4SIgor Russkikh rc = qed_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain); 1818ebf64bf4SIgor Russkikh if (rc == 0 && mdump_retain.valid) 1819ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1820ebf64bf4SIgor Russkikh "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n", 1821ebf64bf4SIgor Russkikh mdump_retain.epoch, 1822ebf64bf4SIgor Russkikh mdump_retain.pf, mdump_retain.status); 1823ebf64bf4SIgor Russkikh else 1824ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1825ebf64bf4SIgor Russkikh "The MFW notified that a critical error occurred in the device\n"); 1826ebf64bf4SIgor Russkikh 1827ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1828ebf64bf4SIgor Russkikh "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n"); 1829ebf64bf4SIgor Russkikh qed_mcp_mdump_ack(p_hwfn, p_ptt); 1830ebf64bf4SIgor Russkikh 1831ebf64bf4SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_HW_ATTN, NULL); 1832ebf64bf4SIgor Russkikh } 1833ebf64bf4SIgor Russkikh 1834cac6f691SSudarsana Reddy Kalluru void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1835cac6f691SSudarsana Reddy Kalluru { 1836cac6f691SSudarsana Reddy Kalluru struct public_func shmem_info; 1837cac6f691SSudarsana Reddy Kalluru u32 port_cfg, val; 1838cac6f691SSudarsana Reddy Kalluru 1839cac6f691SSudarsana Reddy Kalluru if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1840cac6f691SSudarsana Reddy Kalluru return; 1841cac6f691SSudarsana Reddy Kalluru 1842cac6f691SSudarsana Reddy Kalluru memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1843cac6f691SSudarsana Reddy Kalluru port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1844cac6f691SSudarsana Reddy Kalluru offsetof(struct public_port, oem_cfg_port)); 1845cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1846cac6f691SSudarsana Reddy Kalluru OEM_CFG_CHANNEL_TYPE_OFFSET; 1847cac6f691SSudarsana Reddy Kalluru if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1848ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1849ec036eb9SSudarsana Reddy Kalluru "Incorrect UFP Channel type %d port_id 0x%02x\n", 1850ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1851cac6f691SSudarsana Reddy Kalluru 1852cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1853cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_SCHED_TYPE_ETS) { 1854cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1855cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1856cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1857cac6f691SSudarsana Reddy Kalluru } else { 1858cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1859ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1860ec036eb9SSudarsana Reddy Kalluru "Unknown UFP scheduling mode %d port_id 0x%02x\n", 1861ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1862cac6f691SSudarsana Reddy Kalluru } 1863cac6f691SSudarsana Reddy Kalluru 1864cac6f691SSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1865b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1866b5fabb08SSudarsana Reddy Kalluru OEM_CFG_FUNC_TC_OFFSET; 1867cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.tc = (u8)val; 1868b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1869cac6f691SSudarsana Reddy Kalluru OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1870cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1871cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1872cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1873cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1874cac6f691SSudarsana Reddy Kalluru } else { 1875cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1876ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1877ec036eb9SSudarsana Reddy Kalluru "Unknown Host priority control %d port_id 0x%02x\n", 1878ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1879cac6f691SSudarsana Reddy Kalluru } 1880cac6f691SSudarsana Reddy Kalluru 1881cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1882ec036eb9SSudarsana Reddy Kalluru "UFP shmem config: mode = %d tc = %d pri_type = %d port_id 0x%02x\n", 1883ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc, 1884ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type, MFW_PORT(p_hwfn)); 1885cac6f691SSudarsana Reddy Kalluru } 1886cac6f691SSudarsana Reddy Kalluru 1887cac6f691SSudarsana Reddy Kalluru static int 1888cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1889cac6f691SSudarsana Reddy Kalluru { 1890cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1891cac6f691SSudarsana Reddy Kalluru 1892cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1893cac6f691SSudarsana Reddy Kalluru p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1894c4259ddaSDenis Bolotin qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1895c4259ddaSDenis Bolotin p_hwfn->ufp_info.tc); 1896cac6f691SSudarsana Reddy Kalluru 1897cac6f691SSudarsana Reddy Kalluru qed_qm_reconf(p_hwfn, p_ptt); 1898cac6f691SSudarsana Reddy Kalluru } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1899cac6f691SSudarsana Reddy Kalluru /* Merge UFP TC with the dcbx TC data */ 1900cac6f691SSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1901cac6f691SSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 1902cac6f691SSudarsana Reddy Kalluru } else { 1903cac6f691SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1904cac6f691SSudarsana Reddy Kalluru return -EINVAL; 1905cac6f691SSudarsana Reddy Kalluru } 1906cac6f691SSudarsana Reddy Kalluru 1907cac6f691SSudarsana Reddy Kalluru /* update storm FW with negotiation results */ 1908cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_ufp(p_hwfn); 1909cac6f691SSudarsana Reddy Kalluru 1910cac6f691SSudarsana Reddy Kalluru /* update stag pcp value */ 1911cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_stag(p_hwfn); 1912cac6f691SSudarsana Reddy Kalluru 1913cac6f691SSudarsana Reddy Kalluru return 0; 1914cac6f691SSudarsana Reddy Kalluru } 1915cac6f691SSudarsana Reddy Kalluru 1916cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1917cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1918cc875c2eSYuval Mintz { 1919cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 1920cc875c2eSYuval Mintz int rc = 0; 1921cc875c2eSYuval Mintz bool found = false; 1922cc875c2eSYuval Mintz u16 i; 1923cc875c2eSYuval Mintz 1924cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1925cc875c2eSYuval Mintz 1926cc875c2eSYuval Mintz /* Read Messages from MFW */ 1927cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 1928cc875c2eSYuval Mintz 1929cc875c2eSYuval Mintz /* Compare current messages to old ones */ 1930cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 1931cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1932cc875c2eSYuval Mintz continue; 1933cc875c2eSYuval Mintz 1934cc875c2eSYuval Mintz found = true; 1935cc875c2eSYuval Mintz 1936cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1937cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1938cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1939cc875c2eSYuval Mintz 1940cc875c2eSYuval Mintz switch (i) { 1941cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 1942cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1943cc875c2eSYuval Mintz break; 19440b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 19450b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 19460b55e27dSYuval Mintz break; 194739651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 194839651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 194939651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 195039651abdSSudarsana Reddy Kalluru break; 195139651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 195239651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 195339651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 195439651abdSSudarsana Reddy Kalluru break; 195539651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 195639651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 195739651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 195839651abdSSudarsana Reddy Kalluru break; 1959cac6f691SSudarsana Reddy Kalluru case MFW_DRV_MSG_OEM_CFG_UPDATE: 1960cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 1961cac6f691SSudarsana Reddy Kalluru break; 1962334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1963334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1964334c03b5SZvi Nachmani break; 196564515dc8STomer Tayar case MFW_DRV_MSG_ERROR_RECOVERY: 196664515dc8STomer Tayar qed_mcp_handle_process_kill(p_hwfn, p_ptt); 196764515dc8STomer Tayar break; 19686c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 19696c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 19706c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 19716c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 19726c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 19736c754246SSudarsana Reddy Kalluru break; 19744b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 19754b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 19764b01e519SManish Chopra break; 19772a351fd9SMintz, Yuval case MFW_DRV_MSG_S_TAG_UPDATE: 19782a351fd9SMintz, Yuval qed_mcp_update_stag(p_hwfn, p_ptt); 19792a351fd9SMintz, Yuval break; 19803e99c211SIgor Russkikh case MFW_DRV_MSG_FAILURE_DETECTED: 19813e99c211SIgor Russkikh qed_mcp_handle_fan_failure(p_hwfn, p_ptt); 19823e99c211SIgor Russkikh break; 1983ebf64bf4SIgor Russkikh case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED: 1984ebf64bf4SIgor Russkikh qed_mcp_handle_critical_error(p_hwfn, p_ptt); 1985ebf64bf4SIgor Russkikh break; 198659ccf86fSSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_TLV_REQ: 198759ccf86fSSudarsana Reddy Kalluru qed_mfw_tlv_req(p_hwfn); 19882a351fd9SMintz, Yuval break; 1989cc875c2eSYuval Mintz default: 199039815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1991cc875c2eSYuval Mintz rc = -EINVAL; 1992cc875c2eSYuval Mintz } 1993cc875c2eSYuval Mintz } 1994cc875c2eSYuval Mintz 1995cc875c2eSYuval Mintz /* ACK everything */ 1996cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1997cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1998cc875c2eSYuval Mintz 1999cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 2000cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 2001cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 2002cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 2003cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 2004cc875c2eSYuval Mintz (__force u32)val); 2005cc875c2eSYuval Mintz } 2006cc875c2eSYuval Mintz 2007cc875c2eSYuval Mintz if (!found) { 2008cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 2009cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 2010cc875c2eSYuval Mintz rc = -EINVAL; 2011cc875c2eSYuval Mintz } 2012cc875c2eSYuval Mintz 2013cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 2014cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 2015cc875c2eSYuval Mintz 2016cc875c2eSYuval Mintz return rc; 2017cc875c2eSYuval Mintz } 2018cc875c2eSYuval Mintz 20191408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 20201408cc1fSYuval Mintz struct qed_ptt *p_ptt, 20211408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 2022fe56b9e6SYuval Mintz { 2023fe56b9e6SYuval Mintz u32 global_offsize; 2024fe56b9e6SYuval Mintz 20251408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 20261408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 20271408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 20281408cc1fSYuval Mintz 20291408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 20301408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 20311408cc1fSYuval Mintz return 0; 20321408cc1fSYuval Mintz } else { 20331408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 20341408cc1fSYuval Mintz QED_MSG_IOV, 20351408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 20361408cc1fSYuval Mintz return -EINVAL; 20371408cc1fSYuval Mintz } 20381408cc1fSYuval Mintz } 2039fe56b9e6SYuval Mintz 2040fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 20411408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 20421408cc1fSYuval Mintz mcp_info->public_base, 2043fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 20441408cc1fSYuval Mintz *p_mfw_ver = 20451408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 20461408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 20471408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 2048fe56b9e6SYuval Mintz 20491408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 20501408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 20511408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 20521408cc1fSYuval Mintz offsetof(struct public_global, 20531408cc1fSYuval Mintz running_bundle_id)); 20541408cc1fSYuval Mintz } 2055fe56b9e6SYuval Mintz 2056fe56b9e6SYuval Mintz return 0; 2057fe56b9e6SYuval Mintz } 2058fe56b9e6SYuval Mintz 2059ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 2060ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver) 2061ae33666aSTomer Tayar { 2062ae33666aSTomer Tayar u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 2063ae33666aSTomer Tayar 2064ae33666aSTomer Tayar if (IS_VF(p_hwfn->cdev)) 2065ae33666aSTomer Tayar return -EINVAL; 2066ae33666aSTomer Tayar 2067ae33666aSTomer Tayar /* Read the address of the nvm_cfg */ 2068ae33666aSTomer Tayar nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2069ae33666aSTomer Tayar if (!nvm_cfg_addr) { 2070ae33666aSTomer Tayar DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 2071ae33666aSTomer Tayar return -EINVAL; 2072ae33666aSTomer Tayar } 2073ae33666aSTomer Tayar 2074ae33666aSTomer Tayar /* Read the offset of nvm_cfg1 */ 2075ae33666aSTomer Tayar nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2076ae33666aSTomer Tayar 2077ae33666aSTomer Tayar mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2078ae33666aSTomer Tayar offsetof(struct nvm_cfg1, glob) + 2079ae33666aSTomer Tayar offsetof(struct nvm_cfg1_glob, mbi_version); 2080ae33666aSTomer Tayar *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 2081ae33666aSTomer Tayar mbi_ver_addr) & 2082ae33666aSTomer Tayar (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 2083ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 2084ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 2085ae33666aSTomer Tayar 2086ae33666aSTomer Tayar return 0; 2087ae33666aSTomer Tayar } 2088ae33666aSTomer Tayar 2089706d0891SRahul Verma int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, 2090706d0891SRahul Verma struct qed_ptt *p_ptt, u32 *p_media_type) 2091cc875c2eSYuval Mintz { 2092c56a8be7SRahul Verma *p_media_type = MEDIA_UNSPECIFIED; 2093c56a8be7SRahul Verma 2094706d0891SRahul Verma if (IS_VF(p_hwfn->cdev)) 20951408cc1fSYuval Mintz return -EINVAL; 20961408cc1fSYuval Mintz 2097cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 2098cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2099cc875c2eSYuval Mintz return -EBUSY; 2100cc875c2eSYuval Mintz } 2101cc875c2eSYuval Mintz 2102706d0891SRahul Verma if (!p_ptt) { 2103cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 2104706d0891SRahul Verma return -EINVAL; 2105706d0891SRahul Verma } 2106cc875c2eSYuval Mintz 2107706d0891SRahul Verma *p_media_type = qed_rd(p_hwfn, p_ptt, 2108706d0891SRahul Verma p_hwfn->mcp_info->port_addr + 2109706d0891SRahul Verma offsetof(struct public_port, 2110706d0891SRahul Verma media_type)); 2111cc875c2eSYuval Mintz 2112cc875c2eSYuval Mintz return 0; 2113cc875c2eSYuval Mintz } 2114cc875c2eSYuval Mintz 2115c56a8be7SRahul Verma int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, 2116c56a8be7SRahul Verma struct qed_ptt *p_ptt, 2117c56a8be7SRahul Verma u32 *p_transceiver_state, 2118c56a8be7SRahul Verma u32 *p_transceiver_type) 2119c56a8be7SRahul Verma { 2120c56a8be7SRahul Verma u32 transceiver_info; 2121c56a8be7SRahul Verma 212268203a67SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_NONE; 212368203a67SRahul Verma *p_transceiver_state = ETH_TRANSCEIVER_STATE_UPDATING; 212468203a67SRahul Verma 2125c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 2126c56a8be7SRahul Verma return -EINVAL; 2127c56a8be7SRahul Verma 2128c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 2129c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2130c56a8be7SRahul Verma return -EBUSY; 2131c56a8be7SRahul Verma } 2132c56a8be7SRahul Verma 2133c56a8be7SRahul Verma transceiver_info = qed_rd(p_hwfn, p_ptt, 2134c56a8be7SRahul Verma p_hwfn->mcp_info->port_addr + 2135c56a8be7SRahul Verma offsetof(struct public_port, 2136c56a8be7SRahul Verma transceiver_data)); 2137c56a8be7SRahul Verma 2138c56a8be7SRahul Verma *p_transceiver_state = (transceiver_info & 2139c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_MASK) >> 2140c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_OFFSET; 2141c56a8be7SRahul Verma 2142c56a8be7SRahul Verma if (*p_transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 2143c56a8be7SRahul Verma *p_transceiver_type = (transceiver_info & 2144c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_MASK) >> 2145c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_OFFSET; 2146c56a8be7SRahul Verma else 2147c56a8be7SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_UNKNOWN; 2148c56a8be7SRahul Verma 2149c56a8be7SRahul Verma return 0; 2150c56a8be7SRahul Verma } 2151c56a8be7SRahul Verma static bool qed_is_transceiver_ready(u32 transceiver_state, 2152c56a8be7SRahul Verma u32 transceiver_type) 2153c56a8be7SRahul Verma { 2154c56a8be7SRahul Verma if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) && 2155c56a8be7SRahul Verma ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) && 2156c56a8be7SRahul Verma (transceiver_type != ETH_TRANSCEIVER_TYPE_NONE)) 2157c56a8be7SRahul Verma return true; 2158c56a8be7SRahul Verma 2159c56a8be7SRahul Verma return false; 2160c56a8be7SRahul Verma } 2161c56a8be7SRahul Verma 2162c56a8be7SRahul Verma int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, 2163c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_speed_mask) 2164c56a8be7SRahul Verma { 2165c56a8be7SRahul Verma u32 transceiver_type, transceiver_state; 216692619210SArnd Bergmann int ret; 2167c56a8be7SRahul Verma 216892619210SArnd Bergmann ret = qed_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state, 2169c56a8be7SRahul Verma &transceiver_type); 217092619210SArnd Bergmann if (ret) 217192619210SArnd Bergmann return ret; 2172c56a8be7SRahul Verma 2173c56a8be7SRahul Verma if (qed_is_transceiver_ready(transceiver_state, transceiver_type) == 2174c56a8be7SRahul Verma false) 2175c56a8be7SRahul Verma return -EINVAL; 2176c56a8be7SRahul Verma 2177c56a8be7SRahul Verma switch (transceiver_type) { 2178c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_LX: 2179c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_SX: 2180c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_PCC: 2181c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_ACC: 2182c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1000BASET: 2183c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2184c56a8be7SRahul Verma break; 2185c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_SR: 2186c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LR: 2187c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LRM: 2188c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ER: 2189c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_PCC: 2190c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ACC: 2191c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x10G: 2192c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2193c56a8be7SRahul Verma break; 2194c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_LR4: 2195c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_SR4: 2196c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR: 2197c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR: 2198c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2199c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2200c56a8be7SRahul Verma break; 2201c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_AOC: 2202c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_SR4: 2203c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_LR4: 2204c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ER4: 2205c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ACC: 2206c56a8be7SRahul Verma *p_speed_mask = 2207c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2208c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2209c56a8be7SRahul Verma break; 2210c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_SR: 2211c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_LR: 2212c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_AOC: 2213c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_S: 2214c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_M: 2215c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_L: 2216c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2217c56a8be7SRahul Verma break; 2218c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_N: 2219c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_S: 2220c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_L: 2221c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x25G_CR: 2222c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2223c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2224c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2225c56a8be7SRahul Verma break; 22269228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR: 22279228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR: 22289228b7c1SAlexander Lobakin *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 22299228b7c1SAlexander Lobakin NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 22309228b7c1SAlexander Lobakin break; 2231c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_CR4: 2232c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR: 2233c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2234c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2235c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2236c56a8be7SRahul Verma break; 2237c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_CR4: 2238c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR: 2239c56a8be7SRahul Verma *p_speed_mask = 2240c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2241c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G | 2242c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2243c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2244c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G | 2245c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2246c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2247c56a8be7SRahul Verma break; 2248c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR: 2249c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR: 2250c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC: 2251c56a8be7SRahul Verma *p_speed_mask = 2252c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2253c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2254c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2255c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2256c56a8be7SRahul Verma break; 2257c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_XLPPI: 2258c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 2259c56a8be7SRahul Verma break; 2260c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_BASET: 22619228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR: 22629228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR: 2263c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2264c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2265c56a8be7SRahul Verma break; 2266c56a8be7SRahul Verma default: 22671107a674SColin Ian King DP_INFO(p_hwfn, "Unknown transceiver type 0x%x\n", 2268c56a8be7SRahul Verma transceiver_type); 2269c56a8be7SRahul Verma *p_speed_mask = 0xff; 2270c56a8be7SRahul Verma break; 2271c56a8be7SRahul Verma } 2272c56a8be7SRahul Verma 2273c56a8be7SRahul Verma return 0; 2274c56a8be7SRahul Verma } 2275c56a8be7SRahul Verma 2276c56a8be7SRahul Verma int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, 2277c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_board_config) 2278c56a8be7SRahul Verma { 2279c56a8be7SRahul Verma u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr; 2280c56a8be7SRahul Verma 2281c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 2282c56a8be7SRahul Verma return -EINVAL; 2283c56a8be7SRahul Verma 2284c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 2285c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2286c56a8be7SRahul Verma return -EBUSY; 2287c56a8be7SRahul Verma } 2288c56a8be7SRahul Verma if (!p_ptt) { 2289c56a8be7SRahul Verma *p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED; 2290c56a8be7SRahul Verma return -EINVAL; 2291c56a8be7SRahul Verma } 2292c56a8be7SRahul Verma 2293c56a8be7SRahul Verma nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2294c56a8be7SRahul Verma nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2295c56a8be7SRahul Verma port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2296c56a8be7SRahul Verma offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2297c56a8be7SRahul Verma *p_board_config = qed_rd(p_hwfn, p_ptt, 2298c56a8be7SRahul Verma port_cfg_addr + 2299c56a8be7SRahul Verma offsetof(struct nvm_cfg1_port, 2300c56a8be7SRahul Verma board_cfg)); 2301c56a8be7SRahul Verma 2302c56a8be7SRahul Verma return 0; 2303c56a8be7SRahul Verma } 2304c56a8be7SRahul Verma 23056927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 23066927e826SMintz, Yuval static void 23076927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 23086927e826SMintz, Yuval enum qed_pci_personality *p_proto) 23096927e826SMintz, Yuval { 23106927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 23116927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 23126927e826SMintz, Yuval */ 23136927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 23146927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 23156927e826SMintz, Yuval else 23166927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 23176927e826SMintz, Yuval 23186927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 23196927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 23206927e826SMintz, Yuval (u32) *p_proto); 23216927e826SMintz, Yuval } 23226927e826SMintz, Yuval 23236927e826SMintz, Yuval static int 23246927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 23256927e826SMintz, Yuval struct qed_ptt *p_ptt, 23266927e826SMintz, Yuval enum qed_pci_personality *p_proto) 23276927e826SMintz, Yuval { 23286927e826SMintz, Yuval u32 resp = 0, param = 0; 23296927e826SMintz, Yuval int rc; 23306927e826SMintz, Yuval 23316927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 23326927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 23336927e826SMintz, Yuval if (rc) 23346927e826SMintz, Yuval return rc; 23356927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 23366927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 23376927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 23386927e826SMintz, Yuval resp); 23396927e826SMintz, Yuval return -EINVAL; 23406927e826SMintz, Yuval } 23416927e826SMintz, Yuval 23426927e826SMintz, Yuval switch (param) { 23436927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 23446927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 23456927e826SMintz, Yuval break; 23466927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 23476927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 23486927e826SMintz, Yuval break; 23496927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 2350e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_IWARP; 2351e0a8f9deSMichal Kalderon break; 2352e0a8f9deSMichal Kalderon case FW_MB_PARAM_GET_PF_RDMA_BOTH: 2353e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_RDMA; 2354e0a8f9deSMichal Kalderon break; 23556927e826SMintz, Yuval default: 23566927e826SMintz, Yuval DP_NOTICE(p_hwfn, 23576927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 23586927e826SMintz, Yuval param); 23596927e826SMintz, Yuval return -EINVAL; 23606927e826SMintz, Yuval } 23616927e826SMintz, Yuval 23626927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 23636927e826SMintz, Yuval NETIF_MSG_IFUP, 23646927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 23656927e826SMintz, Yuval (u32) *p_proto, resp, param); 23666927e826SMintz, Yuval return 0; 23676927e826SMintz, Yuval } 23686927e826SMintz, Yuval 2369fe56b9e6SYuval Mintz static int 2370fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 2371fe56b9e6SYuval Mintz struct public_func *p_info, 23726927e826SMintz, Yuval struct qed_ptt *p_ptt, 2373fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 2374fe56b9e6SYuval Mintz { 2375fe56b9e6SYuval Mintz int rc = 0; 2376fe56b9e6SYuval Mintz 2377fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 2378fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 23791fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 23801fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 23811fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 23826927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 2383fe56b9e6SYuval Mintz break; 2384c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 2385c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 2386c5ac9319SYuval Mintz break; 23871e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 23881e128c81SArun Easi *p_proto = QED_PCI_FCOE; 23891e128c81SArun Easi break; 2390c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 2391c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 23926927e826SMintz, Yuval /* Fallthrough */ 2393fe56b9e6SYuval Mintz default: 2394fe56b9e6SYuval Mintz rc = -EINVAL; 2395fe56b9e6SYuval Mintz } 2396fe56b9e6SYuval Mintz 2397fe56b9e6SYuval Mintz return rc; 2398fe56b9e6SYuval Mintz } 2399fe56b9e6SYuval Mintz 2400fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 2401fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 2402fe56b9e6SYuval Mintz { 2403fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 2404fe56b9e6SYuval Mintz struct public_func shmem_info; 2405fe56b9e6SYuval Mintz 24061a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 2407fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 2408fe56b9e6SYuval Mintz 2409fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 2410fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 2411fe56b9e6SYuval Mintz 24126927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 24136927e826SMintz, Yuval &info->protocol)) { 2414fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 2415fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 2416fe56b9e6SYuval Mintz return -EINVAL; 2417fe56b9e6SYuval Mintz } 2418fe56b9e6SYuval Mintz 24194b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 2420fe56b9e6SYuval Mintz 2421fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 2422fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 2423fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 2424fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 2425fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 2426fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 2427fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 242814d39648SMintz, Yuval 242914d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 243014d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 2431fe56b9e6SYuval Mintz } else { 2432fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 2433fe56b9e6SYuval Mintz } 2434fe56b9e6SYuval Mintz 243557796759SMintz, Yuval info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 243657796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 243757796759SMintz, Yuval info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 243857796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 2439fe56b9e6SYuval Mintz 2440fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 2441fe56b9e6SYuval Mintz 24420fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 24430fefbfbaSSudarsana Kalluru 244414d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 244514d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 244614d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 244714d39648SMintz, Yuval u32 resp = 0, param = 0; 244814d39648SMintz, Yuval int rc; 244914d39648SMintz, Yuval 245014d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 245114d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 245214d39648SMintz, Yuval if (rc) 245314d39648SMintz, Yuval return rc; 245414d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 245514d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 245614d39648SMintz, Yuval } 245714d39648SMintz, Yuval 2458fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 245914d39648SMintz, Yuval "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 2460fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 2461fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 2462fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 2463fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 246414d39648SMintz, Yuval info->wwn_port, info->wwn_node, 246514d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 2466fe56b9e6SYuval Mintz 2467fe56b9e6SYuval Mintz return 0; 2468fe56b9e6SYuval Mintz } 2469fe56b9e6SYuval Mintz 2470cc875c2eSYuval Mintz struct qed_mcp_link_params 2471cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 2472cc875c2eSYuval Mintz { 2473cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2474cc875c2eSYuval Mintz return NULL; 2475cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 2476cc875c2eSYuval Mintz } 2477cc875c2eSYuval Mintz 2478cc875c2eSYuval Mintz struct qed_mcp_link_state 2479cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 2480cc875c2eSYuval Mintz { 2481cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2482cc875c2eSYuval Mintz return NULL; 2483cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 2484cc875c2eSYuval Mintz } 2485cc875c2eSYuval Mintz 2486cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 2487cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 2488cc875c2eSYuval Mintz { 2489cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2490cc875c2eSYuval Mintz return NULL; 2491cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 2492cc875c2eSYuval Mintz } 2493cc875c2eSYuval Mintz 24941a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2495fe56b9e6SYuval Mintz { 2496fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 2497fe56b9e6SYuval Mintz int rc; 2498fe56b9e6SYuval Mintz 2499fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 25001a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 2501fe56b9e6SYuval Mintz 2502fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 25038f60bafeSYuval Mintz msleep(1020); 2504fe56b9e6SYuval Mintz 2505fe56b9e6SYuval Mintz return rc; 2506fe56b9e6SYuval Mintz } 2507fe56b9e6SYuval Mintz 2508cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 25091a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 2510cee4d264SManish Chopra { 2511cee4d264SManish Chopra u32 flash_size; 2512cee4d264SManish Chopra 25131408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 25141408cc1fSYuval Mintz return -EINVAL; 25151408cc1fSYuval Mintz 2516cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 2517cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 2518cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 2519cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 2520cee4d264SManish Chopra 2521cee4d264SManish Chopra *p_flash_size = flash_size; 2522cee4d264SManish Chopra 2523cee4d264SManish Chopra return 0; 2524cee4d264SManish Chopra } 2525cee4d264SManish Chopra 252664515dc8STomer Tayar int qed_start_recovery_process(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 252764515dc8STomer Tayar { 252864515dc8STomer Tayar struct qed_dev *cdev = p_hwfn->cdev; 252964515dc8STomer Tayar 253064515dc8STomer Tayar if (cdev->recov_in_prog) { 253164515dc8STomer Tayar DP_NOTICE(p_hwfn, 253264515dc8STomer Tayar "Avoid triggering a recovery since such a process is already in progress\n"); 253364515dc8STomer Tayar return -EAGAIN; 253464515dc8STomer Tayar } 253564515dc8STomer Tayar 253664515dc8STomer Tayar DP_NOTICE(p_hwfn, "Triggering a recovery process\n"); 253764515dc8STomer Tayar qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1); 253864515dc8STomer Tayar 253964515dc8STomer Tayar return 0; 254064515dc8STomer Tayar } 254164515dc8STomer Tayar 254264515dc8STomer Tayar #define QED_RECOVERY_PROLOG_SLEEP_MS 100 254364515dc8STomer Tayar 254464515dc8STomer Tayar int qed_recovery_prolog(struct qed_dev *cdev) 254564515dc8STomer Tayar { 254664515dc8STomer Tayar struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 254764515dc8STomer Tayar struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 254864515dc8STomer Tayar int rc; 254964515dc8STomer Tayar 255064515dc8STomer Tayar /* Allow ongoing PCIe transactions to complete */ 255164515dc8STomer Tayar msleep(QED_RECOVERY_PROLOG_SLEEP_MS); 255264515dc8STomer Tayar 255364515dc8STomer Tayar /* Clear the PF's internal FID_enable in the PXP */ 255464515dc8STomer Tayar rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false); 255564515dc8STomer Tayar if (rc) 255664515dc8STomer Tayar DP_NOTICE(p_hwfn, 255764515dc8STomer Tayar "qed_pglueb_set_pfid_enable() failed. rc = %d.\n", 255864515dc8STomer Tayar rc); 255964515dc8STomer Tayar 256064515dc8STomer Tayar return rc; 256164515dc8STomer Tayar } 256264515dc8STomer Tayar 256388072fd4SMintz, Yuval static int 256488072fd4SMintz, Yuval qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 25651408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 25661408cc1fSYuval Mintz { 25671408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 25681408cc1fSYuval Mintz int rc; 25691408cc1fSYuval Mintz 25701408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 25711408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 25721408cc1fSYuval Mintz return 0; 25731408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 25741408cc1fSYuval Mintz 25751408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 25761408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 25771408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 25781408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 25791408cc1fSYuval Mintz 25801408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 25811408cc1fSYuval Mintz &resp, &rc_param); 25821408cc1fSYuval Mintz 25831408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 25841408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 25851408cc1fSYuval Mintz rc = -EINVAL; 25861408cc1fSYuval Mintz } else { 25871408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 25881408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 25891408cc1fSYuval Mintz num, vf_id); 25901408cc1fSYuval Mintz } 25911408cc1fSYuval Mintz 25921408cc1fSYuval Mintz return rc; 25931408cc1fSYuval Mintz } 25941408cc1fSYuval Mintz 259588072fd4SMintz, Yuval static int 259688072fd4SMintz, Yuval qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 259788072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 num) 259888072fd4SMintz, Yuval { 259988072fd4SMintz, Yuval u32 resp = 0, param = num, rc_param = 0; 260088072fd4SMintz, Yuval int rc; 260188072fd4SMintz, Yuval 260288072fd4SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 260388072fd4SMintz, Yuval param, &resp, &rc_param); 260488072fd4SMintz, Yuval 260588072fd4SMintz, Yuval if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 260688072fd4SMintz, Yuval DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 260788072fd4SMintz, Yuval rc = -EINVAL; 260888072fd4SMintz, Yuval } else { 260988072fd4SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_IOV, 261088072fd4SMintz, Yuval "Requested 0x%02x MSI-x interrupts for VFs\n", num); 261188072fd4SMintz, Yuval } 261288072fd4SMintz, Yuval 261388072fd4SMintz, Yuval return rc; 261488072fd4SMintz, Yuval } 261588072fd4SMintz, Yuval 261688072fd4SMintz, Yuval int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 261788072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 vf_id, u8 num) 261888072fd4SMintz, Yuval { 261988072fd4SMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 262088072fd4SMintz, Yuval return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 262188072fd4SMintz, Yuval else 262288072fd4SMintz, Yuval return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 262388072fd4SMintz, Yuval } 262488072fd4SMintz, Yuval 2625fe56b9e6SYuval Mintz int 2626fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2627fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2628fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 2629fe56b9e6SYuval Mintz { 26305529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 26312f67af8cSTomer Tayar struct drv_version_stc drv_version; 26325529bad9STomer Tayar __be32 val; 26335529bad9STomer Tayar u32 i; 26345529bad9STomer Tayar int rc; 2635fe56b9e6SYuval Mintz 26362f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 26372f67af8cSTomer Tayar drv_version.version = p_ver->version; 263867a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 263967a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 26402f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2641fe56b9e6SYuval Mintz } 2642fe56b9e6SYuval Mintz 26435529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 26445529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 26452f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 26462f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 26475529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 26485529bad9STomer Tayar if (rc) 2649fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2650fe56b9e6SYuval Mintz 26515529bad9STomer Tayar return rc; 2652fe56b9e6SYuval Mintz } 265391420b83SSudarsana Kalluru 265476271809STomer Tayar /* A maximal 100 msec waiting time for the MCP to halt */ 265576271809STomer Tayar #define QED_MCP_HALT_SLEEP_MS 10 265676271809STomer Tayar #define QED_MCP_HALT_MAX_RETRIES 10 265776271809STomer Tayar 26584102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 26594102426fSTomer Tayar { 266076271809STomer Tayar u32 resp = 0, param = 0, cpu_state, cnt = 0; 26614102426fSTomer Tayar int rc; 26624102426fSTomer Tayar 26634102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 26644102426fSTomer Tayar ¶m); 266576271809STomer Tayar if (rc) { 26664102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 26674102426fSTomer Tayar return rc; 26684102426fSTomer Tayar } 26694102426fSTomer Tayar 267076271809STomer Tayar do { 267176271809STomer Tayar msleep(QED_MCP_HALT_SLEEP_MS); 267276271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 267376271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) 267476271809STomer Tayar break; 267576271809STomer Tayar } while (++cnt < QED_MCP_HALT_MAX_RETRIES); 267676271809STomer Tayar 267776271809STomer Tayar if (cnt == QED_MCP_HALT_MAX_RETRIES) { 267876271809STomer Tayar DP_NOTICE(p_hwfn, 267976271809STomer Tayar "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 268076271809STomer Tayar qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state); 268176271809STomer Tayar return -EBUSY; 268276271809STomer Tayar } 268376271809STomer Tayar 2684b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 2685b310974eSTomer Tayar 268676271809STomer Tayar return 0; 268776271809STomer Tayar } 268876271809STomer Tayar 268976271809STomer Tayar #define QED_MCP_RESUME_SLEEP_MS 10 269076271809STomer Tayar 26914102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 26924102426fSTomer Tayar { 269376271809STomer Tayar u32 cpu_mode, cpu_state; 26944102426fSTomer Tayar 26954102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 26964102426fSTomer Tayar 26974102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 269876271809STomer Tayar cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT; 269976271809STomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode); 270076271809STomer Tayar msleep(QED_MCP_RESUME_SLEEP_MS); 270176271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 27024102426fSTomer Tayar 270376271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) { 270476271809STomer Tayar DP_NOTICE(p_hwfn, 270576271809STomer Tayar "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 270676271809STomer Tayar cpu_mode, cpu_state); 270776271809STomer Tayar return -EBUSY; 270876271809STomer Tayar } 270976271809STomer Tayar 2710b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, false); 2711b310974eSTomer Tayar 271276271809STomer Tayar return 0; 27134102426fSTomer Tayar } 27144102426fSTomer Tayar 27150fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 27160fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 27170fefbfbaSSudarsana Kalluru enum qed_ov_client client) 27180fefbfbaSSudarsana Kalluru { 27190fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 27200fefbfbaSSudarsana Kalluru u32 drv_mb_param; 27210fefbfbaSSudarsana Kalluru int rc; 27220fefbfbaSSudarsana Kalluru 27230fefbfbaSSudarsana Kalluru switch (client) { 27240fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 27250fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 27260fefbfbaSSudarsana Kalluru break; 27270fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 27280fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 27290fefbfbaSSudarsana Kalluru break; 27300fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 27310fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 27320fefbfbaSSudarsana Kalluru break; 27330fefbfbaSSudarsana Kalluru default: 27340fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 27350fefbfbaSSudarsana Kalluru return -EINVAL; 27360fefbfbaSSudarsana Kalluru } 27370fefbfbaSSudarsana Kalluru 27380fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 27390fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 27400fefbfbaSSudarsana Kalluru if (rc) 27410fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 27420fefbfbaSSudarsana Kalluru 27430fefbfbaSSudarsana Kalluru return rc; 27440fefbfbaSSudarsana Kalluru } 27450fefbfbaSSudarsana Kalluru 27460fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 27470fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 27480fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 27490fefbfbaSSudarsana Kalluru { 27500fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 27510fefbfbaSSudarsana Kalluru u32 drv_mb_param; 27520fefbfbaSSudarsana Kalluru int rc; 27530fefbfbaSSudarsana Kalluru 27540fefbfbaSSudarsana Kalluru switch (drv_state) { 27550fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 27560fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 27570fefbfbaSSudarsana Kalluru break; 27580fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 27590fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 27600fefbfbaSSudarsana Kalluru break; 27610fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 27620fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 27630fefbfbaSSudarsana Kalluru break; 27640fefbfbaSSudarsana Kalluru default: 27650fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 27660fefbfbaSSudarsana Kalluru return -EINVAL; 27670fefbfbaSSudarsana Kalluru } 27680fefbfbaSSudarsana Kalluru 27690fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 27700fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 27710fefbfbaSSudarsana Kalluru if (rc) 27720fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 27730fefbfbaSSudarsana Kalluru 27740fefbfbaSSudarsana Kalluru return rc; 27750fefbfbaSSudarsana Kalluru } 27760fefbfbaSSudarsana Kalluru 27770fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 27780fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 27790fefbfbaSSudarsana Kalluru { 27800fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 27810fefbfbaSSudarsana Kalluru u32 drv_mb_param; 27820fefbfbaSSudarsana Kalluru int rc; 27830fefbfbaSSudarsana Kalluru 27840fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 27850fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 27860fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 27870fefbfbaSSudarsana Kalluru if (rc) 27880fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 27890fefbfbaSSudarsana Kalluru 27900fefbfbaSSudarsana Kalluru return rc; 27910fefbfbaSSudarsana Kalluru } 27920fefbfbaSSudarsana Kalluru 27930fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 27940fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 27950fefbfbaSSudarsana Kalluru { 27960fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 279717991002SMintz, Yuval u32 mfw_mac[2]; 27980fefbfbaSSudarsana Kalluru int rc; 27990fefbfbaSSudarsana Kalluru 28000fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 28010fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 28020fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 28030fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 28040fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 28052f67af8cSTomer Tayar 280617991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 280717991002SMintz, Yuval * in 32-bit granularity. 280817991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 280917991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 281017991002SMintz, Yuval */ 281117991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 281217991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 281317991002SMintz, Yuval 281417991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 281517991002SMintz, Yuval mb_params.data_src_size = 8; 28160fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 28170fefbfbaSSudarsana Kalluru if (rc) 28180fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 28190fefbfbaSSudarsana Kalluru 282014d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 282114d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 282214d39648SMintz, Yuval 28230fefbfbaSSudarsana Kalluru return rc; 28240fefbfbaSSudarsana Kalluru } 28250fefbfbaSSudarsana Kalluru 28260fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 28270fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 28280fefbfbaSSudarsana Kalluru { 28290fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 28300fefbfbaSSudarsana Kalluru u32 drv_mb_param; 28310fefbfbaSSudarsana Kalluru int rc; 28320fefbfbaSSudarsana Kalluru 283314d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 283414d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 283514d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 283614d39648SMintz, Yuval return -EINVAL; 283714d39648SMintz, Yuval } 283814d39648SMintz, Yuval 28390fefbfbaSSudarsana Kalluru switch (wol) { 28400fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 28410fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 28420fefbfbaSSudarsana Kalluru break; 28430fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 28440fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 28450fefbfbaSSudarsana Kalluru break; 28460fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 28470fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 28480fefbfbaSSudarsana Kalluru break; 28490fefbfbaSSudarsana Kalluru default: 28500fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 28510fefbfbaSSudarsana Kalluru return -EINVAL; 28520fefbfbaSSudarsana Kalluru } 28530fefbfbaSSudarsana Kalluru 28540fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 28550fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 28560fefbfbaSSudarsana Kalluru if (rc) 28570fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 28580fefbfbaSSudarsana Kalluru 285914d39648SMintz, Yuval /* Store the WoL update for a future unload */ 286014d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 286114d39648SMintz, Yuval 28620fefbfbaSSudarsana Kalluru return rc; 28630fefbfbaSSudarsana Kalluru } 28640fefbfbaSSudarsana Kalluru 28650fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 28660fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 28670fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 28680fefbfbaSSudarsana Kalluru { 28690fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 28700fefbfbaSSudarsana Kalluru u32 drv_mb_param; 28710fefbfbaSSudarsana Kalluru int rc; 28720fefbfbaSSudarsana Kalluru 28730fefbfbaSSudarsana Kalluru switch (eswitch) { 28740fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 28750fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 28760fefbfbaSSudarsana Kalluru break; 28770fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 28780fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 28790fefbfbaSSudarsana Kalluru break; 28800fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 28810fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 28820fefbfbaSSudarsana Kalluru break; 28830fefbfbaSSudarsana Kalluru default: 28840fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 28850fefbfbaSSudarsana Kalluru return -EINVAL; 28860fefbfbaSSudarsana Kalluru } 28870fefbfbaSSudarsana Kalluru 28880fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 28890fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 28900fefbfbaSSudarsana Kalluru if (rc) 28910fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 28920fefbfbaSSudarsana Kalluru 28930fefbfbaSSudarsana Kalluru return rc; 28940fefbfbaSSudarsana Kalluru } 28950fefbfbaSSudarsana Kalluru 28961a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 28971a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 289891420b83SSudarsana Kalluru { 289991420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 290091420b83SSudarsana Kalluru int rc; 290191420b83SSudarsana Kalluru 290291420b83SSudarsana Kalluru switch (mode) { 290391420b83SSudarsana Kalluru case QED_LED_MODE_ON: 290491420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 290591420b83SSudarsana Kalluru break; 290691420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 290791420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 290891420b83SSudarsana Kalluru break; 290991420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 291091420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 291191420b83SSudarsana Kalluru break; 291291420b83SSudarsana Kalluru default: 291391420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 291491420b83SSudarsana Kalluru return -EINVAL; 291591420b83SSudarsana Kalluru } 291691420b83SSudarsana Kalluru 291791420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 291891420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 291991420b83SSudarsana Kalluru 292091420b83SSudarsana Kalluru return rc; 292191420b83SSudarsana Kalluru } 292203dc76caSSudarsana Reddy Kalluru 29234102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 29244102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 29254102426fSTomer Tayar { 29264102426fSTomer Tayar u32 resp = 0, param = 0; 29274102426fSTomer Tayar int rc; 29284102426fSTomer Tayar 29294102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 29304102426fSTomer Tayar mask_parities, &resp, ¶m); 29314102426fSTomer Tayar 29324102426fSTomer Tayar if (rc) { 29334102426fSTomer Tayar DP_ERR(p_hwfn, 29344102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 29354102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 29364102426fSTomer Tayar DP_ERR(p_hwfn, 29374102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 29384102426fSTomer Tayar rc = -EINVAL; 29394102426fSTomer Tayar } 29404102426fSTomer Tayar 29414102426fSTomer Tayar return rc; 29424102426fSTomer Tayar } 29434102426fSTomer Tayar 29447a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 29457a4b21b7SMintz, Yuval { 29467a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 29477a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 29487a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 29497a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 29507a4b21b7SMintz, Yuval int rc = 0; 29517a4b21b7SMintz, Yuval 29527a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 29537a4b21b7SMintz, Yuval if (!p_ptt) 29547a4b21b7SMintz, Yuval return -EBUSY; 29557a4b21b7SMintz, Yuval 29567a4b21b7SMintz, Yuval while (bytes_left > 0) { 29577a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 29587a4b21b7SMintz, Yuval 29597a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 29607a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 29617a4b21b7SMintz, Yuval addr + offset + 29627a4b21b7SMintz, Yuval (bytes_to_copy << 2963da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 29647a4b21b7SMintz, Yuval &resp, &resp_param, 29657a4b21b7SMintz, Yuval &read_len, 29667a4b21b7SMintz, Yuval (u32 *)(p_buf + offset)); 29677a4b21b7SMintz, Yuval 29687a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 29697a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 29707a4b21b7SMintz, Yuval break; 29717a4b21b7SMintz, Yuval } 29727a4b21b7SMintz, Yuval 29737a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 29747a4b21b7SMintz, Yuval * isn't preemptable. Sleep a bit to prevent CPU hogging. 29757a4b21b7SMintz, Yuval */ 29767a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 29777a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 29787a4b21b7SMintz, Yuval usleep_range(1000, 2000); 29797a4b21b7SMintz, Yuval 29807a4b21b7SMintz, Yuval offset += read_len; 29817a4b21b7SMintz, Yuval bytes_left -= read_len; 29827a4b21b7SMintz, Yuval } 29837a4b21b7SMintz, Yuval 29847a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 29857a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 29867a4b21b7SMintz, Yuval 29877a4b21b7SMintz, Yuval return rc; 29887a4b21b7SMintz, Yuval } 29897a4b21b7SMintz, Yuval 299062e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 299162e4d438SSudarsana Reddy Kalluru { 299262e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 299362e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 299462e4d438SSudarsana Reddy Kalluru 299562e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 299662e4d438SSudarsana Reddy Kalluru if (!p_ptt) 299762e4d438SSudarsana Reddy Kalluru return -EBUSY; 299862e4d438SSudarsana Reddy Kalluru 299962e4d438SSudarsana Reddy Kalluru memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 300062e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 300162e4d438SSudarsana Reddy Kalluru 300262e4d438SSudarsana Reddy Kalluru return 0; 300362e4d438SSudarsana Reddy Kalluru } 300462e4d438SSudarsana Reddy Kalluru 300562e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 300662e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len) 300762e4d438SSudarsana Reddy Kalluru { 300862e4d438SSudarsana Reddy Kalluru u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 300962e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 301062e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 301162e4d438SSudarsana Reddy Kalluru int rc = -EINVAL; 301262e4d438SSudarsana Reddy Kalluru 301362e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 301462e4d438SSudarsana Reddy Kalluru if (!p_ptt) 301562e4d438SSudarsana Reddy Kalluru return -EBUSY; 301662e4d438SSudarsana Reddy Kalluru 301762e4d438SSudarsana Reddy Kalluru switch (cmd) { 3018057d2b19SSudarsana Reddy Kalluru case QED_PUT_FILE_BEGIN: 3019057d2b19SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN; 3020057d2b19SSudarsana Reddy Kalluru break; 302162e4d438SSudarsana Reddy Kalluru case QED_PUT_FILE_DATA: 302262e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 302362e4d438SSudarsana Reddy Kalluru break; 302462e4d438SSudarsana Reddy Kalluru case QED_NVM_WRITE_NVRAM: 302562e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 302662e4d438SSudarsana Reddy Kalluru break; 302762e4d438SSudarsana Reddy Kalluru default: 302862e4d438SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 302962e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 303062e4d438SSudarsana Reddy Kalluru goto out; 303162e4d438SSudarsana Reddy Kalluru } 303262e4d438SSudarsana Reddy Kalluru 303362e4d438SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 3034057d2b19SSudarsana Reddy Kalluru while (buf_idx < len) { 3035057d2b19SSudarsana Reddy Kalluru if (cmd == QED_PUT_FILE_BEGIN) 3036057d2b19SSudarsana Reddy Kalluru nvm_offset = addr; 3037057d2b19SSudarsana Reddy Kalluru else 3038057d2b19SSudarsana Reddy Kalluru nvm_offset = ((buf_size << 3039057d2b19SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_LEN_OFFSET) | addr) + 3040057d2b19SSudarsana Reddy Kalluru buf_idx; 304162e4d438SSudarsana Reddy Kalluru rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 304262e4d438SSudarsana Reddy Kalluru &resp, ¶m, buf_size, 304362e4d438SSudarsana Reddy Kalluru (u32 *)&p_buf[buf_idx]); 304462e4d438SSudarsana Reddy Kalluru if (rc) { 304562e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 304662e4d438SSudarsana Reddy Kalluru resp = FW_MSG_CODE_ERROR; 304762e4d438SSudarsana Reddy Kalluru break; 304862e4d438SSudarsana Reddy Kalluru } 304962e4d438SSudarsana Reddy Kalluru 305062e4d438SSudarsana Reddy Kalluru if (resp != FW_MSG_CODE_OK && 305162e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_OK && 305262e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 305362e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, 305462e4d438SSudarsana Reddy Kalluru "nvm write failed, resp = 0x%08x\n", resp); 305562e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 305662e4d438SSudarsana Reddy Kalluru break; 305762e4d438SSudarsana Reddy Kalluru } 305862e4d438SSudarsana Reddy Kalluru 305962e4d438SSudarsana Reddy Kalluru /* This can be a lengthy process, and it's possible scheduler 306062e4d438SSudarsana Reddy Kalluru * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 306162e4d438SSudarsana Reddy Kalluru */ 306262e4d438SSudarsana Reddy Kalluru if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 306362e4d438SSudarsana Reddy Kalluru usleep_range(1000, 2000); 306462e4d438SSudarsana Reddy Kalluru 3065057d2b19SSudarsana Reddy Kalluru /* For MBI upgrade, MFW response includes the next buffer offset 3066057d2b19SSudarsana Reddy Kalluru * to be delivered to MFW. 3067057d2b19SSudarsana Reddy Kalluru */ 3068057d2b19SSudarsana Reddy Kalluru if (param && cmd == QED_PUT_FILE_DATA) { 3069057d2b19SSudarsana Reddy Kalluru buf_idx = QED_MFW_GET_FIELD(param, 3070057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET); 3071057d2b19SSudarsana Reddy Kalluru buf_size = QED_MFW_GET_FIELD(param, 3072057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE); 3073057d2b19SSudarsana Reddy Kalluru } else { 307462e4d438SSudarsana Reddy Kalluru buf_idx += buf_size; 3075057d2b19SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), 3076057d2b19SSudarsana Reddy Kalluru MCP_DRV_NVM_BUF_LEN); 3077057d2b19SSudarsana Reddy Kalluru } 307862e4d438SSudarsana Reddy Kalluru } 307962e4d438SSudarsana Reddy Kalluru 308062e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 308162e4d438SSudarsana Reddy Kalluru out: 308262e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 308362e4d438SSudarsana Reddy Kalluru 308462e4d438SSudarsana Reddy Kalluru return rc; 308562e4d438SSudarsana Reddy Kalluru } 308662e4d438SSudarsana Reddy Kalluru 3087b51dab46SSudarsana Reddy Kalluru int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3088b51dab46SSudarsana Reddy Kalluru u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 3089b51dab46SSudarsana Reddy Kalluru { 3090b51dab46SSudarsana Reddy Kalluru u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 3091b51dab46SSudarsana Reddy Kalluru u32 resp, param; 3092b51dab46SSudarsana Reddy Kalluru int rc; 3093b51dab46SSudarsana Reddy Kalluru 3094b51dab46SSudarsana Reddy Kalluru nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 3095b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 3096b51dab46SSudarsana Reddy Kalluru nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 3097b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 3098b51dab46SSudarsana Reddy Kalluru 3099b51dab46SSudarsana Reddy Kalluru addr = offset; 3100b51dab46SSudarsana Reddy Kalluru offset = 0; 3101b51dab46SSudarsana Reddy Kalluru bytes_left = len; 3102b51dab46SSudarsana Reddy Kalluru while (bytes_left > 0) { 3103b51dab46SSudarsana Reddy Kalluru bytes_to_copy = min_t(u32, bytes_left, 3104b51dab46SSudarsana Reddy Kalluru MAX_I2C_TRANSACTION_SIZE); 3105b51dab46SSudarsana Reddy Kalluru nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 3106b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 3107b51dab46SSudarsana Reddy Kalluru nvm_offset |= ((addr + offset) << 3108b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 3109b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 3110b51dab46SSudarsana Reddy Kalluru nvm_offset |= (bytes_to_copy << 3111b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 3112b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 3113b51dab46SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 3114b51dab46SSudarsana Reddy Kalluru DRV_MSG_CODE_TRANSCEIVER_READ, 3115b51dab46SSudarsana Reddy Kalluru nvm_offset, &resp, ¶m, &buf_size, 3116b51dab46SSudarsana Reddy Kalluru (u32 *)(p_buf + offset)); 3117b51dab46SSudarsana Reddy Kalluru if (rc) { 3118b51dab46SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 3119b51dab46SSudarsana Reddy Kalluru "Failed to send a transceiver read command to the MFW. rc = %d.\n", 3120b51dab46SSudarsana Reddy Kalluru rc); 3121b51dab46SSudarsana Reddy Kalluru return rc; 3122b51dab46SSudarsana Reddy Kalluru } 3123b51dab46SSudarsana Reddy Kalluru 3124b51dab46SSudarsana Reddy Kalluru if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 3125b51dab46SSudarsana Reddy Kalluru return -ENODEV; 3126b51dab46SSudarsana Reddy Kalluru else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 3127b51dab46SSudarsana Reddy Kalluru return -EINVAL; 3128b51dab46SSudarsana Reddy Kalluru 3129b51dab46SSudarsana Reddy Kalluru offset += buf_size; 3130b51dab46SSudarsana Reddy Kalluru bytes_left -= buf_size; 3131b51dab46SSudarsana Reddy Kalluru } 3132b51dab46SSudarsana Reddy Kalluru 3133b51dab46SSudarsana Reddy Kalluru return 0; 3134b51dab46SSudarsana Reddy Kalluru } 3135b51dab46SSudarsana Reddy Kalluru 313603dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 313703dc76caSSudarsana Reddy Kalluru { 313803dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 313903dc76caSSudarsana Reddy Kalluru int rc = 0; 314003dc76caSSudarsana Reddy Kalluru 314103dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 314203dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 314303dc76caSSudarsana Reddy Kalluru 314403dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 314503dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 314603dc76caSSudarsana Reddy Kalluru 314703dc76caSSudarsana Reddy Kalluru if (rc) 314803dc76caSSudarsana Reddy Kalluru return rc; 314903dc76caSSudarsana Reddy Kalluru 315003dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 315103dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 315203dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 315303dc76caSSudarsana Reddy Kalluru 315403dc76caSSudarsana Reddy Kalluru return rc; 315503dc76caSSudarsana Reddy Kalluru } 315603dc76caSSudarsana Reddy Kalluru 315703dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 315803dc76caSSudarsana Reddy Kalluru { 315903dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 316003dc76caSSudarsana Reddy Kalluru int rc = 0; 316103dc76caSSudarsana Reddy Kalluru 316203dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 316303dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 316403dc76caSSudarsana Reddy Kalluru 316503dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 316603dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 316703dc76caSSudarsana Reddy Kalluru 316803dc76caSSudarsana Reddy Kalluru if (rc) 316903dc76caSSudarsana Reddy Kalluru return rc; 317003dc76caSSudarsana Reddy Kalluru 317103dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 317203dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 317303dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 317403dc76caSSudarsana Reddy Kalluru 317503dc76caSSudarsana Reddy Kalluru return rc; 317603dc76caSSudarsana Reddy Kalluru } 31777a4b21b7SMintz, Yuval 317843645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 31797a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 31807a4b21b7SMintz, Yuval u32 *num_images) 31817a4b21b7SMintz, Yuval { 31827a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 31837a4b21b7SMintz, Yuval int rc = 0; 31847a4b21b7SMintz, Yuval 31857a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 31867a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 31877a4b21b7SMintz, Yuval 31887a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 31897a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 31907a4b21b7SMintz, Yuval if (rc) 31917a4b21b7SMintz, Yuval return rc; 31927a4b21b7SMintz, Yuval 31937a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 31947a4b21b7SMintz, Yuval rc = -EINVAL; 31957a4b21b7SMintz, Yuval 31967a4b21b7SMintz, Yuval return rc; 31977a4b21b7SMintz, Yuval } 31987a4b21b7SMintz, Yuval 319943645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 32007a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 32017a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 32027a4b21b7SMintz, Yuval u32 image_index) 32037a4b21b7SMintz, Yuval { 32047a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 32057a4b21b7SMintz, Yuval int rc; 32067a4b21b7SMintz, Yuval 32077a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 32087a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 32097a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 32107a4b21b7SMintz, Yuval 32117a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 32127a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 32137a4b21b7SMintz, Yuval &resp, &resp_param, 32147a4b21b7SMintz, Yuval &buf_size, 32157a4b21b7SMintz, Yuval (u32 *)p_image_att); 32167a4b21b7SMintz, Yuval if (rc) 32177a4b21b7SMintz, Yuval return rc; 32187a4b21b7SMintz, Yuval 32197a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 32207a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 32217a4b21b7SMintz, Yuval rc = -EINVAL; 32227a4b21b7SMintz, Yuval 32237a4b21b7SMintz, Yuval return rc; 32247a4b21b7SMintz, Yuval } 32252edbff8dSTomer Tayar 322643645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 322743645ce0SSudarsana Reddy Kalluru { 32285e7ba042SDenis Bolotin struct qed_nvm_image_info nvm_info; 322943645ce0SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 323043645ce0SSudarsana Reddy Kalluru int rc; 323143645ce0SSudarsana Reddy Kalluru u32 i; 323243645ce0SSudarsana Reddy Kalluru 32335e7ba042SDenis Bolotin if (p_hwfn->nvm_info.valid) 32345e7ba042SDenis Bolotin return 0; 32355e7ba042SDenis Bolotin 323643645ce0SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 323743645ce0SSudarsana Reddy Kalluru if (!p_ptt) { 323843645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "failed to acquire ptt\n"); 323943645ce0SSudarsana Reddy Kalluru return -EBUSY; 324043645ce0SSudarsana Reddy Kalluru } 324143645ce0SSudarsana Reddy Kalluru 324243645ce0SSudarsana Reddy Kalluru /* Acquire from MFW the amount of available images */ 32435e7ba042SDenis Bolotin nvm_info.num_images = 0; 324443645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 32455e7ba042SDenis Bolotin p_ptt, &nvm_info.num_images); 324643645ce0SSudarsana Reddy Kalluru if (rc == -EOPNOTSUPP) { 324743645ce0SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 324843645ce0SSudarsana Reddy Kalluru goto out; 32495e7ba042SDenis Bolotin } else if (rc || !nvm_info.num_images) { 325043645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Failed getting number of images\n"); 325143645ce0SSudarsana Reddy Kalluru goto err0; 325243645ce0SSudarsana Reddy Kalluru } 325343645ce0SSudarsana Reddy Kalluru 32545e7ba042SDenis Bolotin nvm_info.image_att = kmalloc_array(nvm_info.num_images, 325543645ce0SSudarsana Reddy Kalluru sizeof(struct bist_nvm_image_att), 325643645ce0SSudarsana Reddy Kalluru GFP_KERNEL); 32575e7ba042SDenis Bolotin if (!nvm_info.image_att) { 325843645ce0SSudarsana Reddy Kalluru rc = -ENOMEM; 325943645ce0SSudarsana Reddy Kalluru goto err0; 326043645ce0SSudarsana Reddy Kalluru } 326143645ce0SSudarsana Reddy Kalluru 326243645ce0SSudarsana Reddy Kalluru /* Iterate over images and get their attributes */ 32635e7ba042SDenis Bolotin for (i = 0; i < nvm_info.num_images; i++) { 326443645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 32655e7ba042SDenis Bolotin &nvm_info.image_att[i], i); 326643645ce0SSudarsana Reddy Kalluru if (rc) { 326743645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, 326843645ce0SSudarsana Reddy Kalluru "Failed getting image index %d attributes\n", i); 326943645ce0SSudarsana Reddy Kalluru goto err1; 327043645ce0SSudarsana Reddy Kalluru } 327143645ce0SSudarsana Reddy Kalluru 327243645ce0SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 32735e7ba042SDenis Bolotin nvm_info.image_att[i].len); 327443645ce0SSudarsana Reddy Kalluru } 327543645ce0SSudarsana Reddy Kalluru out: 32765e7ba042SDenis Bolotin /* Update hwfn's nvm_info */ 32775e7ba042SDenis Bolotin if (nvm_info.num_images) { 32785e7ba042SDenis Bolotin p_hwfn->nvm_info.num_images = nvm_info.num_images; 32795e7ba042SDenis Bolotin kfree(p_hwfn->nvm_info.image_att); 32805e7ba042SDenis Bolotin p_hwfn->nvm_info.image_att = nvm_info.image_att; 32815e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = true; 32825e7ba042SDenis Bolotin } 32835e7ba042SDenis Bolotin 328443645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 328543645ce0SSudarsana Reddy Kalluru return 0; 328643645ce0SSudarsana Reddy Kalluru 328743645ce0SSudarsana Reddy Kalluru err1: 32885e7ba042SDenis Bolotin kfree(nvm_info.image_att); 328943645ce0SSudarsana Reddy Kalluru err0: 329043645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 329143645ce0SSudarsana Reddy Kalluru return rc; 329243645ce0SSudarsana Reddy Kalluru } 329343645ce0SSudarsana Reddy Kalluru 329413cf8aabSSudarsana Reddy Kalluru void qed_mcp_nvm_info_free(struct qed_hwfn *p_hwfn) 329513cf8aabSSudarsana Reddy Kalluru { 329613cf8aabSSudarsana Reddy Kalluru kfree(p_hwfn->nvm_info.image_att); 329713cf8aabSSudarsana Reddy Kalluru p_hwfn->nvm_info.image_att = NULL; 329813cf8aabSSudarsana Reddy Kalluru p_hwfn->nvm_info.valid = false; 329913cf8aabSSudarsana Reddy Kalluru } 330013cf8aabSSudarsana Reddy Kalluru 33011ac4329aSDenis Bolotin int 330220675b37SMintz, Yuval qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 330320675b37SMintz, Yuval enum qed_nvm_images image_id, 330420675b37SMintz, Yuval struct qed_nvm_image_att *p_image_att) 330520675b37SMintz, Yuval { 330620675b37SMintz, Yuval enum nvm_image_type type; 330743645ce0SSudarsana Reddy Kalluru u32 i; 330820675b37SMintz, Yuval 330920675b37SMintz, Yuval /* Translate image_id into MFW definitions */ 331020675b37SMintz, Yuval switch (image_id) { 331120675b37SMintz, Yuval case QED_NVM_IMAGE_ISCSI_CFG: 331220675b37SMintz, Yuval type = NVM_TYPE_ISCSI_CFG; 331320675b37SMintz, Yuval break; 331420675b37SMintz, Yuval case QED_NVM_IMAGE_FCOE_CFG: 331520675b37SMintz, Yuval type = NVM_TYPE_FCOE_CFG; 331620675b37SMintz, Yuval break; 33178a52bbabSMichal Kalderon case QED_NVM_IMAGE_MDUMP: 33188a52bbabSMichal Kalderon type = NVM_TYPE_MDUMP; 33198a52bbabSMichal Kalderon break; 33201ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_CFG1: 33211ac4329aSDenis Bolotin type = NVM_TYPE_NVM_CFG1; 33221ac4329aSDenis Bolotin break; 33231ac4329aSDenis Bolotin case QED_NVM_IMAGE_DEFAULT_CFG: 33241ac4329aSDenis Bolotin type = NVM_TYPE_DEFAULT_CFG; 33251ac4329aSDenis Bolotin break; 33261ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_META: 33271ac4329aSDenis Bolotin type = NVM_TYPE_META; 33281ac4329aSDenis Bolotin break; 332920675b37SMintz, Yuval default: 333020675b37SMintz, Yuval DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 333120675b37SMintz, Yuval image_id); 333220675b37SMintz, Yuval return -EINVAL; 333320675b37SMintz, Yuval } 333420675b37SMintz, Yuval 33355e7ba042SDenis Bolotin qed_mcp_nvm_info_populate(p_hwfn); 333643645ce0SSudarsana Reddy Kalluru for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 333743645ce0SSudarsana Reddy Kalluru if (type == p_hwfn->nvm_info.image_att[i].image_type) 333820675b37SMintz, Yuval break; 333943645ce0SSudarsana Reddy Kalluru if (i == p_hwfn->nvm_info.num_images) { 334020675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 334120675b37SMintz, Yuval "Failed to find nvram image of type %08x\n", 334220675b37SMintz, Yuval image_id); 334343645ce0SSudarsana Reddy Kalluru return -ENOENT; 334420675b37SMintz, Yuval } 334520675b37SMintz, Yuval 334643645ce0SSudarsana Reddy Kalluru p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 334743645ce0SSudarsana Reddy Kalluru p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 334820675b37SMintz, Yuval 334920675b37SMintz, Yuval return 0; 335020675b37SMintz, Yuval } 335120675b37SMintz, Yuval 335220675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 335320675b37SMintz, Yuval enum qed_nvm_images image_id, 335420675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len) 335520675b37SMintz, Yuval { 335620675b37SMintz, Yuval struct qed_nvm_image_att image_att; 335720675b37SMintz, Yuval int rc; 335820675b37SMintz, Yuval 335920675b37SMintz, Yuval memset(p_buffer, 0, buffer_len); 336020675b37SMintz, Yuval 3361b60bfdfeSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 336220675b37SMintz, Yuval if (rc) 336320675b37SMintz, Yuval return rc; 336420675b37SMintz, Yuval 336520675b37SMintz, Yuval /* Validate sizes - both the image's and the supplied buffer's */ 336620675b37SMintz, Yuval if (image_att.length <= 4) { 336720675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 336820675b37SMintz, Yuval "Image [%d] is too small - only %d bytes\n", 336920675b37SMintz, Yuval image_id, image_att.length); 337020675b37SMintz, Yuval return -EINVAL; 337120675b37SMintz, Yuval } 337220675b37SMintz, Yuval 337320675b37SMintz, Yuval if (image_att.length > buffer_len) { 337420675b37SMintz, Yuval DP_VERBOSE(p_hwfn, 337520675b37SMintz, Yuval QED_MSG_STORAGE, 337620675b37SMintz, Yuval "Image [%d] is too big - %08x bytes where only %08x are available\n", 337720675b37SMintz, Yuval image_id, image_att.length, buffer_len); 337820675b37SMintz, Yuval return -ENOMEM; 337920675b37SMintz, Yuval } 338020675b37SMintz, Yuval 338120675b37SMintz, Yuval return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 338220675b37SMintz, Yuval p_buffer, image_att.length); 338320675b37SMintz, Yuval } 338420675b37SMintz, Yuval 33859c8517c4STomer Tayar static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 33869c8517c4STomer Tayar { 33879c8517c4STomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 33889c8517c4STomer Tayar 33899c8517c4STomer Tayar switch (res_id) { 33909c8517c4STomer Tayar case QED_SB: 33919c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 33929c8517c4STomer Tayar break; 33939c8517c4STomer Tayar case QED_L2_QUEUE: 33949c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 33959c8517c4STomer Tayar break; 33969c8517c4STomer Tayar case QED_VPORT: 33979c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 33989c8517c4STomer Tayar break; 33999c8517c4STomer Tayar case QED_RSS_ENG: 34009c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 34019c8517c4STomer Tayar break; 34029c8517c4STomer Tayar case QED_PQ: 34039c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 34049c8517c4STomer Tayar break; 34059c8517c4STomer Tayar case QED_RL: 34069c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 34079c8517c4STomer Tayar break; 34089c8517c4STomer Tayar case QED_MAC: 34099c8517c4STomer Tayar case QED_VLAN: 34109c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 34119c8517c4STomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 34129c8517c4STomer Tayar break; 34139c8517c4STomer Tayar case QED_ILT: 34149c8517c4STomer Tayar mfw_res_id = RESOURCE_ILT_E; 34159c8517c4STomer Tayar break; 3416997af5dfSMichal Kalderon case QED_LL2_RAM_QUEUE: 34179c8517c4STomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 34189c8517c4STomer Tayar break; 3419997af5dfSMichal Kalderon case QED_LL2_CTX_QUEUE: 3420997af5dfSMichal Kalderon mfw_res_id = RESOURCE_LL2_CQS_E; 3421997af5dfSMichal Kalderon break; 34229c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 34239c8517c4STomer Tayar case QED_CMDQS_CQS: 34249c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 34259c8517c4STomer Tayar mfw_res_id = RESOURCE_CQS_E; 34269c8517c4STomer Tayar break; 34279c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 34289c8517c4STomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 34299c8517c4STomer Tayar break; 34309c8517c4STomer Tayar case QED_BDQ: 34319c8517c4STomer Tayar mfw_res_id = RESOURCE_BDQ_E; 34329c8517c4STomer Tayar break; 34339c8517c4STomer Tayar default: 34349c8517c4STomer Tayar break; 34359c8517c4STomer Tayar } 34369c8517c4STomer Tayar 34379c8517c4STomer Tayar return mfw_res_id; 34389c8517c4STomer Tayar } 34399c8517c4STomer Tayar 34409c8517c4STomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 2 34412edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 34422edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 34432edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 34442edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 34452edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 34462edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 34479c8517c4STomer Tayar 34489c8517c4STomer Tayar struct qed_resc_alloc_in_params { 34499c8517c4STomer Tayar u32 cmd; 34509c8517c4STomer Tayar enum qed_resources res_id; 34519c8517c4STomer Tayar u32 resc_max_val; 34529c8517c4STomer Tayar }; 34539c8517c4STomer Tayar 34549c8517c4STomer Tayar struct qed_resc_alloc_out_params { 34559c8517c4STomer Tayar u32 mcp_resp; 34569c8517c4STomer Tayar u32 mcp_param; 34579c8517c4STomer Tayar u32 resc_num; 34589c8517c4STomer Tayar u32 resc_start; 34599c8517c4STomer Tayar u32 vf_resc_num; 34609c8517c4STomer Tayar u32 vf_resc_start; 34619c8517c4STomer Tayar u32 flags; 34629c8517c4STomer Tayar }; 34639c8517c4STomer Tayar 34649c8517c4STomer Tayar static int 34659c8517c4STomer Tayar qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 34662edbff8dSTomer Tayar struct qed_ptt *p_ptt, 34679c8517c4STomer Tayar struct qed_resc_alloc_in_params *p_in_params, 34689c8517c4STomer Tayar struct qed_resc_alloc_out_params *p_out_params) 34692edbff8dSTomer Tayar { 34702edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 34719c8517c4STomer Tayar struct resource_info mfw_resc_info; 34722edbff8dSTomer Tayar int rc; 34732edbff8dSTomer Tayar 34749c8517c4STomer Tayar memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 3475bb480242SMintz, Yuval 34769c8517c4STomer Tayar mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 34779c8517c4STomer Tayar if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 34789c8517c4STomer Tayar DP_ERR(p_hwfn, 34799c8517c4STomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 34809c8517c4STomer Tayar p_in_params->res_id, 34819c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id)); 34829c8517c4STomer Tayar return -EINVAL; 34839c8517c4STomer Tayar } 34849c8517c4STomer Tayar 34859c8517c4STomer Tayar switch (p_in_params->cmd) { 34869c8517c4STomer Tayar case DRV_MSG_SET_RESOURCE_VALUE_MSG: 34879c8517c4STomer Tayar mfw_resc_info.size = p_in_params->resc_max_val; 34889c8517c4STomer Tayar /* Fallthrough */ 34899c8517c4STomer Tayar case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 34909c8517c4STomer Tayar break; 34919c8517c4STomer Tayar default: 34929c8517c4STomer Tayar DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 34939c8517c4STomer Tayar p_in_params->cmd); 34949c8517c4STomer Tayar return -EINVAL; 34959c8517c4STomer Tayar } 34969c8517c4STomer Tayar 34979c8517c4STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 34989c8517c4STomer Tayar mb_params.cmd = p_in_params->cmd; 34999c8517c4STomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 35009c8517c4STomer Tayar mb_params.p_data_src = &mfw_resc_info; 35019c8517c4STomer Tayar mb_params.data_src_size = sizeof(mfw_resc_info); 35029c8517c4STomer Tayar mb_params.p_data_dst = mb_params.p_data_src; 35039c8517c4STomer Tayar mb_params.data_dst_size = mb_params.data_src_size; 35049c8517c4STomer Tayar 35059c8517c4STomer Tayar DP_VERBOSE(p_hwfn, 35069c8517c4STomer Tayar QED_MSG_SP, 35079c8517c4STomer Tayar "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 35089c8517c4STomer Tayar p_in_params->cmd, 35099c8517c4STomer Tayar p_in_params->res_id, 35109c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id), 35119c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 35129c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 35139c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 35149c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 35159c8517c4STomer Tayar p_in_params->resc_max_val); 35169c8517c4STomer Tayar 35172edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 35182edbff8dSTomer Tayar if (rc) 35192edbff8dSTomer Tayar return rc; 35202edbff8dSTomer Tayar 35219c8517c4STomer Tayar p_out_params->mcp_resp = mb_params.mcp_resp; 35229c8517c4STomer Tayar p_out_params->mcp_param = mb_params.mcp_param; 35239c8517c4STomer Tayar p_out_params->resc_num = mfw_resc_info.size; 35249c8517c4STomer Tayar p_out_params->resc_start = mfw_resc_info.offset; 35259c8517c4STomer Tayar p_out_params->vf_resc_num = mfw_resc_info.vf_size; 35269c8517c4STomer Tayar p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 35279c8517c4STomer Tayar p_out_params->flags = mfw_resc_info.flags; 35282edbff8dSTomer Tayar 35292edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 35302edbff8dSTomer Tayar QED_MSG_SP, 35319c8517c4STomer Tayar "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 35329c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 35339c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 35349c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 35359c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 35369c8517c4STomer Tayar p_out_params->resc_num, 35379c8517c4STomer Tayar p_out_params->resc_start, 35389c8517c4STomer Tayar p_out_params->vf_resc_num, 35399c8517c4STomer Tayar p_out_params->vf_resc_start, p_out_params->flags); 35409c8517c4STomer Tayar 35419c8517c4STomer Tayar return 0; 35429c8517c4STomer Tayar } 35439c8517c4STomer Tayar 35449c8517c4STomer Tayar int 35459c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 35469c8517c4STomer Tayar struct qed_ptt *p_ptt, 35479c8517c4STomer Tayar enum qed_resources res_id, 35489c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 35499c8517c4STomer Tayar { 35509c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 35519c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 35529c8517c4STomer Tayar int rc; 35539c8517c4STomer Tayar 35549c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 35559c8517c4STomer Tayar in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 35569c8517c4STomer Tayar in_params.res_id = res_id; 35579c8517c4STomer Tayar in_params.resc_max_val = resc_max_val; 35589c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 35599c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 35609c8517c4STomer Tayar &out_params); 35619c8517c4STomer Tayar if (rc) 35629c8517c4STomer Tayar return rc; 35639c8517c4STomer Tayar 35649c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 35659c8517c4STomer Tayar 35669c8517c4STomer Tayar return 0; 35679c8517c4STomer Tayar } 35689c8517c4STomer Tayar 35699c8517c4STomer Tayar int 35709c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 35719c8517c4STomer Tayar struct qed_ptt *p_ptt, 35729c8517c4STomer Tayar enum qed_resources res_id, 35739c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 35749c8517c4STomer Tayar { 35759c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 35769c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 35779c8517c4STomer Tayar int rc; 35789c8517c4STomer Tayar 35799c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 35809c8517c4STomer Tayar in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 35819c8517c4STomer Tayar in_params.res_id = res_id; 35829c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 35839c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 35849c8517c4STomer Tayar &out_params); 35859c8517c4STomer Tayar if (rc) 35869c8517c4STomer Tayar return rc; 35879c8517c4STomer Tayar 35889c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 35899c8517c4STomer Tayar 35909c8517c4STomer Tayar if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 35919c8517c4STomer Tayar *p_resc_num = out_params.resc_num; 35929c8517c4STomer Tayar *p_resc_start = out_params.resc_start; 35939c8517c4STomer Tayar } 35942edbff8dSTomer Tayar 35952edbff8dSTomer Tayar return 0; 35962edbff8dSTomer Tayar } 359718a69e36SMintz, Yuval 359818a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 359918a69e36SMintz, Yuval { 360018a69e36SMintz, Yuval u32 mcp_resp, mcp_param; 360118a69e36SMintz, Yuval 360218a69e36SMintz, Yuval return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 360318a69e36SMintz, Yuval &mcp_resp, &mcp_param); 360418a69e36SMintz, Yuval } 360595691c9cSTomer Tayar 360695691c9cSTomer Tayar static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 360795691c9cSTomer Tayar struct qed_ptt *p_ptt, 360895691c9cSTomer Tayar u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 360995691c9cSTomer Tayar { 361095691c9cSTomer Tayar int rc; 361195691c9cSTomer Tayar 361295691c9cSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 361395691c9cSTomer Tayar p_mcp_resp, p_mcp_param); 361495691c9cSTomer Tayar if (rc) 361595691c9cSTomer Tayar return rc; 361695691c9cSTomer Tayar 361795691c9cSTomer Tayar if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 361895691c9cSTomer Tayar DP_INFO(p_hwfn, 361995691c9cSTomer Tayar "The resource command is unsupported by the MFW\n"); 362095691c9cSTomer Tayar return -EINVAL; 362195691c9cSTomer Tayar } 362295691c9cSTomer Tayar 362395691c9cSTomer Tayar if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 362495691c9cSTomer Tayar u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 362595691c9cSTomer Tayar 362695691c9cSTomer Tayar DP_NOTICE(p_hwfn, 362795691c9cSTomer Tayar "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 362895691c9cSTomer Tayar param, opcode); 362995691c9cSTomer Tayar return -EINVAL; 363095691c9cSTomer Tayar } 363195691c9cSTomer Tayar 363295691c9cSTomer Tayar return rc; 363395691c9cSTomer Tayar } 363495691c9cSTomer Tayar 3635bf774d14SYueHaibing static int 363695691c9cSTomer Tayar __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 363795691c9cSTomer Tayar struct qed_ptt *p_ptt, 363895691c9cSTomer Tayar struct qed_resc_lock_params *p_params) 363995691c9cSTomer Tayar { 364095691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 364195691c9cSTomer Tayar u8 opcode; 364295691c9cSTomer Tayar int rc; 364395691c9cSTomer Tayar 364495691c9cSTomer Tayar switch (p_params->timeout) { 364595691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_DEFAULT: 364695691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ; 364795691c9cSTomer Tayar p_params->timeout = 0; 364895691c9cSTomer Tayar break; 364995691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_NONE: 365095691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_WO_AGING; 365195691c9cSTomer Tayar p_params->timeout = 0; 365295691c9cSTomer Tayar break; 365395691c9cSTomer Tayar default: 365495691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_W_AGING; 365595691c9cSTomer Tayar break; 365695691c9cSTomer Tayar } 365795691c9cSTomer Tayar 365895691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 365995691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 366095691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 366195691c9cSTomer Tayar 366295691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 366395691c9cSTomer Tayar QED_MSG_SP, 366495691c9cSTomer Tayar "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 366595691c9cSTomer Tayar param, p_params->timeout, opcode, p_params->resource); 366695691c9cSTomer Tayar 366795691c9cSTomer Tayar /* Attempt to acquire the resource */ 366895691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 366995691c9cSTomer Tayar if (rc) 367095691c9cSTomer Tayar return rc; 367195691c9cSTomer Tayar 367295691c9cSTomer Tayar /* Analyze the response */ 367395691c9cSTomer Tayar p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 367495691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 367595691c9cSTomer Tayar 367695691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 367795691c9cSTomer Tayar QED_MSG_SP, 367895691c9cSTomer Tayar "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 367995691c9cSTomer Tayar mcp_param, opcode, p_params->owner); 368095691c9cSTomer Tayar 368195691c9cSTomer Tayar switch (opcode) { 368295691c9cSTomer Tayar case RESOURCE_OPCODE_GNT: 368395691c9cSTomer Tayar p_params->b_granted = true; 368495691c9cSTomer Tayar break; 368595691c9cSTomer Tayar case RESOURCE_OPCODE_BUSY: 368695691c9cSTomer Tayar p_params->b_granted = false; 368795691c9cSTomer Tayar break; 368895691c9cSTomer Tayar default: 368995691c9cSTomer Tayar DP_NOTICE(p_hwfn, 369095691c9cSTomer Tayar "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 369195691c9cSTomer Tayar mcp_param, opcode); 369295691c9cSTomer Tayar return -EINVAL; 369395691c9cSTomer Tayar } 369495691c9cSTomer Tayar 369595691c9cSTomer Tayar return 0; 369695691c9cSTomer Tayar } 369795691c9cSTomer Tayar 369895691c9cSTomer Tayar int 369995691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 370095691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 370195691c9cSTomer Tayar { 370295691c9cSTomer Tayar u32 retry_cnt = 0; 370395691c9cSTomer Tayar int rc; 370495691c9cSTomer Tayar 370595691c9cSTomer Tayar do { 370695691c9cSTomer Tayar /* No need for an interval before the first iteration */ 370795691c9cSTomer Tayar if (retry_cnt) { 370895691c9cSTomer Tayar if (p_params->sleep_b4_retry) { 370995691c9cSTomer Tayar u16 retry_interval_in_ms = 371095691c9cSTomer Tayar DIV_ROUND_UP(p_params->retry_interval, 371195691c9cSTomer Tayar 1000); 371295691c9cSTomer Tayar 371395691c9cSTomer Tayar msleep(retry_interval_in_ms); 371495691c9cSTomer Tayar } else { 371595691c9cSTomer Tayar udelay(p_params->retry_interval); 371695691c9cSTomer Tayar } 371795691c9cSTomer Tayar } 371895691c9cSTomer Tayar 371995691c9cSTomer Tayar rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 372095691c9cSTomer Tayar if (rc) 372195691c9cSTomer Tayar return rc; 372295691c9cSTomer Tayar 372395691c9cSTomer Tayar if (p_params->b_granted) 372495691c9cSTomer Tayar break; 372595691c9cSTomer Tayar } while (retry_cnt++ < p_params->retry_num); 372695691c9cSTomer Tayar 372795691c9cSTomer Tayar return 0; 372895691c9cSTomer Tayar } 372995691c9cSTomer Tayar 373095691c9cSTomer Tayar int 373195691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 373295691c9cSTomer Tayar struct qed_ptt *p_ptt, 373395691c9cSTomer Tayar struct qed_resc_unlock_params *p_params) 373495691c9cSTomer Tayar { 373595691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 373695691c9cSTomer Tayar u8 opcode; 373795691c9cSTomer Tayar int rc; 373895691c9cSTomer Tayar 373995691c9cSTomer Tayar opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 374095691c9cSTomer Tayar : RESOURCE_OPCODE_RELEASE; 374195691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 374295691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 374395691c9cSTomer Tayar 374495691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 374595691c9cSTomer Tayar "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 374695691c9cSTomer Tayar param, opcode, p_params->resource); 374795691c9cSTomer Tayar 374895691c9cSTomer Tayar /* Attempt to release the resource */ 374995691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 375095691c9cSTomer Tayar if (rc) 375195691c9cSTomer Tayar return rc; 375295691c9cSTomer Tayar 375395691c9cSTomer Tayar /* Analyze the response */ 375495691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 375595691c9cSTomer Tayar 375695691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 375795691c9cSTomer Tayar "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 375895691c9cSTomer Tayar mcp_param, opcode); 375995691c9cSTomer Tayar 376095691c9cSTomer Tayar switch (opcode) { 376195691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED_PREVIOUS: 376295691c9cSTomer Tayar DP_INFO(p_hwfn, 376395691c9cSTomer Tayar "Resource unlock request for an already released resource [%d]\n", 376495691c9cSTomer Tayar p_params->resource); 376595691c9cSTomer Tayar /* Fallthrough */ 376695691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED: 376795691c9cSTomer Tayar p_params->b_released = true; 376895691c9cSTomer Tayar break; 376995691c9cSTomer Tayar case RESOURCE_OPCODE_WRONG_OWNER: 377095691c9cSTomer Tayar p_params->b_released = false; 377195691c9cSTomer Tayar break; 377295691c9cSTomer Tayar default: 377395691c9cSTomer Tayar DP_NOTICE(p_hwfn, 377495691c9cSTomer Tayar "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 377595691c9cSTomer Tayar mcp_param, opcode); 377695691c9cSTomer Tayar return -EINVAL; 377795691c9cSTomer Tayar } 377895691c9cSTomer Tayar 377995691c9cSTomer Tayar return 0; 378095691c9cSTomer Tayar } 3781f470f22cSsudarsana.kalluru@cavium.com 3782f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3783f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 3784f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 3785f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent) 3786f470f22cSsudarsana.kalluru@cavium.com { 3787f470f22cSsudarsana.kalluru@cavium.com if (p_lock) { 3788f470f22cSsudarsana.kalluru@cavium.com memset(p_lock, 0, sizeof(*p_lock)); 3789f470f22cSsudarsana.kalluru@cavium.com 3790f470f22cSsudarsana.kalluru@cavium.com /* Permanent resources don't require aging, and there's no 3791f470f22cSsudarsana.kalluru@cavium.com * point in trying to acquire them more than once since it's 3792f470f22cSsudarsana.kalluru@cavium.com * unexpected another entity would release them. 3793f470f22cSsudarsana.kalluru@cavium.com */ 3794f470f22cSsudarsana.kalluru@cavium.com if (b_is_permanent) { 3795f470f22cSsudarsana.kalluru@cavium.com p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3796f470f22cSsudarsana.kalluru@cavium.com } else { 3797f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3798f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_interval = 3799f470f22cSsudarsana.kalluru@cavium.com QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3800f470f22cSsudarsana.kalluru@cavium.com p_lock->sleep_b4_retry = true; 3801f470f22cSsudarsana.kalluru@cavium.com } 3802f470f22cSsudarsana.kalluru@cavium.com 3803f470f22cSsudarsana.kalluru@cavium.com p_lock->resource = resource; 3804f470f22cSsudarsana.kalluru@cavium.com } 3805f470f22cSsudarsana.kalluru@cavium.com 3806f470f22cSsudarsana.kalluru@cavium.com if (p_unlock) { 3807f470f22cSsudarsana.kalluru@cavium.com memset(p_unlock, 0, sizeof(*p_unlock)); 3808f470f22cSsudarsana.kalluru@cavium.com p_unlock->resource = resource; 3809f470f22cSsudarsana.kalluru@cavium.com } 3810f470f22cSsudarsana.kalluru@cavium.com } 3811645874e5SSudarsana Reddy Kalluru 3812df9c716dSSudarsana Reddy Kalluru bool qed_mcp_is_smart_an_supported(struct qed_hwfn *p_hwfn) 3813df9c716dSSudarsana Reddy Kalluru { 3814df9c716dSSudarsana Reddy Kalluru return !!(p_hwfn->mcp_info->capabilities & 3815df9c716dSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ); 3816df9c716dSSudarsana Reddy Kalluru } 3817df9c716dSSudarsana Reddy Kalluru 3818645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3819645874e5SSudarsana Reddy Kalluru { 3820645874e5SSudarsana Reddy Kalluru u32 mcp_resp; 3821645874e5SSudarsana Reddy Kalluru int rc; 3822645874e5SSudarsana Reddy Kalluru 3823645874e5SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3824645874e5SSudarsana Reddy Kalluru 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3825645874e5SSudarsana Reddy Kalluru if (!rc) 3826645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3827645874e5SSudarsana Reddy Kalluru "MFW supported features: %08x\n", 3828645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->capabilities); 3829645874e5SSudarsana Reddy Kalluru 3830645874e5SSudarsana Reddy Kalluru return rc; 3831645874e5SSudarsana Reddy Kalluru } 3832645874e5SSudarsana Reddy Kalluru 3833645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3834645874e5SSudarsana Reddy Kalluru { 3835645874e5SSudarsana Reddy Kalluru u32 mcp_resp, mcp_param, features; 3836645874e5SSudarsana Reddy Kalluru 3837e40a826aSSudarsana Reddy Kalluru features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE | 3838ae7e6937SAlexander Lobakin DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK | 3839ae7e6937SAlexander Lobakin DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL; 3840645874e5SSudarsana Reddy Kalluru 3841645874e5SSudarsana Reddy Kalluru return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3842645874e5SSudarsana Reddy Kalluru features, &mcp_resp, &mcp_param); 3843645874e5SSudarsana Reddy Kalluru } 384479284adeSMichal Kalderon 384579284adeSMichal Kalderon int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 384679284adeSMichal Kalderon { 384779284adeSMichal Kalderon struct qed_mcp_mb_params mb_params = {0}; 384879284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 384979284adeSMichal Kalderon u8 fir_valid, l2_valid; 385079284adeSMichal Kalderon int rc; 385179284adeSMichal Kalderon 385279284adeSMichal Kalderon mb_params.cmd = DRV_MSG_CODE_GET_ENGINE_CONFIG; 385379284adeSMichal Kalderon rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 385479284adeSMichal Kalderon if (rc) 385579284adeSMichal Kalderon return rc; 385679284adeSMichal Kalderon 385779284adeSMichal Kalderon if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 385879284adeSMichal Kalderon DP_INFO(p_hwfn, 385979284adeSMichal Kalderon "The get_engine_config command is unsupported by the MFW\n"); 386079284adeSMichal Kalderon return -EOPNOTSUPP; 386179284adeSMichal Kalderon } 386279284adeSMichal Kalderon 386379284adeSMichal Kalderon fir_valid = QED_MFW_GET_FIELD(mb_params.mcp_param, 386479284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID); 386579284adeSMichal Kalderon if (fir_valid) 386679284adeSMichal Kalderon cdev->fir_affin = 386779284adeSMichal Kalderon QED_MFW_GET_FIELD(mb_params.mcp_param, 386879284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE); 386979284adeSMichal Kalderon 387079284adeSMichal Kalderon l2_valid = QED_MFW_GET_FIELD(mb_params.mcp_param, 387179284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID); 387279284adeSMichal Kalderon if (l2_valid) 387379284adeSMichal Kalderon cdev->l2_affin_hint = 387479284adeSMichal Kalderon QED_MFW_GET_FIELD(mb_params.mcp_param, 387579284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE); 387679284adeSMichal Kalderon 387779284adeSMichal Kalderon DP_INFO(p_hwfn, 387879284adeSMichal Kalderon "Engine affinity config: FIR={valid %hhd, value %hhd}, L2_hint={valid %hhd, value %hhd}\n", 387979284adeSMichal Kalderon fir_valid, cdev->fir_affin, l2_valid, cdev->l2_affin_hint); 388079284adeSMichal Kalderon 388179284adeSMichal Kalderon return 0; 388279284adeSMichal Kalderon } 388379284adeSMichal Kalderon 388479284adeSMichal Kalderon int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 388579284adeSMichal Kalderon { 388679284adeSMichal Kalderon struct qed_mcp_mb_params mb_params = {0}; 388779284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 388879284adeSMichal Kalderon int rc; 388979284adeSMichal Kalderon 389079284adeSMichal Kalderon mb_params.cmd = DRV_MSG_CODE_GET_PPFID_BITMAP; 389179284adeSMichal Kalderon rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 389279284adeSMichal Kalderon if (rc) 389379284adeSMichal Kalderon return rc; 389479284adeSMichal Kalderon 389579284adeSMichal Kalderon if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 389679284adeSMichal Kalderon DP_INFO(p_hwfn, 389779284adeSMichal Kalderon "The get_ppfid_bitmap command is unsupported by the MFW\n"); 389879284adeSMichal Kalderon return -EOPNOTSUPP; 389979284adeSMichal Kalderon } 390079284adeSMichal Kalderon 390179284adeSMichal Kalderon cdev->ppfid_bitmap = QED_MFW_GET_FIELD(mb_params.mcp_param, 390279284adeSMichal Kalderon FW_MB_PARAM_PPFID_BITMAP); 390379284adeSMichal Kalderon 390479284adeSMichal Kalderon DP_VERBOSE(p_hwfn, QED_MSG_SP, "PPFID bitmap 0x%hhx\n", 390579284adeSMichal Kalderon cdev->ppfid_bitmap); 390679284adeSMichal Kalderon 390779284adeSMichal Kalderon return 0; 390879284adeSMichal Kalderon } 390938eabdf0SSudarsana Reddy Kalluru 39102d4c8495SSudarsana Reddy Kalluru int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 39112d4c8495SSudarsana Reddy Kalluru u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 39122d4c8495SSudarsana Reddy Kalluru u32 *p_len) 39132d4c8495SSudarsana Reddy Kalluru { 39142d4c8495SSudarsana Reddy Kalluru u32 mb_param = 0, resp, param; 39152d4c8495SSudarsana Reddy Kalluru int rc; 39162d4c8495SSudarsana Reddy Kalluru 39172d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id); 39182d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_INIT) 39192d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39202d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1); 39212d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_FREE) 39222d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39232d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1); 39242d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) { 39252d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39262d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1); 39272d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39282d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID, 39292d4c8495SSudarsana Reddy Kalluru entity_id); 39302d4c8495SSudarsana Reddy Kalluru } 39312d4c8495SSudarsana Reddy Kalluru 39322d4c8495SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 39332d4c8495SSudarsana Reddy Kalluru DRV_MSG_CODE_GET_NVM_CFG_OPTION, 39342d4c8495SSudarsana Reddy Kalluru mb_param, &resp, ¶m, p_len, (u32 *)p_buf); 39352d4c8495SSudarsana Reddy Kalluru 39362d4c8495SSudarsana Reddy Kalluru return rc; 39372d4c8495SSudarsana Reddy Kalluru } 39382d4c8495SSudarsana Reddy Kalluru 393938eabdf0SSudarsana Reddy Kalluru int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 394038eabdf0SSudarsana Reddy Kalluru u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 394138eabdf0SSudarsana Reddy Kalluru u32 len) 394238eabdf0SSudarsana Reddy Kalluru { 394338eabdf0SSudarsana Reddy Kalluru u32 mb_param = 0, resp, param; 394438eabdf0SSudarsana Reddy Kalluru 394538eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id); 394638eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ALL) 394738eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 394838eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ALL, 1); 394938eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_INIT) 395038eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 395138eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1); 395238eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_COMMIT) 395338eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 395438eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT, 1); 395538eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_FREE) 395638eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 395738eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1); 395838eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) { 395938eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 396038eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1); 396138eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 396238eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID, 396338eabdf0SSudarsana Reddy Kalluru entity_id); 396438eabdf0SSudarsana Reddy Kalluru } 396538eabdf0SSudarsana Reddy Kalluru 396638eabdf0SSudarsana Reddy Kalluru return qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, 396738eabdf0SSudarsana Reddy Kalluru DRV_MSG_CODE_SET_NVM_CFG_OPTION, 396838eabdf0SSudarsana Reddy Kalluru mb_param, &resp, ¶m, len, (u32 *)p_buf); 396938eabdf0SSudarsana Reddy Kalluru } 3970d8d6c5a7SIgor Russkikh 3971d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_SIZE MCP_DRV_NVM_BUF_LEN 3972d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_HEADER_SIZE sizeof(u32) 3973d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE \ 3974d8d6c5a7SIgor Russkikh (QED_MCP_DBG_DATA_MAX_SIZE - QED_MCP_DBG_DATA_MAX_HEADER_SIZE) 3975d8d6c5a7SIgor Russkikh 3976d8d6c5a7SIgor Russkikh static int 3977d8d6c5a7SIgor Russkikh __qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn, 3978d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, u8 *p_buf, u8 size) 3979d8d6c5a7SIgor Russkikh { 3980d8d6c5a7SIgor Russkikh struct qed_mcp_mb_params mb_params; 3981d8d6c5a7SIgor Russkikh int rc; 3982d8d6c5a7SIgor Russkikh 3983d8d6c5a7SIgor Russkikh if (size > QED_MCP_DBG_DATA_MAX_SIZE) { 3984d8d6c5a7SIgor Russkikh DP_ERR(p_hwfn, 3985d8d6c5a7SIgor Russkikh "Debug data size is %d while it should not exceed %d\n", 3986d8d6c5a7SIgor Russkikh size, QED_MCP_DBG_DATA_MAX_SIZE); 3987d8d6c5a7SIgor Russkikh return -EINVAL; 3988d8d6c5a7SIgor Russkikh } 3989d8d6c5a7SIgor Russkikh 3990d8d6c5a7SIgor Russkikh memset(&mb_params, 0, sizeof(mb_params)); 3991d8d6c5a7SIgor Russkikh mb_params.cmd = DRV_MSG_CODE_DEBUG_DATA_SEND; 3992d8d6c5a7SIgor Russkikh SET_MFW_FIELD(mb_params.param, DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE, size); 3993d8d6c5a7SIgor Russkikh mb_params.p_data_src = p_buf; 3994d8d6c5a7SIgor Russkikh mb_params.data_src_size = size; 3995d8d6c5a7SIgor Russkikh rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 3996d8d6c5a7SIgor Russkikh if (rc) 3997d8d6c5a7SIgor Russkikh return rc; 3998d8d6c5a7SIgor Russkikh 3999d8d6c5a7SIgor Russkikh if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 4000d8d6c5a7SIgor Russkikh DP_INFO(p_hwfn, 4001d8d6c5a7SIgor Russkikh "The DEBUG_DATA_SEND command is unsupported by the MFW\n"); 4002d8d6c5a7SIgor Russkikh return -EOPNOTSUPP; 4003d8d6c5a7SIgor Russkikh } else if (mb_params.mcp_resp == (u32)FW_MSG_CODE_DEBUG_NOT_ENABLED) { 4004d8d6c5a7SIgor Russkikh DP_INFO(p_hwfn, "The DEBUG_DATA_SEND command is not enabled\n"); 4005d8d6c5a7SIgor Russkikh return -EBUSY; 4006d8d6c5a7SIgor Russkikh } else if (mb_params.mcp_resp != (u32)FW_MSG_CODE_DEBUG_DATA_SEND_OK) { 4007d8d6c5a7SIgor Russkikh DP_NOTICE(p_hwfn, 4008d8d6c5a7SIgor Russkikh "Failed to send debug data to the MFW [resp 0x%08x]\n", 4009d8d6c5a7SIgor Russkikh mb_params.mcp_resp); 4010d8d6c5a7SIgor Russkikh return -EINVAL; 4011d8d6c5a7SIgor Russkikh } 4012d8d6c5a7SIgor Russkikh 4013d8d6c5a7SIgor Russkikh return 0; 4014d8d6c5a7SIgor Russkikh } 4015d8d6c5a7SIgor Russkikh 4016d8d6c5a7SIgor Russkikh enum qed_mcp_dbg_data_type { 4017d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_TYPE_RAW, 4018d8d6c5a7SIgor Russkikh }; 4019d8d6c5a7SIgor Russkikh 4020d8d6c5a7SIgor Russkikh /* Header format: [31:28] PFID, [27:20] flags, [19:12] type, [11:0] S/N */ 4021d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_SN_OFFSET 0 4022d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_SN_MASK 0x00000fff 4023d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_TYPE_OFFSET 12 4024d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_TYPE_MASK 0x000ff000 4025d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_OFFSET 20 4026d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_MASK 0x0ff00000 4027d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_PF_OFFSET 28 4028d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_PF_MASK 0xf0000000 4029d8d6c5a7SIgor Russkikh 4030d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_FIRST 0x1 4031d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_LAST 0x2 4032d8d6c5a7SIgor Russkikh 4033d8d6c5a7SIgor Russkikh static int 4034d8d6c5a7SIgor Russkikh qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn, 4035d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, 4036d8d6c5a7SIgor Russkikh enum qed_mcp_dbg_data_type type, u8 *p_buf, u32 size) 4037d8d6c5a7SIgor Russkikh { 4038d8d6c5a7SIgor Russkikh u8 raw_data[QED_MCP_DBG_DATA_MAX_SIZE], *p_tmp_buf = p_buf; 4039d8d6c5a7SIgor Russkikh u32 tmp_size = size, *p_header, *p_payload; 4040d8d6c5a7SIgor Russkikh u8 flags = 0; 4041d8d6c5a7SIgor Russkikh u16 seq; 4042d8d6c5a7SIgor Russkikh int rc; 4043d8d6c5a7SIgor Russkikh 4044d8d6c5a7SIgor Russkikh p_header = (u32 *)raw_data; 4045d8d6c5a7SIgor Russkikh p_payload = (u32 *)(raw_data + QED_MCP_DBG_DATA_MAX_HEADER_SIZE); 4046d8d6c5a7SIgor Russkikh 4047d8d6c5a7SIgor Russkikh seq = (u16)atomic_inc_return(&p_hwfn->mcp_info->dbg_data_seq); 4048d8d6c5a7SIgor Russkikh 4049d8d6c5a7SIgor Russkikh /* First chunk is marked as 'first' */ 4050d8d6c5a7SIgor Russkikh flags |= QED_MCP_DBG_DATA_HDR_FLAGS_FIRST; 4051d8d6c5a7SIgor Russkikh 4052d8d6c5a7SIgor Russkikh *p_header = 0; 4053d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_SN, seq); 4054d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_TYPE, type); 4055d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags); 4056d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_PF, p_hwfn->abs_pf_id); 4057d8d6c5a7SIgor Russkikh 4058d8d6c5a7SIgor Russkikh while (tmp_size > QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE) { 4059d8d6c5a7SIgor Russkikh memcpy(p_payload, p_tmp_buf, QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE); 4060d8d6c5a7SIgor Russkikh rc = __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data, 4061d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_MAX_SIZE); 4062d8d6c5a7SIgor Russkikh if (rc) 4063d8d6c5a7SIgor Russkikh return rc; 4064d8d6c5a7SIgor Russkikh 4065d8d6c5a7SIgor Russkikh /* Clear the 'first' marking after sending the first chunk */ 4066d8d6c5a7SIgor Russkikh if (p_tmp_buf == p_buf) { 4067d8d6c5a7SIgor Russkikh flags &= ~QED_MCP_DBG_DATA_HDR_FLAGS_FIRST; 4068d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, 4069d8d6c5a7SIgor Russkikh flags); 4070d8d6c5a7SIgor Russkikh } 4071d8d6c5a7SIgor Russkikh 4072d8d6c5a7SIgor Russkikh p_tmp_buf += QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE; 4073d8d6c5a7SIgor Russkikh tmp_size -= QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE; 4074d8d6c5a7SIgor Russkikh } 4075d8d6c5a7SIgor Russkikh 4076d8d6c5a7SIgor Russkikh /* Last chunk is marked as 'last' */ 4077d8d6c5a7SIgor Russkikh flags |= QED_MCP_DBG_DATA_HDR_FLAGS_LAST; 4078d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags); 4079d8d6c5a7SIgor Russkikh memcpy(p_payload, p_tmp_buf, tmp_size); 4080d8d6c5a7SIgor Russkikh 4081d8d6c5a7SIgor Russkikh /* Casting the left size to u8 is ok since at this point it is <= 32 */ 4082d8d6c5a7SIgor Russkikh return __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data, 4083d8d6c5a7SIgor Russkikh (u8)(QED_MCP_DBG_DATA_MAX_HEADER_SIZE + 4084d8d6c5a7SIgor Russkikh tmp_size)); 4085d8d6c5a7SIgor Russkikh } 4086d8d6c5a7SIgor Russkikh 4087d8d6c5a7SIgor Russkikh int 4088d8d6c5a7SIgor Russkikh qed_mcp_send_raw_debug_data(struct qed_hwfn *p_hwfn, 4089d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, u8 *p_buf, u32 size) 4090d8d6c5a7SIgor Russkikh { 4091d8d6c5a7SIgor Russkikh return qed_mcp_send_debug_data(p_hwfn, p_ptt, 4092d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_TYPE_RAW, p_buf, size); 4093d8d6c5a7SIgor Russkikh } 4094