1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/delay.h> 36fe56b9e6SYuval Mintz #include <linux/errno.h> 37fe56b9e6SYuval Mintz #include <linux/kernel.h> 38fe56b9e6SYuval Mintz #include <linux/slab.h> 395529bad9STomer Tayar #include <linux/spinlock.h> 40fe56b9e6SYuval Mintz #include <linux/string.h> 410fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 42fe56b9e6SYuval Mintz #include "qed.h" 4339651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 44fe56b9e6SYuval Mintz #include "qed_hsi.h" 45fe56b9e6SYuval Mintz #include "qed_hw.h" 46fe56b9e6SYuval Mintz #include "qed_mcp.h" 47fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 481408cc1fSYuval Mintz #include "qed_sriov.h" 491408cc1fSYuval Mintz 50fe56b9e6SYuval Mintz #define CHIP_MCP_RESP_ITER_US 10 51fe56b9e6SYuval Mintz 52fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 53fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 54fe56b9e6SYuval Mintz 55fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 56fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 57fe56b9e6SYuval Mintz _val) 58fe56b9e6SYuval Mintz 59fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 60fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 61fe56b9e6SYuval Mintz 62fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 63fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 64fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 67fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 68fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 69fe56b9e6SYuval Mintz 70fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 71fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 72fe56b9e6SYuval Mintz 73fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 74fe56b9e6SYuval Mintz 75fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 76fe56b9e6SYuval Mintz { 77fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 78fe56b9e6SYuval Mintz return false; 79fe56b9e6SYuval Mintz return true; 80fe56b9e6SYuval Mintz } 81fe56b9e6SYuval Mintz 821a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 83fe56b9e6SYuval Mintz { 84fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 85fe56b9e6SYuval Mintz PUBLIC_PORT); 86fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 87fe56b9e6SYuval Mintz 88fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 89fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 90fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 91fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 92fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 93fe56b9e6SYuval Mintz } 94fe56b9e6SYuval Mintz 951a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 96fe56b9e6SYuval Mintz { 97fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 98fe56b9e6SYuval Mintz u32 tmp, i; 99fe56b9e6SYuval Mintz 100fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 101fe56b9e6SYuval Mintz return; 102fe56b9e6SYuval Mintz 103fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 104fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 105fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 106fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 107fe56b9e6SYuval Mintz 108fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 109fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 110fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 111fe56b9e6SYuval Mintz } 112fe56b9e6SYuval Mintz } 113fe56b9e6SYuval Mintz 1144ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 1154ed1eea8STomer Tayar struct list_head list; 1164ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 1174ed1eea8STomer Tayar u16 expected_seq_num; 1184ed1eea8STomer Tayar bool b_is_completed; 1194ed1eea8STomer Tayar }; 1204ed1eea8STomer Tayar 1214ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1224ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1234ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1244ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1254ed1eea8STomer Tayar u16 expected_seq_num) 1264ed1eea8STomer Tayar { 1274ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1284ed1eea8STomer Tayar 1294ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1304ed1eea8STomer Tayar if (!p_cmd_elem) 1314ed1eea8STomer Tayar goto out; 1324ed1eea8STomer Tayar 1334ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1344ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1354ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1364ed1eea8STomer Tayar out: 1374ed1eea8STomer Tayar return p_cmd_elem; 1384ed1eea8STomer Tayar } 1394ed1eea8STomer Tayar 1404ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1414ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1424ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1434ed1eea8STomer Tayar { 1444ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1454ed1eea8STomer Tayar kfree(p_cmd_elem); 1464ed1eea8STomer Tayar } 1474ed1eea8STomer Tayar 1484ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1494ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1504ed1eea8STomer Tayar u16 seq_num) 1514ed1eea8STomer Tayar { 1524ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1534ed1eea8STomer Tayar 1544ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1554ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1564ed1eea8STomer Tayar return p_cmd_elem; 1574ed1eea8STomer Tayar } 1584ed1eea8STomer Tayar 1594ed1eea8STomer Tayar return NULL; 1604ed1eea8STomer Tayar } 1614ed1eea8STomer Tayar 162fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 163fe56b9e6SYuval Mintz { 164fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1654ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1664ed1eea8STomer Tayar 167fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 168fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1694ed1eea8STomer Tayar 1704ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1714ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1724ed1eea8STomer Tayar p_tmp, 1734ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1744ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 175fe56b9e6SYuval Mintz } 1764ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1774ed1eea8STomer Tayar } 1784ed1eea8STomer Tayar 179fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 180fe56b9e6SYuval Mintz 181fe56b9e6SYuval Mintz return 0; 182fe56b9e6SYuval Mintz } 183fe56b9e6SYuval Mintz 1841a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 185fe56b9e6SYuval Mintz { 186fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 187fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 188fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 189fe56b9e6SYuval Mintz 190fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 191fe56b9e6SYuval Mintz if (!p_info->public_base) 192fe56b9e6SYuval Mintz return 0; 193fe56b9e6SYuval Mintz 194fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 195fe56b9e6SYuval Mintz 196fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 197fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 198fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 199fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 200fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 201fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 202fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 203fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 204fe56b9e6SYuval Mintz 205fe56b9e6SYuval Mintz /* Set the MFW MB address */ 206fe56b9e6SYuval Mintz mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 207fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 208fe56b9e6SYuval Mintz PUBLIC_MFW_MB)); 209fe56b9e6SYuval Mintz p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 210fe56b9e6SYuval Mintz p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr); 211fe56b9e6SYuval Mintz 212fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 213fe56b9e6SYuval Mintz * the first command 214fe56b9e6SYuval Mintz */ 215fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 216fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 217fe56b9e6SYuval Mintz 218fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 219fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 220fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 221fe56b9e6SYuval Mintz 2224ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 223fe56b9e6SYuval Mintz 224fe56b9e6SYuval Mintz return 0; 225fe56b9e6SYuval Mintz } 226fe56b9e6SYuval Mintz 2271a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 228fe56b9e6SYuval Mintz { 229fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 230fe56b9e6SYuval Mintz u32 size; 231fe56b9e6SYuval Mintz 232fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 23360fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 234fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 235fe56b9e6SYuval Mintz goto err; 236fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 237fe56b9e6SYuval Mintz 2384ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2394ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2404ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2414ed1eea8STomer Tayar 2424ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2434ed1eea8STomer Tayar 244fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 245fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 246fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 247fe56b9e6SYuval Mintz * the MCP is not initialized 248fe56b9e6SYuval Mintz */ 249fe56b9e6SYuval Mintz return 0; 250fe56b9e6SYuval Mintz } 251fe56b9e6SYuval Mintz 252fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 25360fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 25483aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 255fe56b9e6SYuval Mintz if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr) 256fe56b9e6SYuval Mintz goto err; 257fe56b9e6SYuval Mintz 258fe56b9e6SYuval Mintz return 0; 259fe56b9e6SYuval Mintz 260fe56b9e6SYuval Mintz err: 261fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 262fe56b9e6SYuval Mintz return -ENOMEM; 263fe56b9e6SYuval Mintz } 264fe56b9e6SYuval Mintz 2654ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 2664ed1eea8STomer Tayar struct qed_ptt *p_ptt) 2675529bad9STomer Tayar { 2684ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 2695529bad9STomer Tayar 2704ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 2714ed1eea8STomer Tayar * time and now. 2725529bad9STomer Tayar */ 2734ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 2744ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 2754ed1eea8STomer Tayar QED_MSG_SP, 2764ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 2774ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 2785529bad9STomer Tayar 2794ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 2804ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2815529bad9STomer Tayar } 2825529bad9STomer Tayar } 2835529bad9STomer Tayar 2841a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 285fe56b9e6SYuval Mintz { 2864ed1eea8STomer Tayar u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0; 287fe56b9e6SYuval Mintz int rc = 0; 288fe56b9e6SYuval Mintz 2894ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 2904ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 2914ed1eea8STomer Tayar 2924ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 2935529bad9STomer Tayar 294fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 2954ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 2964ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 2974ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 298fe56b9e6SYuval Mintz 299fe56b9e6SYuval Mintz do { 300fe56b9e6SYuval Mintz /* Wait for MFW response */ 301fe56b9e6SYuval Mintz udelay(delay); 302fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 303fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 304fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 305fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 306fe56b9e6SYuval Mintz 307fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 308fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 309fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 310fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 311fe56b9e6SYuval Mintz } else { 312fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 313fe56b9e6SYuval Mintz rc = -EAGAIN; 314fe56b9e6SYuval Mintz } 315fe56b9e6SYuval Mintz 3164ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3175529bad9STomer Tayar 318fe56b9e6SYuval Mintz return rc; 319fe56b9e6SYuval Mintz } 320fe56b9e6SYuval Mintz 3214ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3224ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 323fe56b9e6SYuval Mintz { 3244ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3254ed1eea8STomer Tayar 3264ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3274ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3284ed1eea8STomer Tayar */ 3294ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3304ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3314ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3324ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3334ed1eea8STomer Tayar } 3344ed1eea8STomer Tayar 3354ed1eea8STomer Tayar return false; 3364ed1eea8STomer Tayar } 3374ed1eea8STomer Tayar 3384ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3394ed1eea8STomer Tayar static int 3404ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3414ed1eea8STomer Tayar { 3424ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3434ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3444ed1eea8STomer Tayar u32 mcp_resp; 3454ed1eea8STomer Tayar u16 seq_num; 3464ed1eea8STomer Tayar 3474ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3484ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3494ed1eea8STomer Tayar 3504ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3514ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3524ed1eea8STomer Tayar return -EAGAIN; 3534ed1eea8STomer Tayar 3544ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3554ed1eea8STomer Tayar if (!p_cmd_elem) { 3564ed1eea8STomer Tayar DP_ERR(p_hwfn, 3574ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 3584ed1eea8STomer Tayar seq_num); 3594ed1eea8STomer Tayar return -EINVAL; 3604ed1eea8STomer Tayar } 3614ed1eea8STomer Tayar 3624ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 3634ed1eea8STomer Tayar 3644ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 3654ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 3664ed1eea8STomer Tayar 3674ed1eea8STomer Tayar /* Get the MFW param */ 3684ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 3694ed1eea8STomer Tayar 3704ed1eea8STomer Tayar /* Get the union data */ 3712f67af8cSTomer Tayar if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 3724ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3734ed1eea8STomer Tayar offsetof(struct public_drv_mb, 3744ed1eea8STomer Tayar union_data); 3754ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 3762f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 3774ed1eea8STomer Tayar } 3784ed1eea8STomer Tayar 3794ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 3804ed1eea8STomer Tayar 3814ed1eea8STomer Tayar return 0; 3824ed1eea8STomer Tayar } 3834ed1eea8STomer Tayar 3844ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3854ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 3864ed1eea8STomer Tayar struct qed_ptt *p_ptt, 3874ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 3884ed1eea8STomer Tayar u16 seq_num) 3894ed1eea8STomer Tayar { 3904ed1eea8STomer Tayar union drv_union_data union_data; 3914ed1eea8STomer Tayar u32 union_data_addr; 3924ed1eea8STomer Tayar 3934ed1eea8STomer Tayar /* Set the union data */ 3944ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3954ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 3964ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 3972f67af8cSTomer Tayar if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 3984ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 3992f67af8cSTomer Tayar p_mb_params->data_src_size); 4004ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4014ed1eea8STomer Tayar sizeof(union_data)); 4024ed1eea8STomer Tayar 4034ed1eea8STomer Tayar /* Set the drv param */ 4044ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4054ed1eea8STomer Tayar 4064ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4074ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4084ed1eea8STomer Tayar 4094ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4104ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4114ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4124ed1eea8STomer Tayar } 4134ed1eea8STomer Tayar 4144ed1eea8STomer Tayar static int 4154ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4164ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4174ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4184ed1eea8STomer Tayar u32 max_retries, u32 delay) 4194ed1eea8STomer Tayar { 4204ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4214ed1eea8STomer Tayar u32 cnt = 0; 4224ed1eea8STomer Tayar u16 seq_num; 423fe56b9e6SYuval Mintz int rc = 0; 424fe56b9e6SYuval Mintz 4254ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 426fe56b9e6SYuval Mintz do { 4274ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4284ed1eea8STomer Tayar * pending command is completed during this iteration. 4294ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4304ed1eea8STomer Tayar */ 4314ed1eea8STomer Tayar 4324ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4334ed1eea8STomer Tayar 4344ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 4354ed1eea8STomer Tayar break; 4364ed1eea8STomer Tayar 4374ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 4384ed1eea8STomer Tayar if (!rc) 4394ed1eea8STomer Tayar break; 4404ed1eea8STomer Tayar else if (rc != -EAGAIN) 4414ed1eea8STomer Tayar goto err; 4424ed1eea8STomer Tayar 4434ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 444fe56b9e6SYuval Mintz udelay(delay); 4454ed1eea8STomer Tayar } while (++cnt < max_retries); 446fe56b9e6SYuval Mintz 4474ed1eea8STomer Tayar if (cnt >= max_retries) { 4484ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 4494ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 4504ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 4514ed1eea8STomer Tayar return -EAGAIN; 452fe56b9e6SYuval Mintz } 4534ed1eea8STomer Tayar 4544ed1eea8STomer Tayar /* Send the mailbox command */ 4554ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 4564ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 4574ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 4584ed1eea8STomer Tayar if (!p_cmd_elem) 4594ed1eea8STomer Tayar goto err; 4604ed1eea8STomer Tayar 4614ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 4624ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 4634ed1eea8STomer Tayar 4644ed1eea8STomer Tayar /* Wait for the MFW response */ 4654ed1eea8STomer Tayar do { 4664ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 4674ed1eea8STomer Tayar * command is completed during this iteration. 4684ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 4694ed1eea8STomer Tayar */ 4704ed1eea8STomer Tayar 4714ed1eea8STomer Tayar udelay(delay); 4724ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4734ed1eea8STomer Tayar 4744ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 4754ed1eea8STomer Tayar break; 4764ed1eea8STomer Tayar 4774ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 4784ed1eea8STomer Tayar if (!rc) 4794ed1eea8STomer Tayar break; 4804ed1eea8STomer Tayar else if (rc != -EAGAIN) 4814ed1eea8STomer Tayar goto err; 4824ed1eea8STomer Tayar 4834ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 4844ed1eea8STomer Tayar } while (++cnt < max_retries); 4854ed1eea8STomer Tayar 4864ed1eea8STomer Tayar if (cnt >= max_retries) { 4874ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 4884ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 4894ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 4904ed1eea8STomer Tayar 4914ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4924ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 4934ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 4944ed1eea8STomer Tayar 4954ed1eea8STomer Tayar return -EAGAIN; 4964ed1eea8STomer Tayar } 4974ed1eea8STomer Tayar 4984ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 4994ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5004ed1eea8STomer Tayar 5014ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5024ed1eea8STomer Tayar QED_MSG_SP, 5034ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5044ed1eea8STomer Tayar p_mb_params->mcp_resp, 5054ed1eea8STomer Tayar p_mb_params->mcp_param, 5064ed1eea8STomer Tayar (cnt * delay) / 1000, (cnt * delay) % 1000); 5074ed1eea8STomer Tayar 5084ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5094ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5104ed1eea8STomer Tayar 5114ed1eea8STomer Tayar return 0; 5124ed1eea8STomer Tayar 5134ed1eea8STomer Tayar err: 5144ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 515fe56b9e6SYuval Mintz return rc; 516fe56b9e6SYuval Mintz } 517fe56b9e6SYuval Mintz 5185529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 519fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 5205529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 521fe56b9e6SYuval Mintz { 5222f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 5234ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 5244ed1eea8STomer Tayar u32 delay = CHIP_MCP_RESP_ITER_US; 525fe56b9e6SYuval Mintz 526fe56b9e6SYuval Mintz /* MCP not initialized */ 527fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 528fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 529fe56b9e6SYuval Mintz return -EBUSY; 530fe56b9e6SYuval Mintz } 531fe56b9e6SYuval Mintz 5322f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 5332f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 5342f67af8cSTomer Tayar DP_ERR(p_hwfn, 5352f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 5362f67af8cSTomer Tayar p_mb_params->data_src_size, 5372f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 5382f67af8cSTomer Tayar return -EINVAL; 5392f67af8cSTomer Tayar } 5402f67af8cSTomer Tayar 5414ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 5424ed1eea8STomer Tayar delay); 543fe56b9e6SYuval Mintz } 544fe56b9e6SYuval Mintz 5455529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 5465529bad9STomer Tayar struct qed_ptt *p_ptt, 5475529bad9STomer Tayar u32 cmd, 5485529bad9STomer Tayar u32 param, 5495529bad9STomer Tayar u32 *o_mcp_resp, 5505529bad9STomer Tayar u32 *o_mcp_param) 551fe56b9e6SYuval Mintz { 5525529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 5535529bad9STomer Tayar int rc; 554fe56b9e6SYuval Mintz 5555529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 5565529bad9STomer Tayar mb_params.cmd = cmd; 5575529bad9STomer Tayar mb_params.param = param; 55814d39648SMintz, Yuval 5595529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 5605529bad9STomer Tayar if (rc) 5615529bad9STomer Tayar return rc; 5625529bad9STomer Tayar 5635529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 5645529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 5655529bad9STomer Tayar 5665529bad9STomer Tayar return 0; 567fe56b9e6SYuval Mintz } 568fe56b9e6SYuval Mintz 5694102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 5704102426fSTomer Tayar struct qed_ptt *p_ptt, 5714102426fSTomer Tayar u32 cmd, 5724102426fSTomer Tayar u32 param, 5734102426fSTomer Tayar u32 *o_mcp_resp, 5744102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 5754102426fSTomer Tayar { 5764102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 5772f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 5784102426fSTomer Tayar int rc; 5794102426fSTomer Tayar 5804102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 5814102426fSTomer Tayar mb_params.cmd = cmd; 5824102426fSTomer Tayar mb_params.param = param; 5832f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 5842f67af8cSTomer Tayar 5852f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 5862f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 5872f67af8cSTomer Tayar 5884102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 5894102426fSTomer Tayar if (rc) 5904102426fSTomer Tayar return rc; 5914102426fSTomer Tayar 5924102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 5934102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 5944102426fSTomer Tayar 5954102426fSTomer Tayar *o_txn_size = *o_mcp_param; 5962f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 5974102426fSTomer Tayar 5984102426fSTomer Tayar return 0; 5994102426fSTomer Tayar } 6004102426fSTomer Tayar 6015d24bcf1STomer Tayar static bool 6025d24bcf1STomer Tayar qed_mcp_can_force_load(u8 drv_role, 6035d24bcf1STomer Tayar u8 exist_drv_role, 6045d24bcf1STomer Tayar enum qed_override_force_load override_force_load) 605fe56b9e6SYuval Mintz { 6065d24bcf1STomer Tayar bool can_force_load = false; 6075d24bcf1STomer Tayar 6085d24bcf1STomer Tayar switch (override_force_load) { 6095d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 6105d24bcf1STomer Tayar can_force_load = true; 6115d24bcf1STomer Tayar break; 6125d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_NEVER: 6135d24bcf1STomer Tayar can_force_load = false; 6145d24bcf1STomer Tayar break; 6155d24bcf1STomer Tayar default: 6165d24bcf1STomer Tayar can_force_load = (drv_role == DRV_ROLE_OS && 6175d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_PREBOOT) || 6185d24bcf1STomer Tayar (drv_role == DRV_ROLE_KDUMP && 6195d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_OS); 6205d24bcf1STomer Tayar break; 6215d24bcf1STomer Tayar } 6225d24bcf1STomer Tayar 6235d24bcf1STomer Tayar return can_force_load; 6245d24bcf1STomer Tayar } 6255d24bcf1STomer Tayar 6265d24bcf1STomer Tayar static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 6275d24bcf1STomer Tayar struct qed_ptt *p_ptt) 6285d24bcf1STomer Tayar { 6295d24bcf1STomer Tayar u32 resp = 0, param = 0; 630fe56b9e6SYuval Mintz int rc; 631fe56b9e6SYuval Mintz 6325d24bcf1STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 6335d24bcf1STomer Tayar &resp, ¶m); 6345d24bcf1STomer Tayar if (rc) 6355d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 6365d24bcf1STomer Tayar "Failed to send cancel load request, rc = %d\n", rc); 637fe56b9e6SYuval Mintz 638fe56b9e6SYuval Mintz return rc; 639fe56b9e6SYuval Mintz } 640fe56b9e6SYuval Mintz 6415d24bcf1STomer Tayar #define CONFIG_QEDE_BITMAP_IDX BIT(0) 6425d24bcf1STomer Tayar #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 6435d24bcf1STomer Tayar #define CONFIG_QEDR_BITMAP_IDX BIT(2) 6445d24bcf1STomer Tayar #define CONFIG_QEDF_BITMAP_IDX BIT(4) 6455d24bcf1STomer Tayar #define CONFIG_QEDI_BITMAP_IDX BIT(5) 6465d24bcf1STomer Tayar #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 6475529bad9STomer Tayar 6485d24bcf1STomer Tayar static u32 qed_get_config_bitmap(void) 6495d24bcf1STomer Tayar { 6505d24bcf1STomer Tayar u32 config_bitmap = 0x0; 6515d24bcf1STomer Tayar 6525d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QEDE)) 6535d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 6545d24bcf1STomer Tayar 6555d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_SRIOV)) 6565d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 6575d24bcf1STomer Tayar 6585d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_RDMA)) 6595d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 6605d24bcf1STomer Tayar 6615d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_FCOE)) 6625d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 6635d24bcf1STomer Tayar 6645d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_ISCSI)) 6655d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 6665d24bcf1STomer Tayar 6675d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_LL2)) 6685d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 6695d24bcf1STomer Tayar 6705d24bcf1STomer Tayar return config_bitmap; 6715d24bcf1STomer Tayar } 6725d24bcf1STomer Tayar 6735d24bcf1STomer Tayar struct qed_load_req_in_params { 6745d24bcf1STomer Tayar u8 hsi_ver; 6755d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 6765d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_1 1 6775d24bcf1STomer Tayar u32 drv_ver_0; 6785d24bcf1STomer Tayar u32 drv_ver_1; 6795d24bcf1STomer Tayar u32 fw_ver; 6805d24bcf1STomer Tayar u8 drv_role; 6815d24bcf1STomer Tayar u8 timeout_val; 6825d24bcf1STomer Tayar u8 force_cmd; 6835d24bcf1STomer Tayar bool avoid_eng_reset; 6845d24bcf1STomer Tayar }; 6855d24bcf1STomer Tayar 6865d24bcf1STomer Tayar struct qed_load_req_out_params { 6875d24bcf1STomer Tayar u32 load_code; 6885d24bcf1STomer Tayar u32 exist_drv_ver_0; 6895d24bcf1STomer Tayar u32 exist_drv_ver_1; 6905d24bcf1STomer Tayar u32 exist_fw_ver; 6915d24bcf1STomer Tayar u8 exist_drv_role; 6925d24bcf1STomer Tayar u8 mfw_hsi_ver; 6935d24bcf1STomer Tayar bool drv_exists; 6945d24bcf1STomer Tayar }; 6955d24bcf1STomer Tayar 6965d24bcf1STomer Tayar static int 6975d24bcf1STomer Tayar __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 6985d24bcf1STomer Tayar struct qed_ptt *p_ptt, 6995d24bcf1STomer Tayar struct qed_load_req_in_params *p_in_params, 7005d24bcf1STomer Tayar struct qed_load_req_out_params *p_out_params) 7015d24bcf1STomer Tayar { 7025d24bcf1STomer Tayar struct qed_mcp_mb_params mb_params; 7035d24bcf1STomer Tayar struct load_req_stc load_req; 7045d24bcf1STomer Tayar struct load_rsp_stc load_rsp; 7055d24bcf1STomer Tayar u32 hsi_ver; 7065d24bcf1STomer Tayar int rc; 7075d24bcf1STomer Tayar 7085d24bcf1STomer Tayar memset(&load_req, 0, sizeof(load_req)); 7095d24bcf1STomer Tayar load_req.drv_ver_0 = p_in_params->drv_ver_0; 7105d24bcf1STomer Tayar load_req.drv_ver_1 = p_in_params->drv_ver_1; 7115d24bcf1STomer Tayar load_req.fw_ver = p_in_params->fw_ver; 7125d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 7135d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 7145d24bcf1STomer Tayar p_in_params->timeout_val); 7155d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 7165d24bcf1STomer Tayar p_in_params->force_cmd); 7175d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 7185d24bcf1STomer Tayar p_in_params->avoid_eng_reset); 7195d24bcf1STomer Tayar 7205d24bcf1STomer Tayar hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 7215d24bcf1STomer Tayar DRV_ID_MCP_HSI_VER_CURRENT : 7225d24bcf1STomer Tayar (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 7235d24bcf1STomer Tayar 7245d24bcf1STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 7255d24bcf1STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 7265d24bcf1STomer Tayar mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 7275d24bcf1STomer Tayar mb_params.p_data_src = &load_req; 7285d24bcf1STomer Tayar mb_params.data_src_size = sizeof(load_req); 7295d24bcf1STomer Tayar mb_params.p_data_dst = &load_rsp; 7305d24bcf1STomer Tayar mb_params.data_dst_size = sizeof(load_rsp); 7315d24bcf1STomer Tayar 7325d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 7335d24bcf1STomer Tayar "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 7345d24bcf1STomer Tayar mb_params.param, 7355d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 7365d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 7375d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 7385d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 7395d24bcf1STomer Tayar 7405d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 7415d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 7425d24bcf1STomer Tayar "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 7435d24bcf1STomer Tayar load_req.drv_ver_0, 7445d24bcf1STomer Tayar load_req.drv_ver_1, 7455d24bcf1STomer Tayar load_req.fw_ver, 7465d24bcf1STomer Tayar load_req.misc0, 7475d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 7485d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, 7495d24bcf1STomer Tayar LOAD_REQ_LOCK_TO), 7505d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 7515d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 7525d24bcf1STomer Tayar } 7535d24bcf1STomer Tayar 7545d24bcf1STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 7555d24bcf1STomer Tayar if (rc) { 7565d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 7575d24bcf1STomer Tayar return rc; 7585d24bcf1STomer Tayar } 7595d24bcf1STomer Tayar 7605d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 7615d24bcf1STomer Tayar "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 7625d24bcf1STomer Tayar p_out_params->load_code = mb_params.mcp_resp; 7635d24bcf1STomer Tayar 7645d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 7655d24bcf1STomer Tayar p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 7665d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, 7675d24bcf1STomer Tayar QED_MSG_SP, 7685d24bcf1STomer Tayar "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 7695d24bcf1STomer Tayar load_rsp.drv_ver_0, 7705d24bcf1STomer Tayar load_rsp.drv_ver_1, 7715d24bcf1STomer Tayar load_rsp.fw_ver, 7725d24bcf1STomer Tayar load_rsp.misc0, 7735d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 7745d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 7755d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 7765d24bcf1STomer Tayar 7775d24bcf1STomer Tayar p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 7785d24bcf1STomer Tayar p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 7795d24bcf1STomer Tayar p_out_params->exist_fw_ver = load_rsp.fw_ver; 7805d24bcf1STomer Tayar p_out_params->exist_drv_role = 7815d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 7825d24bcf1STomer Tayar p_out_params->mfw_hsi_ver = 7835d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 7845d24bcf1STomer Tayar p_out_params->drv_exists = 7855d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 7865d24bcf1STomer Tayar LOAD_RSP_FLAGS0_DRV_EXISTS; 7875d24bcf1STomer Tayar } 7885d24bcf1STomer Tayar 7895d24bcf1STomer Tayar return 0; 7905d24bcf1STomer Tayar } 7915d24bcf1STomer Tayar 7925d24bcf1STomer Tayar static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 7935d24bcf1STomer Tayar enum qed_drv_role drv_role, 7945d24bcf1STomer Tayar u8 *p_mfw_drv_role) 7955d24bcf1STomer Tayar { 7965d24bcf1STomer Tayar switch (drv_role) { 7975d24bcf1STomer Tayar case QED_DRV_ROLE_OS: 7985d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_OS; 7995d24bcf1STomer Tayar break; 8005d24bcf1STomer Tayar case QED_DRV_ROLE_KDUMP: 8015d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_KDUMP; 8025d24bcf1STomer Tayar break; 8035d24bcf1STomer Tayar default: 8045d24bcf1STomer Tayar DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 8055d24bcf1STomer Tayar return -EINVAL; 8065d24bcf1STomer Tayar } 8075d24bcf1STomer Tayar 8085d24bcf1STomer Tayar return 0; 8095d24bcf1STomer Tayar } 8105d24bcf1STomer Tayar 8115d24bcf1STomer Tayar enum qed_load_req_force { 8125d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, 8135d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_PF, 8145d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 8155d24bcf1STomer Tayar }; 8165d24bcf1STomer Tayar 8175d24bcf1STomer Tayar static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 8185d24bcf1STomer Tayar 8195d24bcf1STomer Tayar enum qed_load_req_force force_cmd, 8205d24bcf1STomer Tayar u8 *p_mfw_force_cmd) 8215d24bcf1STomer Tayar { 8225d24bcf1STomer Tayar switch (force_cmd) { 8235d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_NONE: 8245d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 8255d24bcf1STomer Tayar break; 8265d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_PF: 8275d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 8285d24bcf1STomer Tayar break; 8295d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_ALL: 8305d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 8315d24bcf1STomer Tayar break; 8325d24bcf1STomer Tayar } 8335d24bcf1STomer Tayar } 8345d24bcf1STomer Tayar 8355d24bcf1STomer Tayar int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 8365d24bcf1STomer Tayar struct qed_ptt *p_ptt, 8375d24bcf1STomer Tayar struct qed_load_req_params *p_params) 8385d24bcf1STomer Tayar { 8395d24bcf1STomer Tayar struct qed_load_req_out_params out_params; 8405d24bcf1STomer Tayar struct qed_load_req_in_params in_params; 8415d24bcf1STomer Tayar u8 mfw_drv_role, mfw_force_cmd; 8425d24bcf1STomer Tayar int rc; 8435d24bcf1STomer Tayar 8445d24bcf1STomer Tayar memset(&in_params, 0, sizeof(in_params)); 8455d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 8465d24bcf1STomer Tayar in_params.drv_ver_0 = QED_VERSION; 8475d24bcf1STomer Tayar in_params.drv_ver_1 = qed_get_config_bitmap(); 8485d24bcf1STomer Tayar in_params.fw_ver = STORM_FW_VERSION; 8495d24bcf1STomer Tayar rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 8505d24bcf1STomer Tayar if (rc) 8515d24bcf1STomer Tayar return rc; 8525d24bcf1STomer Tayar 8535d24bcf1STomer Tayar in_params.drv_role = mfw_drv_role; 8545d24bcf1STomer Tayar in_params.timeout_val = p_params->timeout_val; 8555d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 8565d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 8575d24bcf1STomer Tayar 8585d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 8595d24bcf1STomer Tayar in_params.avoid_eng_reset = p_params->avoid_eng_reset; 8605d24bcf1STomer Tayar 8615d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 8625d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 8635d24bcf1STomer Tayar if (rc) 8645d24bcf1STomer Tayar return rc; 8655d24bcf1STomer Tayar 8665d24bcf1STomer Tayar /* First handle cases where another load request should/might be sent: 8675d24bcf1STomer Tayar * - MFW expects the old interface [HSI version = 1] 8685d24bcf1STomer Tayar * - MFW responds that a force load request is required 869fe56b9e6SYuval Mintz */ 8705d24bcf1STomer Tayar if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 8715d24bcf1STomer Tayar DP_INFO(p_hwfn, 8725d24bcf1STomer Tayar "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 8735d24bcf1STomer Tayar 8745d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 8755d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 8765d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 8775d24bcf1STomer Tayar if (rc) 8785d24bcf1STomer Tayar return rc; 8795d24bcf1STomer Tayar } else if (out_params.load_code == 8805d24bcf1STomer Tayar FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 8815d24bcf1STomer Tayar if (qed_mcp_can_force_load(in_params.drv_role, 8825d24bcf1STomer Tayar out_params.exist_drv_role, 8835d24bcf1STomer Tayar p_params->override_force_load)) { 8845d24bcf1STomer Tayar DP_INFO(p_hwfn, 8855d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 8865d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 8875d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 8885d24bcf1STomer Tayar out_params.exist_drv_role, 8895d24bcf1STomer Tayar out_params.exist_fw_ver, 8905d24bcf1STomer Tayar out_params.exist_drv_ver_0, 8915d24bcf1STomer Tayar out_params.exist_drv_ver_1); 8925d24bcf1STomer Tayar 8935d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 8945d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 8955d24bcf1STomer Tayar &mfw_force_cmd); 8965d24bcf1STomer Tayar 8975d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 8985d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 8995d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 9005d24bcf1STomer Tayar &out_params); 9015d24bcf1STomer Tayar if (rc) 9025d24bcf1STomer Tayar return rc; 9035d24bcf1STomer Tayar } else { 9045d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 9055d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 9065d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 9075d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 9085d24bcf1STomer Tayar out_params.exist_drv_role, 9095d24bcf1STomer Tayar out_params.exist_fw_ver, 9105d24bcf1STomer Tayar out_params.exist_drv_ver_0, 9115d24bcf1STomer Tayar out_params.exist_drv_ver_1); 9125d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 9135d24bcf1STomer Tayar "Avoid sending a force load request to prevent disruption of active PFs\n"); 9145d24bcf1STomer Tayar 9155d24bcf1STomer Tayar qed_mcp_cancel_load_req(p_hwfn, p_ptt); 916fe56b9e6SYuval Mintz return -EBUSY; 917fe56b9e6SYuval Mintz } 9185d24bcf1STomer Tayar } 9195d24bcf1STomer Tayar 9205d24bcf1STomer Tayar /* Now handle the other types of responses. 9215d24bcf1STomer Tayar * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 9225d24bcf1STomer Tayar * expected here after the additional revised load requests were sent. 9235d24bcf1STomer Tayar */ 9245d24bcf1STomer Tayar switch (out_params.load_code) { 9255d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_ENGINE: 9265d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_PORT: 9275d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_FUNCTION: 9285d24bcf1STomer Tayar if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 9295d24bcf1STomer Tayar out_params.drv_exists) { 9305d24bcf1STomer Tayar /* The role and fw/driver version match, but the PF is 9315d24bcf1STomer Tayar * already loaded and has not been unloaded gracefully. 9325d24bcf1STomer Tayar */ 9335d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 9345d24bcf1STomer Tayar "PF is already loaded\n"); 9355d24bcf1STomer Tayar return -EINVAL; 9365d24bcf1STomer Tayar } 9375d24bcf1STomer Tayar break; 9385d24bcf1STomer Tayar default: 9395d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 9405d24bcf1STomer Tayar "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 9415d24bcf1STomer Tayar out_params.load_code); 9425d24bcf1STomer Tayar return -EBUSY; 9435d24bcf1STomer Tayar } 9445d24bcf1STomer Tayar 9455d24bcf1STomer Tayar p_params->load_code = out_params.load_code; 946fe56b9e6SYuval Mintz 947fe56b9e6SYuval Mintz return 0; 948fe56b9e6SYuval Mintz } 949fe56b9e6SYuval Mintz 9501226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 9511226337aSTomer Tayar { 9521226337aSTomer Tayar u32 wol_param, mcp_resp, mcp_param; 9531226337aSTomer Tayar 9541226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 9551226337aSTomer Tayar case QED_OV_WOL_DISABLED: 9561226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 9571226337aSTomer Tayar break; 9581226337aSTomer Tayar case QED_OV_WOL_ENABLED: 9591226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 9601226337aSTomer Tayar break; 9611226337aSTomer Tayar default: 9621226337aSTomer Tayar DP_NOTICE(p_hwfn, 9631226337aSTomer Tayar "Unknown WoL configuration %02x\n", 9641226337aSTomer Tayar p_hwfn->cdev->wol_config); 9651226337aSTomer Tayar /* Fallthrough */ 9661226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 9671226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 9681226337aSTomer Tayar } 9691226337aSTomer Tayar 9701226337aSTomer Tayar return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param, 9711226337aSTomer Tayar &mcp_resp, &mcp_param); 9721226337aSTomer Tayar } 9731226337aSTomer Tayar 9741226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 9751226337aSTomer Tayar { 9761226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 9771226337aSTomer Tayar struct mcp_mac wol_mac; 9781226337aSTomer Tayar 9791226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 9801226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 9811226337aSTomer Tayar 9821226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 9831226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 9841226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 9851226337aSTomer Tayar 9861226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 9871226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 9881226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 9891226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 9901226337aSTomer Tayar 9911226337aSTomer Tayar DP_VERBOSE(p_hwfn, 9921226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 9931226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 9941226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 9951226337aSTomer Tayar 9961226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 9971226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 9981226337aSTomer Tayar } 9991226337aSTomer Tayar 10001226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 10011226337aSTomer Tayar } 10021226337aSTomer Tayar 10030b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 10040b55e27dSYuval Mintz struct qed_ptt *p_ptt) 10050b55e27dSYuval Mintz { 10060b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 10070b55e27dSYuval Mintz PUBLIC_PATH); 10080b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 10090b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 10100b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 10110b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 10120b55e27dSYuval Mintz int i; 10130b55e27dSYuval Mintz 10140b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 10150b55e27dSYuval Mintz QED_MSG_SP, 10160b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 10170b55e27dSYuval Mintz mfw_path_offsize, path_addr); 10180b55e27dSYuval Mintz 10190b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 10200b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 10210b55e27dSYuval Mintz path_addr + 10220b55e27dSYuval Mintz offsetof(struct public_path, 10230b55e27dSYuval Mintz mcp_vf_disabled) + 10240b55e27dSYuval Mintz sizeof(u32) * i); 10250b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 10260b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 10270b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 10280b55e27dSYuval Mintz } 10290b55e27dSYuval Mintz 10300b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 10310b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 10320b55e27dSYuval Mintz } 10330b55e27dSYuval Mintz 10340b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 10350b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 10360b55e27dSYuval Mintz { 10370b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 10380b55e27dSYuval Mintz PUBLIC_FUNC); 10390b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 10400b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 10410b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 10420b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 10430b55e27dSYuval Mintz int rc; 10440b55e27dSYuval Mintz int i; 10450b55e27dSYuval Mintz 10460b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 10470b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 10480b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 10490b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 10500b55e27dSYuval Mintz 10510b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 10520b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 10532f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 10542f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 10550b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 10560b55e27dSYuval Mintz if (rc) { 10570b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 10580b55e27dSYuval Mintz return -EBUSY; 10590b55e27dSYuval Mintz } 10600b55e27dSYuval Mintz 10610b55e27dSYuval Mintz /* Clear the ACK bits */ 10620b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 10630b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 10640b55e27dSYuval Mintz func_addr + 10650b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 10660b55e27dSYuval Mintz i * sizeof(u32), 0); 10670b55e27dSYuval Mintz 10680b55e27dSYuval Mintz return rc; 10690b55e27dSYuval Mintz } 10700b55e27dSYuval Mintz 1071334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1072334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 1073334c03b5SZvi Nachmani { 1074334c03b5SZvi Nachmani u32 transceiver_state; 1075334c03b5SZvi Nachmani 1076334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 1077334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 1078334c03b5SZvi Nachmani offsetof(struct public_port, 1079334c03b5SZvi Nachmani transceiver_data)); 1080334c03b5SZvi Nachmani 1081334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 1082334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 1083334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1084334c03b5SZvi Nachmani transceiver_state, 1085334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 10861a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 1087334c03b5SZvi Nachmani 1088334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 1089351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 1090334c03b5SZvi Nachmani 1091351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1092334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1093334c03b5SZvi Nachmani else 1094334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1095334c03b5SZvi Nachmani } 1096334c03b5SZvi Nachmani 1097cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 10981a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 1099cc875c2eSYuval Mintz { 1100cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 1101a64b02d5SManish Chopra u8 max_bw, min_bw; 1102cc875c2eSYuval Mintz u32 status = 0; 1103cc875c2eSYuval Mintz 110465ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 110565ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 110665ed2ffdSMintz, Yuval 1107cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 1108cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 1109cc875c2eSYuval Mintz if (!b_reset) { 1110cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 1111cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 1112cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 1113cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1114cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1115cc875c2eSYuval Mintz status, 1116cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 11171a635e48SYuval Mintz offsetof(struct public_port, link_status))); 1118cc875c2eSYuval Mintz } else { 1119cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1120cc875c2eSYuval Mintz "Resetting link indications\n"); 112165ed2ffdSMintz, Yuval goto out; 1122cc875c2eSYuval Mintz } 1123cc875c2eSYuval Mintz 1124fc916ff2SSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) 1125cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1126fc916ff2SSudarsana Reddy Kalluru else 1127fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 1128cc875c2eSYuval Mintz 1129cc875c2eSYuval Mintz p_link->full_duplex = true; 1130cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1131cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1132cc875c2eSYuval Mintz p_link->speed = 100000; 1133cc875c2eSYuval Mintz break; 1134cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1135cc875c2eSYuval Mintz p_link->speed = 50000; 1136cc875c2eSYuval Mintz break; 1137cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1138cc875c2eSYuval Mintz p_link->speed = 40000; 1139cc875c2eSYuval Mintz break; 1140cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1141cc875c2eSYuval Mintz p_link->speed = 25000; 1142cc875c2eSYuval Mintz break; 1143cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1144cc875c2eSYuval Mintz p_link->speed = 20000; 1145cc875c2eSYuval Mintz break; 1146cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1147cc875c2eSYuval Mintz p_link->speed = 10000; 1148cc875c2eSYuval Mintz break; 1149cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1150cc875c2eSYuval Mintz p_link->full_duplex = false; 1151cc875c2eSYuval Mintz /* Fall-through */ 1152cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1153cc875c2eSYuval Mintz p_link->speed = 1000; 1154cc875c2eSYuval Mintz break; 1155cc875c2eSYuval Mintz default: 1156cc875c2eSYuval Mintz p_link->speed = 0; 1157cc875c2eSYuval Mintz } 1158cc875c2eSYuval Mintz 11594b01e519SManish Chopra if (p_link->link_up && p_link->speed) 11604b01e519SManish Chopra p_link->line_speed = p_link->speed; 11614b01e519SManish Chopra else 11624b01e519SManish Chopra p_link->line_speed = 0; 11634b01e519SManish Chopra 11644b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1165a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 11664b01e519SManish Chopra 1167a64b02d5SManish Chopra /* Max bandwidth configuration */ 11684b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1169cc875c2eSYuval Mintz 1170a64b02d5SManish Chopra /* Min bandwidth configuration */ 1171a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 11726f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 11736f437d43SMintz, Yuval p_link->min_pf_rate); 1174a64b02d5SManish Chopra 1175cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1176cc875c2eSYuval Mintz p_link->an_complete = !!(status & 1177cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1178cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 1179cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 1180cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1181cc875c2eSYuval Mintz 1182cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1183cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1184cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 1185cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1186cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1187cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 1188cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1189cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1190cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 1191cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1192cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1193cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 1194cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1195054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1196054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 1197054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 1198cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1199cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 1200cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1201cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1202cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 1203cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1204cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1205cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 1206cc875c2eSYuval Mintz 1207cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 1208cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1209cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 1210cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1211cc875c2eSYuval Mintz 1212cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1213cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1214cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1215cc875c2eSYuval Mintz break; 1216cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1217cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1218cc875c2eSYuval Mintz break; 1219cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1220cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1221cc875c2eSYuval Mintz break; 1222cc875c2eSYuval Mintz default: 1223cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 1224cc875c2eSYuval Mintz } 1225cc875c2eSYuval Mintz 1226cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1227cc875c2eSYuval Mintz 1228cc875c2eSYuval Mintz qed_link_update(p_hwfn); 122965ed2ffdSMintz, Yuval out: 123065ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1231cc875c2eSYuval Mintz } 1232cc875c2eSYuval Mintz 1233351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1234cc875c2eSYuval Mintz { 1235cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 12365529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 12372f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 1238cc875c2eSYuval Mintz int rc = 0; 12395529bad9STomer Tayar u32 cmd; 1240cc875c2eSYuval Mintz 1241cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 12422f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 1243cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1244cc875c2eSYuval Mintz if (!params->speed.autoneg) 12452f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 12462f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 12472f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 12482f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 12492f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 12502f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 1251cc875c2eSYuval Mintz 1252fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 1253fc916ff2SSudarsana Reddy Kalluru 1254cc875c2eSYuval Mintz if (b_up) { 1255cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1256cc875c2eSYuval Mintz "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 12572f67af8cSTomer Tayar phy_cfg.speed, 12582f67af8cSTomer Tayar phy_cfg.pause, 12592f67af8cSTomer Tayar phy_cfg.adv_speed, 12602f67af8cSTomer Tayar phy_cfg.loopback_mode, 12612f67af8cSTomer Tayar phy_cfg.feature_config_flags); 1262cc875c2eSYuval Mintz } else { 1263cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1264cc875c2eSYuval Mintz "Resetting link\n"); 1265cc875c2eSYuval Mintz } 1266cc875c2eSYuval Mintz 12675529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 12685529bad9STomer Tayar mb_params.cmd = cmd; 12692f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 12702f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 12715529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1272cc875c2eSYuval Mintz 1273cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 1274cc875c2eSYuval Mintz if (rc) { 1275cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1276cc875c2eSYuval Mintz return rc; 1277cc875c2eSYuval Mintz } 1278cc875c2eSYuval Mintz 127965ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 128065ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 128165ed2ffdSMintz, Yuval * an attention. 128265ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 128365ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 128465ed2ffdSMintz, Yuval */ 128565ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1286cc875c2eSYuval Mintz 1287cc875c2eSYuval Mintz return 0; 1288cc875c2eSYuval Mintz } 1289cc875c2eSYuval Mintz 12906c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 12916c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 12926c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 12936c754246SSudarsana Reddy Kalluru { 12946c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 12956c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 12966c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 12976c754246SSudarsana Reddy Kalluru u32 hsi_param; 12986c754246SSudarsana Reddy Kalluru 12996c754246SSudarsana Reddy Kalluru switch (type) { 13006c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 13016c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 13026c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 13036c754246SSudarsana Reddy Kalluru break; 13046c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 13056c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 13066c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 13076c754246SSudarsana Reddy Kalluru break; 13086c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 13096c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 13106c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 13116c754246SSudarsana Reddy Kalluru break; 13126c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 13136c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 13146c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 13156c754246SSudarsana Reddy Kalluru break; 13166c754246SSudarsana Reddy Kalluru default: 13176c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 13186c754246SSudarsana Reddy Kalluru return; 13196c754246SSudarsana Reddy Kalluru } 13206c754246SSudarsana Reddy Kalluru 13216c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 13226c754246SSudarsana Reddy Kalluru 13236c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 13246c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 13256c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 13262f67af8cSTomer Tayar mb_params.p_data_src = &stats; 13272f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 13286c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 13296c754246SSudarsana Reddy Kalluru } 13306c754246SSudarsana Reddy Kalluru 13314b01e519SManish Chopra static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 13324b01e519SManish Chopra struct public_func *p_shmem_info) 13334b01e519SManish Chopra { 13344b01e519SManish Chopra struct qed_mcp_function_info *p_info; 13354b01e519SManish Chopra 13364b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 13374b01e519SManish Chopra 13384b01e519SManish Chopra p_info->bandwidth_min = (p_shmem_info->config & 13394b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_MASK) >> 13404b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_SHIFT; 13414b01e519SManish Chopra if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 13424b01e519SManish Chopra DP_INFO(p_hwfn, 13434b01e519SManish Chopra "bandwidth minimum out of bounds [%02x]. Set to 1\n", 13444b01e519SManish Chopra p_info->bandwidth_min); 13454b01e519SManish Chopra p_info->bandwidth_min = 1; 13464b01e519SManish Chopra } 13474b01e519SManish Chopra 13484b01e519SManish Chopra p_info->bandwidth_max = (p_shmem_info->config & 13494b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_MASK) >> 13504b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_SHIFT; 13514b01e519SManish Chopra if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 13524b01e519SManish Chopra DP_INFO(p_hwfn, 13534b01e519SManish Chopra "bandwidth maximum out of bounds [%02x]. Set to 100\n", 13544b01e519SManish Chopra p_info->bandwidth_max); 13554b01e519SManish Chopra p_info->bandwidth_max = 100; 13564b01e519SManish Chopra } 13574b01e519SManish Chopra } 13584b01e519SManish Chopra 13594b01e519SManish Chopra static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 13604b01e519SManish Chopra struct qed_ptt *p_ptt, 13611a635e48SYuval Mintz struct public_func *p_data, int pfid) 13624b01e519SManish Chopra { 13634b01e519SManish Chopra u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 13644b01e519SManish Chopra PUBLIC_FUNC); 13654b01e519SManish Chopra u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 13664b01e519SManish Chopra u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 13674b01e519SManish Chopra u32 i, size; 13684b01e519SManish Chopra 13694b01e519SManish Chopra memset(p_data, 0, sizeof(*p_data)); 13704b01e519SManish Chopra 13711a635e48SYuval Mintz size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 13724b01e519SManish Chopra for (i = 0; i < size / sizeof(u32); i++) 13734b01e519SManish Chopra ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 13744b01e519SManish Chopra func_addr + (i << 2)); 13754b01e519SManish Chopra return size; 13764b01e519SManish Chopra } 13774b01e519SManish Chopra 13781a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 13794b01e519SManish Chopra { 13804b01e519SManish Chopra struct qed_mcp_function_info *p_info; 13814b01e519SManish Chopra struct public_func shmem_info; 13824b01e519SManish Chopra u32 resp = 0, param = 0; 13834b01e519SManish Chopra 13841a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 13854b01e519SManish Chopra 13864b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 13874b01e519SManish Chopra 13884b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 13894b01e519SManish Chopra 1390a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 13914b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 13924b01e519SManish Chopra 13934b01e519SManish Chopra /* Acknowledge the MFW */ 13944b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 13954b01e519SManish Chopra ¶m); 13964b01e519SManish Chopra } 13974b01e519SManish Chopra 1398cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1399cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1400cc875c2eSYuval Mintz { 1401cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 1402cc875c2eSYuval Mintz int rc = 0; 1403cc875c2eSYuval Mintz bool found = false; 1404cc875c2eSYuval Mintz u16 i; 1405cc875c2eSYuval Mintz 1406cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1407cc875c2eSYuval Mintz 1408cc875c2eSYuval Mintz /* Read Messages from MFW */ 1409cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 1410cc875c2eSYuval Mintz 1411cc875c2eSYuval Mintz /* Compare current messages to old ones */ 1412cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 1413cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1414cc875c2eSYuval Mintz continue; 1415cc875c2eSYuval Mintz 1416cc875c2eSYuval Mintz found = true; 1417cc875c2eSYuval Mintz 1418cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1419cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1420cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1421cc875c2eSYuval Mintz 1422cc875c2eSYuval Mintz switch (i) { 1423cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 1424cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1425cc875c2eSYuval Mintz break; 14260b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 14270b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 14280b55e27dSYuval Mintz break; 142939651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 143039651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 143139651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 143239651abdSSudarsana Reddy Kalluru break; 143339651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 143439651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 143539651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 143639651abdSSudarsana Reddy Kalluru break; 143739651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 143839651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 143939651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 144039651abdSSudarsana Reddy Kalluru break; 1441334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1442334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1443334c03b5SZvi Nachmani break; 14446c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 14456c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 14466c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 14476c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 14486c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 14496c754246SSudarsana Reddy Kalluru break; 14504b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 14514b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 14524b01e519SManish Chopra break; 1453cc875c2eSYuval Mintz default: 145439815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1455cc875c2eSYuval Mintz rc = -EINVAL; 1456cc875c2eSYuval Mintz } 1457cc875c2eSYuval Mintz } 1458cc875c2eSYuval Mintz 1459cc875c2eSYuval Mintz /* ACK everything */ 1460cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1461cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1462cc875c2eSYuval Mintz 1463cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 1464cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 1465cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 1466cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1467cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 1468cc875c2eSYuval Mintz (__force u32)val); 1469cc875c2eSYuval Mintz } 1470cc875c2eSYuval Mintz 1471cc875c2eSYuval Mintz if (!found) { 1472cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 1473cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 1474cc875c2eSYuval Mintz rc = -EINVAL; 1475cc875c2eSYuval Mintz } 1476cc875c2eSYuval Mintz 1477cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 1478cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1479cc875c2eSYuval Mintz 1480cc875c2eSYuval Mintz return rc; 1481cc875c2eSYuval Mintz } 1482cc875c2eSYuval Mintz 14831408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 14841408cc1fSYuval Mintz struct qed_ptt *p_ptt, 14851408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 1486fe56b9e6SYuval Mintz { 1487fe56b9e6SYuval Mintz u32 global_offsize; 1488fe56b9e6SYuval Mintz 14891408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 14901408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 14911408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 14921408cc1fSYuval Mintz 14931408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 14941408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 14951408cc1fSYuval Mintz return 0; 14961408cc1fSYuval Mintz } else { 14971408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 14981408cc1fSYuval Mintz QED_MSG_IOV, 14991408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 15001408cc1fSYuval Mintz return -EINVAL; 15011408cc1fSYuval Mintz } 15021408cc1fSYuval Mintz } 1503fe56b9e6SYuval Mintz 1504fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 15051408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 15061408cc1fSYuval Mintz mcp_info->public_base, 1507fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 15081408cc1fSYuval Mintz *p_mfw_ver = 15091408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 15101408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 15111408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 1512fe56b9e6SYuval Mintz 15131408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 15141408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 15151408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 15161408cc1fSYuval Mintz offsetof(struct public_global, 15171408cc1fSYuval Mintz running_bundle_id)); 15181408cc1fSYuval Mintz } 1519fe56b9e6SYuval Mintz 1520fe56b9e6SYuval Mintz return 0; 1521fe56b9e6SYuval Mintz } 1522fe56b9e6SYuval Mintz 15231a635e48SYuval Mintz int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) 1524cc875c2eSYuval Mintz { 1525cc875c2eSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 1526cc875c2eSYuval Mintz struct qed_ptt *p_ptt; 1527cc875c2eSYuval Mintz 15281408cc1fSYuval Mintz if (IS_VF(cdev)) 15291408cc1fSYuval Mintz return -EINVAL; 15301408cc1fSYuval Mintz 1531cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 1532cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1533cc875c2eSYuval Mintz return -EBUSY; 1534cc875c2eSYuval Mintz } 1535cc875c2eSYuval Mintz 1536cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 1537cc875c2eSYuval Mintz 1538cc875c2eSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 1539cc875c2eSYuval Mintz if (!p_ptt) 1540cc875c2eSYuval Mintz return -EBUSY; 1541cc875c2eSYuval Mintz 1542cc875c2eSYuval Mintz *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1543cc875c2eSYuval Mintz offsetof(struct public_port, media_type)); 1544cc875c2eSYuval Mintz 1545cc875c2eSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 1546cc875c2eSYuval Mintz 1547cc875c2eSYuval Mintz return 0; 1548cc875c2eSYuval Mintz } 1549cc875c2eSYuval Mintz 15506927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 15516927e826SMintz, Yuval static void 15526927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 15536927e826SMintz, Yuval enum qed_pci_personality *p_proto) 15546927e826SMintz, Yuval { 15556927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 15566927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 15576927e826SMintz, Yuval */ 15586927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 15596927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 15606927e826SMintz, Yuval else 15616927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 15626927e826SMintz, Yuval 15636927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 15646927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 15656927e826SMintz, Yuval (u32) *p_proto); 15666927e826SMintz, Yuval } 15676927e826SMintz, Yuval 15686927e826SMintz, Yuval static int 15696927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 15706927e826SMintz, Yuval struct qed_ptt *p_ptt, 15716927e826SMintz, Yuval enum qed_pci_personality *p_proto) 15726927e826SMintz, Yuval { 15736927e826SMintz, Yuval u32 resp = 0, param = 0; 15746927e826SMintz, Yuval int rc; 15756927e826SMintz, Yuval 15766927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 15776927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 15786927e826SMintz, Yuval if (rc) 15796927e826SMintz, Yuval return rc; 15806927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 15816927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 15826927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 15836927e826SMintz, Yuval resp); 15846927e826SMintz, Yuval return -EINVAL; 15856927e826SMintz, Yuval } 15866927e826SMintz, Yuval 15876927e826SMintz, Yuval switch (param) { 15886927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 15896927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 15906927e826SMintz, Yuval break; 15916927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 15926927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 15936927e826SMintz, Yuval break; 15946927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_BOTH: 15956927e826SMintz, Yuval DP_NOTICE(p_hwfn, 15966927e826SMintz, Yuval "Current day drivers don't support RoCE & iWARP. Default to RoCE-only\n"); 15976927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 15986927e826SMintz, Yuval break; 15996927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 16006927e826SMintz, Yuval default: 16016927e826SMintz, Yuval DP_NOTICE(p_hwfn, 16026927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 16036927e826SMintz, Yuval param); 16046927e826SMintz, Yuval return -EINVAL; 16056927e826SMintz, Yuval } 16066927e826SMintz, Yuval 16076927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 16086927e826SMintz, Yuval NETIF_MSG_IFUP, 16096927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 16106927e826SMintz, Yuval (u32) *p_proto, resp, param); 16116927e826SMintz, Yuval return 0; 16126927e826SMintz, Yuval } 16136927e826SMintz, Yuval 1614fe56b9e6SYuval Mintz static int 1615fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 1616fe56b9e6SYuval Mintz struct public_func *p_info, 16176927e826SMintz, Yuval struct qed_ptt *p_ptt, 1618fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 1619fe56b9e6SYuval Mintz { 1620fe56b9e6SYuval Mintz int rc = 0; 1621fe56b9e6SYuval Mintz 1622fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 1623fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 16241fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 16251fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 16261fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 16276927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 1628fe56b9e6SYuval Mintz break; 1629c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 1630c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 1631c5ac9319SYuval Mintz break; 16321e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 16331e128c81SArun Easi *p_proto = QED_PCI_FCOE; 16341e128c81SArun Easi break; 1635c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 1636c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 16376927e826SMintz, Yuval /* Fallthrough */ 1638fe56b9e6SYuval Mintz default: 1639fe56b9e6SYuval Mintz rc = -EINVAL; 1640fe56b9e6SYuval Mintz } 1641fe56b9e6SYuval Mintz 1642fe56b9e6SYuval Mintz return rc; 1643fe56b9e6SYuval Mintz } 1644fe56b9e6SYuval Mintz 1645fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 1646fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 1647fe56b9e6SYuval Mintz { 1648fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 1649fe56b9e6SYuval Mintz struct public_func shmem_info; 1650fe56b9e6SYuval Mintz 16511a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1652fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 1653fe56b9e6SYuval Mintz 1654fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 1655fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 1656fe56b9e6SYuval Mintz 16576927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 16586927e826SMintz, Yuval &info->protocol)) { 1659fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 1660fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 1661fe56b9e6SYuval Mintz return -EINVAL; 1662fe56b9e6SYuval Mintz } 1663fe56b9e6SYuval Mintz 16644b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1665fe56b9e6SYuval Mintz 1666fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 1667fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 1668fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 1669fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 1670fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 1671fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 1672fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 167314d39648SMintz, Yuval 167414d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 167514d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 1676fe56b9e6SYuval Mintz } else { 1677fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 1678fe56b9e6SYuval Mintz } 1679fe56b9e6SYuval Mintz 1680fe56b9e6SYuval Mintz info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper | 1681fe56b9e6SYuval Mintz (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32); 1682fe56b9e6SYuval Mintz info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper | 1683fe56b9e6SYuval Mintz (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32); 1684fe56b9e6SYuval Mintz 1685fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 1686fe56b9e6SYuval Mintz 16870fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 16880fefbfbaSSudarsana Kalluru 168914d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 169014d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 169114d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 169214d39648SMintz, Yuval u32 resp = 0, param = 0; 169314d39648SMintz, Yuval int rc; 169414d39648SMintz, Yuval 169514d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 169614d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 169714d39648SMintz, Yuval if (rc) 169814d39648SMintz, Yuval return rc; 169914d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 170014d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 170114d39648SMintz, Yuval } 170214d39648SMintz, Yuval 1703fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 170414d39648SMintz, Yuval "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 1705fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 1706fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 1707fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 1708fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 170914d39648SMintz, Yuval info->wwn_port, info->wwn_node, 171014d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 1711fe56b9e6SYuval Mintz 1712fe56b9e6SYuval Mintz return 0; 1713fe56b9e6SYuval Mintz } 1714fe56b9e6SYuval Mintz 1715cc875c2eSYuval Mintz struct qed_mcp_link_params 1716cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 1717cc875c2eSYuval Mintz { 1718cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1719cc875c2eSYuval Mintz return NULL; 1720cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 1721cc875c2eSYuval Mintz } 1722cc875c2eSYuval Mintz 1723cc875c2eSYuval Mintz struct qed_mcp_link_state 1724cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 1725cc875c2eSYuval Mintz { 1726cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1727cc875c2eSYuval Mintz return NULL; 1728cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 1729cc875c2eSYuval Mintz } 1730cc875c2eSYuval Mintz 1731cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 1732cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 1733cc875c2eSYuval Mintz { 1734cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1735cc875c2eSYuval Mintz return NULL; 1736cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 1737cc875c2eSYuval Mintz } 1738cc875c2eSYuval Mintz 17391a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1740fe56b9e6SYuval Mintz { 1741fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 1742fe56b9e6SYuval Mintz int rc; 1743fe56b9e6SYuval Mintz 1744fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 17451a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 1746fe56b9e6SYuval Mintz 1747fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 17488f60bafeSYuval Mintz msleep(1020); 1749fe56b9e6SYuval Mintz 1750fe56b9e6SYuval Mintz return rc; 1751fe56b9e6SYuval Mintz } 1752fe56b9e6SYuval Mintz 1753cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 17541a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 1755cee4d264SManish Chopra { 1756cee4d264SManish Chopra u32 flash_size; 1757cee4d264SManish Chopra 17581408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 17591408cc1fSYuval Mintz return -EINVAL; 17601408cc1fSYuval Mintz 1761cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 1762cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 1763cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 1764cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 1765cee4d264SManish Chopra 1766cee4d264SManish Chopra *p_flash_size = flash_size; 1767cee4d264SManish Chopra 1768cee4d264SManish Chopra return 0; 1769cee4d264SManish Chopra } 1770cee4d264SManish Chopra 17711408cc1fSYuval Mintz int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 17721408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 17731408cc1fSYuval Mintz { 17741408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 17751408cc1fSYuval Mintz int rc; 17761408cc1fSYuval Mintz 17771408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 17781408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 17791408cc1fSYuval Mintz return 0; 17801408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 17811408cc1fSYuval Mintz 17821408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 17831408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 17841408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 17851408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 17861408cc1fSYuval Mintz 17871408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 17881408cc1fSYuval Mintz &resp, &rc_param); 17891408cc1fSYuval Mintz 17901408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 17911408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 17921408cc1fSYuval Mintz rc = -EINVAL; 17931408cc1fSYuval Mintz } else { 17941408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 17951408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 17961408cc1fSYuval Mintz num, vf_id); 17971408cc1fSYuval Mintz } 17981408cc1fSYuval Mintz 17991408cc1fSYuval Mintz return rc; 18001408cc1fSYuval Mintz } 18011408cc1fSYuval Mintz 1802fe56b9e6SYuval Mintz int 1803fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 1804fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1805fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 1806fe56b9e6SYuval Mintz { 18075529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 18082f67af8cSTomer Tayar struct drv_version_stc drv_version; 18095529bad9STomer Tayar __be32 val; 18105529bad9STomer Tayar u32 i; 18115529bad9STomer Tayar int rc; 1812fe56b9e6SYuval Mintz 18132f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 18142f67af8cSTomer Tayar drv_version.version = p_ver->version; 181567a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 181667a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 18172f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 1818fe56b9e6SYuval Mintz } 1819fe56b9e6SYuval Mintz 18205529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 18215529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 18222f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 18232f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 18245529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 18255529bad9STomer Tayar if (rc) 1826fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1827fe56b9e6SYuval Mintz 18285529bad9STomer Tayar return rc; 1829fe56b9e6SYuval Mintz } 183091420b83SSudarsana Kalluru 18314102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 18324102426fSTomer Tayar { 18334102426fSTomer Tayar u32 resp = 0, param = 0; 18344102426fSTomer Tayar int rc; 18354102426fSTomer Tayar 18364102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 18374102426fSTomer Tayar ¶m); 18384102426fSTomer Tayar if (rc) 18394102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 18404102426fSTomer Tayar 18414102426fSTomer Tayar return rc; 18424102426fSTomer Tayar } 18434102426fSTomer Tayar 18444102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 18454102426fSTomer Tayar { 18464102426fSTomer Tayar u32 value, cpu_mode; 18474102426fSTomer Tayar 18484102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 18494102426fSTomer Tayar 18504102426fSTomer Tayar value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 18514102426fSTomer Tayar value &= ~MCP_REG_CPU_MODE_SOFT_HALT; 18524102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value); 18534102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 18544102426fSTomer Tayar 18554102426fSTomer Tayar return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0; 18564102426fSTomer Tayar } 18574102426fSTomer Tayar 18580fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 18590fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 18600fefbfbaSSudarsana Kalluru enum qed_ov_client client) 18610fefbfbaSSudarsana Kalluru { 18620fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 18630fefbfbaSSudarsana Kalluru u32 drv_mb_param; 18640fefbfbaSSudarsana Kalluru int rc; 18650fefbfbaSSudarsana Kalluru 18660fefbfbaSSudarsana Kalluru switch (client) { 18670fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 18680fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 18690fefbfbaSSudarsana Kalluru break; 18700fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 18710fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 18720fefbfbaSSudarsana Kalluru break; 18730fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 18740fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 18750fefbfbaSSudarsana Kalluru break; 18760fefbfbaSSudarsana Kalluru default: 18770fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 18780fefbfbaSSudarsana Kalluru return -EINVAL; 18790fefbfbaSSudarsana Kalluru } 18800fefbfbaSSudarsana Kalluru 18810fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 18820fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 18830fefbfbaSSudarsana Kalluru if (rc) 18840fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 18850fefbfbaSSudarsana Kalluru 18860fefbfbaSSudarsana Kalluru return rc; 18870fefbfbaSSudarsana Kalluru } 18880fefbfbaSSudarsana Kalluru 18890fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 18900fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 18910fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 18920fefbfbaSSudarsana Kalluru { 18930fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 18940fefbfbaSSudarsana Kalluru u32 drv_mb_param; 18950fefbfbaSSudarsana Kalluru int rc; 18960fefbfbaSSudarsana Kalluru 18970fefbfbaSSudarsana Kalluru switch (drv_state) { 18980fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 18990fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 19000fefbfbaSSudarsana Kalluru break; 19010fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 19020fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 19030fefbfbaSSudarsana Kalluru break; 19040fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 19050fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 19060fefbfbaSSudarsana Kalluru break; 19070fefbfbaSSudarsana Kalluru default: 19080fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 19090fefbfbaSSudarsana Kalluru return -EINVAL; 19100fefbfbaSSudarsana Kalluru } 19110fefbfbaSSudarsana Kalluru 19120fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 19130fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 19140fefbfbaSSudarsana Kalluru if (rc) 19150fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 19160fefbfbaSSudarsana Kalluru 19170fefbfbaSSudarsana Kalluru return rc; 19180fefbfbaSSudarsana Kalluru } 19190fefbfbaSSudarsana Kalluru 19200fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 19210fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 19220fefbfbaSSudarsana Kalluru { 19230fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 19240fefbfbaSSudarsana Kalluru u32 drv_mb_param; 19250fefbfbaSSudarsana Kalluru int rc; 19260fefbfbaSSudarsana Kalluru 19270fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 19280fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 19290fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 19300fefbfbaSSudarsana Kalluru if (rc) 19310fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 19320fefbfbaSSudarsana Kalluru 19330fefbfbaSSudarsana Kalluru return rc; 19340fefbfbaSSudarsana Kalluru } 19350fefbfbaSSudarsana Kalluru 19360fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 19370fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 19380fefbfbaSSudarsana Kalluru { 19390fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 194017991002SMintz, Yuval u32 mfw_mac[2]; 19410fefbfbaSSudarsana Kalluru int rc; 19420fefbfbaSSudarsana Kalluru 19430fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 19440fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 19450fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 19460fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 19470fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 19482f67af8cSTomer Tayar 194917991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 195017991002SMintz, Yuval * in 32-bit granularity. 195117991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 195217991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 195317991002SMintz, Yuval */ 195417991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 195517991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 195617991002SMintz, Yuval 195717991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 195817991002SMintz, Yuval mb_params.data_src_size = 8; 19590fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 19600fefbfbaSSudarsana Kalluru if (rc) 19610fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 19620fefbfbaSSudarsana Kalluru 196314d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 196414d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 196514d39648SMintz, Yuval 19660fefbfbaSSudarsana Kalluru return rc; 19670fefbfbaSSudarsana Kalluru } 19680fefbfbaSSudarsana Kalluru 19690fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 19700fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 19710fefbfbaSSudarsana Kalluru { 19720fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 19730fefbfbaSSudarsana Kalluru u32 drv_mb_param; 19740fefbfbaSSudarsana Kalluru int rc; 19750fefbfbaSSudarsana Kalluru 197614d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 197714d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 197814d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 197914d39648SMintz, Yuval return -EINVAL; 198014d39648SMintz, Yuval } 198114d39648SMintz, Yuval 19820fefbfbaSSudarsana Kalluru switch (wol) { 19830fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 19840fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 19850fefbfbaSSudarsana Kalluru break; 19860fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 19870fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 19880fefbfbaSSudarsana Kalluru break; 19890fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 19900fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 19910fefbfbaSSudarsana Kalluru break; 19920fefbfbaSSudarsana Kalluru default: 19930fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 19940fefbfbaSSudarsana Kalluru return -EINVAL; 19950fefbfbaSSudarsana Kalluru } 19960fefbfbaSSudarsana Kalluru 19970fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 19980fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 19990fefbfbaSSudarsana Kalluru if (rc) 20000fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 20010fefbfbaSSudarsana Kalluru 200214d39648SMintz, Yuval /* Store the WoL update for a future unload */ 200314d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 200414d39648SMintz, Yuval 20050fefbfbaSSudarsana Kalluru return rc; 20060fefbfbaSSudarsana Kalluru } 20070fefbfbaSSudarsana Kalluru 20080fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 20090fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 20100fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 20110fefbfbaSSudarsana Kalluru { 20120fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 20130fefbfbaSSudarsana Kalluru u32 drv_mb_param; 20140fefbfbaSSudarsana Kalluru int rc; 20150fefbfbaSSudarsana Kalluru 20160fefbfbaSSudarsana Kalluru switch (eswitch) { 20170fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 20180fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 20190fefbfbaSSudarsana Kalluru break; 20200fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 20210fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 20220fefbfbaSSudarsana Kalluru break; 20230fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 20240fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 20250fefbfbaSSudarsana Kalluru break; 20260fefbfbaSSudarsana Kalluru default: 20270fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 20280fefbfbaSSudarsana Kalluru return -EINVAL; 20290fefbfbaSSudarsana Kalluru } 20300fefbfbaSSudarsana Kalluru 20310fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 20320fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 20330fefbfbaSSudarsana Kalluru if (rc) 20340fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 20350fefbfbaSSudarsana Kalluru 20360fefbfbaSSudarsana Kalluru return rc; 20370fefbfbaSSudarsana Kalluru } 20380fefbfbaSSudarsana Kalluru 20391a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 20401a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 204191420b83SSudarsana Kalluru { 204291420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 204391420b83SSudarsana Kalluru int rc; 204491420b83SSudarsana Kalluru 204591420b83SSudarsana Kalluru switch (mode) { 204691420b83SSudarsana Kalluru case QED_LED_MODE_ON: 204791420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 204891420b83SSudarsana Kalluru break; 204991420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 205091420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 205191420b83SSudarsana Kalluru break; 205291420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 205391420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 205491420b83SSudarsana Kalluru break; 205591420b83SSudarsana Kalluru default: 205691420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 205791420b83SSudarsana Kalluru return -EINVAL; 205891420b83SSudarsana Kalluru } 205991420b83SSudarsana Kalluru 206091420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 206191420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 206291420b83SSudarsana Kalluru 206391420b83SSudarsana Kalluru return rc; 206491420b83SSudarsana Kalluru } 206503dc76caSSudarsana Reddy Kalluru 20664102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 20674102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 20684102426fSTomer Tayar { 20694102426fSTomer Tayar u32 resp = 0, param = 0; 20704102426fSTomer Tayar int rc; 20714102426fSTomer Tayar 20724102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 20734102426fSTomer Tayar mask_parities, &resp, ¶m); 20744102426fSTomer Tayar 20754102426fSTomer Tayar if (rc) { 20764102426fSTomer Tayar DP_ERR(p_hwfn, 20774102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 20784102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 20794102426fSTomer Tayar DP_ERR(p_hwfn, 20804102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 20814102426fSTomer Tayar rc = -EINVAL; 20824102426fSTomer Tayar } 20834102426fSTomer Tayar 20844102426fSTomer Tayar return rc; 20854102426fSTomer Tayar } 20864102426fSTomer Tayar 20877a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 20887a4b21b7SMintz, Yuval { 20897a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 20907a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 20917a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 20927a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 20937a4b21b7SMintz, Yuval int rc = 0; 20947a4b21b7SMintz, Yuval 20957a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 20967a4b21b7SMintz, Yuval if (!p_ptt) 20977a4b21b7SMintz, Yuval return -EBUSY; 20987a4b21b7SMintz, Yuval 20997a4b21b7SMintz, Yuval while (bytes_left > 0) { 21007a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 21017a4b21b7SMintz, Yuval 21027a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 21037a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 21047a4b21b7SMintz, Yuval addr + offset + 21057a4b21b7SMintz, Yuval (bytes_to_copy << 21067a4b21b7SMintz, Yuval DRV_MB_PARAM_NVM_LEN_SHIFT), 21077a4b21b7SMintz, Yuval &resp, &resp_param, 21087a4b21b7SMintz, Yuval &read_len, 21097a4b21b7SMintz, Yuval (u32 *)(p_buf + offset)); 21107a4b21b7SMintz, Yuval 21117a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 21127a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 21137a4b21b7SMintz, Yuval break; 21147a4b21b7SMintz, Yuval } 21157a4b21b7SMintz, Yuval 21167a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 21177a4b21b7SMintz, Yuval * isn't preemptable. Sleep a bit to prevent CPU hogging. 21187a4b21b7SMintz, Yuval */ 21197a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 21207a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 21217a4b21b7SMintz, Yuval usleep_range(1000, 2000); 21227a4b21b7SMintz, Yuval 21237a4b21b7SMintz, Yuval offset += read_len; 21247a4b21b7SMintz, Yuval bytes_left -= read_len; 21257a4b21b7SMintz, Yuval } 21267a4b21b7SMintz, Yuval 21277a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 21287a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 21297a4b21b7SMintz, Yuval 21307a4b21b7SMintz, Yuval return rc; 21317a4b21b7SMintz, Yuval } 21327a4b21b7SMintz, Yuval 213303dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 213403dc76caSSudarsana Reddy Kalluru { 213503dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 213603dc76caSSudarsana Reddy Kalluru int rc = 0; 213703dc76caSSudarsana Reddy Kalluru 213803dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 213903dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 214003dc76caSSudarsana Reddy Kalluru 214103dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 214203dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 214303dc76caSSudarsana Reddy Kalluru 214403dc76caSSudarsana Reddy Kalluru if (rc) 214503dc76caSSudarsana Reddy Kalluru return rc; 214603dc76caSSudarsana Reddy Kalluru 214703dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 214803dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 214903dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 215003dc76caSSudarsana Reddy Kalluru 215103dc76caSSudarsana Reddy Kalluru return rc; 215203dc76caSSudarsana Reddy Kalluru } 215303dc76caSSudarsana Reddy Kalluru 215403dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 215503dc76caSSudarsana Reddy Kalluru { 215603dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 215703dc76caSSudarsana Reddy Kalluru int rc = 0; 215803dc76caSSudarsana Reddy Kalluru 215903dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 216003dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 216103dc76caSSudarsana Reddy Kalluru 216203dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 216303dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 216403dc76caSSudarsana Reddy Kalluru 216503dc76caSSudarsana Reddy Kalluru if (rc) 216603dc76caSSudarsana Reddy Kalluru return rc; 216703dc76caSSudarsana Reddy Kalluru 216803dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 216903dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 217003dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 217103dc76caSSudarsana Reddy Kalluru 217203dc76caSSudarsana Reddy Kalluru return rc; 217303dc76caSSudarsana Reddy Kalluru } 21747a4b21b7SMintz, Yuval 21757a4b21b7SMintz, Yuval int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn, 21767a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 21777a4b21b7SMintz, Yuval u32 *num_images) 21787a4b21b7SMintz, Yuval { 21797a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 21807a4b21b7SMintz, Yuval int rc = 0; 21817a4b21b7SMintz, Yuval 21827a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 21837a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 21847a4b21b7SMintz, Yuval 21857a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 21867a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 21877a4b21b7SMintz, Yuval if (rc) 21887a4b21b7SMintz, Yuval return rc; 21897a4b21b7SMintz, Yuval 21907a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 21917a4b21b7SMintz, Yuval rc = -EINVAL; 21927a4b21b7SMintz, Yuval 21937a4b21b7SMintz, Yuval return rc; 21947a4b21b7SMintz, Yuval } 21957a4b21b7SMintz, Yuval 21967a4b21b7SMintz, Yuval int qed_mcp_bist_nvm_test_get_image_att(struct qed_hwfn *p_hwfn, 21977a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 21987a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 21997a4b21b7SMintz, Yuval u32 image_index) 22007a4b21b7SMintz, Yuval { 22017a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 22027a4b21b7SMintz, Yuval int rc; 22037a4b21b7SMintz, Yuval 22047a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 22057a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 22067a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 22077a4b21b7SMintz, Yuval 22087a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 22097a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 22107a4b21b7SMintz, Yuval &resp, &resp_param, 22117a4b21b7SMintz, Yuval &buf_size, 22127a4b21b7SMintz, Yuval (u32 *)p_image_att); 22137a4b21b7SMintz, Yuval if (rc) 22147a4b21b7SMintz, Yuval return rc; 22157a4b21b7SMintz, Yuval 22167a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 22177a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 22187a4b21b7SMintz, Yuval rc = -EINVAL; 22197a4b21b7SMintz, Yuval 22207a4b21b7SMintz, Yuval return rc; 22217a4b21b7SMintz, Yuval } 22222edbff8dSTomer Tayar 22239c8517c4STomer Tayar static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 22249c8517c4STomer Tayar { 22259c8517c4STomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 22269c8517c4STomer Tayar 22279c8517c4STomer Tayar switch (res_id) { 22289c8517c4STomer Tayar case QED_SB: 22299c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 22309c8517c4STomer Tayar break; 22319c8517c4STomer Tayar case QED_L2_QUEUE: 22329c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 22339c8517c4STomer Tayar break; 22349c8517c4STomer Tayar case QED_VPORT: 22359c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 22369c8517c4STomer Tayar break; 22379c8517c4STomer Tayar case QED_RSS_ENG: 22389c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 22399c8517c4STomer Tayar break; 22409c8517c4STomer Tayar case QED_PQ: 22419c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 22429c8517c4STomer Tayar break; 22439c8517c4STomer Tayar case QED_RL: 22449c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 22459c8517c4STomer Tayar break; 22469c8517c4STomer Tayar case QED_MAC: 22479c8517c4STomer Tayar case QED_VLAN: 22489c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 22499c8517c4STomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 22509c8517c4STomer Tayar break; 22519c8517c4STomer Tayar case QED_ILT: 22529c8517c4STomer Tayar mfw_res_id = RESOURCE_ILT_E; 22539c8517c4STomer Tayar break; 22549c8517c4STomer Tayar case QED_LL2_QUEUE: 22559c8517c4STomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 22569c8517c4STomer Tayar break; 22579c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 22589c8517c4STomer Tayar case QED_CMDQS_CQS: 22599c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 22609c8517c4STomer Tayar mfw_res_id = RESOURCE_CQS_E; 22619c8517c4STomer Tayar break; 22629c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 22639c8517c4STomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 22649c8517c4STomer Tayar break; 22659c8517c4STomer Tayar case QED_BDQ: 22669c8517c4STomer Tayar mfw_res_id = RESOURCE_BDQ_E; 22679c8517c4STomer Tayar break; 22689c8517c4STomer Tayar default: 22699c8517c4STomer Tayar break; 22709c8517c4STomer Tayar } 22719c8517c4STomer Tayar 22729c8517c4STomer Tayar return mfw_res_id; 22739c8517c4STomer Tayar } 22749c8517c4STomer Tayar 22759c8517c4STomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 2 22762edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 22772edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 22782edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 22792edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 22802edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 22812edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 22829c8517c4STomer Tayar 22839c8517c4STomer Tayar struct qed_resc_alloc_in_params { 22849c8517c4STomer Tayar u32 cmd; 22859c8517c4STomer Tayar enum qed_resources res_id; 22869c8517c4STomer Tayar u32 resc_max_val; 22879c8517c4STomer Tayar }; 22889c8517c4STomer Tayar 22899c8517c4STomer Tayar struct qed_resc_alloc_out_params { 22909c8517c4STomer Tayar u32 mcp_resp; 22919c8517c4STomer Tayar u32 mcp_param; 22929c8517c4STomer Tayar u32 resc_num; 22939c8517c4STomer Tayar u32 resc_start; 22949c8517c4STomer Tayar u32 vf_resc_num; 22959c8517c4STomer Tayar u32 vf_resc_start; 22969c8517c4STomer Tayar u32 flags; 22979c8517c4STomer Tayar }; 22989c8517c4STomer Tayar 22999c8517c4STomer Tayar static int 23009c8517c4STomer Tayar qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 23012edbff8dSTomer Tayar struct qed_ptt *p_ptt, 23029c8517c4STomer Tayar struct qed_resc_alloc_in_params *p_in_params, 23039c8517c4STomer Tayar struct qed_resc_alloc_out_params *p_out_params) 23042edbff8dSTomer Tayar { 23052edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 23069c8517c4STomer Tayar struct resource_info mfw_resc_info; 23072edbff8dSTomer Tayar int rc; 23082edbff8dSTomer Tayar 23099c8517c4STomer Tayar memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 2310bb480242SMintz, Yuval 23119c8517c4STomer Tayar mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 23129c8517c4STomer Tayar if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 23139c8517c4STomer Tayar DP_ERR(p_hwfn, 23149c8517c4STomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 23159c8517c4STomer Tayar p_in_params->res_id, 23169c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id)); 23179c8517c4STomer Tayar return -EINVAL; 23189c8517c4STomer Tayar } 23199c8517c4STomer Tayar 23209c8517c4STomer Tayar switch (p_in_params->cmd) { 23219c8517c4STomer Tayar case DRV_MSG_SET_RESOURCE_VALUE_MSG: 23229c8517c4STomer Tayar mfw_resc_info.size = p_in_params->resc_max_val; 23239c8517c4STomer Tayar /* Fallthrough */ 23249c8517c4STomer Tayar case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 23259c8517c4STomer Tayar break; 23269c8517c4STomer Tayar default: 23279c8517c4STomer Tayar DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 23289c8517c4STomer Tayar p_in_params->cmd); 23299c8517c4STomer Tayar return -EINVAL; 23309c8517c4STomer Tayar } 23319c8517c4STomer Tayar 23329c8517c4STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 23339c8517c4STomer Tayar mb_params.cmd = p_in_params->cmd; 23349c8517c4STomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 23359c8517c4STomer Tayar mb_params.p_data_src = &mfw_resc_info; 23369c8517c4STomer Tayar mb_params.data_src_size = sizeof(mfw_resc_info); 23379c8517c4STomer Tayar mb_params.p_data_dst = mb_params.p_data_src; 23389c8517c4STomer Tayar mb_params.data_dst_size = mb_params.data_src_size; 23399c8517c4STomer Tayar 23409c8517c4STomer Tayar DP_VERBOSE(p_hwfn, 23419c8517c4STomer Tayar QED_MSG_SP, 23429c8517c4STomer Tayar "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 23439c8517c4STomer Tayar p_in_params->cmd, 23449c8517c4STomer Tayar p_in_params->res_id, 23459c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id), 23469c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 23479c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 23489c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 23499c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 23509c8517c4STomer Tayar p_in_params->resc_max_val); 23519c8517c4STomer Tayar 23522edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 23532edbff8dSTomer Tayar if (rc) 23542edbff8dSTomer Tayar return rc; 23552edbff8dSTomer Tayar 23569c8517c4STomer Tayar p_out_params->mcp_resp = mb_params.mcp_resp; 23579c8517c4STomer Tayar p_out_params->mcp_param = mb_params.mcp_param; 23589c8517c4STomer Tayar p_out_params->resc_num = mfw_resc_info.size; 23599c8517c4STomer Tayar p_out_params->resc_start = mfw_resc_info.offset; 23609c8517c4STomer Tayar p_out_params->vf_resc_num = mfw_resc_info.vf_size; 23619c8517c4STomer Tayar p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 23629c8517c4STomer Tayar p_out_params->flags = mfw_resc_info.flags; 23632edbff8dSTomer Tayar 23642edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 23652edbff8dSTomer Tayar QED_MSG_SP, 23669c8517c4STomer Tayar "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 23679c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 23689c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 23699c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 23709c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 23719c8517c4STomer Tayar p_out_params->resc_num, 23729c8517c4STomer Tayar p_out_params->resc_start, 23739c8517c4STomer Tayar p_out_params->vf_resc_num, 23749c8517c4STomer Tayar p_out_params->vf_resc_start, p_out_params->flags); 23759c8517c4STomer Tayar 23769c8517c4STomer Tayar return 0; 23779c8517c4STomer Tayar } 23789c8517c4STomer Tayar 23799c8517c4STomer Tayar int 23809c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 23819c8517c4STomer Tayar struct qed_ptt *p_ptt, 23829c8517c4STomer Tayar enum qed_resources res_id, 23839c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 23849c8517c4STomer Tayar { 23859c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 23869c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 23879c8517c4STomer Tayar int rc; 23889c8517c4STomer Tayar 23899c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 23909c8517c4STomer Tayar in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 23919c8517c4STomer Tayar in_params.res_id = res_id; 23929c8517c4STomer Tayar in_params.resc_max_val = resc_max_val; 23939c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 23949c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 23959c8517c4STomer Tayar &out_params); 23969c8517c4STomer Tayar if (rc) 23979c8517c4STomer Tayar return rc; 23989c8517c4STomer Tayar 23999c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 24009c8517c4STomer Tayar 24019c8517c4STomer Tayar return 0; 24029c8517c4STomer Tayar } 24039c8517c4STomer Tayar 24049c8517c4STomer Tayar int 24059c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 24069c8517c4STomer Tayar struct qed_ptt *p_ptt, 24079c8517c4STomer Tayar enum qed_resources res_id, 24089c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 24099c8517c4STomer Tayar { 24109c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 24119c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 24129c8517c4STomer Tayar int rc; 24139c8517c4STomer Tayar 24149c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 24159c8517c4STomer Tayar in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 24169c8517c4STomer Tayar in_params.res_id = res_id; 24179c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 24189c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 24199c8517c4STomer Tayar &out_params); 24209c8517c4STomer Tayar if (rc) 24219c8517c4STomer Tayar return rc; 24229c8517c4STomer Tayar 24239c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 24249c8517c4STomer Tayar 24259c8517c4STomer Tayar if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 24269c8517c4STomer Tayar *p_resc_num = out_params.resc_num; 24279c8517c4STomer Tayar *p_resc_start = out_params.resc_start; 24289c8517c4STomer Tayar } 24292edbff8dSTomer Tayar 24302edbff8dSTomer Tayar return 0; 24312edbff8dSTomer Tayar } 243218a69e36SMintz, Yuval 243318a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 243418a69e36SMintz, Yuval { 243518a69e36SMintz, Yuval u32 mcp_resp, mcp_param; 243618a69e36SMintz, Yuval 243718a69e36SMintz, Yuval return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 243818a69e36SMintz, Yuval &mcp_resp, &mcp_param); 243918a69e36SMintz, Yuval } 244095691c9cSTomer Tayar 244195691c9cSTomer Tayar static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 244295691c9cSTomer Tayar struct qed_ptt *p_ptt, 244395691c9cSTomer Tayar u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 244495691c9cSTomer Tayar { 244595691c9cSTomer Tayar int rc; 244695691c9cSTomer Tayar 244795691c9cSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 244895691c9cSTomer Tayar p_mcp_resp, p_mcp_param); 244995691c9cSTomer Tayar if (rc) 245095691c9cSTomer Tayar return rc; 245195691c9cSTomer Tayar 245295691c9cSTomer Tayar if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 245395691c9cSTomer Tayar DP_INFO(p_hwfn, 245495691c9cSTomer Tayar "The resource command is unsupported by the MFW\n"); 245595691c9cSTomer Tayar return -EINVAL; 245695691c9cSTomer Tayar } 245795691c9cSTomer Tayar 245895691c9cSTomer Tayar if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 245995691c9cSTomer Tayar u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 246095691c9cSTomer Tayar 246195691c9cSTomer Tayar DP_NOTICE(p_hwfn, 246295691c9cSTomer Tayar "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 246395691c9cSTomer Tayar param, opcode); 246495691c9cSTomer Tayar return -EINVAL; 246595691c9cSTomer Tayar } 246695691c9cSTomer Tayar 246795691c9cSTomer Tayar return rc; 246895691c9cSTomer Tayar } 246995691c9cSTomer Tayar 247095691c9cSTomer Tayar int 247195691c9cSTomer Tayar __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 247295691c9cSTomer Tayar struct qed_ptt *p_ptt, 247395691c9cSTomer Tayar struct qed_resc_lock_params *p_params) 247495691c9cSTomer Tayar { 247595691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 247695691c9cSTomer Tayar u8 opcode; 247795691c9cSTomer Tayar int rc; 247895691c9cSTomer Tayar 247995691c9cSTomer Tayar switch (p_params->timeout) { 248095691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_DEFAULT: 248195691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ; 248295691c9cSTomer Tayar p_params->timeout = 0; 248395691c9cSTomer Tayar break; 248495691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_NONE: 248595691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_WO_AGING; 248695691c9cSTomer Tayar p_params->timeout = 0; 248795691c9cSTomer Tayar break; 248895691c9cSTomer Tayar default: 248995691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_W_AGING; 249095691c9cSTomer Tayar break; 249195691c9cSTomer Tayar } 249295691c9cSTomer Tayar 249395691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 249495691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 249595691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 249695691c9cSTomer Tayar 249795691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 249895691c9cSTomer Tayar QED_MSG_SP, 249995691c9cSTomer Tayar "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 250095691c9cSTomer Tayar param, p_params->timeout, opcode, p_params->resource); 250195691c9cSTomer Tayar 250295691c9cSTomer Tayar /* Attempt to acquire the resource */ 250395691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 250495691c9cSTomer Tayar if (rc) 250595691c9cSTomer Tayar return rc; 250695691c9cSTomer Tayar 250795691c9cSTomer Tayar /* Analyze the response */ 250895691c9cSTomer Tayar p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 250995691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 251095691c9cSTomer Tayar 251195691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 251295691c9cSTomer Tayar QED_MSG_SP, 251395691c9cSTomer Tayar "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 251495691c9cSTomer Tayar mcp_param, opcode, p_params->owner); 251595691c9cSTomer Tayar 251695691c9cSTomer Tayar switch (opcode) { 251795691c9cSTomer Tayar case RESOURCE_OPCODE_GNT: 251895691c9cSTomer Tayar p_params->b_granted = true; 251995691c9cSTomer Tayar break; 252095691c9cSTomer Tayar case RESOURCE_OPCODE_BUSY: 252195691c9cSTomer Tayar p_params->b_granted = false; 252295691c9cSTomer Tayar break; 252395691c9cSTomer Tayar default: 252495691c9cSTomer Tayar DP_NOTICE(p_hwfn, 252595691c9cSTomer Tayar "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 252695691c9cSTomer Tayar mcp_param, opcode); 252795691c9cSTomer Tayar return -EINVAL; 252895691c9cSTomer Tayar } 252995691c9cSTomer Tayar 253095691c9cSTomer Tayar return 0; 253195691c9cSTomer Tayar } 253295691c9cSTomer Tayar 253395691c9cSTomer Tayar int 253495691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 253595691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 253695691c9cSTomer Tayar { 253795691c9cSTomer Tayar u32 retry_cnt = 0; 253895691c9cSTomer Tayar int rc; 253995691c9cSTomer Tayar 254095691c9cSTomer Tayar do { 254195691c9cSTomer Tayar /* No need for an interval before the first iteration */ 254295691c9cSTomer Tayar if (retry_cnt) { 254395691c9cSTomer Tayar if (p_params->sleep_b4_retry) { 254495691c9cSTomer Tayar u16 retry_interval_in_ms = 254595691c9cSTomer Tayar DIV_ROUND_UP(p_params->retry_interval, 254695691c9cSTomer Tayar 1000); 254795691c9cSTomer Tayar 254895691c9cSTomer Tayar msleep(retry_interval_in_ms); 254995691c9cSTomer Tayar } else { 255095691c9cSTomer Tayar udelay(p_params->retry_interval); 255195691c9cSTomer Tayar } 255295691c9cSTomer Tayar } 255395691c9cSTomer Tayar 255495691c9cSTomer Tayar rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 255595691c9cSTomer Tayar if (rc) 255695691c9cSTomer Tayar return rc; 255795691c9cSTomer Tayar 255895691c9cSTomer Tayar if (p_params->b_granted) 255995691c9cSTomer Tayar break; 256095691c9cSTomer Tayar } while (retry_cnt++ < p_params->retry_num); 256195691c9cSTomer Tayar 256295691c9cSTomer Tayar return 0; 256395691c9cSTomer Tayar } 256495691c9cSTomer Tayar 256595691c9cSTomer Tayar int 256695691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 256795691c9cSTomer Tayar struct qed_ptt *p_ptt, 256895691c9cSTomer Tayar struct qed_resc_unlock_params *p_params) 256995691c9cSTomer Tayar { 257095691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 257195691c9cSTomer Tayar u8 opcode; 257295691c9cSTomer Tayar int rc; 257395691c9cSTomer Tayar 257495691c9cSTomer Tayar opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 257595691c9cSTomer Tayar : RESOURCE_OPCODE_RELEASE; 257695691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 257795691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 257895691c9cSTomer Tayar 257995691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 258095691c9cSTomer Tayar "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 258195691c9cSTomer Tayar param, opcode, p_params->resource); 258295691c9cSTomer Tayar 258395691c9cSTomer Tayar /* Attempt to release the resource */ 258495691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 258595691c9cSTomer Tayar if (rc) 258695691c9cSTomer Tayar return rc; 258795691c9cSTomer Tayar 258895691c9cSTomer Tayar /* Analyze the response */ 258995691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 259095691c9cSTomer Tayar 259195691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 259295691c9cSTomer Tayar "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 259395691c9cSTomer Tayar mcp_param, opcode); 259495691c9cSTomer Tayar 259595691c9cSTomer Tayar switch (opcode) { 259695691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED_PREVIOUS: 259795691c9cSTomer Tayar DP_INFO(p_hwfn, 259895691c9cSTomer Tayar "Resource unlock request for an already released resource [%d]\n", 259995691c9cSTomer Tayar p_params->resource); 260095691c9cSTomer Tayar /* Fallthrough */ 260195691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED: 260295691c9cSTomer Tayar p_params->b_released = true; 260395691c9cSTomer Tayar break; 260495691c9cSTomer Tayar case RESOURCE_OPCODE_WRONG_OWNER: 260595691c9cSTomer Tayar p_params->b_released = false; 260695691c9cSTomer Tayar break; 260795691c9cSTomer Tayar default: 260895691c9cSTomer Tayar DP_NOTICE(p_hwfn, 260995691c9cSTomer Tayar "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 261095691c9cSTomer Tayar mcp_param, opcode); 261195691c9cSTomer Tayar return -EINVAL; 261295691c9cSTomer Tayar } 261395691c9cSTomer Tayar 261495691c9cSTomer Tayar return 0; 261595691c9cSTomer Tayar } 2616