1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/types.h> 10fe56b9e6SYuval Mintz #include <asm/byteorder.h> 11fe56b9e6SYuval Mintz #include <linux/delay.h> 12fe56b9e6SYuval Mintz #include <linux/errno.h> 13fe56b9e6SYuval Mintz #include <linux/kernel.h> 14fe56b9e6SYuval Mintz #include <linux/mutex.h> 15fe56b9e6SYuval Mintz #include <linux/slab.h> 16fe56b9e6SYuval Mintz #include <linux/string.h> 17fe56b9e6SYuval Mintz #include "qed.h" 18fe56b9e6SYuval Mintz #include "qed_hsi.h" 19fe56b9e6SYuval Mintz #include "qed_hw.h" 20fe56b9e6SYuval Mintz #include "qed_mcp.h" 21fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 22fe56b9e6SYuval Mintz #define CHIP_MCP_RESP_ITER_US 10 23fe56b9e6SYuval Mintz 24fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 25fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 26fe56b9e6SYuval Mintz 27fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 28fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 29fe56b9e6SYuval Mintz _val) 30fe56b9e6SYuval Mintz 31fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 32fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 33fe56b9e6SYuval Mintz 34fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 35fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 36fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 37fe56b9e6SYuval Mintz 38fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 39fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 40fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 41fe56b9e6SYuval Mintz 42fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 43fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 44fe56b9e6SYuval Mintz 45fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 46fe56b9e6SYuval Mintz 47fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 48fe56b9e6SYuval Mintz { 49fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 50fe56b9e6SYuval Mintz return false; 51fe56b9e6SYuval Mintz return true; 52fe56b9e6SYuval Mintz } 53fe56b9e6SYuval Mintz 54fe56b9e6SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, 55fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 56fe56b9e6SYuval Mintz { 57fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 58fe56b9e6SYuval Mintz PUBLIC_PORT); 59fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 62fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 63fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 64fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 65fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 66fe56b9e6SYuval Mintz } 67fe56b9e6SYuval Mintz 68fe56b9e6SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, 69fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 70fe56b9e6SYuval Mintz { 71fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 72fe56b9e6SYuval Mintz u32 tmp, i; 73fe56b9e6SYuval Mintz 74fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 75fe56b9e6SYuval Mintz return; 76fe56b9e6SYuval Mintz 77fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 78fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 79fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 80fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 81fe56b9e6SYuval Mintz 82fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 83fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 84fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 85fe56b9e6SYuval Mintz } 86fe56b9e6SYuval Mintz } 87fe56b9e6SYuval Mintz 88fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 89fe56b9e6SYuval Mintz { 90fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 91fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 92fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 93fe56b9e6SYuval Mintz } 94fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 95fe56b9e6SYuval Mintz 96fe56b9e6SYuval Mintz return 0; 97fe56b9e6SYuval Mintz } 98fe56b9e6SYuval Mintz 99fe56b9e6SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, 100fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 101fe56b9e6SYuval Mintz { 102fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 103fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 104fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 105fe56b9e6SYuval Mintz 106fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 107fe56b9e6SYuval Mintz if (!p_info->public_base) 108fe56b9e6SYuval Mintz return 0; 109fe56b9e6SYuval Mintz 110fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 111fe56b9e6SYuval Mintz 112fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 113fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 114fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 115fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 116fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 117fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 118fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 119fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 120fe56b9e6SYuval Mintz 121fe56b9e6SYuval Mintz /* Set the MFW MB address */ 122fe56b9e6SYuval Mintz mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 123fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 124fe56b9e6SYuval Mintz PUBLIC_MFW_MB)); 125fe56b9e6SYuval Mintz p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 126fe56b9e6SYuval Mintz p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr); 127fe56b9e6SYuval Mintz 128fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 129fe56b9e6SYuval Mintz * the first command 130fe56b9e6SYuval Mintz */ 131fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 132fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 133fe56b9e6SYuval Mintz 134fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 135fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 136fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 137fe56b9e6SYuval Mintz 138fe56b9e6SYuval Mintz p_info->mcp_hist = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 139fe56b9e6SYuval Mintz 140fe56b9e6SYuval Mintz return 0; 141fe56b9e6SYuval Mintz } 142fe56b9e6SYuval Mintz 143fe56b9e6SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, 144fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 145fe56b9e6SYuval Mintz { 146fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 147fe56b9e6SYuval Mintz u32 size; 148fe56b9e6SYuval Mintz 149fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 150fe56b9e6SYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_ATOMIC); 151fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 152fe56b9e6SYuval Mintz goto err; 153fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 154fe56b9e6SYuval Mintz 155fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 156fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 157fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 158fe56b9e6SYuval Mintz * the MCP is not initialized 159fe56b9e6SYuval Mintz */ 160fe56b9e6SYuval Mintz return 0; 161fe56b9e6SYuval Mintz } 162fe56b9e6SYuval Mintz 163fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 164fe56b9e6SYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_ATOMIC); 165fe56b9e6SYuval Mintz p_info->mfw_mb_shadow = 166fe56b9e6SYuval Mintz kzalloc(sizeof(u32) * MFW_DRV_MSG_MAX_DWORDS( 167fe56b9e6SYuval Mintz p_info->mfw_mb_length), GFP_ATOMIC); 168fe56b9e6SYuval Mintz if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr) 169fe56b9e6SYuval Mintz goto err; 170fe56b9e6SYuval Mintz 171fe56b9e6SYuval Mintz /* Initialize the MFW mutex */ 172fe56b9e6SYuval Mintz mutex_init(&p_info->mutex); 173fe56b9e6SYuval Mintz 174fe56b9e6SYuval Mintz return 0; 175fe56b9e6SYuval Mintz 176fe56b9e6SYuval Mintz err: 177fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to allocate mcp memory\n"); 178fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 179fe56b9e6SYuval Mintz return -ENOMEM; 180fe56b9e6SYuval Mintz } 181fe56b9e6SYuval Mintz 182fe56b9e6SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, 183fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 184fe56b9e6SYuval Mintz { 185fe56b9e6SYuval Mintz u32 seq = ++p_hwfn->mcp_info->drv_mb_seq; 186fe56b9e6SYuval Mintz u8 delay = CHIP_MCP_RESP_ITER_US; 187fe56b9e6SYuval Mintz u32 org_mcp_reset_seq, cnt = 0; 188fe56b9e6SYuval Mintz int rc = 0; 189fe56b9e6SYuval Mintz 190fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 191fe56b9e6SYuval Mintz org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 192fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, 193fe56b9e6SYuval Mintz (DRV_MSG_CODE_MCP_RESET | seq)); 194fe56b9e6SYuval Mintz 195fe56b9e6SYuval Mintz do { 196fe56b9e6SYuval Mintz /* Wait for MFW response */ 197fe56b9e6SYuval Mintz udelay(delay); 198fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 199fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 200fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 201fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 202fe56b9e6SYuval Mintz 203fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 204fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 205fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 206fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 207fe56b9e6SYuval Mintz } else { 208fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 209fe56b9e6SYuval Mintz rc = -EAGAIN; 210fe56b9e6SYuval Mintz } 211fe56b9e6SYuval Mintz 212fe56b9e6SYuval Mintz return rc; 213fe56b9e6SYuval Mintz } 214fe56b9e6SYuval Mintz 215fe56b9e6SYuval Mintz static int qed_do_mcp_cmd(struct qed_hwfn *p_hwfn, 216fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 217fe56b9e6SYuval Mintz u32 cmd, 218fe56b9e6SYuval Mintz u32 param, 219fe56b9e6SYuval Mintz u32 *o_mcp_resp, 220fe56b9e6SYuval Mintz u32 *o_mcp_param) 221fe56b9e6SYuval Mintz { 222fe56b9e6SYuval Mintz u8 delay = CHIP_MCP_RESP_ITER_US; 223fe56b9e6SYuval Mintz u32 seq, cnt = 1, actual_mb_seq; 224fe56b9e6SYuval Mintz int rc = 0; 225fe56b9e6SYuval Mintz 226fe56b9e6SYuval Mintz /* Get actual driver mailbox sequence */ 227fe56b9e6SYuval Mintz actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 228fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 229fe56b9e6SYuval Mintz 230fe56b9e6SYuval Mintz /* Use MCP history register to check if MCP reset occurred between 231fe56b9e6SYuval Mintz * init time and now. 232fe56b9e6SYuval Mintz */ 233fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->mcp_hist != 234fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 235fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Rereading MCP offsets\n"); 236fe56b9e6SYuval Mintz qed_load_mcp_offsets(p_hwfn, p_ptt); 237fe56b9e6SYuval Mintz qed_mcp_cmd_port_init(p_hwfn, p_ptt); 238fe56b9e6SYuval Mintz } 239fe56b9e6SYuval Mintz seq = ++p_hwfn->mcp_info->drv_mb_seq; 240fe56b9e6SYuval Mintz 241fe56b9e6SYuval Mintz /* Set drv param */ 242fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param); 243fe56b9e6SYuval Mintz 244fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 245fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq)); 246fe56b9e6SYuval Mintz 247fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 248fe56b9e6SYuval Mintz "wrote command (%x) to MFW MB param 0x%08x\n", 249fe56b9e6SYuval Mintz (cmd | seq), param); 250fe56b9e6SYuval Mintz 251fe56b9e6SYuval Mintz do { 252fe56b9e6SYuval Mintz /* Wait for MFW response */ 253fe56b9e6SYuval Mintz udelay(delay); 254fe56b9e6SYuval Mintz *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 255fe56b9e6SYuval Mintz 256fe56b9e6SYuval Mintz /* Give the FW up to 5 second (500*10ms) */ 257fe56b9e6SYuval Mintz } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) && 258fe56b9e6SYuval Mintz (cnt++ < QED_DRV_MB_MAX_RETRIES)); 259fe56b9e6SYuval Mintz 260fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 261fe56b9e6SYuval Mintz "[after %d ms] read (%x) seq is (%x) from FW MB\n", 262fe56b9e6SYuval Mintz cnt * delay, *o_mcp_resp, seq); 263fe56b9e6SYuval Mintz 264fe56b9e6SYuval Mintz /* Is this a reply to our command? */ 265fe56b9e6SYuval Mintz if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) { 266fe56b9e6SYuval Mintz *o_mcp_resp &= FW_MSG_CODE_MASK; 267fe56b9e6SYuval Mintz /* Get the MCP param */ 268fe56b9e6SYuval Mintz *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 269fe56b9e6SYuval Mintz } else { 270fe56b9e6SYuval Mintz /* FW BUG! */ 271fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MFW failed to respond!\n"); 272fe56b9e6SYuval Mintz *o_mcp_resp = 0; 273fe56b9e6SYuval Mintz rc = -EAGAIN; 274fe56b9e6SYuval Mintz } 275fe56b9e6SYuval Mintz return rc; 276fe56b9e6SYuval Mintz } 277fe56b9e6SYuval Mintz 278fe56b9e6SYuval Mintz int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 279fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 280fe56b9e6SYuval Mintz u32 cmd, 281fe56b9e6SYuval Mintz u32 param, 282fe56b9e6SYuval Mintz u32 *o_mcp_resp, 283fe56b9e6SYuval Mintz u32 *o_mcp_param) 284fe56b9e6SYuval Mintz { 285fe56b9e6SYuval Mintz int rc = 0; 286fe56b9e6SYuval Mintz 287fe56b9e6SYuval Mintz /* MCP not initialized */ 288fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 289fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized !\n"); 290fe56b9e6SYuval Mintz return -EBUSY; 291fe56b9e6SYuval Mintz } 292fe56b9e6SYuval Mintz 293fe56b9e6SYuval Mintz /* Lock Mutex to ensure only single thread is 294fe56b9e6SYuval Mintz * accessing the MCP at one time 295fe56b9e6SYuval Mintz */ 296fe56b9e6SYuval Mintz mutex_lock(&p_hwfn->mcp_info->mutex); 297fe56b9e6SYuval Mintz rc = qed_do_mcp_cmd(p_hwfn, p_ptt, cmd, param, 298fe56b9e6SYuval Mintz o_mcp_resp, o_mcp_param); 299fe56b9e6SYuval Mintz /* Release Mutex */ 300fe56b9e6SYuval Mintz mutex_unlock(&p_hwfn->mcp_info->mutex); 301fe56b9e6SYuval Mintz 302fe56b9e6SYuval Mintz return rc; 303fe56b9e6SYuval Mintz } 304fe56b9e6SYuval Mintz 305fe56b9e6SYuval Mintz static void qed_mcp_set_drv_ver(struct qed_dev *cdev, 306fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn, 307fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 308fe56b9e6SYuval Mintz { 309fe56b9e6SYuval Mintz u32 i; 310fe56b9e6SYuval Mintz 311fe56b9e6SYuval Mintz /* Copy version string to MCP */ 312fe56b9e6SYuval Mintz for (i = 0; i < MCP_DRV_VER_STR_SIZE_DWORD; i++) 313fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, union_data.ver_str[i], 314fe56b9e6SYuval Mintz *(u32 *)&cdev->ver_str[i * sizeof(u32)]); 315fe56b9e6SYuval Mintz } 316fe56b9e6SYuval Mintz 317fe56b9e6SYuval Mintz int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 318fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 319fe56b9e6SYuval Mintz u32 *p_load_code) 320fe56b9e6SYuval Mintz { 321fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 322fe56b9e6SYuval Mintz u32 param; 323fe56b9e6SYuval Mintz int rc; 324fe56b9e6SYuval Mintz 325fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 326fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized !\n"); 327fe56b9e6SYuval Mintz return -EBUSY; 328fe56b9e6SYuval Mintz } 329fe56b9e6SYuval Mintz 330fe56b9e6SYuval Mintz /* Save driver's version to shmem */ 331fe56b9e6SYuval Mintz qed_mcp_set_drv_ver(cdev, p_hwfn, p_ptt); 332fe56b9e6SYuval Mintz 333fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "fw_seq 0x%08x, drv_pulse 0x%x\n", 334fe56b9e6SYuval Mintz p_hwfn->mcp_info->drv_mb_seq, 335fe56b9e6SYuval Mintz p_hwfn->mcp_info->drv_pulse_seq); 336fe56b9e6SYuval Mintz 337fe56b9e6SYuval Mintz /* Load Request */ 338fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_REQ, 339fe56b9e6SYuval Mintz (PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT | 340fe56b9e6SYuval Mintz cdev->drv_type), 341fe56b9e6SYuval Mintz p_load_code, ¶m); 342fe56b9e6SYuval Mintz 343fe56b9e6SYuval Mintz /* if mcp fails to respond we must abort */ 344fe56b9e6SYuval Mintz if (rc) { 345fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 346fe56b9e6SYuval Mintz return rc; 347fe56b9e6SYuval Mintz } 348fe56b9e6SYuval Mintz 349fe56b9e6SYuval Mintz /* If MFW refused (e.g. other port is in diagnostic mode) we 350fe56b9e6SYuval Mintz * must abort. This can happen in the following cases: 351fe56b9e6SYuval Mintz * - Other port is in diagnostic mode 352fe56b9e6SYuval Mintz * - Previously loaded function on the engine is not compliant with 353fe56b9e6SYuval Mintz * the requester. 354fe56b9e6SYuval Mintz * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION. 355fe56b9e6SYuval Mintz * - 356fe56b9e6SYuval Mintz */ 357fe56b9e6SYuval Mintz if (!(*p_load_code) || 358fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) || 359fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) || 360fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) { 361fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP refused load request, aborting\n"); 362fe56b9e6SYuval Mintz return -EBUSY; 363fe56b9e6SYuval Mintz } 364fe56b9e6SYuval Mintz 365fe56b9e6SYuval Mintz return 0; 366fe56b9e6SYuval Mintz } 367fe56b9e6SYuval Mintz 368cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 369cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 370cc875c2eSYuval Mintz bool b_reset) 371cc875c2eSYuval Mintz { 372cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 373cc875c2eSYuval Mintz u32 status = 0; 374cc875c2eSYuval Mintz 375cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 376cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 377cc875c2eSYuval Mintz if (!b_reset) { 378cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 379cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 380cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 381cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 382cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 383cc875c2eSYuval Mintz status, 384cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 385cc875c2eSYuval Mintz offsetof(struct public_port, 386cc875c2eSYuval Mintz link_status))); 387cc875c2eSYuval Mintz } else { 388cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 389cc875c2eSYuval Mintz "Resetting link indications\n"); 390cc875c2eSYuval Mintz return; 391cc875c2eSYuval Mintz } 392cc875c2eSYuval Mintz 393cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 394cc875c2eSYuval Mintz 395cc875c2eSYuval Mintz p_link->full_duplex = true; 396cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 397cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 398cc875c2eSYuval Mintz p_link->speed = 100000; 399cc875c2eSYuval Mintz break; 400cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 401cc875c2eSYuval Mintz p_link->speed = 50000; 402cc875c2eSYuval Mintz break; 403cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 404cc875c2eSYuval Mintz p_link->speed = 40000; 405cc875c2eSYuval Mintz break; 406cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 407cc875c2eSYuval Mintz p_link->speed = 25000; 408cc875c2eSYuval Mintz break; 409cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 410cc875c2eSYuval Mintz p_link->speed = 20000; 411cc875c2eSYuval Mintz break; 412cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 413cc875c2eSYuval Mintz p_link->speed = 10000; 414cc875c2eSYuval Mintz break; 415cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 416cc875c2eSYuval Mintz p_link->full_duplex = false; 417cc875c2eSYuval Mintz /* Fall-through */ 418cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 419cc875c2eSYuval Mintz p_link->speed = 1000; 420cc875c2eSYuval Mintz break; 421cc875c2eSYuval Mintz default: 422cc875c2eSYuval Mintz p_link->speed = 0; 423cc875c2eSYuval Mintz } 424cc875c2eSYuval Mintz 425cc875c2eSYuval Mintz /* Correct speed according to bandwidth allocation */ 426cc875c2eSYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_max && p_link->speed) { 427cc875c2eSYuval Mintz p_link->speed = p_link->speed * 428cc875c2eSYuval Mintz p_hwfn->mcp_info->func_info.bandwidth_max / 429cc875c2eSYuval Mintz 100; 430cc875c2eSYuval Mintz qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 431cc875c2eSYuval Mintz p_link->speed); 432cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 433cc875c2eSYuval Mintz "Configured MAX bandwidth to be %08x Mb/sec\n", 434cc875c2eSYuval Mintz p_link->speed); 435cc875c2eSYuval Mintz } 436cc875c2eSYuval Mintz 437cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 438cc875c2eSYuval Mintz p_link->an_complete = !!(status & 439cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 440cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 441cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 442cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 443cc875c2eSYuval Mintz 444cc875c2eSYuval Mintz p_link->partner_adv_speed |= 445cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 446cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 447cc875c2eSYuval Mintz p_link->partner_adv_speed |= 448cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 449cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 450cc875c2eSYuval Mintz p_link->partner_adv_speed |= 451cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 452cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 453cc875c2eSYuval Mintz p_link->partner_adv_speed |= 454cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 455cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 456cc875c2eSYuval Mintz p_link->partner_adv_speed |= 457cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 458cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 459cc875c2eSYuval Mintz p_link->partner_adv_speed |= 460cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 461cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 462cc875c2eSYuval Mintz p_link->partner_adv_speed |= 463cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 464cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 465cc875c2eSYuval Mintz 466cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 467cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 468cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 469cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 470cc875c2eSYuval Mintz 471cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 472cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 473cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 474cc875c2eSYuval Mintz break; 475cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 476cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 477cc875c2eSYuval Mintz break; 478cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 479cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 480cc875c2eSYuval Mintz break; 481cc875c2eSYuval Mintz default: 482cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 483cc875c2eSYuval Mintz } 484cc875c2eSYuval Mintz 485cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 486cc875c2eSYuval Mintz 487cc875c2eSYuval Mintz qed_link_update(p_hwfn); 488cc875c2eSYuval Mintz } 489cc875c2eSYuval Mintz 490cc875c2eSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, 491cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 492cc875c2eSYuval Mintz bool b_up) 493cc875c2eSYuval Mintz { 494cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 495cc875c2eSYuval Mintz u32 param = 0, reply = 0, cmd; 496cc875c2eSYuval Mintz struct pmm_phy_cfg phy_cfg; 497cc875c2eSYuval Mintz int rc = 0; 498cc875c2eSYuval Mintz u32 i; 499cc875c2eSYuval Mintz 500cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 501cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized !\n"); 502cc875c2eSYuval Mintz return -EBUSY; 503cc875c2eSYuval Mintz } 504cc875c2eSYuval Mintz 505cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 506cc875c2eSYuval Mintz memset(&phy_cfg, 0, sizeof(phy_cfg)); 507cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 508cc875c2eSYuval Mintz if (!params->speed.autoneg) 509cc875c2eSYuval Mintz phy_cfg.speed = params->speed.forced_speed; 510cc875c2eSYuval Mintz phy_cfg.pause |= (params->pause.autoneg) ? PMM_PAUSE_AUTONEG : 0; 511cc875c2eSYuval Mintz phy_cfg.pause |= (params->pause.forced_rx) ? PMM_PAUSE_RX : 0; 512cc875c2eSYuval Mintz phy_cfg.pause |= (params->pause.forced_tx) ? PMM_PAUSE_TX : 0; 513cc875c2eSYuval Mintz phy_cfg.adv_speed = params->speed.advertised_speeds; 514cc875c2eSYuval Mintz phy_cfg.loopback_mode = params->loopback_mode; 515cc875c2eSYuval Mintz 516cc875c2eSYuval Mintz /* Write the requested configuration to shmem */ 517cc875c2eSYuval Mintz for (i = 0; i < sizeof(phy_cfg); i += 4) 518cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 519cc875c2eSYuval Mintz p_hwfn->mcp_info->drv_mb_addr + 520cc875c2eSYuval Mintz offsetof(struct public_drv_mb, union_data) + i, 521cc875c2eSYuval Mintz ((u32 *)&phy_cfg)[i >> 2]); 522cc875c2eSYuval Mintz 523cc875c2eSYuval Mintz if (b_up) { 524cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 525cc875c2eSYuval Mintz "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 526cc875c2eSYuval Mintz phy_cfg.speed, 527cc875c2eSYuval Mintz phy_cfg.pause, 528cc875c2eSYuval Mintz phy_cfg.adv_speed, 529cc875c2eSYuval Mintz phy_cfg.loopback_mode, 530cc875c2eSYuval Mintz phy_cfg.feature_config_flags); 531cc875c2eSYuval Mintz } else { 532cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 533cc875c2eSYuval Mintz "Resetting link\n"); 534cc875c2eSYuval Mintz } 535cc875c2eSYuval Mintz 536cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "fw_seq 0x%08x, drv_pulse 0x%x\n", 537cc875c2eSYuval Mintz p_hwfn->mcp_info->drv_mb_seq, 538cc875c2eSYuval Mintz p_hwfn->mcp_info->drv_pulse_seq); 539cc875c2eSYuval Mintz 540cc875c2eSYuval Mintz /* Load Request */ 541cc875c2eSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, cmd, 0, &reply, ¶m); 542cc875c2eSYuval Mintz 543cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 544cc875c2eSYuval Mintz if (rc) { 545cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 546cc875c2eSYuval Mintz return rc; 547cc875c2eSYuval Mintz } 548cc875c2eSYuval Mintz 549cc875c2eSYuval Mintz /* Reset the link status if needed */ 550cc875c2eSYuval Mintz if (!b_up) 551cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, true); 552cc875c2eSYuval Mintz 553cc875c2eSYuval Mintz return 0; 554cc875c2eSYuval Mintz } 555cc875c2eSYuval Mintz 556cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 557cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 558cc875c2eSYuval Mintz { 559cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 560cc875c2eSYuval Mintz int rc = 0; 561cc875c2eSYuval Mintz bool found = false; 562cc875c2eSYuval Mintz u16 i; 563cc875c2eSYuval Mintz 564cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 565cc875c2eSYuval Mintz 566cc875c2eSYuval Mintz /* Read Messages from MFW */ 567cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 568cc875c2eSYuval Mintz 569cc875c2eSYuval Mintz /* Compare current messages to old ones */ 570cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 571cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 572cc875c2eSYuval Mintz continue; 573cc875c2eSYuval Mintz 574cc875c2eSYuval Mintz found = true; 575cc875c2eSYuval Mintz 576cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 577cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 578cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 579cc875c2eSYuval Mintz 580cc875c2eSYuval Mintz switch (i) { 581cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 582cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 583cc875c2eSYuval Mintz break; 584cc875c2eSYuval Mintz default: 585cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "Unimplemented MFW message %d\n", i); 586cc875c2eSYuval Mintz rc = -EINVAL; 587cc875c2eSYuval Mintz } 588cc875c2eSYuval Mintz } 589cc875c2eSYuval Mintz 590cc875c2eSYuval Mintz /* ACK everything */ 591cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 592cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 593cc875c2eSYuval Mintz 594cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 595cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 596cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 597cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 598cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 599cc875c2eSYuval Mintz (__force u32)val); 600cc875c2eSYuval Mintz } 601cc875c2eSYuval Mintz 602cc875c2eSYuval Mintz if (!found) { 603cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 604cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 605cc875c2eSYuval Mintz rc = -EINVAL; 606cc875c2eSYuval Mintz } 607cc875c2eSYuval Mintz 608cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 609cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 610cc875c2eSYuval Mintz 611cc875c2eSYuval Mintz return rc; 612cc875c2eSYuval Mintz } 613cc875c2eSYuval Mintz 614fe56b9e6SYuval Mintz int qed_mcp_get_mfw_ver(struct qed_dev *cdev, 615fe56b9e6SYuval Mintz u32 *p_mfw_ver) 616fe56b9e6SYuval Mintz { 617fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 618fe56b9e6SYuval Mintz struct qed_ptt *p_ptt; 619fe56b9e6SYuval Mintz u32 global_offsize; 620fe56b9e6SYuval Mintz 621fe56b9e6SYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 622fe56b9e6SYuval Mintz if (!p_ptt) 623fe56b9e6SYuval Mintz return -EBUSY; 624fe56b9e6SYuval Mintz 625fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 626fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info-> 627fe56b9e6SYuval Mintz public_base, 628fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 629fe56b9e6SYuval Mintz *p_mfw_ver = qed_rd(p_hwfn, p_ptt, 630fe56b9e6SYuval Mintz SECTION_ADDR(global_offsize, 0) + 631fe56b9e6SYuval Mintz offsetof(struct public_global, mfw_ver)); 632fe56b9e6SYuval Mintz 633fe56b9e6SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 634fe56b9e6SYuval Mintz 635fe56b9e6SYuval Mintz return 0; 636fe56b9e6SYuval Mintz } 637fe56b9e6SYuval Mintz 638cc875c2eSYuval Mintz int qed_mcp_get_media_type(struct qed_dev *cdev, 639cc875c2eSYuval Mintz u32 *p_media_type) 640cc875c2eSYuval Mintz { 641cc875c2eSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 642cc875c2eSYuval Mintz struct qed_ptt *p_ptt; 643cc875c2eSYuval Mintz 644cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 645cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized !\n"); 646cc875c2eSYuval Mintz return -EBUSY; 647cc875c2eSYuval Mintz } 648cc875c2eSYuval Mintz 649cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 650cc875c2eSYuval Mintz 651cc875c2eSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 652cc875c2eSYuval Mintz if (!p_ptt) 653cc875c2eSYuval Mintz return -EBUSY; 654cc875c2eSYuval Mintz 655cc875c2eSYuval Mintz *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 656cc875c2eSYuval Mintz offsetof(struct public_port, media_type)); 657cc875c2eSYuval Mintz 658cc875c2eSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 659cc875c2eSYuval Mintz 660cc875c2eSYuval Mintz return 0; 661cc875c2eSYuval Mintz } 662cc875c2eSYuval Mintz 663fe56b9e6SYuval Mintz static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 664fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 665fe56b9e6SYuval Mintz struct public_func *p_data, 666fe56b9e6SYuval Mintz int pfid) 667fe56b9e6SYuval Mintz { 668fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 669fe56b9e6SYuval Mintz PUBLIC_FUNC); 670fe56b9e6SYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 671fe56b9e6SYuval Mintz u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 672fe56b9e6SYuval Mintz u32 i, size; 673fe56b9e6SYuval Mintz 674fe56b9e6SYuval Mintz memset(p_data, 0, sizeof(*p_data)); 675fe56b9e6SYuval Mintz 676fe56b9e6SYuval Mintz size = min_t(u32, sizeof(*p_data), 677fe56b9e6SYuval Mintz QED_SECTION_SIZE(mfw_path_offsize)); 678fe56b9e6SYuval Mintz for (i = 0; i < size / sizeof(u32); i++) 679fe56b9e6SYuval Mintz ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 680fe56b9e6SYuval Mintz func_addr + (i << 2)); 681fe56b9e6SYuval Mintz 682fe56b9e6SYuval Mintz return size; 683fe56b9e6SYuval Mintz } 684fe56b9e6SYuval Mintz 685fe56b9e6SYuval Mintz static int 686fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 687fe56b9e6SYuval Mintz struct public_func *p_info, 688fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 689fe56b9e6SYuval Mintz { 690fe56b9e6SYuval Mintz int rc = 0; 691fe56b9e6SYuval Mintz 692fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 693fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 694fe56b9e6SYuval Mintz *p_proto = QED_PCI_ETH; 695fe56b9e6SYuval Mintz break; 696fe56b9e6SYuval Mintz default: 697fe56b9e6SYuval Mintz rc = -EINVAL; 698fe56b9e6SYuval Mintz } 699fe56b9e6SYuval Mintz 700fe56b9e6SYuval Mintz return rc; 701fe56b9e6SYuval Mintz } 702fe56b9e6SYuval Mintz 703fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 704fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 705fe56b9e6SYuval Mintz { 706fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 707fe56b9e6SYuval Mintz struct public_func shmem_info; 708fe56b9e6SYuval Mintz 709fe56b9e6SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 710fe56b9e6SYuval Mintz MCP_PF_ID(p_hwfn)); 711fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 712fe56b9e6SYuval Mintz 713fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 714fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 715fe56b9e6SYuval Mintz 716fe56b9e6SYuval Mintz if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, 717fe56b9e6SYuval Mintz &info->protocol)) { 718fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 719fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 720fe56b9e6SYuval Mintz return -EINVAL; 721fe56b9e6SYuval Mintz } 722fe56b9e6SYuval Mintz 723fe56b9e6SYuval Mintz if (p_hwfn->cdev->mf_mode != SF) { 724fe56b9e6SYuval Mintz info->bandwidth_min = (shmem_info.config & 725fe56b9e6SYuval Mintz FUNC_MF_CFG_MIN_BW_MASK) >> 726fe56b9e6SYuval Mintz FUNC_MF_CFG_MIN_BW_SHIFT; 727fe56b9e6SYuval Mintz if (info->bandwidth_min < 1 || info->bandwidth_min > 100) { 728fe56b9e6SYuval Mintz DP_INFO(p_hwfn, 729fe56b9e6SYuval Mintz "bandwidth minimum out of bounds [%02x]. Set to 1\n", 730fe56b9e6SYuval Mintz info->bandwidth_min); 731fe56b9e6SYuval Mintz info->bandwidth_min = 1; 732fe56b9e6SYuval Mintz } 733fe56b9e6SYuval Mintz 734fe56b9e6SYuval Mintz info->bandwidth_max = (shmem_info.config & 735fe56b9e6SYuval Mintz FUNC_MF_CFG_MAX_BW_MASK) >> 736fe56b9e6SYuval Mintz FUNC_MF_CFG_MAX_BW_SHIFT; 737fe56b9e6SYuval Mintz if (info->bandwidth_max < 1 || info->bandwidth_max > 100) { 738fe56b9e6SYuval Mintz DP_INFO(p_hwfn, 739fe56b9e6SYuval Mintz "bandwidth maximum out of bounds [%02x]. Set to 100\n", 740fe56b9e6SYuval Mintz info->bandwidth_max); 741fe56b9e6SYuval Mintz info->bandwidth_max = 100; 742fe56b9e6SYuval Mintz } 743fe56b9e6SYuval Mintz } 744fe56b9e6SYuval Mintz 745fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 746fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 747fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 748fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 749fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 750fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 751fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 752fe56b9e6SYuval Mintz } else { 753fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 754fe56b9e6SYuval Mintz } 755fe56b9e6SYuval Mintz 756fe56b9e6SYuval Mintz info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper | 757fe56b9e6SYuval Mintz (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32); 758fe56b9e6SYuval Mintz info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper | 759fe56b9e6SYuval Mintz (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32); 760fe56b9e6SYuval Mintz 761fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 762fe56b9e6SYuval Mintz 763fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 764fe56b9e6SYuval Mintz "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x\n", 765fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 766fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 767fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 768fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 769fe56b9e6SYuval Mintz info->wwn_port, info->wwn_node, info->ovlan); 770fe56b9e6SYuval Mintz 771fe56b9e6SYuval Mintz return 0; 772fe56b9e6SYuval Mintz } 773fe56b9e6SYuval Mintz 774cc875c2eSYuval Mintz struct qed_mcp_link_params 775cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 776cc875c2eSYuval Mintz { 777cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 778cc875c2eSYuval Mintz return NULL; 779cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 780cc875c2eSYuval Mintz } 781cc875c2eSYuval Mintz 782cc875c2eSYuval Mintz struct qed_mcp_link_state 783cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 784cc875c2eSYuval Mintz { 785cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 786cc875c2eSYuval Mintz return NULL; 787cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 788cc875c2eSYuval Mintz } 789cc875c2eSYuval Mintz 790cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 791cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 792cc875c2eSYuval Mintz { 793cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 794cc875c2eSYuval Mintz return NULL; 795cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 796cc875c2eSYuval Mintz } 797cc875c2eSYuval Mintz 798fe56b9e6SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, 799fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 800fe56b9e6SYuval Mintz { 801fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 802fe56b9e6SYuval Mintz int rc; 803fe56b9e6SYuval Mintz 804fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 805fe56b9e6SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 100, 806fe56b9e6SYuval Mintz &resp, ¶m); 807fe56b9e6SYuval Mintz 808fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 809fe56b9e6SYuval Mintz msleep(120); 810fe56b9e6SYuval Mintz 811fe56b9e6SYuval Mintz return rc; 812fe56b9e6SYuval Mintz } 813fe56b9e6SYuval Mintz 814cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 815cee4d264SManish Chopra struct qed_ptt *p_ptt, 816cee4d264SManish Chopra u32 *p_flash_size) 817cee4d264SManish Chopra { 818cee4d264SManish Chopra u32 flash_size; 819cee4d264SManish Chopra 820cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 821cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 822cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 823cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 824cee4d264SManish Chopra 825cee4d264SManish Chopra *p_flash_size = flash_size; 826cee4d264SManish Chopra 827cee4d264SManish Chopra return 0; 828cee4d264SManish Chopra } 829cee4d264SManish Chopra 830fe56b9e6SYuval Mintz int 831fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 832fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 833fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 834fe56b9e6SYuval Mintz { 835fe56b9e6SYuval Mintz int rc = 0; 836fe56b9e6SYuval Mintz u32 param = 0, reply = 0, i; 837fe56b9e6SYuval Mintz 838fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 839fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized !\n"); 840fe56b9e6SYuval Mintz return -EBUSY; 841fe56b9e6SYuval Mintz } 842fe56b9e6SYuval Mintz 843fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, union_data.drv_version.version, 844fe56b9e6SYuval Mintz p_ver->version); 845fe56b9e6SYuval Mintz /* Copy version string to shmem */ 846fe56b9e6SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / 4; i++) { 847fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, 848fe56b9e6SYuval Mintz union_data.drv_version.name[i * sizeof(u32)], 849fe56b9e6SYuval Mintz *(u32 *)&p_ver->name[i * sizeof(u32)]); 850fe56b9e6SYuval Mintz } 851fe56b9e6SYuval Mintz 852fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_VERSION, 0, &reply, 853fe56b9e6SYuval Mintz ¶m); 854fe56b9e6SYuval Mintz if (rc) { 855fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 856fe56b9e6SYuval Mintz return rc; 857fe56b9e6SYuval Mintz } 858fe56b9e6SYuval Mintz 859fe56b9e6SYuval Mintz return 0; 860fe56b9e6SYuval Mintz } 86191420b83SSudarsana Kalluru 86291420b83SSudarsana Kalluru int qed_mcp_set_led(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 86391420b83SSudarsana Kalluru enum qed_led_mode mode) 86491420b83SSudarsana Kalluru { 86591420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 86691420b83SSudarsana Kalluru int rc; 86791420b83SSudarsana Kalluru 86891420b83SSudarsana Kalluru switch (mode) { 86991420b83SSudarsana Kalluru case QED_LED_MODE_ON: 87091420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 87191420b83SSudarsana Kalluru break; 87291420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 87391420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 87491420b83SSudarsana Kalluru break; 87591420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 87691420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 87791420b83SSudarsana Kalluru break; 87891420b83SSudarsana Kalluru default: 87991420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 88091420b83SSudarsana Kalluru return -EINVAL; 88191420b83SSudarsana Kalluru } 88291420b83SSudarsana Kalluru 88391420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 88491420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 88591420b83SSudarsana Kalluru 88691420b83SSudarsana Kalluru return rc; 88791420b83SSudarsana Kalluru } 888