1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/delay.h> 36fe56b9e6SYuval Mintz #include <linux/errno.h> 37fe56b9e6SYuval Mintz #include <linux/kernel.h> 38fe56b9e6SYuval Mintz #include <linux/slab.h> 395529bad9STomer Tayar #include <linux/spinlock.h> 40fe56b9e6SYuval Mintz #include <linux/string.h> 410fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 42fe56b9e6SYuval Mintz #include "qed.h" 43cac6f691SSudarsana Reddy Kalluru #include "qed_cxt.h" 4439651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 45fe56b9e6SYuval Mintz #include "qed_hsi.h" 46fe56b9e6SYuval Mintz #include "qed_hw.h" 47fe56b9e6SYuval Mintz #include "qed_mcp.h" 48fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 491408cc1fSYuval Mintz #include "qed_sriov.h" 501408cc1fSYuval Mintz 510500a70dSMichal Kalderon #define GRCBASE_MCP 0xe00000 520500a70dSMichal Kalderon 53eaa50fc5STomer Tayar #define QED_MCP_RESP_ITER_US 10 54fe56b9e6SYuval Mintz 55fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 56fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 57fe56b9e6SYuval Mintz 58fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 59fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 60fe56b9e6SYuval Mintz _val) 61fe56b9e6SYuval Mintz 62fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 63fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 64fe56b9e6SYuval Mintz 65fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 66fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 67fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 68fe56b9e6SYuval Mintz 69fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 70fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 71fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 72fe56b9e6SYuval Mintz 73fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 74fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 77fe56b9e6SYuval Mintz 78fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 79fe56b9e6SYuval Mintz { 80fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 81fe56b9e6SYuval Mintz return false; 82fe56b9e6SYuval Mintz return true; 83fe56b9e6SYuval Mintz } 84fe56b9e6SYuval Mintz 851a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 86fe56b9e6SYuval Mintz { 87fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 88fe56b9e6SYuval Mintz PUBLIC_PORT); 89fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 90fe56b9e6SYuval Mintz 91fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 92fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 93fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 94fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 95fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 96fe56b9e6SYuval Mintz } 97fe56b9e6SYuval Mintz 981a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 99fe56b9e6SYuval Mintz { 100fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 101fe56b9e6SYuval Mintz u32 tmp, i; 102fe56b9e6SYuval Mintz 103fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 104fe56b9e6SYuval Mintz return; 105fe56b9e6SYuval Mintz 106fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 107fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 108fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 109fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 110fe56b9e6SYuval Mintz 111fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 112fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 113fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 114fe56b9e6SYuval Mintz } 115fe56b9e6SYuval Mintz } 116fe56b9e6SYuval Mintz 1174ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 1184ed1eea8STomer Tayar struct list_head list; 1194ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 1204ed1eea8STomer Tayar u16 expected_seq_num; 1214ed1eea8STomer Tayar bool b_is_completed; 1224ed1eea8STomer Tayar }; 1234ed1eea8STomer Tayar 1244ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1254ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1264ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1274ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1284ed1eea8STomer Tayar u16 expected_seq_num) 1294ed1eea8STomer Tayar { 1304ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1314ed1eea8STomer Tayar 1324ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1334ed1eea8STomer Tayar if (!p_cmd_elem) 1344ed1eea8STomer Tayar goto out; 1354ed1eea8STomer Tayar 1364ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1374ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1384ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1394ed1eea8STomer Tayar out: 1404ed1eea8STomer Tayar return p_cmd_elem; 1414ed1eea8STomer Tayar } 1424ed1eea8STomer Tayar 1434ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1444ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1454ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1464ed1eea8STomer Tayar { 1474ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1484ed1eea8STomer Tayar kfree(p_cmd_elem); 1494ed1eea8STomer Tayar } 1504ed1eea8STomer Tayar 1514ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1524ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1534ed1eea8STomer Tayar u16 seq_num) 1544ed1eea8STomer Tayar { 1554ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1564ed1eea8STomer Tayar 1574ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1584ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1594ed1eea8STomer Tayar return p_cmd_elem; 1604ed1eea8STomer Tayar } 1614ed1eea8STomer Tayar 1624ed1eea8STomer Tayar return NULL; 1634ed1eea8STomer Tayar } 1644ed1eea8STomer Tayar 165fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 166fe56b9e6SYuval Mintz { 167fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1684ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1694ed1eea8STomer Tayar 170fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 171fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1724ed1eea8STomer Tayar 1734ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1744ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1754ed1eea8STomer Tayar p_tmp, 1764ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1774ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 178fe56b9e6SYuval Mintz } 1794ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1804ed1eea8STomer Tayar } 1814ed1eea8STomer Tayar 182fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 1833587cb87STomer Tayar p_hwfn->mcp_info = NULL; 184fe56b9e6SYuval Mintz 185fe56b9e6SYuval Mintz return 0; 186fe56b9e6SYuval Mintz } 187fe56b9e6SYuval Mintz 188f00d25f3STomer Tayar /* Maximum of 1 sec to wait for the SHMEM ready indication */ 189f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_MAX_RETRIES 20 190f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_ITER_MS 50 191f00d25f3STomer Tayar 1921a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 193fe56b9e6SYuval Mintz { 194fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 195f00d25f3STomer Tayar u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES; 196f00d25f3STomer Tayar u8 msec = QED_MCP_SHMEM_RDY_ITER_MS; 197fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 198fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 199fe56b9e6SYuval Mintz 200fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 201f00d25f3STomer Tayar if (!p_info->public_base) { 202f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 203f00d25f3STomer Tayar "The address of the MCP scratch-pad is not configured\n"); 204f00d25f3STomer Tayar return -EINVAL; 205f00d25f3STomer Tayar } 206fe56b9e6SYuval Mintz 207fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 208fe56b9e6SYuval Mintz 209f00d25f3STomer Tayar /* Get the MFW MB address and number of supported messages */ 210f00d25f3STomer Tayar mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 211f00d25f3STomer Tayar SECTION_OFFSIZE_ADDR(p_info->public_base, 212f00d25f3STomer Tayar PUBLIC_MFW_MB)); 213f00d25f3STomer Tayar p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 214f00d25f3STomer Tayar p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, 215f00d25f3STomer Tayar p_info->mfw_mb_addr + 216f00d25f3STomer Tayar offsetof(struct public_mfw_mb, 217f00d25f3STomer Tayar sup_msgs)); 218f00d25f3STomer Tayar 219f00d25f3STomer Tayar /* The driver can notify that there was an MCP reset, and might read the 220f00d25f3STomer Tayar * SHMEM values before the MFW has completed initializing them. 221f00d25f3STomer Tayar * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a 222f00d25f3STomer Tayar * data ready indication. 223f00d25f3STomer Tayar */ 224f00d25f3STomer Tayar while (!p_info->mfw_mb_length && --cnt) { 225f00d25f3STomer Tayar msleep(msec); 226f00d25f3STomer Tayar p_info->mfw_mb_length = 227f00d25f3STomer Tayar (u16)qed_rd(p_hwfn, p_ptt, 228f00d25f3STomer Tayar p_info->mfw_mb_addr + 229f00d25f3STomer Tayar offsetof(struct public_mfw_mb, sup_msgs)); 230f00d25f3STomer Tayar } 231f00d25f3STomer Tayar 232f00d25f3STomer Tayar if (!cnt) { 233f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 234f00d25f3STomer Tayar "Failed to get the SHMEM ready notification after %d msec\n", 235f00d25f3STomer Tayar QED_MCP_SHMEM_RDY_MAX_RETRIES * msec); 236f00d25f3STomer Tayar return -EBUSY; 237f00d25f3STomer Tayar } 238f00d25f3STomer Tayar 239fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 240fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 241fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 242fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 243fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 244fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 245fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 246fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 247fe56b9e6SYuval Mintz 248fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 249fe56b9e6SYuval Mintz * the first command 250fe56b9e6SYuval Mintz */ 251fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 252fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 253fe56b9e6SYuval Mintz 254fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 255fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 256fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 257fe56b9e6SYuval Mintz 2584ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 259fe56b9e6SYuval Mintz 260fe56b9e6SYuval Mintz return 0; 261fe56b9e6SYuval Mintz } 262fe56b9e6SYuval Mintz 2631a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 264fe56b9e6SYuval Mintz { 265fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 266fe56b9e6SYuval Mintz u32 size; 267fe56b9e6SYuval Mintz 268fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 26960fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 270fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 271fe56b9e6SYuval Mintz goto err; 272fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 273fe56b9e6SYuval Mintz 2744ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2754ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2764ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2774ed1eea8STomer Tayar 2784ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2794ed1eea8STomer Tayar 280fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 281fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 282fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 283fe56b9e6SYuval Mintz * the MCP is not initialized 284fe56b9e6SYuval Mintz */ 285fe56b9e6SYuval Mintz return 0; 286fe56b9e6SYuval Mintz } 287fe56b9e6SYuval Mintz 288fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 28960fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 29083aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 291eb2a6b80SChristophe Jaillet if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 292fe56b9e6SYuval Mintz goto err; 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz return 0; 295fe56b9e6SYuval Mintz 296fe56b9e6SYuval Mintz err: 297fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 298fe56b9e6SYuval Mintz return -ENOMEM; 299fe56b9e6SYuval Mintz } 300fe56b9e6SYuval Mintz 3014ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 3024ed1eea8STomer Tayar struct qed_ptt *p_ptt) 3035529bad9STomer Tayar { 3044ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3055529bad9STomer Tayar 3064ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 3074ed1eea8STomer Tayar * time and now. 3085529bad9STomer Tayar */ 3094ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 3104ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 3114ed1eea8STomer Tayar QED_MSG_SP, 3124ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 3134ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 3145529bad9STomer Tayar 3154ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 3164ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 3175529bad9STomer Tayar } 3185529bad9STomer Tayar } 3195529bad9STomer Tayar 3201a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 321fe56b9e6SYuval Mintz { 322eaa50fc5STomer Tayar u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0; 323fe56b9e6SYuval Mintz int rc = 0; 324fe56b9e6SYuval Mintz 325b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 326b310974eSTomer Tayar DP_NOTICE(p_hwfn, 327b310974eSTomer Tayar "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n"); 328b310974eSTomer Tayar return -EBUSY; 329b310974eSTomer Tayar } 330b310974eSTomer Tayar 3314ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 3324ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 3334ed1eea8STomer Tayar 3344ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3355529bad9STomer Tayar 336fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 3374ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 3384ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 3394ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 340fe56b9e6SYuval Mintz 341fe56b9e6SYuval Mintz do { 342fe56b9e6SYuval Mintz /* Wait for MFW response */ 343fe56b9e6SYuval Mintz udelay(delay); 344fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 345fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 346fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 347fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 348fe56b9e6SYuval Mintz 349fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 350fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 351fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 352fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 353fe56b9e6SYuval Mintz } else { 354fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 355fe56b9e6SYuval Mintz rc = -EAGAIN; 356fe56b9e6SYuval Mintz } 357fe56b9e6SYuval Mintz 3584ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3595529bad9STomer Tayar 360fe56b9e6SYuval Mintz return rc; 361fe56b9e6SYuval Mintz } 362fe56b9e6SYuval Mintz 3634ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3644ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 365fe56b9e6SYuval Mintz { 3664ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3674ed1eea8STomer Tayar 3684ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3694ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3704ed1eea8STomer Tayar */ 3714ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3724ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3734ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3744ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3754ed1eea8STomer Tayar } 3764ed1eea8STomer Tayar 3774ed1eea8STomer Tayar return false; 3784ed1eea8STomer Tayar } 3794ed1eea8STomer Tayar 3804ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3814ed1eea8STomer Tayar static int 3824ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3834ed1eea8STomer Tayar { 3844ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3854ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3864ed1eea8STomer Tayar u32 mcp_resp; 3874ed1eea8STomer Tayar u16 seq_num; 3884ed1eea8STomer Tayar 3894ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3904ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3914ed1eea8STomer Tayar 3924ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3934ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3944ed1eea8STomer Tayar return -EAGAIN; 3954ed1eea8STomer Tayar 3964ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3974ed1eea8STomer Tayar if (!p_cmd_elem) { 3984ed1eea8STomer Tayar DP_ERR(p_hwfn, 3994ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 4004ed1eea8STomer Tayar seq_num); 4014ed1eea8STomer Tayar return -EINVAL; 4024ed1eea8STomer Tayar } 4034ed1eea8STomer Tayar 4044ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 4054ed1eea8STomer Tayar 4064ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 4074ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 4084ed1eea8STomer Tayar 4094ed1eea8STomer Tayar /* Get the MFW param */ 4104ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 4114ed1eea8STomer Tayar 4124ed1eea8STomer Tayar /* Get the union data */ 4132f67af8cSTomer Tayar if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 4144ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4154ed1eea8STomer Tayar offsetof(struct public_drv_mb, 4164ed1eea8STomer Tayar union_data); 4174ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 4182f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 4194ed1eea8STomer Tayar } 4204ed1eea8STomer Tayar 4214ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 4224ed1eea8STomer Tayar 4234ed1eea8STomer Tayar return 0; 4244ed1eea8STomer Tayar } 4254ed1eea8STomer Tayar 4264ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 4274ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4284ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4294ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4304ed1eea8STomer Tayar u16 seq_num) 4314ed1eea8STomer Tayar { 4324ed1eea8STomer Tayar union drv_union_data union_data; 4334ed1eea8STomer Tayar u32 union_data_addr; 4344ed1eea8STomer Tayar 4354ed1eea8STomer Tayar /* Set the union data */ 4364ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4374ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 4384ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 4392f67af8cSTomer Tayar if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 4404ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 4412f67af8cSTomer Tayar p_mb_params->data_src_size); 4424ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4434ed1eea8STomer Tayar sizeof(union_data)); 4444ed1eea8STomer Tayar 4454ed1eea8STomer Tayar /* Set the drv param */ 4464ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4474ed1eea8STomer Tayar 4484ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4494ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4504ed1eea8STomer Tayar 4514ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4524ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4534ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4544ed1eea8STomer Tayar } 4554ed1eea8STomer Tayar 456b310974eSTomer Tayar static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd) 457b310974eSTomer Tayar { 458b310974eSTomer Tayar p_hwfn->mcp_info->b_block_cmd = block_cmd; 459b310974eSTomer Tayar 460b310974eSTomer Tayar DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n", 461b310974eSTomer Tayar block_cmd ? "Block" : "Unblock"); 462b310974eSTomer Tayar } 463b310974eSTomer Tayar 464b310974eSTomer Tayar static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn, 465b310974eSTomer Tayar struct qed_ptt *p_ptt) 466b310974eSTomer Tayar { 467b310974eSTomer Tayar u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2; 468b310974eSTomer Tayar u32 delay = QED_MCP_RESP_ITER_US; 469b310974eSTomer Tayar 470b310974eSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 471b310974eSTomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 472b310974eSTomer Tayar cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 473b310974eSTomer Tayar udelay(delay); 474b310974eSTomer Tayar cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 475b310974eSTomer Tayar udelay(delay); 476b310974eSTomer Tayar cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 477b310974eSTomer Tayar 478b310974eSTomer Tayar DP_NOTICE(p_hwfn, 479b310974eSTomer Tayar "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n", 480b310974eSTomer Tayar cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2); 481b310974eSTomer Tayar } 482b310974eSTomer Tayar 4834ed1eea8STomer Tayar static int 4844ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4854ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4864ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 487eaa50fc5STomer Tayar u32 max_retries, u32 usecs) 4884ed1eea8STomer Tayar { 489eaa50fc5STomer Tayar u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000); 4904ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4914ed1eea8STomer Tayar u16 seq_num; 492fe56b9e6SYuval Mintz int rc = 0; 493fe56b9e6SYuval Mintz 4944ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 495fe56b9e6SYuval Mintz do { 4964ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4974ed1eea8STomer Tayar * pending command is completed during this iteration. 4984ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4994ed1eea8STomer Tayar */ 5004ed1eea8STomer Tayar 5014ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5024ed1eea8STomer Tayar 5034ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 5044ed1eea8STomer Tayar break; 5054ed1eea8STomer Tayar 5064ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5074ed1eea8STomer Tayar if (!rc) 5084ed1eea8STomer Tayar break; 5094ed1eea8STomer Tayar else if (rc != -EAGAIN) 5104ed1eea8STomer Tayar goto err; 5114ed1eea8STomer Tayar 5124ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 513eaa50fc5STomer Tayar 514eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 515eaa50fc5STomer Tayar msleep(msecs); 516eaa50fc5STomer Tayar else 517eaa50fc5STomer Tayar udelay(usecs); 5184ed1eea8STomer Tayar } while (++cnt < max_retries); 519fe56b9e6SYuval Mintz 5204ed1eea8STomer Tayar if (cnt >= max_retries) { 5214ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5224ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 5234ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 5244ed1eea8STomer Tayar return -EAGAIN; 525fe56b9e6SYuval Mintz } 5264ed1eea8STomer Tayar 5274ed1eea8STomer Tayar /* Send the mailbox command */ 5284ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 5294ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 5304ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 531c8004600SDan Carpenter if (!p_cmd_elem) { 532c8004600SDan Carpenter rc = -ENOMEM; 5334ed1eea8STomer Tayar goto err; 534c8004600SDan Carpenter } 5354ed1eea8STomer Tayar 5364ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 5374ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5384ed1eea8STomer Tayar 5394ed1eea8STomer Tayar /* Wait for the MFW response */ 5404ed1eea8STomer Tayar do { 5414ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 5424ed1eea8STomer Tayar * command is completed during this iteration. 5434ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 5444ed1eea8STomer Tayar */ 5454ed1eea8STomer Tayar 546eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 547eaa50fc5STomer Tayar msleep(msecs); 548eaa50fc5STomer Tayar else 549eaa50fc5STomer Tayar udelay(usecs); 550eaa50fc5STomer Tayar 5514ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5524ed1eea8STomer Tayar 5534ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 5544ed1eea8STomer Tayar break; 5554ed1eea8STomer Tayar 5564ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5574ed1eea8STomer Tayar if (!rc) 5584ed1eea8STomer Tayar break; 5594ed1eea8STomer Tayar else if (rc != -EAGAIN) 5604ed1eea8STomer Tayar goto err; 5614ed1eea8STomer Tayar 5624ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5634ed1eea8STomer Tayar } while (++cnt < max_retries); 5644ed1eea8STomer Tayar 5654ed1eea8STomer Tayar if (cnt >= max_retries) { 5664ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5674ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 5684ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 569b310974eSTomer Tayar qed_mcp_print_cpu_info(p_hwfn, p_ptt); 5704ed1eea8STomer Tayar 5714ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5724ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5734ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5744ed1eea8STomer Tayar 575b310974eSTomer Tayar if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK)) 576b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 577b310974eSTomer Tayar 5784ed1eea8STomer Tayar return -EAGAIN; 5794ed1eea8STomer Tayar } 5804ed1eea8STomer Tayar 5814ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5824ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5834ed1eea8STomer Tayar 5844ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5854ed1eea8STomer Tayar QED_MSG_SP, 5864ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5874ed1eea8STomer Tayar p_mb_params->mcp_resp, 5884ed1eea8STomer Tayar p_mb_params->mcp_param, 589eaa50fc5STomer Tayar (cnt * usecs) / 1000, (cnt * usecs) % 1000); 5904ed1eea8STomer Tayar 5914ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5924ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5934ed1eea8STomer Tayar 5944ed1eea8STomer Tayar return 0; 5954ed1eea8STomer Tayar 5964ed1eea8STomer Tayar err: 5974ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 598fe56b9e6SYuval Mintz return rc; 599fe56b9e6SYuval Mintz } 600fe56b9e6SYuval Mintz 6015529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 602fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 6035529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 604fe56b9e6SYuval Mintz { 6052f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 6064ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 607eaa50fc5STomer Tayar u32 usecs = QED_MCP_RESP_ITER_US; 608fe56b9e6SYuval Mintz 609fe56b9e6SYuval Mintz /* MCP not initialized */ 610fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 611fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 612fe56b9e6SYuval Mintz return -EBUSY; 613fe56b9e6SYuval Mintz } 614fe56b9e6SYuval Mintz 615b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 616b310974eSTomer Tayar DP_NOTICE(p_hwfn, 617b310974eSTomer Tayar "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n", 618b310974eSTomer Tayar p_mb_params->cmd, p_mb_params->param); 619b310974eSTomer Tayar return -EBUSY; 620b310974eSTomer Tayar } 621b310974eSTomer Tayar 6222f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 6232f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 6242f67af8cSTomer Tayar DP_ERR(p_hwfn, 6252f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 6262f67af8cSTomer Tayar p_mb_params->data_src_size, 6272f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 6282f67af8cSTomer Tayar return -EINVAL; 6292f67af8cSTomer Tayar } 6302f67af8cSTomer Tayar 631eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) { 632eaa50fc5STomer Tayar max_retries = DIV_ROUND_UP(max_retries, 1000); 633eaa50fc5STomer Tayar usecs *= 1000; 634eaa50fc5STomer Tayar } 635eaa50fc5STomer Tayar 6364ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 637eaa50fc5STomer Tayar usecs); 638fe56b9e6SYuval Mintz } 639fe56b9e6SYuval Mintz 6405529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 6415529bad9STomer Tayar struct qed_ptt *p_ptt, 6425529bad9STomer Tayar u32 cmd, 6435529bad9STomer Tayar u32 param, 6445529bad9STomer Tayar u32 *o_mcp_resp, 6455529bad9STomer Tayar u32 *o_mcp_param) 646fe56b9e6SYuval Mintz { 6475529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 6485529bad9STomer Tayar int rc; 649fe56b9e6SYuval Mintz 6505529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6515529bad9STomer Tayar mb_params.cmd = cmd; 6525529bad9STomer Tayar mb_params.param = param; 65314d39648SMintz, Yuval 6545529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6555529bad9STomer Tayar if (rc) 6565529bad9STomer Tayar return rc; 6575529bad9STomer Tayar 6585529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6595529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 6605529bad9STomer Tayar 6615529bad9STomer Tayar return 0; 662fe56b9e6SYuval Mintz } 663fe56b9e6SYuval Mintz 664bf774d14SYueHaibing static int 665bf774d14SYueHaibing qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 66662e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 66762e4d438SSudarsana Reddy Kalluru u32 cmd, 66862e4d438SSudarsana Reddy Kalluru u32 param, 66962e4d438SSudarsana Reddy Kalluru u32 *o_mcp_resp, 67062e4d438SSudarsana Reddy Kalluru u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 67162e4d438SSudarsana Reddy Kalluru { 67262e4d438SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 67362e4d438SSudarsana Reddy Kalluru int rc; 67462e4d438SSudarsana Reddy Kalluru 67562e4d438SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 67662e4d438SSudarsana Reddy Kalluru mb_params.cmd = cmd; 67762e4d438SSudarsana Reddy Kalluru mb_params.param = param; 67862e4d438SSudarsana Reddy Kalluru mb_params.p_data_src = i_buf; 67962e4d438SSudarsana Reddy Kalluru mb_params.data_src_size = (u8)i_txn_size; 68062e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 68162e4d438SSudarsana Reddy Kalluru if (rc) 68262e4d438SSudarsana Reddy Kalluru return rc; 68362e4d438SSudarsana Reddy Kalluru 68462e4d438SSudarsana Reddy Kalluru *o_mcp_resp = mb_params.mcp_resp; 68562e4d438SSudarsana Reddy Kalluru *o_mcp_param = mb_params.mcp_param; 68662e4d438SSudarsana Reddy Kalluru 6875e7ba042SDenis Bolotin /* nvm_info needs to be updated */ 6885e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = false; 6895e7ba042SDenis Bolotin 69062e4d438SSudarsana Reddy Kalluru return 0; 69162e4d438SSudarsana Reddy Kalluru } 69262e4d438SSudarsana Reddy Kalluru 6934102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 6944102426fSTomer Tayar struct qed_ptt *p_ptt, 6954102426fSTomer Tayar u32 cmd, 6964102426fSTomer Tayar u32 param, 6974102426fSTomer Tayar u32 *o_mcp_resp, 6984102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 6994102426fSTomer Tayar { 7004102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 7012f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 7024102426fSTomer Tayar int rc; 7034102426fSTomer Tayar 7044102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 7054102426fSTomer Tayar mb_params.cmd = cmd; 7064102426fSTomer Tayar mb_params.param = param; 7072f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 7082f67af8cSTomer Tayar 7092f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 7102f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 7112f67af8cSTomer Tayar 7124102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 7134102426fSTomer Tayar if (rc) 7144102426fSTomer Tayar return rc; 7154102426fSTomer Tayar 7164102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 7174102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 7184102426fSTomer Tayar 7194102426fSTomer Tayar *o_txn_size = *o_mcp_param; 7202f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 7214102426fSTomer Tayar 7224102426fSTomer Tayar return 0; 7234102426fSTomer Tayar } 7244102426fSTomer Tayar 7255d24bcf1STomer Tayar static bool 7265d24bcf1STomer Tayar qed_mcp_can_force_load(u8 drv_role, 7275d24bcf1STomer Tayar u8 exist_drv_role, 7285d24bcf1STomer Tayar enum qed_override_force_load override_force_load) 729fe56b9e6SYuval Mintz { 7305d24bcf1STomer Tayar bool can_force_load = false; 7315d24bcf1STomer Tayar 7325d24bcf1STomer Tayar switch (override_force_load) { 7335d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 7345d24bcf1STomer Tayar can_force_load = true; 7355d24bcf1STomer Tayar break; 7365d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_NEVER: 7375d24bcf1STomer Tayar can_force_load = false; 7385d24bcf1STomer Tayar break; 7395d24bcf1STomer Tayar default: 7405d24bcf1STomer Tayar can_force_load = (drv_role == DRV_ROLE_OS && 7415d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_PREBOOT) || 7425d24bcf1STomer Tayar (drv_role == DRV_ROLE_KDUMP && 7435d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_OS); 7445d24bcf1STomer Tayar break; 7455d24bcf1STomer Tayar } 7465d24bcf1STomer Tayar 7475d24bcf1STomer Tayar return can_force_load; 7485d24bcf1STomer Tayar } 7495d24bcf1STomer Tayar 7505d24bcf1STomer Tayar static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 7515d24bcf1STomer Tayar struct qed_ptt *p_ptt) 7525d24bcf1STomer Tayar { 7535d24bcf1STomer Tayar u32 resp = 0, param = 0; 754fe56b9e6SYuval Mintz int rc; 755fe56b9e6SYuval Mintz 7565d24bcf1STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 7575d24bcf1STomer Tayar &resp, ¶m); 7585d24bcf1STomer Tayar if (rc) 7595d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 7605d24bcf1STomer Tayar "Failed to send cancel load request, rc = %d\n", rc); 761fe56b9e6SYuval Mintz 762fe56b9e6SYuval Mintz return rc; 763fe56b9e6SYuval Mintz } 764fe56b9e6SYuval Mintz 7655d24bcf1STomer Tayar #define CONFIG_QEDE_BITMAP_IDX BIT(0) 7665d24bcf1STomer Tayar #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 7675d24bcf1STomer Tayar #define CONFIG_QEDR_BITMAP_IDX BIT(2) 7685d24bcf1STomer Tayar #define CONFIG_QEDF_BITMAP_IDX BIT(4) 7695d24bcf1STomer Tayar #define CONFIG_QEDI_BITMAP_IDX BIT(5) 7705d24bcf1STomer Tayar #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 7715529bad9STomer Tayar 7725d24bcf1STomer Tayar static u32 qed_get_config_bitmap(void) 7735d24bcf1STomer Tayar { 7745d24bcf1STomer Tayar u32 config_bitmap = 0x0; 7755d24bcf1STomer Tayar 7765d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QEDE)) 7775d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 7785d24bcf1STomer Tayar 7795d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_SRIOV)) 7805d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 7815d24bcf1STomer Tayar 7825d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_RDMA)) 7835d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 7845d24bcf1STomer Tayar 7855d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_FCOE)) 7865d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 7875d24bcf1STomer Tayar 7885d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_ISCSI)) 7895d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 7905d24bcf1STomer Tayar 7915d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_LL2)) 7925d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 7935d24bcf1STomer Tayar 7945d24bcf1STomer Tayar return config_bitmap; 7955d24bcf1STomer Tayar } 7965d24bcf1STomer Tayar 7975d24bcf1STomer Tayar struct qed_load_req_in_params { 7985d24bcf1STomer Tayar u8 hsi_ver; 7995d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 8005d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_1 1 8015d24bcf1STomer Tayar u32 drv_ver_0; 8025d24bcf1STomer Tayar u32 drv_ver_1; 8035d24bcf1STomer Tayar u32 fw_ver; 8045d24bcf1STomer Tayar u8 drv_role; 8055d24bcf1STomer Tayar u8 timeout_val; 8065d24bcf1STomer Tayar u8 force_cmd; 8075d24bcf1STomer Tayar bool avoid_eng_reset; 8085d24bcf1STomer Tayar }; 8095d24bcf1STomer Tayar 8105d24bcf1STomer Tayar struct qed_load_req_out_params { 8115d24bcf1STomer Tayar u32 load_code; 8125d24bcf1STomer Tayar u32 exist_drv_ver_0; 8135d24bcf1STomer Tayar u32 exist_drv_ver_1; 8145d24bcf1STomer Tayar u32 exist_fw_ver; 8155d24bcf1STomer Tayar u8 exist_drv_role; 8165d24bcf1STomer Tayar u8 mfw_hsi_ver; 8175d24bcf1STomer Tayar bool drv_exists; 8185d24bcf1STomer Tayar }; 8195d24bcf1STomer Tayar 8205d24bcf1STomer Tayar static int 8215d24bcf1STomer Tayar __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 8225d24bcf1STomer Tayar struct qed_ptt *p_ptt, 8235d24bcf1STomer Tayar struct qed_load_req_in_params *p_in_params, 8245d24bcf1STomer Tayar struct qed_load_req_out_params *p_out_params) 8255d24bcf1STomer Tayar { 8265d24bcf1STomer Tayar struct qed_mcp_mb_params mb_params; 8275d24bcf1STomer Tayar struct load_req_stc load_req; 8285d24bcf1STomer Tayar struct load_rsp_stc load_rsp; 8295d24bcf1STomer Tayar u32 hsi_ver; 8305d24bcf1STomer Tayar int rc; 8315d24bcf1STomer Tayar 8325d24bcf1STomer Tayar memset(&load_req, 0, sizeof(load_req)); 8335d24bcf1STomer Tayar load_req.drv_ver_0 = p_in_params->drv_ver_0; 8345d24bcf1STomer Tayar load_req.drv_ver_1 = p_in_params->drv_ver_1; 8355d24bcf1STomer Tayar load_req.fw_ver = p_in_params->fw_ver; 8365d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 8375d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 8385d24bcf1STomer Tayar p_in_params->timeout_val); 8395d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 8405d24bcf1STomer Tayar p_in_params->force_cmd); 8415d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 8425d24bcf1STomer Tayar p_in_params->avoid_eng_reset); 8435d24bcf1STomer Tayar 8445d24bcf1STomer Tayar hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 8455d24bcf1STomer Tayar DRV_ID_MCP_HSI_VER_CURRENT : 8465d24bcf1STomer Tayar (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 8475d24bcf1STomer Tayar 8485d24bcf1STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 8495d24bcf1STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 8505d24bcf1STomer Tayar mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 8515d24bcf1STomer Tayar mb_params.p_data_src = &load_req; 8525d24bcf1STomer Tayar mb_params.data_src_size = sizeof(load_req); 8535d24bcf1STomer Tayar mb_params.p_data_dst = &load_rsp; 8545d24bcf1STomer Tayar mb_params.data_dst_size = sizeof(load_rsp); 855b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 8565d24bcf1STomer Tayar 8575d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8585d24bcf1STomer Tayar "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 8595d24bcf1STomer Tayar mb_params.param, 8605d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 8615d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 8625d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 8635d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 8645d24bcf1STomer Tayar 8655d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 8665d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8675d24bcf1STomer Tayar "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 8685d24bcf1STomer Tayar load_req.drv_ver_0, 8695d24bcf1STomer Tayar load_req.drv_ver_1, 8705d24bcf1STomer Tayar load_req.fw_ver, 8715d24bcf1STomer Tayar load_req.misc0, 8725d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 8735d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, 8745d24bcf1STomer Tayar LOAD_REQ_LOCK_TO), 8755d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 8765d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 8775d24bcf1STomer Tayar } 8785d24bcf1STomer Tayar 8795d24bcf1STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 8805d24bcf1STomer Tayar if (rc) { 8815d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 8825d24bcf1STomer Tayar return rc; 8835d24bcf1STomer Tayar } 8845d24bcf1STomer Tayar 8855d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8865d24bcf1STomer Tayar "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 8875d24bcf1STomer Tayar p_out_params->load_code = mb_params.mcp_resp; 8885d24bcf1STomer Tayar 8895d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 8905d24bcf1STomer Tayar p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 8915d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, 8925d24bcf1STomer Tayar QED_MSG_SP, 8935d24bcf1STomer Tayar "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 8945d24bcf1STomer Tayar load_rsp.drv_ver_0, 8955d24bcf1STomer Tayar load_rsp.drv_ver_1, 8965d24bcf1STomer Tayar load_rsp.fw_ver, 8975d24bcf1STomer Tayar load_rsp.misc0, 8985d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 8995d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 9005d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 9015d24bcf1STomer Tayar 9025d24bcf1STomer Tayar p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 9035d24bcf1STomer Tayar p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 9045d24bcf1STomer Tayar p_out_params->exist_fw_ver = load_rsp.fw_ver; 9055d24bcf1STomer Tayar p_out_params->exist_drv_role = 9065d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 9075d24bcf1STomer Tayar p_out_params->mfw_hsi_ver = 9085d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 9095d24bcf1STomer Tayar p_out_params->drv_exists = 9105d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 9115d24bcf1STomer Tayar LOAD_RSP_FLAGS0_DRV_EXISTS; 9125d24bcf1STomer Tayar } 9135d24bcf1STomer Tayar 9145d24bcf1STomer Tayar return 0; 9155d24bcf1STomer Tayar } 9165d24bcf1STomer Tayar 9175d24bcf1STomer Tayar static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 9185d24bcf1STomer Tayar enum qed_drv_role drv_role, 9195d24bcf1STomer Tayar u8 *p_mfw_drv_role) 9205d24bcf1STomer Tayar { 9215d24bcf1STomer Tayar switch (drv_role) { 9225d24bcf1STomer Tayar case QED_DRV_ROLE_OS: 9235d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_OS; 9245d24bcf1STomer Tayar break; 9255d24bcf1STomer Tayar case QED_DRV_ROLE_KDUMP: 9265d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_KDUMP; 9275d24bcf1STomer Tayar break; 9285d24bcf1STomer Tayar default: 9295d24bcf1STomer Tayar DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 9305d24bcf1STomer Tayar return -EINVAL; 9315d24bcf1STomer Tayar } 9325d24bcf1STomer Tayar 9335d24bcf1STomer Tayar return 0; 9345d24bcf1STomer Tayar } 9355d24bcf1STomer Tayar 9365d24bcf1STomer Tayar enum qed_load_req_force { 9375d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, 9385d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_PF, 9395d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9405d24bcf1STomer Tayar }; 9415d24bcf1STomer Tayar 9425d24bcf1STomer Tayar static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 9435d24bcf1STomer Tayar 9445d24bcf1STomer Tayar enum qed_load_req_force force_cmd, 9455d24bcf1STomer Tayar u8 *p_mfw_force_cmd) 9465d24bcf1STomer Tayar { 9475d24bcf1STomer Tayar switch (force_cmd) { 9485d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_NONE: 9495d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 9505d24bcf1STomer Tayar break; 9515d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_PF: 9525d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 9535d24bcf1STomer Tayar break; 9545d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_ALL: 9555d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 9565d24bcf1STomer Tayar break; 9575d24bcf1STomer Tayar } 9585d24bcf1STomer Tayar } 9595d24bcf1STomer Tayar 9605d24bcf1STomer Tayar int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 9615d24bcf1STomer Tayar struct qed_ptt *p_ptt, 9625d24bcf1STomer Tayar struct qed_load_req_params *p_params) 9635d24bcf1STomer Tayar { 9645d24bcf1STomer Tayar struct qed_load_req_out_params out_params; 9655d24bcf1STomer Tayar struct qed_load_req_in_params in_params; 9665d24bcf1STomer Tayar u8 mfw_drv_role, mfw_force_cmd; 9675d24bcf1STomer Tayar int rc; 9685d24bcf1STomer Tayar 9695d24bcf1STomer Tayar memset(&in_params, 0, sizeof(in_params)); 9705d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 9715d24bcf1STomer Tayar in_params.drv_ver_0 = QED_VERSION; 9725d24bcf1STomer Tayar in_params.drv_ver_1 = qed_get_config_bitmap(); 9735d24bcf1STomer Tayar in_params.fw_ver = STORM_FW_VERSION; 9745d24bcf1STomer Tayar rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 9755d24bcf1STomer Tayar if (rc) 9765d24bcf1STomer Tayar return rc; 9775d24bcf1STomer Tayar 9785d24bcf1STomer Tayar in_params.drv_role = mfw_drv_role; 9795d24bcf1STomer Tayar in_params.timeout_val = p_params->timeout_val; 9805d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9815d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 9825d24bcf1STomer Tayar 9835d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9845d24bcf1STomer Tayar in_params.avoid_eng_reset = p_params->avoid_eng_reset; 9855d24bcf1STomer Tayar 9865d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9875d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9885d24bcf1STomer Tayar if (rc) 9895d24bcf1STomer Tayar return rc; 9905d24bcf1STomer Tayar 9915d24bcf1STomer Tayar /* First handle cases where another load request should/might be sent: 9925d24bcf1STomer Tayar * - MFW expects the old interface [HSI version = 1] 9935d24bcf1STomer Tayar * - MFW responds that a force load request is required 994fe56b9e6SYuval Mintz */ 9955d24bcf1STomer Tayar if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 9965d24bcf1STomer Tayar DP_INFO(p_hwfn, 9975d24bcf1STomer Tayar "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 9985d24bcf1STomer Tayar 9995d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 10005d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 10015d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 10025d24bcf1STomer Tayar if (rc) 10035d24bcf1STomer Tayar return rc; 10045d24bcf1STomer Tayar } else if (out_params.load_code == 10055d24bcf1STomer Tayar FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 10065d24bcf1STomer Tayar if (qed_mcp_can_force_load(in_params.drv_role, 10075d24bcf1STomer Tayar out_params.exist_drv_role, 10085d24bcf1STomer Tayar p_params->override_force_load)) { 10095d24bcf1STomer Tayar DP_INFO(p_hwfn, 10105d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 10115d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10125d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10135d24bcf1STomer Tayar out_params.exist_drv_role, 10145d24bcf1STomer Tayar out_params.exist_fw_ver, 10155d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10165d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10175d24bcf1STomer Tayar 10185d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 10195d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 10205d24bcf1STomer Tayar &mfw_force_cmd); 10215d24bcf1STomer Tayar 10225d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 10235d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 10245d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 10255d24bcf1STomer Tayar &out_params); 10265d24bcf1STomer Tayar if (rc) 10275d24bcf1STomer Tayar return rc; 10285d24bcf1STomer Tayar } else { 10295d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10305d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 10315d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10325d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10335d24bcf1STomer Tayar out_params.exist_drv_role, 10345d24bcf1STomer Tayar out_params.exist_fw_ver, 10355d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10365d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10375d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10385d24bcf1STomer Tayar "Avoid sending a force load request to prevent disruption of active PFs\n"); 10395d24bcf1STomer Tayar 10405d24bcf1STomer Tayar qed_mcp_cancel_load_req(p_hwfn, p_ptt); 1041fe56b9e6SYuval Mintz return -EBUSY; 1042fe56b9e6SYuval Mintz } 10435d24bcf1STomer Tayar } 10445d24bcf1STomer Tayar 10455d24bcf1STomer Tayar /* Now handle the other types of responses. 10465d24bcf1STomer Tayar * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 10475d24bcf1STomer Tayar * expected here after the additional revised load requests were sent. 10485d24bcf1STomer Tayar */ 10495d24bcf1STomer Tayar switch (out_params.load_code) { 10505d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_ENGINE: 10515d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_PORT: 10525d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_FUNCTION: 10535d24bcf1STomer Tayar if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 10545d24bcf1STomer Tayar out_params.drv_exists) { 10555d24bcf1STomer Tayar /* The role and fw/driver version match, but the PF is 10565d24bcf1STomer Tayar * already loaded and has not been unloaded gracefully. 10575d24bcf1STomer Tayar */ 10585d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10595d24bcf1STomer Tayar "PF is already loaded\n"); 10605d24bcf1STomer Tayar return -EINVAL; 10615d24bcf1STomer Tayar } 10625d24bcf1STomer Tayar break; 10635d24bcf1STomer Tayar default: 10645d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10655d24bcf1STomer Tayar "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 10665d24bcf1STomer Tayar out_params.load_code); 10675d24bcf1STomer Tayar return -EBUSY; 10685d24bcf1STomer Tayar } 10695d24bcf1STomer Tayar 10705d24bcf1STomer Tayar p_params->load_code = out_params.load_code; 1071fe56b9e6SYuval Mintz 1072fe56b9e6SYuval Mintz return 0; 1073fe56b9e6SYuval Mintz } 1074fe56b9e6SYuval Mintz 1075666db486STomer Tayar int qed_mcp_load_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1076666db486STomer Tayar { 1077666db486STomer Tayar u32 resp = 0, param = 0; 1078666db486STomer Tayar int rc; 1079666db486STomer Tayar 1080666db486STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp, 1081666db486STomer Tayar ¶m); 1082666db486STomer Tayar if (rc) { 1083666db486STomer Tayar DP_NOTICE(p_hwfn, 1084666db486STomer Tayar "Failed to send a LOAD_DONE command, rc = %d\n", rc); 1085666db486STomer Tayar return rc; 1086666db486STomer Tayar } 1087666db486STomer Tayar 1088666db486STomer Tayar /* Check if there is a DID mismatch between nvm-cfg/efuse */ 1089666db486STomer Tayar if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR) 1090666db486STomer Tayar DP_NOTICE(p_hwfn, 1091666db486STomer Tayar "warning: device configuration is not supported on this board type. The device may not function as expected.\n"); 1092666db486STomer Tayar 1093666db486STomer Tayar return 0; 1094666db486STomer Tayar } 1095666db486STomer Tayar 10961226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10971226337aSTomer Tayar { 1098eaa50fc5STomer Tayar struct qed_mcp_mb_params mb_params; 1099eaa50fc5STomer Tayar u32 wol_param; 11001226337aSTomer Tayar 11011226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 11021226337aSTomer Tayar case QED_OV_WOL_DISABLED: 11031226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 11041226337aSTomer Tayar break; 11051226337aSTomer Tayar case QED_OV_WOL_ENABLED: 11061226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 11071226337aSTomer Tayar break; 11081226337aSTomer Tayar default: 11091226337aSTomer Tayar DP_NOTICE(p_hwfn, 11101226337aSTomer Tayar "Unknown WoL configuration %02x\n", 11111226337aSTomer Tayar p_hwfn->cdev->wol_config); 11121226337aSTomer Tayar /* Fallthrough */ 11131226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 11141226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 11151226337aSTomer Tayar } 11161226337aSTomer Tayar 1117eaa50fc5STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 1118eaa50fc5STomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ; 1119eaa50fc5STomer Tayar mb_params.param = wol_param; 1120b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 1121eaa50fc5STomer Tayar 1122eaa50fc5STomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11231226337aSTomer Tayar } 11241226337aSTomer Tayar 11251226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11261226337aSTomer Tayar { 11271226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 11281226337aSTomer Tayar struct mcp_mac wol_mac; 11291226337aSTomer Tayar 11301226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 11311226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 11321226337aSTomer Tayar 11331226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 11341226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 11351226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 11361226337aSTomer Tayar 11371226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 11381226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 11391226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 11401226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 11411226337aSTomer Tayar 11421226337aSTomer Tayar DP_VERBOSE(p_hwfn, 11431226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 11441226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 11451226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 11461226337aSTomer Tayar 11471226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 11481226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 11491226337aSTomer Tayar } 11501226337aSTomer Tayar 11511226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11521226337aSTomer Tayar } 11531226337aSTomer Tayar 11540b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 11550b55e27dSYuval Mintz struct qed_ptt *p_ptt) 11560b55e27dSYuval Mintz { 11570b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11580b55e27dSYuval Mintz PUBLIC_PATH); 11590b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 11600b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 11610b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 11620b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 11630b55e27dSYuval Mintz int i; 11640b55e27dSYuval Mintz 11650b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 11660b55e27dSYuval Mintz QED_MSG_SP, 11670b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 11680b55e27dSYuval Mintz mfw_path_offsize, path_addr); 11690b55e27dSYuval Mintz 11700b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 11710b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 11720b55e27dSYuval Mintz path_addr + 11730b55e27dSYuval Mintz offsetof(struct public_path, 11740b55e27dSYuval Mintz mcp_vf_disabled) + 11750b55e27dSYuval Mintz sizeof(u32) * i); 11760b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11770b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 11780b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 11790b55e27dSYuval Mintz } 11800b55e27dSYuval Mintz 11810b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 11820b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 11830b55e27dSYuval Mintz } 11840b55e27dSYuval Mintz 11850b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 11860b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 11870b55e27dSYuval Mintz { 11880b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11890b55e27dSYuval Mintz PUBLIC_FUNC); 11900b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 11910b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 11920b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 11930b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 11940b55e27dSYuval Mintz int rc; 11950b55e27dSYuval Mintz int i; 11960b55e27dSYuval Mintz 11970b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11980b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11990b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 12000b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 12010b55e27dSYuval Mintz 12020b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 12030b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 12042f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 12052f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 12060b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 12070b55e27dSYuval Mintz if (rc) { 12080b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 12090b55e27dSYuval Mintz return -EBUSY; 12100b55e27dSYuval Mintz } 12110b55e27dSYuval Mintz 12120b55e27dSYuval Mintz /* Clear the ACK bits */ 12130b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 12140b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 12150b55e27dSYuval Mintz func_addr + 12160b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 12170b55e27dSYuval Mintz i * sizeof(u32), 0); 12180b55e27dSYuval Mintz 12190b55e27dSYuval Mintz return rc; 12200b55e27dSYuval Mintz } 12210b55e27dSYuval Mintz 1222334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1223334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 1224334c03b5SZvi Nachmani { 1225334c03b5SZvi Nachmani u32 transceiver_state; 1226334c03b5SZvi Nachmani 1227334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 1228334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 1229334c03b5SZvi Nachmani offsetof(struct public_port, 1230334c03b5SZvi Nachmani transceiver_data)); 1231334c03b5SZvi Nachmani 1232334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 1233334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 1234334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1235334c03b5SZvi Nachmani transceiver_state, 1236334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 12371a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 1238334c03b5SZvi Nachmani 1239334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 1240351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 1241334c03b5SZvi Nachmani 1242351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1243334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1244334c03b5SZvi Nachmani else 1245334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1246334c03b5SZvi Nachmani } 1247334c03b5SZvi Nachmani 1248645874e5SSudarsana Reddy Kalluru static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1249645874e5SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1250645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_state *p_link) 1251645874e5SSudarsana Reddy Kalluru { 1252645874e5SSudarsana Reddy Kalluru u32 eee_status, val; 1253645874e5SSudarsana Reddy Kalluru 1254645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps = 0; 1255645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps = 0; 1256645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, 1257645874e5SSudarsana Reddy Kalluru p_ptt, 1258645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 1259645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 1260645874e5SSudarsana Reddy Kalluru p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1261645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1262645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1263645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1264645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1265645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1266645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1267645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1268645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1269645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1270645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1271645874e5SSudarsana Reddy Kalluru } 1272645874e5SSudarsana Reddy Kalluru 1273e40a826aSSudarsana Reddy Kalluru static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 1274e40a826aSSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1275e40a826aSSudarsana Reddy Kalluru struct public_func *p_data, int pfid) 1276e40a826aSSudarsana Reddy Kalluru { 1277e40a826aSSudarsana Reddy Kalluru u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1278e40a826aSSudarsana Reddy Kalluru PUBLIC_FUNC); 1279e40a826aSSudarsana Reddy Kalluru u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1280e40a826aSSudarsana Reddy Kalluru u32 func_addr; 1281e40a826aSSudarsana Reddy Kalluru u32 i, size; 1282e40a826aSSudarsana Reddy Kalluru 1283e40a826aSSudarsana Reddy Kalluru func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 1284e40a826aSSudarsana Reddy Kalluru memset(p_data, 0, sizeof(*p_data)); 1285e40a826aSSudarsana Reddy Kalluru 1286e40a826aSSudarsana Reddy Kalluru size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 1287e40a826aSSudarsana Reddy Kalluru for (i = 0; i < size / sizeof(u32); i++) 1288e40a826aSSudarsana Reddy Kalluru ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 1289e40a826aSSudarsana Reddy Kalluru func_addr + (i << 2)); 1290e40a826aSSudarsana Reddy Kalluru return size; 1291e40a826aSSudarsana Reddy Kalluru } 1292e40a826aSSudarsana Reddy Kalluru 1293e40a826aSSudarsana Reddy Kalluru static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 1294e40a826aSSudarsana Reddy Kalluru struct public_func *p_shmem_info) 1295e40a826aSSudarsana Reddy Kalluru { 1296e40a826aSSudarsana Reddy Kalluru struct qed_mcp_function_info *p_info; 1297e40a826aSSudarsana Reddy Kalluru 1298e40a826aSSudarsana Reddy Kalluru p_info = &p_hwfn->mcp_info->func_info; 1299e40a826aSSudarsana Reddy Kalluru 1300e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = QED_MFW_GET_FIELD(p_shmem_info->config, 1301e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MIN_BW); 1302e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 1303e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1304e40a826aSSudarsana Reddy Kalluru "bandwidth minimum out of bounds [%02x]. Set to 1\n", 1305e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min); 1306e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = 1; 1307e40a826aSSudarsana Reddy Kalluru } 1308e40a826aSSudarsana Reddy Kalluru 1309e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = QED_MFW_GET_FIELD(p_shmem_info->config, 1310e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MAX_BW); 1311e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 1312e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1313e40a826aSSudarsana Reddy Kalluru "bandwidth maximum out of bounds [%02x]. Set to 100\n", 1314e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max); 1315e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = 100; 1316e40a826aSSudarsana Reddy Kalluru } 1317e40a826aSSudarsana Reddy Kalluru } 1318e40a826aSSudarsana Reddy Kalluru 1319cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 13201a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 1321cc875c2eSYuval Mintz { 1322cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 1323a64b02d5SManish Chopra u8 max_bw, min_bw; 1324cc875c2eSYuval Mintz u32 status = 0; 1325cc875c2eSYuval Mintz 132665ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 132765ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 132865ed2ffdSMintz, Yuval 1329cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 1330cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 1331cc875c2eSYuval Mintz if (!b_reset) { 1332cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 1333cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 1334cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 1335cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1336cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1337cc875c2eSYuval Mintz status, 1338cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 13391a635e48SYuval Mintz offsetof(struct public_port, link_status))); 1340cc875c2eSYuval Mintz } else { 1341cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1342cc875c2eSYuval Mintz "Resetting link indications\n"); 134365ed2ffdSMintz, Yuval goto out; 1344cc875c2eSYuval Mintz } 1345cc875c2eSYuval Mintz 1346e40a826aSSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) { 1347e40a826aSSudarsana Reddy Kalluru /* Link indication with modern MFW arrives as per-PF 1348e40a826aSSudarsana Reddy Kalluru * indication. 1349e40a826aSSudarsana Reddy Kalluru */ 1350e40a826aSSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & 1351e40a826aSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_VLINK) { 1352e40a826aSSudarsana Reddy Kalluru struct public_func shmem_info; 1353e40a826aSSudarsana Reddy Kalluru 1354e40a826aSSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 1355e40a826aSSudarsana Reddy Kalluru MCP_PF_ID(p_hwfn)); 1356e40a826aSSudarsana Reddy Kalluru p_link->link_up = !!(shmem_info.status & 1357e40a826aSSudarsana Reddy Kalluru FUNC_STATUS_VIRTUAL_LINK_UP); 1358e40a826aSSudarsana Reddy Kalluru qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1359e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1360e40a826aSSudarsana Reddy Kalluru "Virtual link_up = %d\n", p_link->link_up); 1361e40a826aSSudarsana Reddy Kalluru } else { 1362cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1363e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1364e40a826aSSudarsana Reddy Kalluru "Physical link_up = %d\n", p_link->link_up); 1365e40a826aSSudarsana Reddy Kalluru } 1366e40a826aSSudarsana Reddy Kalluru } else { 1367fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 1368e40a826aSSudarsana Reddy Kalluru } 1369cc875c2eSYuval Mintz 1370cc875c2eSYuval Mintz p_link->full_duplex = true; 1371cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1372cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1373cc875c2eSYuval Mintz p_link->speed = 100000; 1374cc875c2eSYuval Mintz break; 1375cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1376cc875c2eSYuval Mintz p_link->speed = 50000; 1377cc875c2eSYuval Mintz break; 1378cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1379cc875c2eSYuval Mintz p_link->speed = 40000; 1380cc875c2eSYuval Mintz break; 1381cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1382cc875c2eSYuval Mintz p_link->speed = 25000; 1383cc875c2eSYuval Mintz break; 1384cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1385cc875c2eSYuval Mintz p_link->speed = 20000; 1386cc875c2eSYuval Mintz break; 1387cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1388cc875c2eSYuval Mintz p_link->speed = 10000; 1389cc875c2eSYuval Mintz break; 1390cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1391cc875c2eSYuval Mintz p_link->full_duplex = false; 1392cc875c2eSYuval Mintz /* Fall-through */ 1393cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1394cc875c2eSYuval Mintz p_link->speed = 1000; 1395cc875c2eSYuval Mintz break; 1396cc875c2eSYuval Mintz default: 1397cc875c2eSYuval Mintz p_link->speed = 0; 139858874c7bSSudarsana Reddy Kalluru p_link->link_up = 0; 1399cc875c2eSYuval Mintz } 1400cc875c2eSYuval Mintz 14014b01e519SManish Chopra if (p_link->link_up && p_link->speed) 14024b01e519SManish Chopra p_link->line_speed = p_link->speed; 14034b01e519SManish Chopra else 14044b01e519SManish Chopra p_link->line_speed = 0; 14054b01e519SManish Chopra 14064b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1407a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 14084b01e519SManish Chopra 1409a64b02d5SManish Chopra /* Max bandwidth configuration */ 14104b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1411cc875c2eSYuval Mintz 1412a64b02d5SManish Chopra /* Min bandwidth configuration */ 1413a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 14146f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 14156f437d43SMintz, Yuval p_link->min_pf_rate); 1416a64b02d5SManish Chopra 1417cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1418cc875c2eSYuval Mintz p_link->an_complete = !!(status & 1419cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1420cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 1421cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 1422cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1423cc875c2eSYuval Mintz 1424cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1425cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1426cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 1427cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1428cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1429cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 1430cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1431cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1432cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 1433cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1434cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1435cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 1436cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1437054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1438054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 1439054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 1440cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1441cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 1442cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1443cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1444cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 1445cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1446cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1447cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 1448cc875c2eSYuval Mintz 1449cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 1450cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1451cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 1452cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1453cc875c2eSYuval Mintz 1454cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1455cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1456cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1457cc875c2eSYuval Mintz break; 1458cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1459cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1460cc875c2eSYuval Mintz break; 1461cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1462cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1463cc875c2eSYuval Mintz break; 1464cc875c2eSYuval Mintz default: 1465cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 1466cc875c2eSYuval Mintz } 1467cc875c2eSYuval Mintz 1468cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1469cc875c2eSYuval Mintz 1470645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1471645874e5SSudarsana Reddy Kalluru qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1472645874e5SSudarsana Reddy Kalluru 1473706d0891SRahul Verma qed_link_update(p_hwfn, p_ptt); 147465ed2ffdSMintz, Yuval out: 147565ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1476cc875c2eSYuval Mintz } 1477cc875c2eSYuval Mintz 1478351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1479cc875c2eSYuval Mintz { 1480cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 14815529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 14822f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 1483cc875c2eSYuval Mintz int rc = 0; 14845529bad9STomer Tayar u32 cmd; 1485cc875c2eSYuval Mintz 1486cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 14872f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 1488cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1489cc875c2eSYuval Mintz if (!params->speed.autoneg) 14902f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 14912f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 14922f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 14932f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 14942f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 14952f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 14964ad95a93SSudarsana Reddy Kalluru 14974ad95a93SSudarsana Reddy Kalluru /* There are MFWs that share this capability regardless of whether 14984ad95a93SSudarsana Reddy Kalluru * this is feasible or not. And given that at the very least adv_caps 14994ad95a93SSudarsana Reddy Kalluru * would be set internally by qed, we want to make sure LFA would 15004ad95a93SSudarsana Reddy Kalluru * still work. 15014ad95a93SSudarsana Reddy Kalluru */ 15024ad95a93SSudarsana Reddy Kalluru if ((p_hwfn->mcp_info->capabilities & 15034ad95a93SSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1504645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1505645874e5SSudarsana Reddy Kalluru if (params->eee.tx_lpi_enable) 1506645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1507645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_1G_ADV) 1508645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1509645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_10G_ADV) 1510645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1511645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1512645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_OFFSET) & 1513645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_MASK; 1514645874e5SSudarsana Reddy Kalluru } 1515cc875c2eSYuval Mintz 1516fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 1517fc916ff2SSudarsana Reddy Kalluru 1518cc875c2eSYuval Mintz if (b_up) { 1519cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1520cc875c2eSYuval Mintz "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 15212f67af8cSTomer Tayar phy_cfg.speed, 15222f67af8cSTomer Tayar phy_cfg.pause, 15232f67af8cSTomer Tayar phy_cfg.adv_speed, 15242f67af8cSTomer Tayar phy_cfg.loopback_mode, 15252f67af8cSTomer Tayar phy_cfg.feature_config_flags); 1526cc875c2eSYuval Mintz } else { 1527cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1528cc875c2eSYuval Mintz "Resetting link\n"); 1529cc875c2eSYuval Mintz } 1530cc875c2eSYuval Mintz 15315529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 15325529bad9STomer Tayar mb_params.cmd = cmd; 15332f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 15342f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 15355529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1536cc875c2eSYuval Mintz 1537cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 1538cc875c2eSYuval Mintz if (rc) { 1539cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1540cc875c2eSYuval Mintz return rc; 1541cc875c2eSYuval Mintz } 1542cc875c2eSYuval Mintz 154365ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 154465ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 154565ed2ffdSMintz, Yuval * an attention. 154665ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 154765ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 154865ed2ffdSMintz, Yuval */ 154965ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1550cc875c2eSYuval Mintz 1551cc875c2eSYuval Mintz return 0; 1552cc875c2eSYuval Mintz } 1553cc875c2eSYuval Mintz 155464515dc8STomer Tayar u32 qed_get_process_kill_counter(struct qed_hwfn *p_hwfn, 155564515dc8STomer Tayar struct qed_ptt *p_ptt) 155664515dc8STomer Tayar { 155764515dc8STomer Tayar u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt; 155864515dc8STomer Tayar 155964515dc8STomer Tayar if (IS_VF(p_hwfn->cdev)) 156064515dc8STomer Tayar return -EINVAL; 156164515dc8STomer Tayar 156264515dc8STomer Tayar path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 156364515dc8STomer Tayar PUBLIC_PATH); 156464515dc8STomer Tayar path_offsize = qed_rd(p_hwfn, p_ptt, path_offsize_addr); 156564515dc8STomer Tayar path_addr = SECTION_ADDR(path_offsize, QED_PATH_ID(p_hwfn)); 156664515dc8STomer Tayar 156764515dc8STomer Tayar proc_kill_cnt = qed_rd(p_hwfn, p_ptt, 156864515dc8STomer Tayar path_addr + 156964515dc8STomer Tayar offsetof(struct public_path, process_kill)) & 157064515dc8STomer Tayar PROCESS_KILL_COUNTER_MASK; 157164515dc8STomer Tayar 157264515dc8STomer Tayar return proc_kill_cnt; 157364515dc8STomer Tayar } 157464515dc8STomer Tayar 157564515dc8STomer Tayar static void qed_mcp_handle_process_kill(struct qed_hwfn *p_hwfn, 157664515dc8STomer Tayar struct qed_ptt *p_ptt) 157764515dc8STomer Tayar { 157864515dc8STomer Tayar struct qed_dev *cdev = p_hwfn->cdev; 157964515dc8STomer Tayar u32 proc_kill_cnt; 158064515dc8STomer Tayar 158164515dc8STomer Tayar /* Prevent possible attentions/interrupts during the recovery handling 158264515dc8STomer Tayar * and till its load phase, during which they will be re-enabled. 158364515dc8STomer Tayar */ 158464515dc8STomer Tayar qed_int_igu_disable_int(p_hwfn, p_ptt); 158564515dc8STomer Tayar 158664515dc8STomer Tayar DP_NOTICE(p_hwfn, "Received a process kill indication\n"); 158764515dc8STomer Tayar 158864515dc8STomer Tayar /* The following operations should be done once, and thus in CMT mode 158964515dc8STomer Tayar * are carried out by only the first HW function. 159064515dc8STomer Tayar */ 159164515dc8STomer Tayar if (p_hwfn != QED_LEADING_HWFN(cdev)) 159264515dc8STomer Tayar return; 159364515dc8STomer Tayar 159464515dc8STomer Tayar if (cdev->recov_in_prog) { 159564515dc8STomer Tayar DP_NOTICE(p_hwfn, 159664515dc8STomer Tayar "Ignoring the indication since a recovery process is already in progress\n"); 159764515dc8STomer Tayar return; 159864515dc8STomer Tayar } 159964515dc8STomer Tayar 160064515dc8STomer Tayar cdev->recov_in_prog = true; 160164515dc8STomer Tayar 160264515dc8STomer Tayar proc_kill_cnt = qed_get_process_kill_counter(p_hwfn, p_ptt); 160364515dc8STomer Tayar DP_NOTICE(p_hwfn, "Process kill counter: %d\n", proc_kill_cnt); 160464515dc8STomer Tayar 160564515dc8STomer Tayar qed_schedule_recovery_handler(p_hwfn); 160664515dc8STomer Tayar } 160764515dc8STomer Tayar 16086c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 16096c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 16106c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 16116c754246SSudarsana Reddy Kalluru { 16126c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 16136c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 16146c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 16156c754246SSudarsana Reddy Kalluru u32 hsi_param; 16166c754246SSudarsana Reddy Kalluru 16176c754246SSudarsana Reddy Kalluru switch (type) { 16186c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 16196c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 16206c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 16216c754246SSudarsana Reddy Kalluru break; 16226c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 16236c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 16246c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 16256c754246SSudarsana Reddy Kalluru break; 16266c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 16276c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 16286c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 16296c754246SSudarsana Reddy Kalluru break; 16306c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 16316c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 16326c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 16336c754246SSudarsana Reddy Kalluru break; 16346c754246SSudarsana Reddy Kalluru default: 16356c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 16366c754246SSudarsana Reddy Kalluru return; 16376c754246SSudarsana Reddy Kalluru } 16386c754246SSudarsana Reddy Kalluru 16396c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 16406c754246SSudarsana Reddy Kalluru 16416c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 16426c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 16436c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 16442f67af8cSTomer Tayar mb_params.p_data_src = &stats; 16452f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 16466c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 16476c754246SSudarsana Reddy Kalluru } 16486c754246SSudarsana Reddy Kalluru 16491a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 16504b01e519SManish Chopra { 16514b01e519SManish Chopra struct qed_mcp_function_info *p_info; 16524b01e519SManish Chopra struct public_func shmem_info; 16534b01e519SManish Chopra u32 resp = 0, param = 0; 16544b01e519SManish Chopra 16551a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 16564b01e519SManish Chopra 16574b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 16584b01e519SManish Chopra 16594b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 16604b01e519SManish Chopra 1661a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 16624b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 16634b01e519SManish Chopra 16644b01e519SManish Chopra /* Acknowledge the MFW */ 16654b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 16664b01e519SManish Chopra ¶m); 16674b01e519SManish Chopra } 16684b01e519SManish Chopra 16692a351fd9SMintz, Yuval static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 16702a351fd9SMintz, Yuval { 16712a351fd9SMintz, Yuval struct public_func shmem_info; 16722a351fd9SMintz, Yuval u32 resp = 0, param = 0; 16732a351fd9SMintz, Yuval 16742a351fd9SMintz, Yuval qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 16752a351fd9SMintz, Yuval 16762a351fd9SMintz, Yuval p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 16772a351fd9SMintz, Yuval FUNC_MF_CFG_OV_STAG_MASK; 16782a351fd9SMintz, Yuval p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 16797e3e375cSSudarsana Reddy Kalluru if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) { 16807e3e375cSSudarsana Reddy Kalluru if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) { 16817e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 16827e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 16837e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1); 16847e3e375cSSudarsana Reddy Kalluru 16857e3e375cSSudarsana Reddy Kalluru /* Configure DB to add external vlan to EDPM packets */ 16867e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1); 16877e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 16887e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 16897e3e375cSSudarsana Reddy Kalluru } else { 16907e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0); 16917e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0); 16927e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0); 16937e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0); 16947e3e375cSSudarsana Reddy Kalluru } 16957e3e375cSSudarsana Reddy Kalluru 16962a351fd9SMintz, Yuval qed_sp_pf_update_stag(p_hwfn); 16972a351fd9SMintz, Yuval } 16982a351fd9SMintz, Yuval 16997e3e375cSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan = %d hw_mode = 0x%x\n", 17007e3e375cSSudarsana Reddy Kalluru p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode); 17017e3e375cSSudarsana Reddy Kalluru 17022a351fd9SMintz, Yuval /* Acknowledge the MFW */ 17032a351fd9SMintz, Yuval qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 17042a351fd9SMintz, Yuval &resp, ¶m); 17052a351fd9SMintz, Yuval } 17062a351fd9SMintz, Yuval 1707cac6f691SSudarsana Reddy Kalluru void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1708cac6f691SSudarsana Reddy Kalluru { 1709cac6f691SSudarsana Reddy Kalluru struct public_func shmem_info; 1710cac6f691SSudarsana Reddy Kalluru u32 port_cfg, val; 1711cac6f691SSudarsana Reddy Kalluru 1712cac6f691SSudarsana Reddy Kalluru if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1713cac6f691SSudarsana Reddy Kalluru return; 1714cac6f691SSudarsana Reddy Kalluru 1715cac6f691SSudarsana Reddy Kalluru memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1716cac6f691SSudarsana Reddy Kalluru port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1717cac6f691SSudarsana Reddy Kalluru offsetof(struct public_port, oem_cfg_port)); 1718cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1719cac6f691SSudarsana Reddy Kalluru OEM_CFG_CHANNEL_TYPE_OFFSET; 1720cac6f691SSudarsana Reddy Kalluru if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1721ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1722ec036eb9SSudarsana Reddy Kalluru "Incorrect UFP Channel type %d port_id 0x%02x\n", 1723ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1724cac6f691SSudarsana Reddy Kalluru 1725cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1726cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_SCHED_TYPE_ETS) { 1727cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1728cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1729cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1730cac6f691SSudarsana Reddy Kalluru } else { 1731cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1732ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1733ec036eb9SSudarsana Reddy Kalluru "Unknown UFP scheduling mode %d port_id 0x%02x\n", 1734ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1735cac6f691SSudarsana Reddy Kalluru } 1736cac6f691SSudarsana Reddy Kalluru 1737cac6f691SSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1738b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1739b5fabb08SSudarsana Reddy Kalluru OEM_CFG_FUNC_TC_OFFSET; 1740cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.tc = (u8)val; 1741b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1742cac6f691SSudarsana Reddy Kalluru OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1743cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1744cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1745cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1746cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1747cac6f691SSudarsana Reddy Kalluru } else { 1748cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1749ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1750ec036eb9SSudarsana Reddy Kalluru "Unknown Host priority control %d port_id 0x%02x\n", 1751ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1752cac6f691SSudarsana Reddy Kalluru } 1753cac6f691SSudarsana Reddy Kalluru 1754cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1755ec036eb9SSudarsana Reddy Kalluru "UFP shmem config: mode = %d tc = %d pri_type = %d port_id 0x%02x\n", 1756ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc, 1757ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type, MFW_PORT(p_hwfn)); 1758cac6f691SSudarsana Reddy Kalluru } 1759cac6f691SSudarsana Reddy Kalluru 1760cac6f691SSudarsana Reddy Kalluru static int 1761cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1762cac6f691SSudarsana Reddy Kalluru { 1763cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1764cac6f691SSudarsana Reddy Kalluru 1765cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1766cac6f691SSudarsana Reddy Kalluru p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1767c4259ddaSDenis Bolotin qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1768c4259ddaSDenis Bolotin p_hwfn->ufp_info.tc); 1769cac6f691SSudarsana Reddy Kalluru 1770cac6f691SSudarsana Reddy Kalluru qed_qm_reconf(p_hwfn, p_ptt); 1771cac6f691SSudarsana Reddy Kalluru } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1772cac6f691SSudarsana Reddy Kalluru /* Merge UFP TC with the dcbx TC data */ 1773cac6f691SSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1774cac6f691SSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 1775cac6f691SSudarsana Reddy Kalluru } else { 1776cac6f691SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1777cac6f691SSudarsana Reddy Kalluru return -EINVAL; 1778cac6f691SSudarsana Reddy Kalluru } 1779cac6f691SSudarsana Reddy Kalluru 1780cac6f691SSudarsana Reddy Kalluru /* update storm FW with negotiation results */ 1781cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_ufp(p_hwfn); 1782cac6f691SSudarsana Reddy Kalluru 1783cac6f691SSudarsana Reddy Kalluru /* update stag pcp value */ 1784cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_stag(p_hwfn); 1785cac6f691SSudarsana Reddy Kalluru 1786cac6f691SSudarsana Reddy Kalluru return 0; 1787cac6f691SSudarsana Reddy Kalluru } 1788cac6f691SSudarsana Reddy Kalluru 1789cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1790cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1791cc875c2eSYuval Mintz { 1792cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 1793cc875c2eSYuval Mintz int rc = 0; 1794cc875c2eSYuval Mintz bool found = false; 1795cc875c2eSYuval Mintz u16 i; 1796cc875c2eSYuval Mintz 1797cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1798cc875c2eSYuval Mintz 1799cc875c2eSYuval Mintz /* Read Messages from MFW */ 1800cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 1801cc875c2eSYuval Mintz 1802cc875c2eSYuval Mintz /* Compare current messages to old ones */ 1803cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 1804cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1805cc875c2eSYuval Mintz continue; 1806cc875c2eSYuval Mintz 1807cc875c2eSYuval Mintz found = true; 1808cc875c2eSYuval Mintz 1809cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1810cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1811cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1812cc875c2eSYuval Mintz 1813cc875c2eSYuval Mintz switch (i) { 1814cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 1815cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1816cc875c2eSYuval Mintz break; 18170b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 18180b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 18190b55e27dSYuval Mintz break; 182039651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 182139651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 182239651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 182339651abdSSudarsana Reddy Kalluru break; 182439651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 182539651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 182639651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 182739651abdSSudarsana Reddy Kalluru break; 182839651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 182939651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 183039651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 183139651abdSSudarsana Reddy Kalluru break; 1832cac6f691SSudarsana Reddy Kalluru case MFW_DRV_MSG_OEM_CFG_UPDATE: 1833cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 1834cac6f691SSudarsana Reddy Kalluru break; 1835334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1836334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1837334c03b5SZvi Nachmani break; 183864515dc8STomer Tayar case MFW_DRV_MSG_ERROR_RECOVERY: 183964515dc8STomer Tayar qed_mcp_handle_process_kill(p_hwfn, p_ptt); 184064515dc8STomer Tayar break; 18416c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 18426c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 18436c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 18446c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 18456c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 18466c754246SSudarsana Reddy Kalluru break; 18474b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 18484b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 18494b01e519SManish Chopra break; 18502a351fd9SMintz, Yuval case MFW_DRV_MSG_S_TAG_UPDATE: 18512a351fd9SMintz, Yuval qed_mcp_update_stag(p_hwfn, p_ptt); 18522a351fd9SMintz, Yuval break; 185359ccf86fSSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_TLV_REQ: 185459ccf86fSSudarsana Reddy Kalluru qed_mfw_tlv_req(p_hwfn); 18552a351fd9SMintz, Yuval break; 1856cc875c2eSYuval Mintz default: 185739815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1858cc875c2eSYuval Mintz rc = -EINVAL; 1859cc875c2eSYuval Mintz } 1860cc875c2eSYuval Mintz } 1861cc875c2eSYuval Mintz 1862cc875c2eSYuval Mintz /* ACK everything */ 1863cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1864cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1865cc875c2eSYuval Mintz 1866cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 1867cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 1868cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 1869cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1870cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 1871cc875c2eSYuval Mintz (__force u32)val); 1872cc875c2eSYuval Mintz } 1873cc875c2eSYuval Mintz 1874cc875c2eSYuval Mintz if (!found) { 1875cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 1876cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 1877cc875c2eSYuval Mintz rc = -EINVAL; 1878cc875c2eSYuval Mintz } 1879cc875c2eSYuval Mintz 1880cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 1881cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1882cc875c2eSYuval Mintz 1883cc875c2eSYuval Mintz return rc; 1884cc875c2eSYuval Mintz } 1885cc875c2eSYuval Mintz 18861408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 18871408cc1fSYuval Mintz struct qed_ptt *p_ptt, 18881408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 1889fe56b9e6SYuval Mintz { 1890fe56b9e6SYuval Mintz u32 global_offsize; 1891fe56b9e6SYuval Mintz 18921408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 18931408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 18941408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 18951408cc1fSYuval Mintz 18961408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 18971408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 18981408cc1fSYuval Mintz return 0; 18991408cc1fSYuval Mintz } else { 19001408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 19011408cc1fSYuval Mintz QED_MSG_IOV, 19021408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 19031408cc1fSYuval Mintz return -EINVAL; 19041408cc1fSYuval Mintz } 19051408cc1fSYuval Mintz } 1906fe56b9e6SYuval Mintz 1907fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 19081408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 19091408cc1fSYuval Mintz mcp_info->public_base, 1910fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 19111408cc1fSYuval Mintz *p_mfw_ver = 19121408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 19131408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 19141408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 1915fe56b9e6SYuval Mintz 19161408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 19171408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 19181408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 19191408cc1fSYuval Mintz offsetof(struct public_global, 19201408cc1fSYuval Mintz running_bundle_id)); 19211408cc1fSYuval Mintz } 1922fe56b9e6SYuval Mintz 1923fe56b9e6SYuval Mintz return 0; 1924fe56b9e6SYuval Mintz } 1925fe56b9e6SYuval Mintz 1926ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 1927ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver) 1928ae33666aSTomer Tayar { 1929ae33666aSTomer Tayar u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 1930ae33666aSTomer Tayar 1931ae33666aSTomer Tayar if (IS_VF(p_hwfn->cdev)) 1932ae33666aSTomer Tayar return -EINVAL; 1933ae33666aSTomer Tayar 1934ae33666aSTomer Tayar /* Read the address of the nvm_cfg */ 1935ae33666aSTomer Tayar nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1936ae33666aSTomer Tayar if (!nvm_cfg_addr) { 1937ae33666aSTomer Tayar DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1938ae33666aSTomer Tayar return -EINVAL; 1939ae33666aSTomer Tayar } 1940ae33666aSTomer Tayar 1941ae33666aSTomer Tayar /* Read the offset of nvm_cfg1 */ 1942ae33666aSTomer Tayar nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1943ae33666aSTomer Tayar 1944ae33666aSTomer Tayar mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1945ae33666aSTomer Tayar offsetof(struct nvm_cfg1, glob) + 1946ae33666aSTomer Tayar offsetof(struct nvm_cfg1_glob, mbi_version); 1947ae33666aSTomer Tayar *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 1948ae33666aSTomer Tayar mbi_ver_addr) & 1949ae33666aSTomer Tayar (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 1950ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 1951ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 1952ae33666aSTomer Tayar 1953ae33666aSTomer Tayar return 0; 1954ae33666aSTomer Tayar } 1955ae33666aSTomer Tayar 1956706d0891SRahul Verma int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, 1957706d0891SRahul Verma struct qed_ptt *p_ptt, u32 *p_media_type) 1958cc875c2eSYuval Mintz { 1959c56a8be7SRahul Verma *p_media_type = MEDIA_UNSPECIFIED; 1960c56a8be7SRahul Verma 1961706d0891SRahul Verma if (IS_VF(p_hwfn->cdev)) 19621408cc1fSYuval Mintz return -EINVAL; 19631408cc1fSYuval Mintz 1964cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 1965cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1966cc875c2eSYuval Mintz return -EBUSY; 1967cc875c2eSYuval Mintz } 1968cc875c2eSYuval Mintz 1969706d0891SRahul Verma if (!p_ptt) { 1970cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 1971706d0891SRahul Verma return -EINVAL; 1972706d0891SRahul Verma } 1973cc875c2eSYuval Mintz 1974706d0891SRahul Verma *p_media_type = qed_rd(p_hwfn, p_ptt, 1975706d0891SRahul Verma p_hwfn->mcp_info->port_addr + 1976706d0891SRahul Verma offsetof(struct public_port, 1977706d0891SRahul Verma media_type)); 1978cc875c2eSYuval Mintz 1979cc875c2eSYuval Mintz return 0; 1980cc875c2eSYuval Mintz } 1981cc875c2eSYuval Mintz 1982c56a8be7SRahul Verma int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, 1983c56a8be7SRahul Verma struct qed_ptt *p_ptt, 1984c56a8be7SRahul Verma u32 *p_transceiver_state, 1985c56a8be7SRahul Verma u32 *p_transceiver_type) 1986c56a8be7SRahul Verma { 1987c56a8be7SRahul Verma u32 transceiver_info; 1988c56a8be7SRahul Verma 198968203a67SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_NONE; 199068203a67SRahul Verma *p_transceiver_state = ETH_TRANSCEIVER_STATE_UPDATING; 199168203a67SRahul Verma 1992c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 1993c56a8be7SRahul Verma return -EINVAL; 1994c56a8be7SRahul Verma 1995c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 1996c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1997c56a8be7SRahul Verma return -EBUSY; 1998c56a8be7SRahul Verma } 1999c56a8be7SRahul Verma 2000c56a8be7SRahul Verma transceiver_info = qed_rd(p_hwfn, p_ptt, 2001c56a8be7SRahul Verma p_hwfn->mcp_info->port_addr + 2002c56a8be7SRahul Verma offsetof(struct public_port, 2003c56a8be7SRahul Verma transceiver_data)); 2004c56a8be7SRahul Verma 2005c56a8be7SRahul Verma *p_transceiver_state = (transceiver_info & 2006c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_MASK) >> 2007c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_OFFSET; 2008c56a8be7SRahul Verma 2009c56a8be7SRahul Verma if (*p_transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 2010c56a8be7SRahul Verma *p_transceiver_type = (transceiver_info & 2011c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_MASK) >> 2012c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_OFFSET; 2013c56a8be7SRahul Verma else 2014c56a8be7SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_UNKNOWN; 2015c56a8be7SRahul Verma 2016c56a8be7SRahul Verma return 0; 2017c56a8be7SRahul Verma } 2018c56a8be7SRahul Verma static bool qed_is_transceiver_ready(u32 transceiver_state, 2019c56a8be7SRahul Verma u32 transceiver_type) 2020c56a8be7SRahul Verma { 2021c56a8be7SRahul Verma if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) && 2022c56a8be7SRahul Verma ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) && 2023c56a8be7SRahul Verma (transceiver_type != ETH_TRANSCEIVER_TYPE_NONE)) 2024c56a8be7SRahul Verma return true; 2025c56a8be7SRahul Verma 2026c56a8be7SRahul Verma return false; 2027c56a8be7SRahul Verma } 2028c56a8be7SRahul Verma 2029c56a8be7SRahul Verma int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, 2030c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_speed_mask) 2031c56a8be7SRahul Verma { 2032c56a8be7SRahul Verma u32 transceiver_type, transceiver_state; 203392619210SArnd Bergmann int ret; 2034c56a8be7SRahul Verma 203592619210SArnd Bergmann ret = qed_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state, 2036c56a8be7SRahul Verma &transceiver_type); 203792619210SArnd Bergmann if (ret) 203892619210SArnd Bergmann return ret; 2039c56a8be7SRahul Verma 2040c56a8be7SRahul Verma if (qed_is_transceiver_ready(transceiver_state, transceiver_type) == 2041c56a8be7SRahul Verma false) 2042c56a8be7SRahul Verma return -EINVAL; 2043c56a8be7SRahul Verma 2044c56a8be7SRahul Verma switch (transceiver_type) { 2045c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_LX: 2046c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_SX: 2047c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_PCC: 2048c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_ACC: 2049c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1000BASET: 2050c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2051c56a8be7SRahul Verma break; 2052c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_SR: 2053c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LR: 2054c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LRM: 2055c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ER: 2056c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_PCC: 2057c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ACC: 2058c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x10G: 2059c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2060c56a8be7SRahul Verma break; 2061c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_LR4: 2062c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_SR4: 2063c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR: 2064c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR: 2065c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2066c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2067c56a8be7SRahul Verma break; 2068c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_AOC: 2069c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_SR4: 2070c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_LR4: 2071c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ER4: 2072c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ACC: 2073c56a8be7SRahul Verma *p_speed_mask = 2074c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2075c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2076c56a8be7SRahul Verma break; 2077c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_SR: 2078c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_LR: 2079c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_AOC: 2080c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_S: 2081c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_M: 2082c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_L: 2083c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2084c56a8be7SRahul Verma break; 2085c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_N: 2086c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_S: 2087c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_L: 2088c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x25G_CR: 2089c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2090c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2091c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2092c56a8be7SRahul Verma break; 2093c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_CR4: 2094c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR: 2095c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2096c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2097c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2098c56a8be7SRahul Verma break; 2099c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_CR4: 2100c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR: 2101c56a8be7SRahul Verma *p_speed_mask = 2102c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2103c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G | 2104c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2105c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2106c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G | 2107c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2108c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2109c56a8be7SRahul Verma break; 2110c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR: 2111c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR: 2112c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC: 2113c56a8be7SRahul Verma *p_speed_mask = 2114c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2115c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2116c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2117c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2118c56a8be7SRahul Verma break; 2119c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_XLPPI: 2120c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 2121c56a8be7SRahul Verma break; 2122c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_BASET: 2123c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2124c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2125c56a8be7SRahul Verma break; 2126c56a8be7SRahul Verma default: 21271107a674SColin Ian King DP_INFO(p_hwfn, "Unknown transceiver type 0x%x\n", 2128c56a8be7SRahul Verma transceiver_type); 2129c56a8be7SRahul Verma *p_speed_mask = 0xff; 2130c56a8be7SRahul Verma break; 2131c56a8be7SRahul Verma } 2132c56a8be7SRahul Verma 2133c56a8be7SRahul Verma return 0; 2134c56a8be7SRahul Verma } 2135c56a8be7SRahul Verma 2136c56a8be7SRahul Verma int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, 2137c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_board_config) 2138c56a8be7SRahul Verma { 2139c56a8be7SRahul Verma u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr; 2140c56a8be7SRahul Verma 2141c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 2142c56a8be7SRahul Verma return -EINVAL; 2143c56a8be7SRahul Verma 2144c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 2145c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2146c56a8be7SRahul Verma return -EBUSY; 2147c56a8be7SRahul Verma } 2148c56a8be7SRahul Verma if (!p_ptt) { 2149c56a8be7SRahul Verma *p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED; 2150c56a8be7SRahul Verma return -EINVAL; 2151c56a8be7SRahul Verma } 2152c56a8be7SRahul Verma 2153c56a8be7SRahul Verma nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2154c56a8be7SRahul Verma nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2155c56a8be7SRahul Verma port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2156c56a8be7SRahul Verma offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2157c56a8be7SRahul Verma *p_board_config = qed_rd(p_hwfn, p_ptt, 2158c56a8be7SRahul Verma port_cfg_addr + 2159c56a8be7SRahul Verma offsetof(struct nvm_cfg1_port, 2160c56a8be7SRahul Verma board_cfg)); 2161c56a8be7SRahul Verma 2162c56a8be7SRahul Verma return 0; 2163c56a8be7SRahul Verma } 2164c56a8be7SRahul Verma 21656927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 21666927e826SMintz, Yuval static void 21676927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 21686927e826SMintz, Yuval enum qed_pci_personality *p_proto) 21696927e826SMintz, Yuval { 21706927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 21716927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 21726927e826SMintz, Yuval */ 21736927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 21746927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 21756927e826SMintz, Yuval else 21766927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 21776927e826SMintz, Yuval 21786927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 21796927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 21806927e826SMintz, Yuval (u32) *p_proto); 21816927e826SMintz, Yuval } 21826927e826SMintz, Yuval 21836927e826SMintz, Yuval static int 21846927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 21856927e826SMintz, Yuval struct qed_ptt *p_ptt, 21866927e826SMintz, Yuval enum qed_pci_personality *p_proto) 21876927e826SMintz, Yuval { 21886927e826SMintz, Yuval u32 resp = 0, param = 0; 21896927e826SMintz, Yuval int rc; 21906927e826SMintz, Yuval 21916927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 21926927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 21936927e826SMintz, Yuval if (rc) 21946927e826SMintz, Yuval return rc; 21956927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 21966927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 21976927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 21986927e826SMintz, Yuval resp); 21996927e826SMintz, Yuval return -EINVAL; 22006927e826SMintz, Yuval } 22016927e826SMintz, Yuval 22026927e826SMintz, Yuval switch (param) { 22036927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 22046927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 22056927e826SMintz, Yuval break; 22066927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 22076927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 22086927e826SMintz, Yuval break; 22096927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 2210e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_IWARP; 2211e0a8f9deSMichal Kalderon break; 2212e0a8f9deSMichal Kalderon case FW_MB_PARAM_GET_PF_RDMA_BOTH: 2213e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_RDMA; 2214e0a8f9deSMichal Kalderon break; 22156927e826SMintz, Yuval default: 22166927e826SMintz, Yuval DP_NOTICE(p_hwfn, 22176927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 22186927e826SMintz, Yuval param); 22196927e826SMintz, Yuval return -EINVAL; 22206927e826SMintz, Yuval } 22216927e826SMintz, Yuval 22226927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 22236927e826SMintz, Yuval NETIF_MSG_IFUP, 22246927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 22256927e826SMintz, Yuval (u32) *p_proto, resp, param); 22266927e826SMintz, Yuval return 0; 22276927e826SMintz, Yuval } 22286927e826SMintz, Yuval 2229fe56b9e6SYuval Mintz static int 2230fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 2231fe56b9e6SYuval Mintz struct public_func *p_info, 22326927e826SMintz, Yuval struct qed_ptt *p_ptt, 2233fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 2234fe56b9e6SYuval Mintz { 2235fe56b9e6SYuval Mintz int rc = 0; 2236fe56b9e6SYuval Mintz 2237fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 2238fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 22391fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 22401fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 22411fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 22426927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 2243fe56b9e6SYuval Mintz break; 2244c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 2245c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 2246c5ac9319SYuval Mintz break; 22471e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 22481e128c81SArun Easi *p_proto = QED_PCI_FCOE; 22491e128c81SArun Easi break; 2250c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 2251c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 22526927e826SMintz, Yuval /* Fallthrough */ 2253fe56b9e6SYuval Mintz default: 2254fe56b9e6SYuval Mintz rc = -EINVAL; 2255fe56b9e6SYuval Mintz } 2256fe56b9e6SYuval Mintz 2257fe56b9e6SYuval Mintz return rc; 2258fe56b9e6SYuval Mintz } 2259fe56b9e6SYuval Mintz 2260fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 2261fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 2262fe56b9e6SYuval Mintz { 2263fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 2264fe56b9e6SYuval Mintz struct public_func shmem_info; 2265fe56b9e6SYuval Mintz 22661a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 2267fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 2268fe56b9e6SYuval Mintz 2269fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 2270fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 2271fe56b9e6SYuval Mintz 22726927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 22736927e826SMintz, Yuval &info->protocol)) { 2274fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 2275fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 2276fe56b9e6SYuval Mintz return -EINVAL; 2277fe56b9e6SYuval Mintz } 2278fe56b9e6SYuval Mintz 22794b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 2280fe56b9e6SYuval Mintz 2281fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 2282fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 2283fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 2284fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 2285fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 2286fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 2287fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 228814d39648SMintz, Yuval 228914d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 229014d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 2291fe56b9e6SYuval Mintz } else { 2292fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 2293fe56b9e6SYuval Mintz } 2294fe56b9e6SYuval Mintz 229557796759SMintz, Yuval info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 229657796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 229757796759SMintz, Yuval info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 229857796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 2299fe56b9e6SYuval Mintz 2300fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 2301fe56b9e6SYuval Mintz 23020fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 23030fefbfbaSSudarsana Kalluru 230414d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 230514d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 230614d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 230714d39648SMintz, Yuval u32 resp = 0, param = 0; 230814d39648SMintz, Yuval int rc; 230914d39648SMintz, Yuval 231014d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 231114d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 231214d39648SMintz, Yuval if (rc) 231314d39648SMintz, Yuval return rc; 231414d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 231514d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 231614d39648SMintz, Yuval } 231714d39648SMintz, Yuval 2318fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 231914d39648SMintz, Yuval "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 2320fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 2321fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 2322fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 2323fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 232414d39648SMintz, Yuval info->wwn_port, info->wwn_node, 232514d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 2326fe56b9e6SYuval Mintz 2327fe56b9e6SYuval Mintz return 0; 2328fe56b9e6SYuval Mintz } 2329fe56b9e6SYuval Mintz 2330cc875c2eSYuval Mintz struct qed_mcp_link_params 2331cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 2332cc875c2eSYuval Mintz { 2333cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2334cc875c2eSYuval Mintz return NULL; 2335cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 2336cc875c2eSYuval Mintz } 2337cc875c2eSYuval Mintz 2338cc875c2eSYuval Mintz struct qed_mcp_link_state 2339cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 2340cc875c2eSYuval Mintz { 2341cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2342cc875c2eSYuval Mintz return NULL; 2343cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 2344cc875c2eSYuval Mintz } 2345cc875c2eSYuval Mintz 2346cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 2347cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 2348cc875c2eSYuval Mintz { 2349cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2350cc875c2eSYuval Mintz return NULL; 2351cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 2352cc875c2eSYuval Mintz } 2353cc875c2eSYuval Mintz 23541a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2355fe56b9e6SYuval Mintz { 2356fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 2357fe56b9e6SYuval Mintz int rc; 2358fe56b9e6SYuval Mintz 2359fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 23601a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 2361fe56b9e6SYuval Mintz 2362fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 23638f60bafeSYuval Mintz msleep(1020); 2364fe56b9e6SYuval Mintz 2365fe56b9e6SYuval Mintz return rc; 2366fe56b9e6SYuval Mintz } 2367fe56b9e6SYuval Mintz 2368cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 23691a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 2370cee4d264SManish Chopra { 2371cee4d264SManish Chopra u32 flash_size; 2372cee4d264SManish Chopra 23731408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 23741408cc1fSYuval Mintz return -EINVAL; 23751408cc1fSYuval Mintz 2376cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 2377cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 2378cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 2379cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 2380cee4d264SManish Chopra 2381cee4d264SManish Chopra *p_flash_size = flash_size; 2382cee4d264SManish Chopra 2383cee4d264SManish Chopra return 0; 2384cee4d264SManish Chopra } 2385cee4d264SManish Chopra 238664515dc8STomer Tayar int qed_start_recovery_process(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 238764515dc8STomer Tayar { 238864515dc8STomer Tayar struct qed_dev *cdev = p_hwfn->cdev; 238964515dc8STomer Tayar 239064515dc8STomer Tayar if (cdev->recov_in_prog) { 239164515dc8STomer Tayar DP_NOTICE(p_hwfn, 239264515dc8STomer Tayar "Avoid triggering a recovery since such a process is already in progress\n"); 239364515dc8STomer Tayar return -EAGAIN; 239464515dc8STomer Tayar } 239564515dc8STomer Tayar 239664515dc8STomer Tayar DP_NOTICE(p_hwfn, "Triggering a recovery process\n"); 239764515dc8STomer Tayar qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1); 239864515dc8STomer Tayar 239964515dc8STomer Tayar return 0; 240064515dc8STomer Tayar } 240164515dc8STomer Tayar 240264515dc8STomer Tayar #define QED_RECOVERY_PROLOG_SLEEP_MS 100 240364515dc8STomer Tayar 240464515dc8STomer Tayar int qed_recovery_prolog(struct qed_dev *cdev) 240564515dc8STomer Tayar { 240664515dc8STomer Tayar struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 240764515dc8STomer Tayar struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 240864515dc8STomer Tayar int rc; 240964515dc8STomer Tayar 241064515dc8STomer Tayar /* Allow ongoing PCIe transactions to complete */ 241164515dc8STomer Tayar msleep(QED_RECOVERY_PROLOG_SLEEP_MS); 241264515dc8STomer Tayar 241364515dc8STomer Tayar /* Clear the PF's internal FID_enable in the PXP */ 241464515dc8STomer Tayar rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false); 241564515dc8STomer Tayar if (rc) 241664515dc8STomer Tayar DP_NOTICE(p_hwfn, 241764515dc8STomer Tayar "qed_pglueb_set_pfid_enable() failed. rc = %d.\n", 241864515dc8STomer Tayar rc); 241964515dc8STomer Tayar 242064515dc8STomer Tayar return rc; 242164515dc8STomer Tayar } 242264515dc8STomer Tayar 242388072fd4SMintz, Yuval static int 242488072fd4SMintz, Yuval qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 24251408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 24261408cc1fSYuval Mintz { 24271408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 24281408cc1fSYuval Mintz int rc; 24291408cc1fSYuval Mintz 24301408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 24311408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 24321408cc1fSYuval Mintz return 0; 24331408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 24341408cc1fSYuval Mintz 24351408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 24361408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 24371408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 24381408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 24391408cc1fSYuval Mintz 24401408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 24411408cc1fSYuval Mintz &resp, &rc_param); 24421408cc1fSYuval Mintz 24431408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 24441408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 24451408cc1fSYuval Mintz rc = -EINVAL; 24461408cc1fSYuval Mintz } else { 24471408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 24481408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 24491408cc1fSYuval Mintz num, vf_id); 24501408cc1fSYuval Mintz } 24511408cc1fSYuval Mintz 24521408cc1fSYuval Mintz return rc; 24531408cc1fSYuval Mintz } 24541408cc1fSYuval Mintz 245588072fd4SMintz, Yuval static int 245688072fd4SMintz, Yuval qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 245788072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 num) 245888072fd4SMintz, Yuval { 245988072fd4SMintz, Yuval u32 resp = 0, param = num, rc_param = 0; 246088072fd4SMintz, Yuval int rc; 246188072fd4SMintz, Yuval 246288072fd4SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 246388072fd4SMintz, Yuval param, &resp, &rc_param); 246488072fd4SMintz, Yuval 246588072fd4SMintz, Yuval if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 246688072fd4SMintz, Yuval DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 246788072fd4SMintz, Yuval rc = -EINVAL; 246888072fd4SMintz, Yuval } else { 246988072fd4SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_IOV, 247088072fd4SMintz, Yuval "Requested 0x%02x MSI-x interrupts for VFs\n", num); 247188072fd4SMintz, Yuval } 247288072fd4SMintz, Yuval 247388072fd4SMintz, Yuval return rc; 247488072fd4SMintz, Yuval } 247588072fd4SMintz, Yuval 247688072fd4SMintz, Yuval int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 247788072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 vf_id, u8 num) 247888072fd4SMintz, Yuval { 247988072fd4SMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 248088072fd4SMintz, Yuval return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 248188072fd4SMintz, Yuval else 248288072fd4SMintz, Yuval return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 248388072fd4SMintz, Yuval } 248488072fd4SMintz, Yuval 2485fe56b9e6SYuval Mintz int 2486fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2487fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2488fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 2489fe56b9e6SYuval Mintz { 24905529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 24912f67af8cSTomer Tayar struct drv_version_stc drv_version; 24925529bad9STomer Tayar __be32 val; 24935529bad9STomer Tayar u32 i; 24945529bad9STomer Tayar int rc; 2495fe56b9e6SYuval Mintz 24962f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 24972f67af8cSTomer Tayar drv_version.version = p_ver->version; 249867a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 249967a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 25002f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2501fe56b9e6SYuval Mintz } 2502fe56b9e6SYuval Mintz 25035529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 25045529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 25052f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 25062f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 25075529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 25085529bad9STomer Tayar if (rc) 2509fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2510fe56b9e6SYuval Mintz 25115529bad9STomer Tayar return rc; 2512fe56b9e6SYuval Mintz } 251391420b83SSudarsana Kalluru 251476271809STomer Tayar /* A maximal 100 msec waiting time for the MCP to halt */ 251576271809STomer Tayar #define QED_MCP_HALT_SLEEP_MS 10 251676271809STomer Tayar #define QED_MCP_HALT_MAX_RETRIES 10 251776271809STomer Tayar 25184102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 25194102426fSTomer Tayar { 252076271809STomer Tayar u32 resp = 0, param = 0, cpu_state, cnt = 0; 25214102426fSTomer Tayar int rc; 25224102426fSTomer Tayar 25234102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 25244102426fSTomer Tayar ¶m); 252576271809STomer Tayar if (rc) { 25264102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 25274102426fSTomer Tayar return rc; 25284102426fSTomer Tayar } 25294102426fSTomer Tayar 253076271809STomer Tayar do { 253176271809STomer Tayar msleep(QED_MCP_HALT_SLEEP_MS); 253276271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 253376271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) 253476271809STomer Tayar break; 253576271809STomer Tayar } while (++cnt < QED_MCP_HALT_MAX_RETRIES); 253676271809STomer Tayar 253776271809STomer Tayar if (cnt == QED_MCP_HALT_MAX_RETRIES) { 253876271809STomer Tayar DP_NOTICE(p_hwfn, 253976271809STomer Tayar "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 254076271809STomer Tayar qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state); 254176271809STomer Tayar return -EBUSY; 254276271809STomer Tayar } 254376271809STomer Tayar 2544b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 2545b310974eSTomer Tayar 254676271809STomer Tayar return 0; 254776271809STomer Tayar } 254876271809STomer Tayar 254976271809STomer Tayar #define QED_MCP_RESUME_SLEEP_MS 10 255076271809STomer Tayar 25514102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 25524102426fSTomer Tayar { 255376271809STomer Tayar u32 cpu_mode, cpu_state; 25544102426fSTomer Tayar 25554102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 25564102426fSTomer Tayar 25574102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 255876271809STomer Tayar cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT; 255976271809STomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode); 256076271809STomer Tayar msleep(QED_MCP_RESUME_SLEEP_MS); 256176271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 25624102426fSTomer Tayar 256376271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) { 256476271809STomer Tayar DP_NOTICE(p_hwfn, 256576271809STomer Tayar "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 256676271809STomer Tayar cpu_mode, cpu_state); 256776271809STomer Tayar return -EBUSY; 256876271809STomer Tayar } 256976271809STomer Tayar 2570b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, false); 2571b310974eSTomer Tayar 257276271809STomer Tayar return 0; 25734102426fSTomer Tayar } 25744102426fSTomer Tayar 25750fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 25760fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 25770fefbfbaSSudarsana Kalluru enum qed_ov_client client) 25780fefbfbaSSudarsana Kalluru { 25790fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 25800fefbfbaSSudarsana Kalluru u32 drv_mb_param; 25810fefbfbaSSudarsana Kalluru int rc; 25820fefbfbaSSudarsana Kalluru 25830fefbfbaSSudarsana Kalluru switch (client) { 25840fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 25850fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 25860fefbfbaSSudarsana Kalluru break; 25870fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 25880fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 25890fefbfbaSSudarsana Kalluru break; 25900fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 25910fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 25920fefbfbaSSudarsana Kalluru break; 25930fefbfbaSSudarsana Kalluru default: 25940fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 25950fefbfbaSSudarsana Kalluru return -EINVAL; 25960fefbfbaSSudarsana Kalluru } 25970fefbfbaSSudarsana Kalluru 25980fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 25990fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 26000fefbfbaSSudarsana Kalluru if (rc) 26010fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 26020fefbfbaSSudarsana Kalluru 26030fefbfbaSSudarsana Kalluru return rc; 26040fefbfbaSSudarsana Kalluru } 26050fefbfbaSSudarsana Kalluru 26060fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 26070fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 26080fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 26090fefbfbaSSudarsana Kalluru { 26100fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 26110fefbfbaSSudarsana Kalluru u32 drv_mb_param; 26120fefbfbaSSudarsana Kalluru int rc; 26130fefbfbaSSudarsana Kalluru 26140fefbfbaSSudarsana Kalluru switch (drv_state) { 26150fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 26160fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 26170fefbfbaSSudarsana Kalluru break; 26180fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 26190fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 26200fefbfbaSSudarsana Kalluru break; 26210fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 26220fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 26230fefbfbaSSudarsana Kalluru break; 26240fefbfbaSSudarsana Kalluru default: 26250fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 26260fefbfbaSSudarsana Kalluru return -EINVAL; 26270fefbfbaSSudarsana Kalluru } 26280fefbfbaSSudarsana Kalluru 26290fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 26300fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 26310fefbfbaSSudarsana Kalluru if (rc) 26320fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 26330fefbfbaSSudarsana Kalluru 26340fefbfbaSSudarsana Kalluru return rc; 26350fefbfbaSSudarsana Kalluru } 26360fefbfbaSSudarsana Kalluru 26370fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 26380fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 26390fefbfbaSSudarsana Kalluru { 26400fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 26410fefbfbaSSudarsana Kalluru u32 drv_mb_param; 26420fefbfbaSSudarsana Kalluru int rc; 26430fefbfbaSSudarsana Kalluru 26440fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 26450fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 26460fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 26470fefbfbaSSudarsana Kalluru if (rc) 26480fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 26490fefbfbaSSudarsana Kalluru 26500fefbfbaSSudarsana Kalluru return rc; 26510fefbfbaSSudarsana Kalluru } 26520fefbfbaSSudarsana Kalluru 26530fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 26540fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 26550fefbfbaSSudarsana Kalluru { 26560fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 265717991002SMintz, Yuval u32 mfw_mac[2]; 26580fefbfbaSSudarsana Kalluru int rc; 26590fefbfbaSSudarsana Kalluru 26600fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 26610fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 26620fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 26630fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 26640fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 26652f67af8cSTomer Tayar 266617991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 266717991002SMintz, Yuval * in 32-bit granularity. 266817991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 266917991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 267017991002SMintz, Yuval */ 267117991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 267217991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 267317991002SMintz, Yuval 267417991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 267517991002SMintz, Yuval mb_params.data_src_size = 8; 26760fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 26770fefbfbaSSudarsana Kalluru if (rc) 26780fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 26790fefbfbaSSudarsana Kalluru 268014d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 268114d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 268214d39648SMintz, Yuval 26830fefbfbaSSudarsana Kalluru return rc; 26840fefbfbaSSudarsana Kalluru } 26850fefbfbaSSudarsana Kalluru 26860fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 26870fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 26880fefbfbaSSudarsana Kalluru { 26890fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 26900fefbfbaSSudarsana Kalluru u32 drv_mb_param; 26910fefbfbaSSudarsana Kalluru int rc; 26920fefbfbaSSudarsana Kalluru 269314d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 269414d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 269514d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 269614d39648SMintz, Yuval return -EINVAL; 269714d39648SMintz, Yuval } 269814d39648SMintz, Yuval 26990fefbfbaSSudarsana Kalluru switch (wol) { 27000fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 27010fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 27020fefbfbaSSudarsana Kalluru break; 27030fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 27040fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 27050fefbfbaSSudarsana Kalluru break; 27060fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 27070fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 27080fefbfbaSSudarsana Kalluru break; 27090fefbfbaSSudarsana Kalluru default: 27100fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 27110fefbfbaSSudarsana Kalluru return -EINVAL; 27120fefbfbaSSudarsana Kalluru } 27130fefbfbaSSudarsana Kalluru 27140fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 27150fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 27160fefbfbaSSudarsana Kalluru if (rc) 27170fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 27180fefbfbaSSudarsana Kalluru 271914d39648SMintz, Yuval /* Store the WoL update for a future unload */ 272014d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 272114d39648SMintz, Yuval 27220fefbfbaSSudarsana Kalluru return rc; 27230fefbfbaSSudarsana Kalluru } 27240fefbfbaSSudarsana Kalluru 27250fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 27260fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 27270fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 27280fefbfbaSSudarsana Kalluru { 27290fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 27300fefbfbaSSudarsana Kalluru u32 drv_mb_param; 27310fefbfbaSSudarsana Kalluru int rc; 27320fefbfbaSSudarsana Kalluru 27330fefbfbaSSudarsana Kalluru switch (eswitch) { 27340fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 27350fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 27360fefbfbaSSudarsana Kalluru break; 27370fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 27380fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 27390fefbfbaSSudarsana Kalluru break; 27400fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 27410fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 27420fefbfbaSSudarsana Kalluru break; 27430fefbfbaSSudarsana Kalluru default: 27440fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 27450fefbfbaSSudarsana Kalluru return -EINVAL; 27460fefbfbaSSudarsana Kalluru } 27470fefbfbaSSudarsana Kalluru 27480fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 27490fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 27500fefbfbaSSudarsana Kalluru if (rc) 27510fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 27520fefbfbaSSudarsana Kalluru 27530fefbfbaSSudarsana Kalluru return rc; 27540fefbfbaSSudarsana Kalluru } 27550fefbfbaSSudarsana Kalluru 27561a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 27571a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 275891420b83SSudarsana Kalluru { 275991420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 276091420b83SSudarsana Kalluru int rc; 276191420b83SSudarsana Kalluru 276291420b83SSudarsana Kalluru switch (mode) { 276391420b83SSudarsana Kalluru case QED_LED_MODE_ON: 276491420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 276591420b83SSudarsana Kalluru break; 276691420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 276791420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 276891420b83SSudarsana Kalluru break; 276991420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 277091420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 277191420b83SSudarsana Kalluru break; 277291420b83SSudarsana Kalluru default: 277391420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 277491420b83SSudarsana Kalluru return -EINVAL; 277591420b83SSudarsana Kalluru } 277691420b83SSudarsana Kalluru 277791420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 277891420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 277991420b83SSudarsana Kalluru 278091420b83SSudarsana Kalluru return rc; 278191420b83SSudarsana Kalluru } 278203dc76caSSudarsana Reddy Kalluru 27834102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 27844102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 27854102426fSTomer Tayar { 27864102426fSTomer Tayar u32 resp = 0, param = 0; 27874102426fSTomer Tayar int rc; 27884102426fSTomer Tayar 27894102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 27904102426fSTomer Tayar mask_parities, &resp, ¶m); 27914102426fSTomer Tayar 27924102426fSTomer Tayar if (rc) { 27934102426fSTomer Tayar DP_ERR(p_hwfn, 27944102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 27954102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 27964102426fSTomer Tayar DP_ERR(p_hwfn, 27974102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 27984102426fSTomer Tayar rc = -EINVAL; 27994102426fSTomer Tayar } 28004102426fSTomer Tayar 28014102426fSTomer Tayar return rc; 28024102426fSTomer Tayar } 28034102426fSTomer Tayar 28047a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 28057a4b21b7SMintz, Yuval { 28067a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 28077a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 28087a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 28097a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 28107a4b21b7SMintz, Yuval int rc = 0; 28117a4b21b7SMintz, Yuval 28127a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 28137a4b21b7SMintz, Yuval if (!p_ptt) 28147a4b21b7SMintz, Yuval return -EBUSY; 28157a4b21b7SMintz, Yuval 28167a4b21b7SMintz, Yuval while (bytes_left > 0) { 28177a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 28187a4b21b7SMintz, Yuval 28197a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 28207a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 28217a4b21b7SMintz, Yuval addr + offset + 28227a4b21b7SMintz, Yuval (bytes_to_copy << 2823da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 28247a4b21b7SMintz, Yuval &resp, &resp_param, 28257a4b21b7SMintz, Yuval &read_len, 28267a4b21b7SMintz, Yuval (u32 *)(p_buf + offset)); 28277a4b21b7SMintz, Yuval 28287a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 28297a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 28307a4b21b7SMintz, Yuval break; 28317a4b21b7SMintz, Yuval } 28327a4b21b7SMintz, Yuval 28337a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 28347a4b21b7SMintz, Yuval * isn't preemptable. Sleep a bit to prevent CPU hogging. 28357a4b21b7SMintz, Yuval */ 28367a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 28377a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 28387a4b21b7SMintz, Yuval usleep_range(1000, 2000); 28397a4b21b7SMintz, Yuval 28407a4b21b7SMintz, Yuval offset += read_len; 28417a4b21b7SMintz, Yuval bytes_left -= read_len; 28427a4b21b7SMintz, Yuval } 28437a4b21b7SMintz, Yuval 28447a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 28457a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 28467a4b21b7SMintz, Yuval 28477a4b21b7SMintz, Yuval return rc; 28487a4b21b7SMintz, Yuval } 28497a4b21b7SMintz, Yuval 285062e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 285162e4d438SSudarsana Reddy Kalluru { 285262e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 285362e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 285462e4d438SSudarsana Reddy Kalluru 285562e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 285662e4d438SSudarsana Reddy Kalluru if (!p_ptt) 285762e4d438SSudarsana Reddy Kalluru return -EBUSY; 285862e4d438SSudarsana Reddy Kalluru 285962e4d438SSudarsana Reddy Kalluru memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 286062e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 286162e4d438SSudarsana Reddy Kalluru 286262e4d438SSudarsana Reddy Kalluru return 0; 286362e4d438SSudarsana Reddy Kalluru } 286462e4d438SSudarsana Reddy Kalluru 286562e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 286662e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len) 286762e4d438SSudarsana Reddy Kalluru { 286862e4d438SSudarsana Reddy Kalluru u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 286962e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 287062e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 287162e4d438SSudarsana Reddy Kalluru int rc = -EINVAL; 287262e4d438SSudarsana Reddy Kalluru 287362e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 287462e4d438SSudarsana Reddy Kalluru if (!p_ptt) 287562e4d438SSudarsana Reddy Kalluru return -EBUSY; 287662e4d438SSudarsana Reddy Kalluru 287762e4d438SSudarsana Reddy Kalluru switch (cmd) { 2878057d2b19SSudarsana Reddy Kalluru case QED_PUT_FILE_BEGIN: 2879057d2b19SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN; 2880057d2b19SSudarsana Reddy Kalluru break; 288162e4d438SSudarsana Reddy Kalluru case QED_PUT_FILE_DATA: 288262e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 288362e4d438SSudarsana Reddy Kalluru break; 288462e4d438SSudarsana Reddy Kalluru case QED_NVM_WRITE_NVRAM: 288562e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 288662e4d438SSudarsana Reddy Kalluru break; 288762e4d438SSudarsana Reddy Kalluru default: 288862e4d438SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 288962e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 289062e4d438SSudarsana Reddy Kalluru goto out; 289162e4d438SSudarsana Reddy Kalluru } 289262e4d438SSudarsana Reddy Kalluru 289362e4d438SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 2894057d2b19SSudarsana Reddy Kalluru while (buf_idx < len) { 2895057d2b19SSudarsana Reddy Kalluru if (cmd == QED_PUT_FILE_BEGIN) 2896057d2b19SSudarsana Reddy Kalluru nvm_offset = addr; 2897057d2b19SSudarsana Reddy Kalluru else 2898057d2b19SSudarsana Reddy Kalluru nvm_offset = ((buf_size << 2899057d2b19SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_LEN_OFFSET) | addr) + 2900057d2b19SSudarsana Reddy Kalluru buf_idx; 290162e4d438SSudarsana Reddy Kalluru rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 290262e4d438SSudarsana Reddy Kalluru &resp, ¶m, buf_size, 290362e4d438SSudarsana Reddy Kalluru (u32 *)&p_buf[buf_idx]); 290462e4d438SSudarsana Reddy Kalluru if (rc) { 290562e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 290662e4d438SSudarsana Reddy Kalluru resp = FW_MSG_CODE_ERROR; 290762e4d438SSudarsana Reddy Kalluru break; 290862e4d438SSudarsana Reddy Kalluru } 290962e4d438SSudarsana Reddy Kalluru 291062e4d438SSudarsana Reddy Kalluru if (resp != FW_MSG_CODE_OK && 291162e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_OK && 291262e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 291362e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, 291462e4d438SSudarsana Reddy Kalluru "nvm write failed, resp = 0x%08x\n", resp); 291562e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 291662e4d438SSudarsana Reddy Kalluru break; 291762e4d438SSudarsana Reddy Kalluru } 291862e4d438SSudarsana Reddy Kalluru 291962e4d438SSudarsana Reddy Kalluru /* This can be a lengthy process, and it's possible scheduler 292062e4d438SSudarsana Reddy Kalluru * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 292162e4d438SSudarsana Reddy Kalluru */ 292262e4d438SSudarsana Reddy Kalluru if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 292362e4d438SSudarsana Reddy Kalluru usleep_range(1000, 2000); 292462e4d438SSudarsana Reddy Kalluru 2925057d2b19SSudarsana Reddy Kalluru /* For MBI upgrade, MFW response includes the next buffer offset 2926057d2b19SSudarsana Reddy Kalluru * to be delivered to MFW. 2927057d2b19SSudarsana Reddy Kalluru */ 2928057d2b19SSudarsana Reddy Kalluru if (param && cmd == QED_PUT_FILE_DATA) { 2929057d2b19SSudarsana Reddy Kalluru buf_idx = QED_MFW_GET_FIELD(param, 2930057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET); 2931057d2b19SSudarsana Reddy Kalluru buf_size = QED_MFW_GET_FIELD(param, 2932057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE); 2933057d2b19SSudarsana Reddy Kalluru } else { 293462e4d438SSudarsana Reddy Kalluru buf_idx += buf_size; 2935057d2b19SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), 2936057d2b19SSudarsana Reddy Kalluru MCP_DRV_NVM_BUF_LEN); 2937057d2b19SSudarsana Reddy Kalluru } 293862e4d438SSudarsana Reddy Kalluru } 293962e4d438SSudarsana Reddy Kalluru 294062e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 294162e4d438SSudarsana Reddy Kalluru out: 294262e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 294362e4d438SSudarsana Reddy Kalluru 294462e4d438SSudarsana Reddy Kalluru return rc; 294562e4d438SSudarsana Reddy Kalluru } 294662e4d438SSudarsana Reddy Kalluru 2947b51dab46SSudarsana Reddy Kalluru int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2948b51dab46SSudarsana Reddy Kalluru u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 2949b51dab46SSudarsana Reddy Kalluru { 2950b51dab46SSudarsana Reddy Kalluru u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 2951b51dab46SSudarsana Reddy Kalluru u32 resp, param; 2952b51dab46SSudarsana Reddy Kalluru int rc; 2953b51dab46SSudarsana Reddy Kalluru 2954b51dab46SSudarsana Reddy Kalluru nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 2955b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 2956b51dab46SSudarsana Reddy Kalluru nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 2957b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 2958b51dab46SSudarsana Reddy Kalluru 2959b51dab46SSudarsana Reddy Kalluru addr = offset; 2960b51dab46SSudarsana Reddy Kalluru offset = 0; 2961b51dab46SSudarsana Reddy Kalluru bytes_left = len; 2962b51dab46SSudarsana Reddy Kalluru while (bytes_left > 0) { 2963b51dab46SSudarsana Reddy Kalluru bytes_to_copy = min_t(u32, bytes_left, 2964b51dab46SSudarsana Reddy Kalluru MAX_I2C_TRANSACTION_SIZE); 2965b51dab46SSudarsana Reddy Kalluru nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 2966b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 2967b51dab46SSudarsana Reddy Kalluru nvm_offset |= ((addr + offset) << 2968b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 2969b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 2970b51dab46SSudarsana Reddy Kalluru nvm_offset |= (bytes_to_copy << 2971b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 2972b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 2973b51dab46SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2974b51dab46SSudarsana Reddy Kalluru DRV_MSG_CODE_TRANSCEIVER_READ, 2975b51dab46SSudarsana Reddy Kalluru nvm_offset, &resp, ¶m, &buf_size, 2976b51dab46SSudarsana Reddy Kalluru (u32 *)(p_buf + offset)); 2977b51dab46SSudarsana Reddy Kalluru if (rc) { 2978b51dab46SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 2979b51dab46SSudarsana Reddy Kalluru "Failed to send a transceiver read command to the MFW. rc = %d.\n", 2980b51dab46SSudarsana Reddy Kalluru rc); 2981b51dab46SSudarsana Reddy Kalluru return rc; 2982b51dab46SSudarsana Reddy Kalluru } 2983b51dab46SSudarsana Reddy Kalluru 2984b51dab46SSudarsana Reddy Kalluru if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 2985b51dab46SSudarsana Reddy Kalluru return -ENODEV; 2986b51dab46SSudarsana Reddy Kalluru else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 2987b51dab46SSudarsana Reddy Kalluru return -EINVAL; 2988b51dab46SSudarsana Reddy Kalluru 2989b51dab46SSudarsana Reddy Kalluru offset += buf_size; 2990b51dab46SSudarsana Reddy Kalluru bytes_left -= buf_size; 2991b51dab46SSudarsana Reddy Kalluru } 2992b51dab46SSudarsana Reddy Kalluru 2993b51dab46SSudarsana Reddy Kalluru return 0; 2994b51dab46SSudarsana Reddy Kalluru } 2995b51dab46SSudarsana Reddy Kalluru 299603dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 299703dc76caSSudarsana Reddy Kalluru { 299803dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 299903dc76caSSudarsana Reddy Kalluru int rc = 0; 300003dc76caSSudarsana Reddy Kalluru 300103dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 300203dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 300303dc76caSSudarsana Reddy Kalluru 300403dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 300503dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 300603dc76caSSudarsana Reddy Kalluru 300703dc76caSSudarsana Reddy Kalluru if (rc) 300803dc76caSSudarsana Reddy Kalluru return rc; 300903dc76caSSudarsana Reddy Kalluru 301003dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 301103dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 301203dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 301303dc76caSSudarsana Reddy Kalluru 301403dc76caSSudarsana Reddy Kalluru return rc; 301503dc76caSSudarsana Reddy Kalluru } 301603dc76caSSudarsana Reddy Kalluru 301703dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 301803dc76caSSudarsana Reddy Kalluru { 301903dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 302003dc76caSSudarsana Reddy Kalluru int rc = 0; 302103dc76caSSudarsana Reddy Kalluru 302203dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 302303dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 302403dc76caSSudarsana Reddy Kalluru 302503dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 302603dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 302703dc76caSSudarsana Reddy Kalluru 302803dc76caSSudarsana Reddy Kalluru if (rc) 302903dc76caSSudarsana Reddy Kalluru return rc; 303003dc76caSSudarsana Reddy Kalluru 303103dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 303203dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 303303dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 303403dc76caSSudarsana Reddy Kalluru 303503dc76caSSudarsana Reddy Kalluru return rc; 303603dc76caSSudarsana Reddy Kalluru } 30377a4b21b7SMintz, Yuval 303843645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 30397a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 30407a4b21b7SMintz, Yuval u32 *num_images) 30417a4b21b7SMintz, Yuval { 30427a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 30437a4b21b7SMintz, Yuval int rc = 0; 30447a4b21b7SMintz, Yuval 30457a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 30467a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 30477a4b21b7SMintz, Yuval 30487a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 30497a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 30507a4b21b7SMintz, Yuval if (rc) 30517a4b21b7SMintz, Yuval return rc; 30527a4b21b7SMintz, Yuval 30537a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 30547a4b21b7SMintz, Yuval rc = -EINVAL; 30557a4b21b7SMintz, Yuval 30567a4b21b7SMintz, Yuval return rc; 30577a4b21b7SMintz, Yuval } 30587a4b21b7SMintz, Yuval 305943645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 30607a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 30617a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 30627a4b21b7SMintz, Yuval u32 image_index) 30637a4b21b7SMintz, Yuval { 30647a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 30657a4b21b7SMintz, Yuval int rc; 30667a4b21b7SMintz, Yuval 30677a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 30687a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 30697a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 30707a4b21b7SMintz, Yuval 30717a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 30727a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 30737a4b21b7SMintz, Yuval &resp, &resp_param, 30747a4b21b7SMintz, Yuval &buf_size, 30757a4b21b7SMintz, Yuval (u32 *)p_image_att); 30767a4b21b7SMintz, Yuval if (rc) 30777a4b21b7SMintz, Yuval return rc; 30787a4b21b7SMintz, Yuval 30797a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 30807a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 30817a4b21b7SMintz, Yuval rc = -EINVAL; 30827a4b21b7SMintz, Yuval 30837a4b21b7SMintz, Yuval return rc; 30847a4b21b7SMintz, Yuval } 30852edbff8dSTomer Tayar 308643645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 308743645ce0SSudarsana Reddy Kalluru { 30885e7ba042SDenis Bolotin struct qed_nvm_image_info nvm_info; 308943645ce0SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 309043645ce0SSudarsana Reddy Kalluru int rc; 309143645ce0SSudarsana Reddy Kalluru u32 i; 309243645ce0SSudarsana Reddy Kalluru 30935e7ba042SDenis Bolotin if (p_hwfn->nvm_info.valid) 30945e7ba042SDenis Bolotin return 0; 30955e7ba042SDenis Bolotin 309643645ce0SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 309743645ce0SSudarsana Reddy Kalluru if (!p_ptt) { 309843645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "failed to acquire ptt\n"); 309943645ce0SSudarsana Reddy Kalluru return -EBUSY; 310043645ce0SSudarsana Reddy Kalluru } 310143645ce0SSudarsana Reddy Kalluru 310243645ce0SSudarsana Reddy Kalluru /* Acquire from MFW the amount of available images */ 31035e7ba042SDenis Bolotin nvm_info.num_images = 0; 310443645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 31055e7ba042SDenis Bolotin p_ptt, &nvm_info.num_images); 310643645ce0SSudarsana Reddy Kalluru if (rc == -EOPNOTSUPP) { 310743645ce0SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 310843645ce0SSudarsana Reddy Kalluru goto out; 31095e7ba042SDenis Bolotin } else if (rc || !nvm_info.num_images) { 311043645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Failed getting number of images\n"); 311143645ce0SSudarsana Reddy Kalluru goto err0; 311243645ce0SSudarsana Reddy Kalluru } 311343645ce0SSudarsana Reddy Kalluru 31145e7ba042SDenis Bolotin nvm_info.image_att = kmalloc_array(nvm_info.num_images, 311543645ce0SSudarsana Reddy Kalluru sizeof(struct bist_nvm_image_att), 311643645ce0SSudarsana Reddy Kalluru GFP_KERNEL); 31175e7ba042SDenis Bolotin if (!nvm_info.image_att) { 311843645ce0SSudarsana Reddy Kalluru rc = -ENOMEM; 311943645ce0SSudarsana Reddy Kalluru goto err0; 312043645ce0SSudarsana Reddy Kalluru } 312143645ce0SSudarsana Reddy Kalluru 312243645ce0SSudarsana Reddy Kalluru /* Iterate over images and get their attributes */ 31235e7ba042SDenis Bolotin for (i = 0; i < nvm_info.num_images; i++) { 312443645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 31255e7ba042SDenis Bolotin &nvm_info.image_att[i], i); 312643645ce0SSudarsana Reddy Kalluru if (rc) { 312743645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, 312843645ce0SSudarsana Reddy Kalluru "Failed getting image index %d attributes\n", i); 312943645ce0SSudarsana Reddy Kalluru goto err1; 313043645ce0SSudarsana Reddy Kalluru } 313143645ce0SSudarsana Reddy Kalluru 313243645ce0SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 31335e7ba042SDenis Bolotin nvm_info.image_att[i].len); 313443645ce0SSudarsana Reddy Kalluru } 313543645ce0SSudarsana Reddy Kalluru out: 31365e7ba042SDenis Bolotin /* Update hwfn's nvm_info */ 31375e7ba042SDenis Bolotin if (nvm_info.num_images) { 31385e7ba042SDenis Bolotin p_hwfn->nvm_info.num_images = nvm_info.num_images; 31395e7ba042SDenis Bolotin kfree(p_hwfn->nvm_info.image_att); 31405e7ba042SDenis Bolotin p_hwfn->nvm_info.image_att = nvm_info.image_att; 31415e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = true; 31425e7ba042SDenis Bolotin } 31435e7ba042SDenis Bolotin 314443645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 314543645ce0SSudarsana Reddy Kalluru return 0; 314643645ce0SSudarsana Reddy Kalluru 314743645ce0SSudarsana Reddy Kalluru err1: 31485e7ba042SDenis Bolotin kfree(nvm_info.image_att); 314943645ce0SSudarsana Reddy Kalluru err0: 315043645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 315143645ce0SSudarsana Reddy Kalluru return rc; 315243645ce0SSudarsana Reddy Kalluru } 315343645ce0SSudarsana Reddy Kalluru 31541ac4329aSDenis Bolotin int 315520675b37SMintz, Yuval qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 315620675b37SMintz, Yuval enum qed_nvm_images image_id, 315720675b37SMintz, Yuval struct qed_nvm_image_att *p_image_att) 315820675b37SMintz, Yuval { 315920675b37SMintz, Yuval enum nvm_image_type type; 316043645ce0SSudarsana Reddy Kalluru u32 i; 316120675b37SMintz, Yuval 316220675b37SMintz, Yuval /* Translate image_id into MFW definitions */ 316320675b37SMintz, Yuval switch (image_id) { 316420675b37SMintz, Yuval case QED_NVM_IMAGE_ISCSI_CFG: 316520675b37SMintz, Yuval type = NVM_TYPE_ISCSI_CFG; 316620675b37SMintz, Yuval break; 316720675b37SMintz, Yuval case QED_NVM_IMAGE_FCOE_CFG: 316820675b37SMintz, Yuval type = NVM_TYPE_FCOE_CFG; 316920675b37SMintz, Yuval break; 31708a52bbabSMichal Kalderon case QED_NVM_IMAGE_MDUMP: 31718a52bbabSMichal Kalderon type = NVM_TYPE_MDUMP; 31728a52bbabSMichal Kalderon break; 31731ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_CFG1: 31741ac4329aSDenis Bolotin type = NVM_TYPE_NVM_CFG1; 31751ac4329aSDenis Bolotin break; 31761ac4329aSDenis Bolotin case QED_NVM_IMAGE_DEFAULT_CFG: 31771ac4329aSDenis Bolotin type = NVM_TYPE_DEFAULT_CFG; 31781ac4329aSDenis Bolotin break; 31791ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_META: 31801ac4329aSDenis Bolotin type = NVM_TYPE_META; 31811ac4329aSDenis Bolotin break; 318220675b37SMintz, Yuval default: 318320675b37SMintz, Yuval DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 318420675b37SMintz, Yuval image_id); 318520675b37SMintz, Yuval return -EINVAL; 318620675b37SMintz, Yuval } 318720675b37SMintz, Yuval 31885e7ba042SDenis Bolotin qed_mcp_nvm_info_populate(p_hwfn); 318943645ce0SSudarsana Reddy Kalluru for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 319043645ce0SSudarsana Reddy Kalluru if (type == p_hwfn->nvm_info.image_att[i].image_type) 319120675b37SMintz, Yuval break; 319243645ce0SSudarsana Reddy Kalluru if (i == p_hwfn->nvm_info.num_images) { 319320675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 319420675b37SMintz, Yuval "Failed to find nvram image of type %08x\n", 319520675b37SMintz, Yuval image_id); 319643645ce0SSudarsana Reddy Kalluru return -ENOENT; 319720675b37SMintz, Yuval } 319820675b37SMintz, Yuval 319943645ce0SSudarsana Reddy Kalluru p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 320043645ce0SSudarsana Reddy Kalluru p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 320120675b37SMintz, Yuval 320220675b37SMintz, Yuval return 0; 320320675b37SMintz, Yuval } 320420675b37SMintz, Yuval 320520675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 320620675b37SMintz, Yuval enum qed_nvm_images image_id, 320720675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len) 320820675b37SMintz, Yuval { 320920675b37SMintz, Yuval struct qed_nvm_image_att image_att; 321020675b37SMintz, Yuval int rc; 321120675b37SMintz, Yuval 321220675b37SMintz, Yuval memset(p_buffer, 0, buffer_len); 321320675b37SMintz, Yuval 3214b60bfdfeSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 321520675b37SMintz, Yuval if (rc) 321620675b37SMintz, Yuval return rc; 321720675b37SMintz, Yuval 321820675b37SMintz, Yuval /* Validate sizes - both the image's and the supplied buffer's */ 321920675b37SMintz, Yuval if (image_att.length <= 4) { 322020675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 322120675b37SMintz, Yuval "Image [%d] is too small - only %d bytes\n", 322220675b37SMintz, Yuval image_id, image_att.length); 322320675b37SMintz, Yuval return -EINVAL; 322420675b37SMintz, Yuval } 322520675b37SMintz, Yuval 322620675b37SMintz, Yuval if (image_att.length > buffer_len) { 322720675b37SMintz, Yuval DP_VERBOSE(p_hwfn, 322820675b37SMintz, Yuval QED_MSG_STORAGE, 322920675b37SMintz, Yuval "Image [%d] is too big - %08x bytes where only %08x are available\n", 323020675b37SMintz, Yuval image_id, image_att.length, buffer_len); 323120675b37SMintz, Yuval return -ENOMEM; 323220675b37SMintz, Yuval } 323320675b37SMintz, Yuval 323420675b37SMintz, Yuval return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 323520675b37SMintz, Yuval p_buffer, image_att.length); 323620675b37SMintz, Yuval } 323720675b37SMintz, Yuval 32389c8517c4STomer Tayar static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 32399c8517c4STomer Tayar { 32409c8517c4STomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 32419c8517c4STomer Tayar 32429c8517c4STomer Tayar switch (res_id) { 32439c8517c4STomer Tayar case QED_SB: 32449c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 32459c8517c4STomer Tayar break; 32469c8517c4STomer Tayar case QED_L2_QUEUE: 32479c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 32489c8517c4STomer Tayar break; 32499c8517c4STomer Tayar case QED_VPORT: 32509c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 32519c8517c4STomer Tayar break; 32529c8517c4STomer Tayar case QED_RSS_ENG: 32539c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 32549c8517c4STomer Tayar break; 32559c8517c4STomer Tayar case QED_PQ: 32569c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 32579c8517c4STomer Tayar break; 32589c8517c4STomer Tayar case QED_RL: 32599c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 32609c8517c4STomer Tayar break; 32619c8517c4STomer Tayar case QED_MAC: 32629c8517c4STomer Tayar case QED_VLAN: 32639c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 32649c8517c4STomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 32659c8517c4STomer Tayar break; 32669c8517c4STomer Tayar case QED_ILT: 32679c8517c4STomer Tayar mfw_res_id = RESOURCE_ILT_E; 32689c8517c4STomer Tayar break; 3269997af5dfSMichal Kalderon case QED_LL2_RAM_QUEUE: 32709c8517c4STomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 32719c8517c4STomer Tayar break; 3272997af5dfSMichal Kalderon case QED_LL2_CTX_QUEUE: 3273997af5dfSMichal Kalderon mfw_res_id = RESOURCE_LL2_CQS_E; 3274997af5dfSMichal Kalderon break; 32759c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 32769c8517c4STomer Tayar case QED_CMDQS_CQS: 32779c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 32789c8517c4STomer Tayar mfw_res_id = RESOURCE_CQS_E; 32799c8517c4STomer Tayar break; 32809c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 32819c8517c4STomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 32829c8517c4STomer Tayar break; 32839c8517c4STomer Tayar case QED_BDQ: 32849c8517c4STomer Tayar mfw_res_id = RESOURCE_BDQ_E; 32859c8517c4STomer Tayar break; 32869c8517c4STomer Tayar default: 32879c8517c4STomer Tayar break; 32889c8517c4STomer Tayar } 32899c8517c4STomer Tayar 32909c8517c4STomer Tayar return mfw_res_id; 32919c8517c4STomer Tayar } 32929c8517c4STomer Tayar 32939c8517c4STomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 2 32942edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 32952edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 32962edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 32972edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 32982edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 32992edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 33009c8517c4STomer Tayar 33019c8517c4STomer Tayar struct qed_resc_alloc_in_params { 33029c8517c4STomer Tayar u32 cmd; 33039c8517c4STomer Tayar enum qed_resources res_id; 33049c8517c4STomer Tayar u32 resc_max_val; 33059c8517c4STomer Tayar }; 33069c8517c4STomer Tayar 33079c8517c4STomer Tayar struct qed_resc_alloc_out_params { 33089c8517c4STomer Tayar u32 mcp_resp; 33099c8517c4STomer Tayar u32 mcp_param; 33109c8517c4STomer Tayar u32 resc_num; 33119c8517c4STomer Tayar u32 resc_start; 33129c8517c4STomer Tayar u32 vf_resc_num; 33139c8517c4STomer Tayar u32 vf_resc_start; 33149c8517c4STomer Tayar u32 flags; 33159c8517c4STomer Tayar }; 33169c8517c4STomer Tayar 33179c8517c4STomer Tayar static int 33189c8517c4STomer Tayar qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 33192edbff8dSTomer Tayar struct qed_ptt *p_ptt, 33209c8517c4STomer Tayar struct qed_resc_alloc_in_params *p_in_params, 33219c8517c4STomer Tayar struct qed_resc_alloc_out_params *p_out_params) 33222edbff8dSTomer Tayar { 33232edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 33249c8517c4STomer Tayar struct resource_info mfw_resc_info; 33252edbff8dSTomer Tayar int rc; 33262edbff8dSTomer Tayar 33279c8517c4STomer Tayar memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 3328bb480242SMintz, Yuval 33299c8517c4STomer Tayar mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 33309c8517c4STomer Tayar if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 33319c8517c4STomer Tayar DP_ERR(p_hwfn, 33329c8517c4STomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 33339c8517c4STomer Tayar p_in_params->res_id, 33349c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id)); 33359c8517c4STomer Tayar return -EINVAL; 33369c8517c4STomer Tayar } 33379c8517c4STomer Tayar 33389c8517c4STomer Tayar switch (p_in_params->cmd) { 33399c8517c4STomer Tayar case DRV_MSG_SET_RESOURCE_VALUE_MSG: 33409c8517c4STomer Tayar mfw_resc_info.size = p_in_params->resc_max_val; 33419c8517c4STomer Tayar /* Fallthrough */ 33429c8517c4STomer Tayar case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 33439c8517c4STomer Tayar break; 33449c8517c4STomer Tayar default: 33459c8517c4STomer Tayar DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 33469c8517c4STomer Tayar p_in_params->cmd); 33479c8517c4STomer Tayar return -EINVAL; 33489c8517c4STomer Tayar } 33499c8517c4STomer Tayar 33509c8517c4STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 33519c8517c4STomer Tayar mb_params.cmd = p_in_params->cmd; 33529c8517c4STomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 33539c8517c4STomer Tayar mb_params.p_data_src = &mfw_resc_info; 33549c8517c4STomer Tayar mb_params.data_src_size = sizeof(mfw_resc_info); 33559c8517c4STomer Tayar mb_params.p_data_dst = mb_params.p_data_src; 33569c8517c4STomer Tayar mb_params.data_dst_size = mb_params.data_src_size; 33579c8517c4STomer Tayar 33589c8517c4STomer Tayar DP_VERBOSE(p_hwfn, 33599c8517c4STomer Tayar QED_MSG_SP, 33609c8517c4STomer Tayar "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 33619c8517c4STomer Tayar p_in_params->cmd, 33629c8517c4STomer Tayar p_in_params->res_id, 33639c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id), 33649c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 33659c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 33669c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 33679c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 33689c8517c4STomer Tayar p_in_params->resc_max_val); 33699c8517c4STomer Tayar 33702edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 33712edbff8dSTomer Tayar if (rc) 33722edbff8dSTomer Tayar return rc; 33732edbff8dSTomer Tayar 33749c8517c4STomer Tayar p_out_params->mcp_resp = mb_params.mcp_resp; 33759c8517c4STomer Tayar p_out_params->mcp_param = mb_params.mcp_param; 33769c8517c4STomer Tayar p_out_params->resc_num = mfw_resc_info.size; 33779c8517c4STomer Tayar p_out_params->resc_start = mfw_resc_info.offset; 33789c8517c4STomer Tayar p_out_params->vf_resc_num = mfw_resc_info.vf_size; 33799c8517c4STomer Tayar p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 33809c8517c4STomer Tayar p_out_params->flags = mfw_resc_info.flags; 33812edbff8dSTomer Tayar 33822edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 33832edbff8dSTomer Tayar QED_MSG_SP, 33849c8517c4STomer Tayar "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 33859c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 33869c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 33879c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 33889c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 33899c8517c4STomer Tayar p_out_params->resc_num, 33909c8517c4STomer Tayar p_out_params->resc_start, 33919c8517c4STomer Tayar p_out_params->vf_resc_num, 33929c8517c4STomer Tayar p_out_params->vf_resc_start, p_out_params->flags); 33939c8517c4STomer Tayar 33949c8517c4STomer Tayar return 0; 33959c8517c4STomer Tayar } 33969c8517c4STomer Tayar 33979c8517c4STomer Tayar int 33989c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 33999c8517c4STomer Tayar struct qed_ptt *p_ptt, 34009c8517c4STomer Tayar enum qed_resources res_id, 34019c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 34029c8517c4STomer Tayar { 34039c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 34049c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 34059c8517c4STomer Tayar int rc; 34069c8517c4STomer Tayar 34079c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 34089c8517c4STomer Tayar in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 34099c8517c4STomer Tayar in_params.res_id = res_id; 34109c8517c4STomer Tayar in_params.resc_max_val = resc_max_val; 34119c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 34129c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 34139c8517c4STomer Tayar &out_params); 34149c8517c4STomer Tayar if (rc) 34159c8517c4STomer Tayar return rc; 34169c8517c4STomer Tayar 34179c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 34189c8517c4STomer Tayar 34199c8517c4STomer Tayar return 0; 34209c8517c4STomer Tayar } 34219c8517c4STomer Tayar 34229c8517c4STomer Tayar int 34239c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 34249c8517c4STomer Tayar struct qed_ptt *p_ptt, 34259c8517c4STomer Tayar enum qed_resources res_id, 34269c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 34279c8517c4STomer Tayar { 34289c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 34299c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 34309c8517c4STomer Tayar int rc; 34319c8517c4STomer Tayar 34329c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 34339c8517c4STomer Tayar in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 34349c8517c4STomer Tayar in_params.res_id = res_id; 34359c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 34369c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 34379c8517c4STomer Tayar &out_params); 34389c8517c4STomer Tayar if (rc) 34399c8517c4STomer Tayar return rc; 34409c8517c4STomer Tayar 34419c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 34429c8517c4STomer Tayar 34439c8517c4STomer Tayar if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 34449c8517c4STomer Tayar *p_resc_num = out_params.resc_num; 34459c8517c4STomer Tayar *p_resc_start = out_params.resc_start; 34469c8517c4STomer Tayar } 34472edbff8dSTomer Tayar 34482edbff8dSTomer Tayar return 0; 34492edbff8dSTomer Tayar } 345018a69e36SMintz, Yuval 345118a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 345218a69e36SMintz, Yuval { 345318a69e36SMintz, Yuval u32 mcp_resp, mcp_param; 345418a69e36SMintz, Yuval 345518a69e36SMintz, Yuval return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 345618a69e36SMintz, Yuval &mcp_resp, &mcp_param); 345718a69e36SMintz, Yuval } 345895691c9cSTomer Tayar 345995691c9cSTomer Tayar static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 346095691c9cSTomer Tayar struct qed_ptt *p_ptt, 346195691c9cSTomer Tayar u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 346295691c9cSTomer Tayar { 346395691c9cSTomer Tayar int rc; 346495691c9cSTomer Tayar 346595691c9cSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 346695691c9cSTomer Tayar p_mcp_resp, p_mcp_param); 346795691c9cSTomer Tayar if (rc) 346895691c9cSTomer Tayar return rc; 346995691c9cSTomer Tayar 347095691c9cSTomer Tayar if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 347195691c9cSTomer Tayar DP_INFO(p_hwfn, 347295691c9cSTomer Tayar "The resource command is unsupported by the MFW\n"); 347395691c9cSTomer Tayar return -EINVAL; 347495691c9cSTomer Tayar } 347595691c9cSTomer Tayar 347695691c9cSTomer Tayar if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 347795691c9cSTomer Tayar u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 347895691c9cSTomer Tayar 347995691c9cSTomer Tayar DP_NOTICE(p_hwfn, 348095691c9cSTomer Tayar "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 348195691c9cSTomer Tayar param, opcode); 348295691c9cSTomer Tayar return -EINVAL; 348395691c9cSTomer Tayar } 348495691c9cSTomer Tayar 348595691c9cSTomer Tayar return rc; 348695691c9cSTomer Tayar } 348795691c9cSTomer Tayar 3488bf774d14SYueHaibing static int 348995691c9cSTomer Tayar __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 349095691c9cSTomer Tayar struct qed_ptt *p_ptt, 349195691c9cSTomer Tayar struct qed_resc_lock_params *p_params) 349295691c9cSTomer Tayar { 349395691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 349495691c9cSTomer Tayar u8 opcode; 349595691c9cSTomer Tayar int rc; 349695691c9cSTomer Tayar 349795691c9cSTomer Tayar switch (p_params->timeout) { 349895691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_DEFAULT: 349995691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ; 350095691c9cSTomer Tayar p_params->timeout = 0; 350195691c9cSTomer Tayar break; 350295691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_NONE: 350395691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_WO_AGING; 350495691c9cSTomer Tayar p_params->timeout = 0; 350595691c9cSTomer Tayar break; 350695691c9cSTomer Tayar default: 350795691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_W_AGING; 350895691c9cSTomer Tayar break; 350995691c9cSTomer Tayar } 351095691c9cSTomer Tayar 351195691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 351295691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 351395691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 351495691c9cSTomer Tayar 351595691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 351695691c9cSTomer Tayar QED_MSG_SP, 351795691c9cSTomer Tayar "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 351895691c9cSTomer Tayar param, p_params->timeout, opcode, p_params->resource); 351995691c9cSTomer Tayar 352095691c9cSTomer Tayar /* Attempt to acquire the resource */ 352195691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 352295691c9cSTomer Tayar if (rc) 352395691c9cSTomer Tayar return rc; 352495691c9cSTomer Tayar 352595691c9cSTomer Tayar /* Analyze the response */ 352695691c9cSTomer Tayar p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 352795691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 352895691c9cSTomer Tayar 352995691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 353095691c9cSTomer Tayar QED_MSG_SP, 353195691c9cSTomer Tayar "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 353295691c9cSTomer Tayar mcp_param, opcode, p_params->owner); 353395691c9cSTomer Tayar 353495691c9cSTomer Tayar switch (opcode) { 353595691c9cSTomer Tayar case RESOURCE_OPCODE_GNT: 353695691c9cSTomer Tayar p_params->b_granted = true; 353795691c9cSTomer Tayar break; 353895691c9cSTomer Tayar case RESOURCE_OPCODE_BUSY: 353995691c9cSTomer Tayar p_params->b_granted = false; 354095691c9cSTomer Tayar break; 354195691c9cSTomer Tayar default: 354295691c9cSTomer Tayar DP_NOTICE(p_hwfn, 354395691c9cSTomer Tayar "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 354495691c9cSTomer Tayar mcp_param, opcode); 354595691c9cSTomer Tayar return -EINVAL; 354695691c9cSTomer Tayar } 354795691c9cSTomer Tayar 354895691c9cSTomer Tayar return 0; 354995691c9cSTomer Tayar } 355095691c9cSTomer Tayar 355195691c9cSTomer Tayar int 355295691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 355395691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 355495691c9cSTomer Tayar { 355595691c9cSTomer Tayar u32 retry_cnt = 0; 355695691c9cSTomer Tayar int rc; 355795691c9cSTomer Tayar 355895691c9cSTomer Tayar do { 355995691c9cSTomer Tayar /* No need for an interval before the first iteration */ 356095691c9cSTomer Tayar if (retry_cnt) { 356195691c9cSTomer Tayar if (p_params->sleep_b4_retry) { 356295691c9cSTomer Tayar u16 retry_interval_in_ms = 356395691c9cSTomer Tayar DIV_ROUND_UP(p_params->retry_interval, 356495691c9cSTomer Tayar 1000); 356595691c9cSTomer Tayar 356695691c9cSTomer Tayar msleep(retry_interval_in_ms); 356795691c9cSTomer Tayar } else { 356895691c9cSTomer Tayar udelay(p_params->retry_interval); 356995691c9cSTomer Tayar } 357095691c9cSTomer Tayar } 357195691c9cSTomer Tayar 357295691c9cSTomer Tayar rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 357395691c9cSTomer Tayar if (rc) 357495691c9cSTomer Tayar return rc; 357595691c9cSTomer Tayar 357695691c9cSTomer Tayar if (p_params->b_granted) 357795691c9cSTomer Tayar break; 357895691c9cSTomer Tayar } while (retry_cnt++ < p_params->retry_num); 357995691c9cSTomer Tayar 358095691c9cSTomer Tayar return 0; 358195691c9cSTomer Tayar } 358295691c9cSTomer Tayar 358395691c9cSTomer Tayar int 358495691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 358595691c9cSTomer Tayar struct qed_ptt *p_ptt, 358695691c9cSTomer Tayar struct qed_resc_unlock_params *p_params) 358795691c9cSTomer Tayar { 358895691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 358995691c9cSTomer Tayar u8 opcode; 359095691c9cSTomer Tayar int rc; 359195691c9cSTomer Tayar 359295691c9cSTomer Tayar opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 359395691c9cSTomer Tayar : RESOURCE_OPCODE_RELEASE; 359495691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 359595691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 359695691c9cSTomer Tayar 359795691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 359895691c9cSTomer Tayar "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 359995691c9cSTomer Tayar param, opcode, p_params->resource); 360095691c9cSTomer Tayar 360195691c9cSTomer Tayar /* Attempt to release the resource */ 360295691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 360395691c9cSTomer Tayar if (rc) 360495691c9cSTomer Tayar return rc; 360595691c9cSTomer Tayar 360695691c9cSTomer Tayar /* Analyze the response */ 360795691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 360895691c9cSTomer Tayar 360995691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 361095691c9cSTomer Tayar "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 361195691c9cSTomer Tayar mcp_param, opcode); 361295691c9cSTomer Tayar 361395691c9cSTomer Tayar switch (opcode) { 361495691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED_PREVIOUS: 361595691c9cSTomer Tayar DP_INFO(p_hwfn, 361695691c9cSTomer Tayar "Resource unlock request for an already released resource [%d]\n", 361795691c9cSTomer Tayar p_params->resource); 361895691c9cSTomer Tayar /* Fallthrough */ 361995691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED: 362095691c9cSTomer Tayar p_params->b_released = true; 362195691c9cSTomer Tayar break; 362295691c9cSTomer Tayar case RESOURCE_OPCODE_WRONG_OWNER: 362395691c9cSTomer Tayar p_params->b_released = false; 362495691c9cSTomer Tayar break; 362595691c9cSTomer Tayar default: 362695691c9cSTomer Tayar DP_NOTICE(p_hwfn, 362795691c9cSTomer Tayar "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 362895691c9cSTomer Tayar mcp_param, opcode); 362995691c9cSTomer Tayar return -EINVAL; 363095691c9cSTomer Tayar } 363195691c9cSTomer Tayar 363295691c9cSTomer Tayar return 0; 363395691c9cSTomer Tayar } 3634f470f22cSsudarsana.kalluru@cavium.com 3635f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3636f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 3637f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 3638f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent) 3639f470f22cSsudarsana.kalluru@cavium.com { 3640f470f22cSsudarsana.kalluru@cavium.com if (p_lock) { 3641f470f22cSsudarsana.kalluru@cavium.com memset(p_lock, 0, sizeof(*p_lock)); 3642f470f22cSsudarsana.kalluru@cavium.com 3643f470f22cSsudarsana.kalluru@cavium.com /* Permanent resources don't require aging, and there's no 3644f470f22cSsudarsana.kalluru@cavium.com * point in trying to acquire them more than once since it's 3645f470f22cSsudarsana.kalluru@cavium.com * unexpected another entity would release them. 3646f470f22cSsudarsana.kalluru@cavium.com */ 3647f470f22cSsudarsana.kalluru@cavium.com if (b_is_permanent) { 3648f470f22cSsudarsana.kalluru@cavium.com p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3649f470f22cSsudarsana.kalluru@cavium.com } else { 3650f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3651f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_interval = 3652f470f22cSsudarsana.kalluru@cavium.com QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3653f470f22cSsudarsana.kalluru@cavium.com p_lock->sleep_b4_retry = true; 3654f470f22cSsudarsana.kalluru@cavium.com } 3655f470f22cSsudarsana.kalluru@cavium.com 3656f470f22cSsudarsana.kalluru@cavium.com p_lock->resource = resource; 3657f470f22cSsudarsana.kalluru@cavium.com } 3658f470f22cSsudarsana.kalluru@cavium.com 3659f470f22cSsudarsana.kalluru@cavium.com if (p_unlock) { 3660f470f22cSsudarsana.kalluru@cavium.com memset(p_unlock, 0, sizeof(*p_unlock)); 3661f470f22cSsudarsana.kalluru@cavium.com p_unlock->resource = resource; 3662f470f22cSsudarsana.kalluru@cavium.com } 3663f470f22cSsudarsana.kalluru@cavium.com } 3664645874e5SSudarsana Reddy Kalluru 3665df9c716dSSudarsana Reddy Kalluru bool qed_mcp_is_smart_an_supported(struct qed_hwfn *p_hwfn) 3666df9c716dSSudarsana Reddy Kalluru { 3667df9c716dSSudarsana Reddy Kalluru return !!(p_hwfn->mcp_info->capabilities & 3668df9c716dSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ); 3669df9c716dSSudarsana Reddy Kalluru } 3670df9c716dSSudarsana Reddy Kalluru 3671645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3672645874e5SSudarsana Reddy Kalluru { 3673645874e5SSudarsana Reddy Kalluru u32 mcp_resp; 3674645874e5SSudarsana Reddy Kalluru int rc; 3675645874e5SSudarsana Reddy Kalluru 3676645874e5SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3677645874e5SSudarsana Reddy Kalluru 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3678645874e5SSudarsana Reddy Kalluru if (!rc) 3679645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3680645874e5SSudarsana Reddy Kalluru "MFW supported features: %08x\n", 3681645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->capabilities); 3682645874e5SSudarsana Reddy Kalluru 3683645874e5SSudarsana Reddy Kalluru return rc; 3684645874e5SSudarsana Reddy Kalluru } 3685645874e5SSudarsana Reddy Kalluru 3686645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3687645874e5SSudarsana Reddy Kalluru { 3688645874e5SSudarsana Reddy Kalluru u32 mcp_resp, mcp_param, features; 3689645874e5SSudarsana Reddy Kalluru 3690e40a826aSSudarsana Reddy Kalluru features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE | 3691e40a826aSSudarsana Reddy Kalluru DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK; 3692645874e5SSudarsana Reddy Kalluru 3693645874e5SSudarsana Reddy Kalluru return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3694645874e5SSudarsana Reddy Kalluru features, &mcp_resp, &mcp_param); 3695645874e5SSudarsana Reddy Kalluru } 369679284adeSMichal Kalderon 369779284adeSMichal Kalderon int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 369879284adeSMichal Kalderon { 369979284adeSMichal Kalderon struct qed_mcp_mb_params mb_params = {0}; 370079284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 370179284adeSMichal Kalderon u8 fir_valid, l2_valid; 370279284adeSMichal Kalderon int rc; 370379284adeSMichal Kalderon 370479284adeSMichal Kalderon mb_params.cmd = DRV_MSG_CODE_GET_ENGINE_CONFIG; 370579284adeSMichal Kalderon rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 370679284adeSMichal Kalderon if (rc) 370779284adeSMichal Kalderon return rc; 370879284adeSMichal Kalderon 370979284adeSMichal Kalderon if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 371079284adeSMichal Kalderon DP_INFO(p_hwfn, 371179284adeSMichal Kalderon "The get_engine_config command is unsupported by the MFW\n"); 371279284adeSMichal Kalderon return -EOPNOTSUPP; 371379284adeSMichal Kalderon } 371479284adeSMichal Kalderon 371579284adeSMichal Kalderon fir_valid = QED_MFW_GET_FIELD(mb_params.mcp_param, 371679284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID); 371779284adeSMichal Kalderon if (fir_valid) 371879284adeSMichal Kalderon cdev->fir_affin = 371979284adeSMichal Kalderon QED_MFW_GET_FIELD(mb_params.mcp_param, 372079284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE); 372179284adeSMichal Kalderon 372279284adeSMichal Kalderon l2_valid = QED_MFW_GET_FIELD(mb_params.mcp_param, 372379284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID); 372479284adeSMichal Kalderon if (l2_valid) 372579284adeSMichal Kalderon cdev->l2_affin_hint = 372679284adeSMichal Kalderon QED_MFW_GET_FIELD(mb_params.mcp_param, 372779284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE); 372879284adeSMichal Kalderon 372979284adeSMichal Kalderon DP_INFO(p_hwfn, 373079284adeSMichal Kalderon "Engine affinity config: FIR={valid %hhd, value %hhd}, L2_hint={valid %hhd, value %hhd}\n", 373179284adeSMichal Kalderon fir_valid, cdev->fir_affin, l2_valid, cdev->l2_affin_hint); 373279284adeSMichal Kalderon 373379284adeSMichal Kalderon return 0; 373479284adeSMichal Kalderon } 373579284adeSMichal Kalderon 373679284adeSMichal Kalderon int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 373779284adeSMichal Kalderon { 373879284adeSMichal Kalderon struct qed_mcp_mb_params mb_params = {0}; 373979284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 374079284adeSMichal Kalderon int rc; 374179284adeSMichal Kalderon 374279284adeSMichal Kalderon mb_params.cmd = DRV_MSG_CODE_GET_PPFID_BITMAP; 374379284adeSMichal Kalderon rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 374479284adeSMichal Kalderon if (rc) 374579284adeSMichal Kalderon return rc; 374679284adeSMichal Kalderon 374779284adeSMichal Kalderon if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 374879284adeSMichal Kalderon DP_INFO(p_hwfn, 374979284adeSMichal Kalderon "The get_ppfid_bitmap command is unsupported by the MFW\n"); 375079284adeSMichal Kalderon return -EOPNOTSUPP; 375179284adeSMichal Kalderon } 375279284adeSMichal Kalderon 375379284adeSMichal Kalderon cdev->ppfid_bitmap = QED_MFW_GET_FIELD(mb_params.mcp_param, 375479284adeSMichal Kalderon FW_MB_PARAM_PPFID_BITMAP); 375579284adeSMichal Kalderon 375679284adeSMichal Kalderon DP_VERBOSE(p_hwfn, QED_MSG_SP, "PPFID bitmap 0x%hhx\n", 375779284adeSMichal Kalderon cdev->ppfid_bitmap); 375879284adeSMichal Kalderon 375979284adeSMichal Kalderon return 0; 376079284adeSMichal Kalderon } 376138eabdf0SSudarsana Reddy Kalluru 37622d4c8495SSudarsana Reddy Kalluru int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 37632d4c8495SSudarsana Reddy Kalluru u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 37642d4c8495SSudarsana Reddy Kalluru u32 *p_len) 37652d4c8495SSudarsana Reddy Kalluru { 37662d4c8495SSudarsana Reddy Kalluru u32 mb_param = 0, resp, param; 37672d4c8495SSudarsana Reddy Kalluru int rc; 37682d4c8495SSudarsana Reddy Kalluru 37692d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id); 37702d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_INIT) 37712d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 37722d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1); 37732d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_FREE) 37742d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 37752d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1); 37762d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) { 37772d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 37782d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1); 37792d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 37802d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID, 37812d4c8495SSudarsana Reddy Kalluru entity_id); 37822d4c8495SSudarsana Reddy Kalluru } 37832d4c8495SSudarsana Reddy Kalluru 37842d4c8495SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 37852d4c8495SSudarsana Reddy Kalluru DRV_MSG_CODE_GET_NVM_CFG_OPTION, 37862d4c8495SSudarsana Reddy Kalluru mb_param, &resp, ¶m, p_len, (u32 *)p_buf); 37872d4c8495SSudarsana Reddy Kalluru 37882d4c8495SSudarsana Reddy Kalluru return rc; 37892d4c8495SSudarsana Reddy Kalluru } 37902d4c8495SSudarsana Reddy Kalluru 379138eabdf0SSudarsana Reddy Kalluru int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 379238eabdf0SSudarsana Reddy Kalluru u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 379338eabdf0SSudarsana Reddy Kalluru u32 len) 379438eabdf0SSudarsana Reddy Kalluru { 379538eabdf0SSudarsana Reddy Kalluru u32 mb_param = 0, resp, param; 379638eabdf0SSudarsana Reddy Kalluru 379738eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id); 379838eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ALL) 379938eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 380038eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ALL, 1); 380138eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_INIT) 380238eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 380338eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1); 380438eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_COMMIT) 380538eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 380638eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT, 1); 380738eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_FREE) 380838eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 380938eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1); 381038eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) { 381138eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 381238eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1); 381338eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 381438eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID, 381538eabdf0SSudarsana Reddy Kalluru entity_id); 381638eabdf0SSudarsana Reddy Kalluru } 381738eabdf0SSudarsana Reddy Kalluru 381838eabdf0SSudarsana Reddy Kalluru return qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, 381938eabdf0SSudarsana Reddy Kalluru DRV_MSG_CODE_SET_NVM_CFG_OPTION, 382038eabdf0SSudarsana Reddy Kalluru mb_param, &resp, ¶m, len, (u32 *)p_buf); 382138eabdf0SSudarsana Reddy Kalluru } 3822